Merge branch 'next' of https://github.com/aquynh/capstone into next
diff --git a/arch/M68K/M68KDisassembler.c b/arch/M68K/M68KDisassembler.c
index c378587..9511444 100644
--- a/arch/M68K/M68KDisassembler.c
+++ b/arch/M68K/M68KDisassembler.c
@@ -188,7 +188,7 @@
static unsigned int m68k_read_safe_16(const m68k_info *info, const uint64_t address)
{
const uint64_t addr = (address - info->baseAddress) & info->address_mask;
- if (info->code_len < 2) {
+ if (info->code_len < addr + 2) {
return 0xaaaa;
}
return m68k_read_disassembler_16(info, addr);
@@ -197,7 +197,7 @@
static unsigned int m68k_read_safe_32(const m68k_info *info, const uint64_t address)
{
const uint64_t addr = (address - info->baseAddress) & info->address_mask;
- if (info->code_len < 4) {
+ if (info->code_len < addr + 4) {
return 0xaaaaaaaa;
}
return m68k_read_disassembler_32(info, addr);
@@ -206,7 +206,7 @@
static uint64_t m68k_read_safe_64(const m68k_info *info, const uint64_t address)
{
const uint64_t addr = (address - info->baseAddress) & info->address_mask;
- if (info->code_len < 8) {
+ if (info->code_len < addr + 8) {
return 0xaaaaaaaaaaaaaaaaLL;
}
return m68k_read_disassembler_64(info, addr);
@@ -3862,14 +3862,16 @@
if (exists_reg_list(info->regs_write, info->regs_write_count, reg))
return;
- info->regs_write[info->regs_write_count++] = (uint16_t)reg;
+ info->regs_write[info->regs_write_count] = (uint16_t)reg;
+ info->regs_write_count++;
}
else
{
if (exists_reg_list(info->regs_read, info->regs_read_count, reg))
return;
- info->regs_read[info->regs_read_count++] = (uint16_t)reg;
+ info->regs_read[info->regs_read_count] = (uint16_t)reg;
+ info->regs_read_count++;
}
}
diff --git a/arch/Mips/MipsDisassembler.c b/arch/Mips/MipsDisassembler.c
index dfc07ee..561f522 100644
--- a/arch/Mips/MipsDisassembler.c
+++ b/arch/Mips/MipsDisassembler.c
@@ -1196,7 +1196,7 @@
return MCDisassembler_Fail;
MCOperand_CreateReg0(Inst, Mips_SP);
- MCOperand_CreateImm0(Inst, Offset << 2);
+ MCOperand_CreateImm0(Inst, Offset * 4);
return MCDisassembler_Success;
}
@@ -1533,7 +1533,7 @@
static DecodeStatus DecodeBranchTarget7MM(MCInst *Inst,
unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder)
{
- int32_t BranchOffset = SignExtend32(Offset, 7) << 1;
+ int32_t BranchOffset = SignExtend32(Offset, 7) * 2;
MCOperand_CreateImm0(Inst, BranchOffset);
return MCDisassembler_Success;
}
@@ -1541,7 +1541,7 @@
static DecodeStatus DecodeBranchTarget10MM(MCInst *Inst,
unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder)
{
- int32_t BranchOffset = SignExtend32(Offset, 10) << 1;
+ int32_t BranchOffset = SignExtend32(Offset, 10) * 2;
MCOperand_CreateImm0(Inst, BranchOffset);
return MCDisassembler_Success;
}
diff --git a/arch/X86/X86Disassembler.c b/arch/X86/X86Disassembler.c
index 95ed978..12c3c57 100644
--- a/arch/X86/X86Disassembler.c
+++ b/arch/X86/X86Disassembler.c
@@ -920,17 +920,25 @@
info.offset = address;
if (instr->flat_insn->detail) {
- instr->flat_insn->detail->x86.op_count = 0;
- instr->flat_insn->detail->x86.sse_cc = X86_SSE_CC_INVALID;
- instr->flat_insn->detail->x86.avx_cc = X86_AVX_CC_INVALID;
- instr->flat_insn->detail->x86.avx_sae = false;
- instr->flat_insn->detail->x86.avx_rm = X86_AVX_RM_INVALID;
- instr->flat_insn->detail->x86.xop_cc = X86_XOP_CC_INVALID;
- instr->flat_insn->detail->x86.eflags = 0;
+ // instr->flat_insn->detail initialization: 3 alternatives
- memset(instr->flat_insn->detail->x86.prefix, 0, sizeof(instr->flat_insn->detail->x86.prefix));
- memset(instr->flat_insn->detail->x86.opcode, 0, sizeof(instr->flat_insn->detail->x86.opcode));
- memset(instr->flat_insn->detail->x86.operands, 0, sizeof(instr->flat_insn->detail->x86.operands));
+
+ // 1. The whole structure, this is how it's done in other arch disassemblers
+ // Probably overkill since cs_detail is huge because of the 36 operands of ARM
+
+ //memset(instr->flat_insn->detail, 0, sizeof(cs_detail));
+
+
+ // 2. Only the part relevant to x86
+
+ memset(instr->flat_insn->detail, 0, offsetof(cs_detail, x86)+sizeof(cs_x86));
+
+
+ // 3. The relevant part except for x86.operands
+ // sizeof(cs_x86) is 0x1c0, sizeof(x86.operands) is 0x180
+ // marginally faster, should be okay since x86.op_count is set to 0
+
+ //memset(instr->flat_insn->detail, 0, offsetof(cs_detail, x86)+offsetof(cs_x86, operands));
}
if (handle->mode & CS_MODE_16)
