| // This is auto-gen data for Capstone engine (www.capstone-engine.org) |
| // By Nguyen Anh Quynh <aquynh@gmail.com> |
| |
| { |
| AArch64_ABSv16i8, ARM64_INS_ABS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ABSv1i64, ARM64_INS_ABS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ABSv2i32, ARM64_INS_ABS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ABSv2i64, ARM64_INS_ABS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ABSv4i16, ARM64_INS_ABS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ABSv4i32, ARM64_INS_ABS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ABSv8i16, ARM64_INS_ABS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ABSv8i8, ARM64_INS_ABS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADCSWr, ARM64_INS_ADC, |
| #ifndef CAPSTONE_DIET |
| { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADCSXr, ARM64_INS_ADC, |
| #ifndef CAPSTONE_DIET |
| { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADCWr, ARM64_INS_ADC, |
| #ifndef CAPSTONE_DIET |
| { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADCXr, ARM64_INS_ADC, |
| #ifndef CAPSTONE_DIET |
| { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADDHNv2i64_v2i32, ARM64_INS_ADDHN, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADDHNv2i64_v4i32, ARM64_INS_ADDHN2, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADDHNv4i32_v4i16, ARM64_INS_ADDHN, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADDHNv4i32_v8i16, ARM64_INS_ADDHN2, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADDHNv8i16_v16i8, ARM64_INS_ADDHN2, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADDHNv8i16_v8i8, ARM64_INS_ADDHN, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADDPv16i8, ARM64_INS_ADDP, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADDPv2i32, ARM64_INS_ADDP, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADDPv2i64, ARM64_INS_ADDP, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADDPv2i64p, ARM64_INS_ADDP, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADDPv4i16, ARM64_INS_ADDP, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADDPv4i32, ARM64_INS_ADDP, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADDPv8i16, ARM64_INS_ADDP, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADDPv8i8, ARM64_INS_ADDP, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADDSWri, ARM64_INS_ADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADDSWrs, ARM64_INS_ADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADDSWrx, ARM64_INS_ADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADDSXri, ARM64_INS_ADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADDSXrs, ARM64_INS_ADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADDSXrx, ARM64_INS_ADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADDSXrx64, ARM64_INS_ADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADDVv16i8v, ARM64_INS_ADDV, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADDVv4i16v, ARM64_INS_ADDV, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADDVv4i32v, ARM64_INS_ADDV, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADDVv8i16v, ARM64_INS_ADDV, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADDVv8i8v, ARM64_INS_ADDV, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADDWri, ARM64_INS_ADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADDWrs, ARM64_INS_ADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADDWrx, ARM64_INS_ADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADDXri, ARM64_INS_ADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADDXrs, ARM64_INS_ADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADDXrx, ARM64_INS_ADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADDXrx64, ARM64_INS_ADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADDv16i8, ARM64_INS_ADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADDv1i64, ARM64_INS_ADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADDv2i32, ARM64_INS_ADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADDv2i64, ARM64_INS_ADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADDv4i16, ARM64_INS_ADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADDv4i32, ARM64_INS_ADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADDv8i16, ARM64_INS_ADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADDv8i8, ARM64_INS_ADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADR, ARM64_INS_ADR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ADRP, ARM64_INS_ADRP, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_AESDrr, ARM64_INS_AESD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_AESErr, ARM64_INS_AESE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_AESIMCrr, ARM64_INS_AESIMC, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_AESMCrr, ARM64_INS_AESMC, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ANDSWri, ARM64_INS_AND, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ANDSWrs, ARM64_INS_AND, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ANDSXri, ARM64_INS_AND, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ANDSXrs, ARM64_INS_AND, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ANDWri, ARM64_INS_AND, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ANDWrs, ARM64_INS_AND, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ANDXri, ARM64_INS_AND, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ANDXrs, ARM64_INS_AND, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ANDv16i8, ARM64_INS_AND, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ANDv8i8, ARM64_INS_AND, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ASRVWr, ARM64_INS_ASR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ASRVXr, ARM64_INS_ASR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_B, ARM64_INS_B, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_JUMP, 0 }, 1, 0 |
| #endif |
| }, |
| { |
| AArch64_BFMWri, ARM64_INS_BFM, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_BFMXri, ARM64_INS_BFM, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_BICSWrs, ARM64_INS_BIC, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_BICSXrs, ARM64_INS_BIC, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_BICWrs, ARM64_INS_BIC, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_BICXrs, ARM64_INS_BIC, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_BICv16i8, ARM64_INS_BIC, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_BICv2i32, ARM64_INS_BIC, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_BICv4i16, ARM64_INS_BIC, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_BICv4i32, ARM64_INS_BIC, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_BICv8i16, ARM64_INS_BIC, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_BICv8i8, ARM64_INS_BIC, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_BIFv16i8, ARM64_INS_BIF, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_BIFv8i8, ARM64_INS_BIF, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_BITv16i8, ARM64_INS_BIT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_BITv8i8, ARM64_INS_BIT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_BL, ARM64_INS_BL, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_CALL, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_BLR, ARM64_INS_BLR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_CALL, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_BR, ARM64_INS_BR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_JUMP, 0 }, 1, 1 |
| #endif |
| }, |
| { |
| AArch64_BRK, ARM64_INS_BRK, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_BSLv16i8, ARM64_INS_BSL, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_BSLv8i8, ARM64_INS_BSL, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_Bcc, ARM64_INS_B, |
| #ifndef CAPSTONE_DIET |
| { ARM64_REG_NZCV, 0 }, { 0 }, { ARM64_GRP_JUMP, 0 }, 1, 0 |
| #endif |
| }, |
| { |
| AArch64_CBNZW, ARM64_INS_CBNZ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_JUMP, 0 }, 1, 0 |
| #endif |
| }, |
| { |
| AArch64_CBNZX, ARM64_INS_CBNZ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_JUMP, 0 }, 1, 0 |
| #endif |
| }, |
| { |
| AArch64_CBZW, ARM64_INS_CBZ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_JUMP, 0 }, 1, 0 |
| #endif |
| }, |
| { |
| AArch64_CBZX, ARM64_INS_CBZ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_JUMP, 0 }, 1, 0 |
| #endif |
| }, |
| { |
| AArch64_CCMNWi, ARM64_INS_CCMN, |
| #ifndef CAPSTONE_DIET |
| { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CCMNWr, ARM64_INS_CCMN, |
| #ifndef CAPSTONE_DIET |
| { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CCMNXi, ARM64_INS_CCMN, |
| #ifndef CAPSTONE_DIET |
| { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CCMNXr, ARM64_INS_CCMN, |
| #ifndef CAPSTONE_DIET |
| { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CCMPWi, ARM64_INS_CCMP, |
| #ifndef CAPSTONE_DIET |
| { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CCMPWr, ARM64_INS_CCMP, |
| #ifndef CAPSTONE_DIET |
| { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CCMPXi, ARM64_INS_CCMP, |
| #ifndef CAPSTONE_DIET |
| { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CCMPXr, ARM64_INS_CCMP, |
| #ifndef CAPSTONE_DIET |
| { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CLREX, ARM64_INS_CLREX, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CLSWr, ARM64_INS_CLS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CLSXr, ARM64_INS_CLS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CLSv16i8, ARM64_INS_CLS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CLSv2i32, ARM64_INS_CLS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CLSv4i16, ARM64_INS_CLS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CLSv4i32, ARM64_INS_CLS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CLSv8i16, ARM64_INS_CLS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CLSv8i8, ARM64_INS_CLS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CLZWr, ARM64_INS_CLZ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CLZXr, ARM64_INS_CLZ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CLZv16i8, ARM64_INS_CLZ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CLZv2i32, ARM64_INS_CLZ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CLZv4i16, ARM64_INS_CLZ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CLZv4i32, ARM64_INS_CLZ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CLZv8i16, ARM64_INS_CLZ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CLZv8i8, ARM64_INS_CLZ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMEQv16i8, ARM64_INS_CMEQ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMEQv16i8rz, ARM64_INS_CMEQ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMEQv1i64, ARM64_INS_CMEQ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMEQv1i64rz, ARM64_INS_CMEQ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMEQv2i32, ARM64_INS_CMEQ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMEQv2i32rz, ARM64_INS_CMEQ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMEQv2i64, ARM64_INS_CMEQ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMEQv2i64rz, ARM64_INS_CMEQ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMEQv4i16, ARM64_INS_CMEQ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMEQv4i16rz, ARM64_INS_CMEQ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMEQv4i32, ARM64_INS_CMEQ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMEQv4i32rz, ARM64_INS_CMEQ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMEQv8i16, ARM64_INS_CMEQ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMEQv8i16rz, ARM64_INS_CMEQ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMEQv8i8, ARM64_INS_CMEQ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMEQv8i8rz, ARM64_INS_CMEQ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMGEv16i8, ARM64_INS_CMGE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMGEv16i8rz, ARM64_INS_CMGE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMGEv1i64, ARM64_INS_CMGE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMGEv1i64rz, ARM64_INS_CMGE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMGEv2i32, ARM64_INS_CMGE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMGEv2i32rz, ARM64_INS_CMGE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMGEv2i64, ARM64_INS_CMGE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMGEv2i64rz, ARM64_INS_CMGE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMGEv4i16, ARM64_INS_CMGE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMGEv4i16rz, ARM64_INS_CMGE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMGEv4i32, ARM64_INS_CMGE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMGEv4i32rz, ARM64_INS_CMGE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMGEv8i16, ARM64_INS_CMGE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMGEv8i16rz, ARM64_INS_CMGE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMGEv8i8, ARM64_INS_CMGE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMGEv8i8rz, ARM64_INS_CMGE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMGTv16i8, ARM64_INS_CMGT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMGTv16i8rz, ARM64_INS_CMGT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMGTv1i64, ARM64_INS_CMGT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMGTv1i64rz, ARM64_INS_CMGT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMGTv2i32, ARM64_INS_CMGT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMGTv2i32rz, ARM64_INS_CMGT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMGTv2i64, ARM64_INS_CMGT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMGTv2i64rz, ARM64_INS_CMGT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMGTv4i16, ARM64_INS_CMGT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMGTv4i16rz, ARM64_INS_CMGT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMGTv4i32, ARM64_INS_CMGT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMGTv4i32rz, ARM64_INS_CMGT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMGTv8i16, ARM64_INS_CMGT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMGTv8i16rz, ARM64_INS_CMGT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMGTv8i8, ARM64_INS_CMGT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMGTv8i8rz, ARM64_INS_CMGT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMHIv16i8, ARM64_INS_CMHI, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMHIv1i64, ARM64_INS_CMHI, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMHIv2i32, ARM64_INS_CMHI, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMHIv2i64, ARM64_INS_CMHI, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMHIv4i16, ARM64_INS_CMHI, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMHIv4i32, ARM64_INS_CMHI, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMHIv8i16, ARM64_INS_CMHI, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMHIv8i8, ARM64_INS_CMHI, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMHSv16i8, ARM64_INS_CMHS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMHSv1i64, ARM64_INS_CMHS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMHSv2i32, ARM64_INS_CMHS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMHSv2i64, ARM64_INS_CMHS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMHSv4i16, ARM64_INS_CMHS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMHSv4i32, ARM64_INS_CMHS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMHSv8i16, ARM64_INS_CMHS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMHSv8i8, ARM64_INS_CMHS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMLEv16i8rz, ARM64_INS_CMLE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMLEv1i64rz, ARM64_INS_CMLE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMLEv2i32rz, ARM64_INS_CMLE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMLEv2i64rz, ARM64_INS_CMLE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMLEv4i16rz, ARM64_INS_CMLE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMLEv4i32rz, ARM64_INS_CMLE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMLEv8i16rz, ARM64_INS_CMLE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMLEv8i8rz, ARM64_INS_CMLE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMLTv16i8rz, ARM64_INS_CMLT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMLTv1i64rz, ARM64_INS_CMLT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMLTv2i32rz, ARM64_INS_CMLT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMLTv2i64rz, ARM64_INS_CMLT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMLTv4i16rz, ARM64_INS_CMLT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMLTv4i32rz, ARM64_INS_CMLT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMLTv8i16rz, ARM64_INS_CMLT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMLTv8i8rz, ARM64_INS_CMLT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMTSTv16i8, ARM64_INS_CMTST, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMTSTv1i64, ARM64_INS_CMTST, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMTSTv2i32, ARM64_INS_CMTST, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMTSTv2i64, ARM64_INS_CMTST, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMTSTv4i16, ARM64_INS_CMTST, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMTSTv4i32, ARM64_INS_CMTST, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMTSTv8i16, ARM64_INS_CMTST, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CMTSTv8i8, ARM64_INS_CMTST, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CNTv16i8, ARM64_INS_CNT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CNTv8i8, ARM64_INS_CNT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CPYi16, ARM64_INS_MOV, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CPYi32, ARM64_INS_MOV, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CPYi64, ARM64_INS_MOV, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CPYi8, ARM64_INS_MOV, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CRC32Brr, ARM64_INS_CRC32B, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CRC32CBrr, ARM64_INS_CRC32CB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CRC32CHrr, ARM64_INS_CRC32CH, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CRC32CWrr, ARM64_INS_CRC32CW, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CRC32CXrr, ARM64_INS_CRC32CX, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CRC32Hrr, ARM64_INS_CRC32H, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CRC32Wrr, ARM64_INS_CRC32W, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CRC32Xrr, ARM64_INS_CRC32X, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CSELWr, ARM64_INS_CSEL, |
| #ifndef CAPSTONE_DIET |
| { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CSELXr, ARM64_INS_CSEL, |
| #ifndef CAPSTONE_DIET |
| { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CSINCWr, ARM64_INS_CSINC, |
| #ifndef CAPSTONE_DIET |
| { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CSINCXr, ARM64_INS_CSINC, |
| #ifndef CAPSTONE_DIET |
| { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CSINVWr, ARM64_INS_CSINV, |
| #ifndef CAPSTONE_DIET |
| { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CSINVXr, ARM64_INS_CSINV, |
| #ifndef CAPSTONE_DIET |
| { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CSNEGWr, ARM64_INS_CSNEG, |
| #ifndef CAPSTONE_DIET |
| { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_CSNEGXr, ARM64_INS_CSNEG, |
| #ifndef CAPSTONE_DIET |
| { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_DCPS1, ARM64_INS_DCPS1, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_DCPS2, ARM64_INS_DCPS2, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_DCPS3, ARM64_INS_DCPS3, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_DMB, ARM64_INS_DMB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_DRPS, ARM64_INS_DRPS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_DSB, ARM64_INS_DSB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_DUPv16i8gpr, ARM64_INS_DUP, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_DUPv16i8lane, ARM64_INS_DUP, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_DUPv2i32gpr, ARM64_INS_DUP, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_DUPv2i32lane, ARM64_INS_DUP, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_DUPv2i64gpr, ARM64_INS_DUP, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_DUPv2i64lane, ARM64_INS_DUP, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_DUPv4i16gpr, ARM64_INS_DUP, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_DUPv4i16lane, ARM64_INS_DUP, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_DUPv4i32gpr, ARM64_INS_DUP, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_DUPv4i32lane, ARM64_INS_DUP, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_DUPv8i16gpr, ARM64_INS_DUP, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_DUPv8i16lane, ARM64_INS_DUP, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_DUPv8i8gpr, ARM64_INS_DUP, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_DUPv8i8lane, ARM64_INS_DUP, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_EONWrs, ARM64_INS_EON, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_EONXrs, ARM64_INS_EON, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_EORWri, ARM64_INS_EOR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_EORWrs, ARM64_INS_EOR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_EORXri, ARM64_INS_EOR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_EORXrs, ARM64_INS_EOR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_EORv16i8, ARM64_INS_EOR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_EORv8i8, ARM64_INS_EOR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_ERET, ARM64_INS_ERET, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_EXTRWrri, ARM64_INS_EXTR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_EXTRXrri, ARM64_INS_EXTR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_EXTv16i8, ARM64_INS_EXT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_EXTv8i8, ARM64_INS_EXT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FABD32, ARM64_INS_FABD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FABD64, ARM64_INS_FABD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FABDv2f32, ARM64_INS_FABD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FABDv2f64, ARM64_INS_FABD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FABDv4f32, ARM64_INS_FABD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FABSDr, ARM64_INS_FABS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FABSSr, ARM64_INS_FABS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FABSv2f32, ARM64_INS_FABS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FABSv2f64, ARM64_INS_FABS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FABSv4f32, ARM64_INS_FABS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FACGE32, ARM64_INS_FACGE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FACGE64, ARM64_INS_FACGE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FACGEv2f32, ARM64_INS_FACGE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FACGEv2f64, ARM64_INS_FACGE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FACGEv4f32, ARM64_INS_FACGE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FACGT32, ARM64_INS_FACGT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FACGT64, ARM64_INS_FACGT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FACGTv2f32, ARM64_INS_FACGT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FACGTv2f64, ARM64_INS_FACGT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FACGTv4f32, ARM64_INS_FACGT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FADDDrr, ARM64_INS_FADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FADDPv2f32, ARM64_INS_FADDP, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FADDPv2f64, ARM64_INS_FADDP, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FADDPv2i32p, ARM64_INS_FADDP, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FADDPv2i64p, ARM64_INS_FADDP, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FADDPv4f32, ARM64_INS_FADDP, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FADDSrr, ARM64_INS_FADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FADDv2f32, ARM64_INS_FADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FADDv2f64, ARM64_INS_FADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FADDv4f32, ARM64_INS_FADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCCMPDrr, ARM64_INS_FCCMP, |
| #ifndef CAPSTONE_DIET |
| { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCCMPEDrr, ARM64_INS_FCCMPE, |
| #ifndef CAPSTONE_DIET |
| { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCCMPESrr, ARM64_INS_FCCMPE, |
| #ifndef CAPSTONE_DIET |
| { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCCMPSrr, ARM64_INS_FCCMP, |
| #ifndef CAPSTONE_DIET |
| { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMEQ32, ARM64_INS_FCMEQ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMEQ64, ARM64_INS_FCMEQ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMEQv1i32rz, ARM64_INS_FCMEQ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMEQv1i64rz, ARM64_INS_FCMEQ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMEQv2f32, ARM64_INS_FCMEQ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMEQv2f64, ARM64_INS_FCMEQ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMEQv2i32rz, ARM64_INS_FCMEQ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMEQv2i64rz, ARM64_INS_FCMEQ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMEQv4f32, ARM64_INS_FCMEQ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMEQv4i32rz, ARM64_INS_FCMEQ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMGE32, ARM64_INS_FCMGE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMGE64, ARM64_INS_FCMGE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMGEv1i32rz, ARM64_INS_FCMGE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMGEv1i64rz, ARM64_INS_FCMGE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMGEv2f32, ARM64_INS_FCMGE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMGEv2f64, ARM64_INS_FCMGE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMGEv2i32rz, ARM64_INS_FCMGE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMGEv2i64rz, ARM64_INS_FCMGE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMGEv4f32, ARM64_INS_FCMGE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMGEv4i32rz, ARM64_INS_FCMGE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMGT32, ARM64_INS_FCMGT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMGT64, ARM64_INS_FCMGT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMGTv1i32rz, ARM64_INS_FCMGT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMGTv1i64rz, ARM64_INS_FCMGT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMGTv2f32, ARM64_INS_FCMGT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMGTv2f64, ARM64_INS_FCMGT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMGTv2i32rz, ARM64_INS_FCMGT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMGTv2i64rz, ARM64_INS_FCMGT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMGTv4f32, ARM64_INS_FCMGT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMGTv4i32rz, ARM64_INS_FCMGT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMLEv1i32rz, ARM64_INS_FCMLE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMLEv1i64rz, ARM64_INS_FCMLE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMLEv2i32rz, ARM64_INS_FCMLE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMLEv2i64rz, ARM64_INS_FCMLE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMLEv4i32rz, ARM64_INS_FCMLE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMLTv1i32rz, ARM64_INS_FCMLT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMLTv1i64rz, ARM64_INS_FCMLT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMLTv2i32rz, ARM64_INS_FCMLT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMLTv2i64rz, ARM64_INS_FCMLT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMLTv4i32rz, ARM64_INS_FCMLT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMPDri, ARM64_INS_FCMP, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMPDrr, ARM64_INS_FCMP, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMPEDri, ARM64_INS_FCMPE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMPEDrr, ARM64_INS_FCMPE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMPESri, ARM64_INS_FCMPE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMPESrr, ARM64_INS_FCMPE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMPSri, ARM64_INS_FCMP, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCMPSrr, ARM64_INS_FCMP, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCSELDrrr, ARM64_INS_FCSEL, |
| #ifndef CAPSTONE_DIET |
| { ARM64_REG_NZCV, 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCSELSrrr, ARM64_INS_FCSEL, |
| #ifndef CAPSTONE_DIET |
| { ARM64_REG_NZCV, 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTASUWDr, ARM64_INS_FCVTAS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTASUWSr, ARM64_INS_FCVTAS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTASUXDr, ARM64_INS_FCVTAS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTASUXSr, ARM64_INS_FCVTAS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTASv1i32, ARM64_INS_FCVTAS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTASv1i64, ARM64_INS_FCVTAS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTASv2f32, ARM64_INS_FCVTAS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTASv2f64, ARM64_INS_FCVTAS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTASv4f32, ARM64_INS_FCVTAS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTAUUWDr, ARM64_INS_FCVTAU, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTAUUWSr, ARM64_INS_FCVTAU, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTAUUXDr, ARM64_INS_FCVTAU, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTAUUXSr, ARM64_INS_FCVTAU, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTAUv1i32, ARM64_INS_FCVTAU, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTAUv1i64, ARM64_INS_FCVTAU, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTAUv2f32, ARM64_INS_FCVTAU, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTAUv2f64, ARM64_INS_FCVTAU, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTAUv4f32, ARM64_INS_FCVTAU, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTDHr, ARM64_INS_FCVT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTDSr, ARM64_INS_FCVT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTHDr, ARM64_INS_FCVT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTHSr, ARM64_INS_FCVT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTLv2i32, ARM64_INS_FCVTL, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTLv4i16, ARM64_INS_FCVTL, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTLv4i32, ARM64_INS_FCVTL2, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTLv8i16, ARM64_INS_FCVTL2, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTMSUWDr, ARM64_INS_FCVTMS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTMSUWSr, ARM64_INS_FCVTMS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTMSUXDr, ARM64_INS_FCVTMS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTMSUXSr, ARM64_INS_FCVTMS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTMSv1i32, ARM64_INS_FCVTMS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTMSv1i64, ARM64_INS_FCVTMS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTMSv2f32, ARM64_INS_FCVTMS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTMSv2f64, ARM64_INS_FCVTMS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTMSv4f32, ARM64_INS_FCVTMS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTMUUWDr, ARM64_INS_FCVTMU, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTMUUWSr, ARM64_INS_FCVTMU, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTMUUXDr, ARM64_INS_FCVTMU, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTMUUXSr, ARM64_INS_FCVTMU, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTMUv1i32, ARM64_INS_FCVTMU, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTMUv1i64, ARM64_INS_FCVTMU, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTMUv2f32, ARM64_INS_FCVTMU, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTMUv2f64, ARM64_INS_FCVTMU, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTMUv4f32, ARM64_INS_FCVTMU, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTNSUWDr, ARM64_INS_FCVTNS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTNSUWSr, ARM64_INS_FCVTNS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTNSUXDr, ARM64_INS_FCVTNS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTNSUXSr, ARM64_INS_FCVTNS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTNSv1i32, ARM64_INS_FCVTNS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTNSv1i64, ARM64_INS_FCVTNS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTNSv2f32, ARM64_INS_FCVTNS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTNSv2f64, ARM64_INS_FCVTNS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTNSv4f32, ARM64_INS_FCVTNS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTNUUWDr, ARM64_INS_FCVTNU, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTNUUWSr, ARM64_INS_FCVTNU, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTNUUXDr, ARM64_INS_FCVTNU, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTNUUXSr, ARM64_INS_FCVTNU, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTNUv1i32, ARM64_INS_FCVTNU, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTNUv1i64, ARM64_INS_FCVTNU, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTNUv2f32, ARM64_INS_FCVTNU, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTNUv2f64, ARM64_INS_FCVTNU, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTNUv4f32, ARM64_INS_FCVTNU, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTNv2i32, ARM64_INS_FCVTN, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTNv4i16, ARM64_INS_FCVTN, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTNv4i32, ARM64_INS_FCVTN2, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTNv8i16, ARM64_INS_FCVTN2, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTPSUWDr, ARM64_INS_FCVTPS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTPSUWSr, ARM64_INS_FCVTPS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTPSUXDr, ARM64_INS_FCVTPS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTPSUXSr, ARM64_INS_FCVTPS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTPSv1i32, ARM64_INS_FCVTPS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTPSv1i64, ARM64_INS_FCVTPS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTPSv2f32, ARM64_INS_FCVTPS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTPSv2f64, ARM64_INS_FCVTPS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTPSv4f32, ARM64_INS_FCVTPS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTPUUWDr, ARM64_INS_FCVTPU, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTPUUWSr, ARM64_INS_FCVTPU, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTPUUXDr, ARM64_INS_FCVTPU, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTPUUXSr, ARM64_INS_FCVTPU, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTPUv1i32, ARM64_INS_FCVTPU, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTPUv1i64, ARM64_INS_FCVTPU, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTPUv2f32, ARM64_INS_FCVTPU, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTPUv2f64, ARM64_INS_FCVTPU, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTPUv4f32, ARM64_INS_FCVTPU, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTSDr, ARM64_INS_FCVT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTSHr, ARM64_INS_FCVT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTXNv1i64, ARM64_INS_FCVTXN, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTXNv2f32, ARM64_INS_FCVTXN, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTXNv4f32, ARM64_INS_FCVTXN2, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTZSSWDri, ARM64_INS_FCVTZS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTZSSWSri, ARM64_INS_FCVTZS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTZSSXDri, ARM64_INS_FCVTZS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTZSSXSri, ARM64_INS_FCVTZS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTZSUWDr, ARM64_INS_FCVTZS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTZSUWSr, ARM64_INS_FCVTZS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| AArch64_FCVTZSUXDr, ARM64_INS_FCVTZS, |
| #ifndef CAPSTONE_DIET<
|
