commit 663f1f976c1b38cb8f27d90f91be62c720926031
author Catena cyber <35799796+catenacyber@users.noreply.github.com> Wed Jun 06 00:17:25 2018 +0200
committer Nguyen Anh Quynh <aquynh@gmail.com> Wed Jun 06 06:17:25 2018 +0800
tree e6d75a85b0aa36e748aa71e567cb51bcf80c7878
parent dcbec535eaaf753239d5e1fcee8133284db3e17b

Fix ARM operand subtracted field (#1163)

arch/ARM/ARMInstPrinter.c

diff --git a/arch/ARM/ARMInstPrinter.c b/arch/ARM/ARMInstPrinter.c
index 1baf1de..5815e3d 100644
--- a/arch/ARM/ARMInstPrinter.c
+++ b/arch/ARM/ARMInstPrinter.c
@@ -1045,7 +1045,7 @@
 		printRegName(MI->csh, O, MCOperand_getReg(MO2));
 		if (MI->csh->detail) {
 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2);
-			if (!sign) {
+			if (sign == ARM_AM_sub) {
 				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = -1;
 				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = true;
 			}
@@ -1066,7 +1066,7 @@
 	}
 
 	if (MI->csh->detail) {
-		if (!sign) {
+		if (sign == ARM_AM_sub) {
 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = -(int)ImmOffs;
 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = true;
 		} else
@@ -1115,13 +1115,8 @@
 		SStream_concat(O, "#%s%u", ARM_AM_getAddrOpcStr(subtracted), ImmOffs);
 	if (MI->csh->detail) {
 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
-
-		if (subtracted) {
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = ImmOffs;
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = true;
-		} else
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = -(int)ImmOffs;
-
+		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = ImmOffs;
+		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub;
 		MI->flat_insn->detail->arm.op_count++;
 	}
 }