| // This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) |
| // By Nguyen Anh Quynh <aquynh@gmail.com> |
| |
| { /* ARM_ADCri, ARM_INS_ADC: adc${s}${p} $rd, $rn, $imm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_ADCrr, ARM_INS_ADC: adc${s}${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_ADCrsi, ARM_INS_ADC: adc${s}${p} $rd, $rn, $shift */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_ADCrsr, ARM_INS_ADC: adc${s}${p} $rd, $rn, $shift */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_ADDri, ARM_INS_ADD: add${s}${p} $rd, $rn, $imm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_ADDrr, ARM_INS_ADD: add${s}${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_ADDrsi, ARM_INS_ADD: add${s}${p} $rd, $rn, $shift */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_ADDrsr, ARM_INS_ADD: add${s}${p} $rd, $rn, $shift */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_ADR, ARM_INS_ADR: adr${p} $rd, $label */ |
| { CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_AESD, ARM_INS_AESD: aesd.8 $vd, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_AESE, ARM_INS_AESE: aese.8 $vd, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_AESIMC, ARM_INS_AESIMC: aesimc.8 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_AESMC, ARM_INS_AESMC: aesmc.8 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_ANDri, ARM_INS_AND: and${s}${p} $rd, $rn, $imm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_ANDrr, ARM_INS_AND: and${s}${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_ANDrsi, ARM_INS_AND: and${s}${p} $rd, $rn, $shift */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_ANDrsr, ARM_INS_AND: and${s}${p} $rd, $rn, $shift */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_BFC, ARM_INS_BFC: bfc${p} $rd, $imm */ |
| { CS_AC_READ | CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_BFI, ARM_INS_BFI: bfi${p} $rd, $rn, $imm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_BICri, ARM_INS_BIC: bic${s}${p} $rd, $rn, $imm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_BICrr, ARM_INS_BIC: bic${s}${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_BICrsi, ARM_INS_BIC: bic${s}${p} $rd, $rn, $shift */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_BICrsr, ARM_INS_BIC: bic${s}${p} $rd, $rn, $shift */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_BKPT, ARM_INS_BKPT: bkpt $val */ |
| { 0 } |
| }, |
| { /* ARM_BL, ARM_INS_BL: bl $func */ |
| { 0 } |
| }, |
| { /* ARM_BLX, ARM_INS_BLX: blx $func */ |
| { CS_AC_READ, 0 } |
| }, |
| { /* ARM_BLX_pred, ARM_INS_BLX: blx${p} $func */ |
| { CS_AC_READ, 0 } |
| }, |
| { /* ARM_BLXi, ARM_INS_BLX: blx $target */ |
| { 0 } |
| }, |
| { /* ARM_BL_pred, ARM_INS_BL: bl${p} $func */ |
| { 0 } |
| }, |
| { /* ARM_BX, ARM_INS_BX: bx $dst */ |
| { CS_AC_READ, 0 } |
| }, |
| { /* ARM_BXJ, ARM_INS_BXJ: bxj${p} $func */ |
| { CS_AC_READ, 0 } |
| }, |
| { /* ARM_BX_RET, ARM_INS_BX: bx${p} lr */ |
| { 0 } |
| }, |
| { /* ARM_BX_pred, ARM_INS_BX: bx${p} $dst */ |
| { CS_AC_READ, 0 } |
| }, |
| { /* ARM_Bcc, ARM_INS_B: b${p} $target */ |
| { 0 } |
| }, |
| { /* ARM_CDP, ARM_INS_CDP: cdp${p} $cop, $opc1, $crd, $crn, $crm, $opc2 */ |
| { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } |
| }, |
| { /* ARM_CDP2, ARM_INS_CDP2: cdp2 $cop, $opc1, $crd, $crn, $crm, $opc2 */ |
| { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } |
| }, |
| { /* ARM_CLREX, ARM_INS_CLREX: clrex */ |
| { 0 } |
| }, |
| { /* ARM_CLZ, ARM_INS_CLZ: clz${p} $rd, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_CMNri, ARM_INS_CMN: cmn${p} $rn, $imm */ |
| { CS_AC_READ, 0 } |
| }, |
| { /* ARM_CMNzrr, ARM_INS_CMN: cmn${p} $rn, $rm */ |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_CMNzrsi, ARM_INS_CMN: cmn${p} $rn, $shift */ |
| { CS_AC_READ, 0 } |
| }, |
| { /* ARM_CMNzrsr, ARM_INS_CMN: cmn${p} $rn, $shift */ |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_CMPri, ARM_INS_CMP: cmp${p} $rn, $imm */ |
| { CS_AC_READ, 0 } |
| }, |
| { /* ARM_CMPrr, ARM_INS_CMP: cmp${p} $rn, $rm */ |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_CMPrsi, ARM_INS_CMP: cmp${p} $rn, $shift */ |
| { CS_AC_READ, 0 } |
| }, |
| { /* ARM_CMPrsr, ARM_INS_CMP: cmp${p} $rn, $shift */ |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_CPS1p, ARM_INS_CPS: cps $mode */ |
| { 0 } |
| }, |
| { /* ARM_CPS2p, ARM_INS_CPS: cps$imod $iflags */ |
| { 0 } |
| }, |
| { /* ARM_CPS3p, ARM_INS_CPS: cps$imod $iflags, $mode */ |
| { 0 } |
| }, |
| { /* ARM_CRC32B, ARM_INS_CRC32B: crc32b $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_CRC32CB, ARM_INS_CRC32CB: crc32cb $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_CRC32CH, ARM_INS_CRC32CH: crc32ch $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_CRC32CW, ARM_INS_CRC32CW: crc32cw $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_CRC32H, ARM_INS_CRC32H: crc32h $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_CRC32W, ARM_INS_CRC32W: crc32w $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_DBG, ARM_INS_DBG: dbg${p} $opt */ |
| { 0 } |
| }, |
| { /* ARM_DMB, ARM_INS_DMB: dmb $opt */ |
| { 0 } |
| }, |
| { /* ARM_DSB, ARM_INS_DSB: dsb $opt */ |
| { 0 } |
| }, |
| { /* ARM_EORri, ARM_INS_EOR: eor${s}${p} $rd, $rn, $imm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_EORrr, ARM_INS_EOR: eor${s}${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_EORrsi, ARM_INS_EOR: eor${s}${p} $rd, $rn, $shift */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_EORrsr, ARM_INS_EOR: eor${s}${p} $rd, $rn, $shift */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_ERET, ARM_INS_ERET: eret${p} */ |
| { 0 } |
| }, |
| { /* ARM_FCONSTD, ARM_INS_VMOV: vmov${p}.f64 $dd, $imm */ |
| { CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_FCONSTS, ARM_INS_VMOV: vmov${p}.f32 $sd, $imm */ |
| { CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_FLDMXDB_UPD, ARM_INS_FLDMDBX: fldmdbx${p} $rn!, $regs */ |
| { CS_AC_READ | CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_FLDMXIA, ARM_INS_FLDMIAX: fldmiax${p} $rn, $regs */ |
| { CS_AC_READ, 0 } |
| }, |
| { /* ARM_FLDMXIA_UPD, ARM_INS_FLDMIAX: fldmiax${p} $rn!, $regs */ |
| { CS_AC_READ | CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_FMSTAT, ARM_INS_VMRS: vmrs${p} apsr_nzcv, fpscr */ |
| { 0 } |
| }, |
| { /* ARM_FSTMXDB_UPD, ARM_INS_FSTMDBX: fstmdbx${p} $rn!, $regs */ |
| { CS_AC_READ | CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_FSTMXIA, ARM_INS_FSTMIAX: fstmiax${p} $rn, $regs */ |
| { CS_AC_READ, 0 } |
| }, |
| { /* ARM_FSTMXIA_UPD, ARM_INS_FSTMIAX: fstmiax${p} $rn!, $regs */ |
| { CS_AC_READ | CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_HINT, ARM_INS_HINT: hint${p} $imm */ |
| { 0 } |
| }, |
| { /* ARM_HLT, ARM_INS_HLT: hlt $val */ |
| { 0 } |
| }, |
| { /* ARM_HVC, ARM_INS_HVC: hvc $imm */ |
| { 0 } |
| }, |
| { /* ARM_ISB, ARM_INS_ISB: isb $opt */ |
| { 0 } |
| }, |
| { /* ARM_LDA, ARM_INS_LDA: lda${p} $rt, $addr */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDAB, ARM_INS_LDAB: ldab${p} $rt, $addr */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDAEX, ARM_INS_LDAEX: ldaex${p} $rt, $addr */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDAEXB, ARM_INS_LDAEXB: ldaexb${p} $rt, $addr */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDAEXD, ARM_INS_LDAEXD: ldaexd${p} $rt, $addr */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDAEXH, ARM_INS_LDAEXH: ldaexh${p} $rt, $addr */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDAH, ARM_INS_LDAH: ldah${p} $rt, $addr */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDC2L_OFFSET, ARM_INS_LDC2L: ldc2l $cop, $crd, $addr */ |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDC2L_OPTION, ARM_INS_LDC2L: ldc2l $cop, $crd, $addr, $option */ |
| { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDC2L_POST, ARM_INS_LDC2L: ldc2l $cop, $crd, $addr, $offset */ |
| { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDC2L_PRE, ARM_INS_LDC2L: ldc2l $cop, $crd, $addr! */ |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDC2_OFFSET, ARM_INS_LDC2: ldc2 $cop, $crd, $addr */ |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDC2_OPTION, ARM_INS_LDC2: ldc2 $cop, $crd, $addr, $option */ |
| { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDC2_POST, ARM_INS_LDC2: ldc2 $cop, $crd, $addr, $offset */ |
| { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDC2_PRE, ARM_INS_LDC2: ldc2 $cop, $crd, $addr! */ |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDCL_OFFSET, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr */ |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDCL_OPTION, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr, $option */ |
| { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDCL_POST, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr, $offset */ |
| { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDCL_PRE, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr! */ |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDC_OFFSET, ARM_INS_LDC: ldc${p} $cop, $crd, $addr */ |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDC_OPTION, ARM_INS_LDC: ldc${p} $cop, $crd, $addr, $option */ |
| { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDC_POST, ARM_INS_LDC: ldc${p} $cop, $crd, $addr, $offset */ |
| { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDC_PRE, ARM_INS_LDC: ldc${p} $cop, $crd, $addr! */ |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDMDA, ARM_INS_LDMDA: ldmda${p} $rn, $regs */ |
| { CS_AC_READ, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_LDMDA_UPD, ARM_INS_LDMDA: ldmda${p} $rn!, $regs */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_LDMDB, ARM_INS_LDMDB: ldmdb${p} $rn, $regs */ |
| { CS_AC_READ, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_LDMDB_UPD, ARM_INS_LDMDB: ldmdb${p} $rn!, $regs */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_LDMIA, ARM_INS_LDM: ldm${p} $rn, $regs */ |
| { CS_AC_READ, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_LDMIA_UPD, ARM_INS_LDM: ldm${p} $rn!, $regs */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_LDMIB, ARM_INS_LDMIB: ldmib${p} $rn, $regs */ |
| { CS_AC_READ, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_LDMIB_UPD, ARM_INS_LDMIB: ldmib${p} $rn!, $regs */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_LDRBT_POST_IMM, ARM_INS_LDRBT: ldrbt${p} $rt, $addr, $offset */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDRBT_POST_REG, ARM_INS_LDRBT: ldrbt${p} $rt, $addr, $offset */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDRB_POST_IMM, ARM_INS_LDRB: ldrb${p} $rt, $addr, $offset */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDRB_POST_REG, ARM_INS_LDRB: ldrb${p} $rt, $addr, $offset */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDRB_PRE_IMM, ARM_INS_LDRB: ldrb${p} $rt, $addr! */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDRB_PRE_REG, ARM_INS_LDRB: ldrb${p} $rt, $addr! */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDRBi12, ARM_INS_LDRB: ldrb${p} $rt, $addr */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDRBrs, ARM_INS_LDRB: ldrb${p} $rt, $shift */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDRD, ARM_INS_LDRD: ldrd${p} $rt, $rt2, $addr */ |
| { CS_AC_WRITE, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_LDRD_POST, ARM_INS_LDRD: ldrd${p} $rt, $rt2, $addr, $offset */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDRD_PRE, ARM_INS_LDRD: ldrd${p} $rt, $rt2, $addr! */ |
| { CS_AC_WRITE, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_LDREX, ARM_INS_LDREX: ldrex${p} $rt, $addr */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDREXB, ARM_INS_LDREXB: ldrexb${p} $rt, $addr */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDREXD, ARM_INS_LDREXD: ldrexd${p} $rt, $addr */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDREXH, ARM_INS_LDREXH: ldrexh${p} $rt, $addr */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDRH, ARM_INS_LDRH: ldrh${p} $rt, $addr */ |
| { CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_LDRHTi, ARM_INS_LDRHT: ldrht${p} $rt, $addr, $offset */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDRHTr, ARM_INS_LDRHT: ldrht${p} $rt, $addr, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDRH_POST, ARM_INS_LDRH: ldrh${p} $rt, $addr, $offset */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDRH_PRE, ARM_INS_LDRH: ldrh${p} $rt, $addr! */ |
| { CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_LDRSB, ARM_INS_LDRSB: ldrsb${p} $rt, $addr */ |
| { CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_LDRSBTi, ARM_INS_LDRSBT: ldrsbt${p} $rt, $addr, $offset */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDRSBTr, ARM_INS_LDRSBT: ldrsbt${p} $rt, $addr, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDRSB_POST, ARM_INS_LDRSB: ldrsb${p} $rt, $addr, $offset */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDRSB_PRE, ARM_INS_LDRSB: ldrsb${p} $rt, $addr! */ |
| { CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_LDRSH, ARM_INS_LDRSH: ldrsh${p} $rt, $addr */ |
| { CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_LDRSHTi, ARM_INS_LDRSHT: ldrsht${p} $rt, $addr, $offset */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDRSHTr, ARM_INS_LDRSHT: ldrsht${p} $rt, $addr, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDRSH_POST, ARM_INS_LDRSH: ldrsh${p} $rt, $addr, $offset */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDRSH_PRE, ARM_INS_LDRSH: ldrsh${p} $rt, $addr! */ |
| { CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_LDRT_POST_IMM, ARM_INS_LDRT: ldrt${p} $rt, $addr, $offset */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDRT_POST_REG, ARM_INS_LDRT: ldrt${p} $rt, $addr, $offset */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDR_POST_IMM, ARM_INS_LDR: ldr${p} $rt, $addr, $offset */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDR_POST_REG, ARM_INS_LDR: ldr${p} $rt, $addr, $offset */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDR_PRE_IMM, ARM_INS_LDR: ldr${p} $rt, $addr! */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDR_PRE_REG, ARM_INS_LDR: ldr${p} $rt, $addr! */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDRcp, ARM_INS_LDR: ldr${p} $rt, $addr */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDRi12, ARM_INS_LDR: ldr${p} $rt, $addr */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_LDRrs, ARM_INS_LDR: ldr${p} $rt, $shift */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_MCR, ARM_INS_MCR: mcr${p} $cop, $opc1, $rt, $crn, $crm, $opc2 */ |
| { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } |
| }, |
| { /* ARM_MCR2, ARM_INS_MCR2: mcr2 $cop, $opc1, $rt, $crn, $crm, $opc2 */ |
| { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } |
| }, |
| { /* ARM_MCRR, ARM_INS_MCRR: mcrr${p} $cop, $opc1, $rt, $rt2, $crm */ |
| { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_MCRR2, ARM_INS_MCRR2: mcrr2 $cop, $opc1, $rt, $rt2, $crm */ |
| { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_MLA, ARM_INS_MLA: mla${s}${p} $rd, $rn, $rm, $ra */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_MLS, ARM_INS_MLS: mls${p} $rd, $rn, $rm, $ra */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_MOVPCLR, ARM_INS_MOV: mov${p} pc, lr */ |
| { 0 } |
| }, |
| { /* ARM_MOVTi16, ARM_INS_MOVT: movt${p} $rd, $imm */ |
| { CS_AC_READ | CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_MOVi, ARM_INS_MOV: mov${s}${p} $rd, $imm */ |
| { CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_MOVi16, ARM_INS_MOVW: movw${p} $rd, $imm */ |
| { CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_MOVr, ARM_INS_MOV: mov${s}${p} $rd, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_MOVr_TC, ARM_INS_MOV: mov${s}${p} $rd, $rm */ |
| { 0 } |
| }, |
| { /* ARM_MOVsi, ARM_INS_MOV: mov${s}${p} $rd, $src */ |
| { CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_MOVsr, ARM_INS_MOV: mov${s}${p} $rd, $src */ |
| { CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_MRC, ARM_INS_MRC: mrc${p} $cop, $opc1, $rt, $crn, $crm, $opc2 */ |
| { CS_AC_READ, CS_AC_IGNORE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } |
| }, |
| { /* ARM_MRC2, ARM_INS_MRC2: mrc2 $cop, $opc1, $rt, $crn, $crm, $opc2 */ |
| { CS_AC_READ, CS_AC_IGNORE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } |
| }, |
| { /* ARM_MRRC, ARM_INS_MRRC: mrrc${p} $cop, $opc1, $rt, $rt2, $crm */ |
| { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_MRRC2, ARM_INS_MRRC2: mrrc2 $cop, $opc1, $rt, $rt2, $crm */ |
| { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_MRS, ARM_INS_MRS: mrs${p} $rd, apsr */ |
| { CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_MRSbanked, ARM_INS_MRS: mrs${p} $rd, $banked */ |
| { CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_MRSsys, ARM_INS_MRS: mrs${p} $rd, spsr */ |
| { CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_MSR, ARM_INS_MSR: msr${p} $mask, $rn */ |
| { CS_AC_READ, 0 } |
| }, |
| { /* ARM_MSRbanked, ARM_INS_MSR: msr${p} $banked, $rn */ |
| { CS_AC_READ, 0 } |
| }, |
| { /* ARM_MSRi, ARM_INS_MSR: msr${p} $mask, $imm */ |
| { 0 } |
| }, |
| { /* ARM_MUL, ARM_INS_MUL: mul${s}${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_MVNi, ARM_INS_MVN: mvn${s}${p} $rd, $imm */ |
| { CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_MVNr, ARM_INS_MVN: mvn${s}${p} $rd, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_MVNsi, ARM_INS_MVN: mvn${s}${p} $rd, $shift */ |
| { CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_MVNsr, ARM_INS_MVN: mvn${s}${p} $rd, $shift */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_ORRri, ARM_INS_ORR: orr${s}${p} $rd, $rn, $imm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_ORRrr, ARM_INS_ORR: orr${s}${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_ORRrsi, ARM_INS_ORR: orr${s}${p} $rd, $rn, $shift */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_ORRrsr, ARM_INS_ORR: orr${s}${p} $rd, $rn, $shift */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_PKHBT, ARM_INS_PKHBT: pkhbt${p} $rd, $rn, $rm$sh */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_PKHTB, ARM_INS_PKHTB: pkhtb${p} $rd, $rn, $rm$sh */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_PLDWi12, ARM_INS_PLDW: pldw $addr */ |
| { CS_AC_READ, 0 } |
| }, |
| { /* ARM_PLDWrs, ARM_INS_PLDW: pldw $shift */ |
| { CS_AC_READ, 0 } |
| }, |
| { /* ARM_PLDi12, ARM_INS_PLD: pld $addr */ |
| { CS_AC_READ, 0 } |
| }, |
| { /* ARM_PLDrs, ARM_INS_PLD: pld $shift */ |
| { CS_AC_READ, 0 } |
| }, |
| { /* ARM_PLIi12, ARM_INS_PLI: pli $addr */ |
| { CS_AC_READ, 0 } |
| }, |
| { /* ARM_PLIrs, ARM_INS_PLI: pli $shift */ |
| { CS_AC_READ, 0 } |
| }, |
| { /* ARM_QADD, ARM_INS_QADD: qadd${p} $rd, $rm, $rn */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_QADD16, ARM_INS_QADD16: qadd16${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_QADD8, ARM_INS_QADD8: qadd8${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_QASX, ARM_INS_QASX: qasx${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_QDADD, ARM_INS_QDADD: qdadd${p} $rd, $rm, $rn */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_QDSUB, ARM_INS_QDSUB: qdsub${p} $rd, $rm, $rn */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_QSAX, ARM_INS_QSAX: qsax${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_QSUB, ARM_INS_QSUB: qsub${p} $rd, $rm, $rn */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_QSUB16, ARM_INS_QSUB16: qsub16${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_QSUB8, ARM_INS_QSUB8: qsub8${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_RBIT, ARM_INS_RBIT: rbit${p} $rd, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_REV, ARM_INS_REV: rev${p} $rd, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_REV16, ARM_INS_REV16: rev16${p} $rd, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_REVSH, ARM_INS_REVSH: revsh${p} $rd, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_RFEDA, ARM_INS_RFEDA: rfeda $rn */ |
| { CS_AC_READ, 0 } |
| }, |
| { /* ARM_RFEDA_UPD, ARM_INS_RFEDA: rfeda $rn! */ |
| { CS_AC_READ, 0 } |
| }, |
| { /* ARM_RFEDB, ARM_INS_RFEDB: rfedb $rn */ |
| { CS_AC_READ, 0 } |
| }, |
| { /* ARM_RFEDB_UPD, ARM_INS_RFEDB: rfedb $rn! */ |
| { CS_AC_READ, 0 } |
| }, |
| { /* ARM_RFEIA, ARM_INS_RFEIA: rfeia $rn */ |
| { CS_AC_READ, 0 } |
| }, |
| { /* ARM_RFEIA_UPD, ARM_INS_RFEIA: rfeia $rn! */ |
| { CS_AC_READ, 0 } |
| }, |
| { /* ARM_RFEIB, ARM_INS_RFEIB: rfeib $rn */ |
| { CS_AC_READ, 0 } |
| }, |
| { /* ARM_RFEIB_UPD, ARM_INS_RFEIB: rfeib $rn! */ |
| { CS_AC_READ, 0 } |
| }, |
| { /* ARM_RSBri, ARM_INS_RSB: rsb${s}${p} $rd, $rn, $imm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_RSBrr, ARM_INS_RSB: rsb${s}${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_RSBrsi, ARM_INS_RSB: rsb${s}${p} $rd, $rn, $shift */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_RSBrsr, ARM_INS_RSB: rsb${s}${p} $rd, $rn, $shift */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_RSCri, ARM_INS_RSC: rsc${s}${p} $rd, $rn, $imm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_RSCrr, ARM_INS_RSC: rsc${s}${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_RSCrsi, ARM_INS_RSC: rsc${s}${p} $rd, $rn, $shift */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_RSCrsr, ARM_INS_RSC: rsc${s}${p} $rd, $rn, $shift */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SADD16, ARM_INS_SADD16: sadd16${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SADD8, ARM_INS_SADD8: sadd8${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SASX, ARM_INS_SASX: sasx${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SBCri, ARM_INS_SBC: sbc${s}${p} $rd, $rn, $imm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SBCrr, ARM_INS_SBC: sbc${s}${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SBCrsi, ARM_INS_SBC: sbc${s}${p} $rd, $rn, $shift */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SBCrsr, ARM_INS_SBC: sbc${s}${p} $rd, $rn, $shift */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SBFX, ARM_INS_SBFX: sbfx${p} $rd, $rn, $lsb, $width */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SDIV, ARM_INS_SDIV: sdiv${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SEL, ARM_INS_SEL: sel${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SETEND, ARM_INS_SETEND: setend $end */ |
| { 0 } |
| }, |
| { /* ARM_SHA1C, ARM_INS_SHA1C: sha1c.32 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SHA1H, ARM_INS_SHA1H: sha1h.32 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SHA1M, ARM_INS_SHA1M: sha1m.32 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SHA1P, ARM_INS_SHA1P: sha1p.32 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SHA1SU0, ARM_INS_SHA1SU0: sha1su0.32 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SHA1SU1, ARM_INS_SHA1SU1: sha1su1.32 $vd, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SHA256H, ARM_INS_SHA256H: sha256h.32 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SHA256H2, ARM_INS_SHA256H2: sha256h2.32 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SHA256SU0, ARM_INS_SHA256SU0: sha256su0.32 $vd, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SHA256SU1, ARM_INS_SHA256SU1: sha256su1.32 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SHADD16, ARM_INS_SHADD16: shadd16${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SHADD8, ARM_INS_SHADD8: shadd8${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SHASX, ARM_INS_SHASX: shasx${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SHSAX, ARM_INS_SHSAX: shsax${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SHSUB16, ARM_INS_SHSUB16: shsub16${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SHSUB8, ARM_INS_SHSUB8: shsub8${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SMC, ARM_INS_SMC: smc${p} $opt */ |
| { 0 } |
| }, |
| { /* ARM_SMLABB, ARM_INS_SMLABB: smlabb${p} $rd, $rn, $rm, $ra */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SMLABT, ARM_INS_SMLABT: smlabt${p} $rd, $rn, $rm, $ra */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SMLAD, ARM_INS_SMLAD: smlad${p} $rd, $rn, $rm, $ra */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SMLADX, ARM_INS_SMLADX: smladx${p} $rd, $rn, $rm, $ra */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SMLAL, ARM_INS_SMLAL: smlal${s}${p} $rdlo, $rdhi, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SMLALBB, ARM_INS_SMLALBB: smlalbb${p} $rdlo, $rdhi, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SMLALBT, ARM_INS_SMLALBT: smlalbt${p} $rdlo, $rdhi, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SMLALD, ARM_INS_SMLALD: smlald${p} $rdlo, $rdhi, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SMLALDX, ARM_INS_SMLALDX: smlaldx${p} $rdlo, $rdhi, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SMLALTB, ARM_INS_SMLALTB: smlaltb${p} $rdlo, $rdhi, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SMLALTT, ARM_INS_SMLALTT: smlaltt${p} $rdlo, $rdhi, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SMLATB, ARM_INS_SMLATB: smlatb${p} $rd, $rn, $rm, $ra */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SMLATT, ARM_INS_SMLATT: smlatt${p} $rd, $rn, $rm, $ra */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SMLAWB, ARM_INS_SMLAWB: smlawb${p} $rd, $rn, $rm, $ra */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SMLAWT, ARM_INS_SMLAWT: smlawt${p} $rd, $rn, $rm, $ra */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SMLSD, ARM_INS_SMLSD: smlsd${p} $rd, $rn, $rm, $ra */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SMLSDX, ARM_INS_SMLSDX: smlsdx${p} $rd, $rn, $rm, $ra */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SMLSLD, ARM_INS_SMLSLD: smlsld${p} $rdlo, $rdhi, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SMLSLDX, ARM_INS_SMLSLDX: smlsldx${p} $rdlo, $rdhi, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SMMLA, ARM_INS_SMMLA: smmla${p} $rd, $rn, $rm, $ra */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SMMLAR, ARM_INS_SMMLAR: smmlar${p} $rd, $rn, $rm, $ra */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SMMLS, ARM_INS_SMMLS: smmls${p} $rd, $rn, $rm, $ra */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SMMLSR, ARM_INS_SMMLSR: smmlsr${p} $rd, $rn, $rm, $ra */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SMMUL, ARM_INS_SMMUL: smmul${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SMMULR, ARM_INS_SMMULR: smmulr${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SMUAD, ARM_INS_SMUAD: smuad${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SMUADX, ARM_INS_SMUADX: smuadx${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SMULBB, ARM_INS_SMULBB: smulbb${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SMULBT, ARM_INS_SMULBT: smulbt${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SMULL, ARM_INS_SMULL: smull${s}${p} $rdlo, $rdhi, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SMULTB, ARM_INS_SMULTB: smultb${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SMULTT, ARM_INS_SMULTT: smultt${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SMULWB, ARM_INS_SMULWB: smulwb${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SMULWT, ARM_INS_SMULWT: smulwt${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SMUSD, ARM_INS_SMUSD: smusd${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SMUSDX, ARM_INS_SMUSDX: smusdx${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SRSDA, ARM_INS_SRSDA: srsda sp, $mode */ |
| { 0 } |
| }, |
| { /* ARM_SRSDA_UPD, ARM_INS_SRSDA: srsda sp!, $mode */ |
| { 0 } |
| }, |
| { /* ARM_SRSDB, ARM_INS_SRSDB: srsdb sp, $mode */ |
| { 0 } |
| }, |
| { /* ARM_SRSDB_UPD, ARM_INS_SRSDB: srsdb sp!, $mode */ |
| { 0 } |
| }, |
| { /* ARM_SRSIA, ARM_INS_SRSIA: srsia sp, $mode */ |
| { 0 } |
| }, |
| { /* ARM_SRSIA_UPD, ARM_INS_SRSIA: srsia sp!, $mode */ |
| { 0 } |
| }, |
| { /* ARM_SRSIB, ARM_INS_SRSIB: srsib sp, $mode */ |
| { 0 } |
| }, |
| { /* ARM_SRSIB_UPD, ARM_INS_SRSIB: srsib sp!, $mode */ |
| { 0 } |
| }, |
| { /* ARM_SSAT, ARM_INS_SSAT: ssat${p} $rd, $sat_imm, $rn$sh */ |
| { CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_SSAT16, ARM_INS_SSAT16: ssat16${p} $rd, $sat_imm, $rn */ |
| { CS_AC_WRITE, CS_AC_IGNORE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SSAX, ARM_INS_SSAX: ssax${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SSUB16, ARM_INS_SSUB16: ssub16${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SSUB8, ARM_INS_SSUB8: ssub8${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STC2L_OFFSET, ARM_INS_STC2L: stc2l $cop, $crd, $addr */ |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STC2L_OPTION, ARM_INS_STC2L: stc2l $cop, $crd, $addr, $option */ |
| { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STC2L_POST, ARM_INS_STC2L: stc2l $cop, $crd, $addr, $offset */ |
| { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STC2L_PRE, ARM_INS_STC2L: stc2l $cop, $crd, $addr! */ |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STC2_OFFSET, ARM_INS_STC2: stc2 $cop, $crd, $addr */ |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STC2_OPTION, ARM_INS_STC2: stc2 $cop, $crd, $addr, $option */ |
| { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STC2_POST, ARM_INS_STC2: stc2 $cop, $crd, $addr, $offset */ |
| { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STC2_PRE, ARM_INS_STC2: stc2 $cop, $crd, $addr! */ |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STCL_OFFSET, ARM_INS_STCL: stcl${p} $cop, $crd, $addr */ |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STCL_OPTION, ARM_INS_STCL: stcl${p} $cop, $crd, $addr, $option */ |
| { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STCL_POST, ARM_INS_STCL: stcl${p} $cop, $crd, $addr, $offset */ |
| { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STCL_PRE, ARM_INS_STCL: stcl${p} $cop, $crd, $addr! */ |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STC_OFFSET, ARM_INS_STC: stc${p} $cop, $crd, $addr */ |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STC_OPTION, ARM_INS_STC: stc${p} $cop, $crd, $addr, $option */ |
| { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STC_POST, ARM_INS_STC: stc${p} $cop, $crd, $addr, $offset */ |
| { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STC_PRE, ARM_INS_STC: stc${p} $cop, $crd, $addr! */ |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STL, ARM_INS_STL: stl${p} $rt, $addr */ |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STLB, ARM_INS_STLB: stlb${p} $rt, $addr */ |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STLEX, ARM_INS_STLEX: stlex${p} $rd, $rt, $addr */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STLEXB, ARM_INS_STLEXB: stlexb${p} $rd, $rt, $addr */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STLEXD, ARM_INS_STLEXD: stlexd${p} $rd, $rt, $addr */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STLEXH, ARM_INS_STLEXH: stlexh${p} $rd, $rt, $addr */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STLH, ARM_INS_STLH: stlh${p} $rt, $addr */ |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STMDA, ARM_INS_STMDA: stmda${p} $rn, $regs */ |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STMDA_UPD, ARM_INS_STMDA: stmda${p} $rn!, $regs */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STMDB, ARM_INS_STMDB: stmdb${p} $rn, $regs */ |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STMDB_UPD, ARM_INS_STMDB: stmdb${p} $rn!, $regs */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STMIA, ARM_INS_STM: stm${p} $rn, $regs */ |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STMIA_UPD, ARM_INS_STM: stm${p} $rn!, $regs */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STMIB, ARM_INS_STMIB: stmib${p} $rn, $regs */ |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STMIB_UPD, ARM_INS_STMIB: stmib${p} $rn!, $regs */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STRBT_POST_IMM, ARM_INS_STRBT: strbt${p} $rt, $addr, $offset */ |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STRBT_POST_REG, ARM_INS_STRBT: strbt${p} $rt, $addr, $offset */ |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STRB_POST_IMM, ARM_INS_STRB: strb${p} $rt, $addr, $offset */ |
| { CS_AC_READ, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_STRB_POST_REG, ARM_INS_STRB: strb${p} $rt, $addr, $offset */ |
| { CS_AC_READ, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_STRB_PRE_IMM, ARM_INS_STRB: strb${p} $rt, $addr! */ |
| { CS_AC_READ, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_STRB_PRE_REG, ARM_INS_STRB: strb${p} $rt, $addr! */ |
| { CS_AC_READ, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_STRBi12, ARM_INS_STRB: strb${p} $rt, $addr */ |
| { CS_AC_READ, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_STRBrs, ARM_INS_STRB: strb${p} $rt, $shift */ |
| { CS_AC_READ, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_STRD, ARM_INS_STRD: strd${p} $rt, $rt2, $addr */ |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STRD_POST, ARM_INS_STRD: strd${p} $rt, $rt2, $addr, $offset */ |
| { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STRD_PRE, ARM_INS_STRD: strd${p} $rt, $rt2, $addr! */ |
| { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STREX, ARM_INS_STREX: strex${p} $rd, $rt, $addr */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STREXB, ARM_INS_STREXB: strexb${p} $rd, $rt, $addr */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STREXD, ARM_INS_STREXD: strexd${p} $rd, $rt, $addr */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STREXH, ARM_INS_STREXH: strexh${p} $rd, $rt, $addr */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STRH, ARM_INS_STRH: strh${p} $rt, $addr */ |
| { CS_AC_READ, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_STRHTi, ARM_INS_STRHT: strht${p} $rt, $addr, $offset */ |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STRHTr, ARM_INS_STRHT: strht${p} $rt, $addr, $rm */ |
| { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STRH_POST, ARM_INS_STRH: strh${p} $rt, $addr, $offset */ |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_STRH_PRE, ARM_INS_STRH: strh${p} $rt, $addr! */ |
| { CS_AC_READ, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_STRT_POST_IMM, ARM_INS_STRT: strt${p} $rt, $addr, $offset */ |
| { CS_AC_READ, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_STRT_POST_REG, ARM_INS_STRT: strt${p} $rt, $addr, $offset */ |
| { CS_AC_READ, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_STR_POST_IMM, ARM_INS_STR: str${p} $rt, $addr, $offset */ |
| { CS_AC_READ, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_STR_POST_REG, ARM_INS_STR: str${p} $rt, $addr, $offset */ |
| { CS_AC_READ, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_STR_PRE_IMM, ARM_INS_STR: str${p} $rt, $addr! */ |
| { CS_AC_READ, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_STR_PRE_REG, ARM_INS_STR: str${p} $rt, $addr! */ |
| { CS_AC_READ, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_STRi12, ARM_INS_STR: str${p} $rt, $addr */ |
| { CS_AC_READ, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_STRrs, ARM_INS_STR: str${p} $rt, $shift */ |
| { CS_AC_READ, 0 } |
| }, |
| { /* ARM_SUBri, ARM_INS_SUB: sub${s}${p} $rd, $rn, $imm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SUBrr, ARM_INS_SUB: sub${s}${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SUBrsi, ARM_INS_SUB: sub${s}${p} $rd, $rn, $shift */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SUBrsr, ARM_INS_SUB: sub${s}${p} $rd, $rn, $shift */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SVC, ARM_INS_SVC: svc${p} $svc */ |
| { 0 } |
| }, |
| { /* ARM_SWP, ARM_INS_SWP: swp${p} $rt, $rt2, $addr */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SWPB, ARM_INS_SWPB: swpb${p} $rt, $rt2, $addr */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SXTAB, ARM_INS_SXTAB: sxtab${p} $rd, $rn, $rm$rot */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SXTAB16, ARM_INS_SXTAB16: sxtab16${p} $rd, $rn, $rm$rot */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SXTAH, ARM_INS_SXTAH: sxtah${p} $rd, $rn, $rm$rot */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_SXTB, ARM_INS_SXTB: sxtb${p} $rd, $rm$rot */ |
| { CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_SXTB16, ARM_INS_SXTB16: sxtb16${p} $rd, $rm$rot */ |
| { CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_SXTH, ARM_INS_SXTH: sxth${p} $rd, $rm$rot */ |
| { CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_TEQri, ARM_INS_TEQ: teq${p} $rn, $imm */ |
| { CS_AC_READ, 0 } |
| }, |
| { /* ARM_TEQrr, ARM_INS_TEQ: teq${p} $rn, $rm */ |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_TEQrsi, ARM_INS_TEQ: teq${p} $rn, $shift */ |
| { CS_AC_READ, 0 } |
| }, |
| { /* ARM_TEQrsr, ARM_INS_TEQ: teq${p} $rn, $shift */ |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_TRAP, ARM_INS_TRAP: trap */ |
| { 0 } |
| }, |
| { /* ARM_TRAPNaCl, ARM_INS_TRAP: trap */ |
| { 0 } |
| }, |
| { /* ARM_TSTri, ARM_INS_TST: tst${p} $rn, $imm */ |
| { CS_AC_READ, 0 } |
| }, |
| { /* ARM_TSTrr, ARM_INS_TST: tst${p} $rn, $rm */ |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_TSTrsi, ARM_INS_TST: tst${p} $rn, $shift */ |
| { CS_AC_READ, 0 } |
| }, |
| { /* ARM_TSTrsr, ARM_INS_TST: tst${p} $rn, $shift */ |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_UADD16, ARM_INS_UADD16: uadd16${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_UADD8, ARM_INS_UADD8: uadd8${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_UASX, ARM_INS_UASX: uasx${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_UBFX, ARM_INS_UBFX: ubfx${p} $rd, $rn, $lsb, $width */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_UDF, ARM_INS_UDF: udf $imm16 */ |
| { 0 } |
| }, |
| { /* ARM_UDIV, ARM_INS_UDIV: udiv${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_UHADD16, ARM_INS_UHADD16: uhadd16${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_UHADD8, ARM_INS_UHADD8: uhadd8${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_UHASX, ARM_INS_UHASX: uhasx${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_UHSAX, ARM_INS_UHSAX: uhsax${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_UHSUB16, ARM_INS_UHSUB16: uhsub16${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_UHSUB8, ARM_INS_UHSUB8: uhsub8${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_UMAAL, ARM_INS_UMAAL: umaal${p} $rdlo, $rdhi, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_UMLAL, ARM_INS_UMLAL: umlal${s}${p} $rdlo, $rdhi, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_UMULL, ARM_INS_UMULL: umull${s}${p} $rdlo, $rdhi, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_UQADD16, ARM_INS_UQADD16: uqadd16${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_UQADD8, ARM_INS_UQADD8: uqadd8${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_UQASX, ARM_INS_UQASX: uqasx${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_UQSAX, ARM_INS_UQSAX: uqsax${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_UQSUB16, ARM_INS_UQSUB16: uqsub16${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_UQSUB8, ARM_INS_UQSUB8: uqsub8${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_USAD8, ARM_INS_USAD8: usad8${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_USADA8, ARM_INS_USADA8: usada8${p} $rd, $rn, $rm, $ra */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_USAT, ARM_INS_USAT: usat${p} $rd, $sat_imm, $rn$sh */ |
| { CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_USAT16, ARM_INS_USAT16: usat16${p} $rd, $sat_imm, $rn */ |
| { CS_AC_WRITE, CS_AC_IGNORE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_USAX, ARM_INS_USAX: usax${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_USUB16, ARM_INS_USUB16: usub16${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_USUB8, ARM_INS_USUB8: usub8${p} $rd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_UXTAB, ARM_INS_UXTAB: uxtab${p} $rd, $rn, $rm$rot */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_UXTAB16, ARM_INS_UXTAB16: uxtab16${p} $rd, $rn, $rm$rot */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_UXTAH, ARM_INS_UXTAH: uxtah${p} $rd, $rn, $rm$rot */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_UXTB, ARM_INS_UXTB: uxtb${p} $rd, $rm$rot */ |
| { CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_UXTB16, ARM_INS_UXTB16: uxtb16${p} $rd, $rm$rot */ |
| { CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_UXTH, ARM_INS_UXTH: uxth${p} $rd, $rm$rot */ |
| { CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_VABALsv2i64, ARM_INS_VABAL: vabal${p}.s32 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABALsv4i32, ARM_INS_VABAL: vabal${p}.s16 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABALsv8i16, ARM_INS_VABAL: vabal${p}.s8 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABALuv2i64, ARM_INS_VABAL: vabal${p}.u32 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABALuv4i32, ARM_INS_VABAL: vabal${p}.u16 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABALuv8i16, ARM_INS_VABAL: vabal${p}.u8 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABAsv16i8, ARM_INS_VABA: vaba${p}.s8 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABAsv2i32, ARM_INS_VABA: vaba${p}.s32 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABAsv4i16, ARM_INS_VABA: vaba${p}.s16 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABAsv4i32, ARM_INS_VABA: vaba${p}.s32 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABAsv8i16, ARM_INS_VABA: vaba${p}.s16 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABAsv8i8, ARM_INS_VABA: vaba${p}.s8 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABAuv16i8, ARM_INS_VABA: vaba${p}.u8 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABAuv2i32, ARM_INS_VABA: vaba${p}.u32 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABAuv4i16, ARM_INS_VABA: vaba${p}.u16 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABAuv4i32, ARM_INS_VABA: vaba${p}.u32 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABAuv8i16, ARM_INS_VABA: vaba${p}.u16 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABAuv8i8, ARM_INS_VABA: vaba${p}.u8 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABDLsv2i64, ARM_INS_VABDL: vabdl${p}.s32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABDLsv4i32, ARM_INS_VABDL: vabdl${p}.s16 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABDLsv8i16, ARM_INS_VABDL: vabdl${p}.s8 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABDLuv2i64, ARM_INS_VABDL: vabdl${p}.u32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABDLuv4i32, ARM_INS_VABDL: vabdl${p}.u16 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABDLuv8i16, ARM_INS_VABDL: vabdl${p}.u8 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABDfd, ARM_INS_VABD: vabd${p}.f32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABDfq, ARM_INS_VABD: vabd${p}.f32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABDsv16i8, ARM_INS_VABD: vabd${p}.s8 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABDsv2i32, ARM_INS_VABD: vabd${p}.s32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABDsv4i16, ARM_INS_VABD: vabd${p}.s16 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABDsv4i32, ARM_INS_VABD: vabd${p}.s32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABDsv8i16, ARM_INS_VABD: vabd${p}.s16 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABDsv8i8, ARM_INS_VABD: vabd${p}.s8 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABDuv16i8, ARM_INS_VABD: vabd${p}.u8 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABDuv2i32, ARM_INS_VABD: vabd${p}.u32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABDuv4i16, ARM_INS_VABD: vabd${p}.u16 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABDuv4i32, ARM_INS_VABD: vabd${p}.u32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABDuv8i16, ARM_INS_VABD: vabd${p}.u16 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABDuv8i8, ARM_INS_VABD: vabd${p}.u8 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABSD, ARM_INS_VABS: vabs${p}.f64 $dd, $dm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABSS, ARM_INS_VABS: vabs${p}.f32 $sd, $sm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABSfd, ARM_INS_VABS: vabs${p}.f32 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABSfq, ARM_INS_VABS: vabs${p}.f32 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABSv16i8, ARM_INS_VABS: vabs${p}.s8 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABSv2i32, ARM_INS_VABS: vabs${p}.s32 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABSv4i16, ARM_INS_VABS: vabs${p}.s16 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABSv4i32, ARM_INS_VABS: vabs${p}.s32 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABSv8i16, ARM_INS_VABS: vabs${p}.s16 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VABSv8i8, ARM_INS_VABS: vabs${p}.s8 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VACGEd, ARM_INS_VACGE: vacge${p}.f32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VACGEq, ARM_INS_VACGE: vacge${p}.f32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VACGTd, ARM_INS_VACGT: vacgt${p}.f32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VACGTq, ARM_INS_VACGT: vacgt${p}.f32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VADDD, ARM_INS_VADD: vadd${p}.f64 $dd, $dn, $dm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VADDHNv2i32, ARM_INS_VADDHN: vaddhn${p}.i64 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VADDHNv4i16, ARM_INS_VADDHN: vaddhn${p}.i32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VADDHNv8i8, ARM_INS_VADDHN: vaddhn${p}.i16 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VADDLsv2i64, ARM_INS_VADDL: vaddl${p}.s32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VADDLsv4i32, ARM_INS_VADDL: vaddl${p}.s16 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VADDLsv8i16, ARM_INS_VADDL: vaddl${p}.s8 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VADDLuv2i64, ARM_INS_VADDL: vaddl${p}.u32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VADDLuv4i32, ARM_INS_VADDL: vaddl${p}.u16 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VADDLuv8i16, ARM_INS_VADDL: vaddl${p}.u8 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VADDS, ARM_INS_VADD: vadd${p}.f32 $sd, $sn, $sm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VADDWsv2i64, ARM_INS_VADDW: vaddw${p}.s32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VADDWsv4i32, ARM_INS_VADDW: vaddw${p}.s16 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VADDWsv8i16, ARM_INS_VADDW: vaddw${p}.s8 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VADDWuv2i64, ARM_INS_VADDW: vaddw${p}.u32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VADDWuv4i32, ARM_INS_VADDW: vaddw${p}.u16 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VADDWuv8i16, ARM_INS_VADDW: vaddw${p}.u8 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VADDfd, ARM_INS_VADD: vadd${p}.f32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VADDfq, ARM_INS_VADD: vadd${p}.f32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VADDv16i8, ARM_INS_VADD: vadd${p}.i8 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VADDv1i64, ARM_INS_VADD: vadd${p}.i64 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VADDv2i32, ARM_INS_VADD: vadd${p}.i32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VADDv2i64, ARM_INS_VADD: vadd${p}.i64 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VADDv4i16, ARM_INS_VADD: vadd${p}.i16 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VADDv4i32, ARM_INS_VADD: vadd${p}.i32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VADDv8i16, ARM_INS_VADD: vadd${p}.i16 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VADDv8i8, ARM_INS_VADD: vadd${p}.i8 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VANDd, ARM_INS_VAND: vand${p} $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VANDq, ARM_INS_VAND: vand${p} $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VBICd, ARM_INS_VBIC: vbic${p} $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VBICiv2i32, ARM_INS_VBIC: vbic${p}.i32 $vd, $simm */ |
| { CS_AC_READ | CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_VBICiv4i16, ARM_INS_VBIC: vbic${p}.i16 $vd, $simm */ |
| { CS_AC_READ | CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_VBICiv4i32, ARM_INS_VBIC: vbic${p}.i32 $vd, $simm */ |
| { CS_AC_READ | CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_VBICiv8i16, ARM_INS_VBIC: vbic${p}.i16 $vd, $simm */ |
| { CS_AC_READ | CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_VBICq, ARM_INS_VBIC: vbic${p} $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VBIFd, ARM_INS_VBIF: vbif${p} $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VBIFq, ARM_INS_VBIF: vbif${p} $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VBITd, ARM_INS_VBIT: vbit${p} $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VBITq, ARM_INS_VBIT: vbit${p} $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VBSLd, ARM_INS_VBSL: vbsl${p} $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VBSLq, ARM_INS_VBSL: vbsl${p} $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCEQfd, ARM_INS_VCEQ: vceq${p}.f32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCEQfq, ARM_INS_VCEQ: vceq${p}.f32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCEQv16i8, ARM_INS_VCEQ: vceq${p}.i8 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCEQv2i32, ARM_INS_VCEQ: vceq${p}.i32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCEQv4i16, ARM_INS_VCEQ: vceq${p}.i16 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCEQv4i32, ARM_INS_VCEQ: vceq${p}.i32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCEQv8i16, ARM_INS_VCEQ: vceq${p}.i16 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCEQv8i8, ARM_INS_VCEQ: vceq${p}.i8 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCEQzv16i8, ARM_INS_VCEQ: vceq${p}.i8 $vd, $vm, #0 */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCEQzv2f32, ARM_INS_VCEQ: vceq${p}.f32 $vd, $vm, #0 */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCEQzv2i32, ARM_INS_VCEQ: vceq${p}.i32 $vd, $vm, #0 */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCEQzv4f32, ARM_INS_VCEQ: vceq${p}.f32 $vd, $vm, #0 */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCEQzv4i16, ARM_INS_VCEQ: vceq${p}.i16 $vd, $vm, #0 */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCEQzv4i32, ARM_INS_VCEQ: vceq${p}.i32 $vd, $vm, #0 */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCEQzv8i16, ARM_INS_VCEQ: vceq${p}.i16 $vd, $vm, #0 */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCEQzv8i8, ARM_INS_VCEQ: vceq${p}.i8 $vd, $vm, #0 */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGEfd, ARM_INS_VCGE: vcge${p}.f32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGEfq, ARM_INS_VCGE: vcge${p}.f32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGEsv16i8, ARM_INS_VCGE: vcge${p}.s8 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGEsv2i32, ARM_INS_VCGE: vcge${p}.s32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGEsv4i16, ARM_INS_VCGE: vcge${p}.s16 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGEsv4i32, ARM_INS_VCGE: vcge${p}.s32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGEsv8i16, ARM_INS_VCGE: vcge${p}.s16 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGEsv8i8, ARM_INS_VCGE: vcge${p}.s8 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGEuv16i8, ARM_INS_VCGE: vcge${p}.u8 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGEuv2i32, ARM_INS_VCGE: vcge${p}.u32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGEuv4i16, ARM_INS_VCGE: vcge${p}.u16 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGEuv4i32, ARM_INS_VCGE: vcge${p}.u32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGEuv8i16, ARM_INS_VCGE: vcge${p}.u16 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGEuv8i8, ARM_INS_VCGE: vcge${p}.u8 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGEzv16i8, ARM_INS_VCGE: vcge${p}.s8 $vd, $vm, #0 */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGEzv2f32, ARM_INS_VCGE: vcge${p}.f32 $vd, $vm, #0 */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGEzv2i32, ARM_INS_VCGE: vcge${p}.s32 $vd, $vm, #0 */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGEzv4f32, ARM_INS_VCGE: vcge${p}.f32 $vd, $vm, #0 */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGEzv4i16, ARM_INS_VCGE: vcge${p}.s16 $vd, $vm, #0 */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGEzv4i32, ARM_INS_VCGE: vcge${p}.s32 $vd, $vm, #0 */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGEzv8i16, ARM_INS_VCGE: vcge${p}.s16 $vd, $vm, #0 */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGEzv8i8, ARM_INS_VCGE: vcge${p}.s8 $vd, $vm, #0 */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGTfd, ARM_INS_VCGT: vcgt${p}.f32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGTfq, ARM_INS_VCGT: vcgt${p}.f32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGTsv16i8, ARM_INS_VCGT: vcgt${p}.s8 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGTsv2i32, ARM_INS_VCGT: vcgt${p}.s32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGTsv4i16, ARM_INS_VCGT: vcgt${p}.s16 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGTsv4i32, ARM_INS_VCGT: vcgt${p}.s32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGTsv8i16, ARM_INS_VCGT: vcgt${p}.s16 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGTsv8i8, ARM_INS_VCGT: vcgt${p}.s8 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGTuv16i8, ARM_INS_VCGT: vcgt${p}.u8 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGTuv2i32, ARM_INS_VCGT: vcgt${p}.u32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGTuv4i16, ARM_INS_VCGT: vcgt${p}.u16 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGTuv4i32, ARM_INS_VCGT: vcgt${p}.u32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGTuv8i16, ARM_INS_VCGT: vcgt${p}.u16 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGTuv8i8, ARM_INS_VCGT: vcgt${p}.u8 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGTzv16i8, ARM_INS_VCGT: vcgt${p}.s8 $vd, $vm, #0 */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGTzv2f32, ARM_INS_VCGT: vcgt${p}.f32 $vd, $vm, #0 */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGTzv2i32, ARM_INS_VCGT: vcgt${p}.s32 $vd, $vm, #0 */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGTzv4f32, ARM_INS_VCGT: vcgt${p}.f32 $vd, $vm, #0 */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGTzv4i16, ARM_INS_VCGT: vcgt${p}.s16 $vd, $vm, #0 */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGTzv4i32, ARM_INS_VCGT: vcgt${p}.s32 $vd, $vm, #0 */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGTzv8i16, ARM_INS_VCGT: vcgt${p}.s16 $vd, $vm, #0 */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCGTzv8i8, ARM_INS_VCGT: vcgt${p}.s8 $vd, $vm, #0 */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCLEzv16i8, ARM_INS_VCLE: vcle${p}.s8 $vd, $vm, #0 */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCLEzv2f32, ARM_INS_VCLE: vcle${p}.f32 $vd, $vm, #0 */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCLEzv2i32, ARM_INS_VCLE: vcle${p}.s32 $vd, $vm, #0 */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCLEzv4f32, ARM_INS_VCLE: vcle${p}.f32 $vd, $vm, #0 */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCLEzv4i16, ARM_INS_VCLE: vcle${p}.s16 $vd, $vm, #0 */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCLEzv4i32, ARM_INS_VCLE: vcle${p}.s32 $vd, $vm, #0 */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCLEzv8i16, ARM_INS_VCLE: vcle${p}.s16 $vd, $vm, #0 */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCLEzv8i8, ARM_INS_VCLE: vcle${p}.s8 $vd, $vm, #0 */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCLSv16i8, ARM_INS_VCLS: vcls${p}.s8 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCLSv2i32, ARM_INS_VCLS: vcls${p}.s32 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCLSv4i16, ARM_INS_VCLS: vcls${p}.s16 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCLSv4i32, ARM_INS_VCLS: vcls${p}.s32 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCLSv8i16, ARM_INS_VCLS: vcls${p}.s16 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCLSv8i8, ARM_INS_VCLS: vcls${p}.s8 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCLTzv16i8, ARM_INS_VCLT: vclt${p}.s8 $vd, $vm, #0 */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCLTzv2f32, ARM_INS_VCLT: vclt${p}.f32 $vd, $vm, #0 */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCLTzv2i32, ARM_INS_VCLT: vclt${p}.s32 $vd, $vm, #0 */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCLTzv4f32, ARM_INS_VCLT: vclt${p}.f32 $vd, $vm, #0 */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCLTzv4i16, ARM_INS_VCLT: vclt${p}.s16 $vd, $vm, #0 */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCLTzv4i32, ARM_INS_VCLT: vclt${p}.s32 $vd, $vm, #0 */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCLTzv8i16, ARM_INS_VCLT: vclt${p}.s16 $vd, $vm, #0 */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCLTzv8i8, ARM_INS_VCLT: vclt${p}.s8 $vd, $vm, #0 */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCLZv16i8, ARM_INS_VCLZ: vclz${p}.i8 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCLZv2i32, ARM_INS_VCLZ: vclz${p}.i32 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCLZv4i16, ARM_INS_VCLZ: vclz${p}.i16 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCLZv4i32, ARM_INS_VCLZ: vclz${p}.i32 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCLZv8i16, ARM_INS_VCLZ: vclz${p}.i16 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCLZv8i8, ARM_INS_VCLZ: vclz${p}.i8 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCMPD, ARM_INS_VCMP: vcmp${p}.f64 $dd, $dm */ |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCMPED, ARM_INS_VCMPE: vcmpe${p}.f64 $dd, $dm */ |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCMPES, ARM_INS_VCMPE: vcmpe${p}.f32 $sd, $sm */ |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCMPEZD, ARM_INS_VCMPE: vcmpe${p}.f64 $dd, #0 */ |
| { CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCMPEZS, ARM_INS_VCMPE: vcmpe${p}.f32 $sd, #0 */ |
| { CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCMPS, ARM_INS_VCMP: vcmp${p}.f32 $sd, $sm */ |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCMPZD, ARM_INS_VCMP: vcmp${p}.f64 $dd, #0 */ |
| { CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCMPZS, ARM_INS_VCMP: vcmp${p}.f32 $sd, #0 */ |
| { CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCNTd, ARM_INS_VCNT: vcnt${p}.8 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCNTq, ARM_INS_VCNT: vcnt${p}.8 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTANSD, ARM_INS_VCVTA: vcvta.s32.f32 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTANSQ, ARM_INS_VCVTA: vcvta.s32.f32 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTANUD, ARM_INS_VCVTA: vcvta.u32.f32 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTANUQ, ARM_INS_VCVTA: vcvta.u32.f32 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTASD, ARM_INS_VCVTA: vcvta.s32.f64 $sd, $dm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTASS, ARM_INS_VCVTA: vcvta.s32.f32 $sd, $sm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTAUD, ARM_INS_VCVTA: vcvta.u32.f64 $sd, $dm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTAUS, ARM_INS_VCVTA: vcvta.u32.f32 $sd, $sm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTBDH, ARM_INS_VCVTB: vcvtb${p}.f16.f64 $sd, $dm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTBHD, ARM_INS_VCVTB: vcvtb${p}.f64.f16 $dd, $sm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTBHS, ARM_INS_VCVTB: vcvtb${p}.f32.f16 $sd, $sm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTBSH, ARM_INS_VCVTB: vcvtb${p}.f16.f32 $sd, $sm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTDS, ARM_INS_VCVT: vcvt${p}.f64.f32 $dd, $sm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTMNSD, ARM_INS_VCVTM: vcvtm.s32.f32 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTMNSQ, ARM_INS_VCVTM: vcvtm.s32.f32 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTMNUD, ARM_INS_VCVTM: vcvtm.u32.f32 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTMNUQ, ARM_INS_VCVTM: vcvtm.u32.f32 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTMSD, ARM_INS_VCVTM: vcvtm.s32.f64 $sd, $dm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTMSS, ARM_INS_VCVTM: vcvtm.s32.f32 $sd, $sm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTMUD, ARM_INS_VCVTM: vcvtm.u32.f64 $sd, $dm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTMUS, ARM_INS_VCVTM: vcvtm.u32.f32 $sd, $sm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTNNSD, ARM_INS_VCVTN: vcvtn.s32.f32 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTNNSQ, ARM_INS_VCVTN: vcvtn.s32.f32 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTNNUD, ARM_INS_VCVTN: vcvtn.u32.f32 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTNNUQ, ARM_INS_VCVTN: vcvtn.u32.f32 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTNSD, ARM_INS_VCVTN: vcvtn.s32.f64 $sd, $dm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTNSS, ARM_INS_VCVTN: vcvtn.s32.f32 $sd, $sm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTNUD, ARM_INS_VCVTN: vcvtn.u32.f64 $sd, $dm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTNUS, ARM_INS_VCVTN: vcvtn.u32.f32 $sd, $sm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTPNSD, ARM_INS_VCVTP: vcvtp.s32.f32 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTPNSQ, ARM_INS_VCVTP: vcvtp.s32.f32 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTPNUD, ARM_INS_VCVTP: vcvtp.u32.f32 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTPNUQ, ARM_INS_VCVTP: vcvtp.u32.f32 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTPSD, ARM_INS_VCVTP: vcvtp.s32.f64 $sd, $dm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTPSS, ARM_INS_VCVTP: vcvtp.s32.f32 $sd, $sm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTPUD, ARM_INS_VCVTP: vcvtp.u32.f64 $sd, $dm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTPUS, ARM_INS_VCVTP: vcvtp.u32.f32 $sd, $sm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTSD, ARM_INS_VCVT: vcvt${p}.f32.f64 $sd, $dm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTTDH, ARM_INS_VCVTT: vcvtt${p}.f16.f64 $sd, $dm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTTHD, ARM_INS_VCVTT: vcvtt${p}.f64.f16 $dd, $sm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTTHS, ARM_INS_VCVTT: vcvtt${p}.f32.f16 $sd, $sm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTTSH, ARM_INS_VCVTT: vcvtt${p}.f16.f32 $sd, $sm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTf2h, ARM_INS_VCVT: vcvt${p}.f16.f32 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTf2sd, ARM_INS_VCVT: vcvt${p}.s32.f32 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTf2sq, ARM_INS_VCVT: vcvt${p}.s32.f32 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTf2ud, ARM_INS_VCVT: vcvt${p}.u32.f32 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTf2uq, ARM_INS_VCVT: vcvt${p}.u32.f32 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTf2xsd, ARM_INS_VCVT: vcvt${p}.s32.f32 $vd, $vm, $simm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTf2xsq, ARM_INS_VCVT: vcvt${p}.s32.f32 $vd, $vm, $simm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTf2xud, ARM_INS_VCVT: vcvt${p}.u32.f32 $vd, $vm, $simm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTf2xuq, ARM_INS_VCVT: vcvt${p}.u32.f32 $vd, $vm, $simm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTh2f, ARM_INS_VCVT: vcvt${p}.f32.f16 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTs2fd, ARM_INS_VCVT: vcvt${p}.f32.s32 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTs2fq, ARM_INS_VCVT: vcvt${p}.f32.s32 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTu2fd, ARM_INS_VCVT: vcvt${p}.f32.u32 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTu2fq, ARM_INS_VCVT: vcvt${p}.f32.u32 $vd, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTxs2fd, ARM_INS_VCVT: vcvt${p}.f32.s32 $vd, $vm, $simm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTxs2fq, ARM_INS_VCVT: vcvt${p}.f32.s32 $vd, $vm, $simm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTxu2fd, ARM_INS_VCVT: vcvt${p}.f32.u32 $vd, $vm, $simm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VCVTxu2fq, ARM_INS_VCVT: vcvt${p}.f32.u32 $vd, $vm, $simm */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VDIVD, ARM_INS_VDIV: vdiv${p}.f64 $dd, $dn, $dm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VDIVS, ARM_INS_VDIV: vdiv${p}.f32 $sd, $sn, $sm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VDUP16d, ARM_INS_VDUP: vdup${p}.16 $v, $r */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VDUP16q, ARM_INS_VDUP: vdup${p}.16 $v, $r */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VDUP32d, ARM_INS_VDUP: vdup${p}.32 $v, $r */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VDUP32q, ARM_INS_VDUP: vdup${p}.32 $v, $r */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VDUP8d, ARM_INS_VDUP: vdup${p}.8 $v, $r */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VDUP8q, ARM_INS_VDUP: vdup${p}.8 $v, $r */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VDUPLN16d, ARM_INS_VDUP: vdup${p}.16 $vd, $vm$lane */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VDUPLN16q, ARM_INS_VDUP: vdup${p}.16 $vd, $vm$lane */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VDUPLN32d, ARM_INS_VDUP: vdup${p}.32 $vd, $vm$lane */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VDUPLN32q, ARM_INS_VDUP: vdup${p}.32 $vd, $vm$lane */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VDUPLN8d, ARM_INS_VDUP: vdup${p}.8 $vd, $vm$lane */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VDUPLN8q, ARM_INS_VDUP: vdup${p}.8 $vd, $vm$lane */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VEORd, ARM_INS_VEOR: veor${p} $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VEORq, ARM_INS_VEOR: veor${p} $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VEXTd16, ARM_INS_VEXT: vext${p}.16 $vd, $vn, $vm, $index */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VEXTd32, ARM_INS_VEXT: vext${p}.32 $vd, $vn, $vm, $index */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VEXTd8, ARM_INS_VEXT: vext${p}.8 $vd, $vn, $vm, $index */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VEXTq16, ARM_INS_VEXT: vext${p}.16 $vd, $vn, $vm, $index */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VEXTq32, ARM_INS_VEXT: vext${p}.32 $vd, $vn, $vm, $index */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VEXTq64, ARM_INS_VEXT: vext${p}.64 $vd, $vn, $vm, $index */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VEXTq8, ARM_INS_VEXT: vext${p}.8 $vd, $vn, $vm, $index */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VFMAD, ARM_INS_VFMA: vfma${p}.f64 $dd, $dn, $dm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VFMAS, ARM_INS_VFMA: vfma${p}.f32 $sd, $sn, $sm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VFMAfd, ARM_INS_VFMA: vfma${p}.f32 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VFMAfq, ARM_INS_VFMA: vfma${p}.f32 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VFMSD, ARM_INS_VFMS: vfms${p}.f64 $dd, $dn, $dm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VFMSS, ARM_INS_VFMS: vfms${p}.f32 $sd, $sn, $sm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VFMSfd, ARM_INS_VFMS: vfms${p}.f32 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VFMSfq, ARM_INS_VFMS: vfms${p}.f32 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VFNMAD, ARM_INS_VFNMA: vfnma${p}.f64 $dd, $dn, $dm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VFNMAS, ARM_INS_VFNMA: vfnma${p}.f32 $sd, $sn, $sm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VFNMSD, ARM_INS_VFNMS: vfnms${p}.f64 $dd, $dn, $dm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VFNMSS, ARM_INS_VFNMS: vfnms${p}.f32 $sd, $sn, $sm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VGETLNi32, ARM_INS_VMOV: vmov${p}.32 $r, $v$lane */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VGETLNs16, ARM_INS_VMOV: vmov${p}.s16 $r, $v$lane */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VGETLNs8, ARM_INS_VMOV: vmov${p}.s8 $r, $v$lane */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VGETLNu16, ARM_INS_VMOV: vmov${p}.u16 $r, $v$lane */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VGETLNu8, ARM_INS_VMOV: vmov${p}.u8 $r, $v$lane */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VHADDsv16i8, ARM_INS_VHADD: vhadd${p}.s8 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VHADDsv2i32, ARM_INS_VHADD: vhadd${p}.s32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VHADDsv4i16, ARM_INS_VHADD: vhadd${p}.s16 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VHADDsv4i32, ARM_INS_VHADD: vhadd${p}.s32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VHADDsv8i16, ARM_INS_VHADD: vhadd${p}.s16 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VHADDsv8i8, ARM_INS_VHADD: vhadd${p}.s8 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VHADDuv16i8, ARM_INS_VHADD: vhadd${p}.u8 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VHADDuv2i32, ARM_INS_VHADD: vhadd${p}.u32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VHADDuv4i16, ARM_INS_VHADD: vhadd${p}.u16 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VHADDuv4i32, ARM_INS_VHADD: vhadd${p}.u32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VHADDuv8i16, ARM_INS_VHADD: vhadd${p}.u16 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VHADDuv8i8, ARM_INS_VHADD: vhadd${p}.u8 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VHSUBsv16i8, ARM_INS_VHSUB: vhsub${p}.s8 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VHSUBsv2i32, ARM_INS_VHSUB: vhsub${p}.s32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VHSUBsv4i16, ARM_INS_VHSUB: vhsub${p}.s16 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VHSUBsv4i32, ARM_INS_VHSUB: vhsub${p}.s32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VHSUBsv8i16, ARM_INS_VHSUB: vhsub${p}.s16 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VHSUBsv8i8, ARM_INS_VHSUB: vhsub${p}.s8 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VHSUBuv16i8, ARM_INS_VHSUB: vhsub${p}.u8 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VHSUBuv2i32, ARM_INS_VHSUB: vhsub${p}.u32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VHSUBuv4i16, ARM_INS_VHSUB: vhsub${p}.u16 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VHSUBuv4i32, ARM_INS_VHSUB: vhsub${p}.u32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VHSUBuv8i16, ARM_INS_VHSUB: vhsub${p}.u16 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VHSUBuv8i8, ARM_INS_VHSUB: vhsub${p}.u8 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1DUPd16, ARM_INS_VLD1: vld1${p}.16 $vd, $rn */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1DUPd16wb_fixed, ARM_INS_VLD1: vld1${p}.16 $vd, $rn! */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1DUPd16wb_register, ARM_INS_VLD1: vld1${p}.16 $vd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1DUPd32, ARM_INS_VLD1: vld1${p}.32 $vd, $rn */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1DUPd32wb_fixed, ARM_INS_VLD1: vld1${p}.32 $vd, $rn! */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1DUPd32wb_register, ARM_INS_VLD1: vld1${p}.32 $vd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1DUPd8, ARM_INS_VLD1: vld1${p}.8 $vd, $rn */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1DUPd8wb_fixed, ARM_INS_VLD1: vld1${p}.8 $vd, $rn! */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1DUPd8wb_register, ARM_INS_VLD1: vld1${p}.8 $vd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1DUPq16, ARM_INS_VLD1: vld1${p}.16 $vd, $rn */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1DUPq16wb_fixed, ARM_INS_VLD1: vld1${p}.16 $vd, $rn! */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1DUPq16wb_register, ARM_INS_VLD1: vld1${p}.16 $vd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1DUPq32, ARM_INS_VLD1: vld1${p}.32 $vd, $rn */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1DUPq32wb_fixed, ARM_INS_VLD1: vld1${p}.32 $vd, $rn! */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1DUPq32wb_register, ARM_INS_VLD1: vld1${p}.32 $vd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1DUPq8, ARM_INS_VLD1: vld1${p}.8 $vd, $rn */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1DUPq8wb_fixed, ARM_INS_VLD1: vld1${p}.8 $vd, $rn! */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1DUPq8wb_register, ARM_INS_VLD1: vld1${p}.8 $vd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1LNd16, ARM_INS_VLD1: vld1${p}.16 \{$vd[$lane]\}, $rn */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1LNd16_UPD, ARM_INS_VLD1: vld1${p}.16 \{$vd[$lane]\}, $rn$rm */ |
| { CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_VLD1LNd32, ARM_INS_VLD1: vld1${p}.32 \{$vd[$lane]\}, $rn */ |
| { CS_AC_READ | CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_VLD1LNd32_UPD, ARM_INS_VLD1: vld1${p}.32 \{$vd[$lane]\}, $rn$rm */ |
| { CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_VLD1LNd8, ARM_INS_VLD1: vld1${p}.8 \{$vd[$lane]\}, $rn */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1LNd8_UPD, ARM_INS_VLD1: vld1${p}.8 \{$vd[$lane]\}, $rn$rm */ |
| { CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_VLD1d16, ARM_INS_VLD1: vld1${p}.16 $vd, $rn */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1d16Q, ARM_INS_VLD1: vld1${p}.16 $vd, $rn */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1d16Qwb_fixed, ARM_INS_VLD1: vld1${p}.16 $vd, $rn! */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1d16Qwb_register, ARM_INS_VLD1: vld1${p}.16 $vd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1d16T, ARM_INS_VLD1: vld1${p}.16 $vd, $rn */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1d16Twb_fixed, ARM_INS_VLD1: vld1${p}.16 $vd, $rn! */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1d16Twb_register, ARM_INS_VLD1: vld1${p}.16 $vd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1d16wb_fixed, ARM_INS_VLD1: vld1${p}.16 $vd, $rn! */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1d16wb_register, ARM_INS_VLD1: vld1${p}.16 $vd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1d32, ARM_INS_VLD1: vld1${p}.32 $vd, $rn */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1d32Q, ARM_INS_VLD1: vld1${p}.32 $vd, $rn */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1d32Qwb_fixed, ARM_INS_VLD1: vld1${p}.32 $vd, $rn! */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1d32Qwb_register, ARM_INS_VLD1: vld1${p}.32 $vd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1d32T, ARM_INS_VLD1: vld1${p}.32 $vd, $rn */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1d32Twb_fixed, ARM_INS_VLD1: vld1${p}.32 $vd, $rn! */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1d32Twb_register, ARM_INS_VLD1: vld1${p}.32 $vd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1d32wb_fixed, ARM_INS_VLD1: vld1${p}.32 $vd, $rn! */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1d32wb_register, ARM_INS_VLD1: vld1${p}.32 $vd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1d64, ARM_INS_VLD1: vld1${p}.64 $vd, $rn */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1d64Q, ARM_INS_VLD1: vld1${p}.64 $vd, $rn */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1d64Qwb_fixed, ARM_INS_VLD1: vld1${p}.64 $vd, $rn! */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1d64Qwb_register, ARM_INS_VLD1: vld1${p}.64 $vd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1d64T, ARM_INS_VLD1: vld1${p}.64 $vd, $rn */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1d64Twb_fixed, ARM_INS_VLD1: vld1${p}.64 $vd, $rn! */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1d64Twb_register, ARM_INS_VLD1: vld1${p}.64 $vd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1d64wb_fixed, ARM_INS_VLD1: vld1${p}.64 $vd, $rn! */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1d64wb_register, ARM_INS_VLD1: vld1${p}.64 $vd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1d8, ARM_INS_VLD1: vld1${p}.8 $vd, $rn */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1d8Q, ARM_INS_VLD1: vld1${p}.8 $vd, $rn */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1d8Qwb_fixed, ARM_INS_VLD1: vld1${p}.8 $vd, $rn! */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1d8Qwb_register, ARM_INS_VLD1: vld1${p}.8 $vd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1d8T, ARM_INS_VLD1: vld1${p}.8 $vd, $rn */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1d8Twb_fixed, ARM_INS_VLD1: vld1${p}.8 $vd, $rn! */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1d8Twb_register, ARM_INS_VLD1: vld1${p}.8 $vd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1d8wb_fixed, ARM_INS_VLD1: vld1${p}.8 $vd, $rn! */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1d8wb_register, ARM_INS_VLD1: vld1${p}.8 $vd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1q16, ARM_INS_VLD1: vld1${p}.16 $vd, $rn */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1q16wb_fixed, ARM_INS_VLD1: vld1${p}.16 $vd, $rn! */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1q16wb_register, ARM_INS_VLD1: vld1${p}.16 $vd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1q32, ARM_INS_VLD1: vld1${p}.32 $vd, $rn */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1q32wb_fixed, ARM_INS_VLD1: vld1${p}.32 $vd, $rn! */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1q32wb_register, ARM_INS_VLD1: vld1${p}.32 $vd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1q64, ARM_INS_VLD1: vld1${p}.64 $vd, $rn */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1q64wb_fixed, ARM_INS_VLD1: vld1${p}.64 $vd, $rn! */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1q64wb_register, ARM_INS_VLD1: vld1${p}.64 $vd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1q8, ARM_INS_VLD1: vld1${p}.8 $vd, $rn */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1q8wb_fixed, ARM_INS_VLD1: vld1${p}.8 $vd, $rn! */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD1q8wb_register, ARM_INS_VLD1: vld1${p}.8 $vd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2DUPd16, ARM_INS_VLD2: vld2${p}.16 $vd, $rn */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2DUPd16wb_fixed, ARM_INS_VLD2: vld2${p}.16 $vd, $rn! */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2DUPd16wb_register, ARM_INS_VLD2: vld2${p}.16 $vd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2DUPd16x2, ARM_INS_VLD2: vld2${p}.16 $vd, $rn */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2DUPd16x2wb_fixed, ARM_INS_VLD2: vld2${p}.16 $vd, $rn! */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2DUPd16x2wb_register, ARM_INS_VLD2: vld2${p}.16 $vd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2DUPd32, ARM_INS_VLD2: vld2${p}.32 $vd, $rn */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2DUPd32wb_fixed, ARM_INS_VLD2: vld2${p}.32 $vd, $rn! */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2DUPd32wb_register, ARM_INS_VLD2: vld2${p}.32 $vd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2DUPd32x2, ARM_INS_VLD2: vld2${p}.32 $vd, $rn */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2DUPd32x2wb_fixed, ARM_INS_VLD2: vld2${p}.32 $vd, $rn! */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2DUPd32x2wb_register, ARM_INS_VLD2: vld2${p}.32 $vd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2DUPd8, ARM_INS_VLD2: vld2${p}.8 $vd, $rn */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2DUPd8wb_fixed, ARM_INS_VLD2: vld2${p}.8 $vd, $rn! */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2DUPd8wb_register, ARM_INS_VLD2: vld2${p}.8 $vd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2DUPd8x2, ARM_INS_VLD2: vld2${p}.8 $vd, $rn */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2DUPd8x2wb_fixed, ARM_INS_VLD2: vld2${p}.8 $vd, $rn! */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2DUPd8x2wb_register, ARM_INS_VLD2: vld2${p}.8 $vd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2LNd16, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane], $dst2[$lane]\}, $rn */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2LNd16_UPD, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane], $dst2[$lane]\}, $rn$rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_VLD2LNd32, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane], $dst2[$lane]\}, $rn */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2LNd32_UPD, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane], $dst2[$lane]\}, $rn$rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_VLD2LNd8, ARM_INS_VLD2: vld2${p}.8 \{$vd[$lane], $dst2[$lane]\}, $rn */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2LNd8_UPD, ARM_INS_VLD2: vld2${p}.8 \{$vd[$lane], $dst2[$lane]\}, $rn$rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_VLD2LNq16, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane], $dst2[$lane]\}, $rn */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2LNq16_UPD, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane], $dst2[$lane]\}, $rn$rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_VLD2LNq32, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane], $dst2[$lane]\}, $rn */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2LNq32_UPD, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane], $dst2[$lane]\}, $rn$rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_VLD2b16, ARM_INS_VLD2: vld2${p}.16 $vd, $rn */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2b16wb_fixed, ARM_INS_VLD2: vld2${p}.16 $vd, $rn! */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2b16wb_register, ARM_INS_VLD2: vld2${p}.16 $vd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2b32, ARM_INS_VLD2: vld2${p}.32 $vd, $rn */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2b32wb_fixed, ARM_INS_VLD2: vld2${p}.32 $vd, $rn! */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2b32wb_register, ARM_INS_VLD2: vld2${p}.32 $vd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2b8, ARM_INS_VLD2: vld2${p}.8 $vd, $rn */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2b8wb_fixed, ARM_INS_VLD2: vld2${p}.8 $vd, $rn! */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2b8wb_register, ARM_INS_VLD2: vld2${p}.8 $vd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2d16, ARM_INS_VLD2: vld2${p}.16 $vd, $rn */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2d16wb_fixed, ARM_INS_VLD2: vld2${p}.16 $vd, $rn! */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2d16wb_register, ARM_INS_VLD2: vld2${p}.16 $vd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2d32, ARM_INS_VLD2: vld2${p}.32 $vd, $rn */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2d32wb_fixed, ARM_INS_VLD2: vld2${p}.32 $vd, $rn! */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2d32wb_register, ARM_INS_VLD2: vld2${p}.32 $vd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2d8, ARM_INS_VLD2: vld2${p}.8 $vd, $rn */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2d8wb_fixed, ARM_INS_VLD2: vld2${p}.8 $vd, $rn! */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2d8wb_register, ARM_INS_VLD2: vld2${p}.8 $vd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2q16, ARM_INS_VLD2: vld2${p}.16 $vd, $rn */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2q16wb_fixed, ARM_INS_VLD2: vld2${p}.16 $vd, $rn! */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2q16wb_register, ARM_INS_VLD2: vld2${p}.16 $vd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2q32, ARM_INS_VLD2: vld2${p}.32 $vd, $rn */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2q32wb_fixed, ARM_INS_VLD2: vld2${p}.32 $vd, $rn! */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2q32wb_register, ARM_INS_VLD2: vld2${p}.32 $vd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2q8, ARM_INS_VLD2: vld2${p}.8 $vd, $rn */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2q8wb_fixed, ARM_INS_VLD2: vld2${p}.8 $vd, $rn! */ |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD2q8wb_register, ARM_INS_VLD2: vld2${p}.8 $vd, $rn, $rm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD3DUPd16, ARM_INS_VLD3: vld3${p}.16 \{$vd[], $dst2[], $dst3[]\}, $rn */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD3DUPd16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd[], $dst2[], $dst3[]\}, $rn$rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD3DUPd32, ARM_INS_VLD3: vld3${p}.32 \{$vd[], $dst2[], $dst3[]\}, $rn */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD3DUPd32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd[], $dst2[], $dst3[]\}, $rn$rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD3DUPd8, ARM_INS_VLD3: vld3${p}.8 \{$vd[], $dst2[], $dst3[]\}, $rn */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD3DUPd8_UPD, ARM_INS_VLD3: vld3${p}.8 \{$vd[], $dst2[], $dst3[]\}, $rn$rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD3DUPq16, ARM_INS_VLD3: vld3${p}.16 \{$vd[], $dst2[], $dst3[]\}, $rn */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD3DUPq16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd[], $dst2[], $dst3[]\}, $rn$rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD3DUPq32, ARM_INS_VLD3: vld3${p}.32 \{$vd[], $dst2[], $dst3[]\}, $rn */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD3DUPq32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd[], $dst2[], $dst3[]\}, $rn$rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD3DUPq8, ARM_INS_VLD3: vld3${p}.8 \{$vd[], $dst2[], $dst3[]\}, $rn */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD3DUPq8_UPD, ARM_INS_VLD3: vld3${p}.8 \{$vd[], $dst2[], $dst3[]\}, $rn$rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD3LNd16, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD3LNd16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn$rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_VLD3LNd32, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD3LNd32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn$rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_VLD3LNd8, ARM_INS_VLD3: vld3${p}.8 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD3LNd8_UPD, ARM_INS_VLD3: vld3${p}.8 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn$rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_VLD3LNq16, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD3LNq16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn$rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_VLD3LNq32, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD3LNq32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn$rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_VLD3d16, ARM_INS_VLD3: vld3${p}.16 \{$vd, $dst2, $dst3\}, $rn */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD3d16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd, $dst2, $dst3\}, $rn$rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_VLD3d32, ARM_INS_VLD3: vld3${p}.32 \{$vd, $dst2, $dst3\}, $rn */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD3d32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd, $dst2, $dst3\}, $rn$rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_VLD3d8, ARM_INS_VLD3: vld3${p}.8 \{$vd, $dst2, $dst3\}, $rn */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD3d8_UPD, ARM_INS_VLD3: vld3${p}.8 \{$vd, $dst2, $dst3\}, $rn$rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_VLD3q16, ARM_INS_VLD3: vld3${p}.16 \{$vd, $dst2, $dst3\}, $rn */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD3q16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd, $dst2, $dst3\}, $rn$rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_VLD3q32, ARM_INS_VLD3: vld3${p}.32 \{$vd, $dst2, $dst3\}, $rn */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD3q32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd, $dst2, $dst3\}, $rn$rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_VLD3q8, ARM_INS_VLD3: vld3${p}.8 \{$vd, $dst2, $dst3\}, $rn */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD3q8_UPD, ARM_INS_VLD3: vld3${p}.8 \{$vd, $dst2, $dst3\}, $rn$rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_VLD4DUPd16, ARM_INS_VLD4: vld4${p}.16 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD4DUPd16_UPD, ARM_INS_VLD4: vld4${p}.16 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn$rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD4DUPd32, ARM_INS_VLD4: vld4${p}.32 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD4DUPd32_UPD, ARM_INS_VLD4: vld4${p}.32 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn$rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD4DUPd8, ARM_INS_VLD4: vld4${p}.8 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD4DUPd8_UPD, ARM_INS_VLD4: vld4${p}.8 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn$rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD4DUPq16, ARM_INS_VLD4: vld4${p}.16 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD4DUPq16_UPD, ARM_INS_VLD4: vld4${p}.16 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn$rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD4DUPq32, ARM_INS_VLD4: vld4${p}.32 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD4DUPq32_UPD, ARM_INS_VLD4: vld4${p}.32 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn$rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD4DUPq8, ARM_INS_VLD4: vld4${p}.8 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD4DUPq8_UPD, ARM_INS_VLD4: vld4${p}.8 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn$rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD4LNd16, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD4LNd16_UPD, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn$rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_VLD4LNd32, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD4LNd32_UPD, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn$rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_VLD4LNd8, ARM_INS_VLD4: vld4${p}.8 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD4LNd8_UPD, ARM_INS_VLD4: vld4${p}.8 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn$rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_VLD4LNq16, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD4LNq16_UPD, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn$rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_VLD4LNq32, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD4LNq32_UPD, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn$rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_VLD4d16, ARM_INS_VLD4: vld4${p}.16 \{$vd, $dst2, $dst3, $dst4\}, $rn */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD4d16_UPD, ARM_INS_VLD4: vld4${p}.16 \{$vd, $dst2, $dst3, $dst4\}, $rn$rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_VLD4d32, ARM_INS_VLD4: vld4${p}.32 \{$vd, $dst2, $dst3, $dst4\}, $rn */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD4d32_UPD, ARM_INS_VLD4: vld4${p}.32 \{$vd, $dst2, $dst3, $dst4\}, $rn$rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_VLD4d8, ARM_INS_VLD4: vld4${p}.8 \{$vd, $dst2, $dst3, $dst4\}, $rn */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD4d8_UPD, ARM_INS_VLD4: vld4${p}.8 \{$vd, $dst2, $dst3, $dst4\}, $rn$rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_VLD4q16, ARM_INS_VLD4: vld4${p}.16 \{$vd, $dst2, $dst3, $dst4\}, $rn */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD4q16_UPD, ARM_INS_VLD4: vld4${p}.16 \{$vd, $dst2, $dst3, $dst4\}, $rn$rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_VLD4q32, ARM_INS_VLD4: vld4${p}.32 \{$vd, $dst2, $dst3, $dst4\}, $rn */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD4q32_UPD, ARM_INS_VLD4: vld4${p}.32 \{$vd, $dst2, $dst3, $dst4\}, $rn$rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_VLD4q8, ARM_INS_VLD4: vld4${p}.8 \{$vd, $dst2, $dst3, $dst4\}, $rn */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLD4q8_UPD, ARM_INS_VLD4: vld4${p}.8 \{$vd, $dst2, $dst3, $dst4\}, $rn$rm */ |
| { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_VLDMDDB_UPD, ARM_INS_VLDMDB: vldmdb${p} $rn!, $regs */ |
| { CS_AC_READ | CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_VLDMDIA, ARM_INS_VLDMIA: vldmia${p} $rn, $regs */ |
| { CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLDMDIA_UPD, ARM_INS_VLDMIA: vldmia${p} $rn!, $regs */ |
| { CS_AC_READ | CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_VLDMSDB_UPD, ARM_INS_VLDMDB: vldmdb${p} $rn!, $regs */ |
| { CS_AC_READ | CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_VLDMSIA, ARM_INS_VLDMIA: vldmia${p} $rn, $regs */ |
| { CS_AC_READ, 0 } |
| }, |
| { /* ARM_VLDMSIA_UPD, ARM_INS_VLDMIA: vldmia${p} $rn!, $regs */ |
| { CS_AC_READ | CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_VLDRD, ARM_INS_VLDR: vldr${p} $dd, $addr */ |
| { CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_VLDRS, ARM_INS_VLDR: vldr${p} $sd, $addr */ |
| { CS_AC_WRITE, 0 } |
| }, |
| { /* ARM_VMAXNMD, ARM_INS_VMAXNM: vmaxnm.f64 $dd, $dn, $dm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMAXNMND, ARM_INS_VMAXNM: vmaxnm.f32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMAXNMNQ, ARM_INS_VMAXNM: vmaxnm.f32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMAXNMS, ARM_INS_VMAXNM: vmaxnm.f32 $sd, $sn, $sm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMAXfd, ARM_INS_VMAX: vmax${p}.f32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMAXfq, ARM_INS_VMAX: vmax${p}.f32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMAXsv16i8, ARM_INS_VMAX: vmax${p}.s8 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMAXsv2i32, ARM_INS_VMAX: vmax${p}.s32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMAXsv4i16, ARM_INS_VMAX: vmax${p}.s16 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMAXsv4i32, ARM_INS_VMAX: vmax${p}.s32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMAXsv8i16, ARM_INS_VMAX: vmax${p}.s16 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMAXsv8i8, ARM_INS_VMAX: vmax${p}.s8 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMAXuv16i8, ARM_INS_VMAX: vmax${p}.u8 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMAXuv2i32, ARM_INS_VMAX: vmax${p}.u32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMAXuv4i16, ARM_INS_VMAX: vmax${p}.u16 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMAXuv4i32, ARM_INS_VMAX: vmax${p}.u32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMAXuv8i16, ARM_INS_VMAX: vmax${p}.u16 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMAXuv8i8, ARM_INS_VMAX: vmax${p}.u8 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMINNMD, ARM_INS_VMINNM: vminnm.f64 $dd, $dn, $dm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMINNMND, ARM_INS_VMINNM: vminnm.f32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMINNMNQ, ARM_INS_VMINNM: vminnm.f32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMINNMS, ARM_INS_VMINNM: vminnm.f32 $sd, $sn, $sm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMINfd, ARM_INS_VMIN: vmin${p}.f32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMINfq, ARM_INS_VMIN: vmin${p}.f32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMINsv16i8, ARM_INS_VMIN: vmin${p}.s8 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMINsv2i32, ARM_INS_VMIN: vmin${p}.s32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMINsv4i16, ARM_INS_VMIN: vmin${p}.s16 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMINsv4i32, ARM_INS_VMIN: vmin${p}.s32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMINsv8i16, ARM_INS_VMIN: vmin${p}.s16 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMINsv8i8, ARM_INS_VMIN: vmin${p}.s8 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMINuv16i8, ARM_INS_VMIN: vmin${p}.u8 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMINuv2i32, ARM_INS_VMIN: vmin${p}.u32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMINuv4i16, ARM_INS_VMIN: vmin${p}.u16 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMINuv4i32, ARM_INS_VMIN: vmin${p}.u32 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMINuv8i16, ARM_INS_VMIN: vmin${p}.u16 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMINuv8i8, ARM_INS_VMIN: vmin${p}.u8 $vd, $vn, $vm */ |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMLAD, ARM_INS_VMLA: vmla${p}.f64 $dd, $dn, $dm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMLALslsv2i32, ARM_INS_VMLAL: vmlal${p}.s32 $vd, $vn, $vm$lane */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMLALslsv4i16, ARM_INS_VMLAL: vmlal${p}.s16 $vd, $vn, $vm$lane */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMLALsluv2i32, ARM_INS_VMLAL: vmlal${p}.u32 $vd, $vn, $vm$lane */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMLALsluv4i16, ARM_INS_VMLAL: vmlal${p}.u16 $vd, $vn, $vm$lane */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMLALsv2i64, ARM_INS_VMLAL: vmlal${p}.s32 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMLALsv4i32, ARM_INS_VMLAL: vmlal${p}.s16 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMLALsv8i16, ARM_INS_VMLAL: vmlal${p}.s8 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMLALuv2i64, ARM_INS_VMLAL: vmlal${p}.u32 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMLALuv4i32, ARM_INS_VMLAL: vmlal${p}.u16 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMLALuv8i16, ARM_INS_VMLAL: vmlal${p}.u8 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMLAS, ARM_INS_VMLA: vmla${p}.f32 $sd, $sn, $sm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMLAfd, ARM_INS_VMLA: vmla${p}.f32 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMLAfq, ARM_INS_VMLA: vmla${p}.f32 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMLAslfd, ARM_INS_VMLA: vmla${p}.f32 $vd, $vn, $vm$lane */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMLAslfq, ARM_INS_VMLA: vmla${p}.f32 $vd, $vn, $vm$lane */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMLAslv2i32, ARM_INS_VMLA: vmla${p}.i32 $vd, $vn, $vm$lane */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMLAslv4i16, ARM_INS_VMLA: vmla${p}.i16 $vd, $vn, $vm$lane */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMLAslv4i32, ARM_INS_VMLA: vmla${p}.i32 $vd, $vn, $vm$lane */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMLAslv8i16, ARM_INS_VMLA: vmla${p}.i16 $vd, $vn, $vm$lane */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMLAv16i8, ARM_INS_VMLA: vmla${p}.i8 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMLAv2i32, ARM_INS_VMLA: vmla${p}.i32 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMLAv4i16, ARM_INS_VMLA: vmla${p}.i16 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMLAv4i32, ARM_INS_VMLA: vmla${p}.i32 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMLAv8i16, ARM_INS_VMLA: vmla${p}.i16 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMLAv8i8, ARM_INS_VMLA: vmla${p}.i8 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMLSD, ARM_INS_VMLS: vmls${p}.f64 $dd, $dn, $dm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMLSLslsv2i32, ARM_INS_VMLSL: vmlsl${p}.s32 $vd, $vn, $vm$lane */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMLSLslsv4i16, ARM_INS_VMLSL: vmlsl${p}.s16 $vd, $vn, $vm$lane */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMLSLsluv2i32, ARM_INS_VMLSL: vmlsl${p}.u32 $vd, $vn, $vm$lane */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMLSLsluv4i16, ARM_INS_VMLSL: vmlsl${p}.u16 $vd, $vn, $vm$lane */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMLSLsv2i64, ARM_INS_VMLSL: vmlsl${p}.s32 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMLSLsv4i32, ARM_INS_VMLSL: vmlsl${p}.s16 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMLSLsv8i16, ARM_INS_VMLSL: vmlsl${p}.s8 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* ARM_VMLSLuv2i64, ARM_INS_VMLSL: vmlsl${p}.u32 $vd, $vn, $vm */ |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ |
