| /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| |* *| |
| |*Target Instruction Enum Values *| |
| |* *| |
| |* Automatically generated file, do not edit! *| |
| |* *| |
| \*===----------------------------------------------------------------------===*/ |
| |
| /* Capstone Disassembly Engine, http://www.capstone-engine.org */ |
| /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ |
| |
| |
| #ifdef GET_INSTRINFO_ENUM |
| #undef GET_INSTRINFO_ENUM |
| |
| enum { |
| ARM_PHI = 0, |
| ARM_INLINEASM = 1, |
| ARM_CFI_INSTRUCTION = 2, |
| ARM_EH_LABEL = 3, |
| ARM_GC_LABEL = 4, |
| ARM_KILL = 5, |
| ARM_EXTRACT_SUBREG = 6, |
| ARM_INSERT_SUBREG = 7, |
| ARM_IMPLICIT_DEF = 8, |
| ARM_SUBREG_TO_REG = 9, |
| ARM_COPY_TO_REGCLASS = 10, |
| ARM_DBG_VALUE = 11, |
| ARM_REG_SEQUENCE = 12, |
| ARM_COPY = 13, |
| ARM_BUNDLE = 14, |
| ARM_LIFETIME_START = 15, |
| ARM_LIFETIME_END = 16, |
| ARM_STACKMAP = 17, |
| ARM_PATCHPOINT = 18, |
| ARM_LOAD_STACK_GUARD = 19, |
| ARM_STATEPOINT = 20, |
| ARM_FRAME_ALLOC = 21, |
| ARM_ABS = 22, |
| ARM_ADCri = 23, |
| ARM_ADCrr = 24, |
| ARM_ADCrsi = 25, |
| ARM_ADCrsr = 26, |
| ARM_ADDSri = 27, |
| ARM_ADDSrr = 28, |
| ARM_ADDSrsi = 29, |
| ARM_ADDSrsr = 30, |
| ARM_ADDri = 31, |
| ARM_ADDrr = 32, |
| ARM_ADDrsi = 33, |
| ARM_ADDrsr = 34, |
| ARM_ADJCALLSTACKDOWN = 35, |
| ARM_ADJCALLSTACKUP = 36, |
| ARM_ADR = 37, |
| ARM_AESD = 38, |
| ARM_AESE = 39, |
| ARM_AESIMC = 40, |
| ARM_AESMC = 41, |
| ARM_ANDri = 42, |
| ARM_ANDrr = 43, |
| ARM_ANDrsi = 44, |
| ARM_ANDrsr = 45, |
| ARM_ASRi = 46, |
| ARM_ASRr = 47, |
| ARM_B = 48, |
| ARM_BCCZi64 = 49, |
| ARM_BCCi64 = 50, |
| ARM_BFC = 51, |
| ARM_BFI = 52, |
| ARM_BICri = 53, |
| ARM_BICrr = 54, |
| ARM_BICrsi = 55, |
| ARM_BICrsr = 56, |
| ARM_BKPT = 57, |
| ARM_BL = 58, |
| ARM_BLX = 59, |
| ARM_BLX_pred = 60, |
| ARM_BLXi = 61, |
| ARM_BL_pred = 62, |
| ARM_BMOVPCB_CALL = 63, |
| ARM_BMOVPCRX_CALL = 64, |
| ARM_BR_JTadd = 65, |
| ARM_BR_JTm = 66, |
| ARM_BR_JTr = 67, |
| ARM_BX = 68, |
| ARM_BXJ = 69, |
| ARM_BX_CALL = 70, |
| ARM_BX_RET = 71, |
| ARM_BX_pred = 72, |
| ARM_Bcc = 73, |
| ARM_CDP = 74, |
| ARM_CDP2 = 75, |
| ARM_CLREX = 76, |
| ARM_CLZ = 77, |
| ARM_CMNri = 78, |
| ARM_CMNzrr = 79, |
| ARM_CMNzrsi = 80, |
| ARM_CMNzrsr = 81, |
| ARM_CMPri = 82, |
| ARM_CMPrr = 83, |
| ARM_CMPrsi = 84, |
| ARM_CMPrsr = 85, |
| ARM_CONSTPOOL_ENTRY = 86, |
| ARM_COPY_STRUCT_BYVAL_I32 = 87, |
| ARM_CPS1p = 88, |
| ARM_CPS2p = 89, |
| ARM_CPS3p = 90, |
| ARM_CRC32B = 91, |
| ARM_CRC32CB = 92, |
| ARM_CRC32CH = 93, |
| ARM_CRC32CW = 94, |
| ARM_CRC32H = 95, |
| ARM_CRC32W = 96, |
| ARM_DBG = 97, |
| ARM_DMB = 98, |
| ARM_DSB = 99, |
| ARM_EORri = 100, |
| ARM_EORrr = 101, |
| ARM_EORrsi = 102, |
| ARM_EORrsr = 103, |
| ARM_ERET = 104, |
| ARM_FCONSTD = 105, |
| ARM_FCONSTS = 106, |
| ARM_FLDMXDB_UPD = 107, |
| ARM_FLDMXIA = 108, |
| ARM_FLDMXIA_UPD = 109, |
| ARM_FMSTAT = 110, |
| ARM_FSTMXDB_UPD = 111, |
| ARM_FSTMXIA = 112, |
| ARM_FSTMXIA_UPD = 113, |
| ARM_HINT = 114, |
| ARM_HLT = 115, |
| ARM_HVC = 116, |
| ARM_ISB = 117, |
| ARM_ITasm = 118, |
| ARM_Int_eh_sjlj_dispatchsetup = 119, |
| ARM_Int_eh_sjlj_longjmp = 120, |
| ARM_Int_eh_sjlj_setjmp = 121, |
| ARM_Int_eh_sjlj_setjmp_nofp = 122, |
| ARM_LDA = 123, |
| ARM_LDAB = 124, |
| ARM_LDAEX = 125, |
| ARM_LDAEXB = 126, |
| ARM_LDAEXD = 127, |
| ARM_LDAEXH = 128, |
| ARM_LDAH = 129, |
| ARM_LDC2L_OFFSET = 130, |
| ARM_LDC2L_OPTION = 131, |
| ARM_LDC2L_POST = 132, |
| ARM_LDC2L_PRE = 133, |
| ARM_LDC2_OFFSET = 134, |
| ARM_LDC2_OPTION = 135, |
| ARM_LDC2_POST = 136, |
| ARM_LDC2_PRE = 137, |
| ARM_LDCL_OFFSET = 138, |
| ARM_LDCL_OPTION = 139, |
| ARM_LDCL_POST = 140, |
| ARM_LDCL_PRE = 141, |
| ARM_LDC_OFFSET = 142, |
| ARM_LDC_OPTION = 143, |
| ARM_LDC_POST = 144, |
| ARM_LDC_PRE = 145, |
| ARM_LDMDA = 146, |
| ARM_LDMDA_UPD = 147, |
| ARM_LDMDB = 148, |
| ARM_LDMDB_UPD = 149, |
| ARM_LDMIA = 150, |
| ARM_LDMIA_RET = 151, |
| ARM_LDMIA_UPD = 152, |
| ARM_LDMIB = 153, |
| ARM_LDMIB_UPD = 154, |
| ARM_LDRBT_POST = 155, |
| ARM_LDRBT_POST_IMM = 156, |
| ARM_LDRBT_POST_REG = 157, |
| ARM_LDRB_POST_IMM = 158, |
| ARM_LDRB_POST_REG = 159, |
| ARM_LDRB_PRE_IMM = 160, |
| ARM_LDRB_PRE_REG = 161, |
| ARM_LDRBi12 = 162, |
| ARM_LDRBrs = 163, |
| ARM_LDRD = 164, |
| ARM_LDRD_POST = 165, |
| ARM_LDRD_PRE = 166, |
| ARM_LDREX = 167, |
| ARM_LDREXB = 168, |
| ARM_LDREXD = 169, |
| ARM_LDREXH = 170, |
| ARM_LDRH = 171, |
| ARM_LDRHTi = 172, |
| ARM_LDRHTr = 173, |
| ARM_LDRH_POST = 174, |
| ARM_LDRH_PRE = 175, |
| ARM_LDRLIT_ga_abs = 176, |
| ARM_LDRLIT_ga_pcrel = 177, |
| ARM_LDRLIT_ga_pcrel_ldr = 178, |
| ARM_LDRSB = 179, |
| ARM_LDRSBTi = 180, |
| ARM_LDRSBTr = 181, |
| ARM_LDRSB_POST = 182, |
| ARM_LDRSB_PRE = 183, |
| ARM_LDRSH = 184, |
| ARM_LDRSHTi = 185, |
| ARM_LDRSHTr = 186, |
| ARM_LDRSH_POST = 187, |
| ARM_LDRSH_PRE = 188, |
| ARM_LDRT_POST = 189, |
| ARM_LDRT_POST_IMM = 190, |
| ARM_LDRT_POST_REG = 191, |
| ARM_LDR_POST_IMM = 192, |
| ARM_LDR_POST_REG = 193, |
| ARM_LDR_PRE_IMM = 194, |
| ARM_LDR_PRE_REG = 195, |
| ARM_LDRcp = 196, |
| ARM_LDRi12 = 197, |
| ARM_LDRrs = 198, |
| ARM_LEApcrel = 199, |
| ARM_LEApcrelJT = 200, |
| ARM_LSLi = 201, |
| ARM_LSLr = 202, |
| ARM_LSRi = 203, |
| ARM_LSRr = 204, |
| ARM_MCR = 205, |
| ARM_MCR2 = 206, |
| ARM_MCRR = 207, |
| ARM_MCRR2 = 208, |
| ARM_MLA = 209, |
| ARM_MLAv5 = 210, |
| ARM_MLS = 211, |
| ARM_MOVCCi = 212, |
| ARM_MOVCCi16 = 213, |
| ARM_MOVCCi32imm = 214, |
| ARM_MOVCCr = 215, |
| ARM_MOVCCsi = 216, |
| ARM_MOVCCsr = 217, |
| ARM_MOVPCLR = 218, |
| ARM_MOVPCRX = 219, |
| ARM_MOVTi16 = 220, |
| ARM_MOVTi16_ga_pcrel = 221, |
| ARM_MOV_ga_pcrel = 222, |
| ARM_MOV_ga_pcrel_ldr = 223, |
| ARM_MOVi = 224, |
| ARM_MOVi16 = 225, |
| ARM_MOVi16_ga_pcrel = 226, |
| ARM_MOVi32imm = 227, |
| ARM_MOVr = 228, |
| ARM_MOVr_TC = 229, |
| ARM_MOVsi = 230, |
| ARM_MOVsr = 231, |
| ARM_MOVsra_flag = 232, |
| ARM_MOVsrl_flag = 233, |
| ARM_MRC = 234, |
| ARM_MRC2 = 235, |
| ARM_MRRC = 236, |
| ARM_MRRC2 = 237, |
| ARM_MRS = 238, |
| ARM_MRSbanked = 239, |
| ARM_MRSsys = 240, |
| ARM_MSR = 241, |
| ARM_MSRbanked = 242, |
| ARM_MSRi = 243, |
| ARM_MUL = 244, |
| ARM_MULv5 = 245, |
| ARM_MVNCCi = 246, |
| ARM_MVNi = 247, |
| ARM_MVNr = 248, |
| ARM_MVNsi = 249, |
| ARM_MVNsr = 250, |
| ARM_ORRri = 251, |
| ARM_ORRrr = 252, |
| ARM_ORRrsi = 253, |
| ARM_ORRrsr = 254, |
| ARM_PICADD = 255, |
| ARM_PICLDR = 256, |
| ARM_PICLDRB = 257, |
| ARM_PICLDRH = 258, |
| ARM_PICLDRSB = 259, |
| ARM_PICLDRSH = 260, |
| ARM_PICSTR = 261, |
| ARM_PICSTRB = 262, |
| ARM_PICSTRH = 263, |
| ARM_PKHBT = 264, |
| ARM_PKHTB = 265, |
| ARM_PLDWi12 = 266, |
| ARM_PLDWrs = 267, |
| ARM_PLDi12 = 268, |
| ARM_PLDrs = 269, |
| ARM_PLIi12 = 270, |
| ARM_PLIrs = 271, |
| ARM_QADD = 272, |
| ARM_QADD16 = 273, |
| ARM_QADD8 = 274, |
| ARM_QASX = 275, |
| ARM_QDADD = 276, |
| ARM_QDSUB = 277, |
| ARM_QSAX = 278, |
| ARM_QSUB = 279, |
| ARM_QSUB16 = 280, |
| ARM_QSUB8 = 281, |
| ARM_RBIT = 282, |
| ARM_REV = 283, |
| ARM_REV16 = 284, |
| ARM_REVSH = 285, |
| ARM_RFEDA = 286, |
| ARM_RFEDA_UPD = 287, |
| ARM_RFEDB = 288, |
| ARM_RFEDB_UPD = 289, |
| ARM_RFEIA = 290, |
| ARM_RFEIA_UPD = 291, |
| ARM_RFEIB = 292, |
| ARM_RFEIB_UPD = 293, |
| ARM_RORi = 294, |
| ARM_RORr = 295, |
| ARM_RRX = 296, |
| ARM_RRXi = 297, |
| ARM_RSBSri = 298, |
| ARM_RSBSrsi = 299, |
| ARM_RSBSrsr = 300, |
| ARM_RSBri = 301, |
| ARM_RSBrr = 302, |
| ARM_RSBrsi = 303, |
| ARM_RSBrsr = 304, |
| ARM_RSCri = 305, |
| ARM_RSCrr = 306, |
| ARM_RSCrsi = 307, |
| ARM_RSCrsr = 308, |
| ARM_SADD16 = 309, |
| ARM_SADD8 = 310, |
| ARM_SASX = 311, |
| ARM_SBCri = 312, |
| ARM_SBCrr = 313, |
| ARM_SBCrsi = 314, |
| ARM_SBCrsr = 315, |
| ARM_SBFX = 316, |
| ARM_SDIV = 317, |
| ARM_SEL = 318, |
| ARM_SETEND = 319, |
| ARM_SHA1C = 320, |
| ARM_SHA1H = 321, |
| ARM_SHA1M = 322, |
| ARM_SHA1P = 323, |
| ARM_SHA1SU0 = 324, |
| ARM_SHA1SU1 = 325, |
| ARM_SHA256H = 326, |
| ARM_SHA256H2 = 327, |
| ARM_SHA256SU0 = 328, |
| ARM_SHA256SU1 = 329, |
| ARM_SHADD16 = 330, |
| ARM_SHADD8 = 331, |
| ARM_SHASX = 332, |
| ARM_SHSAX = 333, |
| ARM_SHSUB16 = 334, |
| ARM_SHSUB8 = 335, |
| ARM_SMC = 336, |
| ARM_SMLABB = 337, |
| ARM_SMLABT = 338, |
| ARM_SMLAD = 339, |
| ARM_SMLADX = 340, |
| ARM_SMLAL = 341, |
| ARM_SMLALBB = 342, |
| ARM_SMLALBT = 343, |
| ARM_SMLALD = 344, |
| ARM_SMLALDX = 345, |
| ARM_SMLALTB = 346, |
| ARM_SMLALTT = 347, |
| ARM_SMLALv5 = 348, |
| ARM_SMLATB = 349, |
| ARM_SMLATT = 350, |
| ARM_SMLAWB = 351, |
| ARM_SMLAWT = 352, |
| ARM_SMLSD = 353, |
| ARM_SMLSDX = 354, |
| ARM_SMLSLD = 355, |
| ARM_SMLSLDX = 356, |
| ARM_SMMLA = 357, |
| ARM_SMMLAR = 358, |
| ARM_SMMLS = 359, |
| ARM_SMMLSR = 360, |
| ARM_SMMUL = 361, |
| ARM_SMMULR = 362, |
| ARM_SMUAD = 363, |
| ARM_SMUADX = 364, |
| ARM_SMULBB = 365, |
| ARM_SMULBT = 366, |
| ARM_SMULL = 367, |
| ARM_SMULLv5 = 368, |
| ARM_SMULTB = 369, |
| ARM_SMULTT = 370, |
| ARM_SMULWB = 371, |
| ARM_SMULWT = 372, |
| ARM_SMUSD = 373, |
| ARM_SMUSDX = 374, |
| ARM_SPACE = 375, |
| ARM_SRSDA = 376, |
| ARM_SRSDA_UPD = 377, |
| ARM_SRSDB = 378, |
| ARM_SRSDB_UPD = 379, |
| ARM_SRSIA = 380, |
| ARM_SRSIA_UPD = 381, |
| ARM_SRSIB = 382, |
| ARM_SRSIB_UPD = 383, |
| ARM_SSAT = 384, |
| ARM_SSAT16 = 385, |
| ARM_SSAX = 386, |
| ARM_SSUB16 = 387, |
| ARM_SSUB8 = 388, |
| ARM_STC2L_OFFSET = 389, |
| ARM_STC2L_OPTION = 390, |
| ARM_STC2L_POST = 391, |
| ARM_STC2L_PRE = 392, |
| ARM_STC2_OFFSET = 393, |
| ARM_STC2_OPTION = 394, |
| ARM_STC2_POST = 395, |
| ARM_STC2_PRE = 396, |
| ARM_STCL_OFFSET = 397, |
| ARM_STCL_OPTION = 398, |
| ARM_STCL_POST = 399, |
| ARM_STCL_PRE = 400, |
| ARM_STC_OFFSET = 401, |
| ARM_STC_OPTION = 402, |
| ARM_STC_POST = 403, |
| ARM_STC_PRE = 404, |
| ARM_STL = 405, |
| ARM_STLB = 406, |
| ARM_STLEX = 407, |
| ARM_STLEXB = 408, |
| ARM_STLEXD = 409, |
| ARM_STLEXH = 410, |
| ARM_STLH = 411, |
| ARM_STMDA = 412, |
| ARM_STMDA_UPD = 413, |
| ARM_STMDB = 414, |
| ARM_STMDB_UPD = 415, |
| ARM_STMIA = 416, |
| ARM_STMIA_UPD = 417, |
| ARM_STMIB = 418, |
| ARM_STMIB_UPD = 419, |
| ARM_STRBT_POST = 420, |
| ARM_STRBT_POST_IMM = 421, |
| ARM_STRBT_POST_REG = 422, |
| ARM_STRB_POST_IMM = 423, |
| ARM_STRB_POST_REG = 424, |
| ARM_STRB_PRE_IMM = 425, |
| ARM_STRB_PRE_REG = 426, |
| ARM_STRBi12 = 427, |
| ARM_STRBi_preidx = 428, |
| ARM_STRBr_preidx = 429, |
| ARM_STRBrs = 430, |
| ARM_STRD = 431, |
| ARM_STRD_POST = 432, |
| ARM_STRD_PRE = 433, |
| ARM_STREX = 434, |
| ARM_STREXB = 435, |
| ARM_STREXD = 436, |
| ARM_STREXH = 437, |
| ARM_STRH = 438, |
| ARM_STRHTi = 439, |
| ARM_STRHTr = 440, |
| ARM_STRH_POST = 441, |
| ARM_STRH_PRE = 442, |
| ARM_STRH_preidx = 443, |
| ARM_STRT_POST = 444, |
| ARM_STRT_POST_IMM = 445, |
| ARM_STRT_POST_REG = 446, |
| ARM_STR_POST_IMM = 447, |
| ARM_STR_POST_REG = 448, |
| ARM_STR_PRE_IMM = 449, |
| ARM_STR_PRE_REG = 450, |
| ARM_STRi12 = 451, |
| ARM_STRi_preidx = 452, |
| ARM_STRr_preidx = 453, |
| ARM_STRrs = 454, |
| ARM_SUBS_PC_LR = 455, |
| ARM_SUBSri = 456, |
| ARM_SUBSrr = 457, |
| ARM_SUBSrsi = 458, |
| ARM_SUBSrsr = 459, |
| ARM_SUBri = 460, |
| ARM_SUBrr = 461, |
| ARM_SUBrsi = 462, |
| ARM_SUBrsr = 463, |
| ARM_SVC = 464, |
| ARM_SWP = 465, |
| ARM_SWPB = 466, |
| ARM_SXTAB = 467, |
| ARM_SXTAB16 = 468, |
| ARM_SXTAH = 469, |
| ARM_SXTB = 470, |
| ARM_SXTB16 = 471, |
| ARM_SXTH = 472, |
| ARM_TAILJMPd = 473, |
| ARM_TAILJMPr = 474, |
| ARM_TCRETURNdi = 475, |
| ARM_TCRETURNri = 476, |
| ARM_TEQri = 477, |
| ARM_TEQrr = 478, |
| ARM_TEQrsi = 479, |
| ARM_TEQrsr = 480, |
| ARM_TPsoft = 481, |
| ARM_TRAP = 482, |
| ARM_TRAPNaCl = 483, |
| ARM_TSTri = 484, |
| ARM_TSTrr = 485, |
| ARM_TSTrsi = 486, |
| ARM_TSTrsr = 487, |
| ARM_UADD16 = 488, |
| ARM_UADD8 = 489, |
| ARM_UASX = 490, |
| ARM_UBFX = 491, |
| ARM_UDF = 492, |
| ARM_UDIV = 493, |
| ARM_UHADD16 = 494, |
| ARM_UHADD8 = 495, |
| ARM_UHASX = 496, |
| ARM_UHSAX = 497, |
| ARM_UHSUB16 = 498, |
| ARM_UHSUB8 = 499, |
| ARM_UMAAL = 500, |
| ARM_UMLAL = 501, |
| ARM_UMLALv5 = 502, |
| ARM_UMULL = 503, |
| ARM_UMULLv5 = 504, |
| ARM_UQADD16 = 505, |
| ARM_UQADD8 = 506, |
| ARM_UQASX = 507, |
| ARM_UQSAX = 508, |
| ARM_UQSUB16 = 509, |
| ARM_UQSUB8 = 510, |
| ARM_USAD8 = 511, |
| ARM_USADA8 = 512, |
| ARM_USAT = 513, |
| ARM_USAT16 = 514, |
| ARM_USAX = 515, |
| ARM_USUB16 = 516, |
| ARM_USUB8 = 517, |
| ARM_UXTAB = 518, |
| ARM_UXTAB16 = 519, |
| ARM_UXTAH = 520, |
| ARM_UXTB = 521, |
| ARM_UXTB16 = 522, |
| ARM_UXTH = 523, |
| ARM_VABALsv2i64 = 524, |
| ARM_VABALsv4i32 = 525, |
| ARM_VABALsv8i16 = 526, |
| ARM_VABALuv2i64 = 527, |
| ARM_VABALuv4i32 = 528, |
| ARM_VABALuv8i16 = 529, |
| ARM_VABAsv16i8 = 530, |
| ARM_VABAsv2i32 = 531, |
| ARM_VABAsv4i16 = 532, |
| ARM_VABAsv4i32 = 533, |
| ARM_VABAsv8i16 = 534, |
| ARM_VABAsv8i8 = 535, |
| ARM_VABAuv16i8 = 536, |
| ARM_VABAuv2i32 = 537, |
| ARM_VABAuv4i16 = 538, |
| ARM_VABAuv4i32 = 539, |
| ARM_VABAuv8i16 = 540, |
| ARM_VABAuv8i8 = 541, |
| ARM_VABDLsv2i64 = 542, |
| ARM_VABDLsv4i32 = 543, |
| ARM_VABDLsv8i16 = 544, |
| ARM_VABDLuv2i64 = 545, |
| ARM_VABDLuv4i32 = 546, |
| ARM_VABDLuv8i16 = 547, |
| ARM_VABDfd = 548, |
| ARM_VABDfq = 549, |
| ARM_VABDsv16i8 = 550, |
| ARM_VABDsv2i32 = 551, |
| ARM_VABDsv4i16 = 552, |
| ARM_VABDsv4i32 = 553, |
| ARM_VABDsv8i16 = 554, |
| ARM_VABDsv8i8 = 555, |
| ARM_VABDuv16i8 = 556, |
| ARM_VABDuv2i32 = 557, |
| ARM_VABDuv4i16 = 558, |
| ARM_VABDuv4i32 = 559, |
| ARM_VABDuv8i16 = 560, |
| ARM_VABDuv8i8 = 561, |
| ARM_VABSD = 562, |
| ARM_VABSS = 563, |
| ARM_VABSfd = 564, |
| ARM_VABSfq = 565, |
| ARM_VABSv16i8 = 566, |
| ARM_VABSv2i32 = 567, |
| ARM_VABSv4i16 = 568, |
| ARM_VABSv4i32 = 569, |
| ARM_VABSv8i16 = 570, |
| ARM_VABSv8i8 = 571, |
| ARM_VACGEd = 572, |
| ARM_VACGEq = 573, |
| ARM_VACGTd = 574, |
| ARM_VACGTq = 575, |
| ARM_VADDD = 576, |
| ARM_VADDHNv2i32 = 577, |
| ARM_VADDHNv4i16 = 578, |
| ARM_VADDHNv8i8 = 579, |
| ARM_VADDLsv2i64 = 580, |
| ARM_VADDLsv4i32 = 581, |
| ARM_VADDLsv8i16 = 582, |
| ARM_VADDLuv2i64 = 583, |
| ARM_VADDLuv4i32 = 584, |
| ARM_VADDLuv8i16 = 585, |
| ARM_VADDS = 586, |
| ARM_VADDWsv2i64 = 587, |
| ARM_VADDWsv4i32 = 588, |
| ARM_VADDWsv8i16 = 589, |
| ARM_VADDWuv2i64 = 590, |
| ARM_VADDWuv4i32 = 591, |
| ARM_VADDWuv8i16 = 592, |
| ARM_VADDfd = 593, |
| ARM_VADDfq = 594, |
| ARM_VADDv16i8 = 595, |
| ARM_VADDv1i64 = 596, |
| ARM_VADDv2i32 = 597, |
| ARM_VADDv2i64 = 598, |
| ARM_VADDv4i16 = 599, |
| ARM_VADDv4i32 = 600, |
| ARM_VADDv8i16 = 601, |
| ARM_VADDv8i8 = 602, |
| ARM_VANDd = 603, |
| ARM_VANDq = 604, |
| ARM_VBICd = 605, |
| ARM_VBICiv2i32 = 606, |
| ARM_VBICiv4i16 = 607, |
| ARM_VBICiv4i32 = 608, |
| ARM_VBICiv8i16 = 609, |
| ARM_VBICq = 610, |
| ARM_VBIFd = 611, |
| ARM_VBIFq = 612, |
| ARM_VBITd = 613, |
| ARM_VBITq = 614, |
| ARM_VBSLd = 615, |
| ARM_VBSLq = 616, |
| ARM_VCEQfd = 617, |
| ARM_VCEQfq = 618, |
| ARM_VCEQv16i8 = 619, |
| ARM_VCEQv2i32 = 620, |
| ARM_VCEQv4i16 = 621, |
| ARM_VCEQv4i32 = 622, |
| ARM_VCEQv8i16 = 623, |
| ARM_VCEQv8i8 = 624, |
| ARM_VCEQzv16i8 = 625, |
| ARM_VCEQzv2f32 = 626, |
| ARM_VCEQzv2i32 = 627, |
| ARM_VCEQzv4f32 = 628, |
| ARM_VCEQzv4i16 = 629, |
| ARM_VCEQzv4i32 = 630, |
| ARM_VCEQzv8i16 = 631, |
| ARM_VCEQzv8i8 = 632, |
| ARM_VCGEfd = 633, |
| ARM_VCGEfq = 634, |
| ARM_VCGEsv16i8 = 635, |
| ARM_VCGEsv2i32 = 636, |
| ARM_VCGEsv4i16 = 637, |
| ARM_VCGEsv4i32 = 638, |
| ARM_VCGEsv8i16 = 639, |
| ARM_VCGEsv8i8 = 640, |
| ARM_VCGEuv16i8 = 641, |
| ARM_VCGEuv2i32 = 642, |
| ARM_VCGEuv4i16 = 643, |
| ARM_VCGEuv4i32 = 644, |
| ARM_VCGEuv8i16 = 645, |
| ARM_VCGEuv8i8 = 646, |
| ARM_VCGEzv16i8 = 647, |
| ARM_VCGEzv2f32 = 648, |
| ARM_VCGEzv2i32 = 649, |
| ARM_VCGEzv4f32 = 650, |
| ARM_VCGEzv4i16 = 651, |
| ARM_VCGEzv4i32 = 652, |
| ARM_VCGEzv8i16 = 653, |
| ARM_VCGEzv8i8 = 654, |
| ARM_VCGTfd = 655, |
| ARM_VCGTfq = 656, |
| ARM_VCGTsv16i8 = 657, |
| ARM_VCGTsv2i32 = 658, |
| ARM_VCGTsv4i16 = 659, |
| ARM_VCGTsv4i32 = 660, |
| ARM_VCGTsv8i16 = 661, |
| ARM_VCGTsv8i8 = 662, |
| ARM_VCGTuv16i8 = 663, |
| ARM_VCGTuv2i32 = 664, |
| ARM_VCGTuv4i16 = 665, |
| ARM_VCGTuv4i32 = 666, |
| ARM_VCGTuv8i16 = 667, |
| ARM_VCGTuv8i8 = 668, |
| ARM_VCGTzv16i8 = 669, |
| ARM_VCGTzv2f32 = 670, |
| ARM_VCGTzv2i32 = 671, |
| ARM_VCGTzv4f32 = 672, |
| ARM_VCGTzv4i16 = 673, |
| ARM_VCGTzv4i32 = 674, |
| ARM_VCGTzv8i16 = 675, |
| ARM_VCGTzv8i8 = 676, |
| ARM_VCLEzv16i8 = 677, |
| ARM_VCLEzv2f32 = 678, |
| ARM_VCLEzv2i32 = 679, |
| ARM_VCLEzv4f32 = 680, |
| ARM_VCLEzv4i16 = 681, |
| ARM_VCLEzv4i32 = 682, |
| ARM_VCLEzv8i16 = 683, |
| ARM_VCLEzv8i8 = 684, |
| ARM_VCLSv16i8 = 685, |
| ARM_VCLSv2i32 = 686, |
| ARM_VCLSv4i16 = 687, |
| ARM_VCLSv4i32 = 688, |
| ARM_VCLSv8i16 = 689, |
| ARM_VCLSv8i8 = 690, |
| ARM_VCLTzv16i8 = 691, |
| ARM_VCLTzv2f32 = 692, |
| ARM_VCLTzv2i32 = 693, |
| ARM_VCLTzv4f32 = 694, |
| ARM_VCLTzv4i16 = 695, |
| ARM_VCLTzv4i32 = 696, |
| ARM_VCLTzv8i16 = 697, |
| ARM_VCLTzv8i8 = 698, |
| ARM_VCLZv16i8 = 699, |
| ARM_VCLZv2i32 = 700, |
| ARM_VCLZv4i16 = 701, |
| ARM_VCLZv4i32 = 702, |
| ARM_VCLZv8i16 = 703, |
| ARM_VCLZv8i8 = 704, |
| ARM_VCMPD = 705, |
| ARM_VCMPED = 706, |
| ARM_VCMPES = 707, |
| ARM_VCMPEZD = 708, |
| ARM_VCMPEZS = 709, |
| ARM_VCMPS = 710, |
| ARM_VCMPZD = 711, |
| ARM_VCMPZS = 712, |
| ARM_VCNTd = 713, |
| ARM_VCNTq = 714, |
| ARM_VCVTANSD = 715, |
| ARM_VCVTANSQ = 716, |
| ARM_VCVTANUD = 717, |
| ARM_VCVTANUQ = 718, |
| ARM_VCVTASD = 719, |
| ARM_VCVTASS = 720, |
| ARM_VCVTAUD = 721, |
| ARM_VCVTAUS = 722, |
| ARM_VCVTBDH = 723, |
| ARM_VCVTBHD = 724, |
| ARM_VCVTBHS = 725, |
| ARM_VCVTBSH = 726, |
| ARM_VCVTDS = 727, |
| ARM_VCVTMNSD = 728, |
| ARM_VCVTMNSQ = 729, |
| ARM_VCVTMNUD = 730, |
| ARM_VCVTMNUQ = 731, |
| ARM_VCVTMSD = 732, |
| ARM_VCVTMSS = 733, |
| ARM_VCVTMUD = 734, |
| ARM_VCVTMUS = 735, |
| ARM_VCVTNNSD = 736, |
| ARM_VCVTNNSQ = 737, |
| ARM_VCVTNNUD = 738, |
| ARM_VCVTNNUQ = 739, |
| ARM_VCVTNSD = 740, |
| ARM_VCVTNSS = 741, |
| ARM_VCVTNUD = 742, |
| ARM_VCVTNUS = 743, |
| ARM_VCVTPNSD = 744, |
| ARM_VCVTPNSQ = 745, |
| ARM_VCVTPNUD = 746, |
| ARM_VCVTPNUQ = 747, |
| ARM_VCVTPSD = 748, |
| ARM_VCVTPSS = 749, |
| ARM_VCVTPUD = 750, |
| ARM_VCVTPUS = 751, |
| ARM_VCVTSD = 752, |
| ARM_VCVTTDH = 753, |
| ARM_VCVTTHD = 754, |
| ARM_VCVTTHS = 755, |
| ARM_VCVTTSH = 756, |
| ARM_VCVTf2h = 757, |
| ARM_VCVTf2sd = 758, |
| ARM_VCVTf2sq = 759, |
| ARM_VCVTf2ud = 760, |
| ARM_VCVTf2uq = 761, |
| ARM_VCVTf2xsd = 762, |
| ARM_VCVTf2xsq = 763, |
| ARM_VCVTf2xud = 764, |
| ARM_VCVTf2xuq = 765, |
| ARM_VCVTh2f = 766, |
| ARM_VCVTs2fd = 767, |
| ARM_VCVTs2fq = 768, |
| ARM_VCVTu2fd = 769, |
| ARM_VCVTu2fq = 770, |
| ARM_VCVTxs2fd = 771, |
| ARM_VCVTxs2fq = 772, |
| ARM_VCVTxu2fd = 773, |
| ARM_VCVTxu2fq = 774, |
| ARM_VDIVD = 775, |
| ARM_VDIVS = 776, |
| ARM_VDUP16d = 777, |
| ARM_VDUP16q = 778, |
| ARM_VDUP32d = 779, |
| ARM_VDUP32q = 780, |
| ARM_VDUP8d = 781, |
| ARM_VDUP8q = 782, |
| ARM_VDUPLN16d = 783, |
| ARM_VDUPLN16q = 784, |
| ARM_VDUPLN32d = 785, |
| ARM_VDUPLN32q = 786, |
| ARM_VDUPLN8d = 787, |
| ARM_VDUPLN8q = 788, |
| ARM_VEORd = 789, |
| ARM_VEORq = 790, |
| ARM_VEXTd16 = 791, |
| ARM_VEXTd32 = 792, |
| ARM_VEXTd8 = 793, |
| ARM_VEXTq16 = 794, |
| ARM_VEXTq32 = 795, |
| ARM_VEXTq64 = 796, |
| ARM_VEXTq8 = 797, |
| ARM_VFMAD = 798, |
| ARM_VFMAS = 799, |
| ARM_VFMAfd = 800, |
| ARM_VFMAfq = 801, |
| ARM_VFMSD = 802, |
| ARM_VFMSS = 803, |
| ARM_VFMSfd = 804, |
| ARM_VFMSfq = 805, |
| ARM_VFNMAD = 806, |
| ARM_VFNMAS = 807, |
| ARM_VFNMSD = 808, |
| ARM_VFNMSS = 809, |
| ARM_VGETLNi32 = 810, |
| ARM_VGETLNs16 = 811, |
| ARM_VGETLNs8 = 812, |
| ARM_VGETLNu16 = 813, |
| ARM_VGETLNu8 = 814, |
| ARM_VHADDsv16i8 = 815, |
| ARM_VHADDsv2i32 = 816, |
| ARM_VHADDsv4i16 = 817, |
| ARM_VHADDsv4i32 = 818, |
| ARM_VHADDsv8i16 = 819, |
| ARM_VHADDsv8i8 = 820, |
| ARM_VHADDuv16i8 = 821, |
| ARM_VHADDuv2i32 = 822, |
| ARM_VHADDuv4i16 = 823, |
| ARM_VHADDuv4i32 = 824, |
| ARM_VHADDuv8i16 = 825, |
| ARM_VHADDuv8i8 = 826, |
| ARM_VHSUBsv16i8 = 827, |
| ARM_VHSUBsv2i32 = 828, |
| ARM_VHSUBsv4i16 = 829, |
| ARM_VHSUBsv4i32 = 830, |
| ARM_VHSUBsv8i16 = 831, |
| ARM_VHSUBsv8i8 = 832, |
| ARM_VHSUBuv16i8 = 833, |
| ARM_VHSUBuv2i32 = 834, |
| ARM_VHSUBuv4i16 = 835, |
| ARM_VHSUBuv4i32 = 836, |
| ARM_VHSUBuv8i16 = 837, |
| ARM_VHSUBuv8i8 = 838, |
| ARM_VLD1DUPd16 = 839, |
| ARM_VLD1DUPd16wb_fixed = 840, |
| ARM_VLD1DUPd16wb_register = 841, |
| ARM_VLD1DUPd32 = 842, |
| ARM_VLD1DUPd32wb_fixed = 843, |
| ARM_VLD1DUPd32wb_register = 844, |
| ARM_VLD1DUPd8 = 845, |
| ARM_VLD1DUPd8wb_fixed = 846, |
| ARM_VLD1DUPd8wb_register = 847, |
| ARM_VLD1DUPq16 = 848, |
| ARM_VLD1DUPq16wb_fixed = 849, |
| ARM_VLD1DUPq16wb_register = 850, |
| ARM_VLD1DUPq32 = 851, |
| ARM_VLD1DUPq32wb_fixed = 852, |
| ARM_VLD1DUPq32wb_register = 853, |
| ARM_VLD1DUPq8 = 854, |
| ARM_VLD1DUPq8wb_fixed = 855, |
| ARM_VLD1DUPq8wb_register = 856, |
| ARM_VLD1LNd16 = 857, |
| ARM_VLD1LNd16_UPD = 858, |
| ARM_VLD1LNd32 = 859, |
| ARM_VLD1LNd32_UPD = 860, |
| ARM_VLD1LNd8 = 861, |
| ARM_VLD1LNd8_UPD = 862, |
| ARM_VLD1LNdAsm_16 = 863, |
| ARM_VLD1LNdAsm_32 = 864, |
| ARM_VLD1LNdAsm_8 = 865, |
| ARM_VLD1LNdWB_fixed_Asm_16 = 866, |
| ARM_VLD1LNdWB_fixed_Asm_32 = 867, |
| ARM_VLD1LNdWB_fixed_Asm_8 = 868, |
| ARM_VLD1LNdWB_register_Asm_16 = 869, |
| ARM_VLD1LNdWB_register_Asm_32 = 870, |
| ARM_VLD1LNdWB_register_Asm_8 = 871, |
| ARM_VLD1LNq16Pseudo = 872, |
| ARM_VLD1LNq16Pseudo_UPD = 873, |
| ARM_VLD1LNq32Pseudo = 874, |
| ARM_VLD1LNq32Pseudo_UPD = 875, |
| ARM_VLD1LNq8Pseudo = 876, |
| ARM_VLD1LNq8Pseudo_UPD = 877, |
| ARM_VLD1d16 = 878, |
| ARM_VLD1d16Q = 879, |
| ARM_VLD1d16Qwb_fixed = 880, |
| ARM_VLD1d16Qwb_register = 881, |
| ARM_VLD1d16T = 882, |
| ARM_VLD1d16Twb_fixed = 883, |
| ARM_VLD1d16Twb_register = 884, |
| ARM_VLD1d16wb_fixed = 885, |
| ARM_VLD1d16wb_register = 886, |
| ARM_VLD1d32 = 887, |
| ARM_VLD1d32Q = 888, |
| ARM_VLD1d32Qwb_fixed = 889, |
| ARM_VLD1d32Qwb_register = 890, |
| ARM_VLD1d32T = 891, |
| ARM_VLD1d32Twb_fixed = 892, |
| ARM_VLD1d32Twb_register = 893, |
| ARM_VLD1d32wb_fixed = 894, |
| ARM_VLD1d32wb_register = 895, |
| ARM_VLD1d64 = 896, |
| ARM_VLD1d64Q = 897, |
| ARM_VLD1d64QPseudo = 898, |
| ARM_VLD1d64QPseudoWB_fixed = 899, |
| ARM_VLD1d64QPseudoWB_register = 900, |
| ARM_VLD1d64Qwb_fixed = 901, |
| ARM_VLD1d64Qwb_register = 902, |
| ARM_VLD1d64T = 903, |
| ARM_VLD1d64TPseudo = 904, |
| ARM_VLD1d64TPseudoWB_fixed = 905, |
| ARM_VLD1d64TPseudoWB_register = 906, |
| ARM_VLD1d64Twb_fixed = 907, |
| ARM_VLD1d64Twb_register = 908, |
| ARM_VLD1d64wb_fixed = 909, |
| ARM_VLD1d64wb_register = 910, |
| ARM_VLD1d8 = 911, |
| ARM_VLD1d8Q = 912, |
| ARM_VLD1d8Qwb_fixed = 913, |
| ARM_VLD1d8Qwb_register = 914, |
| ARM_VLD1d8T = 915, |
| ARM_VLD1d8Twb_fixed = 916, |
| ARM_VLD1d8Twb_register = 917, |
| ARM_VLD1d8wb_fixed = 918, |
| ARM_VLD1d8wb_register = 919, |
| ARM_VLD1q16 = 920, |
| ARM_VLD1q16wb_fixed = 921, |
| ARM_VLD1q16wb_register = 922, |
| ARM_VLD1q32 = 923, |
| ARM_VLD1q32wb_fixed = 924, |
| ARM_VLD1q32wb_register = 925, |
| ARM_VLD1q64 = 926, |
| ARM_VLD1q64wb_fixed = 927, |
| ARM_VLD1q64wb_register = 928, |
| ARM_VLD1q8 = 929, |
| ARM_VLD1q8wb_fixed = 930, |
| ARM_VLD1q8wb_register = 931, |
| ARM_VLD2DUPd16 = 932, |
| ARM_VLD2DUPd16wb_fixed = 933, |
| ARM_VLD2DUPd16wb_register = 934, |
| ARM_VLD2DUPd16x2 = 935, |
| ARM_VLD2DUPd16x2wb_fixed = 936, |
| ARM_VLD2DUPd16x2wb_register = 937, |
| ARM_VLD2DUPd32 = 938, |
| ARM_VLD2DUPd32wb_fixed = 939, |
| ARM_VLD2DUPd32wb_register = 940, |
| ARM_VLD2DUPd32x2 = 941, |
| ARM_VLD2DUPd32x2wb_fixed = 942, |
| ARM_VLD2DUPd32x2wb_register = 943, |
| ARM_VLD2DUPd8 = 944, |
| ARM_VLD2DUPd8wb_fixed = 945, |
| ARM_VLD2DUPd8wb_register = 946, |
| ARM_VLD2DUPd8x2 = 947, |
| ARM_VLD2DUPd8x2wb_fixed = 948, |
| ARM_VLD2DUPd8x2wb_register = 949, |
| ARM_VLD2LNd16 = 950, |
| ARM_VLD2LNd16Pseudo = 951, |
| ARM_VLD2LNd16Pseudo_UPD = 952, |
| ARM_VLD2LNd16_UPD = 953, |
| ARM_VLD2LNd32 = 954, |
| ARM_VLD2LNd32Pseudo = 955, |
| ARM_VLD2LNd32Pseudo_UPD = 956, |
| ARM_VLD2LNd32_UPD = 957, |
| ARM_VLD2LNd8 = 958, |
| ARM_VLD2LNd8Pseudo = 959, |
| ARM_VLD2LNd8Pseudo_UPD = 960, |
| ARM_VLD2LNd8_UPD = 961, |
| ARM_VLD2LNdAsm_16 = 962, |
| ARM_VLD2LNdAsm_32 = 963, |
| ARM_VLD2LNdAsm_8 = 964, |
| ARM_VLD2LNdWB_fixed_Asm_16 = 965, |
| ARM_VLD2LNdWB_fixed_Asm_32 = 966, |
| ARM_VLD2LNdWB_fixed_Asm_8 = 967, |
| ARM_VLD2LNdWB_register_Asm_16 = 968, |
| ARM_VLD2LNdWB_register_Asm_32 = 969, |
| ARM_VLD2LNdWB_register_Asm_8 = 970, |
| ARM_VLD2LNq16 = 971, |
| ARM_VLD2LNq16Pseudo = 972, |
| ARM_VLD2LNq16Pseudo_UPD = 973, |
| ARM_VLD2LNq16_UPD = 974, |
| ARM_VLD2LNq32 = 975, |
| ARM_VLD2LNq32Pseudo = 976, |
| ARM_VLD2LNq32Pseudo_UPD = 977, |
| ARM_VLD2LNq32_UPD = 978, |
| ARM_VLD2LNqAsm_16 = 979, |
| ARM_VLD2LNqAsm_32 = 980, |
| ARM_VLD2LNqWB_fixed_Asm_16 = 981, |
| ARM_VLD2LNqWB_fixed_Asm_32 = 982, |
| ARM_VLD2LNqWB_register_Asm_16 = 983, |
| ARM_VLD2LNqWB_register_Asm_32 = 984, |
| ARM_VLD2b16 = 985, |
| ARM_VLD2b16wb_fixed = 986, |
| ARM_VLD2b16wb_register = 987, |
| ARM_VLD2b32 = 988, |
| ARM_VLD2b32wb_fixed = 989, |
| ARM_VLD2b32wb_register = 990, |
| ARM_VLD2b8 = 991, |
| ARM_VLD2b8wb_fixed = 992, |
| ARM_VLD2b8wb_register = 993, |
| ARM_VLD2d16 = 994, |
| ARM_VLD2d16wb_fixed = 995, |
| ARM_VLD2d16wb_register = 996, |
| ARM_VLD2d32 = 997, |
| ARM_VLD2d32wb_fixed = 998, |
| ARM_VLD2d32wb_register = 999, |
| ARM_VLD2d8 = 1000, |
| ARM_VLD2d8wb_fixed = 1001, |
| ARM_VLD2d8wb_register = 1002, |
| ARM_VLD2q16 = 1003, |
| ARM_VLD2q16Pseudo = 1004, |
| ARM_VLD2q16PseudoWB_fixed = 1005, |
| ARM_VLD2q16PseudoWB_register = 1006, |
| ARM_VLD2q16wb_fixed = 1007, |
| ARM_VLD2q16wb_register = 1008, |
| ARM_VLD2q32 = 1009, |
| ARM_VLD2q32Pseudo = 1010, |
| ARM_VLD2q32PseudoWB_fixed = 1011, |
| ARM_VLD2q32PseudoWB_register = 1012, |
| ARM_VLD2q32wb_fixed = 1013, |
| ARM_VLD2q32wb_register = 1014, |
| ARM_VLD2q8 = 1015, |
| ARM_VLD2q8Pseudo = 1016, |
| ARM_VLD2q8PseudoWB_fixed = 1017, |
| ARM_VLD2q8PseudoWB_register = 1018, |
| ARM_VLD2q8wb_fixed = 1019, |
| ARM_VLD2q8wb_register = 1020, |
| ARM_VLD3DUPd16 = 1021, |
| ARM_VLD3DUPd16Pseudo = 1022, |
| ARM_VLD3DUPd16Pseudo_UPD = 1023, |
| ARM_VLD3DUPd16_UPD = 1024, |
| ARM_VLD3DUPd32 = 1025, |
| ARM_VLD3DUPd32Pseudo = 1026, |
| ARM_VLD3DUPd32Pseudo_UPD = 1027, |
| ARM_VLD3DUPd32_UPD = 1028, |
| ARM_VLD3DUPd8 = 1029, |
| ARM_VLD3DUPd8Pseudo = 1030, |
| ARM_VLD3DUPd8Pseudo_UPD = 1031, |
| ARM_VLD3DUPd8_UPD = 1032, |
| ARM_VLD3DUPdAsm_16 = 1033, |
| ARM_VLD3DUPdAsm_32 = 1034, |
| ARM_VLD3DUPdAsm_8 = 1035, |
| ARM_VLD3DUPdWB_fixed_Asm_16 = 1036, |
| ARM_VLD3DUPdWB_fixed_Asm_32 = 1037, |
| ARM_VLD3DUPdWB_fixed_Asm_8 = 1038, |
| ARM_VLD3DUPdWB_register_Asm_16 = 1039, |
| ARM_VLD3DUPdWB_register_Asm_32 = 1040, |
| ARM_VLD3DUPdWB_register_Asm_8 = 1041, |
| ARM_VLD3DUPq16 = 1042, |
| ARM_VLD3DUPq16_UPD = 1043, |
| ARM_VLD3DUPq32 = 1044, |
| ARM_VLD3DUPq32_UPD = 1045, |
| ARM_VLD3DUPq8 = 1046, |
| ARM_VLD3DUPq8_UPD = 1047, |
| ARM_VLD3DUPqAsm_16 = 1048, |
| ARM_VLD3DUPqAsm_32 = 1049, |
| ARM_VLD3DUPqAsm_8 = 1050, |
| ARM_VLD3DUPqWB_fixed_Asm_16 = 1051, |
| ARM_VLD3DUPqWB_fixed_Asm_32 = 1052, |
| ARM_VLD3DUPqWB_fixed_Asm_8 = 1053, |
| ARM_VLD3DUPqWB_register_Asm_16 = 1054, |
| ARM_VLD3DUPqWB_register_Asm_32 = 1055, |
| ARM_VLD3DUPqWB_register_Asm_8 = 1056, |
| ARM_VLD3LNd16 = 1057, |
| ARM_VLD3LNd16Pseudo = 1058, |
| ARM_VLD3LNd16Pseudo_UPD = 1059, |
| ARM_VLD3LNd16_UPD = 1060, |
| ARM_VLD3LNd32 = 1061, |
| ARM_VLD3LNd32Pseudo = 1062, |
| ARM_VLD3LNd32Pseudo_UPD = 1063, |
| ARM_VLD3LNd32_UPD = 1064, |
| ARM_VLD3LNd8 = 1065, |
| ARM_VLD3LNd8Pseudo = 1066, |
| ARM_VLD3LNd8Pseudo_UPD = 1067, |
| ARM_VLD3LNd8_UPD = 1068, |
| ARM_VLD3LNdAsm_16 = 1069, |
| ARM_VLD3LNdAsm_32 = 1070, |
| ARM_VLD3LNdAsm_8 = 1071, |
| ARM_VLD3LNdWB_fixed_Asm_16 = 1072, |
| ARM_VLD3LNdWB_fixed_Asm_32 = 1073, |
| ARM_VLD3LNdWB_fixed_Asm_8 = 1074, |
| ARM_VLD3LNdWB_register_Asm_16 = 1075, |
| ARM_VLD3LNdWB_register_Asm_32 = 1076, |
| ARM_VLD3LNdWB_register_Asm_8 = 1077, |
| ARM_VLD3LNq16 = 1078, |
| ARM_VLD3LNq16Pseudo = 1079, |
| ARM_VLD3LNq16Pseudo_UPD = 1080, |
| ARM_VLD3LNq16_UPD = 1081, |
| ARM_VLD3LNq32 = 1082, |
| ARM_VLD3LNq32Pseudo = 1083, |
| ARM_VLD3LNq32Pseudo_UPD = 1084, |
| ARM_VLD3LNq32_UPD = 1085, |
| ARM_VLD3LNqAsm_16 = 1086, |
| ARM_VLD3LNqAsm_32 = 1087, |
| ARM_VLD3LNqWB_fixed_Asm_16 = 1088, |
| ARM_VLD3LNqWB_fixed_Asm_32 = 1089, |
| ARM_VLD3LNqWB_register_Asm_16 = 1090, |
| ARM_VLD3LNqWB_register_Asm_32 = 1091, |
| ARM_VLD3d16 = 1092, |
| ARM_VLD3d16Pseudo = 1093, |
| ARM_VLD3d16Pseudo_UPD = 1094, |
| ARM_VLD3d16_UPD = 1095, |
| ARM_VLD3d32 = 1096, |
| ARM_VLD3d32Pseudo = 1097, |
| ARM_VLD3d32Pseudo_UPD = 1098, |
| ARM_VLD3d32_UPD = 1099, |
| ARM_VLD3d8 = 1100, |
| ARM_VLD3d8Pseudo = 1101, |
| ARM_VLD3d8Pseudo_UPD = 1102, |
| ARM_VLD3d8_UPD = 1103, |
| ARM_VLD3dAsm_16 = 1104, |
| ARM_VLD3dAsm_32 = 1105, |
| ARM_VLD3dAsm_8 = 1106, |
| ARM_VLD3dWB_fixed_Asm_16 = 1107, |
| ARM_VLD3dWB_fixed_Asm_32 = 1108, |
| ARM_VLD3dWB_fixed_Asm_8 = 1109, |
| ARM_VLD3dWB_register_Asm_16 = 1110, |
| ARM_VLD3dWB_register_Asm_32 = 1111, |
| ARM_VLD3dWB_register_Asm_8 = 1112, |
| ARM_VLD3q16 = 1113, |
| ARM_VLD3q16Pseudo_UPD = 1114, |
| ARM_VLD3q16_UPD = 1115, |
| ARM_VLD3q16oddPseudo = 1116, |
| ARM_VLD3q16oddPseudo_UPD = 1117, |
| ARM_VLD3q32 = 1118, |
| ARM_VLD3q32Pseudo_UPD = 1119, |
| ARM_VLD3q32_UPD = 1120, |
| ARM_VLD3q32oddPseudo = 1121, |
| ARM_VLD3q32oddPseudo_UPD = 1122, |
| ARM_VLD3q8 = 1123, |
| ARM_VLD3q8Pseudo_UPD = 1124, |
| ARM_VLD3q8_UPD = 1125, |
| ARM_VLD3q8oddPseudo = 1126, |
| ARM_VLD3q8oddPseudo_UPD = 1127, |
| ARM_VLD3qAsm_16 = 1128, |
| ARM_VLD3qAsm_32 = 1129, |
| ARM_VLD3qAsm_8 = 1130, |
| ARM_VLD3qWB_fixed_Asm_16 = 1131, |
| ARM_VLD3qWB_fixed_Asm_32 = 1132, |
| ARM_VLD3qWB_fixed_Asm_8 = 1133, |
| ARM_VLD3qWB_register_Asm_16 = 1134, |
| ARM_VLD3qWB_register_Asm_32 = 1135, |
| ARM_VLD3qWB_register_Asm_8 = 1136, |
| ARM_VLD4DUPd16 = 1137, |
| ARM_VLD4DUPd16Pseudo = 1138, |
| ARM_VLD4DUPd16Pseudo_UPD = 1139, |
| ARM_VLD4DUPd16_UPD = 1140, |
| ARM_VLD4DUPd32 = 1141, |
| ARM_VLD4DUPd32Pseudo = 1142, |
| ARM_VLD4DUPd32Pseudo_UPD = 1143, |
| ARM_VLD4DUPd32_UPD = 1144, |
| ARM_VLD4DUPd8 = 1145, |
| ARM_VLD4DUPd8Pseudo = 1146, |
| ARM_VLD4DUPd8Pseudo_UPD = 1147, |
| ARM_VLD4DUPd8_UPD = 1148, |
| ARM_VLD4DUPdAsm_16 = 1149, |
| ARM_VLD4DUPdAsm_32 = 1150, |
| ARM_VLD4DUPdAsm_8 = 1151, |
| ARM_VLD4DUPdWB_fixed_Asm_16 = 1152, |
| ARM_VLD4DUPdWB_fixed_Asm_32 = 1153, |
| ARM_VLD4DUPdWB_fixed_Asm_8 = 1154, |
| ARM_VLD4DUPdWB_register_Asm_16 = 1155, |
| ARM_VLD4DUPdWB_register_Asm_32 = 1156, |
| ARM_VLD4DUPdWB_register_Asm_8 = 1157, |
| ARM_VLD4DUPq16 = 1158, |
| ARM_VLD4DUPq16_UPD = 1159, |
| ARM_VLD4DUPq32 = 1160, |
| ARM_VLD4DUPq32_UPD = 1161, |
| ARM_VLD4DUPq8 = 1162, |
| ARM_VLD4DUPq8_UPD = 1163, |
| ARM_VLD4DUPqAsm_16 = 1164, |
| ARM_VLD4DUPqAsm_32 = 1165, |
| ARM_VLD4DUPqAsm_8 = 1166, |
| ARM_VLD4DUPqWB_fixed_Asm_16 = 1167, |
| ARM_VLD4DUPqWB_fixed_Asm_32 = 1168, |
| ARM_VLD4DUPqWB_fixed_Asm_8 = 1169, |
| ARM_VLD4DUPqWB_register_Asm_16 = 1170, |
| ARM_VLD4DUPqWB_register_Asm_32 = 1171, |
| ARM_VLD4DUPqWB_register_Asm_8 = 1172, |
| ARM_VLD4LNd16 = 1173, |
| ARM_VLD4LNd16Pseudo = 1174, |
| ARM_VLD4LNd16Pseudo_UPD = 1175, |
| ARM_VLD4LNd16_UPD = 1176, |
| ARM_VLD4LNd32 = 1177, |
| ARM_VLD4LNd32Pseudo = 1178, |
| ARM_VLD4LNd32Pseudo_UPD = 1179, |
| ARM_VLD4LNd32_UPD = 1180, |
| ARM_VLD4LNd8 = 1181, |
| ARM_VLD4LNd8Pseudo = 1182, |
| ARM_VLD4LNd8Pseudo_UPD = 1183, |
| ARM_VLD4LNd8_UPD = 1184, |
| ARM_VLD4LNdAsm_16 = 1185, |
| ARM_VLD4LNdAsm_32 = 1186, |
| ARM_VLD4LNdAsm_8 = 1187, |
| ARM_VLD4LNdWB_fixed_Asm_16 = 1188, |
| ARM_VLD4LNdWB_fixed_Asm_32 = 1189, |
| ARM_VLD4LNdWB_fixed_Asm_8 = 1190, |
| ARM_VLD4LNdWB_register_Asm_16 = 1191, |
| ARM_VLD4LNdWB_register_Asm_32 = 1192, |
| ARM_VLD4LNdWB_register_Asm_8 = 1193, |
| ARM_VLD4LNq16 = 1194, |
| ARM_VLD4LNq16Pseudo = 1195, |
| ARM_VLD4LNq16Pseudo_UPD = 1196, |
| ARM_VLD4LNq16_UPD = 1197, |
| ARM_VLD4LNq32 = 1198, |
| ARM_VLD4LNq32Pseudo = 1199, |
| ARM_VLD4LNq32Pseudo_UPD = 1200, |
| ARM_VLD4LNq32_UPD = 1201, |
| ARM_VLD4LNqAsm_16 = 1202, |
| ARM_VLD4LNqAsm_32 = 1203, |
| ARM_VLD4LNqWB_fixed_Asm_16 = 1204, |
| ARM_VLD4LNqWB_fixed_Asm_32 = 1205, |
| ARM_VLD4LNqWB_register_Asm_16 = 1206, |
| ARM_VLD4LNqWB_register_Asm_32 = 1207, |
| ARM_VLD4d16 = 1208, |
| ARM_VLD4d16Pseudo = 1209, |
| ARM_VLD4d16Pseudo_UPD = 1210, |
| ARM_VLD4d16_UPD = 1211, |
| ARM_VLD4d32 = 1212, |
| ARM_VLD4d32Pseudo = 1213, |
| ARM_VLD4d32Pseudo_UPD = 1214, |
| ARM_VLD4d32_UPD = 1215, |
| ARM_VLD4d8 = 1216, |
| ARM_VLD4d8Pseudo = 1217, |
| ARM_VLD4d8Pseudo_UPD = 1218, |
| ARM_VLD4d8_UPD = 1219, |
| ARM_VLD4dAsm_16 = 1220, |
| ARM_VLD4dAsm_32 = 1221, |
| ARM_VLD4dAsm_8 = 1222, |
| ARM_VLD4dWB_fixed_Asm_16 = 1223, |
| ARM_VLD4dWB_fixed_Asm_32 = 1224, |
| ARM_VLD4dWB_fixed_Asm_8 = 1225, |
| ARM_VLD4dWB_register_Asm_16 = 1226, |
| ARM_VLD4dWB_register_Asm_32 = 1227, |
| ARM_VLD4dWB_register_Asm_8 = 1228, |
| ARM_VLD4q16 = 1229, |
| ARM_VLD4q16Pseudo_UPD = 1230, |
| ARM_VLD4q16_UPD = 1231, |
| ARM_VLD4q16oddPseudo = 1232, |
| ARM_VLD4q16oddPseudo_UPD = 1233, |
| ARM_VLD4q32 = 1234, |
| ARM_VLD4q32Pseudo_UPD = 1235, |
| ARM_VLD4q32_UPD = 1236, |
| ARM_VLD4q32oddPseudo = 1237, |
| ARM_VLD4q32oddPseudo_UPD = 1238, |
| ARM_VLD4q8 = 1239, |
| ARM_VLD4q8Pseudo_UPD = 1240, |
| ARM_VLD4q8_UPD = 1241, |
| ARM_VLD4q8oddPseudo = 1242, |
| ARM_VLD4q8oddPseudo_UPD = 1243, |
| ARM_VLD4qAsm_16 = 1244, |
| ARM_VLD4qAsm_32 = 1245, |
| ARM_VLD4qAsm_8 = 1246, |
| ARM_VLD4qWB_fixed_Asm_16 = 1247, |
| ARM_VLD4qWB_fixed_Asm_32 = 1248, |
| ARM_VLD4qWB_fixed_Asm_8 = 1249, |
| ARM_VLD4qWB_register_Asm_16 = 1250, |
| ARM_VLD4qWB_register_Asm_32 = 1251, |
| ARM_VLD4qWB_register_Asm_8 = 1252, |
| ARM_VLDMDDB_UPD = 1253, |
| ARM_VLDMDIA = 1254, |
| ARM_VLDMDIA_UPD = 1255, |
| ARM_VLDMQIA = 1256, |
| ARM_VLDMSDB_UPD = 1257, |
| ARM_VLDMSIA = 1258, |
| ARM_VLDMSIA_UPD = 1259, |
| ARM_VLDRD = 1260, |
| ARM_VLDRS = 1261, |
| ARM_VMAXNMD = 1262, |
| ARM_VMAXNMND = 1263, |
| ARM_VMAXNMNQ = 1264, |
| ARM_VMAXNMS = 1265, |
| ARM_VMAXfd = 1266, |
| ARM_VMAXfq = 1267, |
| ARM_VMAXsv16i8 = 1268, |
| ARM_VMAXsv2i32 = 1269, |
| ARM_VMAXsv4i16 = 1270, |
| ARM_VMAXsv4i32 = 1271, |
| ARM_VMAXsv8i16 = 1272, |
| ARM_VMAXsv8i8 = 1273, |
| ARM_VMAXuv16i8 = 1274, |
| ARM_VMAXuv2i32 = 1275, |
| ARM_VMAXuv4i16 = 1276, |
| ARM_VMAXuv4i32 = 1277, |
| ARM_VMAXuv8i16 = 1278, |
| ARM_VMAXuv8i8 = 1279, |
| ARM_VMINNMD = 1280, |
| ARM_VMINNMND = 1281, |
| ARM_VMINNMNQ = 1282, |
| ARM_VMINNMS = 1283, |
| ARM_VMINfd = 1284, |
| ARM_VMINfq = 1285, |
| ARM_VMINsv16i8 = 1286, |
| ARM_VMINsv2i32 = 1287, |
| ARM_VMINsv4i16 = 1288, |
| ARM_VMINsv4i32 = 1289, |
| ARM_VMINsv8i16 = 1290, |
| ARM_VMINsv8i8 = 1291, |
| ARM_VMINuv16i8 = 1292, |
| ARM_VMINuv2i32 = 1293, |
| ARM_VMINuv4i16 = 1294, |
| ARM_VMINuv4i32 = 1295, |
| ARM_VMINuv8i16 = 1296, |
| ARM_VMINuv8i8 = 1297, |
| ARM_VMLAD = 1298, |
| ARM_VMLALslsv2i32 = 1299, |
| ARM_VMLALslsv4i16 = 1300, |
| ARM_VMLALsluv2i32 = 1301, |
| ARM_VMLALsluv4i16 = 1302, |
| ARM_VMLALsv2i64 = 1303, |
| ARM_VMLALsv4i32 = 1304, |
| ARM_VMLALsv8i16 = 1305, |
| ARM_VMLALuv2i64 = 1306, |
| ARM_VMLALuv4i32 = 1307, |
| ARM_VMLALuv8i16 = 1308, |
| ARM_VMLAS = 1309, |
| ARM_VMLAfd = 1310, |
| ARM_VMLAfq = 1311, |
| ARM_VMLAslfd = 1312, |
| ARM_VMLAslfq = 1313, |
| ARM_VMLAslv2i32 = 1314, |
| ARM_VMLAslv4i16 = 1315, |
| ARM_VMLAslv4i32 = 1316, |
| ARM_VMLAslv8i16 = 1317, |
| ARM_VMLAv16i8 = 1318, |
| ARM_VMLAv2i32 = 1319, |
| ARM_VMLAv4i16 = 1320, |
| ARM_VMLAv4i32 = 1321, |
| ARM_VMLAv8i16 = 1322, |
| ARM_VMLAv8i8 = 1323, |
| ARM_VMLSD = 1324, |
| ARM_VMLSLslsv2i32 = 1325, |
| ARM_VMLSLslsv4i16 = 1326, |
| ARM_VMLSLsluv2i32 = 1327, |
| ARM_VMLSLsluv4i16 = 1328, |
| ARM_VMLSLsv2i64 = 1329, |
| ARM_VMLSLsv4i32 = 1330, |
| ARM_VMLSLsv8i16 = 1331, |
| ARM_VMLSLuv2i64 = 1332, |
| ARM_VMLSLuv4i32 = 1333, |
| ARM_VMLSLuv8i16 = 1334, |
| ARM_VMLSS = 1335, |
| ARM_VMLSfd = 1336, |
| ARM_VMLSfq = 1337, |
| ARM_VMLSslfd = 1338, |
| ARM_VMLSslfq = 1339, |
| ARM_VMLSslv2i32 = 1340, |
| ARM_VMLSslv4i16 = 1341, |
| ARM_VMLSslv4i32 = 1342, |
| ARM_VMLSslv8i16 = 1343, |
| ARM_VMLSv16i8 = 1344, |
| ARM_VMLSv2i32 = 1345, |
| ARM_VMLSv4i16 = 1346, |
| ARM_VMLSv4i32 = 1347, |
| ARM_VMLSv8i16 = 1348, |
| ARM_VMLSv8i8 = 1349, |
| ARM_VMOVD = 1350, |
| ARM_VMOVD0 = 1351, |
| ARM_VMOVDRR = 1352, |
| ARM_VMOVDcc = 1353, |
| ARM_VMOVLsv2i64 = 1354, |
| ARM_VMOVLsv4i32 = 1355, |
| ARM_VMOVLsv8i16 = 1356, |
| ARM_VMOVLuv2i64 = 1357, |
| ARM_VMOVLuv4i32 = 1358, |
| ARM_VMOVLuv8i16 = 1359, |
| ARM_VMOVNv2i32 = 1360, |
| ARM_VMOVNv4i16 = 1361, |
| ARM_VMOVNv8i8 = 1362, |
| ARM_VMOVQ0 = 1363, |
| ARM_VMOVRRD = 1364, |
| ARM_VMOVRRS = 1365, |
| ARM_VMOVRS = 1366, |
| ARM_VMOVS = 1367, |
| ARM_VMOVSR = 1368, |
| ARM_VMOVSRR = 1369, |
| ARM_VMOVScc = 1370, |
| ARM_VMOVv16i8 = 1371, |
| ARM_VMOVv1i64 = 1372, |
| ARM_VMOVv2f32 = 1373, |
| ARM_VMOVv2i32 = 1374, |
| ARM_VMOVv2i64 = 1375, |
| ARM_VMOVv4f32 = 1376, |
| ARM_VMOVv4i16 = 1377, |
| ARM_VMOVv4i32 = 1378, |
| ARM_VMOVv8i16 = 1379, |
| ARM_VMOVv8i8 = 1380, |
| ARM_VMRS = 1381, |
| ARM_VMRS_FPEXC = 1382, |
| ARM_VMRS_FPINST = 1383, |
| ARM_VMRS_FPINST2 = 1384, |
| ARM_VMRS_FPSID = 1385, |
| ARM_VMRS_MVFR0 = 1386, |
| ARM_VMRS_MVFR1 = 1387, |
| ARM_VMRS_MVFR2 = 1388, |
| ARM_VMSR = 1389, |
| ARM_VMSR_FPEXC = 1390, |
| ARM_VMSR_FPINST = 1391, |
| ARM_VMSR_FPINST2 = 1392, |
| ARM_VMSR_FPSID = 1393, |
| ARM_VMULD = 1394, |
| ARM_VMULLp64 = 1395, |
| ARM_VMULLp8 = 1396, |
| ARM_VMULLslsv2i32 = 1397, |
| ARM_VMULLslsv4i16 = 1398, |
| ARM_VMULLsluv2i32 = 1399, |
| ARM_VMULLsluv4i16 = 1400, |
| ARM_VMULLsv2i64 = 1401, |
| ARM_VMULLsv4i32 = 1402, |
| ARM_VMULLsv8i16 = 1403, |
| ARM_VMULLuv2i64 = 1404, |
| ARM_VMULLuv4i32 = 1405, |
| ARM_VMULLuv8i16 = 1406, |
| ARM_VMULS = 1407, |
| ARM_VMULfd = 1408, |
| ARM_VMULfq = 1409, |
| ARM_VMULpd = 1410, |
| ARM_VMULpq = 1411, |
| ARM_VMULslfd = 1412, |
| ARM_VMULslfq = 1413, |
| ARM_VMULslv2i32 = 1414, |
| ARM_VMULslv4i16 = 1415, |
| ARM_VMULslv4i32 = 1416, |
| ARM_VMULslv8i16 = 1417, |
| ARM_VMULv16i8 = 1418, |
| ARM_VMULv2i32 = 1419, |
| ARM_VMULv4i16 = 1420, |
| ARM_VMULv4i32 = 1421, |
| ARM_VMULv8i16 = 1422, |
| ARM_VMULv8i8 = 1423, |
| ARM_VMVNd = 1424, |
| ARM_VMVNq = 1425, |
| ARM_VMVNv2i32 = 1426, |
| ARM_VMVNv4i16 = 1427, |
| ARM_VMVNv4i32 = 1428, |
| ARM_VMVNv8i16 = 1429, |
| ARM_VNEGD = 1430, |
| ARM_VNEGS = 1431, |
| ARM_VNEGf32q = 1432, |
| ARM_VNEGfd = 1433, |
| ARM_VNEGs16d = 1434, |
| ARM_VNEGs16q = 1435, |
| ARM_VNEGs32d = 1436, |
| ARM_VNEGs32q = 1437, |
| ARM_VNEGs8d = 1438, |
| ARM_VNEGs8q = 1439, |
| ARM_VNMLAD = 1440, |
| ARM_VNMLAS = 1441, |
| ARM_VNMLSD = 1442, |
| ARM_VNMLSS = 1443, |
| ARM_VNMULD = 1444, |
| ARM_VNMULS = 1445, |
| ARM_VORNd = 1446, |
| ARM_VORNq = 1447, |
| ARM_VORRd = 1448, |
| ARM_VORRiv2i32 = 1449, |
| ARM_VORRiv4i16 = 1450, |
| ARM_VORRiv4i32 = 1451, |
| ARM_VORRiv8i16 = 1452, |
| ARM_VORRq = 1453, |
| ARM_VPADALsv16i8 = 1454, |
| ARM_VPADALsv2i32 = 1455, |
| ARM_VPADALsv4i16 = 1456, |
| ARM_VPADALsv4i32 = 1457, |
| ARM_VPADALsv8i16 = 1458, |
| ARM_VPADALsv8i8 = 1459, |
| ARM_VPADALuv16i8 = 1460, |
| ARM_VPADALuv2i32 = 1461, |
| ARM_VPADALuv4i16 = 1462, |
| ARM_VPADALuv4i32 = 1463, |
| ARM_VPADALuv8i16 = 1464, |
| ARM_VPADALuv8i8 = 1465, |
| ARM_VPADDLsv16i8 = 1466, |
| ARM_VPADDLsv2i32 = 1467, |
| ARM_VPADDLsv4i16 = 1468, |
| ARM_VPADDLsv4i32 = 1469, |
| ARM_VPADDLsv8i16 = 1470, |
| ARM_VPADDLsv8i8 = 1471, |
| ARM_VPADDLuv16i8 = 1472, |
| ARM_VPADDLuv2i32 = 1473, |
| ARM_VPADDLuv4i16 = 1474, |
| ARM_VPADDLuv4i32 = 1475, |
| ARM_VPADDLuv8i16 = 1476, |
| ARM_VPADDLuv8i8 = 1477, |
| ARM_VPADDf = 1478, |
| ARM_VPADDi16 = 1479, |
| ARM_VPADDi32 = 1480, |
| ARM_VPADDi8 = 1481, |
| ARM_VPMAXf = 1482, |
| ARM_VPMAXs16 = 1483, |
| ARM_VPMAXs32 = 1484, |
| ARM_VPMAXs8 = 1485, |
| ARM_VPMAXu16 = 1486, |
| ARM_VPMAXu32 = 1487, |
| ARM_VPMAXu8 = 1488, |
| ARM_VPMINf = 1489, |
| ARM_VPMINs16 = 1490, |
| ARM_VPMINs32 = 1491, |
| ARM_VPMINs8 = 1492, |
| ARM_VPMINu16 = 1493, |
| ARM_VPMINu32 = 1494, |
| ARM_VPMINu8 = 1495, |
| ARM_VQABSv16i8 = 1496, |
| ARM_VQABSv2i32 = 1497, |
| ARM_VQABSv4i16 = 1498, |
| ARM_VQABSv4i32 = 1499, |
| ARM_VQABSv8i16 = 1500, |
| ARM_VQABSv8i8 = 1501, |
| ARM_VQADDsv16i8 = 1502, |
| ARM_VQADDsv1i64 = 1503, |
| ARM_VQADDsv2i32 = 1504, |
| ARM_VQADDsv2i64 = 1505, |
| ARM_VQADDsv4i16 = 1506, |
| ARM_VQADDsv4i32 = 1507, |
| ARM_VQADDsv8i16 = 1508, |
| ARM_VQADDsv8i8 = 1509, |
| ARM_VQADDuv16i8 = 1510, |
| ARM_VQADDuv1i64 = 1511, |
| ARM_VQADDuv2i32 = 1512, |
| ARM_VQADDuv2i64 = 1513, |
| ARM_VQADDuv4i16 = 1514, |
| ARM_VQADDuv4i32 = 1515, |
| ARM_VQADDuv8i16 = 1516, |
| ARM_VQADDuv8i8 = 1517, |
| ARM_VQDMLALslv2i32 = 1518, |
| ARM_VQDMLALslv4i16 = 1519, |
| ARM_VQDMLALv2i64 = 1520, |
| ARM_VQDMLALv4i32 = 1521, |
| ARM_VQDMLSLslv2i32 = 1522, |
| ARM_VQDMLSLslv4i16 = 1523, |
| ARM_VQDMLSLv2i64 = 1524, |
| ARM_VQDMLSLv4i32 = 1525, |
| ARM_VQDMULHslv2i32 = 1526, |
| ARM_VQDMULHslv4i16 = 1527, |
| ARM_VQDMULHslv4i32 = 1528, |
| ARM_VQDMULHslv8i16 = 1529, |
| ARM_VQDMULHv2i32 = 1530, |
| ARM_VQDMULHv4i16 = 1531, |
| ARM_VQDMULHv4i32 = 1532, |
| ARM_VQDMULHv8i16 = 1533, |
| ARM_VQDMULLslv2i32 = 1534, |
| ARM_VQDMULLslv4i16 = 1535, |
| ARM_VQDMULLv2i64 = 1536, |
| ARM_VQDMULLv4i32 = 1537, |
| ARM_VQMOVNsuv2i32 = 1538, |
| ARM_VQMOVNsuv4i16 = 1539, |
| ARM_VQMOVNsuv8i8 = 1540, |
| ARM_VQMOVNsv2i32 = 1541, |
| ARM_VQMOVNsv4i16 = 1542, |
| ARM_VQMOVNsv8i8 = 1543, |
| ARM_VQMOVNuv2i32 = 1544, |
| ARM_VQMOVNuv4i16 = 1545, |
| ARM_VQMOVNuv8i8 = 1546, |
| ARM_VQNEGv16i8 = 1547, |
| ARM_VQNEGv2i32 = 1548, |
| ARM_VQNEGv4i16 = 1549, |
| ARM_VQNEGv4i32 = 1550, |
| ARM_VQNEGv8i16 = 1551, |
| ARM_VQNEGv8i8 = 1552, |
| ARM_VQRDMULHslv2i32 = 1553, |
| ARM_VQRDMULHslv4i16 = 1554, |
| ARM_VQRDMULHslv4i32 = 1555, |
| ARM_VQRDMULHslv8i16 = 1556, |
| ARM_VQRDMULHv2i32 = 1557, |
| ARM_VQRDMULHv4i16 = 1558, |
| ARM_VQRDMULHv4i32 = 1559, |
| ARM_VQRDMULHv8i16 = 1560, |
| ARM_VQRSHLsv16i8 = 1561, |
| ARM_VQRSHLsv1i64 = 1562, |
| ARM_VQRSHLsv2i32 = 1563, |
| ARM_VQRSHLsv2i64 = 1564, |
| ARM_VQRSHLsv4i16 = 1565, |
| ARM_VQRSHLsv4i32 = 1566, |
| ARM_VQRSHLsv8i16 = 1567, |
| ARM_VQRSHLsv8i8 = 1568, |
| ARM_VQRSHLuv16i8 = 1569, |
| ARM_VQRSHLuv1i64 = 1570, |
| ARM_VQRSHLuv2i32 = 1571, |
| ARM_VQRSHLuv2i64 = 1572, |
| ARM_VQRSHLuv4i16 = 1573, |
| ARM_VQRSHLuv4i32 = 1574, |
| ARM_VQRSHLuv8i16 = 1575, |
| ARM_VQRSHLuv8i8 = 1576, |
| ARM_VQRSHRNsv2i32 = 1577, |
| ARM_VQRSHRNsv4i16 = 1578, |
| ARM_VQRSHRNsv8i8 = 1579, |
| ARM_VQRSHRNuv2i32 = 1580, |
| ARM_VQRSHRNuv4i16 = 1581, |
| ARM_VQRSHRNuv8i8 = 1582, |
| ARM_VQRSHRUNv2i32 = 1583, |
| ARM_VQRSHRUNv4i16 = 1584, |
| ARM_VQRSHRUNv8i8 = 1585, |
| ARM_VQSHLsiv16i8 = 1586, |
| ARM_VQSHLsiv1i64 = 1587, |
| ARM_VQSHLsiv2i32 = 1588, |
| ARM_VQSHLsiv2i64 = 1589, |
| ARM_VQSHLsiv4i16 = 1590, |
| ARM_VQSHLsiv4i32 = 1591, |
| ARM_VQSHLsiv8i16 = 1592, |
| ARM_VQSHLsiv8i8 = 1593, |
| ARM_VQSHLsuv16i8 = 1594, |
| ARM_VQSHLsuv1i64 = 1595, |
| ARM_VQSHLsuv2i32 = 1596, |
| ARM_VQSHLsuv2i64 = 1597, |
| ARM_VQSHLsuv4i16 = 1598, |
| ARM_VQSHLsuv4i32 = 1599, |
| ARM_VQSHLsuv8i16 = 1600, |
| ARM_VQSHLsuv8i8 = 1601, |
| ARM_VQSHLsv16i8 = 1602, |
| ARM_VQSHLsv1i64 = 1603, |
| ARM_VQSHLsv2i32 = 1604, |
| ARM_VQSHLsv2i64 = 1605, |
| ARM_VQSHLsv4i16 = 1606, |
| ARM_VQSHLsv4i32 = 1607, |
| ARM_VQSHLsv8i16 = 1608, |
| ARM_VQSHLsv8i8 = 1609, |
| ARM_VQSHLuiv16i8 = 1610, |
| ARM_VQSHLuiv1i64 = 1611, |
| ARM_VQSHLuiv2i32 = 1612, |
| ARM_VQSHLuiv2i64 = 1613, |
| ARM_VQSHLuiv4i16 = 1614, |
| ARM_VQSHLuiv4i32 = 1615, |
| ARM_VQSHLuiv8i16 = 1616, |
| ARM_VQSHLuiv8i8 = 1617, |
| ARM_VQSHLuv16i8 = 1618, |
| ARM_VQSHLuv1i64 = 1619, |
| ARM_VQSHLuv2i32 = 1620, |
| ARM_VQSHLuv2i64 = 1621, |
| ARM_VQSHLuv4i16 = 1622, |
| ARM_VQSHLuv4i32 = 1623, |
| ARM_VQSHLuv8i16 = 1624, |
| ARM_VQSHLuv8i8 = 1625, |
| ARM_VQSHRNsv2i32 = 1626, |
| ARM_VQSHRNsv4i16 = 1627, |
| ARM_VQSHRNsv8i8 = 1628, |
| ARM_VQSHRNuv2i32 = 1629, |
| ARM_VQSHRNuv4i16 = 1630, |
| ARM_VQSHRNuv8i8 = 1631, |
| ARM_VQSHRUNv2i32 = 1632, |
| ARM_VQSHRUNv4i16 = 1633, |
| ARM_VQSHRUNv8i8 = 1634, |
| ARM_VQSUBsv16i8 = 1635, |
| ARM_VQSUBsv1i64 = 1636, |
| ARM_VQSUBsv2i32 = 1637, |
| ARM_VQSUBsv2i64 = 1638, |
| ARM_VQSUBsv4i16 = 1639, |
| ARM_VQSUBsv4i32 = 1640, |
| ARM_VQSUBsv8i16 = 1641, |
| ARM_VQSUBsv8i8 = 1642, |
| ARM_VQSUBuv16i8 = 1643, |
| ARM_VQSUBuv1i64 = 1644, |
| ARM_VQSUBuv2i32 = 1645, |
| ARM_VQSUBuv2i64 = 1646, |
| ARM_VQSUBuv4i16 = 1647, |
| ARM_VQSUBuv4i32 = 1648, |
| ARM_VQSUBuv8i16 = 1649, |
| ARM_VQSUBuv8i8 = 1650, |
| ARM_VRADDHNv2i32 = 1651, |
| ARM_VRADDHNv4i16 = 1652, |
| ARM_VRADDHNv8i8 = 1653, |
| ARM_VRECPEd = 1654, |
| ARM_VRECPEfd = 1655, |
| ARM_VRECPEfq = 1656, |
| ARM_VRECPEq = 1657, |
| ARM_VRECPSfd = 1658, |
| ARM_VRECPSfq = 1659, |
| ARM_VREV16d8 = 1660, |
| ARM_VREV16q8 = 1661, |
| ARM_VREV32d16 = 1662, |
| ARM_VREV32d8 = 1663, |
| ARM_VREV32q16 = 1664, |
| ARM_VREV32q8 = 1665, |
| ARM_VREV64d16 = 1666, |
| ARM_VREV64d32 = 1667, |
| ARM_VREV64d8 = 1668, |
| ARM_VREV64q16 = 1669, |
| ARM_VREV64q32 = 1670, |
| ARM_VREV64q8 = 1671, |
| ARM_VRHADDsv16i8 = 1672, |
| ARM_VRHADDsv2i32 = 1673, |
| ARM_VRHADDsv4i16 = 1674, |
| ARM_VRHADDsv4i32 = 1675, |
| ARM_VRHADDsv8i16 = 1676, |
| ARM_VRHADDsv8i8 = 1677, |
| ARM_VRHADDuv16i8 = 1678, |
| ARM_VRHADDuv2i32 = 1679, |
| ARM_VRHADDuv4i16 = 1680, |
| ARM_VRHADDuv4i32 = 1681, |
| ARM_VRHADDuv8i16 = 1682, |
| ARM_VRHADDuv8i8 = 1683, |
| ARM_VRINTAD = 1684, |
| ARM_VRINTAND = 1685, |
| ARM_VRINTANQ = 1686, |
| ARM_VRINTAS = 1687, |
| ARM_VRINTMD = 1688, |
| ARM_VRINTMND = 1689, |
| ARM_VRINTMNQ = 1690, |
| ARM_VRINTMS = 1691, |
| ARM_VRINTND = 1692, |
| ARM_VRINTNND = 1693, |
| ARM_VRINTNNQ = 1694, |
| ARM_VRINTNS = 1695, |
| ARM_VRINTPD = 1696, |
| ARM_VRINTPND = 1697, |
| ARM_VRINTPNQ = 1698, |
| ARM_VRINTPS = 1699, |
| ARM_VRINTRD = 1700, |
| ARM_VRINTRS = 1701, |
| ARM_VRINTXD = 1702, |
| ARM_VRINTXND = 1703, |
| ARM_VRINTXNQ = 1704, |
| ARM_VRINTXS = 1705, |
| ARM_VRINTZD = 1706, |
| ARM_VRINTZND = 1707, |
| ARM_VRINTZNQ = 1708, |
| ARM_VRINTZS = 1709, |
| ARM_VRSHLsv16i8 = 1710, |
| ARM_VRSHLsv1i64 = 1711, |
| ARM_VRSHLsv2i32 = 1712, |
| ARM_VRSHLsv2i64 = 1713, |
| ARM_VRSHLsv4i16 = 1714, |
| ARM_VRSHLsv4i32 = 1715, |
| ARM_VRSHLsv8i16 = 1716, |
| ARM_VRSHLsv8i8 = 1717, |
| ARM_VRSHLuv16i8 = 1718, |
| ARM_VRSHLuv1i64 = 1719, |
| ARM_VRSHLuv2i32 = 1720, |
| ARM_VRSHLuv2i64 = 1721, |
| ARM_VRSHLuv4i16 = 1722, |
| ARM_VRSHLuv4i32 = 1723, |
| ARM_VRSHLuv8i16 = 1724, |
| ARM_VRSHLuv8i8 = 1725, |
| ARM_VRSHRNv2i32 = 1726, |
| ARM_VRSHRNv4i16 = 1727, |
| ARM_VRSHRNv8i8 = 1728, |
| ARM_VRSHRsv16i8 = 1729, |
| ARM_VRSHRsv1i64 = 1730, |
| ARM_VRSHRsv2i32 = 1731, |
| ARM_VRSHRsv2i64 = 1732, |
| ARM_VRSHRsv4i16 = 1733, |
| ARM_VRSHRsv4i32 = 1734, |
| ARM_VRSHRsv8i16 = 1735, |
| ARM_VRSHRsv8i8 = 1736, |
| ARM_VRSHRuv16i8 = 1737, |
| ARM_VRSHRuv1i64 = 1738, |
| ARM_VRSHRuv2i32 = 1739, |
| ARM_VRSHRuv2i64 = 1740, |
| ARM_VRSHRuv4i16 = 1741, |
| ARM_VRSHRuv4i32 = 1742, |
| ARM_VRSHRuv8i16 = 1743, |
| ARM_VRSHRuv8i8 = 1744, |
| ARM_VRSQRTEd = 1745, |
| ARM_VRSQRTEfd = 1746, |
| ARM_VRSQRTEfq = 1747, |
| ARM_VRSQRTEq = 1748, |
| ARM_VRSQRTSfd = 1749, |
| ARM_VRSQRTSfq = 1750, |
| ARM_VRSRAsv16i8 = 1751, |
| ARM_VRSRAsv1i64 = 1752, |
| ARM_VRSRAsv2i32 = 1753, |
| ARM_VRSRAsv2i64 = 1754, |
| ARM_VRSRAsv4i16 = 1755, |
| ARM_VRSRAsv4i32 = 1756, |
| ARM_VRSRAsv8i16 = 1757, |
| ARM_VRSRAsv8i8 = 1758, |
| ARM_VRSRAuv16i8 = 1759, |
| ARM_VRSRAuv1i64 = 1760, |
| ARM_VRSRAuv2i32 = 1761, |
| ARM_VRSRAuv2i64 = 1762, |
| ARM_VRSRAuv4i16 = 1763, |
| ARM_VRSRAuv4i32 = 1764, |
| ARM_VRSRAuv8i16 = 1765, |
| ARM_VRSRAuv8i8 = 1766, |
| ARM_VRSUBHNv2i32 = 1767, |
| ARM_VRSUBHNv4i16 = 1768, |
| ARM_VRSUBHNv8i8 = 1769, |
| ARM_VSELEQD = 1770, |
| ARM_VSELEQS = 1771, |
| ARM_VSELGED = 1772, |
| ARM_VSELGES = 1773, |
| ARM_VSELGTD = 1774, |
| ARM_VSELGTS = 1775, |
| ARM_VSELVSD = 1776, |
| ARM_VSELVSS = 1777, |
| ARM_VSETLNi16 = 1778, |
| ARM_VSETLNi32 = 1779, |
| ARM_VSETLNi8 = 1780, |
| ARM_VSHLLi16 = 1781, |
| ARM_VSHLLi32 = 1782, |
| ARM_VSHLLi8 = 1783, |
| ARM_VSHLLsv2i64 = 1784, |
| ARM_VSHLLsv4i32 = 1785, |
| ARM_VSHLLsv8i16 = 1786, |
| ARM_VSHLLuv2i64 = 1787, |
| ARM_VSHLLuv4i32 = 1788, |
| ARM_VSHLLuv8i16 = 1789, |
| ARM_VSHLiv16i8 = 1790, |
| ARM_VSHLiv1i64 = 1791, |
| ARM_VSHLiv2i32 = 1792, |
| ARM_VSHLiv2i64 = 1793, |
| ARM_VSHLiv4i16 = 1794, |
| ARM_VSHLiv4i32 = 1795, |
| ARM_VSHLiv8i16 = 1796, |
| ARM_VSHLiv8i8 = 1797, |
| ARM_VSHLsv16i8 = 1798, |
| ARM_VSHLsv1i64 = 1799, |
| ARM_VSHLsv2i32 = 1800, |
| ARM_VSHLsv2i64 = 1801, |
| ARM_VSHLsv4i16 = 1802, |
| ARM_VSHLsv4i32 = 1803, |
| ARM_VSHLsv8i16 = 1804, |
| ARM_VSHLsv8i8 = 1805, |
| ARM_VSHLuv16i8 = 1806, |
| ARM_VSHLuv1i64 = 1807, |
| ARM_VSHLuv2i32 = 1808, |
| ARM_VSHLuv2i64 = 1809, |
| ARM_VSHLuv4i16 = 1810, |
| ARM_VSHLuv4i32 = 1811, |
| ARM_VSHLuv8i16 = 1812, |
| ARM_VSHLuv8i8 = 1813, |
| ARM_VSHRNv2i32 = 1814, |
| ARM_VSHRNv4i16 = 1815, |
| ARM_VSHRNv8i8 = 1816, |
| ARM_VSHRsv16i8 = 1817, |
| ARM_VSHRsv1i64 = 1818, |
| ARM_VSHRsv2i32 = 1819, |
| ARM_VSHRsv2i64 = 1820, |
| ARM_VSHRsv4i16 = 1821, |
| ARM_VSHRsv4i32 = 1822, |
| ARM_VSHRsv8i16 = 1823, |
| ARM_VSHRsv8i8 = 1824, |
| ARM_VSHRuv16i8 = 1825, |
| ARM_VSHRuv1i64 = 1826, |
| ARM_VSHRuv2i32 = 1827, |
| ARM_VSHRuv2i64 = 1828, |
| ARM_VSHRuv4i16 = 1829, |
| ARM_VSHRuv4i32 = 1830, |
| ARM_VSHRuv8i16 = 1831, |
| ARM_VSHRuv8i8 = 1832, |
| ARM_VSHTOD = 1833, |
| ARM_VSHTOS = 1834, |
| ARM_VSITOD = 1835, |
| ARM_VSITOS = 1836, |
| ARM_VSLIv16i8 = 1837, |
| ARM_VSLIv1i64 = 1838, |
| ARM_VSLIv2i32 = 1839, |
| ARM_VSLIv2i64 = 1840, |
| ARM_VSLIv4i16 = 1841, |
| ARM_VSLIv4i32 = 1842, |
| ARM_VSLIv8i16 = 1843, |
| ARM_VSLIv8i8 = 1844, |
| ARM_VSLTOD = 1845, |
| ARM_VSLTOS = 1846, |
| ARM_VSQRTD = 1847, |
| ARM_VSQRTS = 1848, |
| ARM_VSRAsv16i8 = 1849, |
| ARM_VSRAsv1i64 = 1850, |
| ARM_VSRAsv2i32 = 1851, |
| ARM_VSRAsv2i64 = 1852, |
| ARM_VSRAsv4i16 = 1853, |
| ARM_VSRAsv4i32 = 1854, |
| ARM_VSRAsv8i16 = 1855, |
| ARM_VSRAsv8i8 = 1856, |
| ARM_VSRAuv16i8 = 1857, |
| ARM_VSRAuv1i64 = 1858, |
| ARM_VSRAuv2i32 = 1859, |
| ARM_VSRAuv2i64 = 1860, |
| ARM_VSRAuv4i16 = 1861, |
| ARM_VSRAuv4i32 = 1862, |
| ARM_VSRAuv8i16 = 1863, |
| ARM_VSRAuv8i8 = 1864, |
| ARM_VSRIv16i8 = 1865, |
| ARM_VSRIv1i64 = 1866, |
| ARM_VSRIv2i32 = 1867, |
| ARM_VSRIv2i64 = 1868, |
| ARM_VSRIv4i16 = 1869, |
| ARM_VSRIv4i32 = 1870, |
| ARM_VSRIv8i16 = 1871, |
| ARM_VSRIv8i8 = 1872, |
| ARM_VST1LNd16 = 1873, |
| ARM_VST1LNd16_UPD = 1874, |
| ARM_VST1LNd32 = 1875, |
| ARM_VST1LNd32_UPD = 1876, |
| ARM_VST1LNd8 = 1877, |
| ARM_VST1LNd8_UPD = 1878, |
| ARM_VST1LNdAsm_16 = 1879, |
| ARM_VST1LNdAsm_32 = 1880, |
| ARM_VST1LNdAsm_8 = 1881, |
| ARM_VST1LNdWB_fixed_Asm_16 = 1882, |
| ARM_VST1LNdWB_fixed_Asm_32 = 1883, |
| ARM_VST1LNdWB_fixed_Asm_8 = 1884, |
| ARM_VST1LNdWB_register_Asm_16 = 1885, |
| ARM_VST1LNdWB_register_Asm_32 = 1886, |
| ARM_VST1LNdWB_register_Asm_8 = 1887, |
| ARM_VST1LNq16Pseudo = 1888, |
| ARM_VST1LNq16Pseudo_UPD = 1889, |
| ARM_VST1LNq32Pseudo = 1890, |
| ARM_VST1LNq32Pseudo_UPD = 1891, |
| ARM_VST1LNq8Pseudo = 1892, |
| ARM_VST1LNq8Pseudo_UPD = 1893, |
| ARM_VST1d16 = 1894, |
| ARM_VST1d16Q = 1895, |
| ARM_VST1d16Qwb_fixed = 1896, |
| ARM_VST1d16Qwb_register = 1897, |
| ARM_VST1d16T = 1898, |
| ARM_VST1d16Twb_fixed = 1899, |
| ARM_VST1d16Twb_register = 1900, |
| ARM_VST1d16wb_fixed = 1901, |
| ARM_VST1d16wb_register = 1902, |
| ARM_VST1d32 = 1903, |
| ARM_VST1d32Q = 1904, |
| ARM_VST1d32Qwb_fixed = 1905, |
| ARM_VST1d32Qwb_register = 1906, |
| ARM_VST1d32T = 1907, |
| ARM_VST1d32Twb_fixed = 1908, |
| ARM_VST1d32Twb_register = 1909, |
| ARM_VST1d32wb_fixed = 1910, |
| ARM_VST1d32wb_register = 1911, |
| ARM_VST1d64 = 1912, |
| ARM_VST1d64Q = 1913, |
| ARM_VST1d64QPseudo = 1914, |
| ARM_VST1d64QPseudoWB_fixed = 1915, |
| ARM_VST1d64QPseudoWB_register = 1916, |
| ARM_VST1d64Qwb_fixed = 1917, |
| ARM_VST1d64Qwb_register = 1918, |
| ARM_VST1d64T = 1919, |
| ARM_VST1d64TPseudo = 1920, |
| ARM_VST1d64TPseudoWB_fixed = 1921, |
| ARM_VST1d64TPseudoWB_register = 1922, |
| ARM_VST1d64Twb_fixed = 1923, |
| ARM_VST1d64Twb_register = 1924, |
| ARM_VST1d64wb_fixed = 1925, |
| ARM_VST1d64wb_register = 1926, |
| ARM_VST1d8 = 1927, |
| ARM_VST1d8Q = 1928, |
| ARM_VST1d8Qwb_fixed = 1929, |
| ARM_VST1d8Qwb_register = 1930, |
| ARM_VST1d8T = 1931, |
| ARM_VST1d8Twb_fixed = 1932, |
| ARM_VST1d8Twb_register = 1933, |
| ARM_VST1d8wb_fixed = 1934, |
| ARM_VST1d8wb_register = 1935, |
| ARM_VST1q16 = 1936, |
| ARM_VST1q16wb_fixed = 1937, |
| ARM_VST1q16wb_register = 1938, |
| ARM_VST1q32 = 1939, |
| ARM_VST1q32wb_fixed = 1940, |
| ARM_VST1q32wb_register = 1941, |
| ARM_VST1q64 = 1942, |
| ARM_VST1q64wb_fixed = 1943, |
| ARM_VST1q64wb_register = 1944, |
| ARM_VST1q8 = 1945, |
| ARM_VST1q8wb_fixed = 1946, |
| ARM_VST1q8wb_register = 1947, |
| ARM_VST2LNd16 = 1948, |
| ARM_VST2LNd16Pseudo = 1949, |
| ARM_VST2LNd16Pseudo_UPD = 1950, |
| ARM_VST2LNd16_UPD = 1951, |
| ARM_VST2LNd32 = 1952, |
| ARM_VST2LNd32Pseudo = 1953, |
| ARM_VST2LNd32Pseudo_UPD = 1954, |
| ARM_VST2LNd32_UPD = 1955, |
| ARM_VST2LNd8 = 1956, |
| ARM_VST2LNd8Pseudo = 1957, |
| ARM_VST2LNd8Pseudo_UPD = 1958, |
| ARM_VST2LNd8_UPD = 1959, |
| ARM_VST2LNdAsm_16 = 1960, |
| ARM_VST2LNdAsm_32 = 1961, |
| ARM_VST2LNdAsm_8 = 1962, |
| ARM_VST2LNdWB_fixed_Asm_16 = 1963, |
| ARM_VST2LNdWB_fixed_Asm_32 = 1964, |
| ARM_VST2LNdWB_fixed_Asm_8 = 1965, |
| ARM_VST2LNdWB_register_Asm_16 = 1966, |
| ARM_VST2LNdWB_register_Asm_32 = 1967, |
| ARM_VST2LNdWB_register_Asm_8 = 1968, |
| ARM_VST2LNq16 = 1969, |
| ARM_VST2LNq16Pseudo = 1970, |
| ARM_VST2LNq16Pseudo_UPD = 1971, |
| ARM_VST2LNq16_UPD = 1972, |
| ARM_VST2LNq32 = 1973, |
| ARM_VST2LNq32Pseudo = 1974, |
| ARM_VST2LNq32Pseudo_UPD = 1975, |
| ARM_VST2LNq32_UPD = 1976, |
| ARM_VST2LNqAsm_16 = 1977, |
| ARM_VST2LNqAsm_32 = 1978, |
| ARM_VST2LNqWB_fixed_Asm_16 = 1979, |
| ARM_VST2LNqWB_fixed_Asm_32 = 1980, |
| ARM_VST2LNqWB_register_Asm_16 = 1981, |
| ARM_VST2LNqWB_register_Asm_32 = 1982, |
| ARM_VST2b16 = 1983, |
| ARM_VST2b16wb_fixed = 1984, |
| ARM_VST2b16wb_register = 1985, |
| ARM_VST2b32 = 1986, |
| ARM_VST2b32wb_fixed = 1987, |
| ARM_VST2b32wb_register = 1988, |
| ARM_VST2b8 = 1989, |
| ARM_VST2b8wb_fixed = 1990, |
| ARM_VST2b8wb_register = 1991, |
| ARM_VST2d16 = 1992, |
| ARM_VST2d16wb_fixed = 1993, |
| ARM_VST2d16wb_register = 1994, |
| ARM_VST2d32 = 1995, |
| ARM_VST2d32wb_fixed = 1996, |
| ARM_VST2d32wb_register = 1997, |
| ARM_VST2d8 = 1998, |
| ARM_VST2d8wb_fixed = 1999, |
| ARM_VST2d8wb_register = 2000, |
| ARM_VST2q16 = 2001, |
| ARM_VST2q16Pseudo = 2002, |
| ARM_VST2q16PseudoWB_fixed = 2003, |
| ARM_VST2q16PseudoWB_register = 2004, |
| ARM_VST2q16wb_fixed = 2005, |
| ARM_VST2q16wb_register = 2006, |
| ARM_VST2q32 = 2007, |
| ARM_VST2q32Pseudo = 2008, |
| ARM_VST2q32PseudoWB_fixed = 2009, |
| ARM_VST2q32PseudoWB_register = 2010, |
| ARM_VST2q32wb_fixed = 2011, |
| ARM_VST2q32wb_register = 2012, |
| ARM_VST2q8 = 2013, |
| ARM_VST2q8Pseudo = 2014, |
| ARM_VST2q8PseudoWB_fixed = 2015, |
| ARM_VST2q8PseudoWB_register = 2016, |
| ARM_VST2q8wb_fixed = 2017, |
| ARM_VST2q8wb_register = 2018, |
| ARM_VST3LNd16 = 2019, |
| ARM_VST3LNd16Pseudo = 2020, |
| ARM_VST3LNd16Pseudo_UPD = 2021, |
| ARM_VST3LNd16_UPD = 2022, |
| ARM_VST3LNd32 = 2023, |
| ARM_VST3LNd32Pseudo = 2024, |
| ARM_VST3LNd32Pseudo_UPD = 2025, |
| ARM_VST3LNd32_UPD = 2026, |
| ARM_VST3LNd8 = 2027, |
| ARM_VST3LNd8Pseudo = 2028, |
| ARM_VST3LNd8Pseudo_UPD = 2029, |
| ARM_VST3LNd8_UPD = 2030, |
| ARM_VST3LNdAsm_16 = 2031, |
| ARM_VST3LNdAsm_32 = 2032, |
| ARM_VST3LNdAsm_8 = 2033, |
| ARM_VST3LNdWB_fixed_Asm_16 = 2034, |
| ARM_VST3LNdWB_fixed_Asm_32 = 2035, |
| ARM_VST3LNdWB_fixed_Asm_8 = 2036, |
| ARM_VST3LNdWB_register_Asm_16 = 2037, |
| ARM_VST3LNdWB_register_Asm_32 = 2038, |
| ARM_VST3LNdWB_register_Asm_8 = 2039, |
| ARM_VST3LNq16 = 2040, |
| ARM_VST3LNq16Pseudo = 2041, |
| ARM_VST3LNq16Pseudo_UPD = 2042, |
| ARM_VST3LNq16_UPD = 2043, |
| ARM_VST3LNq32 = 2044, |
| ARM_VST3LNq32Pseudo = 2045, |
| ARM_VST3LNq32Pseudo_UPD = 2046, |
| ARM_VST3LNq32_UPD = 2047, |
| ARM_VST3LNqAsm_16 = 2048, |
| ARM_VST3LNqAsm_32 = 2049, |
| ARM_VST3LNqWB_fixed_Asm_16 = 2050, |
| ARM_VST3LNqWB_fixed_Asm_32 = 2051, |
| ARM_VST3LNqWB_register_Asm_16 = 2052, |
| ARM_VST3LNqWB_register_Asm_32 = 2053, |
| ARM_VST3d16 = 2054, |
| ARM_VST3d16Pseudo = 2055, |
| ARM_VST3d16Pseudo_UPD = 2056, |
| ARM_VST3d16_UPD = 2057, |
| ARM_VST3d32 = 2058, |
| ARM_VST3d32Pseudo = 2059, |
| ARM_VST3d32Pseudo_UPD = 2060, |
| ARM_VST3d32_UPD = 2061, |
| ARM_VST3d8 = 2062, |
| ARM_VST3d8Pseudo = 2063, |
| ARM_VST3d8Pseudo_UPD = 2064, |
| ARM_VST3d8_UPD = 2065, |
| ARM_VST3dAsm_16 = 2066, |
| ARM_VST3dAsm_32 = 2067, |
| ARM_VST3dAsm_8 = 2068, |
| ARM_VST3dWB_fixed_Asm_16 = 2069, |
| ARM_VST3dWB_fixed_Asm_32 = 2070, |
| ARM_VST3dWB_fixed_Asm_8 = 2071, |
| ARM_VST3dWB_register_Asm_16 = 2072, |
| ARM_VST3dWB_register_Asm_32 = 2073, |
| ARM_VST3dWB_register_Asm_8 = 2074, |
| ARM_VST3q16 = 2075, |
| ARM_VST3q16Pseudo_UPD = 2076, |
| ARM_VST3q16_UPD = 2077, |
| ARM_VST3q16oddPseudo = 2078, |
| ARM_VST3q16oddPseudo_UPD = 2079, |
| ARM_VST3q32 = 2080, |
| ARM_VST3q32Pseudo_UPD = 2081, |
| ARM_VST3q32_UPD = 2082, |
| ARM_VST3q32oddPseudo = 2083, |
| ARM_VST3q32oddPseudo_UPD = 2084, |
| ARM_VST3q8 = 2085, |
| ARM_VST3q8Pseudo_UPD = 2086, |
| ARM_VST3q8_UPD = 2087, |
| ARM_VST3q8oddPseudo = 2088, |
| ARM_VST3q8oddPseudo_UPD = 2089, |
| ARM_VST3qAsm_16 = 2090, |
| ARM_VST3qAsm_32 = 2091, |
| ARM_VST3qAsm_8 = 2092, |
| ARM_VST3qWB_fixed_Asm_16 = 2093, |
| ARM_VST3qWB_fixed_Asm_32 = 2094, |
| ARM_VST3qWB_fixed_Asm_8 = 2095, |
| ARM_VST3qWB_register_Asm_16 = 2096, |
| ARM_VST3qWB_register_Asm_32 = 2097, |
| ARM_VST3qWB_register_Asm_8 = 2098, |
| ARM_VST4LNd16 = 2099, |
| ARM_VST4LNd16Pseudo = 2100, |
| ARM_VST4LNd16Pseudo_UPD = 2101, |
| ARM_VST4LNd16_UPD = 2102, |
| ARM_VST4LNd32 = 2103, |
| ARM_VST4LNd32Pseudo = 2104, |
| ARM_VST4LNd32Pseudo_UPD = 2105, |
| ARM_VST4LNd32_UPD = 2106, |
| ARM_VST4LNd8 = 2107, |
| ARM_VST4LNd8Pseudo = 2108, |
| ARM_VST4LNd8Pseudo_UPD = 2109, |
| ARM_VST4LNd8_UPD = 2110, |
| ARM_VST4LNdAsm_16 = 2111, |
| ARM_VST4LNdAsm_32 = 2112, |
| ARM_VST4LNdAsm_8 = 2113, |
| ARM_VST4LNdWB_fixed_Asm_16 = 2114, |
| ARM_VST4LNdWB_fixed_Asm_32 = 2115, |
| ARM_VST4LNdWB_fixed_Asm_8 = 2116, |
| ARM_VST4LNdWB_register_Asm_16 = 2117, |
| ARM_VST4LNdWB_register_Asm_32 = 2118, |
| ARM_VST4LNdWB_register_Asm_8 = 2119, |
| ARM_VST4LNq16 = 2120, |
| ARM_VST4LNq16Pseudo = 2121, |
| ARM_VST4LNq16Pseudo_UPD = 2122, |
| ARM_VST4LNq16_UPD = 2123, |
| ARM_VST4LNq32 = 2124, |
| ARM_VST4LNq32Pseudo = 2125, |
| ARM_VST4LNq32Pseudo_UPD = 2126, |
| ARM_VST4LNq32_UPD = 2127, |
| ARM_VST4LNqAsm_16 = 2128, |
| ARM_VST4LNqAsm_32 = 2129, |
| ARM_VST4LNqWB_fixed_Asm_16 = 2130, |
| ARM_VST4LNqWB_fixed_Asm_32 = 2131, |
| ARM_VST4LNqWB_register_Asm_16 = 2132, |
| ARM_VST4LNqWB_register_Asm_32 = 2133, |
| ARM_VST4d16 = 2134, |
| ARM_VST4d16Pseudo = 2135, |
| ARM_VST4d16Pseudo_UPD = 2136, |
| ARM_VST4d16_UPD = 2137, |
| ARM_VST4d32 = 2138, |
| ARM_VST4d32Pseudo = 2139, |
| ARM_VST4d32Pseudo_UPD = 2140, |
| ARM_VST4d32_UPD = 2141, |
| ARM_VST4d8 = 2142, |
| ARM_VST4d8Pseudo = 2143, |
| ARM_VST4d8Pseudo_UPD = 2144, |
| ARM_VST4d8_UPD = 2145, |
| ARM_VST4dAsm_16 = 2146, |
| ARM_VST4dAsm_32 = 2147, |
| ARM_VST4dAsm_8 = 2148, |
| ARM_VST4dWB_fixed_Asm_16 = 2149, |
| ARM_VST4dWB_fixed_Asm_32 = 2150, |
| ARM_VST4dWB_fixed_Asm_8 = 2151, |
| ARM_VST4dWB_register_Asm_16 = 2152, |
| ARM_VST4dWB_register_Asm_32 = 2153, |
| ARM_VST4dWB_register_Asm_8 = 2154, |
| ARM_VST4q16 = 2155, |
| ARM_VST4q16Pseudo_UPD = 2156, |
| ARM_VST4q16_UPD = 2157, |
| ARM_VST4q16oddPseudo = 2158, |
| ARM_VST4q16oddPseudo_UPD = 2159, |
| ARM_VST4q32 = 2160, |
| ARM_VST4q32Pseudo_UPD = 2161, |
| ARM_VST4q32_UPD = 2162, |
| ARM_VST4q32oddPseudo = 2163, |
| ARM_VST4q32oddPseudo_UPD = 2164, |
| ARM_VST4q8 = 2165, |
| ARM_VST4q8Pseudo_UPD = 2166, |
| ARM_VST4q8_UPD = 2167, |
| ARM_VST4q8oddPseudo = 2168, |
| ARM_VST4q8oddPseudo_UPD = 2169, |
| ARM_VST4qAsm_16 = 2170, |
| ARM_VST4qAsm_32 = 2171, |
| ARM_VST4qAsm_8 = 2172, |
| ARM_VST4qWB_fixed_Asm_16 = 2173, |
| ARM_VST4qWB_fixed_Asm_32 = 2174, |
| ARM_VST4qWB_fixed_Asm_8 = 2175, |
| ARM_VST4qWB_register_Asm_16 = 2176, |
| ARM_VST4qWB_register_Asm_32 = 2177, |
| ARM_VST4qWB_register_Asm_8 = 2178, |
| ARM_VSTMDDB_UPD = 2179, |
| ARM_VSTMDIA = 2180, |
| ARM_VSTMDIA_UPD = 2181, |
| ARM_VSTMQIA = 2182, |
| ARM_VSTMSDB_UPD = 2183, |
| ARM_VSTMSIA = 2184, |
| ARM_VSTMSIA_UPD = 2185, |
| ARM_VSTRD = 2186, |
| ARM_VSTRS = 2187, |
| ARM_VSUBD = 2188, |
| ARM_VSUBHNv2i32 = 2189, |
| ARM_VSUBHNv4i16 = 2190, |
| ARM_VSUBHNv8i8 = 2191, |
| ARM_VSUBLsv2i64 = 2192, |
| ARM_VSUBLsv4i32 = 2193, |
| ARM_VSUBLsv8i16 = 2194, |
| ARM_VSUBLuv2i64 = 2195, |
| ARM_VSUBLuv4i32 = 2196, |
| ARM_VSUBLuv8i16 = 2197, |
| ARM_VSUBS = 2198, |
| ARM_VSUBWsv2i64 = 2199, |
| ARM_VSUBWsv4i32 = 2200, |
| ARM_VSUBWsv8i16 = 2201, |
| ARM_VSUBWuv2i64 = 2202, |
| ARM_VSUBWuv4i32 = 2203, |
| ARM_VSUBWuv8i16 = 2204, |
| ARM_VSUBfd = 2205, |
| ARM_VSUBfq = 2206, |
| ARM_VSUBv16i8 = 2207, |
| ARM_VSUBv1i64 = 2208, |
| ARM_VSUBv2i32 = 2209, |
| ARM_VSUBv2i64 = 2210, |
| ARM_VSUBv4i16 = 2211, |
| ARM_VSUBv4i32 = 2212, |
| ARM_VSUBv8i16 = 2213, |
| ARM_VSUBv8i8 = 2214, |
| ARM_VSWPd = 2215, |
| ARM_VSWPq = 2216, |
| ARM_VTBL1 = 2217, |
| ARM_VTBL2 = 2218, |
| ARM_VTBL3 = 2219, |
| ARM_VTBL3Pseudo = 2220, |
| ARM_VTBL4 = 2221, |
| ARM_VTBL4Pseudo = 2222, |
| ARM_VTBX1 = 2223, |
| ARM_VTBX2 = 2224, |
| ARM_VTBX3 = 2225, |
| ARM_VTBX3Pseudo = 2226, |
| ARM_VTBX4 = 2227, |
| ARM_VTBX4Pseudo = 2228, |
| ARM_VTOSHD = 2229, |
| ARM_VTOSHS = 2230, |
| ARM_VTOSIRD = 2231, |
| ARM_VTOSIRS = 2232, |
| ARM_VTOSIZD = 2233, |
| ARM_VTOSIZS = 2234, |
| ARM_VTOSLD = 2235, |
| ARM_VTOSLS = 2236, |
| ARM_VTOUHD = 2237, |
| ARM_VTOUHS = 2238, |
| ARM_VTOUIRD = 2239, |
| ARM_VTOUIRS = 2240, |
| ARM_VTOUIZD = 2241, |
| ARM_VTOUIZS = 2242, |
| ARM_VTOULD = 2243, |
| ARM_VTOULS = 2244, |
| ARM_VTRNd16 = 2245, |
| ARM_VTRNd32 = 2246, |
| ARM_VTRNd8 = 2247, |
| ARM_VTRNq16 = 2248, |
| ARM_VTRNq32 = 2249, |
| ARM_VTRNq8 = 2250, |
| ARM_VTSTv16i8 = 2251, |
| ARM_VTSTv2i32 = 2252, |
| ARM_VTSTv4i16 = 2253, |
| ARM_VTSTv4i32 = 2254, |
| ARM_VTSTv8i16 = 2255, |
| ARM_VTSTv8i8 = 2256, |
| ARM_VUHTOD = 2257, |
| ARM_VUHTOS = 2258, |
| ARM_VUITOD = 2259, |
| ARM_VUITOS = 2260, |
| ARM_VULTOD = 2261, |
| ARM_VULTOS = 2262, |
| ARM_VUZPd16 = 2263, |
| ARM_VUZPd8 = 2264, |
| ARM_VUZPq16 = 2265, |
| ARM_VUZPq32 = 2266, |
| ARM_VUZPq8 = 2267, |
| ARM_VZIPd16 = 2268, |
| ARM_VZIPd8 = 2269, |
| ARM_VZIPq16 = 2270, |
| ARM_VZIPq32 = 2271, |
| ARM_VZIPq8 = 2272, |
| ARM_WIN__CHKSTK = 2273, |
| ARM_sysLDMDA = 2274, |
| ARM_sysLDMDA_UPD = 2275, |
| ARM_sysLDMDB = 2276, |
| ARM_sysLDMDB_UPD = 2277, |
| ARM_sysLDMIA = 2278, |
| ARM_sysLDMIA_UPD = 2279, |
| ARM_sysLDMIB = 2280, |
| ARM_sysLDMIB_UPD = 2281, |
| ARM_sysSTMDA = 2282, |
| ARM_sysSTMDA_UPD = 2283, |
| ARM_sysSTMDB = 2284, |
| ARM_sysSTMDB_UPD = 2285, |
| ARM_sysSTMIA = 2286, |
| ARM_sysSTMIA_UPD = 2287, |
| ARM_sysSTMIB = 2288, |
| ARM_sysSTMIB_UPD = 2289, |
| ARM_t2ABS = 2290, |
| ARM_t2ADCri = 2291, |
| ARM_t2ADCrr = 2292, |
| ARM_t2ADCrs = 2293, |
| ARM_t2ADDSri = 2294, |
| ARM_t2ADDSrr = 2295, |
| ARM_t2ADDSrs = 2296, |
| ARM_t2ADDri = 2297, |
| ARM_t2ADDri12 = 2298, |
| ARM_t2ADDrr = 2299, |
| ARM_t2ADDrs = 2300, |
| ARM_t2ADR = 2301, |
| ARM_t2ANDri = 2302, |
| ARM_t2ANDrr = 2303, |
| ARM_t2ANDrs = 2304, |
| ARM_t2ASRri = 2305, |
| ARM_t2ASRrr = 2306, |
| ARM_t2B = 2307, |
| ARM_t2BFC = 2308, |
| ARM_t2BFI = 2309, |
| ARM_t2BICri = 2310, |
| ARM_t2BICrr = 2311, |
| ARM_t2BICrs = 2312, |
| ARM_t2BR_JT = 2313, |
| ARM_t2BXJ = 2314, |
| ARM_t2Bcc = 2315, |
| ARM_t2CDP = 2316, |
| ARM_t2CDP2 = 2317, |
| ARM_t2CLREX = 2318, |
| ARM_t2CLZ = 2319, |
| ARM_t2CMNri = 2320, |
| ARM_t2CMNzrr = 2321, |
| ARM_t2CMNzrs = 2322, |
| ARM_t2CMPri = 2323, |
| ARM_t2CMPrr = 2324, |
| ARM_t2CMPrs = 2325, |
| ARM_t2CPS1p = 2326, |
| ARM_t2CPS2p = 2327, |
| ARM_t2CPS3p = 2328, |
| ARM_t2CRC32B = 2329, |
| ARM_t2CRC32CB = 2330, |
| ARM_t2CRC32CH = 2331, |
| ARM_t2CRC32CW = 2332, |
| ARM_t2CRC32H = 2333, |
| ARM_t2CRC32W = 2334, |
| ARM_t2DBG = 2335, |
| ARM_t2DCPS1 = 2336, |
| ARM_t2DCPS2 = 2337, |
| ARM_t2DCPS3 = 2338, |
| ARM_t2DMB = 2339, |
| ARM_t2DSB = 2340, |
| ARM_t2EORri = 2341, |
| ARM_t2EORrr = 2342, |
| ARM_t2EORrs = 2343, |
| ARM_t2HINT = 2344, |
| ARM_t2HVC = 2345, |
| ARM_t2ISB = 2346, |
| ARM_t2IT = 2347, |
| ARM_t2Int_eh_sjlj_setjmp = 2348, |
| ARM_t2Int_eh_sjlj_setjmp_nofp = 2349, |
| ARM_t2LDA = 2350, |
| ARM_t2LDAB = 2351, |
| ARM_t2LDAEX = 2352, |
| ARM_t2LDAEXB = 2353, |
| ARM_t2LDAEXD = 2354, |
| ARM_t2LDAEXH = 2355, |
| ARM_t2LDAH = 2356, |
| ARM_t2LDC2L_OFFSET = 2357, |
| ARM_t2LDC2L_OPTION = 2358, |
| ARM_t2LDC2L_POST = 2359, |
| ARM_t2LDC2L_PRE = 2360, |
| ARM_t2LDC2_OFFSET = 2361, |
| ARM_t2LDC2_OPTION = 2362, |
| ARM_t2LDC2_POST = 2363, |
| ARM_t2LDC2_PRE = 2364, |
| ARM_t2LDCL_OFFSET = 2365, |
| ARM_t2LDCL_OPTION = 2366, |
| ARM_t2LDCL_POST = 2367, |
| ARM_t2LDCL_PRE = 2368, |
| ARM_t2LDC_OFFSET = 2369, |
| ARM_t2LDC_OPTION = 2370, |
| ARM_t2LDC_POST = 2371, |
| ARM_t2LDC_PRE = 2372, |
| ARM_t2LDMDB = 2373, |
| ARM_t2LDMDB_UPD = 2374, |
| ARM_t2LDMIA = 2375, |
| ARM_t2LDMIA_RET = 2376, |
| ARM_t2LDMIA_UPD = 2377, |
| ARM_t2LDRBT = 2378, |
| ARM_t2LDRB_POST = 2379, |
| ARM_t2LDRB_PRE = 2380, |
| ARM_t2LDRBi12 = 2381, |
| ARM_t2LDRBi8 = 2382, |
| ARM_t2LDRBpci = 2383, |
| ARM_t2LDRBpcrel = 2384, |
| ARM_t2LDRBs = 2385, |
| ARM_t2LDRD_POST = 2386, |
| ARM_t2LDRD_PRE = 2387, |
| ARM_t2LDRDi8 = 2388, |
| ARM_t2LDREX = 2389, |
| ARM_t2LDREXB = 2390, |
| ARM_t2LDREXD = 2391, |
| ARM_t2LDREXH = 2392, |
| ARM_t2LDRHT = 2393, |
| ARM_t2LDRH_POST = 2394, |
| ARM_t2LDRH_PRE = 2395, |
| ARM_t2LDRHi12 = 2396, |
| ARM_t2LDRHi8 = 2397, |
| ARM_t2LDRHpci = 2398, |
| ARM_t2LDRHpcrel = 2399, |
| ARM_t2LDRHs = 2400, |
| ARM_t2LDRSBT = 2401, |
| ARM_t2LDRSB_POST = 2402, |
| ARM_t2LDRSB_PRE = 2403, |
| ARM_t2LDRSBi12 = 2404, |
| ARM_t2LDRSBi8 = 2405, |
| ARM_t2LDRSBpci = 2406, |
| ARM_t2LDRSBpcrel = 2407, |
| ARM_t2LDRSBs = 2408, |
| ARM_t2LDRSHT = 2409, |
| ARM_t2LDRSH_POST = 2410, |
| ARM_t2LDRSH_PRE = 2411, |
| ARM_t2LDRSHi12 = 2412, |
| ARM_t2LDRSHi8 = 2413, |
| ARM_t2LDRSHpci = 2414, |
| ARM_t2LDRSHpcrel = 2415, |
| ARM_t2LDRSHs = 2416, |
| ARM_t2LDRT = 2417, |
| ARM_t2LDR_POST = 2418, |
| ARM_t2LDR_PRE = 2419, |
| ARM_t2LDRi12 = 2420, |
| ARM_t2LDRi8 = 2421, |
| ARM_t2LDRpci = 2422, |
| ARM_t2LDRpci_pic = 2423, |
| ARM_t2LDRpcrel = 2424, |
| ARM_t2LDRs = 2425, |
| ARM_t2LEApcrel = 2426, |
| ARM_t2LEApcrelJT = 2427, |
| ARM_t2LSLri = 2428, |
| ARM_t2LSLrr = 2429, |
| ARM_t2LSRri = 2430, |
| ARM_t2LSRrr = 2431, |
| ARM_t2MCR = 2432, |
| ARM_t2MCR2 = 2433, |
| ARM_t2MCRR = 2434, |
| ARM_t2MCRR2 = 2435, |
| ARM_t2MLA = 2436, |
| ARM_t2MLS = 2437, |
| ARM_t2MOVCCasr = 2438, |
| ARM_t2MOVCCi = 2439, |
| ARM_t2MOVCCi16 = 2440, |
| ARM_t2MOVCCi32imm = 2441, |
| ARM_t2MOVCClsl = 2442, |
| ARM_t2MOVCClsr = 2443, |
| ARM_t2MOVCCr = 2444, |
| ARM_t2MOVCCror = 2445, |
| ARM_t2MOVSsi = 2446, |
| ARM_t2MOVSsr = 2447, |
| ARM_t2MOVTi16 = 2448, |
| ARM_t2MOVTi16_ga_pcrel = 2449, |
| ARM_t2MOV_ga_pcrel = 2450, |
| ARM_t2MOVi = 2451, |
| ARM_t2MOVi16 = 2452, |
| ARM_t2MOVi16_ga_pcrel = 2453, |
| ARM_t2MOVi32imm = 2454, |
| ARM_t2MOVr = 2455, |
| ARM_t2MOVsi = 2456, |
| ARM_t2MOVsr = 2457, |
| ARM_t2MOVsra_flag = 2458, |
| ARM_t2MOVsrl_flag = 2459, |
| ARM_t2MRC = 2460, |
| ARM_t2MRC2 = 2461, |
| ARM_t2MRRC = 2462, |
| ARM_t2MRRC2 = 2463, |
| ARM_t2MRS_AR = 2464, |
| ARM_t2MRS_M = 2465, |
| ARM_t2MRSbanked = 2466, |
| ARM_t2MRSsys_AR = 2467, |
| ARM_t2MSR_AR = 2468, |
| ARM_t2MSR_M = 2469, |
| ARM_t2MSRbanked = 2470, |
| ARM_t2MUL = 2471, |
| ARM_t2MVNCCi = 2472, |
| ARM_t2MVNi = 2473, |
| ARM_t2MVNr = 2474, |
| ARM_t2MVNs = 2475, |
| ARM_t2ORNri = 2476, |
| ARM_t2ORNrr = 2477, |
| ARM_t2ORNrs = 2478, |
| ARM_t2ORRri = 2479, |
| ARM_t2ORRrr = 2480, |
| ARM_t2ORRrs = 2481, |
| ARM_t2PKHBT = 2482, |
| ARM_t2PKHTB = 2483, |
| ARM_t2PLDWi12 = 2484, |
| ARM_t2PLDWi8 = 2485, |
| ARM_t2PLDWs = 2486, |
| ARM_t2PLDi12 = 2487, |
| ARM_t2PLDi8 = 2488, |
| ARM_t2PLDpci = 2489, |
| ARM_t2PLDs = 2490, |
| ARM_t2PLIi12 = 2491, |
| ARM_t2PLIi8 = 2492, |
| ARM_t2PLIpci = 2493, |
| ARM_t2PLIs = 2494, |
| ARM_t2QADD = 2495, |
| ARM_t2QADD16 = 2496, |
| ARM_t2QADD8 = 2497, |
| ARM_t2QASX = 2498, |
| ARM_t2QDADD = 2499, |
| ARM_t2QDSUB = 2500, |
| ARM_t2QSAX = 2501, |
| ARM_t2QSUB = 2502, |
| ARM_t2QSUB16 = 2503, |
| ARM_t2QSUB8 = 2504, |
| ARM_t2RBIT = 2505, |
| ARM_t2REV = 2506, |
| ARM_t2REV16 = 2507, |
| ARM_t2REVSH = 2508, |
| ARM_t2RFEDB = 2509, |
| ARM_t2RFEDBW = 2510, |
| ARM_t2RFEIA = 2511, |
| ARM_t2RFEIAW = 2512, |
| ARM_t2RORri = 2513, |
| ARM_t2RORrr = 2514, |
| ARM_t2RRX = 2515, |
| ARM_t2RSBSri = 2516, |
| ARM_t2RSBSrs = 2517, |
| ARM_t2RSBri = 2518, |
| ARM_t2RSBrr = 2519, |
| ARM_t2RSBrs = 2520, |
| ARM_t2SADD16 = 2521, |
| ARM_t2SADD8 = 2522, |
| ARM_t2SASX = 2523, |
| ARM_t2SBCri = 2524, |
| ARM_t2SBCrr = 2525, |
| ARM_t2SBCrs = 2526, |
| ARM_t2SBFX = 2527, |
| ARM_t2SDIV = 2528, |
| ARM_t2SEL = 2529, |
| ARM_t2SHADD16 = 2530, |
| ARM_t2SHADD8 = 2531, |
| ARM_t2SHASX = 2532, |
| ARM_t2SHSAX = 2533, |
| ARM_t2SHSUB16 = 2534, |
| ARM_t2SHSUB8 = 2535, |
| ARM_t2SMC = 2536, |
| ARM_t2SMLABB = 2537, |
| ARM_t2SMLABT = 2538, |
| ARM_t2SMLAD = 2539, |
| ARM_t2SMLADX = 2540, |
| ARM_t2SMLAL = 2541, |
| ARM_t2SMLALBB = 2542, |
| ARM_t2SMLALBT = 2543, |
| ARM_t2SMLALD = 2544, |
| ARM_t2SMLALDX = 2545, |
| ARM_t2SMLALTB = 2546, |
| ARM_t2SMLALTT = 2547, |
| ARM_t2SMLATB = 2548, |
| ARM_t2SMLATT = 2549, |
| ARM_t2SMLAWB = 2550, |
| ARM_t2SMLAWT = 2551, |
| ARM_t2SMLSD = 2552, |
| ARM_t2SMLSDX = 2553, |
| ARM_t2SMLSLD = 2554, |
| ARM_t2SMLSLDX = 2555, |
| ARM_t2SMMLA = 2556, |
| ARM_t2SMMLAR = 2557, |
| ARM_t2SMMLS = 2558, |
| ARM_t2SMMLSR = 2559, |
| ARM_t2SMMUL = 2560, |
| ARM_t2SMMULR = 2561, |
| ARM_t2SMUAD = 2562, |
| ARM_t2SMUADX = 2563, |
| ARM_t2SMULBB = 2564, |
| ARM_t2SMULBT = 2565, |
| ARM_t2SMULL = 2566, |
| ARM_t2SMULTB = 2567, |
| ARM_t2SMULTT = 2568, |
| ARM_t2SMULWB = 2569, |
| ARM_t2SMULWT = 2570, |
| ARM_t2SMUSD = 2571, |
| ARM_t2SMUSDX = 2572, |
| ARM_t2SRSDB = 2573, |
| ARM_t2SRSDB_UPD = 2574, |
| ARM_t2SRSIA = 2575, |
| ARM_t2SRSIA_UPD = 2576, |
| ARM_t2SSAT = 2577, |
| ARM_t2SSAT16 = 2578, |
| ARM_t2SSAX = 2579, |
| ARM_t2SSUB16 = 2580, |
| ARM_t2SSUB8 = 2581, |
| ARM_t2STC2L_OFFSET = 2582, |
| ARM_t2STC2L_OPTION = 2583, |
| ARM_t2STC2L_POST = 2584, |
| ARM_t2STC2L_PRE = 2585, |
| ARM_t2STC2_OFFSET = 2586, |
| ARM_t2STC2_OPTION = 2587, |
| ARM_t2STC2_POST = 2588, |
| ARM_t2STC2_PRE = 2589, |
| ARM_t2STCL_OFFSET = 2590, |
| ARM_t2STCL_OPTION = 2591, |
| ARM_t2STCL_POST = 2592, |
| ARM_t2STCL_PRE = 2593, |
| ARM_t2STC_OFFSET = 2594, |
| ARM_t2STC_OPTION = 2595, |
| ARM_t2STC_POST = 2596, |
| ARM_t2STC_PRE = 2597, |
| ARM_t2STL = 2598, |
| ARM_t2STLB = 2599, |
| ARM_t2STLEX = 2600, |
| ARM_t2STLEXB = 2601, |
| ARM_t2STLEXD = 2602, |
| ARM_t2STLEXH = 2603, |
| ARM_t2STLH = 2604, |
| ARM_t2STMDB = 2605, |
| ARM_t2STMDB_UPD = 2606, |
| ARM_t2STMIA = 2607, |
| ARM_t2STMIA_UPD = 2608, |
| ARM_t2STRBT = 2609, |
| ARM_t2STRB_POST = 2610, |
| ARM_t2STRB_PRE = 2611, |
| ARM_t2STRB_preidx = 2612, |
| ARM_t2STRBi12 = 2613, |
| ARM_t2STRBi8 = 2614, |
| ARM_t2STRBs = 2615, |
| ARM_t2STRD_POST = 2616, |
| ARM_t2STRD_PRE = 2617, |
| ARM_t2STRDi8 = 2618, |
| ARM_t2STREX = 2619, |
| ARM_t2STREXB = 2620, |
| ARM_t2STREXD = 2621, |
| ARM_t2STREXH = 2622, |
| ARM_t2STRHT = 2623, |
| ARM_t2STRH_POST = 2624, |
| ARM_t2STRH_PRE = 2625, |
| ARM_t2STRH_preidx = 2626, |
| ARM_t2STRHi12 = 2627, |
| ARM_t2STRHi8 = 2628, |
| ARM_t2STRHs = 2629, |
| ARM_t2STRT = 2630, |
| ARM_t2STR_POST = 2631, |
| ARM_t2STR_PRE = 2632, |
| ARM_t2STR_preidx = 2633, |
| ARM_t2STRi12 = 2634, |
| ARM_t2STRi8 = 2635, |
| ARM_t2STRs = 2636, |
| ARM_t2SUBS_PC_LR = 2637, |
| ARM_t2SUBSri = 2638, |
| ARM_t2SUBSrr = 2639, |
| ARM_t2SUBSrs = 2640, |
| ARM_t2SUBri = 2641, |
| ARM_t2SUBri12 = 2642, |
| ARM_t2SUBrr = 2643, |
| ARM_t2SUBrs = 2644, |
| ARM_t2SXTAB = 2645, |
| ARM_t2SXTAB16 = 2646, |
| ARM_t2SXTAH = 2647, |
| ARM_t2SXTB = 2648, |
| ARM_t2SXTB16 = 2649, |
| ARM_t2SXTH = 2650, |
| ARM_t2TBB = 2651, |
| ARM_t2TBB_JT = 2652, |
| ARM_t2TBH = 2653, |
| ARM_t2TBH_JT = 2654, |
| ARM_t2TEQri = 2655, |
| ARM_t2TEQrr = 2656, |
| ARM_t2TEQrs = 2657, |
| ARM_t2TSTri = 2658, |
| ARM_t2TSTrr = 2659, |
| ARM_t2TSTrs = 2660, |
| ARM_t2UADD16 = 2661, |
| ARM_t2UADD8 = 2662, |
| ARM_t2UASX = 2663, |
| ARM_t2UBFX = 2664, |
| ARM_t2UDF = 2665, |
| ARM_t2UDIV = 2666, |
| ARM_t2UHADD16 = 2667, |
| ARM_t2UHADD8 = 2668, |
| ARM_t2UHASX = 2669, |
| ARM_t2UHSAX = 2670, |
| ARM_t2UHSUB16 = 2671, |
| ARM_t2UHSUB8 = 2672, |
| ARM_t2UMAAL = 2673, |
| ARM_t2UMLAL = 2674, |
| ARM_t2UMULL = 2675, |
| ARM_t2UQADD16 = 2676, |
| ARM_t2UQADD8 = 2677, |
| ARM_t2UQASX = 2678, |
| ARM_t2UQSAX = 2679, |
| ARM_t2UQSUB16 = 2680, |
| ARM_t2UQSUB8 = 2681, |
| ARM_t2USAD8 = 2682, |
| ARM_t2USADA8 = 2683, |
| ARM_t2USAT = 2684, |
| ARM_t2USAT16 = 2685, |
| ARM_t2USAX = 2686, |
| ARM_t2USUB16 = 2687, |
| ARM_t2USUB8 = 2688, |
| ARM_t2UXTAB = 2689, |
| ARM_t2UXTAB16 = 2690, |
| ARM_t2UXTAH = 2691, |
| ARM_t2UXTB = 2692, |
| ARM_t2UXTB16 = 2693, |
| ARM_t2UXTH = 2694, |
| ARM_tADC = 2695, |
| ARM_tADDframe = 2696, |
| ARM_tADDhirr = 2697, |
| ARM_tADDi3 = 2698, |
| ARM_tADDi8 = 2699, |
| ARM_tADDrSP = 2700, |
| ARM_tADDrSPi = 2701, |
| ARM_tADDrr = 2702, |
| ARM_tADDspi = 2703, |
| ARM_tADDspr = 2704, |
| ARM_tADJCALLSTACKDOWN = 2705, |
| ARM_tADJCALLSTACKUP = 2706, |
| ARM_tADR = 2707, |
| ARM_tAND = 2708, |
| ARM_tASRri = 2709, |
| ARM_tASRrr = 2710, |
| ARM_tB = 2711, |
| ARM_tBIC = 2712, |
| ARM_tBKPT = 2713, |
| ARM_tBL = 2714, |
| ARM_tBLXi = 2715, |
| ARM_tBLXr = 2716, |
| ARM_tBRIND = 2717, |
| ARM_tBR_JTr = 2718, |
| ARM_tBX = 2719, |
| ARM_tBX_CALL = 2720, |
| ARM_tBX_RET = 2721, |
| ARM_tBX_RET_vararg = 2722, |
| ARM_tBcc = 2723, |
| ARM_tBfar = 2724, |
| ARM_tCBNZ = 2725, |
| ARM_tCBZ = 2726, |
| ARM_tCMNz = 2727, |
| ARM_tCMPhir = 2728, |
| ARM_tCMPi8 = 2729, |
| ARM_tCMPr = 2730, |
| ARM_tCPS = 2731, |
| ARM_tEOR = 2732, |
| ARM_tHINT = 2733, |
| ARM_tHLT = 2734, |
| ARM_tInt_eh_sjlj_longjmp = 2735, |
| ARM_tInt_eh_sjlj_setjmp = 2736, |
| ARM_tLDMIA = 2737, |
| ARM_tLDMIA_UPD = 2738, |
| ARM_tLDRBi = 2739, |
| ARM_tLDRBr = 2740, |
| ARM_tLDRHi = 2741, |
| ARM_tLDRHr = 2742, |
| ARM_tLDRLIT_ga_abs = 2743, |
| ARM_tLDRLIT_ga_pcrel = 2744, |
| ARM_tLDRSB = 2745, |
| ARM_tLDRSH = 2746, |
| ARM_tLDRi = 2747, |
| ARM_tLDRpci = 2748, |
| ARM_tLDRpci_pic = 2749, |
| ARM_tLDRr = 2750, |
| ARM_tLDRspi = 2751, |
| ARM_tLEApcrel = 2752, |
| ARM_tLEApcrelJT = 2753, |
| ARM_tLSLri = 2754, |
| ARM_tLSLrr = 2755, |
| ARM_tLSRri = 2756, |
| ARM_tLSRrr = 2757, |
| ARM_tMOVCCr_pseudo = 2758, |
| ARM_tMOVSr = 2759, |
| ARM_tMOVi8 = 2760, |
| ARM_tMOVr = 2761, |
| ARM_tMUL = 2762, |
| ARM_tMVN = 2763, |
| ARM_tORR = 2764, |
| ARM_tPICADD = 2765, |
| ARM_tPOP = 2766, |
| ARM_tPOP_RET = 2767, |
| ARM_tPUSH = 2768, |
| ARM_tREV = 2769, |
| ARM_tREV16 = 2770, |
| ARM_tREVSH = 2771, |
| ARM_tROR = 2772, |
| ARM_tRSB = 2773, |
| ARM_tSBC = 2774, |
| ARM_tSETEND = 2775, |
| ARM_tSTMIA_UPD = 2776, |
| ARM_tSTRBi = 2777, |
| ARM_tSTRBr = 2778, |
| ARM_tSTRHi = 2779, |
| ARM_tSTRHr = 2780, |
| ARM_tSTRi = 2781, |
| ARM_tSTRr = 2782, |
| ARM_tSTRspi = 2783, |
| ARM_tSUBi3 = 2784, |
| ARM_tSUBi8 = 2785, |
| ARM_tSUBrr = 2786, |
| ARM_tSUBspi = 2787, |
| ARM_tSVC = 2788, |
| ARM_tSXTB = 2789, |
| ARM_tSXTH = 2790, |
| ARM_tTAILJMPd = 2791, |
| ARM_tTAILJMPdND = 2792, |
| ARM_tTAILJMPr = 2793, |
| ARM_tTPsoft = 2794, |
| ARM_tTRAP = 2795, |
| ARM_tTST = 2796, |
| ARM_tUDF = 2797, |
| ARM_tUXTB = 2798, |
| ARM_tUXTH = 2799, |
| ARM_INSTRUCTION_LIST_END = 2800 |
| }; |
| |
| #endif // GET_INSTRINFO_ENUM |
| |
| |
| #ifdef GET_INSTRINFO_MC_DESC |
| #undef GET_INSTRINFO_MC_DESC |
| |
| #define nullptr 0 |
| |
| #define ImplicitList1 0 |
| #define ImplicitList2 0 |
| #define ImplicitList3 0 |
| #define ImplicitList4 0 |
| #define ImplicitList5 0 |
| #define ImplicitList6 0 |
| #define ImplicitList7 0 |
| #define ImplicitList8 0 |
| #define ImplicitList9 0 |
| #define ImplicitList10 0 |
| #define ImplicitList11 0 |
| #define ImplicitList12 0 |
| #define ImplicitList13 0 |
| #define ImplicitList14 0 |
| #define ImplicitList15 0 |
| |
| |
| static MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; |
| static MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; |
| static MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; |
| static MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; |
| static MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; |
| static MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; |
| static MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; |
| static MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; |
| static MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, }; |
| static MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; |
| static MCOperandInfo OperandInfo12[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; |
| static MCOperandInfo OperandInfo13[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; |
| static MCOperandInfo OperandInfo14[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; |
| static MCOperandInfo OperandInfo15[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; |
| static MCOperandInfo OperandInfo16[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; |
| static MCOperandInfo OperandInfo17[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; |
| static MCOperandInfo OperandInfo18[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; |
| static MCOperandInfo OperandInfo19[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; |
| static MCOperandInfo OperandInfo20[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; |
| static MCOperandInfo OperandInfo21[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; |
| static MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; |
| static MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; |
| static MCOperandInfo OperandInfo24[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; |
| static MCOperandInfo OperandInfo25[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; |
| static MCOperandInfo OperandInfo26[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; |
| static MCOperandInfo OperandInfo27[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; |
| static MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI_OPERAND_PCREL, 0 }, }; |
| static MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, }; |
| static MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, }; |
| static MCOperandInfo OperandInfo31[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; |
| static MCOperandInfo OperandInfo32[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; |
| static MCOperandInfo OperandInfo33[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; |
| static MCOperandInfo OperandInfo34[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; |
| static MCOperandInfo OperandInfo35[] = { { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; |
| static MCOperandInfo OperandInfo36[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; |
| static MCOperandInfo OperandInfo37[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; |
| static MCOperandInfo OperandInfo38[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, |
