commit 08b1cfa23512e19d56f7a13b229e7f8a8ef7f931
author Catena cyber <35799796+catenacyber@users.noreply.github.com> Fri Jun 01 14:51:46 2018 +0200
committer Nguyen Anh Quynh <aquynh@gmail.com> Fri Jun 01 20:51:46 2018 +0800
tree 3dee01c28cb2ae4c234bd3a49ae8870ac5fcc982
parent c6dbbd06f8283542dfbb1c88951bb8d2325b0605

Do not shift signed values in Mips disassembling (#1148)

* Do not shift signed values in Mips disassembling

* Do not shift signed values in Mips disassembling

Multiply instead

arch/Mips/MipsDisassembler.c

diff --git a/arch/Mips/MipsDisassembler.c b/arch/Mips/MipsDisassembler.c
index dfc07ee..561f522 100644
--- a/arch/Mips/MipsDisassembler.c
+++ b/arch/Mips/MipsDisassembler.c
@@ -1196,7 +1196,7 @@
 		return MCDisassembler_Fail;
 
 	MCOperand_CreateReg0(Inst, Mips_SP);
-	MCOperand_CreateImm0(Inst, Offset << 2);
+	MCOperand_CreateImm0(Inst, Offset * 4);
 
 	return MCDisassembler_Success;
 }
@@ -1533,7 +1533,7 @@
 static DecodeStatus DecodeBranchTarget7MM(MCInst *Inst,
 		unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder)
 {
-	int32_t BranchOffset = SignExtend32(Offset, 7) << 1;
+	int32_t BranchOffset = SignExtend32(Offset, 7) * 2;
 	MCOperand_CreateImm0(Inst, BranchOffset);
 	return MCDisassembler_Success;
 }
@@ -1541,7 +1541,7 @@
 static DecodeStatus DecodeBranchTarget10MM(MCInst *Inst,
 		unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder)
 {
-	int32_t BranchOffset = SignExtend32(Offset, 10) << 1;
+	int32_t BranchOffset = SignExtend32(Offset, 10) * 2;
 	MCOperand_CreateImm0(Inst, BranchOffset);
 	return MCDisassembler_Success;
 }