Merge with binutils-2_27-branch rev b5d3ac20
Change-Id: Iaa5f379bb904c3eb5b6e041c62c24076d2838063
diff --git a/.gitreview b/.gitreview
new file mode 100644
index 0000000..0c66476
--- /dev/null
+++ b/.gitreview
@@ -0,0 +1,4 @@
+[gerrit]
+host=review.linaro.org
+port=29418
+project=toolchain/binutils-gdb
diff --git a/bfd/ChangeLog.linaro b/bfd/ChangeLog.linaro
new file mode 100644
index 0000000..c5d7117
--- /dev/null
+++ b/bfd/ChangeLog.linaro
@@ -0,0 +1,18 @@
+2017-04-27 Adhemerval Zanella <adhemerval.zanella@linaro.org>
+
+ Backport from mainline:
+ 2017-04-21 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR ld/19617
+ PR ld/21086
+ * elflink.c (elf_link_add_object_symbols): Require
+ --no-dynamic-linker with -E/--dynamic-list when creating
+ dynamic sections.
+
+2016-09-15 Christophe Lyon <christophe.lyon@linaro.org>
+
+ Backport from mainline:
+ 2016-08-23 Nick Clifton <nickc@redhat.com>
+
+ * elf32-arm.c (elf32_arm_count_additional_relocs): Return zero if
+ there is no arm data associated with the section.
diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
index 700bec3..3fab609 100644
--- a/bfd/elf32-arm.c
+++ b/bfd/elf32-arm.c
@@ -18207,7 +18207,7 @@
{
struct _arm_elf_section_data *arm_data;
arm_data = get_arm_elf_section_data (sec);
- return arm_data->additional_reloc_count;
+ return arm_data == NULL ? 0 : arm_data->additional_reloc_count;
}
/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
diff --git a/bfd/elflink.c b/bfd/elflink.c
index 3e24940..c6b6992 100644
--- a/bfd/elflink.c
+++ b/bfd/elflink.c
@@ -3750,6 +3750,7 @@
if (!just_syms
&& (bfd_link_pic (info)
|| (!bfd_link_relocatable (info)
+ && info->nointerp
&& (info->export_dynamic || info->dynamic)))
&& is_elf_hash_table (htab)
&& info->output_bfd->xvec == abfd->xvec
diff --git a/gas/ChangeLog.linaro b/gas/ChangeLog.linaro
new file mode 100644
index 0000000..84a9828
--- /dev/null
+++ b/gas/ChangeLog.linaro
@@ -0,0 +1,21 @@
+2017-06-14 Christophe Lyon <christophe.lyon@linaro.org>
+
+ Backport from mainline:
+ 2017-04-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * config/tc-arm.c (move_or_literal_pool): Remove code generating MOVS.
+ Forbid MOV.W and MOVW if destination is SP or PC.
+
+2016-08-29 Adhemerval Zanella <adhemerval.zanella@linaro.com>
+
+ Backport from mainline:
+ 2016-08-05 Nick Clifton <nickc@redhat.com>
+
+ PR gas/20364
+ * config/tc-aarch64.c (s_ltorg): Change the mapping state after
+ aligning the frag.
+ (aarch64_init): Treat rs_align frags in code sections as
+ containing code, not data.
+ * testsuite/gas/aarch64/pr20364.s: New test.
+ * testsuite/gas/aarch64/pr20364.d: New test driver.
+
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index ddc40f2..74933cb 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -1736,13 +1736,13 @@
if (pool == NULL || pool->symbol == NULL || pool->next_free_entry == 0)
continue;
- mapping_state (MAP_DATA);
-
/* Align pool as you have word accesses.
Only make a frag if we have to. */
if (!need_pass_2)
frag_align (align, 0, 0);
+ mapping_state (MAP_DATA);
+
record_alignment (now_seg, align);
sprintf (sym_name, "$$lit_\002%x", pool->id);
@@ -6373,11 +6373,15 @@
switch (fragP->fr_type)
{
- case rs_align:
case rs_align_test:
case rs_fill:
mapping_state_2 (MAP_DATA, max_chars);
break;
+ case rs_align:
+ /* PR 20364: We can get alignment frags in code sections,
+ so do not just assume that we should use the MAP_DATA state. */
+ mapping_state_2 (subseg_text_p (now_seg) ? MAP_INSN : MAP_DATA, max_chars);
+ break;
case rs_align_code:
mapping_state_2 (MAP_INSN, max_chars);
break;
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 4fa0bfc..b5fad80 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -7930,17 +7930,13 @@
{
if (thumb_p)
{
- /* This can be encoded only for a low register. */
- if ((v & ~0xFF) == 0 && (inst.operands[i].reg < 8))
- {
- /* This can be done with a mov(1) instruction. */
- inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
- inst.instruction |= v;
- return TRUE;
- }
+ /* LDR should not use lead in a flag-setting instruction being
+ chosen so we do not check whether movs can be used. */
- if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)
+ if ((ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)
|| ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m))
+ && inst.operands[i].reg != 13
+ && inst.operands[i].reg != 15)
{
/* Check if on thumb2 it can be done with a mov.w, mvn or
movw instruction. */
diff --git a/gas/testsuite/ChangeLog.linaro b/gas/testsuite/ChangeLog.linaro
new file mode 100644
index 0000000..b36ff7b
--- /dev/null
+++ b/gas/testsuite/ChangeLog.linaro
@@ -0,0 +1,11 @@
+2017-06-14 Christophe Lyon <christophe.lyon@linaro.org>
+
+ Backport from mainline:
+ 2017-04-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.s: Explain
+ expectation of LDR not generating a MOVS for low registers and small
+ constants. Add tests of MOVW generation.
+ * testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.d: Update
+ expected disassembly.
+
diff --git a/gas/testsuite/gas/aarch64/pr20364.d b/gas/testsuite/gas/aarch64/pr20364.d
new file mode 100644
index 0000000..babcff1
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/pr20364.d
@@ -0,0 +1,13 @@
+# Check that ".align <size>, <fill>" does not set the mapping state to DATA, causing unnecessary frag generation.
+#name: PR20364
+#objdump: -d
+
+.*: file format .*
+
+Disassembly of section \.vectors:
+
+0+000 <.*>:
+ 0: d2800000 mov x0, #0x0 // #0
+ 4: 94000000 bl 0 <plat_report_exception>
+ 8: 17fffffe b 0 <bl1_exceptions>
+
diff --git a/gas/testsuite/gas/aarch64/pr20364.s b/gas/testsuite/gas/aarch64/pr20364.s
new file mode 100644
index 0000000..594ad7c
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/pr20364.s
@@ -0,0 +1,28 @@
+ .macro vector_base label
+ .section .vectors, "ax"
+ .align 11, 0
+ \label:
+ .endm
+
+ .macro vector_entry label
+ .section .vectors, "ax"
+ .align 7, 0
+ \label:
+ .endm
+
+ .macro check_vector_size since
+ .if (. - \since) > (32 * 4)
+ .error "Vector exceeds 32 instructions"
+ .endif
+ .endm
+
+ .globl bl1_exceptions
+
+vector_base bl1_exceptions
+
+vector_entry SynchronousExceptionSP0
+ mov x0, #0x0
+ bl plat_report_exception
+ b SynchronousExceptionSP0
+ check_vector_size SynchronousExceptionSP0
+
diff --git a/gas/testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.d b/gas/testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.d
index 55b5f17..7afc135 100644
--- a/gas/testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.d
+++ b/gas/testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.d
@@ -6,19 +6,23 @@
.*: +file format .*arm.*
Disassembly of section \.text:
-0[0-9a-f]+ <[^>]+> 2000[[:space:]]+movs[[:space:]]+r0, #0.*
-0[0-9a-f]+ <[^>]+> 2108[[:space:]]+movs[[:space:]]+r1, #8.*
-0[0-9a-f]+ <[^>]+> 2251[[:space:]]+movs[[:space:]]+r2, #81.*
-0[0-9a-f]+ <[^>]+> 231f[[:space:]]+movs[[:space:]]+r3, #31.*
-0[0-9a-f]+ <[^>]+> 242f[[:space:]]+movs[[:space:]]+r4, #47.*
-0[0-9a-f]+ <[^>]+> 253f[[:space:]]+movs[[:space:]]+r5, #63.*
-0[0-9a-f]+ <[^>]+> 2680[[:space:]]+movs[[:space:]]+r6, #128.*
-0[0-9a-f]+ <[^>]+> 27ff[[:space:]]+movs[[:space:]]+r7, #255.*
+0[0-9a-f]+ <[^>]+> f04f 0000[[:space:]]+mov\.w[[:space:]]+r0, #0.*
+0[0-9a-f]+ <[^>]+> f04f 0108[[:space:]]+mov\.w[[:space:]]+r1, #8.*
+0[0-9a-f]+ <[^>]+> f04f 0251[[:space:]]+mov\.w[[:space:]]+r2, #81.*
+0[0-9a-f]+ <[^>]+> f04f 031f[[:space:]]+mov\.w[[:space:]]+r3, #31.*
+0[0-9a-f]+ <[^>]+> f04f 042f[[:space:]]+mov\.w[[:space:]]+r4, #47.*
+0[0-9a-f]+ <[^>]+> f04f 053f[[:space:]]+mov\.w[[:space:]]+r5, #63.*
+0[0-9a-f]+ <[^>]+> f04f 0680[[:space:]]+mov\.w[[:space:]]+r6, #128.*
+0[0-9a-f]+ <[^>]+> f04f 07ff[[:space:]]+mov\.w[[:space:]]+r7, #255.*
0[0-9a-f]+ <[^>]+> f04f 0800[[:space:]]+mov\.w[[:space:]]+r8, #0.*
0[0-9a-f]+ <[^>]+> f04f 0908[[:space:]]+mov\.w[[:space:]]+r9, #8.*
0[0-9a-f]+ <[^>]+> f04f 0a51[[:space:]]+mov\.w[[:space:]]+sl, #81.*
0[0-9a-f]+ <[^>]+> f04f 0b1f[[:space:]]+mov\.w[[:space:]]+fp, #31.*
0[0-9a-f]+ <[^>]+> f04f 0c2f[[:space:]]+mov\.w[[:space:]]+ip, #47.*
-0[0-9a-f]+ <[^>]+> f04f 0d3f[[:space:]]+mov\.w[[:space:]]+sp, #63.*
0[0-9a-f]+ <[^>]+> f04f 0e80[[:space:]]+mov\.w[[:space:]]+lr, #128.*
-0[0-9a-f]+ <[^>]+> f04f 0fff[[:space:]]+mov\.w[[:space:]]+pc, #255.*
+0[0-9a-f]+ <[^>]+> f64f 78ff[[:space:]]+movw[[:space:]]+r8, #65535.*
+0[0-9a-f]+ <[^>]+> f24f 09f0[[:space:]]+movw[[:space:]]+r9, #61680.*
+0[0-9a-f]+ <[^>]+> f8df d004[[:space:]]+ldr\.w[[:space:]]+sp, \[pc, #4\].*
+0[0-9a-f]+ <[^>]+> f8df f004[[:space:]]+ldr\.w[[:space:]]+pc, \[pc, #4\].*
+0[0-9a-f]+ <[^>]+> 0000003f[[:space:]]+.word[[:space:]]+0x0000003f.*
+0[0-9a-f]+ <[^>]+> 000000ff[[:space:]]+.word[[:space:]]+0x000000ff.*
diff --git a/gas/testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.s b/gas/testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.s
index d225410..b473857 100644
--- a/gas/testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.s
+++ b/gas/testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.s
@@ -2,8 +2,8 @@
.syntax unified
.thumb_func
thumb2_ldr:
- # These can be encoded into movs since constant is small
- # And register can be encoded in 3 bits
+ # These must be encoded into mov.w despite constant and register being
+ # small enough as ldr should not generate a flag-setting instruction.
ldr r0,=0x00
ldr r1,=0x08
ldr r2,=0x51
@@ -12,13 +12,19 @@
ldr r5,=0x3F
ldr r6,=0x80
ldr r7,=0xFF
- # These shall be encoded into mov.w
- # Since register cannot be encoded in 3 bits
+ # These shall be encoded into mov.w since register cannot be encoded in
+ # 3 bits
ldr r8,=0x00
ldr r9,=0x08
ldr r10,=0x51
ldr r11,=0x1F
ldr r12,=0x2F
- ldr r13,=0x3F
ldr r14,=0x80
+ # These shall be encoded into movw since immediate cannot be encoded
+ # with mov.w
+ ldr r8,=0xFFFF
+ ldr r9,=0xF0F0
+ # These should be encoded as ldr since mov immediate is unpredictable
+ # for sp and pc
+ ldr r13,=0x3F
ldr r15,=0xFF
diff --git a/ld/ChangeLog.linaro b/ld/ChangeLog.linaro
new file mode 100644
index 0000000..65f006d
--- /dev/null
+++ b/ld/ChangeLog.linaro
@@ -0,0 +1,11 @@
+2017-04-27 Adhemerval Zanella <adhemerval.zanella@linaro.org>
+
+ Backport from mainline:
+ 2017-04-21 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR ld/19617
+ PR ld/21086
+ * testsuite/ld-elf/pr19617a.d: Pass --no-dynamic-linker to ld.
+ * testsuite/ld-elf/pr19617b.d: Likewise.
+ * testsuite/ld-elf/pr19617c.d: Likewise.
+ *testsuite/ld-i386/pr19636-4d.d: Likewise.
diff --git a/ld/testsuite/ld-elf/pr19617a.d b/ld/testsuite/ld-elf/pr19617a.d
index 784aacb..132021f 100644
--- a/ld/testsuite/ld-elf/pr19617a.d
+++ b/ld/testsuite/ld-elf/pr19617a.d
@@ -1,5 +1,5 @@
#source: pr19617.s
-#ld: -E
+#ld: -E --no-dynamic-linker
#readelf : --dyn-syms --wide
#target: *-*-linux* *-*-gnu* *-*-solaris*
diff --git a/ld/testsuite/ld-elf/pr19617b.d b/ld/testsuite/ld-elf/pr19617b.d
index e1dcb71..4d1886f 100644
--- a/ld/testsuite/ld-elf/pr19617b.d
+++ b/ld/testsuite/ld-elf/pr19617b.d
@@ -1,5 +1,5 @@
#source: pr19617.s
-#ld: --dynamic-list-data
+#ld: --dynamic-list-data --no-dynamic-linker
#readelf : --dyn-syms --wide
#target: *-*-linux* *-*-gnu* *-*-solaris*
diff --git a/ld/testsuite/ld-elf/pr19617c.d b/ld/testsuite/ld-elf/pr19617c.d
index 00e2e7e..9ac8fc1 100644
--- a/ld/testsuite/ld-elf/pr19617c.d
+++ b/ld/testsuite/ld-elf/pr19617c.d
@@ -1,5 +1,5 @@
#source: pr19617.s
-#ld: --dynamic-list-data
+#ld: --dynamic-list-data --no-dynamic-linker
#readelf : --dyn-syms --wide
#target: *-*-linux* *-*-gnu* *-*-solaris*
diff --git a/ld/testsuite/ld-elf/pr21086.c b/ld/testsuite/ld-elf/pr21086.c
new file mode 100644
index 0000000..8fb892c
--- /dev/null
+++ b/ld/testsuite/ld-elf/pr21086.c
@@ -0,0 +1,8 @@
+#include <stdio.h>
+
+int
+main ()
+{
+ printf ("PASS\n");
+ return 0;
+}
diff --git a/ld/testsuite/ld-elf/pr21086.list b/ld/testsuite/ld-elf/pr21086.list
new file mode 100644
index 0000000..a4e712f
--- /dev/null
+++ b/ld/testsuite/ld-elf/pr21086.list
@@ -0,0 +1,3 @@
+{
+ main;
+};
diff --git a/ld/testsuite/ld-i386/pr19636-4d.d b/ld/testsuite/ld-i386/pr19636-4d.d
index a9487f0..e3db609 100644
--- a/ld/testsuite/ld-i386/pr19636-4d.d
+++ b/ld/testsuite/ld-i386/pr19636-4d.d
@@ -1,6 +1,6 @@
#source: pr19636-4.s
#as: --32
-#ld: -E --defsym foobar=0x100 -m elf_i386
+#ld: -E --defsym foobar=0x100 -m elf_i386 --no-dynamic-linker
#readelf : --dyn-syms --wide
Symbol table '\.dynsym' contains [0-9]+ entries:
