Check in ARCompact simulator. A valid configuration is arc-elf.
This is not quite finished and has most likely a few files that are
obsolete & not used, but it's good enough to run gcc regression tests.
diff --git a/Makefile.in b/Makefile.in
index 981ce54..027a03b 100644
--- a/Makefile.in
+++ b/Makefile.in
@@ -354,6 +354,7 @@
AS_FOR_TARGET=@AS_FOR_TARGET@
CC_FOR_TARGET=$(STAGE_CC_WRAPPER) @CC_FOR_TARGET@ $(FLAGS_FOR_TARGET)
+
# If GCC_FOR_TARGET is not overriden on the command line, then this
# variable is passed down to the gcc Makefile, where it is used to
# build libgcc2.a. We define it here so that it can itself be
diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 1b54ff7..c17aa3c 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,9 @@
+2009-03-09 J"orn Rennecke <joern.rennecke@arc.com>
+
+ (from codito)
+ * elf32-arc.c (ELF_MACHINE_ALT1): Define.
+ * cpu-arc.c: Update ARC mach values.
+
2008-02-26 Alan Modra <amodra@bigpond.net.au>
* elf32-ppc.c (ppc_elf_check_relocs): Set pointer_equality_needed
diff --git a/bfd/archures.c b/bfd/archures.c
index 9a5c7c4..16a4d33 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -300,10 +300,10 @@
.#define bfd_mach_v850e 'E'
.#define bfd_mach_v850e1 '1'
. bfd_arch_arc, {* ARC Cores *}
-.#define bfd_mach_arc_5 5
-.#define bfd_mach_arc_6 6
-.#define bfd_mach_arc_7 7
-.#define bfd_mach_arc_8 8
+.#define bfd_mach_arc_a4 0
+.#define bfd_mach_arc_a5 1
+.#define bfd_mach_arc_arc600 2
+.#define bfd_mach_arc_arc700 3
. bfd_arch_m32c, {* Renesas M16C/M32C. *}
.#define bfd_mach_m16c 0x75
.#define bfd_mach_m32c 0x78
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index c1b5341..12f6a40 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1977,10 +1977,10 @@
#define bfd_mach_v850e 'E'
#define bfd_mach_v850e1 '1'
bfd_arch_arc, /* ARC Cores */
-#define bfd_mach_arc_5 5
-#define bfd_mach_arc_6 6
-#define bfd_mach_arc_7 7
-#define bfd_mach_arc_8 8
+#define bfd_mach_arc_a4 0
+#define bfd_mach_arc_a5 1
+#define bfd_mach_arc_arc600 2
+#define bfd_mach_arc_arc700 3
bfd_arch_m32c, /* Renesas M16C/M32C. */
#define bfd_mach_m16c 0x75
#define bfd_mach_m32c 0x78
@@ -3223,6 +3223,112 @@
through 0. */
BFD_RELOC_ARC_B26,
+/* ARCompact 21 bit pc-relative branch. The lowest bit must be zero and is
+not stored in the instruction. The remaining 20 bits are installed in
+2 groups of 10 bits each. The high 10 bits are installed in bits 26
+through 17 and the remaining 10 bits in bits 15 through 6. */
+ BFD_RELOC_ARC_S21H_PCREL,
+
+/* ARCompact 21 bit pc-relative branch. The lowest two bits must be zero and
+are not stored in the instruction. The remaining 19 bits are installed in
+2 groups of 9 and 10 bits each. The high 9 bits are installed in bits 26
+through 18 and the remaining 10 bits in bits 15 through 6. */
+ BFD_RELOC_ARC_S21W_PCREL,
+
+/* ARCompact 25 bit pc-relative branch. The lowest bit must be zero and is
+not stored in the instruction. The remaining 24 bits are installed in
+3 groups of 10 bits, 10 bits and 4 bits each. The high 10 bits are
+installed in bits 26 through 17, next 10 bits in bits 15 through 6 and the
+remaining 4 bits in bits 3 through 0. */
+ BFD_RELOC_ARC_S25H_PCREL,
+
+/* ARCompact 25 bit pc-relative branch. The lowest two bits must be zero and
+are not stored in the instruction. The remaining 23 bits are installed in
+3 groups of 10 bits, 9 bits and 4 bits each. The high 9 bits are installed
+in bits 26 through 18, next 10 bits in bits 15 through 6 and the
+remaining 4 bits in bits 3 through 0. */
+ BFD_RELOC_ARC_S25W_PCREL,
+
+/* ARCompact 13 bit pc-relative branch. The lowest 2 bits must be zero and
+are not stored in the the instruction. The upper 11 bits are installed
+in bits 10 through 0. */
+ BFD_RELOC_ARC_S13_PCREL,
+
+/* ARCompact Middle-endian 32 bit word relocation */
+ BFD_RELOC_ARC_32_ME,
+
+/* ARCompact PC Relative 32 bit relocation. */
+ BFD_RELOC_ARC_PC32 ,
+
+/* ARC 700 GOT specific relocation. This computes the distance from the current
+pcl to the symbol's global offset table entry. */
+ BFD_RELOC_ARC_GOTPC32,
+
+/* ARC 700 PLT specific relocation. This computes the distance from the base
+of the PLT to the symbols PLT entry. */
+ BFD_RELOC_ARC_PLT32 ,
+
+/* ARC 700 Copy relocation. This refers to a location in the writable segment
+and during execution the dynamic linker copies data associated with the shared
+objects symbol to the location specified by the offset. Created for
+dynamic linking by the linker . */
+ BFD_RELOC_ARC_COPY,
+
+/* ARC 700 Global Data relocaton.This is to set a GOT entry to the address
+of the specified symbol . This allows one to determine the correspondence
+between symbols and GOT entries. */
+ BFD_RELOC_ARC_GLOB_DAT,
+
+/* This gives the location of a PLT entrys GOT entry. The dynamic linker
+modifies the GOT entry so that the PLT will transfer control to the designated
+symbols address. Created by the linker. */
+ BFD_RELOC_ARC_JMP_SLOT,
+
+/* This gives the location of a value representing a relative address.
+The dynamic linker adds the load address of the shared library to
+the relative address to compute the final address. */
+ BFD_RELOC_ARC_RELATIVE,
+
+/* This gives the difference between a symbols value and the address of the
+Global Offset Table This causes the linker to build the GOT. */
+ BFD_RELOC_ARC_GOTOFF,
+
+/* This gives the difference between the address of the GOT base and the
+current PC. The symbol referenced is _GLOBAL_OFFSET_TABLE . */
+ BFD_RELOC_ARC_GOTPC,
+
+/* ARC 700 GOT specific relocation. This computes the distance from the base
+of the GOT to the symbol's global offset table entry. */
+ BFD_RELOC_ARC_GOT32,
+
+/* small data reloc 1 */
+ BFD_RELOC_ARC_SDA,
+
+/* small data reloc 2 */
+ BFD_RELOC_ARC_SDA32,
+
+/* small data reloc 3 */
+ BFD_RELOC_ARC_SDA_LDST,
+
+/* small data reloc 4 */
+ BFD_RELOC_ARC_SDA_LDST1,
+
+/* small data reloc 5 */
+ BFD_RELOC_ARC_SDA_LDST2,
+
+/* small data reloc 6 */
+ BFD_RELOC_ARC_SDA16_LD,
+
+/* small data reloc 7 */
+ BFD_RELOC_ARC_SDA16_LD1,
+
+/* small data reloc 8 */
+ BFD_RELOC_ARC_SDA16_LD2,
+
+/* small data reloc 9 */
+ BFD_RELOC_ARC_SDA32_ME,
+
+
/* ADI Blackfin 16 bit immediate absolute reloc. */
BFD_RELOC_BFIN_16_IMM,
diff --git a/bfd/config.bfd b/bfd/config.bfd
index 03ef1c3..e8d263e 100644
--- a/bfd/config.bfd
+++ b/bfd/config.bfd
@@ -201,7 +201,7 @@
targ_defvec=bfd_elf32_am33lin_vec
;;
- arc-*-elf*)
+ arc-*-elf* | arc-*-linux-uclibc*)
targ_defvec=bfd_elf32_littlearc_vec
targ_selvecs=bfd_elf32_bigarc_vec
;;
diff --git a/bfd/configure b/bfd/configure
index 882b320..892d328 100755
--- a/bfd/configure
+++ b/bfd/configure
@@ -2995,7 +2995,7 @@
# Define the identity of the package.
PACKAGE=bfd
- VERSION=2.18.50
+ VERSION=2.18-arc-20070530
cat >>confdefs.h <<_ACEOF
diff --git a/bfd/configure.in b/bfd/configure.in
index 99ea584..295cf36 100644
--- a/bfd/configure.in
+++ b/bfd/configure.in
@@ -8,7 +8,7 @@
AC_CANONICAL_TARGET
AC_ISC_POSIX
-AM_INIT_AUTOMAKE(bfd, 2.18.50)
+AM_INIT_AUTOMAKE(bfd, 2.18-arc-20070530)
dnl These must be called before AM_PROG_LIBTOOL, because it may want
dnl to call AC_CHECK_PROG.
diff --git a/bfd/cpu-arc.c b/bfd/cpu-arc.c
index ca41998..69ed133 100644
--- a/bfd/cpu-arc.c
+++ b/bfd/cpu-arc.c
@@ -42,15 +42,16 @@
static const bfd_arch_info_type arch_info_struct[] =
{
- ARC ( bfd_mach_arc_5, "arc5", FALSE, &arch_info_struct[1] ),
- ARC ( bfd_mach_arc_5, "base", FALSE, &arch_info_struct[2] ),
- ARC ( bfd_mach_arc_6, "arc6", FALSE, &arch_info_struct[3] ),
- ARC ( bfd_mach_arc_7, "arc7", FALSE, &arch_info_struct[4] ),
- ARC ( bfd_mach_arc_8, "arc8", FALSE, NULL ),
+ ARC ( bfd_mach_arc_a4, "A4", FALSE, &arch_info_struct[1] ),
+ ARC ( bfd_mach_arc_a5, "A5", FALSE, &arch_info_struct[2] ),
+ ARC ( bfd_mach_arc_arc600, "ARC600", FALSE, &arch_info_struct[3] ),
+ ARC ( bfd_mach_arc_arc600, "A6", FALSE, &arch_info_struct[4] ),
+ ARC ( bfd_mach_arc_arc700, "ARC700", FALSE, &arch_info_struct[5]),
+ ARC ( bfd_mach_arc_arc700, "A7", FALSE, NULL),
};
const bfd_arch_info_type bfd_arc_arch =
- ARC ( bfd_mach_arc_6, "arc", TRUE, &arch_info_struct[0] );
+ ARC ( bfd_mach_arc_a4, "A4", TRUE, &arch_info_struct[0] );
/* Utility routines. */
diff --git a/bfd/elf32-arc.c b/bfd/elf32-arc.c
index 3ef83f9..548d726 100644
--- a/bfd/elf32-arc.c
+++ b/bfd/elf32-arc.c
@@ -3,6 +3,13 @@
Free Software Foundation, Inc.
Contributed by Doug Evans (dje@cygnus.com).
+ Sources derived from work done by Sankhya Technologies (www.sankhya.com)
+
+ Cleaned up , Comments and Position Independent Code support added by
+ Saurabh Verma (saurabh.verma@codito.com)
+ Ramana Radhakrishnan(ramana.radhakrishnan@codito.com)
+
+
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
@@ -25,124 +32,530 @@
#include "libbfd.h"
#include "elf-bfd.h"
#include "elf/arc.h"
-#include "libiberty.h"
-/* Try to minimize the amount of space occupied by relocation tables
- on the ROM (not that the ROM won't be swamped by other ELF overhead). */
+ /* ****************************************************************
+ * NOTE: The pic related work starts after the comment marked as
+ * ~~~~~~ "* PIC-related routines for the arc backend "
+ * ****************************************************************/
+#define BFD_DEBUG_PIC(x)
+
+/* #define BFD_DEBUG_PIC(x) (fprintf(stderr,"DEBUG: %d@%s: ", \
+ __LINE__,__PRETTY_FUNCTION__),x) */
-#define USE_REL 1
+/* We must define USE_RELA to get the proper fixups for PC relative
+ branches to symbols defined in other object files. The addend is
+ used to account for the PC having been incremented before the PC
+ relative address is calculated. mlm */
+#define USE_RELA
+/* Handle PC relative relocation */
static bfd_reloc_status_type
-arc_elf_b22_pcrel (bfd * abfd,
- arelent * reloc_entry,
- asymbol * symbol,
- void * data,
- asection * input_section,
- bfd * output_bfd,
- char ** error_message)
+arc_elf_b22_pcrel (bfd *abfd ATTRIBUTE_UNUSED,
+ arelent *reloc_entry,
+ asymbol *symbol,
+ void *data ATTRIBUTE_UNUSED,
+ asection *input_section,
+ bfd *output_bfd,
+ char **error_message ATTRIBUTE_UNUSED)
{
- /* If linking, back up the final symbol address by the address of the
- reloc. This cannot be accomplished by setting the pcrel_offset
- field to TRUE, as bfd_install_relocation will detect this and refuse
- to install the offset in the first place, but bfd_perform_relocation
- will still insist on removing it. */
- if (output_bfd == NULL)
- reloc_entry->addend -= reloc_entry->address;
+ /* If incremental linking, update the address of the relocation with the
+ section offset */
- /* Fall through to the default elf reloc handler. */
- return bfd_elf_generic_reloc (abfd, reloc_entry, symbol, data,
- input_section, output_bfd, error_message);
+
+ if (output_bfd != (bfd *) NULL)
+ {
+ reloc_entry->address += input_section->output_offset;
+ if ((symbol->flags & BSF_SECTION_SYM) && symbol->section)
+ reloc_entry->addend
+ += ((**(reloc_entry->sym_ptr_ptr)).section)->output_offset;
+ return bfd_reloc_ok;
+ }
+ return bfd_reloc_continue;
}
+#define bfd_put32(a,b,c)
+static bfd_vma bfd_get_32_me (bfd *, const unsigned char *);
+static void bfd_put_32_me (bfd *, bfd_vma, unsigned char *);
+
+
+static bfd_reloc_status_type arcompact_elf_me_reloc
+ (bfd *, arelent *, asymbol *, void *, asection *, bfd *, char **);
+static bfd_reloc_status_type arc_unsupported_reloc
+ (bfd *, arelent *, asymbol *, void *, asection *, bfd *, char **);
+static bfd_boolean arc_elf_merge_private_bfd_data (bfd *ibfd, bfd *obfd);
+static reloc_howto_type * arc_elf_calculate_howto_index
+ (enum elf_arc_reloc_type r_type);
+
+
+#define INIT_SYM_STRING "init"
+#define FINI_SYM_STRING "fini"
+
+/* The default symbols representing the init and fini dyn values */
+char * init_str = INIT_SYM_STRING;
+char * fini_str = FINI_SYM_STRING;
+
+/* The ARC linker needs to keep track of the number of relocs that it
+ decides to copy in check_relocs for each symbol. This is so that
+ it can discard PC relative relocs if it doesn't need them when
+ linking with -Bsymbolic. We store the information in a field
+ extending the regular ELF linker hash table. */
+
+/* This structure keeps track of the number of PC relative relocs we
+ have copied for a given symbol. */
+#define bfd_elf32_bfd_link_hash_table_create \
+ elf_ARC_link_hash_table_create
+
+struct elf_ARC_pcrel_relocs_copied
+{
+ /* Next section. */
+ struct elf_ARC_pcrel_relocs_copied *next;
+ /* A section in dynobj. */
+ asection *section;
+ /* Number of relocs copied in this section. */
+ bfd_size_type count;
+};
+
+/* ARC ELF linker hash entry. */
+
+struct elf_ARC_link_hash_entry
+{
+ struct elf_link_hash_entry root;
+
+ /* Number of PC relative relocs copied for this symbol. */
+ struct elf_ARC_pcrel_relocs_copied *pcrel_relocs_copied;
+};
+
+/* ARC ELF linker hash table. */
+
+struct elf_ARC_link_hash_table
+{
+ struct elf_link_hash_table root;
+};
+
+/* Declare this now that the above structures are defined. */
+
+static bfd_boolean elf_ARC_discard_copies
+ (struct elf_ARC_link_hash_entry *, void *);
+
+/* Traverse an ARC ELF linker hash table. */
+
+#define elf_ARC_link_hash_traverse(table, func, info) \
+ (elf_link_hash_traverse \
+ (&(table)->root, \
+ (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
+ (info)))
+
+/* Get the ARC ELF linker hash table from a link_info structure. */
+
+#define elf_ARC_hash_table(p) \
+ ((struct elf_ARC_link_hash_table *) ((p)->hash))
+
+/* Create an entry in an ARC ELF linker hash table. */
+
+static struct bfd_hash_entry *
+elf_ARC_link_hash_newfunc (struct bfd_hash_entry *entry,
+ struct bfd_hash_table *table,
+ const char *string)
+{
+ struct elf_ARC_link_hash_entry *ret =
+ (struct elf_ARC_link_hash_entry *) entry;
+
+ /* Allocate the structure if it has not already been allocated by a
+ subclass. */
+ if (ret == (struct elf_ARC_link_hash_entry *) NULL)
+ ret = ((struct elf_ARC_link_hash_entry *)
+ bfd_hash_allocate (table,
+ sizeof (struct elf_ARC_link_hash_entry)));
+ if (ret == (struct elf_ARC_link_hash_entry *) NULL)
+ return (struct bfd_hash_entry *) ret;
+
+ /* Call the allocation method of the superclass. */
+ ret = ((struct elf_ARC_link_hash_entry *)
+ _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
+ table, string));
+ if (ret != (struct elf_ARC_link_hash_entry *) NULL)
+ {
+ ret->pcrel_relocs_copied = NULL;
+ }
+
+ return (struct bfd_hash_entry *) ret;
+}
+
+/* Create an ARC ELF linker hash table. */
+
+static struct bfd_link_hash_table *
+elf_ARC_link_hash_table_create (bfd * abfd)
+{
+ struct elf_ARC_link_hash_table *ret;
+
+ ret = ((struct elf_ARC_link_hash_table *)
+ bfd_alloc (abfd, sizeof (struct elf_ARC_link_hash_table)));
+ if (ret == (struct elf_ARC_link_hash_table *) NULL)
+ return NULL;
+
+ if (! _bfd_elf_link_hash_table_init (&ret->root, abfd,
+ elf_ARC_link_hash_newfunc,
+ sizeof (struct elf_ARC_link_hash_entry)))
+ {
+ bfd_release (abfd, ret);
+ return NULL;
+ }
+
+ return &ret->root.root;
+}
+
+/* This function is called via elf_ARC_link_hash_traverse if we are
+ creating a shared object with -Bsymbolic. It discards the space
+ allocated to copy PC relative relocs against symbols which are
+ defined in regular objects. We allocated space for them in the
+ check_relocs routine, but we won't fill them in in the
+ relocate_section routine. */
+
+/*ARGSUSED*/
+static bfd_boolean
+elf_ARC_discard_copies (struct elf_ARC_link_hash_entry * h,
+ void *ignore ATTRIBUTE_UNUSED)
+{
+ struct elf_ARC_pcrel_relocs_copied *s;
+
+ /* We only discard relocs for symbols defined in a regular object. */
+ if (!h->root.def_regular)
+ return TRUE;
+
+ for (s = h->pcrel_relocs_copied; s != NULL; s = s->next)
+ s->section->size -=
+ s->count * sizeof (Elf32_External_Rela); /* relA */
+
+ return TRUE;
+}
+
+/* The HOWTO Array needs to be specified as follows.
+ HOWTO
+ {
+ type --- > Relocation Type
+ rightshift --- > Rightshift the value by this amount.
+ size --- > Size 0- byte , 1-short, 2 -long
+ bitsize --- > Exact bitsize.
+ pcrel --- > PC Relative reloc.
+ bitpos --- > Bit Position.
+ complain_on_overflow ---> What complaint on overflow.
+ function --- > Any special function to be used .
+ name --- > Relocation Name.
+ partial_inplace--> Addend sits partially in place and in
+ Reloc Table.
+ srcmask ---> Source Mask 0 for RELA and corresponding
+ field if USE_REL or partial_inplace
+ is set.
+ dstmask ---> Destination Mask . Destination field mask.
+ pcreloffset ---> pcrel offset . If a PCREL reloc is created
+ and the assembler leaves an offset in here.
+
+ }
+ If in the backend you need to access the howto array, please
+ use the arc_elf_calculate_howto_index function. All changes in
+ the HOWTO array need a corresponding change in the above mentioned
+ function. The need for this function is the presence of a hole
+ in the ARC ABI.
+*/
+
+#define ARC_RELA_HOWTO(type,rightshift,size,bitsz,pcrel,bitpos , \
+function,name,dstmask) \
+ \
+ HOWTO( type,rightshift,size,bitsz,pcrel,bitpos, \
+ complain_overflow_bitfield,function, \
+ name,FALSE,0,dstmask,FALSE)
+
+#define ARCOMPACT_RELA_HOWTO(type,rightshift,size,bitsz,pcrel,bitpos, \
+ function,name,dstmask) \
+ \
+ HOWTO( type,rightshift,size,bitsz,pcrel,bitpos, \
+ complain_overflow_signed,function, \
+ name,FALSE,0,dstmask,FALSE)
+
+
+
+#define ARC_UNSUPPORTED_HOWTO(type,name) \
+ ARC_RELA_HOWTO (type ,0 ,2 ,32,FALSE,0,arc_unsupported_reloc,name,0)
+
+
static reloc_howto_type elf_arc_howto_table[] =
{
/* This reloc does nothing. */
- HOWTO (R_ARC_NONE, /* Type. */
- 0, /* Rightshift. */
- 2, /* Size (0 = byte, 1 = short, 2 = long). */
- 32, /* Bitsize. */
- FALSE, /* PC_relative. */
- 0, /* Bitpos. */
- complain_overflow_bitfield, /* Complain_on_overflow. */
- bfd_elf_generic_reloc, /* Special_function. */
- "R_ARC_NONE", /* Name. */
- TRUE, /* Partial_inplace. */
- 0, /* Src_mask. */
- 0, /* Dst_mask. */
- FALSE), /* PCrel_offset. */
-
+ ARC_RELA_HOWTO (R_ARC_NONE ,0 ,2 ,32,FALSE,0,bfd_elf_generic_reloc,
+ "R_ARC_NONE",0),
+ ARC_RELA_HOWTO (R_ARC_8 ,0 ,0 , 8,FALSE,0,bfd_elf_generic_reloc,
+ "R_ARC_8" ,0xff),
+ ARC_RELA_HOWTO (R_ARC_16 ,0 ,1 ,16,FALSE,0,bfd_elf_generic_reloc,
+ "R_ARC_16",0xffff),
+ ARC_RELA_HOWTO (R_ARC_24 ,0 ,2 ,24,FALSE,0,bfd_elf_generic_reloc,
+ "R_ARC_24",0xffffff),
/* A standard 32 bit relocation. */
- HOWTO (R_ARC_32, /* Type. */
- 0, /* Rightshift. */
- 2, /* Size (0 = byte, 1 = short, 2 = long). */
- 32, /* Bitsize. */
- FALSE, /* PC_relative. */
- 0, /* Bitpos. */
- complain_overflow_bitfield, /* Complain_on_overflow. */
- bfd_elf_generic_reloc, /* Special_function. */
- "R_ARC_32", /* Name. */
- TRUE, /* Partial_inplace. */
- 0xffffffff, /* Src_mask. */
- 0xffffffff, /* Dst_mask. */
- FALSE), /* PCrel_offset. */
-
+ ARC_RELA_HOWTO (R_ARC_32 ,0 ,2 ,32,FALSE,0,bfd_elf_generic_reloc,
+ "R_ARC_32",-1),
/* A 26 bit absolute branch, right shifted by 2. */
- HOWTO (R_ARC_B26, /* Type. */
- 2, /* Rightshift. */
- 2, /* Size (0 = byte, 1 = short, 2 = long). */
- 26, /* Bitsize. */
- FALSE, /* PC_relative. */
- 0, /* Bitpos. */
- complain_overflow_bitfield, /* Complain_on_overflow. */
- bfd_elf_generic_reloc, /* Special_function. */
- "R_ARC_B26", /* Name. */
- TRUE, /* Partial_inplace. */
- 0x00ffffff, /* Src_mask. */
- 0x00ffffff, /* Dst_mask. */
- FALSE), /* PCrel_offset. */
-
+ ARC_RELA_HOWTO (R_ARC_B26 ,2 ,2 ,26,FALSE,0,bfd_elf_generic_reloc,
+ "R_ARC_B26",0xffffff),
/* A relative 22 bit branch; bits 21-2 are stored in bits 26-7. */
- HOWTO (R_ARC_B22_PCREL, /* Type. */
- 2, /* Rightshift. */
- 2, /* Size (0 = byte, 1 = short, 2 = long). */
- 22, /* Bitsize. */
- TRUE, /* PC_relative. */
- 7, /* Bitpos. */
- complain_overflow_signed, /* Complain_on_overflow. */
- arc_elf_b22_pcrel, /* Special_function. */
- "R_ARC_B22_PCREL", /* Name. */
- TRUE, /* Partial_inplace. */
- 0x07ffff80, /* Src_mask. */
- 0x07ffff80, /* Dst_mask. */
- FALSE), /* PCrel_offset. */
+ ARC_RELA_HOWTO (R_ARC_B22_PCREL,2,2,22,TRUE,7,arc_elf_b22_pcrel,
+ "R_ARC_B22_PCREL",0x7ffff80),
+ ARC_RELA_HOWTO (R_ARC_H30 ,2 ,2 ,32, FALSE, 0, bfd_elf_generic_reloc,
+ "R_ARC_H30",-1),
+ ARC_UNSUPPORTED_HOWTO(R_ARC_N8,"R_ARC_N8"),
+ ARC_UNSUPPORTED_HOWTO(R_ARC_N16,"R_ARC_N16"),
+ ARC_UNSUPPORTED_HOWTO(R_ARC_N24,"R_ARC_N24"),
+ ARC_UNSUPPORTED_HOWTO(R_ARC_N32,"R_ARC_N32"),
+ ARC_UNSUPPORTED_HOWTO(R_ARC_SDA,"R_ARC_SDA"),
+ ARC_UNSUPPORTED_HOWTO(R_ARC_SECTOFF,"R_ARC_SECTOFF"),
+
+ /* FIXME: Change complaint to complain_overflow_signed. */
+ /* Tangent-A5 relocations. */
+ ARCOMPACT_RELA_HOWTO (R_ARC_S21H_PCREL,1,2,21,TRUE,0,arcompact_elf_me_reloc,
+ "R_ARC_S21H_PCREL",0x7feffc0),
+ ARCOMPACT_RELA_HOWTO (R_ARC_S21W_PCREL,2,2,21,TRUE,0,arcompact_elf_me_reloc,
+ "R_ARC_S21W_PCREL",0x7fcffc0),
+ ARCOMPACT_RELA_HOWTO (R_ARC_S25H_PCREL,1,2,25,TRUE,0,arcompact_elf_me_reloc,
+ "R_ARC_S25H_PCREL",0x7feffcf),
+ ARCOMPACT_RELA_HOWTO (R_ARC_S25W_PCREL,2,2,25,TRUE,0,arcompact_elf_me_reloc,
+ "R_ARC_S25W_PCREL",0x7fcffcf),
+
+ ARCOMPACT_RELA_HOWTO (R_ARC_SDA32,0,2,32,FALSE,0,arcompact_elf_me_reloc,
+ "R_ARC_SDA32",-1),
+ ARCOMPACT_RELA_HOWTO (R_ARC_SDA_LDST,0,2,9,FALSE,15,arcompact_elf_me_reloc,
+ "R_ARC_SDA_LDST",0x00ff8000),
+ ARCOMPACT_RELA_HOWTO (R_ARC_SDA_LDST1,1,2,10,FALSE,15,arcompact_elf_me_reloc,
+ "R_ARC_SDA_LDST1",0x00ff8000),
+ ARCOMPACT_RELA_HOWTO (R_ARC_SDA_LDST2,2,2,11,FALSE,15,arcompact_elf_me_reloc,
+ "R_ARC_SDA_LDST2",0x00ff8000),
+
+ ARCOMPACT_RELA_HOWTO (R_ARC_SDA16_LD,0,2,9,FALSE,0,arcompact_elf_me_reloc,
+ "R_ARC_SDA16_LD",0x01ff),
+ ARCOMPACT_RELA_HOWTO (R_ARC_SDA16_LD1,1,2,10,FALSE,0,arcompact_elf_me_reloc,
+ "R_ARC_SDA16_LD1",0x01ff),
+ ARCOMPACT_RELA_HOWTO (R_ARC_SDA16_LD2,2,2,11,FALSE,0,arcompact_elf_me_reloc,
+ "R_ARC_SDA16_LD2",0x01ff),
+
+ ARCOMPACT_RELA_HOWTO (R_ARC_S13_PCREL,2,1,13,TRUE,0,arcompact_elf_me_reloc,
+ "R_ARC_S13_PCREL",0x7ff),
+
+ ARC_UNSUPPORTED_HOWTO (R_ARC_W,"R_ARC_W"),
+
+/* 'Middle-endian' (ME) 32-bit word relocations, stored in two half-words.
+ The individual half-words are stored in the native endian of the
+ machine; this is how all 32-bit instructions and long-words are stored
+ in the ARCompact ISA in the executable section. */
+
+ ARC_RELA_HOWTO (R_ARC_32_ME ,0 ,2 ,32, FALSE, 0, arcompact_elf_me_reloc,
+ "R_ARC_32_ME",-1),
+
+ ARC_UNSUPPORTED_HOWTO (R_ARC_N32_ME,"R_ARC_N32_ME"),
+ ARC_UNSUPPORTED_HOWTO (R_ARC_SECTOFF_ME,"R_ARC_SECTOFF_ME"),
+
+ ARCOMPACT_RELA_HOWTO (R_ARC_SDA32_ME,0,2,32,FALSE,0,arcompact_elf_me_reloc,
+ "R_ARC_SDA32_ME",-1),
+
+ ARC_UNSUPPORTED_HOWTO (R_ARC_W_ME,"R_ARC_W_ME"),
+ ARC_UNSUPPORTED_HOWTO (R_ARC_H30_ME,"R_ARC_H30_ME"),
+ ARC_UNSUPPORTED_HOWTO (R_ARC_SECTOFF_U8,"R_ARC_SECTOFF_U8"),
+ ARC_UNSUPPORTED_HOWTO (R_ARC_SECTOFF_S9,"R_ARC_SECTOFF_S9"),
+ ARC_UNSUPPORTED_HOWTO (R_AC_SECTOFF_U8,"R_AC_SECTOFF_U8"),
+ ARC_UNSUPPORTED_HOWTO (R_AC_SECTOFF_U8_1,"R_AC_SECTOFF_U8_1"),
+ ARC_UNSUPPORTED_HOWTO (R_AC_SECTOFF_U8_2,"R_ARC_SECTOFF_U8_2"),
+ ARC_UNSUPPORTED_HOWTO (R_AC_SECTOFF_S9,"R_AC_SECTOFF_S9"),
+ ARC_UNSUPPORTED_HOWTO (R_AC_SECTOFF_S9_1,"R_AC_SECTOFF_S9_1"),
+ ARC_UNSUPPORTED_HOWTO (R_AC_SECTOFF_S9_2,"R_AC_SECTOFF_S9_2"),
+ ARC_UNSUPPORTED_HOWTO (R_ARC_SECTOFF_ME_1,"R_ARC_SECTOFF_ME_1"),
+ ARC_UNSUPPORTED_HOWTO (R_ARC_SECTOFF_ME_2,"R_ARC_SECTOFF_ME_2"),
+ ARC_UNSUPPORTED_HOWTO (R_ARC_SECTOFF_1,"R_ARC_SECTOFF_1"),
+ ARC_UNSUPPORTED_HOWTO (R_ARC_SECTOFF_2,"R_ARC_SECTOFF_2"),
+ /* There is a gap here of 5. */
+ #define R_ARC_hole_base 0x2d
+ #define R_ARC_reloc_hole_gap 5
+
+ ARC_RELA_HOWTO (R_ARC_PC32, 0, 2, 32, FALSE, 0, arcompact_elf_me_reloc,
+ "R_ARC_PC32",-1),
+ /* PC relative was true for this earlier. */
+ ARC_RELA_HOWTO (R_ARC_GOTPC32, 0, 2, 32, FALSE, 0, arcompact_elf_me_reloc,
+ "R_ARC_GOTPC32",-1),
+
+ ARC_RELA_HOWTO (R_ARC_PLT32, 0, 2, 32, FALSE, 0, arcompact_elf_me_reloc,
+ "R_ARC_PLT32",-1),
+
+ ARC_RELA_HOWTO (R_ARC_COPY, 0, 2, 32, FALSE,0 , arcompact_elf_me_reloc,
+ "R_ARC_COPY",-1),
+
+ ARC_RELA_HOWTO (R_ARC_GLOB_DAT, 0, 2, 32, FALSE,0 , arcompact_elf_me_reloc,
+ "R_ARC_GLOB_DAT",-1),
+
+ ARC_RELA_HOWTO (R_ARC_JMP_SLOT, 0, 2, 32, FALSE,0 , arcompact_elf_me_reloc,
+ "R_ARC_JMP_SLOT",-1),
+
+ ARC_RELA_HOWTO (R_ARC_RELATIVE, 0, 2, 32, FALSE,0 , arcompact_elf_me_reloc,
+ "R_ARC_RELATIVE",-1),
+
+ ARC_RELA_HOWTO (R_ARC_GOTOFF, 0, 2, 32, FALSE,0 , arcompact_elf_me_reloc,
+ "R_ARC_GOTOFF",-1),
+
+ ARC_RELA_HOWTO (R_ARC_GOTPC, 0, 2, 32, FALSE,0 , arcompact_elf_me_reloc,
+ "R_ARC_GOTPC",-1),
};
+/*Indicates whether the value contained in
+ the relocation type is signed, usnigned
+ or the reclocation type is unsupported.
+ 0 -> unsigned reloc type
+ 1 -> signed reloc type
+ -1 -> reloc type unsupported*/
+short arc_signed_reloc_type[] =
+{
+ 0, // R_ARC_NONE Reloc Number
+ 0, // R_ARC_8
+ 0, // R_ARC_16
+ 0, // R_ARC_24
+ 0, // R_ARC_32
+ 0, // R_ARC_B26
+ 1, // R_ARC_B22_PCREL 0x6
+
+ 0, // R_ARC_H30 0x7
+ -1, // R_ARC_N8
+ -1, // R_ARC_N16
+ -1, // R_ARC_N24
+ -1, // R_ARC_N32
+ -1, // R_ARC_SDA
+ -1, // R_ARC_SECTOFF 0xD
+
+ 1, // R_ARC_S21H_PCREL 0xE
+ 1, // R_ARC_S21W_PCREL
+ 1, // R_ARC_S25H_PCREL
+ 1, // R_ARC_S25W_PCREL 0x11
+
+ 1, // R_ARC_SDA32 0x12
+ 1, // R_ARC_SDA_LDST
+ 1, // R_ARC_SDA_LDST1
+ 1, // R_ARC_SDA_LDST2 0x15
+
+ 1, // R_ARC_SDA16_LD 0x16
+ 1, // R_ARC_SDA16_LD1
+ 1, // R_ARC_SDA16_LD2 0x18
+
+ 1, // R_ARC_S13_PCREL 0x19
+
+ -1, // R_ARC_W 0x1A
+ 0, // R_ARC_32_ME 0x1B
+
+ -1, // R_ARC_N32_ME 0x1c
+ -1, // R_ARC_SECTOFF_ME 0x1D
+
+ 0, // R_ARC_SDA32_ME 0x1E
+
+ -1, // R_ARC_W_ME 0x1F
+ -1, // R_ARC_H30_ME
+ -1, // R_ARC_SECTOFF_U8
+ -1, // R_ARC_SECTOFF_S9
+ -1, // R_AC_SECTOFF_U8
+ -1, // R_AC_SECTOFF_U8_1
+ -1, // R_AC_SECTOFF_U8_2
+ -1, // R_AC_SECTOFF_S9
+ -1, // R_AC_SECTOFF_S9_1
+ -1, // R_AC_SECTOFF_S9_2
+ -1, // R_ARC_SECTOFF_ME_1
+ -1, // R_ARC_SECTOFF_ME_2
+ -1, // R_ARC_SECTOFF_1
+ -1, // R_ARC_SECTOFF_2 0x2c
+
+ -1, // R_ARC_hole_base starts here 0x2d
+ -1, // 0x2e
+ -1, // 0x2f
+ -1, // 0x30
+ -1, // ends here 0x31
+
+ 0, // R_ARC_PC32 0x32
+ 0, // R_ARC_GOTPC32
+ 0, // R_ARC_PLT32
+ 0, // R_ARC_COPY
+ 0, // R_ARC_GLOB_DAT
+ 0, // R_ARC_JMP_SLOT
+ 0, // R_ARC_RELATIVE
+ 0, // R_ARC_GOTOFF
+ 0, // R_ARC_GOTPC 0x3a
+ 0, // R_ARC_GOT32 0x3b
+};
+
+
+
+static bfd_reloc_status_type
+arc_unsupported_reloc (bfd * ibfd ATTRIBUTE_UNUSED,
+ arelent * rel ATTRIBUTE_UNUSED,
+ asymbol * sym ATTRIBUTE_UNUSED,
+ void *ptr ATTRIBUTE_UNUSED,
+ asection * section ATTRIBUTE_UNUSED,
+ bfd *obfd ATTRIBUTE_UNUSED,
+ char ** data ATTRIBUTE_UNUSED
+ )
+{
+ return bfd_reloc_notsupported;
+}
+
+
/* Map BFD reloc types to ARC ELF reloc types. */
struct arc_reloc_map
{
- bfd_reloc_code_real_type bfd_reloc_val;
- unsigned char elf_reloc_val;
+ enum bfd_reloc_code_real bfd_reloc_val;
+ enum elf_arc_reloc_type elf_reloc_val;
};
static const struct arc_reloc_map arc_reloc_map[] =
{
- { BFD_RELOC_NONE, R_ARC_NONE, },
+ { BFD_RELOC_NONE, R_ARC_NONE },
+ { BFD_RELOC_8, R_ARC_8 },
+ { BFD_RELOC_16,R_ARC_16 },
+ { BFD_RELOC_24, R_ARC_24 },
{ BFD_RELOC_32, R_ARC_32 },
{ BFD_RELOC_CTOR, R_ARC_32 },
{ BFD_RELOC_ARC_B26, R_ARC_B26 },
{ BFD_RELOC_ARC_B22_PCREL, R_ARC_B22_PCREL },
+ { BFD_RELOC_ARC_S21H_PCREL, R_ARC_S21H_PCREL },
+ { BFD_RELOC_ARC_S21W_PCREL, R_ARC_S21W_PCREL },
+ { BFD_RELOC_ARC_S25H_PCREL, R_ARC_S25H_PCREL },
+ { BFD_RELOC_ARC_S25W_PCREL, R_ARC_S25W_PCREL },
+ { BFD_RELOC_ARC_S13_PCREL, R_ARC_S13_PCREL },
+ { BFD_RELOC_ARC_32_ME, R_ARC_32_ME },
+ { BFD_RELOC_ARC_PC32, R_ARC_PC32 },
+ { BFD_RELOC_ARC_GOTPC32, R_ARC_GOTPC32 },
+ { BFD_RELOC_ARC_COPY , R_ARC_COPY },
+ { BFD_RELOC_ARC_JMP_SLOT, R_ARC_JMP_SLOT },
+ { BFD_RELOC_ARC_GLOB_DAT, R_ARC_GLOB_DAT },
+ { BFD_RELOC_ARC_GOTOFF , R_ARC_GOTOFF },
+ { BFD_RELOC_ARC_GOTPC , R_ARC_GOTPC },
+ { BFD_RELOC_ARC_PLT32 , R_ARC_PLT32 },
+
+ { BFD_RELOC_ARC_SDA, R_ARC_SDA },
+ { BFD_RELOC_ARC_SDA32, R_ARC_SDA32 },
+ { BFD_RELOC_ARC_SDA32_ME, R_ARC_SDA32_ME },
+ { BFD_RELOC_ARC_SDA_LDST, R_ARC_SDA_LDST },
+ { BFD_RELOC_ARC_SDA_LDST1, R_ARC_SDA_LDST1 },
+ { BFD_RELOC_ARC_SDA_LDST2, R_ARC_SDA_LDST2 },
+ { BFD_RELOC_ARC_SDA16_LD, R_ARC_SDA16_LD },
+ { BFD_RELOC_ARC_SDA16_LD1, R_ARC_SDA16_LD1 },
+ { BFD_RELOC_ARC_SDA16_LD2, R_ARC_SDA16_LD2 }
};
static reloc_howto_type *
-bfd_elf32_bfd_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
+arc_elf32_bfd_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
bfd_reloc_code_real_type code)
{
unsigned int i;
-
- for (i = ARRAY_SIZE (arc_reloc_map); i--;)
- if (arc_reloc_map[i].bfd_reloc_val == code)
- return elf_arc_howto_table + arc_reloc_map[i].elf_reloc_val;
+ for (i = 0;
+ i < sizeof (arc_reloc_map) / sizeof (struct arc_reloc_map);
+ i++)
+ {
+ if (arc_reloc_map[i].bfd_reloc_val == code)
+ {
+ enum elf_arc_reloc_type r_type;
+ r_type = arc_reloc_map[i].elf_reloc_val;
+ return arc_elf_calculate_howto_index(r_type);
+ }
+ }
return NULL;
}
@@ -163,6 +576,19 @@
return NULL;
}
+/* Calculate the howto index. */
+static reloc_howto_type *
+arc_elf_calculate_howto_index(enum elf_arc_reloc_type r_type)
+{
+ BFD_ASSERT (r_type < (unsigned int) R_ARC_max);
+ BFD_ASSERT ((r_type < (unsigned int) R_ARC_hole_base)
+ || (r_type
+ >= (unsigned int) R_ARC_hole_base + R_ARC_reloc_hole_gap));
+ if (r_type > R_ARC_hole_base)
+ r_type -= R_ARC_reloc_hole_gap;
+ return &elf_arc_howto_table[r_type];
+
+}
/* Set the howto pointer for an ARC ELF reloc. */
static void
@@ -170,11 +596,64 @@
arelent *cache_ptr,
Elf_Internal_Rela *dst)
{
- unsigned int r_type;
+ enum elf_arc_reloc_type r_type;
+
r_type = ELF32_R_TYPE (dst->r_info);
- BFD_ASSERT (r_type < (unsigned int) R_ARC_max);
- cache_ptr->howto = &elf_arc_howto_table[r_type];
+ cache_ptr->howto = arc_elf_calculate_howto_index(r_type);
+}
+
+/* Merge backend specific data from an object file to the output
+ object file when linking. */
+static bfd_boolean
+arc_elf_merge_private_bfd_data (bfd *ibfd, bfd *obfd)
+{
+ unsigned short mach_ibfd;
+ static unsigned short mach_obfd = EM_NONE;
+
+ if ( bfd_get_flavour (ibfd) != bfd_target_elf_flavour
+ || bfd_get_flavour (obfd) != bfd_target_elf_flavour)
+ return TRUE;
+ if (bfd_count_sections (ibfd) == 0)
+ return TRUE ; /* For the case of empty archive files */
+
+ mach_ibfd = elf_elfheader (ibfd)->e_machine;
+
+ /* Check if we have the same endianess. */
+ if (! _bfd_generic_verify_endian_match (ibfd, obfd))
+ {
+ _bfd_error_handler (_("\
+ERROR: Endian Match failed . Attempting to link %B with binary %s \
+of opposite endian-ness"),
+ ibfd, bfd_get_filename (obfd));
+ return FALSE;
+ }
+
+ if (mach_obfd == EM_NONE)
+ {
+ mach_obfd = mach_ibfd;
+ }
+ else
+ {
+ if((mach_ibfd==EM_ARC && mach_obfd==EM_ARCOMPACT) ||
+ (mach_ibfd==EM_ARCOMPACT && mach_obfd==EM_ARC))
+ {
+ _bfd_error_handler (_("\ERROR: Attempting to link an %s binary(%B) \
+with a binary incompatible %s binary(%s)"),
+ (mach_ibfd == EM_ARC) ? "A4" : "ARCompact",
+ ibfd,
+ (mach_obfd == EM_ARC) ? "A4" : "ARCompact",
+ bfd_get_filename (obfd));
+ return FALSE;
+ }
+ }
+
+ if (bfd_get_mach (obfd) < bfd_get_mach (ibfd))
+ {
+ return bfd_set_arch_mach (obfd, bfd_arch_arc, bfd_get_mach(ibfd));
+ }
+
+ return TRUE;
}
/* Set the right machine number for an ARC ELF file. */
@@ -182,30 +661,30 @@
static bfd_boolean
arc_elf_object_p (bfd *abfd)
{
- unsigned int mach = bfd_mach_arc_6;
+ int mach;
+ unsigned long arch = elf_elfheader (abfd)->e_flags & EF_ARC_MACH;
- if (elf_elfheader(abfd)->e_machine == EM_ARC)
+ switch (arch)
{
- unsigned long arch = elf_elfheader (abfd)->e_flags & EF_ARC_MACH;
-
- switch (arch)
- {
- case E_ARC_MACH_ARC5:
- mach = bfd_mach_arc_5;
- break;
- default:
- case E_ARC_MACH_ARC6:
- mach = bfd_mach_arc_6;
- break;
- case E_ARC_MACH_ARC7:
- mach = bfd_mach_arc_7;
- break;
- case E_ARC_MACH_ARC8:
- mach = bfd_mach_arc_8;
- break;
- }
+ case E_ARC_MACH_A4:
+ mach = bfd_mach_arc_a4;
+ break;
+ case E_ARC_MACH_A5:
+ mach = bfd_mach_arc_a5;
+ break;
+ case E_ARC_MACH_ARC600:
+ mach = bfd_mach_arc_arc600;
+ break;
+ case E_ARC_MACH_ARC700:
+ mach = bfd_mach_arc_arc700;
+ break;
+ default:
+ /* Unknown cpu type. ??? What to do? */
+ return FALSE;
}
- return bfd_default_set_arch_mach (abfd, bfd_arch_arc, mach);
+
+ (void) bfd_default_set_arch_mach (abfd, bfd_arch_arc, mach);
+ return TRUE;
}
/* The final processing done just before writing out an ARC ELF object file.
@@ -215,39 +694,2468 @@
arc_elf_final_write_processing (bfd *abfd,
bfd_boolean linker ATTRIBUTE_UNUSED)
{
+ int mach;
unsigned long val;
- switch (bfd_get_mach (abfd))
+ switch (mach = bfd_get_mach (abfd))
{
- case bfd_mach_arc_5:
- val = E_ARC_MACH_ARC5;
+ case bfd_mach_arc_a4:
+ val = E_ARC_MACH_A4;
+ elf_elfheader (abfd)->e_machine = EM_ARC;
+ break;
+ case bfd_mach_arc_a5:
+ val = E_ARC_MACH_A5;
+ elf_elfheader (abfd)->e_machine = EM_ARCOMPACT;
+ break;
+ case bfd_mach_arc_arc600:
+ val = E_ARC_MACH_ARC600;
+ elf_elfheader (abfd)->e_machine = EM_ARCOMPACT;
+ break;
+ case bfd_mach_arc_arc700:
+ val = E_ARC_MACH_ARC700;
+ elf_elfheader (abfd)->e_machine = EM_ARCOMPACT;
break;
default:
- case bfd_mach_arc_6:
- val = E_ARC_MACH_ARC6;
- break;
- case bfd_mach_arc_7:
- val = E_ARC_MACH_ARC7;
- break;
- case bfd_mach_arc_8:
- val = E_ARC_MACH_ARC8;
- break;
+ abort();
}
+
elf_elfheader (abfd)->e_flags &=~ EF_ARC_MACH;
elf_elfheader (abfd)->e_flags |= val;
}
-#define TARGET_LITTLE_SYM bfd_elf32_littlearc_vec
-#define TARGET_LITTLE_NAME "elf32-littlearc"
-#define TARGET_BIG_SYM bfd_elf32_bigarc_vec
-#define TARGET_BIG_NAME "elf32-bigarc"
-#define ELF_ARCH bfd_arch_arc
-#define ELF_MACHINE_CODE EM_ARC
-#define ELF_MAXPAGESIZE 0x1000
+/* Handle an ARCompact 'middle-endian' relocation. */
+static bfd_reloc_status_type
+arcompact_elf_me_reloc (bfd *abfd ,
+ arelent *reloc_entry,
+ asymbol *symbol_in,
+ void *data,
+ asection *input_section,
+ bfd *output_bfd,
+ char ** error_message ATTRIBUTE_UNUSED)
+{
+ unsigned long insn;
+#ifdef USE_REL
+ unsigned long offset
+#endif
+ bfd_vma sym_value;
+ enum elf_arc_reloc_type r_type;
+ bfd_vma addr = reloc_entry->address;
+ bfd_byte *hit_data = addr + (bfd_byte *) data;
-#define elf_info_to_howto 0
-#define elf_info_to_howto_rel arc_info_to_howto_rel
-#define elf_backend_object_p arc_elf_object_p
-#define elf_backend_final_write_processing arc_elf_final_write_processing
+ r_type = reloc_entry->howto->type;
+
+ if (output_bfd != NULL)
+ {
+ reloc_entry->address += input_section->output_offset;
+
+ /* In case of relocateable link and if the reloc is against a
+ section symbol, the addend needs to be adjusted according to
+ where the section symbol winds up in the output section. */
+
+ if ((symbol_in->flags & BSF_SECTION_SYM) && symbol_in->section)
+ reloc_entry->addend += symbol_in->section->output_offset;
+
+ return bfd_reloc_ok;
+ }
+
+ /* Return an error if the symbol is not defined. An undefined weak
+ symbol is considered to have a value of zero (SVR4 ABI, p. 4-27). */
+
+ if (symbol_in != NULL && bfd_is_und_section (symbol_in->section)
+ && ((symbol_in->flags & BSF_WEAK) == 0))
+ return bfd_reloc_undefined;
+
+ if (bfd_is_com_section (symbol_in->section))
+ sym_value = 0;
+ else
+ sym_value = (symbol_in->value
+ + symbol_in->section->output_section->vma
+ + symbol_in->section->output_offset);
+
+ sym_value += reloc_entry->addend;
+
+ if (r_type != R_ARC_32_ME) {
+ sym_value -= (input_section->output_section->vma
+ + input_section->output_offset);
+ sym_value -= (reloc_entry->address & ~0x3);
+ }
+
+ insn = bfd_get_32_me(abfd, hit_data);
+
+ switch(r_type)
+ {
+ case R_ARC_S21H_PCREL:
+#ifdef USE_REL
+ /* Retrieve the offset from the instruction, if any. */
+ /* Extract the first 10 bits from Position 6 to 15 in insn. */
+ offset = ((insn << 16) >> 22) << 10;
+
+ /* Extract the remaining 10 bits from Position 17 to 26 in insn. */
+ offset |= ((insn << 5) >> 22);
+
+ /* Fill in 1 bit to get the 21 bit Offset Value. */
+ offset = offset << 1;
+
+ /* Ramana : No addends remain in place. */
+ /* sym_value += offset; */
+
+#endif /* USE_REL. */
+ /* Extract the instruction opcode alone from 'insn'. */
+ insn = insn & 0xf801003f;
+ insn |= ((((sym_value >> 1) & 0x3ff) << 17)
+ | (((sym_value >> 1) & 0xffc00) >> 4));
+ break;
+ case R_ARC_S21W_PCREL:
+#ifdef USE_REL
+ /* Retrieve the offset from the instruction, if any */
+ /* Extract the first 10 bits from Position 6 to 15 in insn */
+ offset = ((insn << 16) >> 22) << 9;
+
+ /* Extract the remaining 9 bits from Position 18 to 26 in insn */
+ offset |= ((insn << 5) >> 23);
+
+ /* Fill in 2 bits to get the 25 bit Offset Value */
+ offset = offset << 2;
+
+ /* No addends remain in place */
+ /* sym_value += offset; */
+
+#endif /* USE_REL. */
+ /* Extract the instruction opcode alone from 'insn' */
+ insn = insn & 0xf803003f;
+
+ insn |= ((((sym_value >> 2) & 0x1ff) << 18)
+ | (((sym_value >> 2) & 0x7fe00) >> 3));
+ break;
+ case R_ARC_S25H_PCREL:
+#ifdef USE_REL
+ /* Retrieve the offset from the instruction, if any */
+ /* Extract the high 4 bits from Position 0 to 3 in insn */
+ offset = ((insn << 28) >> 28) << 10;
+
+ /* Extract the next 10 bits from Position 6 to 15 in insn */
+ offset |= ((insn << 16) >> 22);
+ offset = offset << 10;
+
+ /* Extract the remaining 10 bits from Position 17 to 26 in insn */
+ offset |= ((insn << 5) >> 22);
+
+ /* Fill in 1 bit to get the 25 bit Offset Value */
+ offset = offset << 1;
+
+ /* Ramana : No addends remain in place. */
+ /* sym_value += offset; */
+
+
+#endif /* USE_REL. */
+ /* Extract the instruction opcode alone from 'insn' */
+ insn = insn & 0xf8010030;
+
+ insn |= ((((sym_value >> 1) & 0x3ff) << 17)
+ | (((sym_value >> 1) & 0xffc00) >> 4)
+ | (((sym_value >> 1) & 0xf00000) >> 20));
+ break;
+ case R_ARC_PLT32:
+ break;
+ case R_ARC_S25W_PCREL:
+#ifdef USE_REL
+ /* Retrieve the offset from the instruction, if any */
+ /* Extract the high 4 bits from Position 0 to 3 in insn */
+ offset = ((insn << 28) >> 28) << 10;
+
+ /* Extract the next 10 bits from Position 6 to 15 in insn */
+ offset |= ((insn << 16) >> 22);
+ offset = offset << 9;
+
+ /* Extract the remaining 9 bits from Position 18 to 26 in insn */
+ offset |= ((insn << 5) >> 23);
+
+ /* Fill in 2 bits to get the 25 bit Offset Value */
+ offset = offset << 2;
+
+ /* Ramana : No addends remain in place */
+ /* sym_value += offset; */
+
+#endif /* USE_REL. */
+ /* Extract the instruction opcode alone from 'insn' */
+ insn = insn & 0xf8030030;
+
+ insn |= ((((sym_value >> 2) & 0x1ff) << 18)
+ | (((sym_value >> 2) & 0x7fe00) >> 3)
+ | (((sym_value >> 2) & 0x780000) >> 19));
+ break;
+ case R_ARC_S13_PCREL:
+#ifdef USE_REL
+ /* Retrieve the offset from the instruction, if any */
+ /* Extract the 11 bits from Position 0 to 10 in insn */
+ offset = (insn << 5) >> 21;
+
+ /* Fill in 2 bits to get the 13 bit Offset Value */
+ offset = offset << 2;
+
+ /* No addends remain in place */
+ /* sym_value += offset; */
+#endif
+ /* Extract the instruction opcode alone from 'insn' */
+ insn = (insn & 0xf800ffff);
+ insn |= ((sym_value >> 2) & 0x7ff) << 16;
+ break;
+ case R_ARC_GOTPC32:
+ case R_ARC_32_ME:
+ insn = sym_value;
+ break;
+ default:
+ return bfd_reloc_notsupported;
+ break;
+ }
+
+ /* Middle-Endian Instruction Encoding only for executable code */
+ /* FIXME:: I am still not sure about this. Ramana . */
+ if (input_section && (input_section->flags & SEC_CODE))
+ bfd_put_32_me(abfd, insn, hit_data);
+ else
+ bfd_put_32(abfd, insn, hit_data);
+
+ return bfd_reloc_ok;
+}
+
+static bfd_vma
+bfd_get_32_me (bfd * abfd,const unsigned char * data)
+{
+ bfd_vma value = 0;
+
+ if (bfd_big_endian(abfd)) {
+ value = bfd_get_32 (abfd, data);
+ }
+ else {
+ value = ((bfd_get_8 (abfd, data) & 255) << 16);
+ value |= ((bfd_get_8 (abfd, data + 1) & 255) << 24);
+ value |= (bfd_get_8 (abfd, data + 2) & 255);
+ value |= ((bfd_get_8 (abfd, data + 3) & 255) << 8);
+ }
+
+ return value;
+}
+
+static void
+bfd_put_32_me (bfd *abfd, bfd_vma value,unsigned char *data)
+{
+ bfd_put_16 (abfd, (value & 0xffff0000) >> 16, data);
+ bfd_put_16 (abfd, value & 0xffff, data + 2);
+}
+
+
+/* ******************************************
+ * PIC-related routines for the arc backend
+ * ******************************************/
+
+/* This will be overridden by the interpreter specified in
+ the linker specs */
+#define ELF_DYNAMIC_INTERPRETER "/sbin/ld-uClibc.so"
+
+/* size of one plt entry */
+#define PLT_ENTRY_SIZE 12
+
+/* The zeroth entry in the absolute plt entry */
+static const bfd_byte elf_arc_abs_plt0_entry [2 * PLT_ENTRY_SIZE] =
+ {
+ 0x00, 0x16, /* ld %r11, [0] */
+ 0x0b, 0x70,
+ 0x00, 0x00,
+ 0x00, 0x00,
+ 0x00, 0x16, /* ld %r10, [0] */
+ 0x0a, 0x70, /* */
+ 0,0,
+ 0,0,
+ 0x20, 0x20, /* j [%r10] */
+ 0x80, 0x02, /* ---"---- */
+ 0x00, 0x00, /* pad */
+ 0x00, 0x00 /* pad */
+ };
+
+/* Contents of the subsequent entries in the absolute plt */
+static const bfd_byte elf_arc_abs_pltn_entry [PLT_ENTRY_SIZE] =
+ {
+ 0x30, 0x27, /* ld %r12, [%pc,func@gotpc] */
+ 0x8c, 0x7f, /* ------ " " -------------- */
+ 0x00, 0x00, /* ------ " " -------------- */
+ 0x00, 0x00, /* ------ " " -------------- */
+ 0x20, 0x7c, /* j_s.d [%r12] */
+ 0xef, 0x74, /* mov_s %r12, %pcl */
+ };
+
+/* The zeroth entry in the pic plt entry */
+static const bfd_byte elf_arc_pic_plt0_entry [2 * PLT_ENTRY_SIZE] =
+ {
+ 0x30, 0x27, /* ld %r11, [pcl,0] : 0 to be replaced by _DYNAMIC@GOTPC+4 */
+ 0x8b, 0x7f,
+ 0x00, 0x00,
+ 0x00, 0x00,
+ 0x30, 0x27, /* ld %r10, [pcl,0] : 0 to be replaced by -DYNAMIC@GOTPC+8 */
+ 0x8a, 0x7f, /* */
+ 0,0,
+ 0,0,
+ 0x20, 0x20, /* j [%r10] */
+ 0x80, 0x02, /* ---"---- */
+ 0x00, 0x00, /* pad */
+ 0x00, 0x00 /* pad */
+ };
+
+/* Contents of the subsequent entries in the pic plt */
+static const bfd_byte elf_arc_pic_pltn_entry [PLT_ENTRY_SIZE] =
+ {
+ 0x30, 0x27, /* ld %r12, [%pc,func@got] */
+ 0x8c, 0x7f, /* ------ " " -------------- */
+ 0x00, 0x00, /* ------ " " -------------- */
+ 0x00, 0x00, /* ------ " " -------------- */
+ 0x20, 0x7c, /* j_s.d [%r12] */
+ 0xef, 0x74, /* mov_s %r12, %pcl */
+ };
+
+
+/* Function: arc_plugin_one_reloc
+ * Brief : Fill in the relocated value of the symbol into an insn
+ * depending on the relocation type. The instruction is
+ * assumed to have been read in the correct format (ME / LE/ BE)
+ * Args : 1. insn : the original insn into which the relocated
+ * value has to be filled in.
+ * 2. rel : the relocation entry.
+ * 3. value : the value to be plugged in the insn.
+ * 4. overflow_detected : Pointer to short to indicate relocation
+ * overflows.
+ * 5. symbol_defined : bool value representing if the symbol
+ * definition is present.
+ * Returns : the insn with the relocated value plugged in.
+ */
+static unsigned long
+arc_plugin_one_reloc (unsigned long insn, Elf_Internal_Rela *rel,
+ int value,
+ short *overflow_detected, bfd_boolean symbol_defined
+ )
+{
+ unsigned long offset;
+ long long check_overfl_pos,check_overfl_neg;
+ reloc_howto_type *howto;
+ enum elf_arc_reloc_type r_type;
+
+ r_type = ELF32_R_TYPE (rel->r_info);
+ howto = arc_elf_calculate_howto_index(r_type);
+
+ if (arc_signed_reloc_type [howto->type] == 1)
+ {
+ check_overfl_pos = (long long)1 << (howto->bitsize-1);
+ check_overfl_neg = -check_overfl_pos;
+ if ((value >= check_overfl_pos) || (check_overfl_neg > value))
+ *overflow_detected = 1;
+ }
+ else
+ {
+ check_overfl_pos = (long long)1 << (howto->bitsize);
+ check_overfl_neg = 0;
+ if ((unsigned int) value >= check_overfl_pos)
+ *overflow_detected = 1;
+ }
+
+ if (*overflow_detected
+ && symbol_defined == TRUE)
+ {
+ (*_bfd_error_handler ) ("Error: Overflow detected in relocation value;");
+ if (howto->pc_relative)
+ (*_bfd_error_handler) ("Relocation value should be between %lld and %lld whereas it %d",
+ check_overfl_pos - 1, (signed long long) check_overfl_neg,
+ value);
+ else
+ (*_bfd_error_handler) ("Relocation value should be between %lld and %lld whereas it %ld",
+ check_overfl_pos - 1, (signed long long) check_overfl_neg,
+ (unsigned int) value);
+
+ bfd_set_error (bfd_error_bad_value);
+ *overflow_detected = 1;
+ return 0;
+ }
+ else
+ *overflow_detected = 0;
+
+ switch(r_type)
+ {
+ case R_ARC_B26:
+ /* Retrieve the offset from the instruction, if any */
+ /* Extract the last 24 bits from Position 0 to 23 in insn */
+
+ offset = insn & 0x00ffffff;
+ /* Fill in 2 bit to get the 26 bit Offset Value */
+ offset = offset << 2;
+
+
+ /* Extract the instruction opcode alone from 'insn' */
+ insn = insn & 0xff000000;
+ /* With the addend now being in the addend table, there is no
+ * need to use this
+ */
+ /* Ramana : No longer required since
+ * addends no longer exist in place
+ */
+ /* value += offset; */
+ insn |= ((value >> 2) & (~0xff000000));
+ break;
+
+ case R_ARC_B22_PCREL:
+ /* Retrieve the offset from the instruction, if any */
+ /* Extract the first 10 bits from Position 6 to 15 in insn */
+ offset = ((insn << 5) >> 12);
+
+ /* Fill in 2 bit to get the 22 bit Offset Value */
+ offset = offset << 2;
+
+ /* Extract the instruction opcode alone from 'insn' */
+ insn = insn & 0xf800007f;
+
+ /* Ramana: All addends exist in the relocation table. Ignore
+ * the in place addend
+ */
+ /*value += offset; */
+
+ insn |= ((value >> 2) << 7) & (~0xf800007f);
+
+ break;
+
+ case R_ARC_S21H_PCREL:
+ /* Retrieve the offset from the instruction, if any */
+ /* Extract the first 10 bits from Position 6 to 15 in insn */
+ offset = ((insn << 16) >> 22) << 10;
+
+ /* Extract the remaining 10 bits from Position 17 to 26 in insn */
+ offset |= ((insn << 5) >> 22);
+
+ /* Fill in 1 bit to get the 21 bit Offset Value */
+ offset = offset << 1;
+
+ /* Extract the instruction opcode alone from 'insn' */
+ insn = insn & 0xf801003f;
+
+
+
+ /* Ramana: All addends exist in the relocation table. Ignore
+ * the in place addend
+ */
+ /*value += offset; */
+
+
+ insn |= ((((value >> 1) & 0x3ff) << 17)
+ | (((value >> 1) & 0xffc00) >> 4));
+ break;
+ case R_ARC_S21W_PCREL:
+ /* Retrieve the offset from the instruction, if any */
+ /* Extract the first 10 bits from Position 6 to 15 in insn */
+ offset = ((insn << 16) >> 22) << 9;
+
+ /* Extract the remaining 9 bits from Position 18 to 26 in insn */
+ offset |= ((insn << 5) >> 23);
+
+ /* Fill in 2 bits to get the 25 bit Offset Value */
+ offset = offset << 2;
+
+ /* Extract the instruction opcode alone from 'insn' */
+ insn = insn & 0xf803003f;
+
+ /* Ramana: All addends exist in the relocation table. Ignore
+ * the in place addend
+ */
+
+ /*value += offset;*/
+
+
+ insn |= ((((value >> 2) & 0x1ff) << 18)
+ | (((value >> 2) & 0x7fe00) >> 3));
+ break;
+ case R_ARC_S25H_PCREL:
+ /* Retrieve the offset from the instruction, if any */
+ /* Extract the high 4 bits from Position 0 to 3 in insn */
+ offset = ((insn << 28) >> 28) << 10;
+
+ /* Extract the next 10 bits from Position 6 to 15 in insn */
+ offset |= ((insn << 16) >> 22);
+ offset = offset << 10;
+
+ /* Extract the remaining 10 bits from Position 17 to 26 in insn */
+ offset |= ((insn << 5) >> 22);
+
+ /* Fill in 1 bit to get the 25 bit Offset Value */
+ offset = offset << 1;
+
+ /* Extract the instruction opcode alone from 'insn' */
+ insn = insn & 0xf8010030;
+
+ /* Ramana: All addends exist in the relocation table. Ignore
+ * the in place addend
+ */
+
+ /* value += offset; */
+
+ insn |= ((((value >> 1) & 0x3ff) << 17)
+ | (((value >> 1) & 0xffc00) >> 4)
+ | (((value >> 1) & 0xf00000) >> 20));
+ break;
+ case R_ARC_PLT32:
+ BFD_DEBUG_PIC (fprintf(stderr,"plt for %x value=0x%x\n",insn,value));
+ /*
+ Relocations of the type R_ARC_PLT32 are for the BLcc
+ instructions. However the BL instruction takes a 25-bit relative
+ displacement while the BLcc instruction takes a 21-bit relative
+ displacement. We are using bit-17 to distinguish between these two
+ cases and handle them differently.
+ */
+
+ if(insn & 0x00020000) /* Non-conditional */
+ {
+ insn = insn & 0xf8030030;
+ insn |= (((value >> 2) & 0x780000) >> 19);
+ }
+ else /* Conditional */
+ {
+ insn = insn & 0xf803003f;
+ }
+
+ insn |= ((((value >> 2) & 0x1ff) << 18)
+ | (((value >> 2) & 0x7fe00) >> 3));
+ break;
+ case R_ARC_S25W_PCREL:
+
+ /* Retrieve the offset from the instruction, if any */
+ /* Extract the high 4 bits from Position 0 to 3 in insn */
+ offset = ((insn << 28) >> 28) << 10;
+
+ /* Extract the next 10 bits from Position 6 to 15 in insn */
+ offset |= ((insn << 16) >> 22);
+ offset = offset << 9;
+
+ /* Extract the remaining 9 bits from Position 18 to 26 in insn */
+ offset |= ((insn << 5) >> 23);
+
+ /* Fill in 2 bits to get the 25 bit Offset Value */
+ offset = offset << 2;
+ /* Extract the instruction opcode alone from 'insn' */
+ insn = insn & 0xf8030030;
+ /* Ramana: All addends exist in the relocation table. Ignore
+ * the in place addend
+ */
+
+ /* value += offset; */
+
+ insn |= ((((value >> 2) & 0x1ff) << 18)
+ | (((value >> 2) & 0x7fe00) >> 3)
+ | (((value >> 2) & 0x780000) >> 19));
+ break;
+ case R_ARC_S13_PCREL:
+ /* Retrieve the offset from the instruction, if any */
+ /* Extract the 11 bits from Position 0 to 10 in insn */
+ offset = (insn << 5) >> 21;
+
+ /* Fill in 2 bits to get the 13 bit Offset Value */
+ offset = offset << 2;
+
+ /* Extract the instruction opcode alone from 'insn' */
+ insn = (insn & 0xf800ffff);
+
+ /* Ramana: All addends exist in the relocation table. Ignore
+ * the in place addend
+ */
+
+ /* value += offset; */
+
+ insn |= ((value >> 2) & 0x7ff) << 16;
+ break;
+
+ case R_ARC_32:
+ case R_ARC_GOTPC:
+ case R_ARC_GOTOFF:
+ case R_ARC_GOTPC32:
+ case R_ARC_32_ME:
+ insn = value;
+
+ case R_ARC_8:
+ case R_ARC_16:
+ case R_ARC_24:
+ /* One would have to OR the value here since
+ insn would contain the bits read in correctly. */
+
+
+ insn |= value ;
+ break;
+
+ case R_ARC_SDA32_ME:
+ insn |= value;
+ break;
+
+ case R_ARC_SDA_LDST2:
+ value >>= 1;
+ case R_ARC_SDA_LDST1:
+ value >>= 1;
+ case R_ARC_SDA_LDST:
+ value &= 0x1ff;
+ insn |= ( ((value & 0xff) << 16) | ((value >> 8) << 15));
+ break;
+
+ case R_ARC_SDA16_LD:
+ /* FIXME: The 16-bit insns shd not come in as higher bits of a 32-bit word */
+ insn |= (value & 0x1ff) <<16;
+ break;
+
+ case R_ARC_SDA16_LD1:
+ /* FIXME: The 16-bit insns shd not come in as higher bits of a 32-bit word */
+ insn |= ((value >> 1) & 0x1ff ) <<16;
+ break;
+
+ case R_ARC_SDA16_LD2:
+ /* FIXME: The 16-bit insns shd not come in as higher bits of a 32-bit word */
+ insn |= ((value >> 2) & 0x1ff) <<16;
+ break;
+
+ default:
+ /* FIXME:: This should go away once the HOWTO Array
+ is used for this purpose.
+ */
+ fprintf(stderr, "Unsupported reloc used : %s (value = %d)\n", (arc_elf_calculate_howto_index(r_type))->name, value);
+ break;
+ }
+
+ return insn;
+}
+
+/* Function : elf_arc_check_relocs
+ * Brief : Check the relocation entries and take any special
+ * actions, depending on the relocation type if needed.
+ * Args : 1. abfd : The input bfd
+ * 2. info : link information
+ * 3. sec : section being relocated
+ * 4. relocs : the list of relocations.
+ * Returns : True/False as the return status.
+ */
+static bfd_boolean
+elf_arc_check_relocs (bfd *abfd,
+ struct bfd_link_info *info,
+ asection *sec,
+ const Elf_Internal_Rela *relocs)
+{
+ bfd *dynobj;
+ Elf_Internal_Shdr *symtab_hdr;
+ struct elf_link_hash_entry **sym_hashes;
+ bfd_vma *local_got_offsets;
+ const Elf_Internal_Rela *rel;
+ const Elf_Internal_Rela *rel_end;
+ asection *sgot;
+ asection *srelgot;
+ asection *sreloc;
+
+ if (info->relocatable)
+ return TRUE;
+
+ dynobj = elf_hash_table (info)->dynobj;
+ symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
+ sym_hashes = elf_sym_hashes (abfd);
+ local_got_offsets = elf_local_got_offsets (abfd);
+
+ sgot = NULL;
+ srelgot = NULL;
+ sreloc = NULL;
+
+ rel_end = relocs + sec->reloc_count;
+ for (rel = relocs; rel < rel_end; rel++)
+ {
+ unsigned long r_symndx;
+ struct elf_link_hash_entry *h;
+ BFD_DEBUG_PIC (fprintf(stderr,"Processing reloc #%d in %s\n",
+ rel-relocs,__PRETTY_FUNCTION__));
+
+ r_symndx = ELF32_R_SYM (rel->r_info);
+
+ if (r_symndx < symtab_hdr->sh_info)
+ h = NULL;
+ else
+ h = sym_hashes[r_symndx - symtab_hdr->sh_info];
+
+ /* Some relocs require a global offset table. */
+ if (dynobj == NULL)
+ {
+ switch (ELF32_R_TYPE (rel->r_info))
+ {
+ case R_ARC_GOTPC32:
+ case R_ARC_GOTOFF:
+ case R_ARC_GOTPC:
+ elf_hash_table (info)->dynobj = dynobj = abfd;
+ if (! _bfd_elf_create_got_section (dynobj, info))
+ return FALSE;
+ break;
+
+ default:
+ break;
+ }
+ }
+
+ switch (ELF32_R_TYPE (rel->r_info))
+ {
+ case R_ARC_GOTPC32:
+ /* This symbol requires a global offset table entry. */
+
+ if (sgot == NULL)
+ {
+ sgot = bfd_get_section_by_name (dynobj, ".got");
+ BFD_ASSERT (sgot != NULL);
+ }
+
+ if (srelgot == NULL
+ && (h != NULL || info->shared))
+ {
+ srelgot = bfd_get_section_by_name (dynobj, ".rela.got");
+ if (srelgot == NULL)
+ {
+ srelgot = bfd_make_section (dynobj, ".rela.got");
+ if (srelgot == NULL
+ || ! bfd_set_section_flags (dynobj, srelgot,
+ (SEC_ALLOC
+ | SEC_LOAD
+ | SEC_HAS_CONTENTS
+ | SEC_IN_MEMORY
+ | SEC_LINKER_CREATED
+ | SEC_READONLY))
+ || ! bfd_set_section_alignment (dynobj, srelgot, 2))
+ return FALSE;
+ }
+ }
+
+ if (h != NULL)
+ {
+ if (h->got.offset != (bfd_vma) -1)
+ {
+ BFD_DEBUG_PIC(fprintf(stderr, "got entry stab entry already done%d\n",r_symndx));
+
+ /* We have already allocated space in the .got. */
+ break;
+ }
+
+
+ h->got.offset = sgot->size;
+ BFD_DEBUG_PIC(fprintf(stderr, "got entry stab entry %d got offset=0x%x\n",r_symndx,
+ h->got.offset));
+
+ /* Make sure this symbol is output as a dynamic symbol. */
+ if (h->dynindx == -1)
+ {
+ if (! bfd_elf_link_record_dynamic_symbol (info, h))
+ return FALSE;
+ }
+
+ BFD_DEBUG_PIC(fprintf (stderr, "Got raw size increased\n"));
+ srelgot->size += sizeof (Elf32_External_Rela);
+ }
+ else
+ {
+ /* This is a global offset table entry for a local
+ symbol. */
+ if (local_got_offsets == NULL)
+ {
+ size_t size;
+ register unsigned int i;
+
+ size = symtab_hdr->sh_info * sizeof (bfd_vma);
+ local_got_offsets = (bfd_vma *) bfd_alloc (abfd, size);
+ if (local_got_offsets == NULL)
+ return FALSE;
+ elf_local_got_offsets (abfd) = local_got_offsets;
+ for (i = 0; i < symtab_hdr->sh_info; i++)
+ local_got_offsets[i] = (bfd_vma) -1;
+ }
+ if (local_got_offsets[r_symndx] != (bfd_vma) -1)
+ {
+ BFD_DEBUG_PIC(fprintf(stderr, "got entry stab entry already done%d\n",r_symndx));
+
+ /* We have already allocated space in the .got. */
+ break;
+ }
+
+ BFD_DEBUG_PIC(fprintf(stderr, "got entry stab entry %d\n",r_symndx));
+
+
+ local_got_offsets[r_symndx] = sgot->size;
+
+ if (info->shared)
+ {
+ /* If we are generating a shared object, we need to
+ output a R_ARC_RELATIVE reloc so that the dynamic
+ linker can adjust this GOT entry. */
+ srelgot->size += sizeof (Elf32_External_Rela);
+ }
+ }
+
+ BFD_DEBUG_PIC(fprintf (stderr, "Got raw size increased\n"));
+
+ sgot->size += 4;
+
+ break;
+
+ case R_ARC_PLT32:
+ /* This symbol requires a procedure linkage table entry. We
+ actually build the entry in adjust_dynamic_symbol,
+ because this might be a case of linking PIC code which is
+ never referenced by a dynamic object, in which case we
+ don't need to generate a procedure linkage table entry
+ after all. */
+
+ /* If this is a local symbol, we resolve it directly without
+ creating a procedure linkage table entry. */
+ if (h == NULL)
+ continue;
+
+ h->needs_plt = 1;
+
+ break;
+
+ case R_ARC_32:
+ case R_ARC_32_ME:
+ case R_ARC_PC32:
+ /* If we are creating a shared library, and this is a reloc
+ against a global symbol, or a non PC relative reloc
+ against a local symbol, then we need to copy the reloc
+ into the shared library. However, if we are linking with
+ -Bsymbolic, we do not need to copy a reloc against a
+ global symbol which is defined in an object we are
+ including in the link (i.e., DEF_REGULAR is set). At
+ this point we have not seen all the input files, so it is
+ possible that DEF_REGULAR is not set now but will be set
+ later (it is never cleared). We account for that
+ possibility below by storing information in the
+ pcrel_relocs_copied field of the hash table entry. */
+ if (info->shared
+ && (ELF32_R_TYPE (rel->r_info) != R_ARC_PC32
+ || (h != NULL
+ && (!info->symbolic || !h->def_regular))))
+ {
+ /* When creating a shared object, we must copy these
+ reloc types into the output file. We create a reloc
+ section in dynobj and make room for this reloc. */
+ if (sreloc == NULL)
+ {
+ const char *name;
+
+ name = (bfd_elf_string_from_elf_section
+ (abfd,
+ elf_elfheader (abfd)->e_shstrndx,
+ elf_section_data (sec)->rel_hdr.sh_name));
+ if (name == NULL)
+ return FALSE;
+
+ BFD_ASSERT (strncmp (name, ".rela", 5) == 0
+ && strcmp (bfd_get_section_name (abfd, sec),
+ name + 5) == 0);
+
+ sreloc = bfd_get_section_by_name (dynobj, name);
+ if (sreloc == NULL)
+ {
+ flagword flags;
+
+ sreloc = bfd_make_section (dynobj, name);
+ flags = (SEC_HAS_CONTENTS | SEC_READONLY
+ | SEC_IN_MEMORY | SEC_LINKER_CREATED);
+ if ((sec->flags & SEC_ALLOC) != 0)
+ flags |= SEC_ALLOC | SEC_LOAD;
+ if (sreloc == NULL
+ || ! bfd_set_section_flags (dynobj, sreloc, flags)
+ || ! bfd_set_section_alignment (dynobj, sreloc, 2))
+ return FALSE;
+ }
+ }
+
+ sreloc->size += sizeof (Elf32_External_Rela);
+
+ /* If we are linking with -Bsymbolic, and this is a
+ global symbol, we count the number of PC relative
+ relocations we have entered for this symbol, so that
+ we can discard them again if the symbol is later
+ defined by a regular object. Note that this function
+ is only called if we are using an elf_ARC linker
+ hash table, which means that h is really a pointer to
+ an elf_ARC_link_hash_entry. */
+ if (h != NULL && info->symbolic
+ && ELF32_R_TYPE (rel->r_info) == R_ARC_PC32)
+ {
+ struct elf_ARC_link_hash_entry *eh;
+ struct elf_ARC_pcrel_relocs_copied *p;
+
+ eh = (struct elf_ARC_link_hash_entry *) h;
+
+ for (p = eh->pcrel_relocs_copied; p != NULL; p = p->next)
+ if (p->section == sreloc)
+ break;
+
+ if (p == NULL)
+ {
+ p = ((struct elf_ARC_pcrel_relocs_copied *)
+ bfd_alloc (dynobj, sizeof *p));
+ if (p == NULL)
+ return FALSE;
+ p->next = eh->pcrel_relocs_copied;
+ eh->pcrel_relocs_copied = p;
+ p->section = sreloc;
+ p->count = 0;
+ }
+
+ ++p->count;
+ }
+ }
+
+ break;
+
+ default:
+ break;
+ }
+
+ }
+
+ return TRUE;
+}
+
+
+/* Relocate an arc ELF section. */
+/* Function : elf_arc_relocate_section
+ * Brief : Relocate an arc section, by handling all the relocations
+ * appearing in that section.
+ * Args : output_bfd : The bfd being written to.
+ * info : Link information.
+ * input_bfd : The input bfd.
+ * input_section : The section being relocated.
+ * contents : contents of the section being relocated.
+ * relocs : List of relocations in the section.
+ * local_syms : is a pointer to the swapped in local symbols.
+ * local_section : is an array giving the section in the input file
+ * corresponding to the st_shndx field of each
+ * local symbol.
+ * Returns :
+ */
+static bfd_boolean
+elf_arc_relocate_section (bfd *output_bfd,
+ struct bfd_link_info *info,
+ bfd *input_bfd,
+ asection *input_section,
+ bfd_byte * contents,
+ Elf_Internal_Rela *relocs,
+ Elf_Internal_Sym *local_syms,
+ asection **local_sections)
+{
+ bfd *dynobj;
+ Elf_Internal_Shdr *symtab_hdr;
+ struct elf_link_hash_entry **sym_hashes;
+ bfd_vma *local_got_offsets;
+ asection *sgot;
+ asection *splt;
+ asection *sreloc;
+ Elf_Internal_Rela *rel;
+ Elf_Internal_Rela *relend;
+ short overflow_detected=0;
+
+ dynobj = elf_hash_table (info)->dynobj;
+ symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
+ sym_hashes = elf_sym_hashes (input_bfd);
+ local_got_offsets = elf_local_got_offsets (input_bfd);
+
+ sgot = NULL;
+ splt = NULL;
+ sreloc = NULL;
+
+ rel = relocs;
+ relend = relocs + input_section->reloc_count;
+ for (; rel < relend; rel++)
+ {
+ enum elf_arc_reloc_type r_type;
+ reloc_howto_type *howto;
+ unsigned long r_symndx;
+ struct elf_link_hash_entry *h;
+ Elf_Internal_Sym *sym;
+ asection *sec;
+ bfd_vma relocation;
+ bfd_reloc_status_type r;
+ bfd_boolean symbol_defined = TRUE;
+
+ /* Distance of the relocation slot in the insn .This value is used for
+ handling relative relocations. */
+ long offset_in_insn = 0;
+
+ /* The insn bytes */
+ unsigned long insn;
+
+
+ r_type = ELF32_R_TYPE (rel->r_info);
+
+ if (r_type >= (int) R_ARC_max)
+ {
+ bfd_set_error (bfd_error_bad_value);
+ return FALSE;
+ }
+ howto = arc_elf_calculate_howto_index(r_type);
+
+ BFD_DEBUG_PIC (fprintf(stderr,"Reloc type=%s in %s\n",
+ howto->name,
+ __PRETTY_FUNCTION__));
+
+ r_symndx = ELF32_R_SYM (rel->r_info);
+
+
+ if (info->relocatable)
+ {
+ /* This is a relocateable link. We don't have to change
+ anything, unless the reloc is against a section symbol,
+ in which case we have to adjust according to where the
+ section symbol winds up in the output section. */
+
+ /* Checks if this is a local symbol
+ * and thus the reloc might (will??) be against a section symbol.
+ */
+ if (r_symndx < symtab_hdr->sh_info)
+ {
+ sym = local_syms + r_symndx;
+ if (ELF_ST_TYPE (sym->st_info) == STT_SECTION)
+ {
+ sec = local_sections[r_symndx];
+
+ /* for RELA relocs.Just adjust the addend
+ value in the relocation entry. */
+ rel->r_addend += sec->output_offset + sym->st_value;
+
+ BFD_DEBUG_PIC(fprintf (stderr, "local symbols reloc \
+(section=%d %s) seen in %s\n", \
+ r_symndx,\
+ local_sections[r_symndx]->name, \
+ __PRETTY_FUNCTION__));
+ }
+ }
+
+ continue;
+ }
+
+ /* This is a final link. */
+ h = NULL;
+ sym = NULL;
+ sec = NULL;
+
+ if (r_symndx < symtab_hdr->sh_info)
+ {
+ /* This is a local symbol */
+ sym = local_syms + r_symndx;
+ sec = local_sections[r_symndx];
+ relocation = (sec->output_section->vma
+ + sec->output_offset
+ + sym->st_value);
+
+ /* Mergeable section handling */
+ if ((sec->flags & SEC_MERGE)
+ && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
+ {
+ asection *msec;
+ msec = sec;
+ rel->r_addend = _bfd_elf_rel_local_sym (output_bfd, sym,
+ &msec, rel->r_addend);
+ rel->r_addend -= relocation;
+ rel->r_addend += msec->output_section->vma + msec->output_offset;
+ }
+
+ relocation += rel->r_addend;
+ }
+ else
+ {
+ /* Global symbols */
+
+ /* get the symbol's entry in the symtab */
+ h = sym_hashes[r_symndx - symtab_hdr->sh_info];
+
+ while (h->root.type == bfd_link_hash_indirect
+ || h->root.type == bfd_link_hash_warning)
+ h = (struct elf_link_hash_entry *) h->root.u.i.link;
+
+ /* if we have encountered a definition for this symbol */
+ if (h->root.type == bfd_link_hash_defined
+ || h->root.type == bfd_link_hash_defweak)
+ {
+ sec = h->root.u.def.section;
+ if (r_type == R_ARC_GOTPC
+ || (r_type == R_ARC_PLT32
+ && h->plt.offset != (bfd_vma) -1)
+ || (r_type == R_ARC_GOTPC32
+ && elf_hash_table (info)->dynamic_sections_created
+ && (! info->shared
+ || (! info->symbolic && h->dynindx != -1)
+ || !h->def_regular))
+ || (info->shared
+ && ((! info->symbolic && h->dynindx != -1)
+ || !h->def_regular)
+ && (r_type == R_ARC_32
+ || r_type == R_ARC_PC32)
+ && (input_section->flags & SEC_ALLOC) != 0))
+ {
+ /* In these cases, we don't need the relocation
+ value. We check specially because in some
+ obscure cases sec->output_section will be NULL. */
+ relocation = 0;
+ }
+ else if (sec->output_section == NULL)
+ {
+ (*_bfd_error_handler)
+ ("%s: warning: unresolvable relocation against symbol `%s' from %s section",
+ bfd_get_filename (input_bfd), h->root.root.string,
+ bfd_get_section_name (input_bfd, input_section));
+ relocation = 0;
+ }
+ else if (0 && r_type == R_ARC_SDA16_LD2) /* FIXME: delete this piece of code */
+ {
+ relocation = (h->root.u.def.value
+ + sec->output_offset);
+ /* add the addend since the arc has RELA relocations */
+ relocation += rel->r_addend;
+ }
+ else
+ {
+ relocation = (h->root.u.def.value
+ + sec->output_section->vma
+ + sec->output_offset);
+ /* add the addend since the arc has RELA relocations */
+ relocation += rel->r_addend;
+ }
+ }
+ else if (h->root.type == bfd_link_hash_undefweak)
+ relocation = 0;
+ else if (info->shared && !info->symbolic)
+ relocation = 0;
+ else
+ {
+ if (! ((*info->callbacks->undefined_symbol)
+ (info, h->root.root.string,
+ input_bfd, input_section, rel->r_offset, TRUE)))
+ return FALSE;
+ symbol_defined = FALSE;
+ relocation = 0;
+ }
+ }
+ BFD_DEBUG_PIC ( fprintf (stderr, "Relocation = %d (%x)\n", relocation, relocation));
+
+
+ switch (r_type)
+ {
+ case R_ARC_GOTPC32:
+ /* Relocation is to the entry for this symbol in the global
+ offset table. */
+ if (sgot == NULL)
+ {
+ sgot = bfd_get_section_by_name (dynobj, ".got");
+ BFD_DEBUG_PIC (fprintf (stderr, "made got\n"));
+ BFD_ASSERT (sgot != NULL);
+ }
+
+ if (h != NULL)
+ {
+ bfd_vma off;
+
+ off = h->got.offset;
+ BFD_ASSERT (off != (bfd_vma) -1);
+
+ if (! elf_hash_table (info)->dynamic_sections_created
+ || (info->shared
+ && (info->symbolic || h->dynindx == -1)
+ && h->def_regular))
+ {
+ /* This is actually a static link, or it is a
+ -Bsymbolic link and the symbol is defined
+ locally, or the symbol was forced to be local
+ because of a version file. We must initialize
+ this entry in the global offset table. Since the
+ offset must always be a multiple of 4, we use the
+ least significant bit to record whether we have
+ initialized it already.
+
+ When doing a dynamic link, we create a .rela.got
+ relocation entry to initialize the value. This
+ is done in the finish_dynamic_symbol routine. */
+ if ((off & 1) != 0)
+ off &= ~1;
+ else
+ {
+ bfd_put_32 (output_bfd, relocation,
+ sgot->contents + off);
+ h->got.offset |= 1;
+ }
+ }
+
+ relocation = sgot->output_section->vma + sgot->output_offset + off;
+ BFD_DEBUG_PIC(fprintf(stderr, "OFFSET=0x%x output_offset=%x (1)\n", off, sgot->output_offset));
+ }
+ else
+ {
+ bfd_vma off;
+
+ BFD_ASSERT (local_got_offsets != NULL
+ && local_got_offsets[r_symndx] != (bfd_vma) -1);
+
+ off = local_got_offsets[r_symndx];
+
+ /* The offset must always be a multiple of 4. We use
+ the least significant bit to record whether we have
+ already generated the necessary reloc. */
+ if ((off & 1) != 0)
+ off &= ~1;
+ else
+ {
+ bfd_put_32 (output_bfd, relocation,
+ sgot->contents + off);
+
+ if (info->shared)
+ {
+ asection *srelgot;
+ Elf_Internal_Rela outrel;
+ bfd_byte *loc;
+
+ srelgot = bfd_get_section_by_name (dynobj, ".rela.got");
+ BFD_ASSERT (srelgot != NULL);
+
+ outrel.r_offset = (sgot->output_section->vma
+ + sgot->output_offset
+ + off);
+ /* RELA relocs */
+ outrel.r_addend = 0;
+
+ outrel.r_info = ELF32_R_INFO (0, R_ARC_RELATIVE);
+ loc = srelgot->contents;
+ loc += srelgot->reloc_count++ * sizeof (Elf32_External_Rela); /* relA */
+ bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+ }
+
+ local_got_offsets[r_symndx] |= 1;
+ }
+
+ relocation = sgot->output_section->vma + sgot->output_offset + off;
+ BFD_DEBUG_PIC(fprintf(stderr, "OFFSET=0x%x (2)\n", off));
+ }
+
+ BFD_DEBUG_PIC(fprintf(stderr, "RELOCATION =%x\n",relocation));
+ /* the data in GOT32 relocs is 4 bytes into the insn */
+ offset_in_insn = 4;
+
+ break;
+
+ case R_ARC_GOTOFF:
+ /* Relocation is relative to the start of the global offset
+ table. */
+
+ if (sgot == NULL)
+ {
+ sgot = bfd_get_section_by_name (dynobj, ".got");
+ BFD_ASSERT (sgot != NULL);
+ }
+
+ /* Note that sgot->output_offset is not involved in this
+ calculation. We always want the start of .got. If we
+ defined _GLOBAL_OFFSET_TABLE in a different way, as is
+ permitted by the ABI, we might have to change this
+ calculation. */
+ BFD_DEBUG_PIC(fprintf(stderr,"GOTOFF relocation = %x. Subtracting %x\n",relocation, sgot->output_section->vma));
+ relocation -= sgot->output_section->vma;
+
+ break;
+
+ case R_ARC_GOTPC:
+ /* Use global offset table as symbol value. */
+
+ if (sgot == NULL)
+ {
+ sgot = bfd_get_section_by_name (dynobj, ".got");
+ BFD_ASSERT (sgot != NULL);
+ }
+
+ relocation = sgot->output_section->vma;
+
+ offset_in_insn = 4;
+ break;
+
+ case R_ARC_PLT32:
+ /* Relocation is to the entry for this symbol in the
+ procedure linkage table. */
+
+ /* Resolve a PLT32 reloc again a local symbol directly,
+ without using the procedure linkage table. */
+ if (h == NULL)
+ break;
+
+ if (h->plt.offset == (bfd_vma) -1)
+ {
+ /* We didn't make a PLT entry for this symbol. This
+ happens when statically linking PIC code, or when
+ using -Bsymbolic. */
+ break;
+ }
+
+ if (splt == NULL)
+ {
+ splt = bfd_get_section_by_name (dynobj, ".plt");
+ BFD_ASSERT (splt != NULL);
+ }
+
+ relocation = (splt->output_section->vma
+ + splt->output_offset
+ + h->plt.offset);
+
+ break;
+
+ case R_ARC_32:
+ case R_ARC_32_ME:
+ case R_ARC_PC32:
+ if (info->shared
+ && (r_type != R_ARC_PC32
+ || (h != NULL
+ && h->dynindx != -1
+ && (!info->symbolic || !h->def_regular))))
+ {
+ Elf_Internal_Rela outrel;
+ bfd_boolean skip, relocate;
+ bfd_byte *loc;
+
+ /* When generating a shared object, these relocations
+ are copied into the output file to be resolved at run
+ time. */
+
+ if (sreloc == NULL)
+ {
+ const char *name;
+
+ name = (bfd_elf_string_from_elf_section
+ (input_bfd,
+ elf_elfheader (input_bfd)->e_shstrndx,
+ elf_section_data (input_section)->rel_hdr.sh_name));
+ if (name == NULL)
+ return FALSE;
+
+ BFD_ASSERT (strncmp (name, ".rela", 5) == 0
+ && strcmp (bfd_get_section_name (input_bfd,
+ input_section),
+ name + 5) == 0);
+
+ sreloc = bfd_get_section_by_name (dynobj, name);
+
+ BFD_ASSERT (sreloc != NULL);
+ }
+
+ skip = FALSE;
+
+ outrel.r_offset = _bfd_elf_section_offset (output_bfd,
+ info,
+ input_section,
+ rel->r_offset);
+ if (outrel.r_offset == (bfd_vma) -1)
+ skip = TRUE;
+
+ outrel.r_addend = 0;
+ outrel.r_offset += (input_section->output_section->vma
+ + input_section->output_offset);
+
+ if (skip)
+ {
+ memset (&outrel, 0, sizeof outrel);
+ relocate = FALSE;
+ }
+ else if (r_type == R_ARC_PC32)
+ {
+ BFD_ASSERT (h != NULL && h->dynindx != -1);
+ if ((input_section->flags & SEC_ALLOC) != 0)
+ relocate = FALSE;
+ else
+ relocate = TRUE;
+ outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARC_PC32);
+ }
+ else
+ {
+ /* h->dynindx may be -1 if this symbol was marked to
+ become local. */
+ if (h == NULL
+ || ((info->symbolic || h->dynindx == -1)
+ && h->def_regular))
+ {
+ relocate = TRUE;
+ outrel.r_addend = 0;
+ outrel.r_info = ELF32_R_INFO (0, R_ARC_RELATIVE);
+ }
+ else
+ {
+ BFD_ASSERT (h->dynindx != -1);
+ if ((input_section->flags & SEC_ALLOC) != 0)
+ relocate = FALSE;
+ else
+ relocate = TRUE;
+ outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARC_32);
+ }
+ }
+
+ BFD_ASSERT(sreloc->contents != 0);
+
+ loc = sreloc->contents;
+ loc += sreloc->reloc_count++ * sizeof (Elf32_External_Rela); /* relA */
+
+ bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+
+ /* If this reloc is against an external symbol, we do
+ not want to fiddle with the addend. Otherwise, we
+ need to include the symbol value so that it becomes
+ an addend for the dynamic reloc. */
+ if (! relocate)
+ continue;
+ }
+
+ /* PLT32 has to be w.r.t the instruction's start */
+ offset_in_insn = 0;
+ break;
+
+ case R_ARC_B22_PCREL:
+ /* 'offset_in_insn' in case of the A4 is from the instruction in
+ the delay slot of the branch instruction hence the -4 offset. */
+ offset_in_insn = -4;
+ break;
+
+ case R_ARC_SDA32_ME:
+
+ case R_ARC_SDA_LDST:
+ case R_ARC_SDA_LDST1:
+ case R_ARC_SDA_LDST2:
+
+ case R_ARC_SDA16_LD:
+ case R_ARC_SDA16_LD1:
+ case R_ARC_SDA16_LD2:
+ {
+ /* Get the base of .sdata section */
+ struct elf_link_hash_entry *h;
+
+ h = elf_link_hash_lookup (elf_hash_table (info), "__SDATA_BEGIN__",
+ FALSE, FALSE, TRUE);
+
+ if (h->root.type == bfd_link_hash_undefined)
+ {
+ (*_bfd_error_handler)("Error: Linker symbol __SDATA_BEGIN__ not found");
+ bfd_set_error (bfd_error_bad_value);
+ return FALSE;
+ }
+
+ /* Subtract the address of __SDATA_BEGIN__ from the relocation value */
+ /// fprintf (stderr, "relocation BEFORE = 0x%x SDATA_BEGIN = 0x%x\n", relocation, h->root.u.def.value);
+ relocation -= (h->root.u.def.value + h->root.u.def.section->output_section->vma);
+ // fprintf (stderr, "relocation AFTER = 0x%x SDATA_BEGIN = 0x%x\n", relocation, h->root.u.def.value);
+ break;
+ }
+ default:
+ /* FIXME: Putting in a random dummy relocation value for the time being */
+ // fprintf (stderr, "In %s, relocation = 0x%x, r_type = %d\n", __PRETTY_FUNCTION__, relocation, r_type);
+ break;
+ }
+
+
+ /* get the insn bytes here */
+ if(elf_elfheader(input_bfd)->e_machine == EM_ARC)
+ insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
+ else
+ if(input_section && (input_section->flags & SEC_CODE))
+ insn = bfd_get_32_me (input_bfd, contents + rel->r_offset);
+ else
+ insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
+
+ BFD_DEBUG_PIC(fprintf(stderr, "relocation before the pc relative stuff @offset 0x%x= %d[0x%x]\n",
+ rel->r_offset,relocation, relocation));
+
+ BFD_DEBUG_PIC(fprintf(stderr,"addend = 0x%x\n",rel->r_addend));
+
+ /* For branches we need to find the offset from pcl rounded down to 4 byte boundary.Hence the (& ~3) */
+ if (howto->pc_relative || r_type==R_ARC_PLT32 || r_type==R_ARC_GOTPC || r_type==R_ARC_GOTPC32)
+ {
+ relocation -= (((input_section->output_section->vma + input_section->output_offset + rel->r_offset) & ~3) - offset_in_insn );
+ }
+#if 0
+ else if (r_type==R_ARC_GOTPC32)
+ {
+ relocation -= (input_section->output_section->vma +
+ input_section->output_offset + rel->r_offset
+ - offset_in_insn );
+ }
+#endif
+
+
+
+ BFD_DEBUG_PIC(fprintf(stderr, "relocation AFTER the pc relative handling = %d[0x%x]\n", relocation, relocation));
+
+ /* What does the modified insn look like */
+ insn = arc_plugin_one_reloc (insn, rel, relocation,
+ &overflow_detected, symbol_defined);
+
+ if (overflow_detected)
+ {
+ if(h)
+ (*_bfd_error_handler) ("Global symbol: \"%s\".", h->root.root.string);
+ else
+ (*_bfd_error_handler) ("Local symbol: \"%s\".", local_sections[r_symndx]->name);
+ (*_bfd_error_handler) ("\nRelocation type is:%s \nFileName:%s \
+ \nSection Name:%s\
+ \nOffset in Section:%ld", howto->name, bfd_get_filename (input_bfd),
+ bfd_get_section_name (input_bfd, input_section),
+ rel->r_offset);
+
+ return FALSE;
+ }
+
+ BFD_DEBUG_PIC (fprintf (stderr, "Relocation = %d [0x%x]\n", relocation, relocation));
+
+ /* now write back into the section, with middle endian encoding
+ only for executable section */
+ if(elf_elfheader(input_bfd)->e_machine == EM_ARC)
+ bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
+ else
+ if (input_section && (input_section->flags & SEC_CODE))
+ bfd_put_32_me (input_bfd, insn, contents + rel->r_offset);
+ else
+ bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
+
+ r = bfd_reloc_ok;
+
+
+ if (r != bfd_reloc_ok)
+ {
+ switch (r)
+ {
+ default:
+ case bfd_reloc_outofrange:
+ abort ();
+ case bfd_reloc_overflow:
+ {
+ const char *name;
+
+ if (h != NULL)
+ name = h->root.root.string;
+ else
+ {
+ name = bfd_elf_string_from_elf_section (input_bfd,
+ symtab_hdr->sh_link,
+ sym->st_name);
+ if (name == NULL)
+ return FALSE;
+ if (*name == '\0')
+ name = bfd_section_name (input_bfd, sec);
+ }
+ if (! ((*info->callbacks->reloc_overflow)
+ (info, (h ? &h->root : NULL), name, howto->name,
+ (bfd_vma) 0, input_bfd, input_section, rel->r_offset)))
+ return FALSE;
+ }
+ break;
+ }
+ }
+
+ }
+
+ return TRUE;
+}
+
+
+/* Function : elf_arc_finish_dynamic_symbol
+ * Brief : Finish up dynamic symbol handling. We set the
+ * contents of various dynamic sections here.
+ * Args : output_bfd :
+ * info :
+ * h :
+ * sym :
+ * Returns : True/False as the return status.
+ */
+static bfd_boolean
+elf_arc_finish_dynamic_symbol (bfd *output_bfd,
+ struct bfd_link_info *info,
+ struct elf_link_hash_entry *h,
+ Elf_Internal_Sym *sym)
+{
+ bfd *dynobj;
+
+ dynobj = elf_hash_table (info)->dynobj;
+
+ if (h->plt.offset != (bfd_vma) -1)
+ {
+ asection *splt;
+ asection *sgot;
+ asection *srel;
+ bfd_vma plt_index;
+ bfd_vma got_offset;
+ Elf_Internal_Rela rel;
+ bfd_byte *loc;
+
+ /* This symbol has an entry in the procedure linkage table. Set
+ it up. */
+
+ BFD_ASSERT (h->dynindx != -1);
+
+ splt = bfd_get_section_by_name (dynobj, ".plt");
+ sgot = bfd_get_section_by_name (dynobj, ".got.plt");
+ srel = bfd_get_section_by_name (dynobj, ".rela.plt");
+ BFD_ASSERT (splt != NULL && sgot != NULL && srel != NULL);
+
+ /* Get the index in the procedure linkage table which
+ corresponds to this symbol. This is the index of this symbol
+ in all the symbols for which we are making plt entries. The
+ first TWO entries in the procedure linkage table are reserved. */
+ plt_index = h->plt.offset / PLT_ENTRY_SIZE - 2;
+
+ /* Get the offset into the .got table of the entry that
+ corresponds to this function. Each .got entry is 4 bytes.
+ The first three are reserved. */
+ got_offset = (plt_index + 3) * 4;
+
+ /* Fill in the entry in the procedure linkage table. */
+ if (! info->shared)
+ {
+ memcpy (splt->contents + h->plt.offset, elf_arc_abs_pltn_entry,
+ PLT_ENTRY_SIZE);
+
+ /* fill in the limm in the plt entry to make it jump through its corresponding *(gotentry) */
+ bfd_put_32_me (output_bfd,
+ (sgot-> output_section->vma + sgot->output_offset + got_offset)
+ -(splt->output_section->vma + splt->output_offset + h->plt.offset),
+ splt->contents + h->plt.offset + 4);
+
+ }
+ else
+ {
+ memcpy (splt->contents + h->plt.offset, elf_arc_pic_pltn_entry,
+ PLT_ENTRY_SIZE);
+
+ /* fill in the limm in the plt entry to make it jump through its corresponding *(gotentry) */
+ bfd_put_32_me (output_bfd,
+ (sgot-> output_section->vma + sgot->output_offset + got_offset)
+ -(splt->output_section->vma + splt->output_offset + h->plt.offset),
+ splt->contents + h->plt.offset + 4);
+
+ }
+
+
+ /* Fill in the entry in the global offset table. */
+ bfd_put_32 (output_bfd,
+ (splt->output_section->vma
+ + splt->output_offset),
+ sgot->contents + got_offset);
+
+ /* Fill in the entry in the .rela.plt section. */
+ rel.r_offset = (sgot->output_section->vma
+ + sgot->output_offset
+ + got_offset);
+ /* RELA relocs */
+ rel.r_addend = 0;
+ rel.r_info = ELF32_R_INFO (h->dynindx, R_ARC_JMP_SLOT);
+
+ loc = srel->contents;
+ loc += plt_index * sizeof (Elf32_External_Rela); /* relA */
+
+ bfd_elf32_swap_reloca_out (output_bfd, &rel, loc);
+
+ if (!h->def_regular)
+ {
+ /* Mark the symbol as undefined, rather than as defined in
+ the .plt section. Leave the value alone. */
+ sym->st_shndx = SHN_UNDEF;
+ }
+
+ }
+
+ if (h->got.offset != (bfd_vma) -1)
+ {
+ asection *sgot;
+ asection *srel;
+ Elf_Internal_Rela rel;
+ bfd_byte *loc;
+
+ /* This symbol has an entry in the global offset table. Set it
+ up. */
+
+ sgot = bfd_get_section_by_name (dynobj, ".got");
+ srel = bfd_get_section_by_name (dynobj, ".rela.got");
+ BFD_ASSERT (sgot != NULL && srel != NULL);
+
+ rel.r_offset = (sgot->output_section->vma
+ + sgot->output_offset
+ + (h->got.offset &~ 1));
+
+ /* If this is a -Bsymbolic link, and the symbol is defined
+ locally, we just want to emit a RELATIVE reloc. Likewise if
+ the symbol was forced to be local because of a version file.
+ The entry in the global offset table will already have been
+ initialized in the relocate_section function. */
+ if (info->shared
+ && (info->symbolic || h->dynindx == -1)
+ && h->def_regular)
+ {
+ rel.r_addend = 0;
+ rel.r_info = ELF32_R_INFO (0, R_ARC_RELATIVE);
+ }
+ else
+ {
+ bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + h->got.offset);
+ /* RELA relocs */
+ rel.r_addend = 0;
+ rel.r_info = ELF32_R_INFO (h->dynindx, R_ARC_GLOB_DAT);
+ }
+
+ loc = srel->contents;
+ loc += srel->reloc_count++ * sizeof (Elf32_External_Rela);/* relA */
+
+ bfd_elf32_swap_reloca_out (output_bfd, &rel, loc);
+ }
+
+ if (h->needs_copy)
+ {
+ asection *s;
+ Elf_Internal_Rela rel;
+ bfd_byte *loc;
+
+ /* This symbol needs a copy reloc. Set it up. */
+
+ BFD_ASSERT (h->dynindx != -1
+ && (h->root.type == bfd_link_hash_defined
+ || h->root.type == bfd_link_hash_defweak));
+
+ s = bfd_get_section_by_name (h->root.u.def.section->owner,
+ ".rela.bss");
+ BFD_ASSERT (s != NULL);
+
+ rel.r_addend = 0;
+ rel.r_offset = (h->root.u.def.value
+ + h->root.u.def.section->output_section->vma
+ + h->root.u.def.section->output_offset);
+ rel.r_info = ELF32_R_INFO (h->dynindx, R_ARC_COPY);
+
+ loc = s->contents;
+ loc += s->reloc_count++ * sizeof (Elf32_External_Rela); /* relA */
+
+ bfd_elf32_swap_reloca_out (output_bfd, &rel, loc);
+ }
+
+ /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. */
+ if (strcmp (h->root.root.string, "_DYNAMIC") == 0
+ || strcmp (h->root.root.string, "__DYNAMIC") == 0
+ || strcmp (h->root.root.string, "_GLOBAL_OFFSET_TABLE_") == 0)
+ sym->st_shndx = SHN_ABS;
+
+ return TRUE;
+}
+
+
+/* Function : elf_arc_finish_dynamic_sections
+ * Brief : Finish up the dynamic sections handling.
+ * Args : output_bfd :
+ * info :
+ * h :
+ * sym :
+ * Returns : True/False as the return status.
+ */
+static bfd_boolean
+elf_arc_finish_dynamic_sections (bfd *output_bfd,struct bfd_link_info *info)
+{
+ bfd *dynobj;
+ asection *sgot;
+ asection *sdyn;
+ asection *sec_ptr;
+ char * oldname;
+
+ dynobj = elf_hash_table (info)->dynobj;
+
+ sgot = bfd_get_section_by_name (dynobj, ".got.plt");
+ BFD_ASSERT (sgot != NULL);
+ sdyn = bfd_get_section_by_name (dynobj, ".dynamic");
+
+ if (elf_hash_table (info)->dynamic_sections_created)
+ {
+ asection *splt;
+ Elf32_External_Dyn *dyncon, *dynconend;
+
+ splt = bfd_get_section_by_name (dynobj, ".plt");
+ BFD_ASSERT (splt != NULL && sdyn != NULL);
+
+ dyncon = (Elf32_External_Dyn *) sdyn->contents;
+ dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
+ for (; dyncon < dynconend; dyncon++)
+ {
+ Elf_Internal_Dyn dyn;
+ const char *name;
+ asection *s;
+
+ bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
+
+ switch (dyn.d_tag)
+ {
+ default:
+ break;
+
+ case DT_INIT:
+ oldname = INIT_SYM_STRING;
+ name = init_str;
+ goto get_sym;
+
+ case DT_FINI:
+ oldname = FINI_SYM_STRING;
+ name = fini_str;
+ goto get_sym;
+
+ get_sym:
+ {
+ struct elf_link_hash_entry *h;
+
+ h = elf_link_hash_lookup (elf_hash_table (info), name,
+ FALSE, FALSE, TRUE);
+ if (h != NULL
+ && (h->root.type == bfd_link_hash_defined
+ || h->root.type == bfd_link_hash_defweak))
+ {
+ dyn.d_un.d_val = h->root.u.def.value;
+ sec_ptr = h->root.u.def.section;
+ if (sec_ptr->output_section != NULL)
+ dyn.d_un.d_val += (sec_ptr->output_section->vma
+ + sec_ptr->output_offset);
+ else
+ {
+ /* The symbol is imported from another shared
+ library and does not apply to this one. */
+ dyn.d_un.d_val = 0;
+ }
+
+ bfd_elf32_swap_dyn_out (dynobj, &dyn, dyncon);
+ }
+ else
+ {
+ (*_bfd_error_handler)
+ ("warning: specified init/fini symbol %s not found.Defaulting to address of symbol %s",
+ name, oldname);
+
+ /* restore the default name */
+ name = oldname;
+
+ h = elf_link_hash_lookup (elf_hash_table (info), name,
+ FALSE, FALSE, TRUE);
+ if (h != NULL
+ && (h->root.type == bfd_link_hash_defined
+ || h->root.type == bfd_link_hash_defweak))
+ {
+ dyn.d_un.d_val = h->root.u.def.value;
+ sec_ptr = h->root.u.def.section;
+ if (sec_ptr->output_section != NULL)
+ dyn.d_un.d_val += (sec_ptr->output_section->vma
+ + sec_ptr->output_offset);
+ else
+ {
+ /* The symbol is imported from another shared
+ library and does not apply to this one. */
+ dyn.d_un.d_val = 0;
+ }
+
+ bfd_elf32_swap_dyn_out (dynobj, &dyn, dyncon);
+ }
+
+ }
+
+ }
+ break;
+
+ case DT_PLTGOT:
+ name = ".plt";
+ goto get_vma;
+ case DT_JMPREL:
+ name = ".rela.plt";
+ get_vma:
+ s = bfd_get_section_by_name (output_bfd, name);
+ BFD_ASSERT (s != NULL);
+ dyn.d_un.d_ptr = s->vma;
+ bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+ break;
+
+ case DT_PLTRELSZ:
+ s = bfd_get_section_by_name (output_bfd, ".rela.plt");
+ BFD_ASSERT (s != NULL);
+ dyn.d_un.d_val = s->size;
+ bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+ break;
+
+ case DT_RELASZ:
+ /* My reading of the SVR4 ABI indicates that the
+ procedure linkage table relocs (DT_JMPREL) should be
+ included in the overall relocs (DT_REL). This is
+ what Solaris does. However, UnixWare can not handle
+ that case. Therefore, we override the DT_RELASZ entry
+ here to make it not include the JMPREL relocs. Since
+ the linker script arranges for .rela.plt to follow all
+ other relocation sections, we don't have to worry
+ about changing the DT_REL entry. */
+ s = bfd_get_section_by_name (output_bfd, ".rela.plt");
+ if (s != NULL)
+ dyn.d_un.d_val -= s->size;
+ bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+ break;
+ }
+ }
+
+ /* Fill in the first entry in the procedure linkage table. */
+ if (splt->size > 0)
+ {
+ if (info->shared)
+ {
+ memcpy (splt->contents, elf_arc_pic_plt0_entry, 2 * PLT_ENTRY_SIZE);
+
+ /* fill in the _DYNAMIC@GOTPC+4 and
+ _DYNAMIC@GOTPC+8 at PLT0+4 and PLT0+12 */
+ bfd_put_32_me (output_bfd,
+ ( sgot->output_section->vma + sgot->output_offset + 4 )
+ -(splt->output_section->vma + splt->output_offset ),
+ splt->contents + 4);
+ bfd_put_32_me (output_bfd,
+ (sgot->output_section->vma + sgot->output_offset + 8)
+ -(splt->output_section->vma + splt->output_offset +8),
+ splt->contents + 12);
+
+ /* put got base at plt0+12 */
+ bfd_put_32 (output_bfd,
+ (sgot->output_section->vma + sgot->output_offset),
+ splt->contents + 20);
+ }
+ else
+ {
+ memcpy (splt->contents, elf_arc_abs_plt0_entry, 2 * PLT_ENTRY_SIZE);
+
+ /* in the executable, fill in the exact got addresses
+ for the module id ptr (gotbase+4) and the dl resolve
+ routine (gotbase+8) in the middle endian format */
+ bfd_put_32_me (output_bfd,
+ sgot->output_section->vma + sgot->output_offset + 4,
+ splt->contents + 4);
+ bfd_put_32_me (output_bfd,
+ sgot->output_section->vma + sgot->output_offset + 8,
+ splt->contents + 12);
+
+ /* put got base at plt0+12 */
+ bfd_put_32 (output_bfd,
+ (sgot->output_section->vma + sgot->output_offset),
+ splt->contents + 20);
+
+ }
+
+
+ }
+
+ /* UnixWare sets the entsize of .plt to 4, although that doesn't
+ really seem like the right value. */
+ elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
+
+ }
+
+
+ /* Fill in the first three entries in the global offset table. */
+ if (sgot->size > 0)
+ {
+ if (sdyn == NULL)
+ bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
+ else
+ bfd_put_32 (output_bfd,
+ sdyn->output_section->vma + sdyn->output_offset,
+ sgot->contents);
+ bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
+ bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
+ }
+
+ elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
+
+ return TRUE;
+}
+
+/* Desc : Adjust a symbol defined by a dynamic object and referenced by a
+ regular object. The current definition is in some section of the
+ dynamic object, but we're not including those sections. We have to
+ change the definition to something the rest of the link can
+ understand. */
+
+static bfd_boolean
+elf_arc_adjust_dynamic_symbol (struct bfd_link_info *info,
+ struct elf_link_hash_entry *h)
+{
+ bfd *dynobj;
+ asection *s;
+ unsigned int power_of_two;
+
+ dynobj = elf_hash_table (info)->dynobj;
+
+ /* Make sure we know what is going on here. */
+ BFD_ASSERT (dynobj != NULL
+ && (h->needs_plt
+ || h->u.weakdef != NULL
+ || (h->def_dynamic && h->ref_regular && !h->def_regular)));
+
+ /* If this is a function, put it in the procedure linkage table. We
+ will fill in the contents of the procedure linkage table later,
+ when we know the address of the .got section. */
+ if (h->type == STT_FUNC || h->needs_plt)
+ {
+ if (!info->shared && !h->def_dynamic && !h->ref_dynamic)
+ {
+ /* This case can occur if we saw a PLT32 reloc in an input
+ file, but the symbol was never referred to by a dynamic
+ object. In such a case, we don't actually need to build
+ a procedure linkage table, and we can just do a PC32
+ reloc instead. */
+ BFD_ASSERT (h->needs_plt);
+ return TRUE;
+ }
+
+ /* Make sure this symbol is output as a dynamic symbol. */
+ if (h->dynindx == -1)
+ {
+ if (! bfd_elf_link_record_dynamic_symbol (info, h))
+ return FALSE;
+ }
+
+ s = bfd_get_section_by_name (dynobj, ".plt");
+ BFD_ASSERT (s != NULL);
+
+ /* If this is the first .plt entry, make room for the special
+ first entry. */
+ if (s->size == 0)
+ {
+ s->size += 2 *PLT_ENTRY_SIZE;
+ BFD_DEBUG_PIC (fprintf (stderr, "first plt entry at %d\n", s->size));
+ }
+ else
+ {
+ BFD_DEBUG_PIC (fprintf (stderr, "Next plt entry at %d\n", s->size));
+ }
+
+ /* If this symbol is not defined in a regular file, and we are
+ not generating a shared library, then set the symbol to this
+ location in the .plt. This is required to make function
+ pointers compare as equal between the normal executable and
+ the shared library. */
+ if (!info->shared && !h->def_regular)
+ {
+ h->root.u.def.section = s;
+ h->root.u.def.value = s->size;
+ }
+
+ h->plt.offset = s->size;
+
+ /* Make room for this entry. */
+ s->size += PLT_ENTRY_SIZE;
+
+ /* We also need to make an entry in the .got.plt section, which
+ will be placed in the .got section by the linker script. */
+
+ s = bfd_get_section_by_name (dynobj, ".got.plt");
+ BFD_ASSERT (s != NULL);
+ s->size += 4;
+
+ /* We also need to make an entry in the .rela.plt section. */
+ s = bfd_get_section_by_name (dynobj, ".rela.plt");
+ BFD_ASSERT (s != NULL);
+ s->size += sizeof (Elf32_External_Rela);
+
+ return TRUE;
+ }
+
+ /* If this is a weak symbol, and there is a real definition, the
+ processor independent code will have arranged for us to see the
+ real definition first, and we can just use the same value. */
+ if (h->u.weakdef != NULL)
+ {
+ BFD_ASSERT (h->u.weakdef->root.type == bfd_link_hash_defined
+ || h->u.weakdef->root.type == bfd_link_hash_defweak);
+ h->root.u.def.section = h->u.weakdef->root.u.def.section;
+ h->root.u.def.value = h->u.weakdef->root.u.def.value;
+ return TRUE;
+ }
+
+ /* This is a reference to a symbol defined by a dynamic object which
+ is not a function. */
+
+ /* If we are creating a shared library, we must presume that the
+ only references to the symbol are via the global offset table.
+ For such cases we need not do anything here; the relocations will
+ be handled correctly by relocate_section. */
+ if (info->shared)
+ return TRUE;
+
+ /* We must allocate the symbol in our .dynbss section, which will
+ become part of the .bss section of the executable. There will be
+ an entry for this symbol in the .dynsym section. The dynamic
+ object will contain position independent code, so all references
+ from the dynamic object to this symbol will go through the global
+ offset table. The dynamic linker will use the .dynsym entry to
+ determine the address it must put in the global offset table, so
+ both the dynamic object and the regular object will refer to the
+ same memory location for the variable. */
+
+ s = bfd_get_section_by_name (dynobj, ".dynbss");
+ BFD_ASSERT (s != NULL);
+
+ /* We must generate a R_ARC_COPY reloc to tell the dynamic linker to
+ copy the initial value out of the dynamic object and into the
+ runtime process image. We need to remember the offset into the
+ .rela.bss section we are going to use. */
+ if ((h->root.u.def.section->flags & SEC_ALLOC) != 0)
+ {
+ asection *srel;
+
+ srel = bfd_get_section_by_name (dynobj, ".rela.bss");
+ BFD_ASSERT (srel != NULL);
+ srel->size += sizeof (Elf32_External_Rela);
+ h->needs_copy = 1;
+ }
+
+ /* We need to figure out the alignment required for this symbol. I
+ have no idea how ELF linkers handle this. */
+ power_of_two = bfd_log2 (h->size);
+ if (power_of_two > 3)
+ power_of_two = 3;
+
+ /* Apply the required alignment. */
+ s->size = BFD_ALIGN (s->size, (bfd_size_type) (1 << power_of_two));
+ if (power_of_two > bfd_get_section_alignment (dynobj, s))
+ {
+ if (! bfd_set_section_alignment (dynobj, s, power_of_two))
+ return FALSE;
+ }
+
+ /* Define the symbol as being at this point in the section. */
+ h->root.u.def.section = s;
+ h->root.u.def.value = s->size;
+
+ /* Increment the section size to make room for the symbol. */
+ s->size += h->size;
+
+ return TRUE;
+}
+
+/* Set the sizes of the dynamic sections. */
+
+static bfd_boolean
+elf_arc_size_dynamic_sections (bfd *output_bfd,
+ struct bfd_link_info *info)
+{
+ bfd *dynobj;
+ asection *s;
+ bfd_boolean plt;
+ bfd_boolean relocs;
+ bfd_boolean reltext;
+
+ dynobj = elf_hash_table (info)->dynobj;
+ BFD_ASSERT (dynobj != NULL);
+
+ if (elf_hash_table (info)->dynamic_sections_created)
+ {
+ struct elf_link_hash_entry *h;
+
+ /* Set the contents of the .interp section to the interpreter. */
+ if (! info->shared)
+ {
+ s = bfd_get_section_by_name (dynobj, ".interp");
+ BFD_ASSERT (s != NULL);
+ s->size = sizeof ELF_DYNAMIC_INTERPRETER;
+ s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
+ }
+
+ /* Add some entries to the .dynamic section. We fill in some of the
+ values later, in elf_bfd_final_link, but we must add the entries
+ now so that we know the final size of the .dynamic section. */
+ /* Checking if the .init section is present. We also create DT_INIT / DT_FINE
+ * entries if the init_str has been changed by the user
+ */
+ h = elf_link_hash_lookup (elf_hash_table (info), "init", FALSE,
+ FALSE, FALSE);
+ if ((h != NULL
+ && (h->ref_regular || h->def_regular))
+ || (strcmp (init_str, INIT_SYM_STRING) != 0))
+ {
+ /*Ravi: changed from bfd_elf32_add_dynamic_entry */
+ if (! _bfd_elf_add_dynamic_entry (info, DT_INIT, 0))
+ return FALSE;
+ }
+ h = elf_link_hash_lookup (elf_hash_table (info), "fini", FALSE,
+ FALSE, FALSE);
+ if ((h != NULL
+ && (h->ref_regular || h->def_regular))
+ || (strcmp (fini_str, FINI_SYM_STRING) != 0))
+
+ {
+ /*Ravi: changed from bfd_elf32_add_dynamic_entry */
+ if (! _bfd_elf_add_dynamic_entry (info, DT_FINI, 0))
+ return FALSE;
+ }
+
+ }
+ else
+ {
+ /* We may have created entries in the .rela.got section.
+ However, if we are not creating the dynamic sections, we will
+ not actually use these entries. Reset the size of .rela.got,
+ which will cause it to get stripped from the output file
+ below. */
+ s = bfd_get_section_by_name (dynobj, ".rela.got");
+ if (s != NULL)
+ s->size = 0;
+ }
+
+ /* If this is a -Bsymbolic shared link, then we need to discard all
+ PC relative relocs against symbols defined in a regular object.
+ We allocated space for them in the check_relocs routine, but we
+ will not fill them in in the relocate_section routine. */
+ if (info->shared && info->symbolic)
+ elf_ARC_link_hash_traverse (elf_ARC_hash_table (info),
+ elf_ARC_discard_copies,
+ (void *) NULL);
+
+ /* The check_relocs and adjust_dynamic_symbol entry points have
+ determined the sizes of the various dynamic sections. Allocate
+ memory for them. */
+ plt = FALSE;
+ relocs = FALSE;
+ reltext = FALSE;
+ for (s = dynobj->sections; s != NULL; s = s->next)
+ {
+ const char *name;
+ bfd_boolean strip;
+
+ if ((s->flags & SEC_LINKER_CREATED) == 0)
+ continue;
+
+ /* It's OK to base decisions on the section name, because none
+ of the dynobj section names depend upon the input files. */
+ name = bfd_get_section_name (dynobj, s);
+
+ strip = FALSE;
+
+ if (strcmp (name, ".plt") == 0)
+ {
+ if (s->size == 0)
+ {
+ /* Strip this section if we don't need it; see the
+ comment below. */
+ strip = TRUE;
+ }
+ else
+ {
+ /* Remember whether there is a PLT. */
+ plt = TRUE;
+ }
+ }
+ else if (strncmp (name, ".rela", 5) == 0)
+ {
+ if (s->size == 0)
+ {
+ /* If we don't need this section, strip it from the
+ output file. This is mostly to handle .rela.bss and
+ .rela.plt. We must create both sections in
+ create_dynamic_sections, because they must be created
+ before the linker maps input sections to output
+ sections. The linker does that before
+ adjust_dynamic_symbol is called, and it is that
+ function which decides whether anything needs to go
+ into these sections. */
+ strip = TRUE;
+ }
+ else
+ {
+ asection *target;
+
+ /* Remember whether there are any reloc sections other
+ than .rela.plt. */
+ if (strcmp (name, ".rela.plt") != 0)
+ {
+ const char *outname;
+
+ relocs = TRUE;
+
+ /* If this relocation section applies to a read only
+ section, then we probably need a DT_TEXTREL
+ entry. The entries in the .rela.plt section
+ really apply to the .got section, which we
+ created ourselves and so know is not readonly. */
+ outname = bfd_get_section_name (output_bfd,
+ s->output_section);
+ target = bfd_get_section_by_name (output_bfd, outname + 4);
+ if (target != NULL
+ && (target->flags & SEC_READONLY) != 0
+ && (target->flags & SEC_ALLOC) != 0)
+ reltext = TRUE;
+ }
+
+ /* We use the reloc_count field as a counter if we need
+ to copy relocs into the output file. */
+ s->reloc_count = 0;
+ }
+ }
+ else if (strncmp (name, ".got", 4) != 0)
+ {
+ /* It's not one of our sections, so don't allocate space. */
+ continue;
+ }
+
+ if (strip)
+ {
+ asection **spp;
+
+ for (spp = &s->output_section->owner->sections;
+ *spp != s->output_section;
+ spp = &(*spp)->next)
+ ;
+ *spp = s->output_section->next;
+ --s->output_section->owner->section_count;
+
+ continue;
+ }
+
+ /* Allocate memory for the section contents. */
+ s->contents = (bfd_byte *) bfd_alloc (dynobj, s->size);
+ if (s->contents == NULL && s->size != 0)
+ return FALSE;
+ }
+
+ if (elf_hash_table (info)->dynamic_sections_created)
+ {
+ /* Add some entries to the .dynamic section. We fill in the
+ values later, in elf_arc_finish_dynamic_sections, but we
+ must add the entries now so that we get the correct size for
+ the .dynamic section. The DT_DEBUG entry is filled in by the
+ dynamic linker and used by the debugger. */
+ if (! info->shared)
+ {
+ /*Ravi: changed from bfd_elf32_add_dynamic_entry */
+ if (! _bfd_elf_add_dynamic_entry (info, DT_DEBUG, 0))
+ return FALSE;
+ }
+
+ if (plt)
+ {
+ /*Ravi: changed from bfd_elf32_add_dynamic_entry */
+ if (! _bfd_elf_add_dynamic_entry (info, DT_PLTGOT, 0)
+ || ! _bfd_elf_add_dynamic_entry (info, DT_PLTRELSZ, 0)
+ || ! _bfd_elf_add_dynamic_entry (info, DT_PLTREL, DT_RELA)
+ || ! _bfd_elf_add_dynamic_entry (info, DT_JMPREL, 0))
+ return FALSE;
+ }
+
+ if (relocs)
+ {
+ /*Ravi: changed from bfd_elf32_add_dynamic_entry */
+ if (! _bfd_elf_add_dynamic_entry (info, DT_RELA, 0)
+ || ! _bfd_elf_add_dynamic_entry (info, DT_RELASZ, 0)
+ || ! _bfd_elf_add_dynamic_entry (info, DT_RELENT,
+ sizeof (Elf32_External_Rela)))
+ return FALSE;
+ }
+
+ if (reltext)
+ {
+ /*Ravi: changed from bfd_elf32_add_dynamic_entry */
+ if (! _bfd_elf_add_dynamic_entry (info, DT_TEXTREL, 0))
+ return FALSE;
+ }
+ }
+
+ return TRUE;
+}
+
+/* Core file support. */
+/* Support for core dump NOTE sections. */
+
+static bfd_boolean
+elf_arc_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
+{
+ int offset;
+ size_t size;
+
+ switch (note->descsz)
+ {
+ default:
+ return FALSE;
+
+ case 240: /* Linux/ARC700 */
+ /* pr_cursig */
+ elf_tdata (abfd)->core_signal = bfd_get_16 (abfd, note->descdata + 12);
+
+ /* pr_pid */
+ elf_tdata (abfd)->core_pid = bfd_get_32 (abfd, note->descdata + 24);
+
+ /* pr_reg */
+ offset = 72;
+ size = 164;
+
+ break;
+ }
+
+
+ /* Make a ".reg/999" section. */
+ return _bfd_elfcore_make_pseudosection (abfd, ".reg",
+ size, note->descpos + offset);
+}
+
+static bfd_boolean
+elf_arc_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
+{
+
+ switch (note->descsz)
+ {
+ default:
+ return FALSE;
+
+ case 124: /* ARC / Linux elf_prpsinfo. */
+ elf_tdata (abfd)->core_program
+ = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
+ elf_tdata (abfd)->core_command
+ = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
+ }
+
+
+ /* Note that for some reason, a spurious space is tacked
+ onto the end of the args in some (at least one anyway)
+ implementations, so strip it off if it exists. */
+ {
+ char *command = elf_tdata (abfd)->core_command;
+ int n = strlen (command);
+
+ if (0 < n && command[n - 1] == ' ')
+ command[n - 1] = '\0';
+ }
+
+ return TRUE;
+}
+
+#define TARGET_LITTLE_SYM bfd_elf32_littlearc_vec
+#define TARGET_LITTLE_NAME "elf32-littlearc"
+#define TARGET_BIG_SYM bfd_elf32_bigarc_vec
+#define TARGET_BIG_NAME "elf32-bigarc"
+#define ELF_ARCH bfd_arch_arc
+#define ELF_MACHINE_CODE EM_ARC
+#define ELF_MACHINE_ALT1 EM_ARCOMPACT
+#define ELF_MAXPAGESIZE 0x1000
+
+#define elf_info_to_howto arc_info_to_howto_rel
+#define elf_info_to_howto_rel arc_info_to_howto_rel
+#define bfd_elf32_bfd_merge_private_bfd_data arc_elf_merge_private_bfd_data
+#define bfd_elf32_bfd_reloc_type_lookup arc_elf32_bfd_reloc_type_lookup
+
+#define elf_backend_object_p arc_elf_object_p
+#define elf_backend_final_write_processing arc_elf_final_write_processing
+#define elf_backend_relocate_section elf_arc_relocate_section
+#define elf_backend_check_relocs elf_arc_check_relocs
+#define elf_backend_adjust_dynamic_symbol elf_arc_adjust_dynamic_symbol
+
+#define elf_backend_finish_dynamic_sections elf_arc_finish_dynamic_sections
+
+#define elf_backend_finish_dynamic_symbol elf_arc_finish_dynamic_symbol
+
+#define elf_backend_create_dynamic_sections _bfd_elf_create_dynamic_sections
+
+#define elf_backend_size_dynamic_sections elf_arc_size_dynamic_sections
+
+#define elf_backend_want_got_plt 1
+#define elf_backend_plt_readonly 1
+#define elf_backend_want_plt_sym 0
+#define elf_backend_got_header_size 12
+#define elf_backend_grok_psinfo elf_arc_grok_psinfo
+#define elf_backend_grok_prstatus elf_arc_grok_prstatus
#include "elf32-target.h"
diff --git a/bfd/libbfd.h b/bfd/libbfd.h
index cfc364f..0eced4c 100644
--- a/bfd/libbfd.h
+++ b/bfd/libbfd.h
@@ -1402,6 +1402,32 @@
"BFD_RELOC_SH_TLS_TPOFF32",
"BFD_RELOC_ARC_B22_PCREL",
"BFD_RELOC_ARC_B26",
+ "BFD_RELOC_ARC_S21H_PCREL",
+ "BFD_RELOC_ARC_S21W_PCREL",
+ "BFD_RELOC_ARC_S25H_PCREL",
+ "BFD_RELOC_ARC_S25W_PCREL",
+ "BFD_RELOC_ARC_S13_PCREL",
+ "BFD_RELOC_ARC_32_ME",
+ "BFD_RELOC_ARC_PC32 ",
+ "BFD_RELOC_ARC_GOTPC32",
+ "BFD_RELOC_ARC_PLT32 ",
+ "BFD_RELOC_ARC_COPY",
+ "BFD_RELOC_ARC_GLOB_DAT",
+ "BFD_RELOC_ARC_JMP_SLOT",
+ "BFD_RELOC_ARC_RELATIVE",
+ "BFD_RELOC_ARC_GOTOFF",
+ "BFD_RELOC_ARC_GOTPC",
+ "BFD_RELOC_ARC_GOT32",
+ "BFD_RELOC_ARC_SDA",
+ "BFD_RELOC_ARC_SDA32",
+ "BFD_RELOC_ARC_SDA_LDST",
+ "BFD_RELOC_ARC_SDA_LDST1",
+ "BFD_RELOC_ARC_SDA_LDST2",
+ "BFD_RELOC_ARC_SDA16_LD",
+ "BFD_RELOC_ARC_SDA16_LD1",
+ "BFD_RELOC_ARC_SDA16_LD2",
+ "BFD_RELOC_ARC_SDA32_ME",
+
"BFD_RELOC_BFIN_16_IMM",
"BFD_RELOC_BFIN_16_HIGH",
"BFD_RELOC_BFIN_4_PCREL",
diff --git a/bfd/reloc.c b/bfd/reloc.c
index 027ede0..8e1dee5 100644
--- a/bfd/reloc.c
+++ b/bfd/reloc.c
@@ -3179,6 +3179,137 @@
ARC 26 bit absolute branch. The lowest two bits must be zero and are not
stored in the instruction. The high 24 bits are installed in bits 23
through 0.
+ENUM
+ BFD_RELOC_ARC_S21H_PCREL
+ENUMDOC
+ ARCompact 21 bit pc-relative branch. The lowest bit must be zero and is
+ not stored in the instruction. The remaining 20 bits are installed in
+ 2 groups of 10 bits each. The high 10 bits are installed in bits 26
+ through 17 and the remaining 10 bits in bits 15 through 6.
+ENUM
+ BFD_RELOC_ARC_S21W_PCREL
+ENUMDOC
+ ARCompact 21 bit pc-relative branch. The lowest two bits must be zero and
+ are not stored in the instruction. The remaining 19 bits are installed in
+ 2 groups of 9 and 10 bits each. The high 9 bits are installed in bits 26
+ through 18 and the remaining 10 bits in bits 15 through 6.
+ENUM
+ BFD_RELOC_ARC_S25H_PCREL
+ENUMDOC
+ ARCompact 25 bit pc-relative branch. The lowest bit must be zero and is
+ not stored in the instruction. The remaining 24 bits are installed in
+ 3 groups of 10 bits, 10 bits and 4 bits each. The high 10 bits are
+ installed in bits 26 through 17, next 10 bits in bits 15 through 6 and the
+ remaining 4 bits in bits 3 through 0.
+ENUM
+ BFD_RELOC_ARC_S25W_PCREL
+ENUMDOC
+ ARCompact 25 bit pc-relative branch. The lowest two bits must be zero and
+ are not stored in the instruction. The remaining 23 bits are installed in
+ 3 groups of 10 bits, 9 bits and 4 bits each. The high 9 bits are installed
+ in bits 26 through 18, next 10 bits in bits 15 through 6 and the
+ remaining 4 bits in bits 3 through 0.
+ENUM
+ BFD_RELOC_ARC_S13_PCREL
+ENUMDOC
+ ARCompact 13 bit pc-relative branch. The lowest 2 bits must be zero and
+ are not stored in the the instruction. The upper 11 bits are installed
+ in bits 10 through 0.
+ENUM
+ BFD_RELOC_ARC_32_ME
+ENUMDOC
+ ARCompact Middle-endian 32 bit word relocation
+ENUM
+ BFD_RELOC_ARC_PC32
+ENUMDOC
+ ARCompact PC Relative 32 bit relocation.
+ENUM
+ BFD_RELOC_ARC_GOTPC32
+ENUMDOC
+ ARC 700 GOT specific relocation. This computes the distance from the current
+pcl to the symbol's global offset table entry.
+ENUM
+ BFD_RELOC_ARC_PLT32
+ENUMDOC
+ ARC 700 PLT specific relocation. This computes the distance from the base
+of the PLT to the symbols PLT entry.
+ENUM
+ BFD_RELOC_ARC_COPY
+ENUMDOC
+ ARC 700 Copy relocation. This refers to a location in the writable segment
+and during execution the dynamic linker copies data associated with the shared
+objects symbol to the location specified by the offset. Created for
+dynamic linking by the linker .
+ENUM
+BFD_RELOC_ARC_GLOB_DAT
+ENUMDOC
+ ARC 700 Global Data relocaton.This is to set a GOT entry to the address
+of the specified symbol . This allows one to determine the correspondence
+between symbols and GOT entries.
+ENUM
+BFD_RELOC_ARC_JMP_SLOT
+ENUMDOC
+ This gives the location of a PLT entrys GOT entry. The dynamic linker
+modifies the GOT entry so that the PLT will transfer control to the designated
+symbols address. Created by the linker.
+ENUM
+BFD_RELOC_ARC_RELATIVE
+ENUMDOC
+ This gives the location of a value representing a relative address.
+The dynamic linker adds the load address of the shared library to
+the relative address to compute the final address.
+ENUM
+BFD_RELOC_ARC_GOTOFF
+ENUMDOC
+This gives the difference between a symbols value and the address of the
+Global Offset Table This causes the linker to build the GOT.
+ENUM
+BFD_RELOC_ARC_GOTPC
+ENUMDOC
+This gives the difference between the address of the GOT base and the
+current PC. The symbol referenced is _GLOBAL_OFFSET_TABLE .
+ENUM
+BFD_RELOC_ARC_GOT32
+ENUMDOC
+ARC 700 GOT specific relocation. This computes the distance from the base
+of the GOT to the symbol's global offset table entry.
+ENUM
+BFD_RELOC_ARC_SDA
+ENUMDOC
+small data reloc 1
+ENUM
+BFD_RELOC_ARC_SDA32
+ENUMDOC
+small data reloc 2
+ENUM
+BFD_RELOC_ARC_SDA_LDST
+ENUMDOC
+small data reloc 3
+ENUM
+BFD_RELOC_ARC_SDA_LDST1
+ENUMDOC
+small data reloc 4
+ENUM
+BFD_RELOC_ARC_SDA_LDST2
+ENUMDOC
+small data reloc 5
+ENUM
+BFD_RELOC_ARC_SDA16_LD
+ENUMDOC
+small data reloc 6
+ENUM
+BFD_RELOC_ARC_SDA16_LD1
+ENUMDOC
+small data reloc 7
+ENUM
+BFD_RELOC_ARC_SDA16_LD2
+ENUMDOC
+small data reloc 8
+ENUM
+BFD_RELOC_ARC_SDA32_ME
+ENUMDOC
+small data reloc 9
+COMMENT
ENUM
BFD_RELOC_BFIN_16_IMM
diff --git a/cpu/ARCompact.cpu b/cpu/ARCompact.cpu
new file mode 100644
index 0000000..5e609a2
--- /dev/null
+++ b/cpu/ARCompact.cpu
@@ -0,0 +1,3293 @@
+; ARCompact CPU description. -*- Scheme -*-
+; Copyright 1998, 1999, 2000, 2001, 2003, 2006, 2007, 2008
+; Free Software Foundation, Inc.
+; This file is part of CGEN.
+; See file COPYING.CGEN for details.
+
+(include "simplify.inc")
+
+(if (application-is? SID-SIMULATOR)
+ (fixme))
+
+; This is how we do delayed jumps for sim.
+(define-pmacro (delay-jump target) (delay 1 (set pc target)))
+
+; define-arch must appear first
+
+(define-arch
+ (name ARCompact) ; name of cpu family
+ (comment "ARC ARCompact")
+ (default-alignment aligned)
+ ; Should be #t but cgen can't handle variable length insns with #t
+ (insn-lsb0? #f)
+ ; a4 not modelled here.
+ (machs a5 arc600 arc700)
+ (isas ARCompact)
+)
+
+; Attributes
+(define-attr
+ (type enum)
+ (for insn)
+ (name LIMM)
+ (comment "can take long immediate for operand")
+ (attrs)
+ (values none h B BC C)
+ (default none)
+)
+
+(define-attr
+ (type boolean)
+ (for insn)
+ (name SHORT_P)
+ (comment "has short opcode")
+ (attrs)
+ (default #f)
+)
+
+(define-attr
+ (type boolean)
+ (for mach)
+ (name ISARC700)
+ (comment "to test mach being arc700")
+ (attrs)
+ (default #f)
+)
+
+; Instruction set parameters.
+
+(define-isa
+ (name ARCompact)
+
+ ; The default size of an instruction in bits
+ (default-insn-bitsize 32)
+
+ ; Number of bits of insn we can initially fetch.
+ ; ??? FIXME: this should be 16, but that gives spurious decoder ambiguities.
+ ; ??? weirdly enough, base_insn is still expected to be 16 bits.
+ (base-insn-bitsize 32)
+
+ ; Used in computing bit numbers.
+ (default-insn-word-bitsize 32)
+
+ ; Initial bitnumbers to decode insns by.
+ ;(decode-assist (0 1 2 3 4))
+ ;(decode-assist (0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15))
+ (decode-splits
+ (f-F ()
+ ( (unchanged (0)) (update (1))))
+ (f-op-A ()
+ (
+ (normal (.iota 32))
+ (special (.iota 32 32))))
+ (f-op-B ()
+ (
+ (normal (.iota 32))
+ (special (.iota 32 32))))
+ (f-op-C ()
+ (
+ (no-ilink (.splice (.unsplice (.iota 28)) (.unsplice (.iota 30 31))))
+ (ilinkx (28 29))))
+ (f-op-Cj ()
+ (
+ (normal (.splice (.unsplice (.iota 28)) 30 31 60))
+ (ilinkx (28 29))
+ (jump-limm (62))
+ (special (.splice (.unsplice (.iota 28 32)) 61 63)))))
+
+ ; insn-types - not used.
+ ; Instruction framing (frame) - not used.
+)
+
+; Cpu family definitions.
+
+; ??? define-cpu-family [and in general "cpu-family"] might be clearer than
+; define-cpu.
+; ??? Have define-arch provide defaults for architecture that define-cpu can
+; then override [reduces duplication in define-cpu].
+; ??? Another way to go is to delete cpu-families entirely and have one mach
+; able to inherit things from another mach (would also need the ability to
+; not only override specific inherited things but also disable some,
+; e.g. if an insn wasn't supported).
+
+(define-cpu
+ ; cpu names must be distinct from the architecture name and machine names.
+ ; The "b" suffix stands for "base" and is the convention.
+ ; It does not make sense to label ARCtangent-A5 as the "base" in the cgen
+ ; sense here because the ARC600 supports only a reduced set of 16 core
+ ; registers.
+ ; The "f" suffix stands for "family" and is the convention.
+ (name a5f)
+ (comment "ARCtangent-A5 processor family")
+ (endian little)
+ (word-bitsize 32)
+ (insn-chunk-bitsize 16)
+ ; Generated files have a "5" suffix.
+ (file-transform "5")
+)
+
+(define-cpu
+ (name arc600f)
+ (comment "ARC 600 processor family")
+ (endian either)
+ (word-bitsize 32)
+ (insn-chunk-bitsize 16)
+ ; Generated files have a "6" suffix.
+ (file-transform "6")
+)
+
+(define-cpu
+ (name arc700f)
+ (comment "ARC 700 processor family")
+ (endian either)
+ (word-bitsize 32)
+ (insn-chunk-bitsize 16)
+ ; Generated files have a "7" suffix.
+ (file-transform "7")
+)
+
+(define-mach
+ (name a5)
+ (comment "ARCtangent-A5 cpu")
+ (cpu a5f)
+ (bfd-name "A5")
+)
+
+(define-mach
+ (name arc600)
+ (comment "ARC600 cpu")
+ (cpu arc600f)
+ (bfd-name "ARC600")
+)
+
+(define-mach
+ (name arc700)
+ (comment "ARC700 cpu")
+ (attrs ISARC700)
+ (cpu arc700f)
+ (bfd-name "ARC700")
+)
+
+; Model descriptions. No exact timing modelling at the moment.
+(define-model
+ (name A5)
+ (comment "ARCtangent-A5 cpu")
+ (mach a5)
+ (unit u-exec "Execution Unit" ()
+ 1 1 ; issue done
+ ()
+ ((b INT -1) (c INT -1)) ;inputs
+ ((a INT -1)) ; outputs
+ ())
+)
+
+(define-model
+ (name ARC600)
+ (comment "ARC600 cpu")
+ (mach arc600)
+ (unit u-exec "Execution Unit" ()
+ 1 1 ; issue done
+ ()
+ ((b INT -1) (c INT -1)) ;inputs
+ ((a INT -1)) ; outputs
+ ())
+)
+
+(define-model
+ (name ARC700)
+ (comment "ARC700 cpu")
+ (mach arc700)
+ (unit u-exec "Execution Unit" ()
+ 1 1 ; issue done
+ ()
+ ((b INT -1) (c INT -1)) ;inputs
+ ((a INT -1)) ; outputs
+ ())
+)
+
+; Instruction fields.
+;
+; Attributes:
+; RESERVED: bits are not used to decode insn, must be all 0.
+
+;(define-attr
+; (for ifield operand)
+; (type boolean)
+; (name RESERVED)
+; (comment "This field is reserved.")
+;)
+
+(define-pmacro (d2nf xname xcomment xattrs xstart xlength)
+ (define-ifield
+ (name xname)
+ (comment xcomment)
+ (.splice attrs (.unsplice xattrs))
+ (word-offset 16)
+ (word-length 16)
+ (start xstart)
+ (length xlength)
+ (mode UINT)
+ (encode #f)
+ (decode #f)
+ )
+)
+
+(define-pmacro (d3f xname xcomment xattrs xstart xlength)
+ (define-ifield
+ (name xname)
+ (comment xcomment)
+ (.splice attrs (.unsplice xattrs))
+ (word-offset 32)
+ (word-length 16)
+ (start xstart)
+ (length xlength)
+ (mode UINT)
+ (encode #f)
+ (decode #f)
+ )
+)
+
+(dnf f-cond-Q "Condition" () 27 5)
+;(d2nf f-cond-Q "Condition" () 11 5)
+(dnf f-cond-i2 "Condition" () 5 2)
+(dnf f-cond-i3 "Condition" () 7 3)
+(dnf f-brcond "brcc / bbit condition" () 28 4)
+;(d2nf f-brcond "brcc / bbit condition" () 12 4)
+(dnf f-op--a "operand a" () 13 3)
+(dnf f-op--b "operand b" () 5 3)
+(dnf f-op--c "operand c" () 8 3)
+(dnf f-B-5-3 "bits 5..3 of B" () 17 3)
+;(d2nf f-B-5-3 "bits 5..3 of B" () 1 3)
+(dnmf f-op-B "operand B" () UINT
+ (f-op--b f-B-5-3)
+ (sequence () ; insert
+ (set (ifield f-op--b) (and (ifield f-op-B) (const 7)))
+ (set (ifield f-B-5-3) (srl (ifield f-op-B) (const 3)))
+ )
+ (sequence () ; extract
+ (set (ifield f-op-B) (or (ifield f-op--b)
+ (sll (ifield f-B-5-3) (const 3))))
+ )
+)
+(dnf f-op-C "operand C" () 20 6)
+(dnf f-op-Cj "operand C" () 20 6)
+;(d2nf f-op-C "operand C" () 4 6)
+(dnf f-h-2-0 "bits 2..0 of h" () 8 3)
+(dnf f-h-5-3 "bits 5..3 of h" () 13 3)
+(dnmf f-op-h "operand h" () UINT
+ (f-h-2-0 f-h-5-3)
+ (sequence () ; insert
+ (set (ifield f-h-2-0) (and (ifield f-op-h) (const 7)))
+ (set (ifield f-h-5-3) (srl (ifield f-op-h) (const 3)))
+ )
+ (sequence () ; extract
+ (set (ifield f-op-h) (or (ifield f-h-2-0)
+ (sll (ifield f-h-5-3) (const 3))))
+ )
+)
+(dnf f-u6 "uns 6 bit immediate" () 20 6)
+;(d2nf f-u6 "uns 6 bit immediate" () 4 6)
+(df f-u6x2 "uns 6 bit immediate x 2" () 20 6 UINT
+ ((value pc) (srl SI value 1))
+ ((value pc) (sll SI value 1)))
+(dnf f-delay-N "delay slot exposed" () 26 1)
+;(d2nf f-delay-N "delay slot exposed" () 10 1)
+(dnf f-res27 "reserved bit 27" (RESERVED) 27 1)
+(dnf f-F "update flags" () 16 1)
+;(d2nf f-F "update flags" () 0 1)
+(dnf f-cbranch-imm "compare immediate" () 27 1)
+;(d2nf f-cbranch-imm "compare immediate" () 11 1)
+(dnf f-op-A "operand A" () 26 6)
+;(d2nf f-op-A "operand A" () 10 6)
+(df f-s12h "high part of s12imm" () 26 6 INT #f #f)
+(dnmf f-s12 "signed 12 bit immediate" () INT
+ (f-u6 f-s12h)
+ (sequence () ; insert
+ (set (ifield f-u6) (and (ifield f-s12) (const 63)))
+ (set (ifield f-s12h) (sra (ifield f-s12) (const 6)))
+ )
+ (sequence () ; extract
+ (set (ifield f-s12) (or (ifield f-u6)
+ (sll (ifield f-s12h) (const 6))))
+ )
+)
+(dnmf f-s12x2 "signed 12 bit immediate times 2" () INT
+ (f-u6 f-s12h)
+ (sequence () ; insert
+ (set (ifield f-u6) (and (sra (ifield f-s12x2) 1) (const 63)))
+ (set (ifield f-s12h) (sra (ifield f-s12x2) (const 7)))
+ )
+ (sequence () ; extract
+ (set (ifield f-s12x2) (or (sll (ifield f-u6) (const 1))
+ (sll (ifield f-s12h) (const 7))))
+ )
+)
+(df f-rel10 "disp10" (PCREL-ADDR) 7 9 INT
+ ((value pc) (sra WI (sub WI value (and WI pc (const -4))) (const 1)))
+ ((value pc) (add WI (sll WI value (const 1)) (and WI pc (const -4)))))
+(df f-rel7 "disp7" (PCREL-ADDR) 10 6 INT
+ ((value pc) (sra WI (sub WI value (and WI pc (const -4))) (const 1)))
+ ((value pc) (add WI (sll WI value (const 1)) (and WI pc (const -4)))))
+(df f-rel8 "disp8" (PCREL-ADDR) 9 7 INT
+ ((value pc) (sra WI (sub WI value (and WI pc (const -4))) (const 1)))
+ ((value pc) (add WI (sll WI value (const 1)) (and WI pc (const -4)))))
+(df f-rel13bl "disp13" (PCREL-ADDR) 5 11 INT
+ ((value pc) (sra WI (sub WI value (and WI pc (const -4))) (const 2)))
+ ((value pc) (add WI (sll WI value (const 2)) (and WI pc (const -4)))))
+(dnf f-d21l "21 bit disp low part" () 5 10)
+(dnf f-d21bl "bl disp low part" () 5 9)
+(df f-d21h "21 bit disp high part" () 16 10 INT #f #f)
+(dnf f-d25m "25 bit disp med part" () 16 10)
+;(d2nf f-d25m "25 bit disp med part" () 0 10)
+(df f-d25h "25 bit disp high part" () 28 4 INT #f #f)
+(dnmf f-rel21 "21 bit pc relative signed offset" (PCREL-ADDR) INT
+ (f-d21l f-d21h)
+ (sequence () ; insert
+ (set (ifield f-d21l)
+ (and (srl (sub (ifield f-rel21) (and pc (const -4)))
+ (const 1))
+ (const #x3ff)))
+ (set (ifield f-d21h)
+ (sra (sub (ifield f-rel21) (and pc (const -4)))
+ (const 11)))
+ )
+ (sequence () ; extract
+ (set (ifield f-rel21)
+ (add (or (sll (ifield f-d21l) (const 1))
+ (sll (ifield f-d21h) (const 11)))
+ (and pc (const -4))))
+ )
+)
+(dnmf f-rel21bl "21 bit bl pc relative signed offset" (PCREL-ADDR) INT
+ (f-d21bl f-d21h)
+ (sequence () ; insert
+ (set (ifield f-d21bl)
+ (and (srl (sub (ifield f-rel21bl) (and pc (const -4)))
+ (const 2))
+ (const #x1ff)))
+ (set (ifield f-d21h)
+ (sra (sub (ifield f-rel21bl) (and pc (const -4)))
+ (const 11)))
+ )
+ (sequence () ; extract
+ (set (ifield f-rel21bl)
+ (add (or (sll (ifield f-d21bl) (const 2))
+ (sll (ifield f-d21h) (const 11)))
+ (and pc (const -4))))
+ )
+)
+(dnmf f-rel25 "25 bit pc relative signed offset" (PCREL-ADDR) INT
+ (f-d21l f-d25m f-d25h)
+ (sequence () ; insert
+ (set (ifield f-d21l)
+ (and (srl (sub (ifield f-rel25) (and pc (const -4)))
+ (const 1))
+ (const #x3ff)))
+ (set (ifield f-d25m)
+ (srl (sub (ifield f-rel25) (and pc (const -4)))
+ (const 11)))
+ (set (ifield f-d25h)
+ (sra (sub (ifield f-rel25) (and pc (const -4)))
+ (const 21)))
+ )
+ (sequence () ; extract
+ (set (ifield f-rel25)
+ (add (or (or (sll (ifield f-d21l) (const 1))
+ (sll (ifield f-d25m) (const 11)))
+ (sll (ifield f-d25h) (const 21)))
+ (and pc (const -4))))
+ )
+)
+(dnmf f-rel25bl "25 bit bl pc relative signed offset" (PCREL-ADDR) INT
+ (f-d21bl f-d25m f-d25h)
+ (sequence () ; insert
+ (set (ifield f-d21bl)
+ (and (srl (sub (ifield f-rel25bl) (and pc (const -4)))
+ (const 2))
+ (const #x1ff)))
+ (set (ifield f-d25m)
+ (srl (sub (ifield f-rel25bl) (and pc (const -4)))
+ (const 11)))
+ (set (ifield f-d25h)
+ (sra (sub (ifield f-rel25bl) (and pc (const -4)))
+ (const 21)))
+ )
+ (sequence () ; extract
+ (set (ifield f-rel25bl)
+ (add (or (or (sll (ifield f-d21bl) (const 2))
+ (sll (ifield f-d25m) (const 11)))
+ (sll (ifield f-d25h) (const 21)))
+ (and pc (const -4))))
+ )
+)
+
+(dnf f-d9l "9 bit disp low part" () 8 7)
+(df f-d9h "9 bit disp high part" () 16 1 INT #f #f)
+(dnmf f-rel9 "9 bit pc relative signed offset" (PCREL-ADDR) INT
+ (f-d9l f-d9h)
+ (sequence () ; insert
+ (set (ifield f-d9l)
+ (and (srl (sub (ifield f-rel9) (and pc (const -4)))
+ (const 1))
+ (const #x7f)))
+ (set (ifield f-d9h)
+ (sra (sub (ifield f-rel9) (and pc (const -4)))
+ (const 8)))
+ )
+ (sequence () ; extract
+ (set (ifield f-rel9)
+ (add (or (sll (ifield f-d9l) (const 1))
+ (sll (ifield f-d9h) (const 8)))
+ (and pc (const -4))))
+ )
+)
+(dnf f-u3 "uns 3 bit immediate" () 13 3)
+(dnf f-u5 "uns 5 bit immediate" () 11 5)
+(dnf f-u7 "uns 7 bit immediate" () 9 7)
+(dnf f-u8 "uns 8 bit immediate" () 8 8)
+(dnmf f-s9 "sgn 9 bit immediate" () INT
+ (f-u8 f-d9h)
+ (sequence () ; insert
+ (set (ifield f-u8)
+ (and (ifield f-s9) (const #xff)))
+ (set (ifield f-d9h) (sra (ifield f-s9) (const 8)))
+ )
+ (sequence () ; extract
+ (set (ifield f-s9)
+ (or (ifield f-u8)
+ (sll (ifield f-d9h) (const 8))))
+ )
+)
+
+(df f-u5x2 "uns 5 bit immediate x 2" () 11 5 UINT
+ ((value pc) (srl SI value 1))
+ ((value pc) (sll SI value 1)))
+(df f-u5x4 "uns 5 bit immediate x 4" () 11 5 UINT
+ ((value pc) (srl SI value 2))
+ ((value pc) (sll SI value 2)))
+(df f-u8x4 "uns 8 bit immediate x 4" () 8 8 UINT
+ ((value pc) (srl SI value 2))
+ ((value pc) (sll SI value 2)))
+(df f-s9x1 "sgn 9 bit immediate x 1" () 7 9 INT #f #f)
+(df f-s9x2 "sgn 9 bit immediate x 2" () 7 9 INT
+ ((value pc) (srl SI value 1))
+ ((value pc) (sll SI value 1)))
+(df f-s9x4 "sgn 9 bit immediate x 4" () 7 9 INT
+ ((value pc) (srl SI value 2))
+ ((value pc) (sll SI value 2)))
+
+; ??? condition code setting and branching could be sped up if we
+; didn't compute the condition codes till they are used - e.g.
+; for a compare insn, store the two inputs and a code that says to
+; use compare semantics.
+
+; The condition code bits.
+
+(dsh h-lbit "loop inhibit bit" () (register BI))
+(dsh h-zbit "zerobit" () (register BI))
+(dsh h-nbit "negative bit" () (register BI))
+(dsh h-cbit "carry bit" () (register BI))
+(dsh h-vbit "overflow bit" () (register BI))
+(dsh h-ubit "user mode bit" () (register BI))
+(dsh h-e1 "interupt 1 enable bit" () (register BI))
+(dsh h-e2 "interupt 2 enable bit" () (register BI))
+(dsh h-s1bit "channel 1 saturate" () (register BI))
+(dsh h-s2bit "channel 2 saturate" () (register BI))
+
+(dnop lbit "loop inhibit bit" () h-lbit f-nil)
+(dnop zbit "zero bit" () h-zbit f-nil)
+(dnop nbit "negative bit" () h-nbit f-nil)
+(dnop cbit "carry bit" () h-cbit f-nil)
+(dnop vbit "overflow bit" () h-vbit f-nil)
+(dnop s1bit "channel 1 saturate" () h-s1bit f-nil)
+(dnop s2bit "channel 2 saturate" () h-s2bit f-nil)
+
+; ??? There should be an official rtx to do this. Until then.
+(define-pmacro (invalid-insn)
+ (error VOID "invalid insn")
+)
+
+(define-pmacro (invalid-expr)
+ (sequence BI () (error "invalid insn") (const 0))
+)
+
+(define-pmacro (my-eval form)
+ (eval form)
+)
+
+(define-pmacro (twice val)
+ (val val)
+)
+
+; We simulate interrupts just before jumps - that's good enough for profiling.
+; We simulate timer0, which uses vector 3 (vector base + 0x18) and ilink1.
+(define-pmacro (int-jump xxjsemantics) (int-timer1 pc 0 xxjsemantics))
+(define-pmacro (int-jumpd xxjsemantics) (int-timer1 pc 1 xxjsemantics))
+(define-pmacro (int-timer1 retaddr delayed_p xjsemantics)
+ (if (andif (ge (sub (c-code SI "CPU_INSN_COUNT (current_cpu)")
+ (reg h-timer-expire))
+ 0)
+ (andif (reg h-e1) (and (aux-control0) 1)))
+ (sequence ()
+ (set (aux-count0)
+ (sub (c-code SI "CPU_INSN_COUNT (current_cpu)")
+ (reg h-timer-expire)))
+ (cond
+ ( (reg h-ubit)
+ (sequence ((SI countp) (UHI count))
+ (set countp (add (and (srl retaddr 1) -2) (reg h-prof-offset)))
+ (set count (add (mem UHI countp) 1))
+ (if count (set (mem UHI countp) count))
+ xjsemantics))
+ (delayed_p xjsemantics)
+ (else (sequence ()
+ (set (reg h-cr 29) retaddr)
+ (set (aux-status32_l1) (reg h-status32))
+ (set (reg h-e1) 0)
+ (set pc (add (aux-int_vector_base) #x18))))
+ ))
+ xjsemantics)
+)
+
+; Define the list of conditions selectable with the 'Q' instruction field.
+; This is a separate macro so that we can use it both for the enum
+; values sued in a case form and the indices that are extracted from
+; the insn.
+(define-pmacro (Qvalues)
+ (
+ (al 0) (eq 1) (z 1) (ne 2) (nz 2) (pl 3) (p 3) (mi 4) (n 4)
+ (cs 5) (c 5) (lo 5) (cc 6) (nc 6) (hs 6) (vs 7) (v 7) (vc 8) (nv 8)
+ (gt 9) (ge 10) (lt 11) (le 12) (hi 13) (ls 14) (pnz 15)
+ ; add custom conditions here
+ )
+)
+
+; ??? optional arguments don't work for apply - need matching arg count.
+(define-pmacro (.car2 l2) (.apply (.pmacro (x y) x) l2))
+(define-pmacro (.cadr2 l2) (.apply (.pmacro (x y) y) l2))
+(define-pmacro (.car3 l3) (.apply (.pmacro (x y z) x) l3))
+(define-pmacro (.cdr3 l3) (.apply (.pmacro (x y z) (y z)) l3))
+(define-pmacro (.cadr3 l3) (.apply (.pmacro (x y z) y) l3))
+(define-pmacro (.caddr3 l3) (.apply (.pmacro (x y z) z) l3))
+
+(define-pmacro (upvalues xvalues)
+ (values (.map (.pmacro (l) ((.upcase (.car2 l)) (.cadr2 l))) (xvalues))))
+
+(define-enum
+ (name e-Qvalues)
+ (comment "enum values for Qcond to be used in case form")
+ (prefix COND_)
+ (upvalues Qvalues)
+)
+
+; evaluate f, then substitute elements in fa with elements in aa.
+(define-pmacro (.subst fa aa f) (.apply (.subst1 .pmacro fa f) aa))
+(define-pmacro (.subst1 pm a f) (pm a f))
+
+; evaluate f, then for each element in aal, substitute elements in fa with
+; elements from elemnet in aal.
+(define-pmacro (.substmap fa aal f)
+ (.subst (- .sstr) (- .str)
+ (.subst (- .substx) (- .subst)
+ (.substmap1 .map .pmacro fa aal f))))
+(define-pmacro (.substmap1 mp pm fa aal f)
+ (mp (pm (aa) (.substx fa aa f)) aal))
+
+;define delayed branch
+(define-pmacro (dDbranch di xxname misc-arg d0semantics d1semantics)
+ (.splice begin
+ (.unsplice
+ (.substmap
+ (delay-S delay-N xxxsemantics)
+ ( ("" (f-delay-N 0) (int-jump d0semantics))
+ (".d" (f-delay-N 1) (int-jumpd d1semantics)))
+ ; ??? should also use int-jump above, but that exposes delay bug.
+ (.splice di (.sstr xxname delay-S) (.unsplice misc-arg) xxxsemantics)
+ )
+ )
+ )
+)
+
+(define-pmacro (dQcond xname xprefix xccalias)
+ (define-hardware
+ (name xname)
+ (attrs VIRTUAL)
+ (type register BI (32))
+ (indices keyword ""
+ ; add un-prefixed empty key; prepend xprefix to the keys in
+ ; xccalias / Qvalues.
+ (.subst (xxprefix x.str) (xprefix .str)
+ (.splice ("" 0)
+ (.unsplice
+ (.map (.pmacro (l2) ((x.str xxprefix (.car2 l2)) (.cadr2 l2)))
+ (.splice (.unsplice xccalias) (.unsplice (Qvalues))))))))
+ (get (Q)
+ (case BI Q
+ ((COND_AL) 1)
+ ((COND_EQ) zbit)
+ ((COND_NE) (not zbit))
+ ((COND_PL) (not nbit))
+ ((COND_MI) nbit)
+ ((COND_CS) cbit)
+ ((COND_CC) (not cbit))
+ ((COND_VS) vbit)
+ ((COND_VC) (not vbit))
+ ((COND_GT) (and (not zbit) (eq nbit vbit)))
+ ((COND_GE) (eq nbit vbit))
+ ((COND_LT) (ne nbit vbit))
+ ((COND_LE) (or zbit (ne nbit vbit)))
+ ((COND_HI) (and (not cbit) (not zbit)))
+ ((COND_LS) (or cbit zbit))
+ ((COND_PNZ) (and (not nbit) (not zbit)))
+ ; add custom conditions here
+ (else (sequence BI () (invalid-expr) 1)))
+ )
+ (set (Q val) (nop))
+ )
+)
+
+; 'RA' is special; it is only valid for bra. However, a macro insn
+; doesn't work for bra, because cgen macro insns bypass relaxation.
+(dQcond h-Qcondb "" ((ra 0)))
+(dQcond h-Qcondj "" ())
+(dQcond h-Qcondi "." ())
+
+(define-hardware
+ (name h-uncondb)
+ (type immediate BI)
+ (values keyword "" (("" 0) (al 0) (ra 0)))
+)
+
+(define-hardware
+ (name h-uncondj)
+ (type immediate BI)
+ (values keyword "" (("" 0) (al 0)))
+)
+
+(define-hardware
+ (name h-uncondi)
+ (type immediate BI)
+ (values keyword "" (("" 0) (".al" 0)))
+)
+
+;; ??? Without the else clause in the case form, syntactically invalid C is
+;; generated - the expression ends then with <condition> ? <value> .
+(define-hardware
+ (name h-i2cond)
+ (attrs VIRTUAL)
+ (type register BI (3))
+ (indices keyword "COND2_" (("" 0) (al 0) (ra 0) (eq 1) (z 1) (ne 2) (nz 2)))
+ (get (i2)
+ (case BI i2
+ ((0) 1) ; COND2_AL
+ ((1) zbit) ; COND2_EQ
+ ((2) (not zbit)) ; COND2_NE
+ (else (error BI "unreachable - put in because of parser error"))
+ )
+ )
+ (set (i2 val) (nop))
+)
+
+(define-pmacro (m-i3cond)
+ ((gt 0) (ge 1) (lt 2) (le 3)
+ (hi 4) (cc 5) (nc 5) (hs 5)
+ (cs 6) (c 6) (lo 6) (ls 7))
+)
+
+(define-enum
+ (name e-i3cond)
+ (comment "enum values for i3cond to be used in case form")
+ (prefix COND3_)
+ (upvalues m-i3cond)
+)
+
+(define-hardware
+ (name h-i3cond)
+ (attrs VIRTUAL)
+ (type register BI (8))
+ (indices keyword "COND3_" (m-i3cond))
+ (get (i3)
+ (case BI i3
+ ((COND3_CS) cbit)
+ ((COND3_CC) (not cbit))
+ ((COND3_GT) (and (not zbit) (eq nbit vbit)))
+ ((COND3_GE) (eq nbit vbit))
+ ((COND3_LT) (ne nbit vbit))
+ ((COND3_LE) (or zbit (ne nbit vbit)))
+ ((COND3_HI) (and (not cbit) (not zbit)))
+ ((COND3_LS) (or cbit zbit))
+ (else (error BI "unreachable - put in because of parser error"))
+ )
+ )
+ (set (i3 val) (nop))
+)
+
+(define-pmacro (m-brcond)
+ ((req 0) (rne 1) (rlt 2) (rge 3) (rlo 4) (rhs 5) (bit0 14) (bit1 15))
+)
+
+(define-enum
+ (name e-brcond)
+ (comment "enum values for brcond to be used in case form")
+ (prefix CONDBR_)
+ (upvalues m-brcond)
+)
+
+(define-hardware
+ (name h-delay)
+ (type immediate (UINT 1))
+ (values keyword "" (("" 0) (".d" 1)))
+)
+
+(define-hardware
+ (name h-uflags)
+ (type immediate (UINT 1))
+ (values keyword "" (("" 0) (".f" 1)))
+)
+
+; implicit 0
+(define-hardware
+ (name h-nil)
+ (type immediate (UINT 1))
+ (values keyword "" (("" 0)))
+)
+
+; for cmp / rcmp / tst / btst: always update flags, no syntactical suffix.
+(define-hardware
+ (name h-auflags)
+ (type immediate (UINT 1))
+ (values keyword "" (("" 1)))
+)
+
+; for cmp / rcmp / tst / btst: always update flags, .f optional
+(define-hardware
+ (name h-aufflags)
+ (type immediate (UINT 1))
+ (values keyword "" ((".f" 1) ("" 1)))
+)
+
+(define-hardware
+ (name h-Di)
+ (type immediate (UINT 1))
+ (values keyword "" (("" 0) (".di" 1)))
+)
+
+(define-hardware
+ (name h-insn16)
+ (type immediate BI)
+ (values keyword "" ((_s 0) ("" 0)))
+)
+
+(define-hardware
+ (name h-insn32)
+ (type immediate BI)
+ (values keyword "" (("" 0) (_l 0)))
+)
+
+(define-hardware
+ (name h-_aw)
+ (type immediate BI)
+ (values keyword "" ((.a 0) (.aw 0)))
+)
+
+(define-pmacro (cr-values prefix ilink-values)
+ (.splice
+ (.unsplice prefix)
+ (gp 26) (fp 27) (sp 28) (blink 31) (mlo 57) (mmid 58) (mhi 59)
+ (lp_count 60) (pcl 63)
+ (.unsplice ilink-values)
+ ; r0 .. r60
+ (.unsplice (.map (.pmacro (n) ((.str "r" n) n)) (.iota 29)))
+ (.unsplice (.map (.pmacro (n) ((.str "r" n) n)) (.iota 30 31))))
+)
+
+(define-keyword
+ (name cr-names)
+ (print-name h-cr)
+ (prefix "")
+ (cr-values (values) ((ilink1 29) (ilink2 30) (r29 29) (r30 30)))
+)
+
+; ??? can't actually use this in define-hardware because that results
+; in linebreaks in a #define preprocessor directive.
+(define-pmacro (get-limm offset)
+ (sequence SI ((HI high) (HI low))
+ (set high (mem HI (add pc offset)))
+ (set low (mem HI (add pc (add offset 2))))
+ (or (sll (zext SI high) 16) (zext SI low))
+ )
+)
+
+; ??? This doesn't work because the 'mem' rtx requires a 'pc' symbol to
+; be in scope.
+;(define-hardware
+; (name h-limm)
+; (comment "long immediate")
+; (attrs VIRTUAL)
+; (type register SI (5))
+; (get (offset)
+; (or
+; (sll (zext SI (mem UHI (add (reg h-pc) offset))) 16)
+; (zext SI (mem UHI (add (reg h-pc) (add offset 2))))))
+; (set (offset newval) (nop))
+;)
+
+; ??? (reg h-pc) gives the wrong result when read inside of a pbb.
+(define-pmacro (set-pcl!) (set (raw-reg h-cr 63) (and (c-code SI "pc") -4)))
+
+(define-hardware
+ (name h-cr)
+ (comment "core registers")
+ (type register SI (64))
+ (indices extern-keyword cr-names)
+ (get (index)
+ (case SI index
+ ((61) (invalid-expr))
+ ; ??? Since memory can't be read from a define-hardware, we are
+ ; dependent on the semantic snippets in limmh / limmB / limmBC
+ ; to supply the long immediate value in reg 62.
+ ;((62) (reg h-limm 4))
+ ;((63) (and -4 (reg h-pc))) ; current insn address, made aligned
+ (else (raw-reg h-cr index))))
+ (set (index newval)
+ (case index
+ ((62) (nop))
+ ((61 63) (invalid-insn))
+ (else (set (raw-reg h-cr index) newval))))
+)
+
+; for 16 bit opcodes, normal operands can only access 8 registers.
+(define-hardware
+ (name h-cr16)
+ (comment "core registers - for 16 bit opcode access")
+ (attrs VIRTUAL)
+ (type register SI (8))
+ (indices keyword "r"
+ (.map (.pmacro (n m) ((.str n) m))
+ (.splice (.unsplice (.iota 4)) (.unsplice (.iota 4 12)))
+ (.iota 8)))
+ (get (index)
+ (case SI index
+ ((0 1 2 3) (raw-reg h-cr index))
+ (else (raw-reg h-cr (add index 8)))))
+ (set (index newval)
+ (case index
+ ((0 1 2 3) (set (raw-reg h-cr index) newval))
+ (else (set (raw-reg h-cr (add index 8)) newval))))
+)
+
+; ; for 16 bit opcodes, we need a different offset to fetch long immediates.
+; (define-hardware
+; (name h-hr)
+; (comment "core registers - for 16 bit opcode high register access")
+; (attrs VIRTUAL)
+; (type register SI (64))
+; (indices extern-keyword cr-names)
+; (get (index)
+; (case SI index
+; ((61) (invalid-expr))
+; ((62) (reg h-limm 2))
+; ((63) (and -4 (reg h-pc))) ; current insn address, made aligned
+; (else (raw-reg h-cr index))))
+; (set (index newval)
+; (case index
+; ((62) (nop))
+; ((61 63) (invalid-insn))
+; (else (set (raw-reg h-cr index) newval))))
+; )
+
+(define-hardware
+ (name h-r0)
+ (attrs VIRTUAL)
+ (comment "Core Register 0")
+ (type register SI (1))
+ (indices keyword "" ((r0 0)))
+ (get (index) (raw-reg h-cr 0))
+ (set (index newval) (set (raw-reg h-cr 0) newval))
+)
+
+(define-hardware
+ (name h-gp)
+ (attrs VIRTUAL)
+ (comment "global pointer")
+ (type register SI (1))
+ (indices keyword "" ((r26 0) (gp 0)))
+ (get (index) (raw-reg h-cr 26))
+ (set (index newval) (set (raw-reg h-cr 26) newval))
+)
+
+(define-hardware
+ (name h-sp)
+ (attrs VIRTUAL)
+ (comment "stack pointer")
+ (type register SI (1))
+ (indices keyword "" ((sp 0) (r28 0)))
+ (get (index) (raw-reg h-cr 28))
+ (set (index newval) (set (raw-reg h-cr 28) newval))
+)
+
+; This needs set-pcl! to be executed first. h-pc can't be used because it
+; gives the wrong result inside a pbb.
+(define-hardware
+ (name h-pcl)
+ (attrs VIRTUAL)
+ (comment "read program counter aligned")
+ (type register SI (1))
+ (indices keyword "" ((pcl 0) (r63 0)))
+ (get (index) (raw-reg h-cr 63))
+ (set (index newval) (invalid-expr))
+)
+
+(define-hardware
+ (name h-noilink)
+ (attrs VIRTUAL)
+ (comment "not ilink1 nor ilink2")
+ (type register SI (2))
+ (indices keyword "" (cr-values () ()))
+ (get (index) (raw-reg h-cr index))
+ (set (index newval) (set (raw-reg h-cr index) newval))
+)
+
+(define-hardware
+ (name h-ilinkx)
+ (attrs VIRTUAL)
+ (comment "ilink1 or ilink2")
+ (type register SI (2))
+ (indices keyword "" ((ilink1 29) (r29 29) (ilink2 30) (r30 30)))
+ (get (index) (raw-reg h-cr index))
+ (set (index newval) (set (raw-reg h-cr index) newval))
+)
+
+(define-hardware
+ (name h-r31)
+ (attrs VIRTUAL)
+ (comment "Core Register 0")
+ (type register SI (1))
+ (indices keyword "" ((blink 0) (r31 0)))
+ (get (index) (raw-reg h-cr 31))
+ (set (index newval) (set (raw-reg h-cr 31) newval))
+)
+
+; (define-pmacro (aux-status) (reg h-auxr 0)) etc.
+(.splice begin (.unsplice (.map
+ (.pmacro (xname xnum) (define-pmacro ((.sym aux- xname)) (reg h-auxr xnum)))
+ (status semaphore lp_start lp_end identity debug pc
+ status32_l1 status32_l2
+ mulhi
+ count0 control0 limit0 int_vector_base macmode irq_lv12
+ count1 control1 limit1 urq_lev irq_hint
+ eret erbta erstatus ecr efa
+ icause1 icause2 ienable itrigger
+ xpu bta bta_l1 bta_l2 irq_pulse_cancel irq_pending)
+ (0 1 2 3 4 5 6 11 12 18 33 34 35 37 65 67 256 257 258 512 513
+ 1024 1025 1026 1027 1028 1034 1035 1036 1037
+ 1040 1042 1043 1044 1045 1046)
+)))
+
+(define-hardware
+ (name h-auxr)
+ (comment "auxiliary registers")
+ (type register SI (64))
+ (indices extern-keyword cr-names)
+ (get (index)
+ (case SI index
+ ((0) (invalid-expr)) ; obsolete, should not be used by gcc
+ ; 6 is next_pc. This is only used from dlrsr, i.e. 32 bit opcode.
+ ; limmB / limmBC has already been evaluated.
+ ((6) (add (reg h-pc) 4))
+ ((10) ; status32 ; FIXME: read other bits.
+ (or (sll (zext SI lbit) 12) (or (sll (zext SI zbit) 11)
+ (or (sll (zext SI nbit) 10) (or (sll (zext SI cbit) 9)
+ (or (sll (zext SI vbit) 8) (or (sll (zext SI (reg h-e1)) 1)
+ (sll (zext SI (reg h-e2)) 2))))))))
+ ((#x21) ; aux_count0 == insn_count + (aux_limit0 - timer_expire)
+ (add (c-code SI "CPU_INSN_COUNT (current_cpu)")
+ (sub (raw-reg h-auxr #x23) (reg h-timer-expire))))
+ ((65) (or (sll (zext SI s1bit) 9) (sll (zext SI s2bit) 4)))
+ (else (raw-reg h-auxr index))))
+ (set (index newval)
+ (case index
+ ((0) (invalid-insn))
+ ((3) (sequence () (set (raw-reg h-auxr 3) newval)
+ (c-call "scache_flush_cpu")))
+ ((4 5 6 10 1027 1040 1041 1046) (nop))
+ ; handle [timer0] COUNT0, CONTROL0, LIMIT0
+ ( (#x21 #x22 #x23)
+ (sequence ()
+ (set (raw-reg h-auxr index) newval)
+ ; ??? This implementation does not actually support
+ ; differences of aux-limit0 and aux-count0 that exceed
+ ; or come close to 1<<31.
+ ; timer_expire := insn_count + (aux_limit0 - aux_count0)
+ (set (reg h-timer-expire)
+ (add (c-code SI "CPU_INSN_COUNT (current_cpu)")
+ (sub (raw-reg h-auxr #x23) (raw-reg h-auxr #x21))))))
+ ((65) (cond ((and newval 2) (set s1bit 0) (set s2bit 0))))
+ (else (set (raw-reg h-auxr index) newval)))
+ )
+)
+
+(define-hardware
+ (name h-status32)
+ (attrs VIRTUAL)
+ (comment "status32")
+ (type register SI (1))
+ (indices keyword "" (("status32" 0)))
+ (get (index) (reg h-auxr 10))
+ (set (index newval)
+ (sequence ()
+; (if (eq-attr (current-mach) ISARC700 TRUE)
+ (set lbit (and (srl newval 12) 1))
+;)
+ (set zbit (and (srl newval 11) 1))
+ (set nbit (and (srl newval 10) 1))
+ (set cbit (and (srl newval 9) 1))
+ (set vbit (and (srl newval 8) 1))
+ (set (reg h-e1) (and (srl newval 1) 1))
+ (set (reg h-e2) (and (srl newval 2) 1))
+ ; FIXME: set other bits.
+ )
+ )
+)
+
+(define-hardware
+ (name h-timer-expire)
+ (comment "used internally in simulator to speed up timer expiration check")
+ (type register SI (1))
+)
+(define-hardware
+ (name h-prof-offset)
+ (comment "offset to profile counters")
+ (type register SI (1))
+)
+(define-hardware
+ (name h-ne)
+ (type immediate BI)
+ (values keyword "" ((ne 0)))
+)
+
+(dnh h-pc "program counter" (PC PROFILE) (pc) () () ())
+
+(dnop Qcondb "Condition" () h-Qcondb f-cond-Q)
+(dnop Qcondj "Condition" () h-Qcondj f-cond-Q)
+(dnop Qcondi "Condition" () h-Qcondi f-cond-Q)
+(dnop uncondb "unconditional branch" () h-uncondb f-nil)
+(dnop uncondj "unconditional jump" () h-uncondj f-nil)
+(dnop uncondi "unconditional insn" () h-uncondi f-nil)
+(dnop i2cond "Condition" () h-i2cond f-cond-i2)
+(dnop i3cond "Condition" () h-i3cond f-cond-i3)
+(dnop delay_N "Delay slot exposed" () h-delay f-delay-N)
+(dnop _S "16 bit opcode" () h-insn16 f-nil)
+(dnop _L "32 bit opcode" () h-insn32 f-nil)
+(dnop F "update flags" () h-uflags f-F)
+(dnop F1 "always update flags" () h-auflags f-F)
+(dnop F1F "always update flags; .F allowed" () h-aufflags f-F)
+(dnop F0 "never update flags" () h-nil f-F)
+(dnop R_a "Core Register a" () h-cr16 f-op--a)
+(dnop RA "Core Register A" () h-cr f-op-A)
+(dnop R_b "Core Register b" () h-cr16 f-op--b)
+(dnop RB "Core Register B" () h-cr f-op-B)
+(dnop R_c "Core Register b" () h-cr16 f-op--c)
+(dnop RC "Core Register C" () h-cr f-op-C)
+;(dnop Rh "Core register h" () h-hr f-op-h)
+(dnop Rh "Core register h" () h-cr f-op-h)
+(dnop R0 "Core Register 0" () h-r0 f-nil)
+(dnop R31 "Core Register 31" () h-r31 f-nil)
+(dnop GP "Global Pointer" () h-gp f-nil)
+(dnop SP "Stack Pointer" () h-sp f-nil)
+(dnop PCL "read PC - aligned" () h-pcl f-nil)
+(dnop RA_0 "encode A as 0" () h-nil f-op-A)
+(dnop RB_0 "encode B as 0" () h-nil f-op-B)
+(dnop RC_ilink "inlink[01] as op C" () h-ilinkx f-op-Cj)
+(dnop RC_noilink "Core reg C, not ilink" () h-noilink f-op-Cj)
+(dnop NE "NE condition " () h-ne f-nil)
+(dnop U6 "6 bit unsigned immediate" () h-uint f-u6)
+(dnop U6x2 "6 bit unsigned immediate" () h-uint f-u6x2)
+(dnop u3 "3 bit unsigned immediate" () h-uint f-u3)
+(dnop u5 "5 bit unsigned immediate" () h-uint f-u5)
+(dnop u7 "7 bit unsigned immediate" () h-uint f-u7)
+(dnop u8 "8 bit unsigned immediate" () h-uint f-u8)
+(dnop s9 "8 bit signed immediate" () h-sint f-s9)
+(dnop s12 "12 bit signed immediate" () h-sint f-s12)
+(dnop s12x2 "12 bit signed immediate" () h-sint f-s12x2)
+(dnop u5x4 "5 bit uns imm times 4" () h-uint f-u5x4)
+(dnop sc_u5_ "5 bit uns imm times 4" () h-uint f-u5x4)
+(dnop sc_u5w "5 bit uns imm times 2" () h-uint f-u5x2)
+(dnop sc_u5b "5 bit uns imm times 1" () h-uint f-u5)
+(dnop u8x4 "8 bit uns imm times 4" () h-uint f-u8x4)
+(dnop s9x4 "9 bit sgn imm times 4" () h-uint f-s9x4)
+(dnop sc_s9_ "8 bit uns imm times 4" () h-uint f-s9x4)
+(dnop sc_s9w "8 bit uns imm times 2" () h-uint f-s9x2)
+(dnop sc_s9b "8 bit uns imm times 1" () h-uint f-s9x1)
+(dnop label7 "7 bit pc relative address" () h-iaddr f-rel7)
+(dnop label8 "8 bit pc relative address" () h-iaddr f-rel8)
+(dnop label9 "9 bit pc relative address" () h-iaddr f-rel9)
+(dnop label10 "10 bit pc relative address" () h-iaddr f-rel10)
+(dnop label13a "13 bit bl pc rel address" () h-iaddr f-rel13bl)
+(dnop label21 "21 bit pc relative address" () h-iaddr f-rel21)
+(dnop label21a "21 bit bl pc rel address" () h-iaddr f-rel21bl)
+(dnop label25 "25 bit pc relative address" () h-iaddr f-rel25)
+(dnop label25a "25 bit bl pc rel address" () h-iaddr f-rel25bl)
+
+(define-normal-insn-enum e-ra-rn
+ "Core Register A encodings"
+ () RA_R f-op-A (.map .str (.iota 64))
+)
+
+; process expansion of dd*i macros so that arguments are bound properly.
+(define-pmacro (dddgoi xxname xF xdstA xdstB xsrcB xsrcC xRA xRB
+ xscale xxxsemantics expansion)
+ (.subst
+ (xxF xxdstA xxdstB xxsrcB xxsrcC xxRA xxRB xxscale xxsemantics defpm)
+ (xF xdstA xdstB xsrcB xsrcC xRA xRB xscale xxxsemantics define-pmacro)
+ (defpm (xxname xop xformat xattrs xsemantics xfsemantics) expansion))
+)
+
+; ddgoi <name> <flag-syntax/encoding> <dsta-syntax> <dstb-syntax> <srcb-syntax> <RA-encode> <RB-encode> <semantics-expander>
+; define 'define general operations instruction' macro
+; this must be used before dnai / daiQ / x.str is defined to prevent
+; premature evaluation.
+(define-pmacro (ddgoi xxname xxF xxdstA xxdstB xxsrcB xxsrcC
+ xxRA xxRB xxsemantics)
+ (dddgoi xxname xxF xxdstA xxdstB xxsrcB xxsrcC xxRA xxRB "" xxsemantics
+ (begin (ddgoi_s12) (ddgoi_ccu6) (ddgoi_u6) (ddgoi_r_r) (ddgoi_cc)))
+)
+
+(define-pmacro (ddgoi_r_r)
+ (dnai ((x.str) xop "_L_r_r" xxdstA xxsrcC)
+ ((x.str) xop " register-register")
+ ((x.str) xop "$_L$" xxF xxdstA xxsrcB xxsrcC)
+ (+ (GO_BASE) GO_TYPE_R_R xformat xxF xxRB RC xxRA)
+ (splicelist (((LIMM BC)) xattrs))
+ (xxsemantics limmBC xsemantics xfsemantics xxRA RB RC))
+)
+
+(define-pmacro (ddgsoi_r_r)
+ (dnai ((x.str) xop "_L_r_r" xxdstA xxsrcC)
+ ((x.str) xop " register-register")
+ ((x.str) xop "$_L$" xxF xxdstA xxsrcB xxsrcC)
+ (+ (GO_BASE) GO_TYPE_R_R xformat xxF xxRB RC xxRA)
+ (splicelist (((LIMM C)) xattrs))
+ (xxsemantics limmC xsemantics xfsemantics xxRA RB RC))
+)
+
+(define-pmacro (ddgoi_u6)
+ (dnai ((x.str) xop "_L_u6" xxdstA)
+ ((x.str) xop " with unsigned 6 bit immediate")
+ ((x.str) xop "$_L$" xxF xxdstA xxsrcB "$U6")
+ (+ (GO_BASE) GO_TYPE_U6 xformat xxF xxRB U6 xxRA)
+ (splicelist (((LIMM B)) xattrs))
+ (xxsemantics limmB xsemantics xfsemantics xxRA RB U6))
+)
+
+(define-pmacro (ddgsoi_u6) (ddgsoi_u6_1 "$U6"))
+(define-pmacro (ddgsoi_u6_1 u6-syntax)
+ (dnai ((x.str) xop "_L_u6" xxdstA)
+ ((x.str) xop " with unsigned 6 bit immediate")
+ ((x.str) xop "$_L$" xxF xxdstA xxsrcB u6-syntax)
+ (+ (GO_BASE) GO_TYPE_U6 xformat xxF xxRB U6 xxRA)
+ (splicelist (((LIMM B)) xattrs))
+ (xxsemantics limmB xsemantics xfsemantics xxRA RB U6))
+)
+
+;??? default arguments are broken, otherwise we could use:
+;(define-pmacro (ddgoi_s12 (s12-syntax . "$s12")) ...
+(define-pmacro (ddgoi_s12) (ddgoi_s12_1 "$s12"))
+(define-pmacro (ddgoi_s12_1 s12-syntax)
+ (dnai ((x.str) xop "_L_s12" xxdstA)
+ ((x.str) xop " with signed 12 bit immediate " xxscale)
+ ((x.str) xop "$_L$" xxF xxdstB xxsrcB s12-syntax xxscale)
+ (+ (GO_BASE) GO_TYPE_S12 xformat xxF xxRB ((x.sym) s12 xxscale))
+ (splicelist (((LIMM B)) xattrs))
+ (xxsemantics limmB xsemantics xfsemantics RB RB ((x.sym) s12 xxscale)))
+)
+
+(define-pmacro (ddgoi_cc)
+ (daiQ ((x.str) xop "_cc" xxdstA xxsrcC)
+ ((x.str) xop " conditional register")
+ ((x.str) xop "$Qcondi$" xxF xxdstB xxsrcB xxsrcC)
+ (+ (GO_BASE) GO_TYPE_CC GO_CC_REG xformat xxF xxRB RC Qcondi)
+ (splicelist (((LIMM BC)) xattrs))
+ limmBC (xxsemantics nop xsemantics xfsemantics RB RB RC))
+)
+
+(define-pmacro (ddgoi_ccu6)
+ (daiQ ((x.str) xop "_ccu6" xxdstA)
+ ((x.str) xop " conditional with 6 bit immediate " xxscale)
+ ((x.str) xop "$Qcondi$" xxF xxdstB xxsrcB "$U6" xxscale)
+ (+ (GO_BASE) GO_TYPE_CC GO_CC_U6 xformat xxF xxRB ((x.sym) U6 xxscale)
+ Qcondi)
+ (splicelist (((LIMM B)) xattrs))
+ limmB (xxsemantics nop xsemantics xfsemantics RB RB ((x.sym) U6 xxscale)))
+)
+
+; like above, but we can't use daiQ because there is an 'else' action to do.
+(define-pmacro (ddlpcc_ccu6)
+ (define-insn
+ (name "lpcc_ccu6")
+ (comment "lpcc conditional with 6 bit immediate")
+ (attrs (LIMM B))
+ (syntax ((x.str) "lp$Qcondi$" xxF xxdstB xxsrcB "$U6" xxscale))
+ (format (+ OPM_GO GO_TYPE_CC GO_CC_U6 xformat xxF xxRB ((x.sym) U6 xxscale)
+ Qcondi))
+ (semantics (sequence ()
+ (limmB)
+ (if Qcondb
+ (xxsemantics nop xsemantics xfsemantics RB RB ((x.sym) U6 xxscale))
+ (int-jump (set pc (add (and WI pc (const -4)) ((x.sym) U6 xxscale)))))
+ ))
+ )
+)
+
+; dgoi: define general operations instruction
+(ddgoi dgoi F " $RA," " $RB," "$RB," "$RC" RA RB fsemantics)
+; dgmov: define general move instruction
+(dddgoi dgmov F " " " " "$RB," "$RC" RA_0 RB "" esemantics
+ (.subst (limmB B limmBC BC) (nop none limmC C)
+ (begin (ddgoi_s12) (ddgoi_ccu6) (ddgoi_u6) (ddgoi_r_r) (ddgoi_cc)))
+)
+; dg2oi - define general 2-operand operations instruction
+(ddgoi dg2oi F1 " " " " "$RB," "$RC" RA_0 RB esemantics)
+; dsfi1 - define special format instruction, one operand
+(ddgoi dsfi F0 " " " " "" "$RC" RA_0 RB_0 esemantics)
+; dji - define jump instruction
+(dddgoi dji F0 " " " " "" "[-]" RA_0 RB_0 "" esemantics
+ (begin (ddgoi_s12) (ddgoi_ccu6) (ddgoi_u6)))
+; djri - define jump instruction / with register/limm field
+(dddgoi djri F0 " " " " "" "[$RC_noilink]" RA_0 RB_0 "" esemantics
+ (.subst (RC) (RC_noilink)
+ (begin (ddgoi_r_r) (ddgoi_cc))))
+; djdi - define jump instruction with .d suffix
+(ddgoi djdi F0 ".d " ".d " "" "[$RC]" RA_0 RB_0 esemantics)
+; d_divaw: divaw instruction
+(ddgoi d_divaw F0 " $RA," " $RB," "$RB," "$RC" RA RB fsemantics)
+; define j with ilink[01] destination
+(dddgoi djilink F1F " " " " "" "[$RC_ilink]" RA_0 RB_0 "" esemantics
+ (.subst (RC) (RC_ilink) ((ddgoi_r_r) (ddgoi_cc))))
+; dlpcci: define lpcc insn
+(dddgoi dlpcci F0 " " " " "" - RA_0 RB_0 x2 esemantics
+ (begin (ddgoi_s12) (ddlpcc_ccu6)))
+; dgsoi: define general single operand instruction
+(dddgoi dgsoi F " " " $RB," "$RB," "$RC" RB GO_OP_SOP "" fsemantics
+ (begin (ddgsoi_r_r) (ddgsoi_u6)))
+; variant of same for ex insn
+(dddgoi dex EXDi " " " $RB," "$RB," "$RC" RB GO_OP_SOP "" fsemantics
+ (begin (ddgoi_r_r) (ddgoi_u6)))
+(dddgoi dbegin - - - - - - - - - (begin))
+
+(define-pmacro (ddjsi xxname xxdelay)
+ (define-pmacro (xxname xop xformat xattrs xsemantics xdispose)
+ (
+ (dsai ((x.str) xop "_s" xxdelay) ((x.str) xop "_s" xxdelay)
+ ((x.str) xop "$_S" xxdelay " [$R_b]")
+ (+ OPM_SGO I16_GO_SOP xformat R_b)
+ xattrs
+ (esemantics-f-0 nop xsemantics xdispose R_b R_b R_b))
+ )
+ )
+)
+
+(ddjsi djsi "")
+(ddjsi djsid ".d")
+
+(define-pmacro (ddjsblink xxname xxsuffix jcond)
+ (define-pmacro (xxname xop xformat xattrs xsemantics xdispose)
+ (
+ (dsai ((x.str) xop "_s" xxsuffix) ((x.str) xop "_s" xxsuffix)
+ ((x.str) xop xxsuffix " [$R31]")
+ (+ OPM_SGO I16_GO_SOP I16_GO_SOP_ZOP xformat)
+ xattrs
+ (esemantics-f-0 nop (if jcond xsemantics) xdispose R31 R31 R31))
+ )
+ )
+)
+
+(ddjsblink djsblink "$_S" 1)
+(ddjsblink djsblinkd "$_S.d" 1)
+(ddjsblink djsblinkeq "eq$_S" (ne zbit 0))
+(ddjsblink djsblinkne "ne$_S" (eq zbit 0))
+
+(dddgoi dlrsr F0 " " " " "$RB," "[$RC]" RA_0 RB "" esemantics
+ (begin (ddgoi_r_r) (ddgoi_s12_1 "[$s12]") (ddgsoi_u6_1 "[$U6]")))
+
+; now that we are done with ddgoi, we can define x.str
+(define-pmacro (x.str) .str)
+(define-pmacro (x.sym) .sym)
+
+; redefine this when processing extension instructions
+(define-pmacro (GO_BASE) OPM_GO)
+
+; Same as dni but leave out timing.
+; Also, xattrs is moved after xformat to make it easier to
+; mix-and-match with dgoi / dmfi
+; dnai - define-normal-arc-insn
+
+(define-pmacro (dnai xname xcomment xsyntax xformat xattrs xsemantics)
+ (define-insn
+ (name xname)
+ (comment xcomment)
+ (.splice attrs (.unsplice xattrs))
+ (syntax xsyntax)
+ (format xformat)
+ (semantics xsemantics)
+ )
+)
+
+; ??? FIXME: When mixing 16 and 32 bit instructions straightforwardly, an
+; invalid decoder is generated, see:
+; http://www.sourceware.org/ml/cgen/2007-q1/msg00047.html
+; Therefore, we have to lie to cgen, pretending that the 16 bit opcode insns
+; have a 32 bit opcode.
+; we leave the value of f-dummy undefined, so that the disassembler will
+; find the 16 bit insn in any 32 bit word that starts with it.
+(dnf f-dummy "dummy field" () 16 16)
+(dnop dummy-op "(first 16 bit of) next insn" () h-uint f-dummy)
+; define short arc instruction
+(define-pmacro (dsai xname xcomment xsyntax xformat xattrs xsemantics)
+ (dnai xname xcomment xsyntax
+ (.splice (.unsplice xformat) dummy-op)
+ (.splice (.unsplice xattrs) SHORT_P)
+ xsemantics
+ )
+)
+
+; daiQ - define-arc-insn-with-Q-condition-field
+(define-pmacro (daiQ xname xcomment xsyntax xformat xattrs limmsem xsemantics)
+ (define-insn
+ (name xname)
+ (comment xcomment)
+ (.splice attrs (.unsplice xattrs))
+ (syntax xsyntax)
+ (format xformat)
+ (semantics (sequence () (limmsem) (if Qcondb xsemantics)))
+ )
+)
+
+; Fetch long immediate.
+(define-pmacro (fetch-limm! offset)
+ (sequence ((HI high) (HI low))
+ (set high (mem HI (add pc offset)))
+ (set low (mem HI (add pc (add offset 2))))
+ (set (raw-reg h-cr 62) (or (sll (zext SI high) 16) (zext SI low)))
+ )
+)
+
+(define-pmacro (limmB)
+ (sequence ()
+ (if (eq f-op-B 62) (fetch-limm! 4))
+ (if (eq f-op-B 63) (set-pcl!))
+ )
+)
+
+(define-pmacro (limmBC)
+ (sequence ()
+ (if (or (eq f-op-B 62) (eq f-op-C 62)) (fetch-limm! 4))
+ (if (or (eq f-op-B 63) (eq f-op-C 63)) (set-pcl!))
+ )
+)
+
+(define-pmacro (limmC)
+ (sequence ()
+ (if (eq f-op-C 62) (fetch-limm! 4))
+ (if (eq f-op-C 63) (set-pcl!))
+ )
+)
+
+(define-pmacro (limmh)
+ (sequence ()
+ (if (eq f-op-h 62) (fetch-limm! 2))
+ (if (eq f-op-h 63) (set-pcl!))
+ )
+)
+
+; semantics for dgoi: xsemantics specifies how to calculate the result
+; from xB and xC; xfsemantics specifies flag setting semantics that
+; are in effect when the F bit is set. The result is assigned to xA.
+(define-pmacro (fsemantics limmsem xsemantics xfsemantics xA xB xC)
+ (.subst (A B C) (xA xB xC)
+ (sequence ((SI result) (BI cur_s1bit) (BI cur_s2bit))
+ (limmsem)
+ (set result xsemantics)
+ (if F xfsemantics)
+ (set xA result)
+ )
+ )
+)
+
+; semantics for dgmov, dg2oi:
+; evaluate the xdispose argument, passing the other arguments -
+; except xA, which is ignored.
+(define-pmacro (esemantics limmsem xsemantics xdispose xA xB xC)
+ (xdispose limmsem xsemantics F xB xC))
+
+; likewise, but tpass const0 for F.
+(define-pmacro (esemantics-f-0 limmsem xsemantics xdispose xA xB xC)
+ (xdispose limmsem xsemantics (const 0) xB xC))
+
+(define-pmacro (nfsemantics limmsem xsemantics xA xB xC)
+ (sequence ((SI result) (SI B) (SI C))
+ (limmsem)
+ (set B xB)
+ (set C xC)
+ (set xA xsemantics)
+ )
+)
+
+(define-pmacro (flagNZ)
+ (sequence ()
+ (set nbit (nflag result))
+ (set zbit (zflag result))
+ )
+)
+
+(define-pmacro (cmpsemantics limmsem xsemantics xF xB xC)
+ (sequence ((SI result) (DI tmp) (DI B) (DI C))
+ (limmsem)
+ (set B (ext DI xB))
+ (set C (ext DI xC))
+ (set tmp xsemantics)
+ (set result (subword SI tmp 1))
+ (flagNZ)
+ (set vbit (ne (nflag result) (nflag tmp)))
+ (set B (zext DI xB))
+ (set C (zext DI xC))
+ (set tmp xsemantics)
+ (set cbit (nflag tmp))
+ )
+)
+
+(define-pmacro (tstsemantics limmsem xsemantics xF xB xC)
+ (sequence ((SI result) (SI B) (SI C))
+ (limmsem)
+ (set B xB)
+ (set C xC)
+ (set result xsemantics)
+ (flagNZ)
+ )
+)
+
+(define-pmacro (movsemantics limmsem xsemantics xF xB xC)
+ (sequence ((SI result))
+ (limmsem)
+ (set result xC)
+ (set xB result)
+ (if (gt SI xF 0) (flagNZ))
+ )
+)
+
+; for special format instructions
+(define-pmacro (sfisemantics limmsem xsemantics xF xB xC)
+ (sequence ((SI result))
+ (limmsem)
+ (.subst (F B C) (xF xB xC) xsemantics)
+ )
+)
+
+; For jumps
+(define-pmacro (jsemantics limmsem xsemantics xF xB xC)
+ (int-jump (sequence ((SI result))
+ (limmsem)
+ (.subst (F B C) (xF xB xC) xsemantics)
+ ))
+)
+
+(define-pmacro (jdsemantics limmsem xsemantics xF xB xC)
+ (int-jumpd (sequence ((SI result))
+ (limmsem)
+ (.subst (F B C) (xF xB xC) xsemantics)
+ ))
+)
+
+(dnf f-opm "major opcode" () 0 5)
+
+(define-normal-insn-enum op-maj
+ "major opcode"
+ () OPM_ f-opm
+ (
+ (B 0) (BLR 1) (LD_S9 2) (ST_S9 3) (GO 4)
+ (X05 5) (X06 6) (X07 7)
+ (SLDADDR 12) (SADDSUBSHI 13) (SMOVCMPADDH 14) (SGO 15)
+ (LDO_S 16) (LDOB_S 17) (LDOW_S 18) (LDOWX_S 19)
+ (STO_S 20) (STOB_S 21) (STOW_S 22)
+ (SSHSUBBIMM 23)
+ (SP 24) (GP 25) (LDPCREL 26) (SMOVU8 27) (SADDCMPU7 28)
+ (BR_S 29) (B_S 30) (BL_S 31)
+ (PSEUDO 32)
+ )
+)
+
+(dnf f-go-type "general operations type" () 8 2)
+(dnf f-go-cc-type "general operations conditional subtype" () 26 1)
+;(d2nf f-go-cc-type "general operations conditional subtype" () 10 1)
+
+(dnf f-go-op "general operations sub-opcode" () 10 6)
+
+(define-normal-insn-enum go-type
+ "general operations type"
+ () GO_TYPE_ f-go-type
+ ((R_R 0) (U6 1) (S12 2) (CC 3))
+)
+
+(define-normal-insn-enum go-cc-type
+ "general operations conditional subtype"
+ () GO_CC_ f-go-cc-type
+ ((REG 0) (U6 1))
+)
+
+(define-normal-insn-enum go-op
+ "general operations type"
+ () GO_OP_ f-go-op
+ (
+ (ADD 0) (ADC 1) (SUB 2) (SBC 3) (AND 4) (OR 5) (BIC 6) (XOR 7)
+ (MAX 8) (MIN 9) (MOV 10) (TST 11) (CMP 12) (RCMP 13) (RSUB 14) (BSET 15)
+ (BCLR 16) (BTST 17) (BXOR 18) (BMSK 19) (ADD1 20) (ADD2 21) (ADD3 22)
+ (SUB1 23) (SUB2 24) (SUB3 25) (MPY 26) (MPYH 27) (MPYHU 28) (MPYU 29)
+ (RES30 30) (RES31 31)
+ (J 32) (J_D 33) (JL 34) (JL_D 35) (LP 40) (FLAG 41) (LR 42) (SR 43) (SOP 47)
+ )
+)
+
+(define-normal-insn-enum go-sop
+ "general single-operand operations type"
+ () GO_OP_SOP_ f-op-A
+ (
+ (ASL 0) (ASR 1) (LSR 2) (ROR 3) (RRC 4) (SEXB 5) (SEXW 6) (EXTB 7)
+ (EXTW 8) (ABS 9) (NOT 10) (RLC 11) (EX 12) (ZOP 63)
+ (PSEUDO 62)
+ )
+)
+
+(dnf f-i16-43 "short ld add register type" () 11 2)
+
+(define-normal-insn-enum i16ldaddr-type
+ "short add / sub immediate type"
+ () I16_LDADDR_ f-i16-43
+ ((LD 0) (LDB 1) (LDW 2) (ADD 3))
+)
+
+(define-normal-insn-enum i16addsubshi-type
+ "short add / sub immediate type"
+ () I16_ADDSUBSHI_ f-i16-43
+ ((ADD 0) (SUB 1) (ASL 2) (ASR 3))
+)
+
+(define-normal-insn-enum i16movcmpaddh-type
+ "short mov / cmp / add with high register type"
+ () I16_MOVCMPADDH_ f-i16-43
+ ((ADD 0) (MOVbh 1) (CMP 2) (MOVhb 3))
+)
+
+(dnf f-i16-go "short general operations type" () 11 5)
+
+(define-normal-insn-enum i16go-type
+ "short general operations"
+ () I16_GO_ f-i16-go
+ ((SOP 0) (SUB 2) (AND 4) (OR 5) (BIC 6) (XOR 7)
+ (TST 11) (MUL64 12) (SEXB 13) (SEXW 14)
+ (EXTB 15) (EXTW 16) (ABS 17) (NOT 18) (NEG 19) (ADD1 20) (ADD2 21) (ADD3 22)
+ (ASLM 24) (LSRM 25) (ASRM 26) (ASL 27) (ASR 28) (LSR 29) (TRAP 30) (BRK 31))
+)
+
+(define-normal-insn-enum i16go-sop-type
+ "short general operations single operand"
+ () I16_GO_SOP_ f-op--c
+ ((J 0) (J_D 1) (JL 2) (JL_D 3) (SUB_NE 6) (ZOP 7))
+)
+
+(define-normal-insn-enum i16go-zop-type
+ "short general operations single operand"
+ () I16_GO_ZOP_ f-op--b
+ ((NOP 0) (UNIMP 1) (JEQ 4) (JNE 5) (J 6) (J_D 7))
+)
+
+(define-normal-insn-enum i16sp-type
+ "sp based insn type"
+ () I16_SP_ f-op--c
+ ((LD 0) (LDB 1) (ST 2) (STB 3) (ADD 4) (ADDSUB 5) (POP 6) (PUSH 7))
+)
+
+(define-normal-insn-enum i16addsub_spsp-type
+ "sp based 1op insn type"
+ () I16_SP_ADDSUB_ f-op--b
+ ((ADD 0) (SUB 1))
+)
+
+(dnf f-i16-gp-type "gp-relative insn type" () 5 2)
+
+(define-normal-insn-enum i16gp-type
+ "gp-relative insn type"
+ () I16_GP_ f-i16-gp-type
+ ((LD 0) (LDB 1) (LDW 2) (ADD 3))
+)
+
+
+(dnf f-i16addcmpu7-type "short add / cmp immediate type" () 8 1)
+
+(define-normal-insn-enum i16addcmpu7-type
+ "short add / cmp immediate type"
+ () I16_ADDCMPU7_ f-i16addcmpu7-type
+ ((ADD 0) (CMP 1))
+)
+
+(define-pmacro (d16addr xop xformat xattrs xsemantics xfsemantics)
+ (
+ (dsai (.str xop "_s_abc") (.str xop "_s register - register")
+ (.str xop "$_S $R_a,$R_b,$R_c")
+ (+ OPM_SLDADDR xformat R_b R_c R_a)
+ xattrs
+ (nfsemantics nop xsemantics R_a R_b R_c)
+ )
+ )
+)
+
+(define-pmacro (d16addsubshi xop xformat xattrs xsemantics xfsemantics)
+ (
+ (dsai (.str xop "_s_cbu3") (.str xop "_s reg-reg-u3")
+ (.str xop "$_S $R_c,$R_b,$u3")
+ (+ OPM_SADDSUBSHI xformat R_b R_c u3)
+ xattrs
+ (nfsemantics nop xsemantics R_c R_b u3)
+ )
+ )
+)
+
+(define-pmacro (d16addh xop xformat xattrs xsemantics xfsemantics)
+ (
+ (dsai (.str xop "_s_mcah") (.str xop "_s high reg")
+ (.str xop "$_S $R_b,$R_b,$Rh")
+ (+ OPM_SMOVCMPADDH xformat R_b Rh)
+ (.splice (LIMM h) (.unsplice xattrs))
+ (nfsemantics limmh xsemantics R_b R_b Rh)
+ )
+ )
+)
+
+(define-pmacro (d16movcmph xop xformat xattrs xsemantics xdispose)
+ (
+ (dsai (.str xop "_s_mcah") (.str xop "_s high reg")
+ (.str xop "$_S $R_b,$Rh")
+ (+ OPM_SMOVCMPADDH xformat R_b Rh)
+ (.splice (LIMM h) (.unsplice xattrs))
+ (xdispose limmh xsemantics -1 R_b Rh)
+ )
+ )
+)
+
+; this differs from d16movcmph in that registers are swapped,
+; and there is no Rh immediate
+(define-pmacro (d16movhb xop xformat xattrs xsemantics xdispose)
+ (
+ (dsai (.str xop "_s_mcahb") (.str xop "_s high reg")
+ (.str xop "$_S $Rh,$R_b")
+ (+ OPM_SMOVCMPADDH xformat R_b Rh)
+ xattrs
+ (xdispose nop xsemantics -1 Rh R_b)
+ )
+ )
+)
+
+(define-pmacro (d16goi xop xformat xattrs xsemantics xfsemantics)
+ (
+ (dsai (.str xformat "_s_go") (.str xop "_s b,b,c")
+ (.str xop "$_S $R_b,$R_b,$R_c")
+ (+ OPM_SGO xformat R_b R_c)
+ xattrs
+ (nfsemantics nop xsemantics R_b R_b R_c)
+ )
+ )
+)
+
+(define-pmacro (d16g2oi xop xformat xattrs xsemantics xdispose)
+ (
+ (dsai (.str xop "_s_go") (.str xop "_s b,c")
+ (.str xop "$_S $R_b,$R_c")
+ (+ OPM_SGO xformat R_b R_c)
+ xattrs
+ (xdispose nop xsemantics - R_b R_c)
+ )
+ )
+)
+
+(define-pmacro (dsubs_ne xop xformat xattrs xsemantics xfsemantics)
+ (
+ (dsai (.str xop "_s_go_sub_ne") (.str xop "_s.ne b,b,b")
+ (.str xop "$_S $NE$R_b,$R_b,$R_b")
+ (+ OPM_SGO I16_GO_SOP xformat R_b)
+ xattrs
+ (if (eq zbit 0) (set R_b 0))
+ )
+ )
+)
+
+(define-normal-insn-enum i16shsubbimm
+ "shift / sub / bit immediate short insn w/ u5 type"
+ () I16_SHSUBBIMM_ f-op--c
+ ((ASL 0) (LSR 1) (ASR 2) (SUB 3) (BSET 4) (BCLR 5) (BMSK 6) (BTST 7))
+)
+
+(define-pmacro (d16shsubbimm xop xformat xattrs xsemantics xfsemantics)
+ (
+ (dsai (.str xop "_s_ssb") (.str xop "_s b,b,u5")
+ (.str xop "$_S $R_b,$R_b,$u5")
+ (+ OPM_SSHSUBBIMM R_b xformat u5)
+ xattrs
+ (nfsemantics nop xsemantics R_b R_b u5)
+ )
+ )
+)
+
+(define-pmacro (d16btst xop xformat xattrs xsemantics xdispose)
+ (
+ (dsai (.str xop "_s_ssb") (.str xop "_s b,u5")
+ (.str xop "$_S $R_b,$u5")
+ (+ OPM_SSHSUBBIMM R_b xformat u5)
+ xattrs
+ (xdispose nop xsemantics -1 R_b u5)
+ )
+ )
+)
+
+(define-pmacro (d16add-b-sp xop xformat xattrs xsemantics xfsemantics)
+ (
+ (dsai (.str xop "_s_absp") (.str xop "_s b,sp,u5x4")
+ (.str xop "$_S $R_b,$SP,$u5x4")
+ (+ OPM_SP R_b xformat u5x4)
+ xattrs
+ (nfsemantics nop xsemantics R_b SP u5x4)
+ )
+ )
+)
+
+(define-pmacro (d16addsub-sp-sp xop xformat xattrs xsemantics xfsemantics)
+ (
+ (dsai (.str xop "_s_asspsp") (.str xop "_s sp,sp,u5x4")
+ (.str xop "$_S $SP,$SP,$u5x4")
+ (+ OPM_SP I16_SP_ADDSUB xformat u5x4)
+ xattrs
+ (nfsemantics nop xsemantics SP SP u5x4)
+ )
+ )
+)
+
+(define-pmacro (d16gp_add xop xformat xattrs xsemantics xfsemantics)
+ (
+ (dsai (.str xop "_s_gp") (.str xop "_s r0,gp,s9x4")
+ (.str xop "$_S $R0,$GP,$s9x4")
+ (+ OPM_GP xformat s9x4)
+ xattrs
+ (nfsemantics nop xsemantics R0 GP s9x4)
+ )
+ )
+)
+
+(define-pmacro (d16movu8 xop xformat xattrs xsemantics xdispose)
+ (
+ (dsai (.str xop "_s_r_u7") (.str xop " register - 8 bit immediate")
+ (.str xop "$_S $R_b,$u7")
+ (+ xformat R_b u8)
+ xattrs
+ (xdispose nop xsemantics -1 R_b u8)
+ )
+ )
+)
+
+(define-pmacro (d16addu7 xop xformat xattrs xsemantics xfsemantics)
+ (
+ (dsai (.str xop "_s_r_u7") (.str xop " register - 7 bit immediate")
+ (.str xop "$_S $R_b,$R_b,$u7")
+ (+ OPM_SADDCMPU7 xformat R_b u7)
+ xattrs
+ (nfsemantics nop xsemantics R_b R_b u7)
+ )
+ )
+)
+
+(define-pmacro (d16cmpu7 xop xformat xattrs xsemantics xdispose)
+ (
+ (dsai (.str xop "_s_r_u7") (.str xop " register - 7 bit immediate")
+ (.str xop "$_S $R_b,$u7")
+ (+ OPM_SADDCMPU7 xformat R_b u7)
+ xattrs
+ (xdispose nop xsemantics -1 R_b u7)
+ )
+ )
+)
+
+(define-pmacro (splicelist listlist)
+ (.subst (x sp) (xx .splice)
+ (.splice sp (.unsplice (.subst (x un) (xx .unsplice)
+ (.map (.pmacro (e) (un e)) listlist)))))
+)
+; dmfi - define multi-format insn
+; xformlist is a list of lists in the form (format macro-name attributes)
+; the first form has to generate a begin.
+; Note that macro-name can not be at the start of the lists in xformlist,
+; lest the macros would be expanded too early.
+; attributes is at the end so that when cgen gains the ability to handle
+; variable-length lists in macros (.car / .cdr would be sufficient in this
+; case), this parameter can be made optional.
+
+; Operate on one element. This expands to:
+; <macro-name> <mnemonic> <format> <attributes> <semantics> <fsemantics>
+(define-pmacro (dmfie xxop xxform xxsemantics xxfsemantics)
+ ((.cadr3 xxform) xxop (.car3 xxform) (.caddr3 xxform) xxsemantics xxfsemantics))
+
+; ??? This could be a lot simpler if .pmacro would do proper argument binding.
+(define-pmacro (dmfi xop xform xsemantics xfsemantics)
+ (splicelist (.map (.pmacro (l) (.apply dmfie l))
+ (.map (.apply .pmacro
+ ((e) (xop e xsemantics xfsemantics)))
+ xform)))
+)
+
+(dnf f-buf "branch unconditional far tag " () 15 1)
+(define-normal-insn-enum i-buf
+ ""
+ () B_ f-buf
+ (
+ (cc 0) (uncond_far 1)
+ )
+)
+
+(define-normal-insn-enum i-blr
+ ""
+ () BLR_ f-buf
+ (
+ (BL 0) (BR 1)
+ )
+)
+
+(dnf f-br "br RC / u6 tag " () 27 1)
+;(d2nf f-br "br RC / u6 tag " () 11 1)
+(define-normal-insn-enum i-br
+ ""
+ () BR_ f-br
+ (
+ (RC 0) (U6 1)
+ )
+)
+
+(dnf f-bluf "branch & link unconditional far tag " () 14 1)
+(define-normal-insn-enum op-bl
+ ""
+ () BL_ f-bluf
+ (
+ (cc 0) (uncond_far 1)
+ )
+)
+
+; check that xmach-ext is enabled.
+; values: MPY, MUL, BSHIFT, ARITH, NORM, SWAP, DSP
+; ARITH is built into arc700.
+(define-pmacro (mach-ext xmach-ext semantics)
+; FIXME: check that xmach-ext is enabled.
+ (cond SI ((eq 0 1) (invalid-expr))
+ (else semantics))
+)
+(define-pmacro (mach-ext-seq xxmach-ext locals semantics)
+ (if (mach-ext xxmach-ext (const 1))
+ (.splice sequence locals (.unsplice semantics)))
+)
+; Branch insns.
+
+(dsai b_s "branch short"
+ "b$i2cond $label10"
+ (+ i2cond OPM_B_S label10)
+ (RELAXABLE)
+ (if i2cond
+ (int-jump (set pc label10)))
+)
+
+(define-normal-insn-enum i-bcc_s
+ ""
+ () B_S_ f-cond-i2
+ (
+ (cc 3)
+ )
+)
+
+(dsai bcc_s "branch conditionally short"
+ "b$i3cond$_S $label7"
+ (+ i3cond OPM_B_S B_S_cc label7)
+ (RELAXABLE)
+ (if i3cond
+ (int-jump (set pc label7)))
+)
+
+(dnf f-brscond "brcc_s condition" () 8 1)
+(define-hardware
+ (name h-RccS)
+ (type immediate BI)
+ (values keyword "" ((eq 0) (ne 1)))
+)
+(dnop RccS "BRcc_s" () h-RccS f-brscond)
+
+(dsai brcc_s "branch on compare register with zero short"
+ "br$RccS$_S $R_b,0,$label8"
+ (+ OPM_BR_S R_b RccS label8)
+ (RELAXABLE)
+ (if (case BI RccS
+ ((0) (eq R_b 0))
+ ((1) (ne R_b 0))
+ (else (error BI "unreachable - put in because of parser error")))
+ (int-jump (set pc label8)))
+)
+
+(dDbranch daiQ bcc_l
+ ( "Branch Conditionally"
+ (.sstr "b$Qcondb$_L" delay-S " $label21")
+ (+ Qcondb delay-N OPM_B B_cc label21)
+ (RELAXED)
+ nop)
+ (set pc label21)
+ (delay-jump label21)
+)
+
+(dDbranch dnai b_l
+ ( "Branch Unconditional Far"
+ (.sstr "b$uncondb$_L" delay-S " $label25")
+ (+ delay-N OPM_B B_uncond_far label25 (f-res27 0))
+ (RELAXED))
+ (set pc label25)
+ (delay-jump label25)
+)
+
+(define-hardware
+ (name h-Rcc)
+ (type immediate SI)
+ (values keyword "" (m-brcond))
+)
+(dnop Rcc "BRcc / BBIT Condition" () h-Rcc f-brcond)
+
+(define-pmacro (dbri-semantics xxxlimm xxxc jump)
+ (sequence ((SI condition) (SI B) (SI C))
+ (set condition Rcc)
+ (xxxlimm)
+ (set B RB)
+ (set C xxxc)
+ (if (case BI condition
+ ((CONDBR_REQ) (eq B C))
+ ((CONDBR_RNE) (ne B C))
+ ((CONDBR_RLT) (lt B C))
+ ((CONDBR_RGE) (ge B C))
+ ((CONDBR_RLO) (ltu B C))
+ ((CONDBR_RHS) (geu B C))
+ ((CONDBR_BIT0) (eq (and B (sll 1 C)) 0))
+ ((CONDBR_BIT1) (ne (and B (sll 1 C)) 0))
+ (else (error BI "unreachable - put in because of parser error"))
+ )
+ jump)
+ )
+)
+
+; FIXME: Rcc syntax
+(define-pmacro (dbri xxlimm xxc xxattrs)
+ (dDbranch dnai (.sym brcc_ xxc)
+ ( "BRcc / BBIT"
+ (.sstr "b$Rcc" delay-S " $RB,$" xxc ",$label9")
+ (+ OPM_BLR RB BLR_BR xxc delay-N (.sym BR_ xxc) label9 Rcc) xxattrs)
+ (dbri-semantics xxlimm xxc (set pc label9))
+ (dbri-semantics xxlimm xxc (delay-jump label9))
+ )
+)
+
+(dbri limmBC RC ((LIMM BC))) (dbri nop U6 ())
+
+(dsai bl_s "branch and Link short"
+ "bl$uncondj$_S $label13a"
+ (+ OPM_BL_S label13a)
+ (RELAXABLE)
+ (int-jump (sequence ()
+ (set (reg h-cr 31) (add pc 2))
+ (set pc label13a)))
+)
+
+(dDbranch daiQ blcc
+ ( "Branch and Link Conditionally"
+ (.sstr "bl$Qcondj$_L" delay-S " $label21")
+ (+ Qcondj delay-N OPM_BLR BL_cc BLR_BL label21a)
+ (RELAXED)
+ nop)
+ (sequence ()
+ (set (reg h-cr 31) (add pc 4))
+ (set pc label21a))
+ (sequence ()
+ (set (reg h-cr 31) (add pc 8))
+ (delay-jump label21a))
+)
+
+(dDbranch dnai bl
+ ( "Branch and Link"
+ (.sstr "bl$uncondj$_L" delay-S " $label25a")
+ (+ delay-N OPM_BLR BL_uncond_far BLR_BL label25a (f-res27 0))
+ (RELAXED))
+ (sequence ()
+ (set (reg h-cr 31) (add pc 4))
+ (set pc label25a))
+ (sequence ((HI nword))
+ ; The return address depends on the length of the next opcode
+ ; (Long immediate is not allowed in delay slot.)
+ (set nword (mem HI (add pc 4)))
+ (if (and (and nword (sra nword 1)) #xa000)
+ (set (reg h-cr 31) (add pc 6))
+ (set (reg h-cr 31) (add pc 8)))
+ (delay-jump label25a))
+)
+
+(dnf f-ldozzx "load w/ offs: data size / ext" () 23 3)
+;(d2nf f-ldozzx "load w/ offs: data size / ext" () 7 3)
+(dnf f-ldr6zzx "load reg-reg: data size / ext" () 10 6)
+(dnf f-stozzr "store w/ offs: data size / reserved" () 29 3)
+;(d2nf f-stozz "store w/ offs: data size" () 13 2)
+(dnf f-ldoaa "load w/ offs addr write-back" () 21 2)
+;(d2nf f-ldoaa "load w/ offs addr write-back" () 5 2)
+(dnf f-ldraa "load reg-reg addr write-back" () 8 2)
+(dnf f-stoaa "store reg-reg addr write-back" () 27 2)
+;(d2nf f-stoaa "store reg-reg addr write-back" () 11 2)
+(dnf f-LDODi "ld w/ offs Direct mem access" () 20 1)
+;(d2nf f-LDODi "ld w/ offs Direct mem access" () 4 1)
+(dnf f-LDRDi "ld reg-reg Direct mem access" () 16 1)
+;(d2nf f-LDRDi "ld reg-reg Direct mem access" () 0 1)
+(dnf f-STODi "st w/ offs Direct mem access" () 26 1)
+;(d2nf f-STODi "st w/ offs Direct mem access" () 10 1)
+(dnop LDODi "ld /w offs Direct mem access" () h-Di f-LDODi)
+(dnop LDRDi "ld reg-reg Direct mem access" () h-Di f-LDRDi)
+(dnop STODi "ld w/ offs Direct mem access" () h-Di f-STODi)
+(dnop EXDi "ex Direct memory access" () h-Di f-F)
+(dnop _AW ".AW suffix" () h-_aw f-nil)
+
+(define-normal-insn-enum i-ldozz
+ ""
+ () LDO_LD f-ldozzx
+ (("" 0) (B 2) (BX 3) (W 4) (WX 5))
+)
+
+; This includes the 3 fixed (for load with offset) bits before zzx
+; that read '6'.
+(define-normal-insn-enum i-ldr6zzx
+ ""
+ () LDR_LD f-ldr6zzx
+ (("" 48) (B 50) (BX 51) (W 52) (WX 53))
+)
+
+(define-normal-insn-enum i-stozzr
+ ""
+ () STO_ST f-stozzr
+ (("" 0) (B 2) (W 4))
+)
+
+(define-normal-insn-enum i-ldoaa
+ ""
+ () LDOAA_ f-ldoaa
+ ((NO 0) (AW 1) (AB 2) (AS 3))
+)
+
+(define-normal-insn-enum i-ldraa
+ ""
+ () LDRAA_ f-ldraa
+ ((NO 0) (AW 1) (AB 2) (AS 3))
+)
+
+(define-normal-insn-enum i-stoaa
+ ""
+ () STOAA_ f-stoaa
+ ((NO 0) (AW 1) (AB 2) (AS 3))
+)
+
+(define-pmacro (ASscale__ offs) (sll offs 2))
+(define-pmacro (ASscale_w offs) (sll offs 1))
+(define-pmacro (ASscale_b offs) (invalid-expr))
+
+(define-pmacro (memsemantics xop s xA xB xC)
+ (sequence ((SI eaddr))
+ (set eaddr (add xB xC))
+ (.subst (A) (xA) s)
+ )
+)
+
+; ??? result when updating same register as written-back base for .AW / .AB
+; and as load destination is actually undefined. Should we invoke
+; invalid-insn for that?
+(define-pmacro (memawsemantics xop s xA xB xC)
+ (sequence ((SI eaddr))
+ (set eaddr (add xB xC))
+ (set xB eaddr)
+ (.subst (A) (xA) s)
+ )
+)
+
+(define-pmacro (memabsemantics xop s xA xB xC)
+ (sequence ((SI sum) (SI eaddr))
+ (set sum (add xB xC))
+ (set eaddr xB)
+ (.subst (A) (xA) s)
+ (set xB sum)
+ )
+)
+
+(define-pmacro (memassemantics xop s xA xB xC)
+ (sequence ((SI eaddr))
+ (set eaddr
+ (add xB ((.sym ASscale _ (.substring (.str xop _) 2 3)) xC)))
+ (.subst (A) (xA) s)
+ )
+)
+
+(define-pmacro (ddmemaa beglist xxname xxname1 xxprefix)
+ (define-pmacro (xxname xop xformat xattrs xsemantics xext)
+ (.splice (.unsplice beglist)
+ (xxname1 xop xformat (.sym xxprefix AA_NO) xattrs memsemantics
+ xsemantics "" xext)
+ (xxname1 xop xformat (.sym xxprefix AA_AW) xattrs memawsemantics
+ xsemantics $_AW xext)
+ (xxname1 xop xformat (.sym xxprefix AA_AB) xattrs memabsemantics
+ xsemantics .ab xext)
+ (xxname1 xop xformat (.sym xxprefix AA_AS) xattrs memassemantics
+ xsemantics .as xext)
+ )
+ )
+)
+
+(ddmemaa (begin) dldoi dldoi1 LDO)
+(ddmemaa () dldri dldri1 LDR)
+(ddmemaa (begin) dstoi dstoi1 STO)
+
+(define-pmacro (dldoi1 xop xformat aaformat xattrs addrsemantics xsemantics
+ xaa xext)
+ (dnai (.str xop xaa xext "_abs") (.str xop " with offset")
+ (.str xop xaa xext "$LDODi $RA,[$RB,$s9]")
+ (+ OPM_LD_S9 xformat aaformat LDODi RB RA s9)
+ (splicelist (((LIMM B)) xattrs))
+ (sequence () (limmB) (addrsemantics xop xsemantics RA RB s9))
+ )
+)
+
+(define-pmacro (dldri1 xop xformat aaformat xattrs addrsemantics xsemantics
+ xaa xext)
+ (dnai (.str xop xaa xext "_abc") (.str xop " register-register")
+ (.str xop xaa xext "$LDRDi $RA,[$RB,$RC]")
+ (+ OPM_GO xformat aaformat LDRDi RB RA RC)
+ (splicelist (((LIMM BC)) xattrs))
+ (sequence () (limmBC) (addrsemantics xop xsemantics RA RB RC))
+ )
+)
+
+(define-pmacro (dstoi1 xop xformat aaformat xattrs addrsemantics xsemantics
+ xaa xext)
+ (dnai (.str xop xaa xext "_abs") (.str xop " with offset")
+ (.str xop xaa xext "$STODi $RC,[$RB,$s9]")
+ (+ OPM_ST_S9 xformat aaformat LDODi RB RC s9)
+ (splicelist (((LIMM BC)) xattrs))
+ (sequence () (limmBC) (addrsemantics xop xsemantics RC RB s9))
+ )
+)
+
+(define-pmacro (d16ldr xop xformat xattrs xsemantics xext)
+ (
+ (dsai (.str xop "_s_abc") (.str xop "_s register - register")
+ (.str xop "$_S" xext " $R_a,[$R_b,$R_c]")
+ (+ OPM_SLDADDR xformat R_b R_c R_a)
+ xattrs
+ (memsemantics xop xsemantics R_a R_b R_c)
+ )
+ )
+)
+
+(define-pmacro (memopscale xop base)
+ (.sym base (.substring (.str xop _) 2 3)))
+
+(define-pmacro (d16memo xop xformat xattrs xsemantics xext)
+ (
+ (dsai (.str xop "_s" xext "_abu") (.str xop "_s with offset")
+ (.str xop "$_S" xext " $R_c,[$R_b,$" (memopscale xop sc_u5) "]")
+ (+ xformat R_b R_c (memopscale xop sc_u5))
+ xattrs
+ (memsemantics xop xsemantics R_c R_b (memopscale xop sc_u5))
+ )
+ )
+)
+
+(define-pmacro (d16memsp xop xformat xattrs xsemantics xext)
+ (
+ (dsai (.str xop "_s_absp") (.str xop "_s b,sp,u5x4")
+ (.str xop "$_S $R_b,[$SP,$u5x4]")
+ (+ OPM_SP R_b xformat u5x4)
+ xattrs
+ (memsemantics xop xsemantics R_b SP u5x4)
+ )
+ )
+)
+
+(define-pmacro (dmemgpreli xop xformat xattrs xsemantics xext)
+ (
+ (dsai (.str xop "_s_gprel") (.str xop "_s gprel")
+ (.str xop "$_S $R_b,[$GP,$" (memopscale xop sc_s9) "]")
+ (+ OPM_GP xformat (memopscale xop sc_s9))
+ xattrs
+ (memsemantics xop xsemantics R0 GP (memopscale xop sc_s9))
+ )
+ )
+)
+
+(define-pmacro (dmempcreli xop xformat xattrs xsemantics xext)
+ (
+ (dsai (.str xop "_s_pcrel") (.str xop "_s pcrel")
+ (.str xop "$_S $R_b,[$PCL,$u8x4]")
+ (+ xformat R_b u8x4)
+ xattrs
+ (memsemantics xop xsemantics R_b (and pc -4) u8x4)
+ )
+ )
+)
+
+(dmfi "ld"
+ ((LDO_LD dldoi (RELAXED))
+ (LDR_LD dldri (RELAXED))
+ (I16_LDADDR_LD d16ldr (RELAXABLE))
+ (OPM_LDO_S d16memo (RELAXABLE))
+ (I16_SP_LD d16memsp (RELAXABLE))
+ (I16_GP_LD dmemgpreli (RELAXABLE))
+ (OPM_LDPCREL dmempcreli (RELAXABLE)))
+ (set A (mem SI eaddr))
+ ""
+)
+
+(dmfi ldb
+ ((LDO_LDB dldoi (RELAXED))
+ (LDR_LDB dldri (RELAXED))
+ (I16_LDADDR_LDB d16ldr (RELAXABLE))
+ (OPM_LDOB_S d16memo (RELAXABLE))
+ (I16_SP_LDB d16memsp (RELAXABLE))
+ (I16_GP_LDB dmemgpreli (RELAXABLE)))
+ (set A (zext SI (mem QI eaddr)))
+ ""
+)
+
+(dmfi ldb
+ ((LDO_LDBX dldoi (RELAXED))
+ (LDR_LDBX dldri (RELAXED)))
+ (set A (ext SI (mem QI eaddr)))
+ ".x"
+)
+
+(dmfi ldw
+ ((LDO_LDW dldoi (RELAXED))
+ (LDR_LDW dldri (RELAXED))
+ (I16_LDADDR_LDW d16ldr (RELAXABLE))
+ (OPM_LDOW_S d16memo (RELAXABLE))
+ (I16_GP_LDW dmemgpreli (RELAXABLE)))
+ (set A (zext SI (mem HI eaddr)))
+ ""
+)
+
+(dmfi ldw
+ ((LDO_LDWX dldoi (RELAXED))
+ (LDR_LDWX dldri (RELAXED))
+ (OPM_LDOWX_S d16memo (RELAXABLE)))
+ (set A (ext SI (mem HI eaddr)))
+ ".x"
+)
+
+(dmfi "st"
+ ((STO_ST dstoi (RELAXED))
+ (OPM_STO_S d16memo (RELAXABLE))
+ (I16_SP_ST d16memsp (RELAXABLE)))
+ (set (mem SI eaddr) A)
+ ""
+)
+(dmfi stb
+ ((STO_STB dstoi (RELAXED))
+ (OPM_STOB_S d16memo (RELAXABLE))
+ (I16_SP_STB d16memsp(RELAXABLE)))
+ (set (mem QI eaddr) A)
+ ""
+)
+
+(dmfi stw
+ ((STO_STW dstoi (RELAXED))
+ (OPM_STOW_S d16memo (RELAXABLE)))
+ (set (mem HI eaddr) A)
+ ""
+)
+
+
+; general operations
+
+(dmfi add
+ ( (GO_OP_ADD dgoi (RELAXED))
+ (I16_LDADDR_ADD d16addr (RELAXABLE))
+ (I16_ADDSUBSHI_ADD d16addsubshi (RELAXABLE))
+ (I16_MOVCMPADDH_ADD d16addh (RELAXABLE))
+ (I16_SP_ADD d16add-b-sp (RELAXABLE))
+ (I16_SP_ADDSUB_ADD d16addsub-sp-sp (RELAXABLE))
+ (I16_GP_ADD d16gp_add (RELAXABLE))
+ (I16_ADDCMPU7_ADD d16addu7 (RELAXABLE)))
+ (add B C)
+ (sequence ()
+ (flagNZ)
+ (set vbit (add-oflag B C 0))
+ (set cbit (add-cflag B C 0))
+ )
+)
+
+(dgoi adc GO_OP_ADC () (addc B C cbit)
+ (sequence ()
+ (flagNZ)
+ (set vbit (add-oflag B C cbit))
+ (set cbit (add-cflag B C cbit))
+ )
+)
+
+(dmfi sub
+ ( (GO_OP_SUB dgoi (RELAXED))
+ (I16_ADDSUBSHI_SUB d16addsubshi (RELAXABLE))
+ (I16_GO_SUB d16goi (RELAXABLE))
+ (I16_GO_SOP_SUB_NE dsubs_ne (RELAXABLE))
+ (I16_SHSUBBIMM_SUB d16shsubbimm (RELAXABLE))
+ (I16_SP_ADDSUB_SUB d16addsub-sp-sp (RELAXABLE)))
+ (sub B C)
+ (sequence ()
+ (flagNZ)
+ (set vbit (sub-oflag B C 0))
+ (set cbit (sub-cflag B C 0))
+ )
+)
+
+(dgoi sbc GO_OP_SBC () (subc B C cbit)
+ (sequence ()
+ (flagNZ)
+ (set vbit (sub-oflag B C cbit))
+ (set cbit (sub-cflag B C cbit))
+ )
+)
+
+(dmfi and
+ ((GO_OP_AND dgoi (RELAXED))
+ (I16_GO_AND d16goi (RELAXABLE)))
+ (and B C)
+ (flagNZ)
+)
+
+(dmfi or
+ ((GO_OP_OR dgoi (RELAXED))
+ (I16_GO_OR d16goi (RELAXABLE)))
+ (or B C)
+ (flagNZ)
+)
+
+(dmfi bic
+ ((GO_OP_BIC dgoi (RELAXED))
+ (I16_GO_BIC d16goi (RELAXABLE)))
+ (and B (inv C))
+ (flagNZ)
+)
+
+(dmfi xor
+ ((GO_OP_XOR dgoi (RELAXED))
+ (I16_GO_XOR d16goi (RELAXABLE)))
+ (xor B C)
+ (flagNZ)
+)
+
+(dgoi max GO_OP_MAX () (cond SI ((gt B C) B) (else C))
+ (sequence ()
+ (flagNZ)
+ (set cbit (ge SI C B))
+ (set vbit (sub-oflag B C 0))
+ )
+)
+
+(dgoi min GO_OP_MIN () (cond SI ((lt B C) B) (else C))
+ (sequence ()
+ (flagNZ)
+ (set cbit (le SI C B))
+ (set vbit (sub-oflag B C 0))
+ )
+)
+
+(dmfi mov
+ ((GO_OP_MOV dgmov (RELAXED))
+ (I16_MOVCMPADDH_MOVbh d16movcmph (RELAXABLE))
+ (I16_MOVCMPADDH_MOVhb d16movhb (RELAXABLE))
+ (OPM_SMOVU8 d16movu8 (RELAXABLE)))
+ ()
+ movsemantics
+)
+
+(dmfi tst
+ ((GO_OP_TST dg2oi (RELAXED))
+ (I16_GO_TST d16g2oi (RELAXABLE)))
+ (and B C)
+ tstsemantics
+)
+
+(dmfi cmp
+ ((GO_OP_CMP dg2oi (RELAXED))
+ (I16_MOVCMPADDH_CMP d16movcmph (RELAXABLE))
+ (I16_ADDCMPU7_CMP d16cmpu7 (RELAXABLE)))
+ (sub B C)
+ cmpsemantics
+)
+
+(dg2oi rcmp GO_OP_RCMP (RELAXED) (sub C B) cmpsemantics)
+
+(dgoi rsub GO_OP_RSUB () (sub C B)
+ (sequence ()
+ (flagNZ)
+ (set vbit (sub-oflag C B 0))
+ (set cbit (sub-cflag C B 0))
+ )
+)
+
+(dmfi bset
+ ((GO_OP_BSET dgoi (RELAXED))
+ (I16_SHSUBBIMM_BSET d16shsubbimm (RELAXABLE)))
+ (or B (sll 1 (and C 31)))
+ (flagNZ)
+)
+
+(dmfi bclr
+ ((GO_OP_BCLR dgoi (RELAXED))
+ (I16_SHSUBBIMM_BCLR d16shsubbimm (RELAXABLE)))
+ (and B (inv (sll 1 (and C 31))))
+ (flagNZ)
+)
+
+(dmfi btst
+ ((GO_OP_BTST dg2oi (RELAXED))
+ (I16_SHSUBBIMM_BTST d16btst (RELAXABLE)))
+ (and B (sll 1 (and C 31)))
+ tstsemantics
+)
+
+(dgoi bxor GO_OP_BXOR () (xor B (sll 1 (and C 31)))
+ (flagNZ)
+)
+
+(dmfi bmsk
+ ((GO_OP_BMSK dgoi (RELAXED))
+ (I16_SHSUBBIMM_BMSK d16shsubbimm (RELAXABLE)))
+ (and B (sub (sll (sll USI 1 (and C 31)) 1) 1))
+ (flagNZ)
+)
+
+; define shift-add insn
+(define-pmacro (dshaddi xxn)
+ (dmfi (.sym add xxn)
+ (((.sym GO_OP_ADD xxn) dgoi (RELAXED))
+ ((.sym I16_GO_ADD xxn) d16goi (RELAXABLE)))
+ (add B (sll C xxn))
+ (sequence ((SI sC))
+ (set sC (sll C xxn))
+ (flagNZ)
+ (set vbit (add-oflag B sC 0))
+ (set cbit (add-cflag B sC 0))
+ )
+ )
+)
+
+(dshaddi 1) (dshaddi 2) (dshaddi 3)
+
+; define shift-sub insn
+(define-pmacro (dshsubi xxn)
+ (dgoi (.sym sub xxn)
+ (.sym GO_OP_SUB xxn) (RELAXED)
+ (sub B (sll C xxn))
+ (sequence ((SI sC))
+ (set sC (sll C xxn))
+ (flagNZ)
+ (set vbit (sub-oflag B sC 0))
+ (set cbit (sub-cflag B sC 0))
+ )
+ )
+)
+
+(dshsubi 1) (dshsubi 2) (dshsubi 3)
+
+(dgoi mpy GO_OP_MPY ()
+ (mach-ext MPY (mul B C))
+ (sequence ()
+ (flagNZ)
+ (set vbit (ne (ext DI result) (mul (ext DI B) (ext DI C)))))
+)
+
+(dgoi mpyh GO_OP_MPYH ()
+ (mach-ext MPY (subword SI (mul (ext DI B) (ext DI C)) 0))
+ (sequence () (flagNZ) (set vbit 0))
+)
+
+(dgoi mpyhu GO_OP_MPYHU ()
+ (mach-ext MPY (subword SI (mul (zext DI B) (zext DI C)) 0))
+ (sequence () (flagNZ) (set vbit 0))
+)
+
+(dgoi mpyu GO_OP_MPYU ()
+ (mach-ext MPY (mul B C))
+ (sequence ()
+ (flagNZ)
+ (set vbit (ne (zext DI result) (mul (zext DI B) (zext DI C)))))
+)
+
+(dmfi j
+ ((GO_OP_J djri (RELAXED))
+ (GO_OP_J djilink (RELAXED)))
+ (sequence ()
+ (case VOID f-op-Cj
+ ; ilink1
+ ((29) (if F (set (reg h-status32) (aux-status32_l1))
+ (invalid-insn)))
+ ; ilink2
+ ((30) (if F (set (reg h-status32) (aux-status32_l2))
+ (invalid-insn)))
+ (else (if F (invalid-insn))))
+ (set pc C)
+ )
+ jsemantics
+)
+
+(dmfi j
+ ((GO_OP_J dji (RELAXED))
+ (I16_GO_SOP_J djsi (RELAXABLE))
+ (I16_GO_ZOP_J djsblink (RELAXABLE))
+ (I16_GO_ZOP_JEQ djsblinkeq (RELAXABLE))
+ (I16_GO_ZOP_JNE djsblinkne (RELAXABLE)))
+ (sequence ()
+ (if F (invalid-insn))
+ (set pc C)
+ )
+ jsemantics
+)
+
+(dmfi j
+ ((GO_OP_J_D djdi (RELAXED))
+ (I16_GO_SOP_J_D djsid (RELAXABLE))
+ (I16_GO_ZOP_J_D djsblinkd (RELAXABLE)))
+ (delay-jump C)
+ jdsemantics ; ??? should be jsemantics, but that exposes delay bug
+)
+
+(dji jl GO_OP_JL (RELAXED)
+ (sequence ()
+ (set pc C)
+ (set (reg h-cr 31) (add pc 4))
+ )
+ jsemantics
+)
+
+(dmfi jl
+ ((- dbegin -) (I16_GO_SOP_JL djsi (RELAXABLE)))
+ (sequence ()
+ (set pc C)
+ (set (reg h-cr 31) (add pc 2))
+ )
+ jsemantics
+)
+
+(dmfi jl
+ ((GO_OP_JL djri (RELAXED)))
+ (sequence ()
+ (set pc C)
+ (set (reg h-cr 31) (add pc (if SI (eq f-op-C 62) 8 4)))
+ )
+ jsemantics
+)
+
+(djdi jl GO_OP_JL_D (RELAXED)
+ (sequence ((HI nword))
+ ; The return address depends on the length of the next opcode
+ ; (Long immediate is not allowed in delay slot.)
+ (set nword (mem HI (add pc 4)))
+ (if (and (and nword (sra nword 1)) #xa000)
+ (set (reg h-cr 31) (add pc 6))
+ (set (reg h-cr 31) (add pc 8)))
+ (delay-jump C)
+ )
+ jdsemantics ; ??? should be jsemantics, but that exposes delay bug
+)
+
+(dmfi jl
+ ((- dbegin -) (I16_GO_SOP_JL_D djsid (RELAXABLE)))
+ (sequence ((HI nword))
+ ; The return address depends on the length of the next opcode
+ ; (Long immediate is not allowed in delay slot.)
+ (set nword (mem HI (add pc 2)))
+ (if (and (and nword (sra nword 1)) #xa000)
+ (set (reg h-cr 31) (add pc 4))
+ (set (reg h-cr 31) (add pc 6)))
+ (delay-jump C)
+ )
+ jdsemantics ; ??? should be jsemantics, but that exposes delay bug
+)
+
+(dlpcci lp GO_OP_LP (COND-CTI)
+ (sequence ()
+ (set (aux-lp_end) (add (and WI pc (const -4)) C))
+ (set (aux-lp_start) (add pc 4))
+ )
+ jsemantics
+)
+
+(dsfi flag GO_OP_FLAG ()
+ (sequence ()
+ ; Check processsor halt flag H.
+ (if (and C 1)
+ (c-code
+ "sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc,\
+ sim_exited, a5f_h_cr_get (current_cpu, 0));"))
+ (set (reg h-status32) C))
+ sfisemantics
+)
+
+(dlrsr lr GO_OP_LR ()
+ (set B (reg h-auxr C))
+ sfisemantics
+)
+
+; changing loop_end flushes scache, but to make flush effective, consider this
+; COND-CTI.
+(dlrsr sr GO_OP_SR (COND-CTI)
+ (set (reg h-auxr C) B)
+ sfisemantics
+)
+
+(dmfi asl
+ ( (GO_OP_SOP_ASL dgsoi (RELAXED))
+ (I16_GO_ASL d16goi (RELAXABLE)))
+ (add C C)
+ (sequence ()
+ (flagNZ)
+ (set vbit (add-oflag C C 0))
+ (set cbit (add-cflag C C 0))
+ )
+)
+
+(dmfi asr
+ ( (GO_OP_SOP_ASR dgsoi (RELAXED))
+ (I16_GO_ASR d16goi (RELAXABLE)))
+ (sra C 1)
+ (sequence ()
+ (flagNZ)
+ (set cbit (and C 1))
+ )
+)
+
+(dmfi lsr
+ ( (GO_OP_SOP_LSR dgsoi (RELAXED))
+ (I16_GO_LSR d16goi (RELAXABLE)))
+ (srl C 1)
+ (sequence ()
+ (flagNZ)
+ (set cbit (and C 1))
+ )
+)
+
+(dgsoi ror GO_OP_SOP_ROR ()
+ (or (srl C 1) (sll C 31))
+ (sequence ()
+ (flagNZ)
+ (set cbit (and C 1))
+ )
+)
+
+(dgsoi rrc GO_OP_SOP_RRC ()
+ (or (srl C 1) (sll (zext SI cbit) 31))
+ (sequence ()
+ (flagNZ)
+ (set cbit (and C 1))
+ )
+)
+
+; ??? immediate fields lack a mode, so we often have to cast a value to
+; have a defined mode.
+(define-pmacro (cast mode val) (sequence mode () val))
+
+; ??? problems with finding the right signedness appear to be more stubborn.
+(define-pmacro (really_cast mode val)
+(sequence mode ((mode res)) (set res val) res))
+
+(dmfi sexb
+ ( (GO_OP_SOP_SEXB dgsoi (RELAXED))
+ (I16_GO_SEXB d16goi (RELAXABLE)))
+ (ext SI (cast QI C))
+ (flagNZ)
+)
+
+(dmfi sexw
+ ( (GO_OP_SOP_SEXW dgsoi (RELAXED))
+ (I16_GO_SEXW d16goi (RELAXABLE)))
+ (ext SI (cast HI C))
+ (flagNZ)
+)
+
+(dmfi extb
+ ( (GO_OP_SOP_EXTB dgsoi (RELAXED))
+ (I16_GO_EXTB d16goi (RELAXABLE)))
+ (zext SI (cast QI C))
+ (flagNZ)
+)
+
+(dmfi extw
+ ( (GO_OP_SOP_EXTW dgsoi (RELAXED))
+ (I16_GO_EXTW d16goi (RELAXABLE)))
+ (zext SI (cast HI C))
+ (flagNZ)
+)
+
+(dmfi abs
+ ( (GO_OP_SOP_ABS dgsoi (RELAXED))
+ (I16_GO_ABS d16goi (RELAXABLE)))
+ (abs (really_cast SI C))
+ (sequence ()
+ (set zbit (zflag result))
+ (set cbit (nflag (cast SI C)))
+ (set vbit (eq C #x80000000))
+ (set nbit vbit)
+ )
+)
+
+(dmfi not
+ ( (GO_OP_SOP_NOT dgsoi (RELAXED))
+ (I16_GO_NOT d16goi (RELAXABLE)))
+ (inv C)
+ (flagNZ)
+)
+
+(dgsoi rlc GO_OP_SOP_RLC ()
+ (or (sll C 1) cbit)
+ (sequence ()
+ (flagNZ)
+ (set cbit (srl C 31))
+ ; ??? vbit undefined, should we do something pseudo-random?
+ )
+)
+
+(dex ex GO_OP_SOP_EX ((MACH arc700))
+ ; ??? A sequence with values, but without locals is generated syntactically
+ ; invalid if a form inside has no value.
+ (sequence SI ((SI dummy)) ; use dummy local to work around generator bug
+ (set (mem SI C) A)
+ (mem SI C)
+ )
+ (nop) ; F controls Direct (non-cached) memory access
+)
+
+; ??? need to define expansion of neg into rsub
+;(define-macro-insn
+; (name macro-insn-name)
+; (comment "description")
+; (attrs attribute-list)
+; (syntax "assembler syntax")
+; (expansions expansion-spec)
+;)
+
+(dmfi neg
+ ((- dbegin -) (I16_GO_NEG d16goi ()))
+ (neg C)
+ (flagNZ)
+)
+
+(define-normal-insn-enum go-zop
+ "general zero-operand operations type"
+ ; ??? FIXME: using multi-ifields is broken, see:
+ ; http://sourceware.org/ml/cgen/2007-q1/msg00059.html
+ ;() GO_OP_ZOP_ f-op-B
+ () GO_OP_ZOP_ f-op--b
+ ((SLEEP 1) (SWI 2) (SYNC 3) (RTIE 4) (BRK 5))
+)
+
+; ??? unimplemented: sleep, sync, rtie
+(dnai
+ swi
+ "swi / trap0"
+ "swi" ; ??? create trap0 alias for arc700
+ (+ OPM_GO GO_OP_ZOP_SWI GO_TYPE_U6 GO_OP_SOP F0 GO_OP_SOP_ZOP (f-op-C 0)
+ (f-B-5-3 0) ; FIXME
+ )
+ ()
+ (int-jump (sequence ()
+ ; If a system call is simulated, r0..r2 and r8 are used,
+ ; and r0 is set to a new value.
+ ;(use (reg h-cr 0))
+ ;(use (reg h-cr 1))
+ ;(use (reg h-cr 2))
+ ;(use (reg h-cr 8))
+ (clobber (reg h-cr 0))
+ (set pc (c-call SI "arc_trap" pc 4 0))))
+)
+
+(dnf f-trapnum "trap number" () 5 6)
+(dnop trapnum "6 bit trap number" () h-uint f-trapnum)
+(dsai
+ trap_s
+ "trap"
+ "trap$_S $trapnum"
+ (+ OPM_SGO I16_GO_TRAP trapnum)
+ ()
+ (int-jump (sequence ()
+ (set pc (c-call SI "arc_trap" pc 2 trapnum))
+ ; If a system call is simulated, r0 is set to a new value.
+ (clobber (reg h-cr 0))))
+)
+
+(dnai
+ brk
+ "brk"
+ "brk"
+ (+ OPM_GO GO_OP_ZOP_BRK GO_TYPE_U6 GO_OP_SOP F0 GO_OP_SOP_ZOP (f-op-C 0)
+ (f-B-5-3 0)) ; FIXME
+ ()
+ (c-call "arc_breakpoint" pc 4))
+
+(dsai
+ brk_s
+ "brk_s"
+ "brk_s"
+ (+ OPM_SGO I16_GO_BRK (f-trapnum 63))
+ ()
+ (c-call "arc_breakpoint" pc 2))
+
+(define-normal-insn-enum x05-go-op
+ "general operations type"
+ () X05_ f-go-op
+ (
+ (ASL 0) (LSR 1) (ASR 2) (ROR 3) (MUL64 4) (MULU64 5) (ADDS 6) (SUBS 7)
+ (DIVAW 8) (ASLS 10) (ASRS 11) (ADDSDW 40) (SUBSDW 41) (SOP 47)
+ (CMACRDW 38) (MACDW 16) (MACFLW 52) (MACHFLW 55) (MACHLW 54) (MACHULW 53)
+ (MACLW 51) (MACRDW 18) (MACUDW 17) (MSUBDW 20) (MULDW 12) (MULFLW 50)
+ (MULHFLW 57) (MULHLW 56) (MULLW 49) (MULRDW 14) (MULUDW 13) (MULULW 48)
+ )
+)
+
+(define-pmacro (GO_BASE) OPM_X05)
+
+(dmfi asl
+ ( (X05_ASL dgoi (RELAXED))
+ (I16_ADDSUBSHI_ASL d16addsubshi (RELAXABLE))
+ (I16_SHSUBBIMM_ASL d16shsubbimm (RELAXABLE))
+ (I16_GO_ASLM d16goi (RELAXABLE))
+ )
+ (mach-ext BSHIFT (sll B (and C 31)))
+ (sequence ()
+ (flagNZ)
+ (set cbit (if BI (eq (and C 31) 0) 0 (and (srl B (sub 32 (and C 31))) 1)))
+ )
+)
+
+(dmfi lsr
+ ( (X05_LSR dgoi (RELAXED))
+ (I16_SHSUBBIMM_LSR d16shsubbimm (RELAXABLE))
+ (I16_GO_LSRM d16goi (RELAXABLE)))
+ (mach-ext BSHIFT (srl B (and C 31)))
+ (sequence ()
+ (flagNZ)
+ (set cbit (if BI (eq (and C 31) 0) 0 (and (srl B (sub (and C 31) 1)) 1)))
+ )
+)
+
+(dmfi asr
+ ( (X05_ASR dgoi (RELAXED))
+ (I16_ADDSUBSHI_ASR d16addsubshi (RELAXABLE))
+ (I16_SHSUBBIMM_ASR d16shsubbimm (RELAXABLE))
+ (I16_GO_ASRM d16goi (RELAXABLE)))
+ (mach-ext BSHIFT (sra B (and C 31)))
+ (sequence ()
+ (flagNZ)
+ (set cbit (if BI (eq (and C 31) 0) 0 (and (srl B (sub (and C 31) 1)) 1)))
+ )
+)
+
+(dgoi ror X05_ROR ()
+ (mach-ext BSHIFT (ror B (and C 31)))
+ (sequence ()
+ (flagNZ)
+ (set cbit (if BI (eq (and C 31) 0) 0 (and (srl B (sub (and C 31) 1)) 1)))
+ )
+)
+
+; ??? syntax should allow 0, prefix.
+(dmfi mul64
+ ( (X05_MUL64 dg2oi (RELAXED))
+ (I16_GO_MUL64 d16g2oi (RELAXABLE)))
+ (mach-ext-seq MUL ((DI result))
+ ( (set result (mul (ext DI B) (ext DI C)))
+ (set (reg h-cr 57) (subword SI result 1))
+ (set (reg h-cr 58) (subword SI (srl result 16) 1))
+ (set (reg h-cr 59) (subword SI result 0))
+ )
+ )
+ sfisemantics
+)
+
+(dg2oi mulu64 X05_MULU64 ()
+ (mach-ext-seq MUL ((DI result))
+ ( (set result (mul (zext DI B) (zext DI C)))
+ (set (reg h-cr 57) (subword SI result 1))
+ (set (reg h-cr 58) (subword SI (srl result 16) 1))
+ (set (reg h-cr 59) (subword SI result 0))
+ )
+ )
+ sfisemantics
+)
+
+(define-pmacro (SImin) (add #x-7fffffff -1))
+
+(define-pmacro (sat32 tmp)
+ (sequence SI ()
+ (cond SI
+ ((gt tmp #x7fffffff) (set cur_s1bit 1) #x7fffffff)
+ ((lt tmp (SImin)) (set cur_s1bit 1) (SImin))
+ (else (set cur_s1bit 0) tmp)))
+)
+
+(define-pmacro (sat32op op B C)
+ (sequence SI ((DI tmp))
+ (set tmp (op (ext DI B) (ext DI C)))
+ (sat32 tmp))
+)
+
+(define-pmacro (sat16 val)
+ (sequence HI ((SI tmp))
+ (set tmp val)
+ (cond SI
+ ((gt tmp #x7fff) (set cur_s1bit 1) #x7fff)
+ ((lt tmp #x-8000) (set cur_s1bit 1) #x-8000)
+ (else tmp)))
+)
+
+(define-pmacro (sat_shift op_pos op_neg B C)
+ (sequence SI ((DI b))
+ (set b (ext DI B))
+ (set b
+ (cond DI
+ ((eq b 0) 0)
+ ((gt C 31) (op_pos b 31))
+ ((lt C -31) (op_neg b 31))
+ ((ge C 0) (op_pos b C))
+ (else (op_neg B (neg C)))))
+ (sat32 b))
+)
+
+(define-pmacro (satdw op B C)
+ (sequence SI ((SI C_SI) (HI res1) (HI res2))
+ (set res2 (sat16 (op (subword HI B 1) (subword HI (cast SI C) 1))))
+ (set cur_s2bit cur_s1bit)
+ (set res1 (sat16 (op (subword HI B 0) (subword HI (cast SI C) 0))))
+ (or (sll res1 16) res2))
+)
+
+; saturating operations leave cbit alone, except for adds and subs,
+; which clear it
+(define-pmacro (flagNZVS)
+ (sequence ()
+ (flagNZ)
+ (set vbit cur_s1bit)
+ (cond (cur_s1bit (set s1bit 1) (set s2bit 1))))
+)
+
+(define-pmacro (flagNZVS1S2)
+ (sequence ()
+ (flagNZ)
+ (set vbit (or cur_s1bit cur_s2bit))
+ (if cur_s1bit (set s1bit 1))
+ (if cur_s2bit (set s2bit 1)))
+)
+
+(dgoi adds X05_ADDS ()
+ (mach-ext ARITH (sat32op add B C))
+ (sequence () (flagNZVS) (set cbit 0))
+)
+
+(dgoi subs X05_SUBS ()
+ (mach-ext ARITH (sat32op sub B C))
+ (sequence () (flagNZVS) (set cbit 0))
+)
+
+(d_divaw divaw X05_DIVAW ()
+ (mach-ext ARITH
+ (sequence SI ((USI tmp))
+ (set tmp (sll B 1))
+ (if SI (eq (and (sub SI tmp C) #x80000000) 0)
+ (add (sub tmp C) 1)
+ tmp)))
+ (nop)
+)
+
+(dgoi asls X05_ASLS ()
+ (mach-ext ARITH (sat_shift sll sra B (cast SI C)))
+ (flagNZVS)
+)
+
+(dgoi asrs X05_ASRS ()
+ (mach-ext ARITH (sat_shift sra sll B (cast SI C)))
+ (flagNZVS)
+)
+
+(dgoi addsdw X05_ADDSDW ()
+ (mach-ext ARITH (satdw add B C))
+ (flagNZVS1S2)
+)
+
+(dgoi subsdw X05_SUBSDW ()
+ (mach-ext ARITH (satdw sub B C))
+ (flagNZVS1S2)
+)
+
+(define-normal-insn-enum x05-sop-kind
+ "x06 extension single-operand operantion"
+ () X05_SOP_ f-op-A
+ (
+ (SWAP 0) (NORM 1) (SAT16 2) (RND16 3) (ABSSW 4) (ABSS 5) (NEGSW 6) (NEGS 7)
+ (NORMW 8) (ZOP 63)
+ )
+)
+
+(dgsoi swap X05_SOP_SWAP ()
+ (mach-ext ARITH (ror C 16))
+ (flagNZ)
+)
+
+(define-pmacro (arc-norm in)
+ (mach-ext NORM
+ (.splice sequence SI ((SI val) (SI bits))
+ (set val (if SI (ge in 0) in (inv in)))
+ (set bits 31)
+ (.unsplice (.map
+ (.pmacro (num)
+ (cond ((ge val (sll 1 (sub (sll 1 num) 1)))
+ (set val (srl val (sll 1 num)))
+ (set bits (sub bits (sll 1 num))))))
+ (.iota 5 4 -1)))
+ bits))
+)
+
+(dgsoi norm X05_SOP_NORM ()
+ (arc-norm (cast SI C))
+ (sequence ()
+ (set nbit (nflag C))
+ (set zbit (zflag C)))
+)
+
+(dgsoi rnd16 X05_SOP_RND16 ()
+ (mach-ext ARITH (srl (sat32op add #x8000 C) 16))
+ (flagNZVS)
+)
+
+(dgsoi abssw X05_SOP_ABSSW ()
+ (mach-ext ARITH (sat16 (abs (ext SI (cast HI C)))))
+ (flagNZVS)
+)
+
+(dgsoi abss X05_SOP_ABSS ()
+ (mach-ext ARITH (if SI (ge (cast SI C) 0) C (sat32op sub 0 C)))
+ (flagNZVS)
+)
+
+(dgsoi negsw X05_SOP_NEGSW ()
+ (mach-ext ARITH (sat16 (ext SI (cast HI C))))
+ (flagNZVS)
+)
+
+(dgsoi negs X05_SOP_NEGS ()
+ (mach-ext ARITH (sat32op sub 0 C))
+ (flagNZVS)
+)
+
+(dgsoi normw X05_SOP_NORMW ()
+ (arc-norm (or (sll C 16) (and C #xffff)))
+ (flagNZ)
+)
+
+
+
+; ??? FIXME: Add macro-insn for 32 bit nop.
+(dsai nop_s "nop" "nop_s"
+ (+ OPM_SGO I16_GO_SOP I16_GO_SOP_ZOP I16_GO_ZOP_NOP)
+ ()
+ (nop)
+)
+
+(dsai unimp_s "unimp" "unimp_s"
+ (+ OPM_SGO I16_GO_SOP I16_GO_SOP_ZOP I16_GO_ZOP_UNIMP)
+ ()
+ (invalid-insn)
+)
+
+(define-normal-insn-enum pushpop-kind
+ ""
+ () PUSHPOP_ f-u5
+ ((B 1) (BLINK 17))
+)
+
+(define-normal-insn-enum pushpop-R_b
+ ""
+ () "" f-op--b
+ ((OP_B_0))
+)
+
+(dsai pop_s_b "pop" "pop$_S $R_b"
+ (+ OPM_SP I16_SP_POP R_b PUSHPOP_B)
+ ()
+ (sequence ()
+ (set R_b (mem SI SP))
+ (set SP (add SP 4)))
+)
+
+(dsai pop_s_blink "pop" "pop$_S $R31"
+ (+ OPM_SP I16_SP_POP OP_B_0 PUSHPOP_BLINK)
+ ()
+ (sequence ()
+ (set R31 (mem SI SP))
+ (set SP (add SP 4)))
+)
+
+(dsai push_s_b "push" "push$_S $R_b"
+ (+ OPM_SP I16_SP_PUSH R_b PUSHPOP_B)
+ ()
+ (sequence ()
+ (set SP (add SP -4))
+ (set (mem SI SP) R_b))
+)
+
+(dsai push_s_blink "push" "push$_S $R31"
+ (+ OPM_SP I16_SP_PUSH OP_B_0 PUSHPOP_BLINK)
+ ()
+ (sequence ()
+ (set SP (add SP -4))
+ (set (mem SI SP) R31))
+)
+
+(dgoi mullw X05_MULLW ()
+ (sequence SI ((DI tmp))
+ (set tmp (mach-ext DSP (mul (ext DI B) (ext DI (and C #xffff)))))
+ (set (reg h-cr 57) (subword SI tmp 1))
+ (set (reg h-cr 56) (subword SI tmp 0))
+ (sat32 tmp))
+ (flagNZVS)
+)
+
+(dgoi maclw X05_MACLW ()
+ (sequence SI ((DI old) (DI tmp) (SI SItmp))
+ (set old (add (sll (zext DI (reg h-cr 56)) 32) (zext DI (reg h-cr 57))))
+ (set tmp (mach-ext DSP (mul (ext DI B) (ext DI (and C #xffff)))))
+ (set vbit (not (srl (xor old tmp) 63)))
+ (set tmp (add old tmp))
+ (set vbit (and vbit (srl (xor old tmp) 63)))
+ (cond ((ne vbit 0) (set tmp (xor (sra old 63) (srl -1 1)))))
+ (set (reg h-cr 57) (subword SI tmp 1))
+ (set (reg h-cr 56) (subword SI tmp 0))
+ (set SItmp (sat32 tmp))
+ (set cur_s1bit (or cur_s1bit vbit))
+ SItmp)
+ (flagNZVS)
+)
+
+(dgoi machlw X05_MACHLW ()
+ (sequence SI ((DI old) (DI tmp))
+ (set old (add (sll (zext DI (reg h-cr 56)) 32) (zext DI (reg h-cr 57))))
+ (set tmp (mach-ext DSP (mul (ext DI B) (ext DI (and C #x-10000)))))
+ (set vbit (not (srl (xor old tmp) 63)))
+ (set tmp (add old tmp))
+ (set cur_s1bit (and vbit (xor old tmp)))
+ (cond (cur_s1bit (set tmp (xor (sra old 63) (srl -1 1)))))
+ (set (reg h-cr 57) (subword SI tmp 1))
+ (set (reg h-cr 56) (subword SI tmp 0))
+ (subword SI tmp 0))
+ (flagNZVS)
+)
+
+(dgoi mululw X05_MULULW ()
+ (sequence SI ((DI tmp))
+ (set tmp (mach-ext DSP (mul (zext DI B) (zext DI (and C #xffff)))))
+ (set (reg h-cr 57) (subword SI tmp 1))
+ (set (reg h-cr 56) (subword SI tmp 0))
+ (sat32 tmp))
+ (flagNZVS)
+)
+
+(dgoi machulw X05_MACHULW ()
+ (sequence SI ((DI old) (DI tmp))
+ (set old (add (sll (zext DI (reg h-cr 56)) 32) (zext DI (reg h-cr 57))))
+ (set tmp (mach-ext DSP (mul (zext DI B) (zext DI (and C #x-10000)))))
+ (set tmp (add old tmp))
+ (set cur_s1bit
+ (cond BI
+ ((gtu old tmp)
+ (sequence BI () (set tmp -1) 1))
+ (else 0)))
+ (set (reg h-cr 57) (subword SI tmp 1))
+ (set (reg h-cr 56) (subword SI tmp 0))
+ (subword SI tmp 0))
+ (flagNZVS)
+)
+
+(define-insn
+ (name current_loop_end)
+ (comment "pseudo insn for zero-overhead loop end")
+ (attrs)
+ ;(syntax xsyntax)
+ ; FIXME: ??? this should not have a format
+ (format (+ OPM_GO GO_TYPE_R_R GO_OP_SOP F0 GO_OP_SOP_PSEUDO RB_0 RC))
+ (semantics
+ (if (and (eq pc (aux-lp_end)) (not lbit)) ; double-check lp_end
+ (sequence ()
+ (set (reg h-cr 60) (add (reg h-cr 60) -1)) ; decrement lp_count
+ (if (reg h-cr 60) ; test lp_count
+ (int-timer1 (aux-lp_start) 0
+ (set pc (aux-lp_start)))) ; jump to lp_start
+ )
+ )
+ )
+)
+
+; a zero-overhead loop end can't trigger at the start of a pbb. If the
+; preceding instruction is a branch, we must put it in the same pbb,
+; thus postponing the branch decision till we see the loop end.
+(define-insn
+ (name current_loop_end_after_branch)
+ (comment "pseudo insn for zero-overhead loop end ending after branch")
+ (attrs)
+ ;(syntax xsyntax)
+ ; FIXME: ??? this should not have a format
+ (format (+ OPM_GO GO_TYPE_R_R GO_OP_SOP F0 GO_OP_SOP_PSEUDO RB_0 RC))
+ (semantics
+ (cond
+ ( (c-code SI "\n#ifdef SEM_IN_SWITCH\npbb_br_type != SEM_BRANCH_UNTAKEN\n#else\nCPU_PBB_BR_NPC (current_cpu) != SEM_BRANCH_UNTAKEN\n#endif\n")
+ (c-code "\n#ifdef SEM_IN_SWITCH\nnpc = pbb_br_npc; br_type = pbb_br_type;\n#else\nnpc = CPU_PBB_BR_NPC (current_cpu); br_type = CPU_PBB_BR_TYPE (current_cpu);\n#endif\n"))
+ ( (and (eq pc (aux-lp_end)) (not lbit)) ; double-check lp_end
+ (sequence ()
+ (set (reg h-cr 60) (add (reg h-cr 60) -1)) ; decrement lp_count
+ (if (reg h-cr 60) ; test lp_count
+ (int-timer1 (aux-lp_start) 0
+ (set pc (aux-lp_start)))) ; jump to lp_start
+ )
+ )
+ )
+ )
+)
+
+; like current_loop_end_after_branch, but model arc600 idiosyncrasy:
+; decrement lp_count even if branch is taken.
+(define-insn
+ (name arc600_current_loop_end_after_branch)
+ (comment "pseudo insn for zero-overhead loop end ending after branch")
+ (attrs)
+ ;(syntax xsyntax)
+ ; FIXME: ??? this should not have a format
+ (format (+ OPM_GO GO_TYPE_R_R GO_OP_SOP F0 GO_OP_SOP_PSEUDO RB_0 RC))
+ (semantics
+ (cond
+ ( (c-code SI "\n#ifdef SEM_IN_SWITCH\npbb_br_type != SEM_BRANCH_UNTAKEN\n#else\nCPU_PBB_BR_NPC (current_cpu) != SEM_BRANCH_UNTAKEN\n#endif\n")
+ (sequence ()
+ (c-code "\n#ifdef SEM_IN_SWITCH\nnpc = pbb_br_npc; br_type = pbb_br_type;\n#else\nnpc = CPU_PBB_BR_NPC (current_cpu); br_type = CPU_PBB_BR_TYPE (current_cpu);\n#endif\n")
+ (set (reg h-cr 60) (add (reg h-cr 60) -1)))) ; decrement lp_count
+ ( (and (eq pc (aux-lp_end)) (not lbit)) ; double-check lp_end
+ (sequence ()
+ (set (reg h-cr 60) (add (reg h-cr 60) -1)) ; decrement lp_count
+ (if (reg h-cr 60) ; test lp_count
+ (int-timer1 (aux-lp_start) 0
+ (set pc (aux-lp_start)))) ; jump to lp_start
+ )
+ )
+ )
+ )
+)
diff --git a/cpu/ChangeLog b/cpu/ChangeLog
index 707c585..405ee77 100644
--- a/cpu/ChangeLog
+++ b/cpu/ChangeLog
@@ -1,3 +1,7 @@
+2009-03-09 J"orn Rennecke <joern.rennecke@arc.com>
+
+ * arc.opc, sh-sim.cpu, arc.cpu, ARCompact.cpu: New files.
+
2008-01-29 Alan Modra <amodra@bigpond.net.au>
* mt.opc (parse_imm16): Apply 2007-09-26 opcodes/mt-asm.c change
diff --git a/cpu/arc.cpu b/cpu/arc.cpu
new file mode 100644
index 0000000..f791e9e
--- /dev/null
+++ b/cpu/arc.cpu
@@ -0,0 +1 @@
+(include "ARCompact.cpu")
diff --git a/cpu/arc.opc b/cpu/arc.opc
new file mode 100644
index 0000000..10fbf0b
--- /dev/null
+++ b/cpu/arc.opc
@@ -0,0 +1,364 @@
+/* ARC opcode support. -*- C -*-
+ Copyright 1998, 1999, 2000, 2001, 2004, 2005, 2007, 2008
+ Free Software Foundation, Inc.
+ This file is part of CGEN.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
+
+/* This file is an addendum to arc.cpu. Heavy use of C code isn't
+ appropriate in .cpu files, so it resides here. This especially applies
+ to assembly/disassembly where parsing/printing can be quite involved.
+ Such things aren't really part of the specification of the cpu, per se,
+ so .cpu files provide the general framework and .opc files handle the
+ nitty-gritty details as necessary.
+
+ Each section is delimited with start and end markers.
+
+ <arch>-opc.h additions use: "-- opc.h"
+ <arch>-opc.c additions use: "-- opc.c"
+ <arch>-asm.c additions use: "-- asm.c"
+ <arch>-dis.c additions use: "-- dis.c"
+ <arch>-ibd.h additions use: "-- ibd.h" */
+
+ /* Copyright (C) 2000, 2001, 2004, 2005 Red Hat, Inc. */
+/* -- opc.h */
+
+#undef CGEN_DIS_HASH_SIZE
+#define CGEN_DIS_HASH_SIZE 1024
+#undef CGEN_DIS_HASH
+#define CGEN_DIS_HASH(buffer, value, big_p) \
+ arc_cgen_dis_hash (buffer, big_p)
+extern unsigned int arc_cgen_dis_hash (const char *, int);
+/* Override CGEN_INSN_BITSIZE for sim/common/cgen-trace.c .
+ insn extraction for simulation is fine with 32 bits, since we fetch long
+ immediates as part of the semantics if required, but for disassembly
+ we must make sure we read all the bits while we have the information how
+ to read them. */
+#define CGEN_INSN_DISASM_BITSIZE(insn) 64
+extern char limm_str[];
+
+/* cgen can't generate correct decoders for variable-length insns,
+ so we have it generate a decoder that assumes all insns are 32 bit.
+ And even if the decoder generator bug were fixed, having the decoder
+ understand long immediates would be messy.
+ The simulator calculates instruction sizes as part of the semantics.
+ For disassembly, we redefine CGEN_EXTRACT_FN so that we can correct
+ the calculated instruction length. */
+#undef CGEN_EXTRACT_FN
+#define CGEN_EXTRACT_FN(cd, insn) ARC_CGEN_EXTRACT_FN
+extern int arc_insn_length (unsigned long insn_value, const CGEN_INSN *insn,
+ CGEN_EXTRACT_INFO *info, bfd_vma pc);
+static inline int
+ARC_CGEN_EXTRACT_FN (CGEN_CPU_DESC cd, const CGEN_INSN *insn,
+ CGEN_EXTRACT_INFO *info, CGEN_INSN_INT insn_value,
+ CGEN_FIELDS *fields, bfd_vma pc)
+{
+ static int initialized = 0;
+ /* ??? There is no suitable hook for one-time initialization. */
+ if (!initialized)
+ {
+ static CGEN_KEYWORD_ENTRY arc_cgen_opval_limm_entry0 =
+ { limm_str, 62, {0, {{{0, 0}}}}, 0, 0 };
+ static CGEN_KEYWORD_ENTRY arc_cgen_opval_limm_entry1 =
+ { limm_str, 62, {0, {{{0, 0}}}}, 0, 0 };
+
+ cgen_keyword_add (&arc_cgen_opval_cr_names, &arc_cgen_opval_limm_entry0);
+ cgen_keyword_add (&arc_cgen_opval_h_noilink, &arc_cgen_opval_limm_entry1);
+ initialized = 1;
+ }
+ /* ??? sim/common/cgen-trace.c:sim_cgen_disassemble_insn uses its own
+ home-brewn instruction target-to-host conversion, which gets the
+ endianness wrong for ARC. */
+ if (cd->endian == CGEN_ENDIAN_LITTLE)
+ insn_value = ((insn_value >> 16) & 0xffff) | (insn_value << 16);
+
+ /* First, do the normal extract handler call, but ignore its value. */
+ ((cd)->extract_handlers[(insn)->opcode->handlers.extract]
+ (cd, insn, info, insn_value, fields, pc));
+ /* Now calculate the actual insn length, and extract any long immediate
+ if present. */
+ return arc_insn_length (insn_value, insn, info, pc);
+}
+
+/* -- */
+
+/* -- opc.c */
+unsigned int
+arc_cgen_dis_hash (const char * buf, int big_p)
+{
+ const unsigned char *ubuf = (unsigned const char *) buf;
+ int b0 = ubuf[0], b1 = ubuf[1], w;
+
+ if (big_p)
+ w = (b0 << 8) + b1;
+ else
+ w = (b1 << 8) + b0;
+
+ switch (w >> 11)
+ {
+ case 0x01: /* branches */
+ return ((w >> 6) | w);
+ case 0x04: /* general operations */
+ case 0x05: case 0x06: case 0x07: /* 32 bit extension instructions */
+ return ((w >> 3) & 768) | (w & 255);
+ case 0x0c: /* .s load/add register-register */
+ case 0x0d: /* .s add/sub/shift register-immediate */
+ case 0x0e: /* .s mov/cmp/add with high register */
+ return ((w >> 6) & 992) | (w & 24);
+ case 0x0f: /* 16 bit general operations */
+ return ((w >> 6) & 992) | (w & 31);
+ case 0x17: /* .s shift/subtract/bit immediate */
+ case 0x18: /* .s stack-pointer based */
+ return ((w >> 6) & 992) | ((w >> 5) & 7);
+ case 0x19: /* load/add GP-relative */
+ case 0x1e: /* branch conditionally */
+ return ((w >> 6) & (992 | 24));
+ case 0x1c: /* add/cmp immediate */
+ case 0x1d: /* branch on compare register with zero */
+ return ((w >> 6) & (992 | 2));
+ default:
+ return ((w >> 6) & 992);
+ }
+}
+
+/* -- */
+
+/* -- asm.c */
+#if 0
+static const char * MISSING_CLOSING_PARENTHESIS = N_("missing `)'");
+
+/* Handle '#' prefixes (i.e. skip over them). */
+
+static const char *
+parse_hash (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ const char **strp,
+ int opindex ATTRIBUTE_UNUSED,
+ long *valuep ATTRIBUTE_UNUSED)
+{
+ if (**strp == '#')
+ ++*strp;
+ return NULL;
+}
+
+/* Handle shigh(), high(). */
+
+static const char *
+parse_hi16 (CGEN_CPU_DESC cd,
+ const char **strp,
+ int opindex,
+ unsigned long *valuep)
+{
+ const char *errmsg;
+ enum cgen_parse_operand_result result_type;
+ bfd_vma value;
+
+ if (**strp == '#')
+ ++*strp;
+
+ if (strncasecmp (*strp, "high(", 5) == 0)
+ {
+ *strp += 5;
+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_HI16_ULO,
+ & result_type, & value);
+ if (**strp != ')')
+ return MISSING_CLOSING_PARENTHESIS;
+ ++*strp;
+ if (errmsg == NULL
+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+ {
+ value >>= 16;
+ value &= 0xffff;
+ }
+ *valuep = value;
+ return errmsg;
+ }
+ else if (strncasecmp (*strp, "shigh(", 6) == 0)
+ {
+ *strp += 6;
+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_HI16_SLO,
+ & result_type, & value);
+ if (**strp != ')')
+ return MISSING_CLOSING_PARENTHESIS;
+ ++*strp;
+ if (errmsg == NULL
+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+ {
+ value += 0x8000;
+ value >>= 16;
+ value &= 0xffff;
+ }
+ *valuep = value;
+ return errmsg;
+ }
+
+ return cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
+}
+
+/* Handle low() in a signed context. Also handle sda().
+ The signedness of the value doesn't matter to low(), but this also
+ handles the case where low() isn't present. */
+
+static const char *
+parse_slo16 (CGEN_CPU_DESC cd,
+ const char ** strp,
+ int opindex,
+ long * valuep)
+{
+ const char *errmsg;
+ enum cgen_parse_operand_result result_type;
+ bfd_vma value;
+
+ if (**strp == '#')
+ ++*strp;
+
+ if (strncasecmp (*strp, "low(", 4) == 0)
+ {
+ *strp += 4;
+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_LO16,
+ & result_type, & value);
+ if (**strp != ')')
+ return MISSING_CLOSING_PARENTHESIS;
+ ++*strp;
+ if (errmsg == NULL
+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+ value = ((value & 0xffff) ^ 0x8000) - 0x8000;
+ *valuep = value;
+ return errmsg;
+ }
+
+ if (strncasecmp (*strp, "sda(", 4) == 0)
+ {
+ *strp += 4;
+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_SDA16,
+ NULL, & value);
+ if (**strp != ')')
+ return MISSING_CLOSING_PARENTHESIS;
+ ++*strp;
+ *valuep = value;
+ return errmsg;
+ }
+
+ return cgen_parse_signed_integer (cd, strp, opindex, valuep);
+}
+
+/* Handle low() in an unsigned context.
+ The signedness of the value doesn't matter to low(), but this also
+ handles the case where low() isn't present. */
+
+static const char *
+parse_ulo16 (CGEN_CPU_DESC cd,
+ const char **strp,
+ int opindex,
+ unsigned long *valuep)
+{
+ const char *errmsg;
+ enum cgen_parse_operand_result result_type;
+ bfd_vma value;
+
+ if (**strp == '#')
+ ++*strp;
+
+ if (strncasecmp (*strp, "low(", 4) == 0)
+ {
+ *strp += 4;
+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_LO16,
+ & result_type, & value);
+ if (**strp != ')')
+ return MISSING_CLOSING_PARENTHESIS;
+ ++*strp;
+ if (errmsg == NULL
+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+ value &= 0xffff;
+ *valuep = value;
+ return errmsg;
+ }
+
+ return cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
+}
+#endif
+
+/* -- */
+
+/* -- dis.c */
+char limm_str[11] = "0x";
+
+/* Read a long immediate and write it hexadecimally into limm_str. */
+static void
+read_limm (CGEN_EXTRACT_INFO *ex_info, bfd_vma pc)
+{
+ unsigned char buf[2];
+ int i;
+ char *limmp = limm_str + 2;
+ disassemble_info *dis_info = (disassemble_info *) ex_info->dis_info;
+
+ for (i = 0; i < 2; i++, limmp +=4, pc += 2)
+ {
+ int status = (*dis_info->read_memory_func) (pc, buf, 2, dis_info);
+
+ if (status != 0)
+ (*dis_info->memory_error_func) (status, pc, dis_info);
+ sprintf (limmp, "%.4x",
+ (unsigned) bfd_get_bits (buf, 16,
+ dis_info->endian == BFD_ENDIAN_BIG));
+ }
+}
+
+/* Return the actual instruction length, in bits, which depends on the size
+ of the opcode - 2 or 4 bytes - and the absence or presence of a (4 byte)
+ long immediate.
+ Also, if a long immediate is present, put its hexadecimal representation
+ into limm_str.
+ ??? cgen-opc.c:cgen_lookup_insn has a 'sanity' check of the length
+ that will fail if its input length differs from the result of
+ CGEN_EXTRACT_FN. Need to check when this could trigger. */
+int
+arc_insn_length (unsigned long insn_value, const CGEN_INSN *insn,
+ CGEN_EXTRACT_INFO *info, bfd_vma pc)
+{
+ switch (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_LIMM))
+ {
+ case LIMM_NONE:
+ return CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_SHORT_P) ? 16 : 32;
+ case LIMM_H:
+ {
+ /* This is a short insn; extract the actual opcode. */
+ unsigned high = insn_value >> 16;
+
+ if ((high & 0xe7) != 0xc7)
+ return 16;
+ read_limm (info, pc+2);
+ return 48;
+ }
+ case LIMM_B:
+ if ((insn_value & 0x07007000) != 0x06007000)
+ return 32;
+ break;
+ case LIMM_BC:
+ if ((insn_value & 0x07007000) == 0x06007000)
+ break;
+ /* Fall through. */
+ case LIMM_C:
+ if ((insn_value & 0x00000fc0) != 0x00000f80)
+ return 32;
+ break;
+ default:
+ abort ();
+ }
+ read_limm (info, pc+4);
+ return 64;
+}
+
+/* -- */
diff --git a/cpu/sh-sim.cpu b/cpu/sh-sim.cpu
new file mode 100644
index 0000000..878a139
--- /dev/null
+++ b/cpu/sh-sim.cpu
@@ -0,0 +1,46 @@
+; SuperH SHcompact instruction set description. -*- Scheme -*-
+; Copyright (C) 2006 Red Hat, Inc.
+; This file is part of CGEN.
+; See file COPYING.CGEN for details.
+
+; Syntax for "delay" is different for SID vs SIM.
+(define-pmacro (set-delay del targ src)
+ (delay del (set targ src)))
+
+; SIM does not use parallel insns to implement "delay".
+(define-pmacro (isa-parallel-insns n)
+ (parallel-insns 1)
+)
+
+; Not needed for the sim.
+(define-pmacro (save-delayed-pc disp)
+ (nop)
+)
+
+(define-pmacro (save-branch-prediction tra likely)
+ (nop)
+)
+
+(define-pmacro (save-branch-optimization likely)
+ (nop)
+)
+
+(define-pmacro (save-cfg-address address)
+ (nop)
+)
+
+; For making profiling calls and dynamic configuration.
+(define-pmacro (cg-profile caller callee)
+ (nop)
+)
+(define-pmacro (cg-profile-delay caller callee delay)
+ (nop)
+)
+(define-pmacro (notify-ret pr)
+ (nop)
+)
+; For dynamic configuration only.
+(define-pmacro (cg-profile-jump caller callee)
+ (nop)
+)
+
diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index a9db051..dd56c13 100644
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,3 +1,8 @@
+2009-03-09 J"orn Rennecke <joern.rennecke@arc.com>
+
+ * configure.tgt: Add arc case.
+ * config/arc: Old / new directory.
+
2008-03-27 Joel Brobecker <brobecker@adacore.com>
* NEWS: Replace "Changes since GDB 6.7" into changes in GDB 6.8".
diff --git a/gdb/Makefile.in b/gdb/Makefile.in
index 2373562..f526073 100644
--- a/gdb/Makefile.in
+++ b/gdb/Makefile.in
@@ -657,6 +657,7 @@
elf_reloc_macros_h = $(INCLUDE_DIR)/elf/reloc-macros.h
elf_sh_h = $(INCLUDE_DIR)/elf/sh.h
elf_arm_h = $(INCLUDE_DIR)/elf/arm.h $(elf_reloc_macros_h)
+elf_arc_h = $(INCLUDE_DIR)/elf/arc.h $(elf_reloc_macros_h)
elf_bfd_h = $(BFD_SRC)/elf-bfd.h
elf_frv_h = $(INCLUDE_DIR)/elf/frv.h $(elf_reloc_macros_h)
elf_m32c_h = $(INCLUDE_DIR)/elf/m32c.h $(elf_reloc_macros_h)
@@ -669,6 +670,7 @@
demangle_h = $(INCLUDE_DIR)/demangle.h
obstack_h = $(INCLUDE_DIR)/obstack.h
opcode_m68hc11_h = $(INCLUDE_DIR)/opcode/m68hc11.h
+opcode_arc_h = $(INCLUDE_DIR)/opcode/arc.h
readline_h = $(READLINE_SRC)/readline.h
readline_tilde_h = $(READLINE_SRC)/tilde.h
readline_history_h = $(READLINE_SRC)/history.h
@@ -729,6 +731,10 @@
arch_utils_h = arch-utils.h
arm_linux_tdep_h = arm-linux-tdep.h
arm_tdep_h = arm-tdep.h
+arc_tdep_h = arc-tdep.h
+arc_jtag_h = arc-jtag.h
+arc_jtag_ops_h = arc-jtag-ops.h
+arc_regnums_defs_h = arc-regnums-defs.h
auxv_h = auxv.h
ax_gdb_h = ax-gdb.h
ax_h = ax.h $(doublest_h)
@@ -1529,6 +1535,8 @@
amd64obsd-nat.c amd64obsd-tdep.c \
amd64-linux-nat.c amd64-linux-tdep.c \
amd64-sol2-tdep.c \
+ arc-tdep.c arc-linux-tdep.c arc-jtag.c \
+ arc-jtag-ops.c arc-jtag.c \
arm-linux-nat.c arm-linux-tdep.c arm-tdep.c \
armnbsd-nat.c armbsd-tdep.c armnbsd-tdep.c armobsd-tdep.c \
avr-tdep.c \
@@ -1893,6 +1901,20 @@
$(gdbcmd_h) $(inferior_h) $(gdb_string_h) $(regcache_h) \
$(gdb_assert_h) $(sim_regno_h) $(gdbcore_h) $(osabi_h) $(version_h) \
$(floatformat_h) $(target_descriptions_h)
+arc-jtag.o:arc-jtag.c $(arc_jtag_h) $(defs_h) $(gdbcore_h) \
+ $(arc_regnums_defs_h) $(gdbcmd_h)
+arc-jtag-ops.o: arc-jtag-ops.c $(arc_jtag_ops_h) $(arc_tdep_h)
+arc-jtag-tdep.o:arc-jtag-tdep.c $(arc_tdep_h) $(arc_jtag_h) $(defs_h) \
+ $(osabi_h) $(frame_h) $(regcache_h) $(gdb_assert_h) $(inferior_h) \
+ $(arc_tdep_h) $(arc_jtag_h)
+arc-linux-tdep.o: arc-linux-tdep.c $(defs_h) $(osabi_h) $(frame_h) \
+ $(regcache_h) $(gdb_assert_h) $(inferior_h) $(reggroups_h) \
+ $(solib_svr4_h) $(symtab_h) $(objfiles_h) $(block_h) $(arc_tdep_h)
+arc-tdep.o: arc-tdep.c $(defs_h) $(arch_utils_h) $(frame_h) $(inferior_h) \
+ $(gdbcmd_h) $(gdbcore_h) $(gdb_string_h) $(dis_asm_h) $(regcache_h) \
+ $(doublest_h) $(value_h) $(frame_unwind_h) $(frame_base_h) \
+ $(trad_frame_h) $(arc_tdep_h) $(elf_bfd_h) $(elf_arc_h) \
+ $(opcode_arc_h) $(gdb_assert_h) $(bfd_in2_h) $(observer_h)
arm-linux-nat.o: arm-linux-nat.c $(defs_h) $(inferior_h) $(gdbcore_h) \
$(gdb_string_h) $(regcache_h) $(arm_tdep_h) $(gregset_h) \
$(target_h) $(linux_nat_h) $(gdb_proc_service_h) $(arm_linux_tdep_h) \
diff --git a/gdb/config/arc/a4-jtag.mt b/gdb/config/arc/a4-jtag.mt
new file mode 100644
index 0000000..e3907ba
--- /dev/null
+++ b/gdb/config/arc/a4-jtag.mt
@@ -0,0 +1,3 @@
+# Target: ARC embedded system
+TDEPFILES= arc-tdep.o arc-jtag.o arc-jtag-tdep.o arc-jtag-ops.o
+DEPRECATED_TM_FILE= tm-a4-jtag.h
diff --git a/gdb/config/arc/arc.mt b/gdb/config/arc/arc.mt
new file mode 100644
index 0000000..cb98a49
--- /dev/null
+++ b/gdb/config/arc/arc.mt
@@ -0,0 +1,4 @@
+# Target: arc processor
+TDEPFILES= arc-tdep.o monitor.o arc-rom.o dsrec.o remote-arc-sdi.o
+SIM_OBS = remote-sim.o
+SIM = ../sim/arc/libsim.a
diff --git a/gdb/config/arc/embed.mt b/gdb/config/arc/embed.mt
new file mode 100644
index 0000000..a6d47a2
--- /dev/null
+++ b/gdb/config/arc/embed.mt
@@ -0,0 +1,3 @@
+# Target: ARC embedded system
+TDEPFILES= arc-tdep.o arc-jtag.o arc-jtag-tdep.o arc-jtag-ops.o
+DEPRECATED_TM_FILE= tm-embed.h
diff --git a/gdb/config/arc/linux.mt b/gdb/config/arc/linux.mt
new file mode 100644
index 0000000..0c5f000
--- /dev/null
+++ b/gdb/config/arc/linux.mt
@@ -0,0 +1,3 @@
+# Target: ARC based machine running GNU/Linux
+DEPRECATED_TM_FILE= tm-linux.h
+TDEPFILES= arc-tdep.o arc-linux-tdep.o solib.o solib-svr4.o solib-legacy.o corelow.o
diff --git a/gdb/config/arc/tm-a4-jtag.h b/gdb/config/arc/tm-a4-jtag.h
new file mode 100644
index 0000000..dc5ab71
--- /dev/null
+++ b/gdb/config/arc/tm-a4-jtag.h
@@ -0,0 +1,103 @@
+#define ARC4_JTAG 1
+#define CONFIG_OSABI GDB_OSABI_UNKNOWN
+
+struct gdbarch *arc_jtag_init (struct gdbarch *gdbarch);
+#define CONFIG_INIT_TDEP arc_jtag_init
+
+/* The core regnums here are the same as the hardware register numbers. We
+ cannot do that for aux registers, because the aux regs on the h/w do not
+ have contiguous numbers. */
+enum arc4_jtag_regnums
+ {
+ ARC_FP_REGNUM = 27,
+ ARC_SP_REGNUM ,
+ ARC_ILINK1_REGNUM ,
+ ARC_ILINK2_REGNUM ,
+ ARC_BLINK_REGNUM ,
+ /* Extension core regs are 32..59 inclusive. */
+ ARC_LP_COUNT_REGNUM = 60,
+ /* 61 is reserved, 62 is not a real register. */
+ ARC_PCL_REGNUM = 63,
+
+ /* Now the aux registers. */
+
+ ARC_STATUS_REGNUM = 64,
+ ARC_SEMAPHORE_REGNUM ,
+ ARC_LP_START_REGNUM ,
+ ARC_LP_END_REGNUM ,
+ ARC_IDENTITY_REGNUM ,
+ ARC_DEBUG_REGNUM ,
+#ifndef ARC4_JTAG
+ ARC_PC_REGNUM ,
+ ARC_STATUS32_REGNUM ,
+ ARC_STATUS32_L1_REGNUM ,
+ ARC_STATUS32_L2_REGNUM ,
+
+ ARC_COUNT0_REGNUM ,
+ ARC_CONTROL0_REGNUM ,
+ ARC_LIMIT0_REGNUM ,
+ ARC_INT_VECTOR_BASE_REGNUM ,
+ ARC_AUX_MACMODE_REGNUM ,
+ ARC_AUX_IRQ_LV12_REGNUM ,
+
+ ARC_COUNT1_REGNUM ,
+ ARC_CONTROL1_REGNUM ,
+ ARC_LIMIT1_REGNUM ,
+ ARC_AUX_IRQ_LEV_REGNUM ,
+ ARC_AUX_IRQ_HINT_REGNUM ,
+ ARC_ERET_REGNUM ,
+ ARC_ERBTA_REGNUM ,
+ ARC_ERSTATUS_REGNUM ,
+ ARC_ECR_REGNUM ,
+ ARC_EFA_REGNUM ,
+ ARC_ICAUSE1_REGNUM ,
+ ARC_ICAUSE2_REGNUM ,
+ ARC_AUX_IENABLE_REGNUM ,
+ ARC_AUX_ITRIGGER_REGNUM ,
+ ARC_XPU_REGNUM ,
+ ARC_BTA_REGNUM ,
+ ARC_BTA_L1_REGNUM ,
+ ARC_BTA_L2_REGNUM ,
+ ARC_AUX_IRQ_PULSE_CANCEL_REGNUM ,
+ ARC_AUX_IRQ_PENDING_REGNUM ,
+
+ /* Build configuration registers. */
+ ARC_BCR_0_REGNUM ,
+ ARC_BCR_1_REGNUM ,
+ ARC_BCR_2_REGNUM ,
+ ARC_BCR_3_REGNUM ,
+ ARC_BCR_4_REGNUM ,
+ ARC_BCR_5_REGNUM ,
+ ARC_BCR_6_REGNUM ,
+ ARC_BCR_7_REGNUM ,
+ ARC_BCR_8_REGNUM ,
+ ARC_BCR_9_REGNUM ,
+ ARC_BCR_A_REGNUM ,
+ ARC_BCR_B_REGNUM ,
+ ARC_BCR_C_REGNUM ,
+ ARC_BCR_D_REGNUM ,
+ ARC_BCR_E_REGNUM ,
+ ARC_BCR_F_REGNUM ,
+ ARC_BCR_10_REGNUM ,
+ ARC_BCR_11_REGNUM ,
+ ARC_BCR_12_REGNUM ,
+
+ ARC_BCR_13_REGNUM ,
+ ARC_BCR_14_REGNUM ,
+ ARC_BCR_15_REGNUM ,
+ ARC_BCR_16_REGNUM ,
+ ARC_BCR_17_REGNUM ,
+ ARC_BCR_18_REGNUM ,
+ ARC_BCR_19_REGNUM ,
+ ARC_BCR_1A_REGNUM ,
+ ARC_BCR_1B_REGNUM ,
+ ARC_BCR_1C_REGNUM ,
+ ARC_BCR_1D_REGNUM ,
+ ARC_BCR_1E_REGNUM ,
+ ARC_BCR_1F_REGNUM ,
+
+#endif
+ ARC_NR_REGS
+
+ };
+
diff --git a/gdb/config/arc/tm-embed.h b/gdb/config/arc/tm-embed.h
new file mode 100644
index 0000000..9ac1c1a
--- /dev/null
+++ b/gdb/config/arc/tm-embed.h
@@ -0,0 +1,101 @@
+
+#define CONFIG_OSABI GDB_OSABI_UNKNOWN
+
+struct gdbarch *arc_jtag_init (struct gdbarch *gdbarch);
+#define CONFIG_INIT_TDEP arc_jtag_init
+
+/* The core regnums here are the same as the hardware register numbers. We
+ cannot do that for aux registers, because the aux regs on the h/w do not
+ have contiguous numbers. */
+enum arc700_jtag_regnums
+ {
+ ARC_FP_REGNUM = 27,
+ ARC_SP_REGNUM ,
+ ARC_ILINK1_REGNUM ,
+ ARC_ILINK2_REGNUM ,
+ ARC_BLINK_REGNUM ,
+ /* Extension core regs are 32..59 inclusive. */
+ ARC_LP_COUNT_REGNUM = 60,
+ /* 61 is reserved, 62 is not a real register. */
+ ARC_PCL_REGNUM = 63,
+
+ /* Now the aux registers. */
+
+ ARC_STATUS_REGNUM = 64,
+ ARC_SEMAPHORE_REGNUM ,
+ ARC_LP_START_REGNUM ,
+ ARC_LP_END_REGNUM ,
+ ARC_IDENTITY_REGNUM ,
+ ARC_DEBUG_REGNUM ,
+ ARC_PC_REGNUM ,
+ ARC_STATUS32_REGNUM ,
+ ARC_STATUS32_L1_REGNUM ,
+ ARC_STATUS32_L2_REGNUM ,
+
+ ARC_COUNT0_REGNUM ,
+ ARC_CONTROL0_REGNUM ,
+ ARC_LIMIT0_REGNUM ,
+ ARC_INT_VECTOR_BASE_REGNUM ,
+ ARC_AUX_MACMODE_REGNUM ,
+ ARC_AUX_IRQ_LV12_REGNUM ,
+
+ ARC_COUNT1_REGNUM ,
+ ARC_CONTROL1_REGNUM ,
+ ARC_LIMIT1_REGNUM ,
+ ARC_AUX_IRQ_LEV_REGNUM ,
+ ARC_AUX_IRQ_HINT_REGNUM ,
+ ARC_ERET_REGNUM ,
+ ARC_ERBTA_REGNUM ,
+ ARC_ERSTATUS_REGNUM ,
+ ARC_ECR_REGNUM ,
+ ARC_EFA_REGNUM ,
+ ARC_ICAUSE1_REGNUM ,
+ ARC_ICAUSE2_REGNUM ,
+ ARC_AUX_IENABLE_REGNUM ,
+ ARC_AUX_ITRIGGER_REGNUM ,
+ ARC_XPU_REGNUM ,
+ ARC_BTA_REGNUM ,
+ ARC_BTA_L1_REGNUM ,
+ ARC_BTA_L2_REGNUM ,
+ ARC_AUX_IRQ_PULSE_CANCEL_REGNUM ,
+ ARC_AUX_IRQ_PENDING_REGNUM ,
+
+ /* Build configuration registers. */
+ ARC_BCR_0_REGNUM ,
+ ARC_BCR_1_REGNUM ,
+ ARC_BCR_2_REGNUM ,
+ ARC_BCR_3_REGNUM ,
+ ARC_BCR_4_REGNUM ,
+ ARC_BCR_5_REGNUM ,
+ ARC_BCR_6_REGNUM ,
+ ARC_BCR_7_REGNUM ,
+ ARC_BCR_8_REGNUM ,
+ ARC_BCR_9_REGNUM ,
+ ARC_BCR_A_REGNUM ,
+ ARC_BCR_B_REGNUM ,
+ ARC_BCR_C_REGNUM ,
+ ARC_BCR_D_REGNUM ,
+ ARC_BCR_E_REGNUM ,
+ ARC_BCR_F_REGNUM ,
+ ARC_BCR_10_REGNUM ,
+ ARC_BCR_11_REGNUM ,
+ ARC_BCR_12_REGNUM ,
+
+ ARC_BCR_13_REGNUM ,
+ ARC_BCR_14_REGNUM ,
+ ARC_BCR_15_REGNUM ,
+ ARC_BCR_16_REGNUM ,
+ ARC_BCR_17_REGNUM ,
+ ARC_BCR_18_REGNUM ,
+ ARC_BCR_19_REGNUM ,
+ ARC_BCR_1A_REGNUM ,
+ ARC_BCR_1B_REGNUM ,
+ ARC_BCR_1C_REGNUM ,
+ ARC_BCR_1D_REGNUM ,
+ ARC_BCR_1E_REGNUM ,
+ ARC_BCR_1F_REGNUM ,
+
+
+ ARC_NR_REGS
+ };
+
diff --git a/gdb/config/arc/tm-linux.h b/gdb/config/arc/tm-linux.h
new file mode 100644
index 0000000..18b1240
--- /dev/null
+++ b/gdb/config/arc/tm-linux.h
@@ -0,0 +1,35 @@
+#include "config/tm-linux.h"
+
+#define CONFIG_OSABI GDB_OSABI_LINUX
+
+/* Do nothing. */
+#define CONFIG_INIT_TDEP {}
+
+enum arc700_linux_regnums
+ {
+ /* Regnums 0..26 are R0..R26 */
+ ARC_BTA_REGNUM = 27,
+ ARC_LP_START_REGNUM = 28,
+ ARC_LP_END_REGNUM = 29,
+ ARC_LP_COUNT_REGNUM = 30,
+ ARC_STATUS32_REGNUM = 31,
+ ARC_BLINK_REGNUM = 32,
+ ARC_FP_REGNUM = 33,
+ ARC_SP_REGNUM = 34,
+ ARC_EFA_REGNUM = 35,
+ ARC_RET_REGNUM = 36,
+ ARC_ORIG_R8_REGNUM = 37,
+ ARC_STOP_PC_REGNUM = 38
+ };
+
+#define ARC_NR_REGS 39
+
+/* Pseudo-regs. */
+#define ARC_ILINK1_REGNUM (NUM_REGS)
+#define ARC_ILINK2_REGNUM (NUM_REGS+1)
+#define ARC_ERET_REGNUM (NUM_REGS+2)
+#define ARC_STATUS32_L1_REGNUM (NUM_REGS+3)
+#define ARC_STATUS32_L2_REGNUM (NUM_REGS+4)
+#define ARC_ERSTATUS_REGNUM (NUM_REGS+5)
+
+#define ARC_NR_PSEUDO_REGS 6
diff --git a/gdb/configure.tgt b/gdb/configure.tgt
index 1dcb833..ccfe674 100644
--- a/gdb/configure.tgt
+++ b/gdb/configure.tgt
@@ -60,6 +60,18 @@
gdb_target_obs="alpha-tdep.o"
;;
+arc*-*-linux*)
+ gdb_target_obs="arc-tdep.o arc-linux-tdep.o solib.o solib-svr4.o \
+ solib-legacy.o corelow.o"
+ build_gdbserver=yes
+ ;;
+arc-a4-*)
+ gdb_target_obs="arc-tdep.o arc-jtag.o arc-jtag-tdep.o arc-jtag-ops.o"
+ ;;
+arc*-*-*)
+ gdb_target_obs="arc-tdep.o arc-jtag.o arc-jtag-tdep.o arc-jtag-ops.o"
+ ;;
+
am33_2.0*-*-linux*)
# Target: Matsushita mn10300 (AM33) running Linux
gdb_target_obs="mn10300-tdep.o mn10300-linux-tdep.o corelow.o \
diff --git a/gdb/doc/Makefile.in b/gdb/doc/Makefile.in
index 141e486..bf67b97 100644
--- a/gdb/doc/Makefile.in
+++ b/gdb/doc/Makefile.in
@@ -110,6 +110,7 @@
$(srcdir)/fdl.texi \
$(srcdir)/gpl.texi \
$(srcdir)/agentexpr.texi \
+ $(srcdir)/arc.texi \
$(READLINE_DIR)/rluser.texi \
$(READLINE_DIR)/inc-hist.texinfo
GDB_DOC_BUILD_INCLUDES = \
diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo
index 9072e2f..876cdd1 100644
--- a/gdb/doc/gdb.texinfo
+++ b/gdb/doc/gdb.texinfo
@@ -14677,6 +14677,7 @@
@menu
+* ARC:: ARC
* ARM:: ARM RDI
* M32R/D:: Renesas M32R/D
* M68K:: Motorola M68K
@@ -14692,6 +14693,8 @@
* Super-H:: Renesas Super-H
@end menu
+@include arc.texi
+
@node ARM
@subsection ARM
@cindex ARM RDI
diff --git a/gdb/dwarf2-frame.c b/gdb/dwarf2-frame.c
index c4cd9f3..8db1b68 100644
--- a/gdb/dwarf2-frame.c
+++ b/gdb/dwarf2-frame.c
@@ -592,6 +592,10 @@
fs->regs.reg[reg].loc.offset = -offset;
break;
+ case DW_CFA_MWARC_info:
+ /* Ignored. */
+ insn_ptr = read_uleb128 (insn_ptr, insn_end, &utmp);
+ break;
default:
internal_error (__FILE__, __LINE__, _("Unknown CFI encountered."));
}
@@ -1715,6 +1719,8 @@
augmentation += 2;
}
+ if (augmentation[0] == 'H' && augmentation [1] == 'C')
+ augmentation += 2;
cie->code_alignment_factor =
read_unsigned_leb128 (unit->abfd, buf, &bytes_read);
buf += bytes_read;
diff --git a/gdb/dwarf2read.c b/gdb/dwarf2read.c
index af9585b..5a53268 100644
--- a/gdb/dwarf2read.c
+++ b/gdb/dwarf2read.c
@@ -782,7 +782,7 @@
struct dwarf2_cu *);
static gdb_byte *read_full_die (struct die_info **, bfd *, gdb_byte *,
- struct dwarf2_cu *, int *);
+ struct dwarf2_cu *, int *, unsigned int);
static gdb_byte *read_attribute (struct attribute *, struct attr_abbrev *,
bfd *, gdb_byte *, struct dwarf2_cu *);
@@ -955,12 +955,14 @@
static struct die_info *read_die_and_children (gdb_byte *info_ptr, bfd *abfd,
struct dwarf2_cu *,
gdb_byte **new_info_ptr,
- struct die_info *parent);
+ struct die_info *parent,
+ unsigned int dwarf2_sibling_offset);
static struct die_info *read_die_and_siblings (gdb_byte *info_ptr, bfd *abfd,
struct dwarf2_cu *,
gdb_byte **new_info_ptr,
- struct die_info *parent);
+ struct die_info *parent,
+ unsigned int dwarf2_sibling_offset);
static void free_die_list (struct die_info *);
@@ -5134,7 +5136,7 @@
static struct die_info *
read_comp_unit (gdb_byte *info_ptr, bfd *abfd, struct dwarf2_cu *cu)
{
- return read_die_and_children (info_ptr, abfd, cu, &info_ptr, NULL);
+ return read_die_and_children (info_ptr, abfd, cu, &info_ptr, NULL, 0);
}
/* Read a single die and all its descendents. Set the die's sibling
@@ -5147,19 +5149,21 @@
read_die_and_children (gdb_byte *info_ptr, bfd *abfd,
struct dwarf2_cu *cu,
gdb_byte **new_info_ptr,
- struct die_info *parent)
+ struct die_info *parent,
+ unsigned int dwarf2_last_sibling_offset)
{
struct die_info *die;
gdb_byte *cur_ptr;
int has_children;
- cur_ptr = read_full_die (&die, abfd, info_ptr, cu, &has_children);
+ cur_ptr = read_full_die (&die, abfd, info_ptr, cu, &has_children,
+ dwarf2_last_sibling_offset);
store_in_ref_table (die->offset, die, cu);
if (has_children)
{
- die->child = read_die_and_siblings (cur_ptr, abfd, cu,
- new_info_ptr, die);
+ die->child = read_die_and_siblings (cur_ptr, abfd, cu, new_info_ptr,
+ die, dwarf2_last_sibling_offset);
}
else
{
@@ -5180,9 +5184,11 @@
read_die_and_siblings (gdb_byte *info_ptr, bfd *abfd,
struct dwarf2_cu *cu,
gdb_byte **new_info_ptr,
- struct die_info *parent)
+ struct die_info *parent,
+ unsigned int dwarf2_last_sibling_offset)
{
struct die_info *first_die, *last_sibling;
+ struct attribute *attr = NULL;
gdb_byte *cur_ptr;
cur_ptr = info_ptr;
@@ -5191,8 +5197,23 @@
while (1)
{
struct die_info *die
- = read_die_and_children (cur_ptr, abfd, cu, &cur_ptr, parent);
+ = read_die_and_children (cur_ptr, abfd, cu, &cur_ptr, parent,
+ dwarf2_last_sibling_offset);
+ int ctr;
+ /* Ramana. Workaround for Metaware compiler bug. We don't
+ use dwarf2_attr here because that follows DW_AT_specification
+ and creates issues for us here.We just need to find
+ the offset of the sibling for this DIE. */
+
+ for (ctr=0; ctr < die->num_attrs ;ctr ++)
+ {
+ if (die->attrs[ctr].name == DW_AT_sibling)
+ {
+ dwarf2_last_sibling_offset = die->attrs[ctr].u.addr;
+ break;
+ }
+ }
if (!first_die)
{
first_die = die;
@@ -5918,13 +5939,22 @@
static gdb_byte *
read_full_die (struct die_info **diep, bfd *abfd, gdb_byte *info_ptr,
- struct dwarf2_cu *cu, int *has_children)
+ struct dwarf2_cu *cu, int *has_children,
+ unsigned int dwarf2_last_sibling_offset)
{
unsigned int abbrev_number, bytes_read, i, offset;
struct abbrev_info *abbrev;
struct die_info *die;
offset = info_ptr - dwarf2_per_objfile->info_buffer;
+
+ /* The Metaware Compiler inserts a padding die in the middle
+ of the debug info. Ignore this till it is corrected. */
+ if (dwarf2_last_sibling_offset && (offset < dwarf2_last_sibling_offset))
+ {
+ info_ptr += (dwarf2_last_sibling_offset - offset);
+ offset = dwarf2_last_sibling_offset;
+ }
abbrev_number = read_unsigned_leb128 (abfd, info_ptr, &bytes_read);
info_ptr += bytes_read;
if (!abbrev_number)
diff --git a/gdb/gdbserver/Makefile.in b/gdb/gdbserver/Makefile.in
index 2c7cb75..d967ff5 100644
--- a/gdb/gdbserver/Makefile.in
+++ b/gdb/gdbserver/Makefile.in
@@ -328,6 +328,9 @@
spu-low.o: spu-low.c $(server_h)
+reg-arc.o : reg-arc.c $(regdef_h)
+reg-arc.c : $(srcdir)/../regformats/reg-arc.dat $(regdat_sh)
+ sh $(regdat_sh) $(srcdir)/../regformats/reg-arc.dat reg-arc.c
reg-arm.o : reg-arm.c $(regdef_h)
reg-arm.c : $(srcdir)/../regformats/reg-arm.dat $(regdat_sh)
$(SHELL) $(regdat_sh) $(srcdir)/../regformats/reg-arm.dat reg-arm.c
diff --git a/gdb/gdbserver/configure.srv b/gdb/gdbserver/configure.srv
index 4f1c22b..c0d246b 100644
--- a/gdb/gdbserver/configure.srv
+++ b/gdb/gdbserver/configure.srv
@@ -26,6 +26,11 @@
# Input is taken from the "${target}" variable.
case "${target}" in
+ arc*-*-linux*) srv_regobj=reg-arc.o
+ srv_tgtobj="linux-low.o linux-arc-low.o"
+ srv_linux_usrregs=yes
+ srv_linux_thread_db=yes
+ ;;
arm*-*-linux*) srv_tgtobj="linux-low.o linux-arm-low.o"
srv_linux_usrregs=yes
srv_linux_regsets=yes
diff --git a/gdb/gdbserver/proc-service.c b/gdb/gdbserver/proc-service.c
index c875313..065bfdf 100644
--- a/gdb/gdbserver/proc-service.c
+++ b/gdb/gdbserver/proc-service.c
@@ -64,9 +64,30 @@
const char *name, psaddr_t *sym_addr)
{
CORE_ADDR addr;
+ char *uscorename;
+
+ /* First try name, then the name with an underscore prepended. Older ARC
+ toolchains prepend an underscore to all symbol names. */
if (look_up_one_symbol (name, &addr) == 0)
- return PS_NOSYM;
+ {
+ int err;
+
+ uscorename = (char *)malloc (strlen(name)+2);
+ if (!uscorename)
+ {
+ fatal ("%s: malloc failed", __FUNCTION__);
+ }
+
+ /* Prepend underscore. */
+ uscorename[0] = '_';
+ strcpy(uscorename+1, name);
+
+ err = look_up_one_symbol (uscorename, &addr);
+ free (uscorename);
+ if (err == 0)
+ return PS_NOSYM;
+ }
*sym_addr = (psaddr_t) (unsigned long) addr;
return PS_OK;
diff --git a/gdb/gdbserver/remote-utils.c b/gdb/gdbserver/remote-utils.c
index 2e049ee..496334c 100644
--- a/gdb/gdbserver/remote-utils.c
+++ b/gdb/gdbserver/remote-utils.c
@@ -169,7 +169,9 @@
}
#endif
-#ifdef HAVE_SGTTY
+/* #ifdef HAVE_SGTTY */
+ /* soam */
+#if 0
{
struct sgttyb sg;
@@ -771,7 +773,8 @@
c1 = fromhex (readchar ());
c2 = fromhex (readchar ());
- if (csum == (c1 << 4) + c2)
+/* if (csum == (c1 << 4) + c2) */
+ if(1) /* (soam) for testing */
break;
fprintf (stderr, "Bad checksum, sentsum=0x%x, csum=0x%x, buf=%s\n",
diff --git a/gdb/remote.c b/gdb/remote.c
index 3f50ff2..ac0d4f9 100644
--- a/gdb/remote.c
+++ b/gdb/remote.c
@@ -2761,6 +2761,7 @@
if (exec_bfd) /* No use without an exec file. */
remote_check_symbols (symfile_objfile);
}
+ observer_notify_inferior_created (¤t_target, from_tty);
}
/* This takes a program previously attached to and detaches it. After
diff --git a/gdb/testsuite/gdb.asm/asm-source.exp b/gdb/testsuite/gdb.asm/asm-source.exp
index 0f531a9..a94fd98 100644
--- a/gdb/testsuite/gdb.asm/asm-source.exp
+++ b/gdb/testsuite/gdb.asm/asm-source.exp
@@ -48,6 +48,12 @@
"*arm-*-*" {
set asm-arch arm
}
+ "arc-*-*" {
+ set asm-arch arc
+ set asm-flags "-I${srcdir}/${subdir} -I${objdir}/${subdir}"
+ set debug-flags "-gdwarf-2"
+ append link-flags " -marclinux"
+ }
"xscale-*-*" {
set asm-arch arm
}
diff --git a/gdb/testsuite/gdb.base/float.exp b/gdb/testsuite/gdb.base/float.exp
index e0f0d9f..ca84466 100644
--- a/gdb/testsuite/gdb.base/float.exp
+++ b/gdb/testsuite/gdb.base/float.exp
@@ -97,6 +97,8 @@
gdb_test "info float" "fr4.*fr4R.*fr31R.*" "info float"
} elseif [istarget "sparc*-*-*"] then {
gdb_test "info float" "f0.*f1.*f31.*d0.*d30.*" "info float"
+} elseif [istarget "arc*-*-*"] then {
+ gdb_test "info float" "Software FPU.*"
} else {
gdb_test "info float" "No floating.point info available for this processor." "info float (unknown target)"
}
diff --git a/gdb/testsuite/lib/gdbserver-support.exp b/gdb/testsuite/lib/gdbserver-support.exp
index 6fbaa22..73de76f 100644
--- a/gdb/testsuite/lib/gdbserver-support.exp
+++ b/gdb/testsuite/lib/gdbserver-support.exp
@@ -250,6 +250,10 @@
proc gdbserver_spawn { child_args } {
set target_exec [gdbserver_download]
+ if [target_info exists tests_dir] {
+ set tests_dir [target_info tests_dir]
+ set gdbserver_server_exec $tests_dir/$gdbserver_server_exec
+ }
# Fire off the debug agent. This flavour of gdbserver takes as
# arguments the port information, the name of the executable file to
# be debugged, and any arguments.
diff --git a/gdb/version.in b/gdb/version.in
index 21afad3..99b56c2 100644
--- a/gdb/version.in
+++ b/gdb/version.in
@@ -1 +1 @@
-6.8
+6.8-arc-20070620
diff --git a/include/ChangeLog b/include/ChangeLog
index fd6c3d2..9ea8f3b 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,12 @@
+2009-03-09 J"orn Rennecke <joern.rennecke@arc.com>
+
+ * opcode/cgen.h (struct cgen_cpu_desc):
+ New int argument for member dis_hash.
+
+ * dis-asm.h (print_insn_arc): Declare.
+
+ * dis-asm.h (arc_get_disassembler): Argument is (bfd *).
+
2008-02-15 Alan Modra <amodra@bigpond.net.au>
* bfdlink.h (struct bfd_link_hash_table): Delete creator field.
diff --git a/include/dis-asm.h b/include/dis-asm.h
index 40afe17..bfe95b1 100644
--- a/include/dis-asm.h
+++ b/include/dis-asm.h
@@ -1,6 +1,6 @@
/* Interface between the opcode library and its callers.
- Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
+ Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
@@ -210,6 +210,7 @@
typedef int (*disassembler_ftype) (bfd_vma, disassemble_info *);
extern int print_insn_alpha (bfd_vma, disassemble_info *);
+extern int print_insn_arc (bfd_vma, disassemble_info *);
extern int print_insn_avr (bfd_vma, disassemble_info *);
extern int print_insn_bfin (bfd_vma, disassemble_info *);
extern int print_insn_big_arm (bfd_vma, disassemble_info *);
@@ -283,7 +284,7 @@
extern int print_insn_z8001 (bfd_vma, disassemble_info *);
extern int print_insn_z8002 (bfd_vma, disassemble_info *);
-extern disassembler_ftype arc_get_disassembler (void *);
+extern disassembler_ftype arc_get_disassembler (bfd *);
extern disassembler_ftype cris_get_disassembler (bfd *);
extern void print_i386_disassembler_options (FILE *);
diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog
index b1c7567..ef37592 100644
--- a/include/elf/ChangeLog
+++ b/include/elf/ChangeLog
@@ -1,3 +1,8 @@
+2009-03-09 J"orn Rennecke <joern.rennecke@arc.com>
+
+ (adapted from codito)
+ * common.h (EM_ARCOMPACT): Define.
+
2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
* mips.h: Update copyright.
diff --git a/include/elf/arc.h b/include/elf/arc.h
index e2f4f41..f2a4edc 100644
--- a/include/elf/arc.h
+++ b/include/elf/arc.h
@@ -1,5 +1,5 @@
/* ARC ELF support for BFD.
- Copyright 1995, 1997, 1998, 2000, 2001 Free Software Foundation, Inc.
+ Copyright (C) 1995, 1997 Free Software Foundation, Inc.
Contributed by Doug Evans, (dje@cygnus.com)
This file is part of BFD, the Binary File Descriptor library.
@@ -28,29 +28,89 @@
/* Relocations. */
START_RELOC_NUMBERS (elf_arc_reloc_type)
- RELOC_NUMBER (R_ARC_NONE, 0)
- RELOC_NUMBER (R_ARC_32, 1)
- RELOC_NUMBER (R_ARC_B26, 2)
- RELOC_NUMBER (R_ARC_B22_PCREL, 3)
+ RELOC_NUMBER (R_ARC_NONE, 0x0)
+ RELOC_NUMBER (R_ARC_8, 0x1)
+ RELOC_NUMBER (R_ARC_16,0x2)
+ RELOC_NUMBER (R_ARC_24,0x3)
+ RELOC_NUMBER (R_ARC_32,0x4)
+ RELOC_NUMBER (R_ARC_B26,0x5)
+ RELOC_NUMBER (R_ARC_B22_PCREL, 0x6)
+
+ RELOC_NUMBER (R_ARC_H30,0x7)
+ RELOC_NUMBER (R_ARC_N8, 0x8)
+ RELOC_NUMBER (R_ARC_N16,0x9)
+ RELOC_NUMBER (R_ARC_N24,0xA)
+ RELOC_NUMBER (R_ARC_N32,0xB)
+ RELOC_NUMBER (R_ARC_SDA,0xC)
+ RELOC_NUMBER (R_ARC_SECTOFF,0xD)
+
+ RELOC_NUMBER (R_ARC_S21H_PCREL, 0xE)
+ RELOC_NUMBER (R_ARC_S21W_PCREL, 0xF)
+ RELOC_NUMBER (R_ARC_S25H_PCREL, 0x10)
+ RELOC_NUMBER (R_ARC_S25W_PCREL, 0x11)
+
+ RELOC_NUMBER (R_ARC_SDA32, 0x12)
+ RELOC_NUMBER (R_ARC_SDA_LDST, 0x13)
+ RELOC_NUMBER (R_ARC_SDA_LDST1, 0x14)
+ RELOC_NUMBER (R_ARC_SDA_LDST2, 0x15)
+ RELOC_NUMBER (R_ARC_SDA16_LD,0x16)
+ RELOC_NUMBER (R_ARC_SDA16_LD1,0x17)
+ RELOC_NUMBER (R_ARC_SDA16_LD2,0x18)
+
+
+ RELOC_NUMBER (R_ARC_S13_PCREL,0x19 )
+
+ RELOC_NUMBER (R_ARC_W, 0x1A)
+ RELOC_NUMBER (R_ARC_32_ME, 0x1B)
+
+ RELOC_NUMBER (R_ARC_N32_ME , 0x1C)
+ RELOC_NUMBER (R_ARC_SECTOFF_ME, 0x1D)
+ RELOC_NUMBER (R_ARC_SDA32_ME , 0x1E)
+ RELOC_NUMBER (R_ARC_W_ME, 0x1F)
+ RELOC_NUMBER (R_ARC_H30_ME, 0x20)
+
+ RELOC_NUMBER (R_ARC_SECTOFF_U8, 0x21)
+ RELOC_NUMBER (R_ARC_SECTOFF_S9, 0x22)
+
+
+ RELOC_NUMBER (R_AC_SECTOFF_U8, 0x23)
+ RELOC_NUMBER (R_AC_SECTOFF_U8_1, 0x24)
+ RELOC_NUMBER (R_AC_SECTOFF_U8_2, 0x25)
+
+
+ RELOC_NUMBER (R_AC_SECTOFF_S9, 0x26)
+ RELOC_NUMBER (R_AC_SECTOFF_S9_1, 0x27)
+ RELOC_NUMBER (R_AC_SECTOFF_S9_2, 0x28)
+
+
+ RELOC_NUMBER (R_ARC_SECTOFF_ME_1 ,0x29)
+ RELOC_NUMBER (R_ARC_SECTOFF_ME_2, 0x2A)
+ RELOC_NUMBER (R_ARC_SECTOFF_1, 0x2B)
+ RELOC_NUMBER (R_ARC_SECTOFF_2, 0x2C)
+
+
+ RELOC_NUMBER (R_ARC_PC32, 0x32)
+ RELOC_NUMBER (R_ARC_GOTPC32,0x33)
+ RELOC_NUMBER (R_ARC_PLT32,0x34)
+ RELOC_NUMBER (R_ARC_COPY, 0x35)
+ RELOC_NUMBER (R_ARC_GLOB_DAT, 0x36)
+ RELOC_NUMBER (R_ARC_JMP_SLOT, 0x37)
+ RELOC_NUMBER (R_ARC_RELATIVE, 0x38)
+ RELOC_NUMBER (R_ARC_GOTOFF, 0x39)
+ RELOC_NUMBER (R_ARC_GOTPC, 0x3A)
+ RELOC_NUMBER (R_ARC_GOT32, 0x3B)
END_RELOC_NUMBERS (R_ARC_max)
/* Processor specific flags for the ELF header e_flags field. */
/* Four bit ARC machine type field. */
-
-#define EF_ARC_MACH 0x0000000f
+#define EF_ARC_MACH 0x0000000f
/* Various CPU types. */
+#define E_ARC_MACH_A4 0x00000000
+#define E_ARC_MACH_A5 0x00000001
+#define E_ARC_MACH_ARC600 0x00000002
+#define E_ARC_MACH_ARC700 0x00000003
-#define E_ARC_MACH_ARC5 0
-#define E_ARC_MACH_ARC6 1
-#define E_ARC_MACH_ARC7 2
-#define E_ARC_MACH_ARC8 3
-
-/* Leave bits 0xf0 alone in case we ever have more than 16 cpu types. */
-
-/* File contains position independent code. */
-
-#define EF_ARC_PIC 0x00000100
#endif /* _ELF_ARC_H */
diff --git a/include/elf/common.h b/include/elf/common.h
index b6d981f..b1ab694 100644
--- a/include/elf/common.h
+++ b/include/elf/common.h
@@ -178,7 +178,8 @@
#define EM_MN10200 90 /* Matsushita MN10200 */
#define EM_PJ 91 /* picoJava */
#define EM_OPENRISC 92 /* OpenRISC 32-bit embedded processor */
-#define EM_ARC_A5 93 /* ARC Cores Tangent-A5 */
+#define EM_ARCOMPACT 93 /* ARC Cores Tangent-A5 */
+#define EM_ARCOMPACT 93 /* Also ARC600 & ARC700 */
#define EM_XTENSA 94 /* Tensilica Xtensa Architecture */
#define EM_IP2K 101 /* Ubicom IP2022 micro controller */
#define EM_CR 103 /* National Semiconductor CompactRISC */
diff --git a/include/elf/dwarf2.h b/include/elf/dwarf2.h
index 371a038..14da6b3 100644
--- a/include/elf/dwarf2.h
+++ b/include/elf/dwarf2.h
@@ -757,7 +757,9 @@
/* GNU extensions. */
DW_CFA_GNU_window_save = 0x2d,
DW_CFA_GNU_args_size = 0x2e,
- DW_CFA_GNU_negative_offset_extended = 0x2f
+ DW_CFA_GNU_negative_offset_extended = 0x2f,
+ /* Metaware High C compiler extensions. */
+ DW_CFA_MWARC_info = 0x34
};
#define DW_CIE_ID 0xffffffff
diff --git a/include/gdb/ChangeLog b/include/gdb/ChangeLog
index 458fa7d..ac1c126 100644
--- a/include/gdb/ChangeLog
+++ b/include/gdb/ChangeLog
@@ -1,3 +1,8 @@
+2009-03-09 J"orn Rennecke <joern.rennecke@arc.com>
+
+ * callback.h (get_path): Declare.
+ * target-io/arc.h: New file.
+
2008-01-01 Daniel Jacobowitz <dan@codesourcery.com>
Updated copyright notices for most files.
diff --git a/include/gdb/callback.h b/include/gdb/callback.h
index 5ae1d00..edddc4a 100644
--- a/include/gdb/callback.h
+++ b/include/gdb/callback.h
@@ -320,6 +320,14 @@
int cb_is_stdout PARAMS ((host_callback *, int));
int cb_is_stderr PARAMS ((host_callback *, int));
+/* Utility of cb_syscall to fetch a path name.
+ The buffer is malloc'd and the address is stored in BUFP.
+ The result is that of get_string, but prepended with
+ simulator_sysroot if the string starts with '/'.
+ If an error occurs, no buffer is left malloc'd. */
+#define TADDR unsigned long
+int get_path PARAMS ((host_callback *, CB_SYSCALL *, TADDR, char **));
+
/* Perform a system call. */
CB_RC cb_syscall PARAMS ((host_callback *, CB_SYSCALL *));
diff --git a/include/gdb/target-io/arc.h b/include/gdb/target-io/arc.h
new file mode 100644
index 0000000..a5b1716
--- /dev/null
+++ b/include/gdb/target-io/arc.h
@@ -0,0 +1,54 @@
+/* Hosted File I/O interface definitions, for GDB, the GNU Debugger.
+
+ Copyright (C) 2007 Free Software Foundation, Inc.
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
+ 02111-1307, USA. */
+
+#ifndef GDB_TGTIO_ARC_H_
+#define GDB_TGTIO_ARC_H_
+
+/* This describes struct stat as seen by the simulator on the host,
+ in order to fill in the fields as they are expected by an arc target. */
+
+#ifdef __GNUC__
+#define TGTIO_PACKED __attribute__ ((packed))
+#endif
+
+struct fio_arc_stat {
+ unsigned long
+ tgt_st_dev : 32,
+ tgt_st_ino : 32,
+ tgt_st_mode : 16,
+ tgt_st_nlink: 16,
+ tgt_st_uid : 16,
+ tgt_st_gid : 16,
+ tgt_st_rdev : 32,
+ tgt_st_size : 32,
+ tgt_st_blksize: 32,
+ tgt_st_blocks: 32;
+ long long tgt_st_atime : 64 TGTIO_PACKED;
+ long long tgt_st_mtime : 64 TGTIO_PACKED;
+ long long tgt_st_ctime : 64 TGTIO_PACKED;
+ char tgt_st_reserved[8];
+};
+
+/* Likewise for struct timeval. */
+struct fio_timeval
+{
+ long long tgt_tv_sec : 64 TGTIO_PACKED;
+ long tgt_tv_usec : 32;
+};
+#endif /* GDB_TGTIO_ARC_H_ */
diff --git a/include/opcode/arc.h b/include/opcode/arc.h
index 8ddcf54..184a081 100644
--- a/include/opcode/arc.h
+++ b/include/opcode/arc.h
@@ -27,86 +27,142 @@
whatever is supported by a particular cpu. This lets us have one entry
apply to several cpus.
- The `base' cpu must be 0. The cpu type is treated independently of
- endianness. The complete `mach' number includes endianness.
+ This duplicates bfd_mach_arc_xxx. For now I wish to isolate this from bfd
+ and bfd from this. Also note that these numbers are bit values as we want
+ to allow for things available on more than one ARC (but not necessarily all
+ ARCs). */
+
+/* The `base' cpu must be 0 (table entries are omitted for the base cpu).
+ The cpu type is treated independently of endianness.
+ The complete `mach' number includes endianness.
These values are internal to opcodes/bfd/binutils/gas. */
-#define ARC_MACH_5 0
-#define ARC_MACH_6 1
-#define ARC_MACH_7 2
-#define ARC_MACH_8 4
+#define ARC_MACH_ARC4 1
+#define ARC_MACH_ARC5 2
+#define ARC_MACH_ARC6 4
+#define ARC_MACH_ARC7 8
/* Additional cpu values can be inserted here and ARC_MACH_BIG moved down. */
#define ARC_MACH_BIG 16
+/* ARC processors which implement ARCompact ISA. */
+#define ARCOMPACT (ARC_MACH_ARC5 | ARC_MACH_ARC6 | ARC_MACH_ARC7)
+
/* Mask of number of bits necessary to record cpu type. */
#define ARC_MACH_CPU_MASK (ARC_MACH_BIG - 1)
-
/* Mask of number of bits necessary to record cpu type + endianness. */
#define ARC_MACH_MASK ((ARC_MACH_BIG << 1) - 1)
/* Type to denote an ARC instruction (at least a 32 bit unsigned int). */
-
typedef unsigned int arc_insn;
struct arc_opcode {
- char *syntax; /* syntax of insn */
- unsigned long mask, value; /* recognize insn if (op&mask) == value */
- int flags; /* various flag bits */
+ char *syntax; /* syntax of insn */
+ unsigned long mask, value; /* recognize insn if (op&mask)==value */
+ int flags; /* various flag bits */
/* Values for `flags'. */
/* Return CPU number, given flag bits. */
#define ARC_OPCODE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK)
-
/* Return MACH number, given flag bits. */
#define ARC_OPCODE_MACH(bits) ((bits) & ARC_MACH_MASK)
-
/* First opcode flag bit available after machine mask. */
#define ARC_OPCODE_FLAG_START (ARC_MACH_MASK + 1)
/* This insn is a conditional branch. */
#define ARC_OPCODE_COND_BRANCH (ARC_OPCODE_FLAG_START)
-#define SYNTAX_3OP (ARC_OPCODE_COND_BRANCH << 1)
-#define SYNTAX_LENGTH (SYNTAX_3OP )
-#define SYNTAX_2OP (SYNTAX_3OP << 1)
-#define OP1_MUST_BE_IMM (SYNTAX_2OP << 1)
-#define OP1_IMM_IMPLIED (OP1_MUST_BE_IMM << 1)
-#define SYNTAX_VALID (OP1_IMM_IMPLIED << 1)
+#define SYNTAX_LENGTH (ARC_OPCODE_COND_BRANCH << 1)
+#define SYNTAX_3OP (SYNTAX_LENGTH )
+#define SYNTAX_2OP (SYNTAX_3OP << 1)
+#define SYNTAX_1OP (SYNTAX_2OP << 1)
+#define SYNTAX_NOP (SYNTAX_1OP << 1)
+#define OP1_DEST_IGNORED (SYNTAX_NOP << 1)
+#define OP1_MUST_BE_IMM (OP1_DEST_IGNORED << 1)
+#define OP1_IMM_IMPLIED (OP1_MUST_BE_IMM << 1)
+#define SUFFIX_NONE (OP1_IMM_IMPLIED << 1)
+#define SUFFIX_COND (SUFFIX_NONE << 1)
+#define SUFFIX_FLAG (SUFFIX_COND << 1)
+#define SYNTAX_VALID (SUFFIX_FLAG << 1)
-#define I(x) (((x) & 31) << 27)
-#define A(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGA)
-#define B(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGB)
-#define C(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGC)
-#define R(x,b,m) (((x) & (m)) << (b)) /* value X, mask M, at bit B */
-/* These values are used to optimize assembly and disassembly. Each insn
- is on a list of related insns (same first letter for assembly, same
- insn code for disassembly). */
- struct arc_opcode *next_asm; /* Next instr to try during assembly. */
- struct arc_opcode *next_dis; /* Next instr to try during disassembly. */
+#define AC_SYNTAX_3OP (0x01)
+#define AC_SYNTAX_2OP (AC_SYNTAX_3OP << 1)
+#define AC_SYNTAX_1OP (AC_SYNTAX_2OP << 1)
+#define AC_SYNTAX_NOP (AC_SYNTAX_1OP << 1)
+#define AC_SYNTAX_SIMD (AC_SYNTAX_NOP << 1)
+#define AC_OP1_DEST_IGNORED (AC_SYNTAX_SIMD << 1)
+#define AC_OP1_MUST_BE_IMM (AC_OP1_DEST_IGNORED << 1)
+#define AC_OP1_IMM_IMPLIED (AC_OP1_MUST_BE_IMM << 1)
-/* Macros to create the hash values for the lists. */
+
+#define AC_SIMD_SYNTAX_VVV (AC_OP1_IMM_IMPLIED << 1)
+#define AC_SIMD_SYNTAX_VV0 (AC_SIMD_SYNTAX_VVV << 1)
+#define AC_SIMD_SYNTAX_VbI0 (AC_SIMD_SYNTAX_VV0 << 1)
+#define AC_SIMD_SYNTAX_Vb00 (AC_SIMD_SYNTAX_VbI0 << 1)
+#define AC_SIMD_SYNTAX_VbC0 (AC_SIMD_SYNTAX_Vb00 << 1)
+#define AC_SIMD_SYNTAX_V00 (AC_SIMD_SYNTAX_VbC0 << 1)
+#define AC_SIMD_SYNTAX_VC0 (AC_SIMD_SYNTAX_V00 << 1)
+#define AC_SIMD_SYNTAX_VVC (AC_SIMD_SYNTAX_VC0 << 1)
+#define AC_SIMD_SYNTAX_VV (AC_SIMD_SYNTAX_VVC << 1)
+#define AC_SIMD_SYNTAX_VVI (AC_SIMD_SYNTAX_VV << 1)
+#define AC_SIMD_SYNTAX_C (AC_SIMD_SYNTAX_VVI << 1)
+#define AC_SIMD_SYNTAX_0 (AC_SIMD_SYNTAX_C << 1)
+#define AC_SIMD_SYNTAX_CC (AC_SIMD_SYNTAX_0 << 1)
+#define AC_SIMD_SYNTAX_C0 (AC_SIMD_SYNTAX_CC << 1)
+#define AC_SIMD_SYNTAX_DC (AC_SIMD_SYNTAX_C0 << 1)
+#define AC_SIMD_SYNTAX_D0 (AC_SIMD_SYNTAX_DC << 1)
+#define AC_SIMD_SYNTAX_VD (AC_SIMD_SYNTAX_D0 << 1)
+
+
+ //#define AC_SUFFIX_NONE (AC_SIMD_SYNTAX_VD << 1)
+#define AC_SUFFIX_NONE (0x1)
+#define AC_SUFFIX_COND (AC_SUFFIX_NONE << 1)
+#define AC_SUFFIX_FLAG (AC_SUFFIX_COND << 1)
+#define AC_SIMD_FLAGS_NONE (AC_SUFFIX_FLAG << 1)
+#define AC_SIMD_FLAG_SET (AC_SIMD_FLAGS_NONE << 1)
+#define AC_SIMD_FLAG1_SET (AC_SIMD_FLAG_SET << 1)
+#define AC_SIMD_FLAG2_SET (AC_SIMD_FLAG1_SET << 1)
+#define AC_SIMD_ENCODE_U8 (AC_SIMD_FLAG2_SET << 1)
+#define AC_SIMD_ENCODE_U6 (AC_SIMD_ENCODE_U8 << 1)
+#define AC_SIMD_SCALE_1 (AC_SIMD_ENCODE_U6 << 1)
+#define AC_SIMD_SCALE_2 (AC_SIMD_SCALE_1 << 1)
+#define AC_SIMD_SCALE_3 (AC_SIMD_SCALE_2 << 1)
+#define AC_SIMD_SCALE_4 (AC_SIMD_SCALE_3 << 1)
+#define AC_SIMD_ENCODE_LIMM (AC_SIMD_SCALE_4 << 1)
+
+
+
+
+#define I(x) (((unsigned) (x) & 31) << 27)
+#define A(x) (((unsigned) (x) & ARC_MASK_REG) << ARC_SHIFT_REGA)
+#define B(x) (((unsigned) (x) & ARC_MASK_REG) << ARC_SHIFT_REGB)
+#define C(x) (((unsigned) (x) & ARC_MASK_REG) << ARC_SHIFT_REGC)
+#define R(x,b,m) (((unsigned) (x) & (m)) << (b)) /* value X, mask M, at bit B */
+
+ /* These values are used to optimize assembly and disassembly. Each insn is
+ on a list of related insns (same first letter for assembly, same insn code
+ for disassembly). */
+ struct arc_opcode *next_asm; /* Next instruction to try during assembly. */
+ struct arc_opcode *next_dis; /* Next instruction to try during disassembly. */
+
+ /* Macros to create the hash values for the lists. */
#define ARC_HASH_OPCODE(string) \
((string)[0] >= 'a' && (string)[0] <= 'z' ? (string)[0] - 'a' : 26)
#define ARC_HASH_ICODE(insn) \
((unsigned int) (insn) >> 27)
- /* Macros to access `next_asm', `next_dis' so users needn't care about the
- underlying mechanism. */
+ /* Macros to access `next_asm', `next_dis' so users needn't care about the
+ underlying mechanism. */
#define ARC_OPCODE_NEXT_ASM(op) ((op)->next_asm)
#define ARC_OPCODE_NEXT_DIS(op) ((op)->next_dis)
};
-/* this is an "insert at front" linked list per Metaware spec
- that new definitions override older ones. */
-extern struct arc_opcode *arc_ext_opcodes;
-
struct arc_operand_value {
- char *name; /* eg: "eq" */
- short value; /* eg: 1 */
- unsigned char type; /* index into `arc_operands' */
- unsigned char flags; /* various flag bits */
+ char *name; /* eg: "eq" */
+ short value; /* eg: 1 */
+ unsigned char type; /* index into `arc_operands' */
+ unsigned char flags; /* various flag bits */
/* Values for `flags'. */
@@ -121,20 +177,22 @@
struct arc_operand_value operand;
};
+/* List of extension condition codes, core registers and auxiliary registers.
+ Calls to gas/config/tc-arc.c:arc_extoper built up this list. */
extern struct arc_ext_operand_value *arc_ext_operands;
struct arc_operand {
-/* One of the insn format chars. */
+ /* One of the insn format chars. */
unsigned char fmt;
-/* The number of bits in the operand (may be unused for a modifier). */
+ /* The number of bits in the operand (may be unused for a modifier). */
unsigned char bits;
-/* How far the operand is left shifted in the instruction, or
- the modifier's flag bit (may be unused for a modifier. */
+ /* How far the operand is left shifted in the instruction, or
+ the modifier's flag bit (may be unused for a modifier. */
unsigned char shift;
-/* Various flag bits. */
+ /* Various flag bits. */
int flags;
/* Values for `flags'. */
@@ -176,10 +234,11 @@
in special ways. */
#define ARC_OPERAND_FAKE 0x100
-/* separate flags operand for j and jl instructions */
+/* separate flags operand for j and jl instructions */
#define ARC_OPERAND_JUMPFLAGS 0x200
-/* allow warnings and errors to be issued after call to insert_xxxxxx */
+/* allow warnings and errors to be issued after call to insert_xxxxxx */
+
#define ARC_OPERAND_WARN 0x400
#define ARC_OPERAND_ERROR 0x800
@@ -189,6 +248,15 @@
/* this is a store operand */
#define ARC_OPERAND_STORE 0x10000
+/* this is an unsigned operand */
+#define ARC_OPERAND_UNSIGNED 0x20000
+
+/* this operand's value must be 2-byte aligned */
+#define ARC_OPERAND_2BYTE_ALIGNED 0x40000
+
+/* this operand's value must be 4-byte aligned */
+#define ARC_OPERAND_4BYTE_ALIGNED 0x80000
+
/* Modifier values. */
/* A dot is required before a suffix. Eg: .le */
#define ARC_MOD_DOT 0x1000
@@ -199,70 +267,165 @@
/* An auxiliary register name is expected. */
#define ARC_MOD_AUXREG 0x4000
+ /* This should be a small data symbol, i.e. suffixed with an @sda */
+#define ARC_MOD_SDASYM 0x100000
+
/* Sum of all ARC_MOD_XXX bits. */
-#define ARC_MOD_BITS 0x7000
+#define ARC_MOD_BITS 0x107000
/* Non-zero if the operand type is really a modifier. */
#define ARC_MOD_P(X) ((X) & ARC_MOD_BITS)
-/* enforce read/write only register restrictions */
+/* enforce read/write only register restrictions */
+
#define ARC_REGISTER_READONLY 0x01
#define ARC_REGISTER_WRITEONLY 0x02
#define ARC_REGISTER_NOSHORT_CUT 0x04
-/* Insertion function. This is used by the assembler. To insert an
- operand value into an instruction, check this field.
+/* Registers which are normally used in 16-bit ARCompact insns */
+#define ARC_REGISTER_16 0x8
- If it is NULL, execute
- i |= (p & ((1 << o->bits) - 1)) << o->shift;
- (I is the instruction which we are filling in, O is a pointer to
- this structure, and OP is the opcode value; this assumes twos
- complement arithmetic).
-
- If this field is not NULL, then simply call it with the
- instruction and the operand value. It will return the new value
- of the instruction. If the ERRMSG argument is not NULL, then if
- the operand value is illegal, *ERRMSG will be set to a warning
- string (the operand will be inserted in any case). If the
- operand value is legal, *ERRMSG will be unchanged.
+ /*
+ FIXME: The following 5 definitions is a unclean way of passing
+ information to md_assemble. New opcode is a possibility but its
+ already very crowded.
+ */
+ /*The u6 operand needs to be incremented by 1 for some pseudo mnemonics of
+ the BRcc instruction. */
+#define ARC_INCR_U6 0x100000
- REG is non-NULL when inserting a register value. */
+#define ARC_SIMD_SCALE1 (ARC_INCR_U6 << 0x1)
+#define ARC_SIMD_SCALE2 (ARC_SIMD_SCALE1 << 0x1)
+#define ARC_SIMD_SCALE3 (ARC_SIMD_SCALE2 << 0x1)
+#define ARC_SIMD_SCALE4 (ARC_SIMD_SCALE3 << 0x1)
- arc_insn (*insert)
- (arc_insn insn, const struct arc_operand *operand, int mods,
- const struct arc_operand_value *reg, long value, const char **errmsg);
-/* Extraction function. This is used by the disassembler. To
- extract this operand type from an instruction, check this field.
-
- If it is NULL, compute
- op = ((i) >> o->shift) & ((1 << o->bits) - 1);
- if ((o->flags & ARC_OPERAND_SIGNED) != 0
- && (op & (1 << (o->bits - 1))) != 0)
- op -= 1 << o->bits;
- (I is the instruction, O is a pointer to this structure, and OP
- is the result; this assumes twos complement arithmetic).
-
- If this field is not NULL, then simply call it with the
- instruction value. It will return the value of the operand. If
- the INVALID argument is not NULL, *INVALID will be set to
- non-zero if this operand type can not actually be extracted from
- this operand (i.e., the instruction does not match). If the
- operand is valid, *INVALID will not be changed.
+/* Registers for the Aurora SIMD ISA*/
+#define ARC_REGISTER_SIMD_VR 0x10
+#define ARC_REGISTER_SIMD_I 0x20
+#define ARC_REGISTER_SIMD_DR 0x40
- INSN is a pointer to an array of two `arc_insn's. The first element is
- the insn, the second is the limm if present.
- Operands that have a printable form like registers and suffixes have
- their struct arc_operand_value pointer stored in OPVAL. */
+ /* Insertion function. This is used by the assembler. To insert an
+ operand value into an instruction, check this field.
- long (*extract)
- (arc_insn *insn, const struct arc_operand *operand, int mods,
- const struct arc_operand_value **opval, int *invalid);
+ If it is NULL, execute
+ i |= (p & ((1 << o->bits) - 1)) << o->shift;
+ (I is the instruction which we are filling in, O is a pointer to
+ this structure, and OP is the opcode value; this assumes twos
+ complement arithmetic).
+
+ If this field is not NULL, then simply call it with the
+ instruction and the operand value. It will return the new value
+ of the instruction. If the ERRMSG argument is not NULL, then if
+ the operand value is illegal, *ERRMSG will be set to a warning
+ string (the operand will be inserted in any case). If the
+ operand value is legal, *ERRMSG will be unchanged.
+
+ REG is non-NULL when inserting a register value. */
+
+ arc_insn (*insert) (arc_insn insn, const struct arc_operand *operand,
+ int mods, const struct arc_operand_value *reg,
+ long value, const char **errmsg);
+
+ /* Extraction function. This is used by the disassembler. To
+ extract this operand type from an instruction, check this field.
+
+ If it is NULL, compute
+ op = ((i) >> o->shift) & ((1 << o->bits) - 1);
+ if ((o->flags & ARC_OPERAND_SIGNED) != 0
+ && (op & (1 << (o->bits - 1))) != 0)
+ op -= 1 << o->bits;
+ (I is the instruction, O is a pointer to this structure, and OP
+ is the result; this assumes twos complement arithmetic).
+
+ If this field is not NULL, then simply call it with the
+ instruction value. It will return the value of the operand. If
+ the INVALID argument is not NULL, *INVALID will be set to
+ non-zero if this operand type can not actually be extracted from
+ this operand (i.e., the instruction does not match). If the
+ operand is valid, *INVALID will not be changed.
+
+ INSN is a pointer to an array of two `arc_insn's. The first element is
+ the insn, the second is the limm if present.
+
+ Operands that have a printable form like registers and suffixes have
+ their struct arc_operand_value pointer stored in OPVAL. */
+
+ long (*extract) (arc_insn *insn,
+ const struct arc_operand *operand, int mods,
+ const struct arc_operand_value **opval, int *invalid);
};
-/* Bits that say what version of cpu we have. These should be passed to
- arc_init_opcode_tables. At present, all there is is the cpu type. */
+enum
+{
+ BR_exec_when_no_jump,
+ BR_exec_always,
+ BR_exec_when_jump
+};
+
+enum Flow
+{
+ noflow,
+ direct_jump,
+ direct_call,
+ indirect_jump,
+ indirect_call,
+ invalid_instr
+};
+
+enum { no_reg = 99 };
+enum { allOperandsSize = 256 };
+
+struct arcDisState
+{
+ void *_this;
+ int instructionLen;
+ void (*err)(void*, const char*);
+ const char *(*coreRegName)(void*, int);
+ const char *(*auxRegName)(void*, int);
+ const char *(*condCodeName)(void*, int);
+ const char *(*instName)(void*, int, int, int*);
+
+ unsigned char* instruction;
+ unsigned index;
+ const char *comm[6]; /* instr name, cond, NOP, 3 operands */
+
+ union {
+ unsigned int registerNum;
+ unsigned int shortimm;
+ unsigned int longimm;
+ } source_operand;
+
+ enum ARC_Debugger_OperandType sourceType;
+
+ int opWidth;
+ int targets[4];
+ int addresses[4];
+ /* Set as a side-effect of calling the disassembler.
+ Used only by the debugger. */
+ enum Flow flow;
+ int register_for_indirect_jump;
+ int ea_reg1, ea_reg2, _offset;
+ int _cond, _opcode;
+ unsigned long words[2];
+ char *commentBuffer;
+ char instrBuffer[40];
+ char operandBuffer[allOperandsSize];
+ char _ea_present;
+ char _addrWriteBack; /* Address writeback */
+ char _mem_load;
+ char _load_len;
+ char nullifyMode;
+ unsigned char commNum;
+ unsigned char isBranch;
+ unsigned char tcnt;
+ unsigned char acnt;
+};
+
+/* Bits that say what version of cpu we have.
+ These should be passed to arc_init_opcode_tables.
+ At present, all there is is the cpu type. */
/* CPU number, given value passed to `arc_init_opcode_tables'. */
#define ARC_HAVE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK)
@@ -281,29 +444,45 @@
#define ARC_SHIFT_REGA 21
#define ARC_SHIFT_REGB 15
#define ARC_SHIFT_REGC 9
+#define ARC_SHIFT_REGA_AC 0
+#define ARC_SHIFT_REGB_LOW_AC 24
+#define ARC_SHIFT_REGB_HIGH_AC 12
+#define ARC_SHIFT_REGC_AC 6
#define ARC_MASK_REG 63
/* Delay slot types. */
-#define ARC_DELAY_NONE 0 /* no delay slot */
-#define ARC_DELAY_NORMAL 1 /* delay slot in both cases */
-#define ARC_DELAY_JUMP 2 /* delay slot only if branch taken */
+#define ARC_DELAY_NONE 0 /* no delay slot */
+#define ARC_DELAY_NORMAL 1 /* delay slot in both cases */
+#define ARC_DELAY_JUMP 2 /* delay slot only if branch taken */
/* Non-zero if X will fit in a signed 9 bit field. */
#define ARC_SHIMM_CONST_P(x) ((long) (x) >= -256 && (long) (x) <= 255)
-extern const struct arc_operand arc_operands[];
-extern const int arc_operand_count;
-extern struct arc_opcode arc_opcodes[];
+extern const struct arc_operand arc_operands_a4[];
+extern const struct arc_operand arc_operands_ac[];
+extern const struct arc_operand *arc_operands;
+extern int arc_operand_count;
+extern /*const*/ struct arc_opcode arc_opcodes[];
extern const int arc_opcodes_count;
-extern const struct arc_operand_value arc_suffixes[];
-extern const int arc_suffixes_count;
-extern const struct arc_operand_value arc_reg_names[];
-extern const int arc_reg_names_count;
-extern unsigned char arc_operand_map[];
+extern const struct arc_operand_value arc_suffixes_a4[];
+extern const struct arc_operand_value arc_suffixes_ac[];
+extern const struct arc_operand_value *arc_suffixes;
+extern int arc_suffixes_count;
+extern const struct arc_operand_value arc_reg_names_a4[];
+extern const struct arc_operand_value arc_reg_names_ac[];
+extern const struct arc_operand_value *arc_reg_names;
+extern int arc_reg_names_count;
+extern unsigned char arc_operand_map_a4[];
+extern unsigned char arc_operand_map_ac[];
+extern unsigned char *arc_operand_map;
+//extern int mach_a4;
+//extern int compact_insn_16;
+
+int mach_a4;
+int compact_insn_16;
/* Utility fns in arc-opc.c. */
int arc_get_opcode_mach (int, int);
-
/* `arc_opcode_init_tables' must be called before `arc_xxx_supported'. */
void arc_opcode_init_tables (int);
void arc_opcode_init_insert (void);
@@ -311,13 +490,22 @@
const struct arc_opcode *arc_opcode_lookup_asm (const char *);
const struct arc_opcode *arc_opcode_lookup_dis (unsigned int);
int arc_opcode_limm_p (long *);
-const struct arc_operand_value *arc_opcode_lookup_suffix
- (const struct arc_operand *type, int value);
+const struct arc_operand_value *arc_opcode_lookup_suffix (const struct arc_operand *type, int value);
int arc_opcode_supported (const struct arc_opcode *);
int arc_opval_supported (const struct arc_operand_value *);
-int arc_limm_fixup_adjust (arc_insn);
-int arc_insn_is_j (arc_insn);
int arc_insn_not_jl (arc_insn);
-int arc_operand_type (int);
-struct arc_operand_value *get_ext_suffix (char *);
-int arc_get_noshortcut_flag (void);
+
+extern char *arc_aux_reg_name (int);
+extern struct arc_operand_value *get_ext_suffix (char *);
+
+extern int ac_branch_or_jump_insn (arc_insn);
+extern int ac_lpcc_insn (arc_insn);
+extern int ac_constant_operand (const struct arc_operand *);
+extern int ac_register_operand (const struct arc_operand *);
+extern int ac_symbol_operand (const struct arc_operand *);
+extern int ARC700_register_simd_operand (char);
+extern int arc_operand_type (int);
+extern int ac_add_reg_sdasym_insn (arc_insn);
+extern int ac_get_load_sdasym_insn_type (arc_insn, int);
+extern int ac_get_store_sdasym_insn_type (arc_insn, int);
+extern int arc_limm_fixup_adjust (arc_insn);
diff --git a/include/opcode/cgen.h b/include/opcode/cgen.h
index e8fd5d3..12a4461 100644
--- a/include/opcode/cgen.h
+++ b/include/opcode/cgen.h
@@ -1,6 +1,6 @@
/* Header file for targets using CGEN: Cpu tools GENerator.
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007
Free Software Foundation, Inc.
This file is part of GDB, the GNU debugger, and the GNU Binutils.
@@ -1339,7 +1339,7 @@
int (* dis_hash_p) (const CGEN_INSN *);
/* Disassembler hash function. */
- unsigned int (* dis_hash) (const char *, CGEN_INSN_INT);
+ unsigned int (* dis_hash) (const char *, CGEN_INSN_INT, int);
/* Number of entries in disassembler hash table. */
unsigned int dis_hash_size;
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index c0a83c4..4f83203 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,21 @@
+2009-03-09 J"orn Rennecke <joern.rennecke@arc.com>
+
+ * arc-ext.c (arcExtMap_add): Fix pointer basetype signedness problem.
+
+ * cgen-dis.c (hash_insn_array): Supply big_p parameter to cd->dis_hash.
+ (hash_insn_list, cgen_dis_lookup_insn): Likewise.
+
+ * configure.in (bfd_arc_arch): Use cgen.
+ * configure: Regenerate.
+ * arc-dis.c, arc-opc.c, arc-opc.h, arc-opinst.c: Generate.
+ * Makefile.am (HFILES, CFILES): Use cgen files.
+ (CLEANFILES): Add stamp-arc.
+ (CGEN_CPUS): Add arc.
+ (ARC_DEPS, stamp-arc): New.
+ (arc rules): Use rules for cgen build.
+ * Makefile.in: Regenerate.
+ * arc-desc.c, arc-ibld.c, arc-asm.c: Generate.
+
2008-02-23 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl: Disallow 16-bit near indirect branches for
diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am
index 8cd2be1..14ae763 100644
--- a/opcodes/Makefile.am
+++ b/opcodes/Makefile.am
@@ -29,6 +29,7 @@
# Header files.
HFILES = \
+ arc-desc.h arc-opc.h \
cgen-ops.h cgen-types.h \
fr30-desc.h fr30-opc.h \
frv-desc.h frv-opc.h \
@@ -59,9 +60,13 @@
CFILES = \
alpha-dis.c \
alpha-opc.c \
- arc-dis.c \
- arc-opc.c \
arc-ext.c \
+ arc-asm.c \
+ arc-desc.c \
+ arc-dis.c \
+ arc-ibld.c \
+ arc-opc.c \
+ arc-opinst.c \
arm-dis.c \
avr-dis.c \
bfin-dis.c \
@@ -213,9 +218,13 @@
ALL_MACHINES = \
alpha-dis.lo \
alpha-opc.lo \
- arc-dis.lo \
- arc-opc.lo \
arc-ext.lo \
+ arc-asm.lo \
+ arc-desc.lo \
+ arc-dis.lo \
+ arc-ibld.lo \
+ arc-opc.lo \
+ arc-opinst.lo \
arm-dis.lo \
avr-dis.lo \
bfin-dis.lo \
@@ -421,7 +430,7 @@
rm -f $(DESTDIR)$(bfdincludedir)/dis-asm.h
CLEANFILES = \
- stamp-ip2k stamp-m32c stamp-m32r stamp-fr30 stamp-frv \
+ stamp-arc stamp-ip2k stamp-m32c stamp-m32r stamp-fr30 stamp-frv \
stamp-openrisc stamp-iq2000 stamp-mep stamp-mt stamp-xstormy16 stamp-xc16x\
libopcodes.a stamp-lib dep.sed DEP DEPA DEP1 DEP2
@@ -438,9 +447,10 @@
$(CGENDIR)/opc-opinst.scm \
cgen-asm.in cgen-dis.in cgen-ibld.in
-CGEN_CPUS = fr30 frv ip2k m32c m32r mep mt openrisc xc16x xstormy16
+CGEN_CPUS = arc fr30 frv ip2k m32c m32r mep mt openrisc xc16x xstormy16
if CGEN_MAINT
+ARC_DEPS = stamp-arc
IP2K_DEPS = stamp-ip2k
M32C_DEPS = stamp-m32c
M32R_DEPS = stamp-m32r
@@ -453,6 +463,7 @@
XC16X_DEPS = stamp-xc16x
XSTORMY16_DEPS = stamp-xstormy16
else
+ARC_DEPS =
IP2K_DEPS =
M32C_DEPS =
M32R_DEPS =
@@ -482,6 +493,13 @@
.PHONY: run-cgen-all
# For now, require developers to configure with --enable-cgen-maint.
+$(srcdir)/arc-desc.h $(srcdir)/arc-desc.c $(srcdir)/arc-opc.h $(srcdir)/arc-opc.c $(srcdir)/arc-ibld.c $(srcdir)/arc-opinst.c $(srcdir)/arc-asm.c $(srcdir)/arc-dis.c: $(ARC_DEPS)
+ @true
+stamp-arc: $(CGENDEPS) $(srcdir)/../cpu/arc.cpu $(srcdir)/../cpu/arc.opc
+ $(MAKE) run-cgen arch=arc prefix=arc options=opinst \
+ archfile=$(srcdir)/../cpu/arc.cpu \
+ opcfile=$(srcdir)/../cpu/arc.opc extrafiles=opinst
+
$(srcdir)/ip2k-desc.h $(srcdir)/ip2k-desc.c $(srcdir)/ip2k-opc.h $(srcdir)/ip2k-opc.c $(srcdir)/ip2k-ibld.c $(srcdir)/ip2k-asm.c $(srcdir)/ip2k-dis.c: $(IP2K_DEPS)
@true
stamp-ip2k: $(CGENDEPS) $(CPUDIR)/ip2k.cpu $(CPUDIR)/ip2k.opc
@@ -656,18 +674,41 @@
alpha-opc.lo: alpha-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/opcode/alpha.h $(BFD_H) $(INCDIR)/ansidecl.h \
$(INCDIR)/symcat.h opintl.h
-arc-dis.lo: arc-dis.c $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
- $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h \
- $(INCDIR)/symcat.h $(INCDIR)/opcode/arc.h $(BFDDIR)/elf-bfd.h \
- $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
- $(INCDIR)/bfdlink.h $(INCDIR)/elf/arc.h $(INCDIR)/elf/reloc-macros.h \
- opintl.h arc-dis.h arc-ext.h
-arc-opc.lo: arc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
- $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/opcode/arc.h \
- opintl.h
arc-ext.lo: arc-ext.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h arc-ext.h \
$(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h
+arc-asm.lo: arc-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+ $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
+ arc-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+ $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h arc-opc.h \
+ opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \
+ $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
+arc-desc.lo: arc-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+ $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
+ arc-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+ $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h arc-opc.h \
+ opintl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
+ $(INCDIR)/xregex.h $(INCDIR)/xregex2.h
+arc-dis.lo: arc-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
+ $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
+ arc-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+ $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h arc-opc.h \
+ opintl.h
+arc-ibld.lo: arc-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
+ $(BFD_H) $(INCDIR)/symcat.h arc-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+ $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h \
+ arc-opc.h opintl.h $(INCDIR)/safe-ctype.h
+arc-opc.lo: arc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+ $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
+ arc-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+ $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h arc-opc.h \
+ $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h
+arc-opinst.lo: arc-opinst.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+ $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
+ arc-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+ $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h arc-opc.h
arm-dis.lo: arm-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
$(INCDIR)/opcode/arm.h opintl.h $(INCDIR)/safe-ctype.h \
diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in
index 73642f1..b412e0c 100644
--- a/opcodes/Makefile.in
+++ b/opcodes/Makefile.in
@@ -257,6 +257,7 @@
# Header files.
HFILES = \
+ arc-desc.h arc-opc.h \
cgen-ops.h cgen-types.h \
fr30-desc.h fr30-opc.h \
frv-desc.h frv-opc.h \
@@ -288,9 +289,13 @@
CFILES = \
alpha-dis.c \
alpha-opc.c \
- arc-dis.c \
- arc-opc.c \
arc-ext.c \
+ arc-asm.c \
+ arc-desc.c \
+ arc-dis.c \
+ arc-ibld.c \
+ arc-opc.c \
+ arc-opinst.c \
arm-dis.c \
avr-dis.c \
bfin-dis.c \
@@ -442,9 +447,13 @@
ALL_MACHINES = \
alpha-dis.lo \
alpha-opc.lo \
- arc-dis.lo \
- arc-opc.lo \
arc-ext.lo \
+ arc-asm.lo \
+ arc-desc.lo \
+ arc-dis.lo \
+ arc-ibld.lo \
+ arc-opc.lo \
+ arc-opinst.lo \
arm-dis.lo \
avr-dis.lo \
bfin-dis.lo \
@@ -604,7 +613,7 @@
noinst_LIBRARIES = libopcodes.a
POTFILES = $(HFILES) $(CFILES)
CLEANFILES = \
- stamp-ip2k stamp-m32c stamp-m32r stamp-fr30 stamp-frv \
+ stamp-arc stamp-ip2k stamp-m32c stamp-m32r stamp-fr30 stamp-frv \
stamp-openrisc stamp-iq2000 stamp-mep stamp-mt stamp-xstormy16 stamp-xc16x\
libopcodes.a stamp-lib dep.sed DEP DEPA DEP1 DEP2
@@ -619,7 +628,9 @@
$(CGENDIR)/opc-opinst.scm \
cgen-asm.in cgen-dis.in cgen-ibld.in
-CGEN_CPUS = fr30 frv ip2k m32c m32r mep mt openrisc xc16x xstormy16
+CGEN_CPUS = arc fr30 frv ip2k m32c m32r mep mt openrisc xc16x xstormy16
+@CGEN_MAINT_FALSE@ARC_DEPS =
+@CGEN_MAINT_TRUE@ARC_DEPS = stamp-arc
@CGEN_MAINT_FALSE@IP2K_DEPS =
@CGEN_MAINT_TRUE@IP2K_DEPS = stamp-ip2k
@CGEN_MAINT_FALSE@M32C_DEPS =
@@ -1035,6 +1046,13 @@
.PHONY: run-cgen-all
# For now, require developers to configure with --enable-cgen-maint.
+$(srcdir)/arc-desc.h $(srcdir)/arc-desc.c $(srcdir)/arc-opc.h $(srcdir)/arc-opc.c $(srcdir)/arc-ibld.c $(srcdir)/arc-opinst.c $(srcdir)/arc-asm.c $(srcdir)/arc-dis.c: $(ARC_DEPS)
+ @true
+stamp-arc: $(CGENDEPS) $(srcdir)/../cpu/arc.cpu $(srcdir)/../cpu/arc.opc
+ $(MAKE) run-cgen arch=arc prefix=arc options=opinst \
+ archfile=$(srcdir)/../cpu/arc.cpu \
+ opcfile=$(srcdir)/../cpu/arc.opc extrafiles=opinst
+
$(srcdir)/ip2k-desc.h $(srcdir)/ip2k-desc.c $(srcdir)/ip2k-opc.h $(srcdir)/ip2k-opc.c $(srcdir)/ip2k-ibld.c $(srcdir)/ip2k-asm.c $(srcdir)/ip2k-dis.c: $(IP2K_DEPS)
@true
stamp-ip2k: $(CGENDEPS) $(CPUDIR)/ip2k.cpu $(CPUDIR)/ip2k.opc
@@ -1208,18 +1226,41 @@
alpha-opc.lo: alpha-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/opcode/alpha.h $(BFD_H) $(INCDIR)/ansidecl.h \
$(INCDIR)/symcat.h opintl.h
-arc-dis.lo: arc-dis.c $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
- $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h \
- $(INCDIR)/symcat.h $(INCDIR)/opcode/arc.h $(BFDDIR)/elf-bfd.h \
- $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
- $(INCDIR)/bfdlink.h $(INCDIR)/elf/arc.h $(INCDIR)/elf/reloc-macros.h \
- opintl.h arc-dis.h arc-ext.h
-arc-opc.lo: arc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
- $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/opcode/arc.h \
- opintl.h
arc-ext.lo: arc-ext.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h arc-ext.h \
$(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h
+arc-asm.lo: arc-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+ $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
+ arc-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+ $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h arc-opc.h \
+ opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \
+ $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
+arc-desc.lo: arc-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+ $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
+ arc-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+ $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h arc-opc.h \
+ opintl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
+ $(INCDIR)/xregex.h $(INCDIR)/xregex2.h
+arc-dis.lo: arc-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
+ $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
+ arc-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+ $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h arc-opc.h \
+ opintl.h
+arc-ibld.lo: arc-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
+ $(BFD_H) $(INCDIR)/symcat.h arc-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+ $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h \
+ arc-opc.h opintl.h $(INCDIR)/safe-ctype.h
+arc-opc.lo: arc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+ $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
+ arc-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+ $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h arc-opc.h \
+ $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h
+arc-opinst.lo: arc-opinst.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+ $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
+ arc-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+ $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h arc-opc.h
arm-dis.lo: arm-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
$(INCDIR)/opcode/arm.h opintl.h $(INCDIR)/safe-ctype.h \
diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c
index b5eb8a5..de6e1d0 100644
--- a/opcodes/arc-dis.c
+++ b/opcodes/arc-dis.c
@@ -1,7 +1,11 @@
-/* Instruction printing code for the ARC.
- Copyright 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2005, 2007
+/* Disassembler interface for targets using CGEN. -*- C -*-
+ CGEN: Cpu tools GENerator
+
+ THIS FILE IS MACHINE GENERATED WITH CGEN.
+ - the resultant file is machine generated, cgen-dis.in isn't
+
+ Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007
Free Software Foundation, Inc.
- Contributed by Doug Evans (dje@cygnus.com).
This file is part of libopcodes.
@@ -16,1218 +20,801 @@
License for more details.
You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
- MA 02110-1301, USA. */
+ along with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+/* ??? Eventually more and more of this stuff can go to cpu-independent files.
+ Keep that in mind. */
+
+#include "sysdep.h"
+#include <stdio.h>
#include "ansidecl.h"
-#include "libiberty.h"
#include "dis-asm.h"
-#include "opcode/arc.h"
-#include "elf-bfd.h"
-#include "elf/arc.h"
-#include <string.h>
+#include "bfd.h"
+#include "symcat.h"
+#include "libiberty.h"
+#include "arc-desc.h"
+#include "arc-opc.h"
#include "opintl.h"
-#include <stdarg.h>
-#include "arc-dis.h"
-#include "arc-ext.h"
+/* Default text to print if an instruction isn't recognized. */
+#define UNKNOWN_INSN_MSG _("*unknown*")
-#ifndef dbg
-#define dbg (0)
+static void print_normal
+ (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
+static void print_address
+ (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED;
+static void print_keyword
+ (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED;
+static void print_insn_normal
+ (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
+static int print_insn
+ (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned);
+static int default_print_insn
+ (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED;
+static int read_insn
+ (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
+ unsigned long *);
+
+/* -- disassembler routines inserted here. */
+
+/* -- dis.c */
+char limm_str[11] = "0x";
+
+/* Read a long immediate and write it hexadecimally into limm_str. */
+static void
+read_limm (CGEN_EXTRACT_INFO *ex_info, bfd_vma pc)
+{
+ unsigned char buf[2];
+ int i;
+ char *limmp = limm_str + 2;
+ disassemble_info *dis_info = (disassemble_info *) ex_info->dis_info;
+
+ for (i = 0; i < 2; i++, limmp +=4, pc += 2)
+ {
+ int status = (*dis_info->read_memory_func) (pc, buf, 2, dis_info);
+
+ if (status != 0)
+ (*dis_info->memory_error_func) (status, pc, dis_info);
+ sprintf (limmp, "%.4x",
+ (unsigned) bfd_get_bits (buf, 16,
+ dis_info->endian == BFD_ENDIAN_BIG));
+ }
+}
+
+/* Return the actual instruction length, in bits, which depends on the size
+ of the opcode - 2 or 4 bytes - and the absence or presence of a (4 byte)
+ long immediate.
+ Also, if a long immediate is present, put its hexadecimal representation
+ into limm_str.
+ ??? cgen-opc.c:cgen_lookup_insn has a 'sanity' check of the length
+ that will fail if its input length differs from the result of
+ CGEN_EXTRACT_FN. Need to check when this could trigger. */
+int
+arc_insn_length (unsigned long insn_value, const CGEN_INSN *insn,
+ CGEN_EXTRACT_INFO *info, bfd_vma pc)
+{
+ switch (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_LIMM))
+ {
+ case LIMM_NONE:
+ return CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_SHORT_P) ? 16 : 32;
+ case LIMM_H:
+ {
+ /* This is a short insn; extract the actual opcode. */
+ unsigned high = insn_value >> 16;
+
+ if ((high & 0xe7) != 0xc7)
+ return 16;
+ read_limm (info, pc+2);
+ return 48;
+ }
+ case LIMM_B:
+ if ((insn_value & 0x07007000) != 0x06007000)
+ return 32;
+ break;
+ case LIMM_BC:
+ if ((insn_value & 0x07007000) == 0x06007000)
+ break;
+ /* Fall through. */
+ case LIMM_C:
+ if ((insn_value & 0x00000fc0) != 0x00000f80)
+ return 32;
+ break;
+ default:
+ abort ();
+ }
+ read_limm (info, pc+4);
+ return 64;
+}
+
+/* -- */
+
+void arc_cgen_print_operand
+ (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
+
+/* Main entry point for printing operands.
+ XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
+ of dis-asm.h on cgen.h.
+
+ This function is basically just a big switch statement. Earlier versions
+ used tables to look up the function to use, but
+ - if the table contains both assembler and disassembler functions then
+ the disassembler contains much of the assembler and vice-versa,
+ - there's a lot of inlining possibilities as things grow,
+ - using a switch statement avoids the function call overhead.
+
+ This function could be moved into `print_insn_normal', but keeping it
+ separate makes clear the interface between `print_insn_normal' and each of
+ the handlers. */
+
+void
+arc_cgen_print_operand (CGEN_CPU_DESC cd,
+ int opindex,
+ void * xinfo,
+ CGEN_FIELDS *fields,
+ void const *attrs ATTRIBUTE_UNUSED,
+ bfd_vma pc,
+ int length)
+{
+ disassemble_info *info = (disassemble_info *) xinfo;
+
+ switch (opindex)
+ {
+ case ARC_OPERAND_EXDI :
+ print_keyword (cd, info, & arc_cgen_opval_h_Di, fields->f_F, 0);
+ break;
+ case ARC_OPERAND_F :
+ print_keyword (cd, info, & arc_cgen_opval_h_uflags, fields->f_F, 0);
+ break;
+ case ARC_OPERAND_F0 :
+ print_keyword (cd, info, & arc_cgen_opval_h_nil, fields->f_F, 0);
+ break;
+ case ARC_OPERAND_F1 :
+ print_keyword (cd, info, & arc_cgen_opval_h_auflags, fields->f_F, 0);
+ break;
+ case ARC_OPERAND_F1F :
+ print_keyword (cd, info, & arc_cgen_opval_h_aufflags, fields->f_F, 0);
+ break;
+ case ARC_OPERAND_GP :
+ print_keyword (cd, info, & arc_cgen_opval_h_gp, 0, 0);
+ break;
+ case ARC_OPERAND_LDODI :
+ print_keyword (cd, info, & arc_cgen_opval_h_Di, fields->f_LDODi, 0);
+ break;
+ case ARC_OPERAND_LDRDI :
+ print_keyword (cd, info, & arc_cgen_opval_h_Di, fields->f_LDRDi, 0);
+ break;
+ case ARC_OPERAND_NE :
+ print_keyword (cd, info, & arc_cgen_opval_h_ne, 0, 0);
+ break;
+ case ARC_OPERAND_PCL :
+ print_keyword (cd, info, & arc_cgen_opval_h_pcl, 0, 0);
+ break;
+ case ARC_OPERAND_QCONDB :
+ print_keyword (cd, info, & arc_cgen_opval_h_Qcondb, fields->f_cond_Q, 0);
+ break;
+ case ARC_OPERAND_QCONDI :
+ print_keyword (cd, info, & arc_cgen_opval_h_Qcondi, fields->f_cond_Q, 0);
+ break;
+ case ARC_OPERAND_QCONDJ :
+ print_keyword (cd, info, & arc_cgen_opval_h_Qcondj, fields->f_cond_Q, 0);
+ break;
+ case ARC_OPERAND_R0 :
+ print_keyword (cd, info, & arc_cgen_opval_h_r0, 0, 0);
+ break;
+ case ARC_OPERAND_R31 :
+ print_keyword (cd, info, & arc_cgen_opval_h_r31, 0, 0);
+ break;
+ case ARC_OPERAND_RA :
+ print_keyword (cd, info, & arc_cgen_opval_cr_names, fields->f_op_A, 0);
+ break;
+ case ARC_OPERAND_RA_0 :
+ print_keyword (cd, info, & arc_cgen_opval_h_nil, fields->f_op_A, 0);
+ break;
+ case ARC_OPERAND_RB :
+ print_keyword (cd, info, & arc_cgen_opval_cr_names, fields->f_op_B, 0|(1<<CGEN_OPERAND_VIRTUAL));
+ break;
+ case ARC_OPERAND_RB_0 :
+ print_keyword (cd, info, & arc_cgen_opval_h_nil, fields->f_op_B, 0|(1<<CGEN_OPERAND_VIRTUAL));
+ break;
+ case ARC_OPERAND_RC :
+ print_keyword (cd, info, & arc_cgen_opval_cr_names, fields->f_op_C, 0);
+ break;
+ case ARC_OPERAND_RC_ILINK :
+ print_keyword (cd, info, & arc_cgen_opval_h_ilinkx, fields->f_op_Cj, 0);
+ break;
+ case ARC_OPERAND_RC_NOILINK :
+ print_keyword (cd, info, & arc_cgen_opval_h_noilink, fields->f_op_Cj, 0);
+ break;
+ case ARC_OPERAND_R_A :
+ print_keyword (cd, info, & arc_cgen_opval_h_cr16, fields->f_op__a, 0);
+ break;
+ case ARC_OPERAND_R_B :
+ print_keyword (cd, info, & arc_cgen_opval_h_cr16, fields->f_op__b, 0);
+ break;
+ case ARC_OPERAND_R_C :
+ print_keyword (cd, info, & arc_cgen_opval_h_cr16, fields->f_op__c, 0);
+ break;
+ case ARC_OPERAND_RCC :
+ print_keyword (cd, info, & arc_cgen_opval_h_Rcc, fields->f_brcond, 0);
+ break;
+ case ARC_OPERAND_RCCS :
+ print_keyword (cd, info, & arc_cgen_opval_h_RccS, fields->f_brscond, 0);
+ break;
+ case ARC_OPERAND_RH :
+ print_keyword (cd, info, & arc_cgen_opval_cr_names, fields->f_op_h, 0|(1<<CGEN_OPERAND_VIRTUAL));
+ break;
+ case ARC_OPERAND_SP :
+ print_keyword (cd, info, & arc_cgen_opval_h_sp, 0, 0);
+ break;
+ case ARC_OPERAND_STODI :
+ print_keyword (cd, info, & arc_cgen_opval_h_Di, fields->f_STODi, 0);
+ break;
+ case ARC_OPERAND_U6 :
+ print_normal (cd, info, fields->f_u6, 0, pc, length);
+ break;
+ case ARC_OPERAND_U6X2 :
+ print_normal (cd, info, fields->f_u6x2, 0, pc, length);
+ break;
+ case ARC_OPERAND__AW :
+ print_keyword (cd, info, & arc_cgen_opval_h__aw, 0, 0);
+ break;
+ case ARC_OPERAND__L :
+ print_keyword (cd, info, & arc_cgen_opval_h_insn32, 0, 0);
+ break;
+ case ARC_OPERAND__S :
+ print_keyword (cd, info, & arc_cgen_opval_h_insn16, 0, 0);
+ break;
+ case ARC_OPERAND_CBIT :
+ print_normal (cd, info, 0, 0, pc, length);
+ break;
+ case ARC_OPERAND_DELAY_N :
+ print_keyword (cd, info, & arc_cgen_opval_h_delay, fields->f_delay_N, 0);
+ break;
+ case ARC_OPERAND_DUMMY_OP :
+ print_normal (cd, info, fields->f_dummy, 0, pc, length);
+ break;
+ case ARC_OPERAND_I2COND :
+ print_keyword (cd, info, & arc_cgen_opval_h_i2cond, fields->f_cond_i2, 0);
+ break;
+ case ARC_OPERAND_I3COND :
+ print_keyword (cd, info, & arc_cgen_opval_h_i3cond, fields->f_cond_i3, 0);
+ break;
+ case ARC_OPERAND_LABEL10 :
+ print_address (cd, info, fields->f_rel10, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+ break;
+ case ARC_OPERAND_LABEL13A :
+ print_address (cd, info, fields->f_rel13bl, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+ break;
+ case ARC_OPERAND_LABEL21 :
+ print_address (cd, info, fields->f_rel21, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
+ break;
+ case ARC_OPERAND_LABEL21A :
+ print_address (cd, info, fields->f_rel21bl, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
+ break;
+ case ARC_OPERAND_LABEL25 :
+ print_address (cd, info, fields->f_rel25, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
+ break;
+ case ARC_OPERAND_LABEL25A :
+ print_address (cd, info, fields->f_rel25bl, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
+ break;
+ case ARC_OPERAND_LABEL7 :
+ print_address (cd, info, fields->f_rel7, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+ break;
+ case ARC_OPERAND_LABEL8 :
+ print_address (cd, info, fields->f_rel8, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+ break;
+ case ARC_OPERAND_LABEL9 :
+ print_address (cd, info, fields->f_rel9, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
+ break;
+ case ARC_OPERAND_LBIT :
+ print_normal (cd, info, 0, 0, pc, length);
+ break;
+ case ARC_OPERAND_NBIT :
+ print_normal (cd, info, 0, 0, pc, length);
+ break;
+ case ARC_OPERAND_S12 :
+ print_normal (cd, info, fields->f_s12, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
+ break;
+ case ARC_OPERAND_S12X2 :
+ print_normal (cd, info, fields->f_s12x2, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
+ break;
+ case ARC_OPERAND_S1BIT :
+ print_normal (cd, info, 0, 0, pc, length);
+ break;
+ case ARC_OPERAND_S2BIT :
+ print_normal (cd, info, 0, 0, pc, length);
+ break;
+ case ARC_OPERAND_S9 :
+ print_normal (cd, info, fields->f_s9, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
+ break;
+ case ARC_OPERAND_S9X4 :
+ print_normal (cd, info, fields->f_s9x4, 0, pc, length);
+ break;
+ case ARC_OPERAND_SC_S9_ :
+ print_normal (cd, info, fields->f_s9x4, 0, pc, length);
+ break;
+ case ARC_OPERAND_SC_S9B :
+ print_normal (cd, info, fields->f_s9x1, 0, pc, length);
+ break;
+ case ARC_OPERAND_SC_S9W :
+ print_normal (cd, info, fields->f_s9x2, 0, pc, length);
+ break;
+ case ARC_OPERAND_SC_U5_ :
+ print_normal (cd, info, fields->f_u5x4, 0, pc, length);
+ break;
+ case ARC_OPERAND_SC_U5B :
+ print_normal (cd, info, fields->f_u5, 0, pc, length);
+ break;
+ case ARC_OPERAND_SC_U5W :
+ print_normal (cd, info, fields->f_u5x2, 0, pc, length);
+ break;
+ case ARC_OPERAND_TRAPNUM :
+ print_normal (cd, info, fields->f_trapnum, 0, pc, length);
+ break;
+ case ARC_OPERAND_U3 :
+ print_normal (cd, info, fields->f_u3, 0, pc, length);
+ break;
+ case ARC_OPERAND_U5 :
+ print_normal (cd, info, fields->f_u5, 0, pc, length);
+ break;
+ case ARC_OPERAND_U5X4 :
+ print_normal (cd, info, fields->f_u5x4, 0, pc, length);
+ break;
+ case ARC_OPERAND_U7 :
+ print_normal (cd, info, fields->f_u7, 0, pc, length);
+ break;
+ case ARC_OPERAND_U8 :
+ print_normal (cd, info, fields->f_u8, 0, pc, length);
+ break;
+ case ARC_OPERAND_U8X4 :
+ print_normal (cd, info, fields->f_u8x4, 0, pc, length);
+ break;
+ case ARC_OPERAND_UNCONDB :
+ print_keyword (cd, info, & arc_cgen_opval_h_uncondb, 0, 0);
+ break;
+ case ARC_OPERAND_UNCONDI :
+ print_keyword (cd, info, & arc_cgen_opval_h_uncondi, 0, 0);
+ break;
+ case ARC_OPERAND_UNCONDJ :
+ print_keyword (cd, info, & arc_cgen_opval_h_uncondj, 0, 0);
+ break;
+ case ARC_OPERAND_VBIT :
+ print_normal (cd, info, 0, 0, pc, length);
+ break;
+ case ARC_OPERAND_ZBIT :
+ print_normal (cd, info, 0, 0, pc, length);
+ break;
+
+ default :
+ /* xgettext:c-format */
+ fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
+ opindex);
+ abort ();
+ }
+}
+
+cgen_print_fn * const arc_cgen_print_handlers[] =
+{
+ print_insn_normal,
+};
+
+
+void
+arc_cgen_init_dis (CGEN_CPU_DESC cd)
+{
+ arc_cgen_init_opcode_table (cd);
+ arc_cgen_init_ibld_table (cd);
+ cd->print_handlers = & arc_cgen_print_handlers[0];
+ cd->print_operand = arc_cgen_print_operand;
+}
+
+
+/* Default print handler. */
+
+static void
+print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ void *dis_info,
+ long value,
+ unsigned int attrs,
+ bfd_vma pc ATTRIBUTE_UNUSED,
+ int length ATTRIBUTE_UNUSED)
+{
+ disassemble_info *info = (disassemble_info *) dis_info;
+
+#ifdef CGEN_PRINT_NORMAL
+ CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length);
#endif
-/* Classification of the opcodes for the decoder to print
- the instructions. */
-
-typedef enum
-{
- CLASS_A4_ARITH,
- CLASS_A4_OP3_GENERAL,
- CLASS_A4_FLAG,
- /* All branches other than JC. */
- CLASS_A4_BRANCH,
- CLASS_A4_JC ,
- /* All loads other than immediate
- indexed loads. */
- CLASS_A4_LD0,
- CLASS_A4_LD1,
- CLASS_A4_ST,
- CLASS_A4_SR,
- /* All single operand instructions. */
- CLASS_A4_OP3_SUBOPC3F,
- CLASS_A4_LR
-} a4_decoding_class;
-
-#define BIT(word,n) ((word) & (1 << n))
-#define BITS(word,s,e) (((word) << (31 - e)) >> (s + (31 - e)))
-#define OPCODE(word) (BITS ((word), 27, 31))
-#define FIELDA(word) (BITS ((word), 21, 26))
-#define FIELDB(word) (BITS ((word), 15, 20))
-#define FIELDC(word) (BITS ((word), 9, 14))
-
-/* FIELD D is signed in all of its uses, so we make sure argument is
- treated as signed for bit shifting purposes: */
-#define FIELDD(word) (BITS (((signed int)word), 0, 8))
-
-#define PUT_NEXT_WORD_IN(a) \
- do \
- { \
- if (is_limm == 1 && !NEXT_WORD (1)) \
- mwerror (state, _("Illegal limm reference in last instruction!\n")); \
- a = state->words[1]; \
- } \
- while (0)
-
-#define CHECK_FLAG_COND_NULLIFY() \
- do \
- { \
- if (is_shimm == 0) \
- { \
- flag = BIT (state->words[0], 8); \
- state->nullifyMode = BITS (state->words[0], 5, 6); \
- cond = BITS (state->words[0], 0, 4); \
- } \
- } \
- while (0)
-
-#define CHECK_COND() \
- do \
- { \
- if (is_shimm == 0) \
- cond = BITS (state->words[0], 0, 4); \
- } \
- while (0)
-
-#define CHECK_FIELD(field) \
- do \
- { \
- if (field == 62) \
- { \
- is_limm++; \
- field##isReg = 0; \
- PUT_NEXT_WORD_IN (field); \
- limm_value = field; \
- } \
- else if (field > 60) \
- { \
- field##isReg = 0; \
- is_shimm++; \
- flag = (field == 61); \
- field = FIELDD (state->words[0]); \
- } \
- } \
- while (0)
-
-#define CHECK_FIELD_A() \
- do \
- { \
- fieldA = FIELDA (state->words[0]); \
- if (fieldA > 60) \
- { \
- fieldAisReg = 0; \
- fieldA = 0; \
- } \
- } \
- while (0)
-
-#define CHECK_FIELD_B() \
- do \
- { \
- fieldB = FIELDB (state->words[0]); \
- CHECK_FIELD (fieldB); \
- } \
- while (0)
-
-#define CHECK_FIELD_C() \
- do \
- { \
- fieldC = FIELDC (state->words[0]); \
- CHECK_FIELD (fieldC); \
- } \
- while (0)
-
-#define IS_SMALL(x) (((field##x) < 256) && ((field##x) > -257))
-#define IS_REG(x) (field##x##isReg)
-#define WRITE_FORMAT_LB_Rx_RB(x) WRITE_FORMAT (x, "[","]","","")
-#define WRITE_FORMAT_x_COMMA_LB(x) WRITE_FORMAT (x, "",",[","",",[")
-#define WRITE_FORMAT_COMMA_x_RB(x) WRITE_FORMAT (x, ",","]",",","]")
-#define WRITE_FORMAT_x_RB(x) WRITE_FORMAT (x, "","]","","]")
-#define WRITE_FORMAT_COMMA_x(x) WRITE_FORMAT (x, ",","",",","")
-#define WRITE_FORMAT_x_COMMA(x) WRITE_FORMAT (x, "",",","",",")
-#define WRITE_FORMAT_x(x) WRITE_FORMAT (x, "","","","")
-#define WRITE_FORMAT(x,cb1,ca1,cb,ca) strcat (formatString, \
- (IS_REG (x) ? cb1"%r"ca1 : \
- usesAuxReg ? cb"%a"ca : \
- IS_SMALL (x) ? cb"%d"ca : cb"%h"ca))
-#define WRITE_FORMAT_RB() strcat (formatString, "]")
-#define WRITE_COMMENT(str) (state->comm[state->commNum++] = (str))
-#define WRITE_NOP_COMMENT() if (!fieldAisReg && !flag) WRITE_COMMENT ("nop");
-
-#define NEXT_WORD(x) (offset += 4, state->words[x])
-
-#define add_target(x) (state->targets[state->tcnt++] = (x))
-
-static char comment_prefix[] = "\t; ";
-
-static const char *
-core_reg_name (struct arcDisState * state, int val)
-{
- if (state->coreRegName)
- return (*state->coreRegName)(state->_this, val);
- return 0;
+ /* Print the operand as directed by the attributes. */
+ if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
+ ; /* nothing to do */
+ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
+ (*info->fprintf_func) (info->stream, "%ld", value);
+ else
+ (*info->fprintf_func) (info->stream, "0x%lx", value);
}
-static const char *
-aux_reg_name (struct arcDisState * state, int val)
-{
- if (state->auxRegName)
- return (*state->auxRegName)(state->_this, val);
- return 0;
-}
-
-static const char *
-cond_code_name (struct arcDisState * state, int val)
-{
- if (state->condCodeName)
- return (*state->condCodeName)(state->_this, val);
- return 0;
-}
-
-static const char *
-instruction_name (struct arcDisState * state,
- int op1,
- int op2,
- int * flags)
-{
- if (state->instName)
- return (*state->instName)(state->_this, op1, op2, flags);
- return 0;
-}
+/* Default address handler. */
static void
-mwerror (struct arcDisState * state, const char * msg)
+print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ void *dis_info,
+ bfd_vma value,
+ unsigned int attrs,
+ bfd_vma pc ATTRIBUTE_UNUSED,
+ int length ATTRIBUTE_UNUSED)
{
- if (state->err != 0)
- (*state->err)(state->_this, (msg));
+ disassemble_info *info = (disassemble_info *) dis_info;
+
+#ifdef CGEN_PRINT_ADDRESS
+ CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length);
+#endif
+
+ /* Print the operand as directed by the attributes. */
+ if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
+ ; /* Nothing to do. */
+ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
+ (*info->print_address_func) (value, info);
+ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
+ (*info->print_address_func) (value, info);
+ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
+ (*info->fprintf_func) (info->stream, "%ld", (long) value);
+ else
+ (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
}
-static const char *
-post_address (struct arcDisState * state, int addr)
-{
- static char id[3 * ARRAY_SIZE (state->addresses)];
- int j, i = state->acnt;
+/* Keyword print handler. */
- if (i < ((int) ARRAY_SIZE (state->addresses)))
+static void
+print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ void *dis_info,
+ CGEN_KEYWORD *keyword_table,
+ long value,
+ unsigned int attrs ATTRIBUTE_UNUSED)
+{
+ disassemble_info *info = (disassemble_info *) dis_info;
+ const CGEN_KEYWORD_ENTRY *ke;
+
+ ke = cgen_keyword_lookup_value (keyword_table, value);
+ if (ke != NULL)
+ (*info->fprintf_func) (info->stream, "%s", ke->name);
+ else
+ (*info->fprintf_func) (info->stream, "???");
+}
+
+/* Default insn printer.
+
+ DIS_INFO is defined as `void *' so the disassembler needn't know anything
+ about disassemble_info. */
+
+static void
+print_insn_normal (CGEN_CPU_DESC cd,
+ void *dis_info,
+ const CGEN_INSN *insn,
+ CGEN_FIELDS *fields,
+ bfd_vma pc,
+ int length)
+{
+ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+ disassemble_info *info = (disassemble_info *) dis_info;
+ const CGEN_SYNTAX_CHAR_TYPE *syn;
+
+ CGEN_INIT_PRINT (cd);
+
+ for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
{
- state->addresses[i] = addr;
- ++state->acnt;
- j = i*3;
- id[j+0] = '@';
- id[j+1] = '0'+i;
- id[j+2] = 0;
-
- return id + j;
- }
- return "";
-}
-
-static void
-arc_sprintf (struct arcDisState *state, char *buf, const char *format, ...)
-{
- char *bp;
- const char *p;
- int size, leading_zero, regMap[2];
- long auxNum;
- va_list ap;
-
- va_start (ap, format);
-
- bp = buf;
- *bp = 0;
- p = format;
- auxNum = -1;
- regMap[0] = 0;
- regMap[1] = 0;
-
- while (1)
- switch (*p++)
- {
- case 0:
- goto DOCOMM; /* (return) */
- default:
- *bp++ = p[-1];
- break;
- case '%':
- size = 0;
- leading_zero = 0;
- RETRY: ;
- switch (*p++)
- {
- case '0':
- case '1':
- case '2':
- case '3':
- case '4':
- case '5':
- case '6':
- case '7':
- case '8':
- case '9':
- {
- /* size. */
- size = p[-1] - '0';
- if (size == 0)
- leading_zero = 1; /* e.g. %08x */
- while (*p >= '0' && *p <= '9')
- {
- size = size * 10 + *p - '0';
- p++;
- }
- goto RETRY;
- }
-#define inc_bp() bp = bp + strlen (bp)
-
- case 'h':
- {
- unsigned u = va_arg (ap, int);
-
- /* Hex. We can change the format to 0x%08x in
- one place, here, if we wish.
- We add underscores for easy reading. */
- if (u > 65536)
- sprintf (bp, "0x%x_%04x", u >> 16, u & 0xffff);
- else
- sprintf (bp, "0x%x", u);
- inc_bp ();
- }
- break;
- case 'X': case 'x':
- {
- int val = va_arg (ap, int);
-
- if (size != 0)
- if (leading_zero)
- sprintf (bp, "%0*x", size, val);
- else
- sprintf (bp, "%*x", size, val);
- else
- sprintf (bp, "%x", val);
- inc_bp ();
- }
- break;
- case 'd':
- {
- int val = va_arg (ap, int);
-
- if (size != 0)
- sprintf (bp, "%*d", size, val);
- else
- sprintf (bp, "%d", val);
- inc_bp ();
- }
- break;
- case 'r':
- {
- /* Register. */
- int val = va_arg (ap, int);
-
-#define REG2NAME(num, name) case num: sprintf (bp, ""name); \
- regMap[(num < 32) ? 0 : 1] |= 1 << (num - ((num < 32) ? 0 : 32)); break;
-
- switch (val)
- {
- REG2NAME (26, "gp");
- REG2NAME (27, "fp");
- REG2NAME (28, "sp");
- REG2NAME (29, "ilink1");
- REG2NAME (30, "ilink2");
- REG2NAME (31, "blink");
- REG2NAME (60, "lp_count");
- default:
- {
- const char * ext;
-
- ext = core_reg_name (state, val);
- if (ext)
- sprintf (bp, "%s", ext);
- else
- sprintf (bp,"r%d",val);
- }
- break;
- }
- inc_bp ();
- } break;
-
- case 'a':
- {
- /* Aux Register. */
- int val = va_arg (ap, int);
-
-#define AUXREG2NAME(num, name) case num: sprintf (bp,name); break;
-
- switch (val)
- {
- AUXREG2NAME (0x0, "status");
- AUXREG2NAME (0x1, "semaphore");
- AUXREG2NAME (0x2, "lp_start");
- AUXREG2NAME (0x3, "lp_end");
- AUXREG2NAME (0x4, "identity");
- AUXREG2NAME (0x5, "debug");
- default:
- {
- const char *ext;
-
- ext = aux_reg_name (state, val);
- if (ext)
- sprintf (bp, "%s", ext);
- else
- arc_sprintf (state, bp, "%h", val);
- }
- break;
- }
- inc_bp ();
- }
- break;
-
- case 's':
- {
- sprintf (bp, "%s", va_arg (ap, char *));
- inc_bp ();
- }
- break;
-
- default:
- fprintf (stderr, "?? format %c\n", p[-1]);
- break;
- }
- }
-
- DOCOMM: *bp = 0;
- va_end (ap);
-}
-
-static void
-write_comments_(struct arcDisState * state,
- int shimm,
- int is_limm,
- long limm_value)
-{
- if (state->commentBuffer != 0)
- {
- int i;
-
- if (is_limm)
+ if (CGEN_SYNTAX_MNEMONIC_P (*syn))
{
- const char *name = post_address (state, limm_value + shimm);
-
- if (*name != 0)
- WRITE_COMMENT (name);
+ (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
+ continue;
}
- for (i = 0; i < state->commNum; i++)
+ if (CGEN_SYNTAX_CHAR_P (*syn))
{
- if (i == 0)
- strcpy (state->commentBuffer, comment_prefix);
- else
- strcat (state->commentBuffer, ", ");
- strncat (state->commentBuffer, state->comm[i],
- sizeof (state->commentBuffer));
+ (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
+ continue;
}
+
+ /* We have an operand. */
+ arc_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
+ fields, CGEN_INSN_ATTRS (insn), pc, length);
}
}
-
-#define write_comments2(x) write_comments_ (state, x, is_limm, limm_value)
-#define write_comments() write_comments2 (0)
-
-static const char *condName[] =
-{
- /* 0..15. */
- "" , "z" , "nz" , "p" , "n" , "c" , "nc" , "v" ,
- "nv" , "gt" , "ge" , "lt" , "le" , "hi" , "ls" , "pnz"
-};
-
-static void
-write_instr_name_(struct arcDisState * state,
- const char * instrName,
- int cond,
- int condCodeIsPartOfName,
- int flag,
- int signExtend,
- int addrWriteBack,
- int directMem)
-{
- strcpy (state->instrBuffer, instrName);
-
- if (cond > 0)
- {
- const char *cc = 0;
-
- if (!condCodeIsPartOfName)
- strcat (state->instrBuffer, ".");
-
- if (cond < 16)
- cc = condName[cond];
- else
- cc = cond_code_name (state, cond);
-
- if (!cc)
- cc = "???";
-
- strcat (state->instrBuffer, cc);
- }
-
- if (flag)
- strcat (state->instrBuffer, ".f");
-
- switch (state->nullifyMode)
- {
- case BR_exec_always:
- strcat (state->instrBuffer, ".d");
- break;
- case BR_exec_when_jump:
- strcat (state->instrBuffer, ".jd");
- break;
- }
-
- if (signExtend)
- strcat (state->instrBuffer, ".x");
-
- if (addrWriteBack)
- strcat (state->instrBuffer, ".a");
-
- if (directMem)
- strcat (state->instrBuffer, ".di");
-}
-
-#define write_instr_name() \
- do \
- { \
- write_instr_name_(state, instrName,cond, condCodeIsPartOfName, \
- flag, signExtend, addrWriteBack, directMem); \
- formatString[0] = '\0'; \
- } \
- while (0)
-
-enum
-{
- op_LD0 = 0, op_LD1 = 1, op_ST = 2, op_3 = 3,
- op_BC = 4, op_BLC = 5, op_LPC = 6, op_JC = 7,
- op_ADD = 8, op_ADC = 9, op_SUB = 10, op_SBC = 11,
- op_AND = 12, op_OR = 13, op_BIC = 14, op_XOR = 15
-};
-
-extern disassemble_info tm_print_insn_info;
+
+/* Subroutine of print_insn. Reads an insn into the given buffers and updates
+ the extract info.
+ Returns 0 if all is well, non-zero otherwise. */
static int
-dsmOneArcInst (bfd_vma addr, struct arcDisState * state)
+read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ bfd_vma pc,
+ disassemble_info *info,
+ bfd_byte *buf,
+ int buflen,
+ CGEN_EXTRACT_INFO *ex_info,
+ unsigned long *insn_value)
{
- int condCodeIsPartOfName = 0;
- a4_decoding_class decodingClass;
- const char * instrName;
- int repeatsOp = 0;
- int fieldAisReg = 1;
- int fieldBisReg = 1;
- int fieldCisReg = 1;
- int fieldA;
- int fieldB;
- int fieldC = 0;
- int flag = 0;
- int cond = 0;
- int is_shimm = 0;
- int is_limm = 0;
- long limm_value = 0;
- int signExtend = 0;
- int addrWriteBack = 0;
- int directMem = 0;
- int is_linked = 0;
- int offset = 0;
- int usesAuxReg = 0;
- int flags;
- int ignoreFirstOpd;
- char formatString[60];
+ int status = (*info->read_memory_func) (pc, buf, buflen, info);
- state->instructionLen = 4;
- state->nullifyMode = BR_exec_when_no_jump;
- state->opWidth = 12;
- state->isBranch = 0;
-
- state->_mem_load = 0;
- state->_ea_present = 0;
- state->_load_len = 0;
- state->ea_reg1 = no_reg;
- state->ea_reg2 = no_reg;
- state->_offset = 0;
-
- if (! NEXT_WORD (0))
- return 0;
-
- state->_opcode = OPCODE (state->words[0]);
- instrName = 0;
- decodingClass = CLASS_A4_ARITH; /* default! */
- repeatsOp = 0;
- condCodeIsPartOfName=0;
- state->commNum = 0;
- state->tcnt = 0;
- state->acnt = 0;
- state->flow = noflow;
- ignoreFirstOpd = 0;
-
- if (state->commentBuffer)
- state->commentBuffer[0] = '\0';
-
- switch (state->_opcode)
- {
- case op_LD0:
- switch (BITS (state->words[0],1,2))
- {
- case 0:
- instrName = "ld";
- state->_load_len = 4;
- break;
- case 1:
- instrName = "ldb";
- state->_load_len = 1;
- break;
- case 2:
- instrName = "ldw";
- state->_load_len = 2;
- break;
- default:
- instrName = "??? (0[3])";
- state->flow = invalid_instr;
- break;
- }
- decodingClass = CLASS_A4_LD0;
- break;
-
- case op_LD1:
- if (BIT (state->words[0],13))
- {
- instrName = "lr";
- decodingClass = CLASS_A4_LR;
- }
- else
- {
- switch (BITS (state->words[0], 10, 11))
- {
- case 0:
- instrName = "ld";
- state->_load_len = 4;
- break;
- case 1:
- instrName = "ldb";
- state->_load_len = 1;
- break;
- case 2:
- instrName = "ldw";
- state->_load_len = 2;
- break;
- default:
- instrName = "??? (1[3])";
- state->flow = invalid_instr;
- break;
- }
- decodingClass = CLASS_A4_LD1;
- }
- break;
-
- case op_ST:
- if (BIT (state->words[0], 25))
- {
- instrName = "sr";
- decodingClass = CLASS_A4_SR;
- }
- else
- {
- switch (BITS (state->words[0], 22, 23))
- {
- case 0:
- instrName = "st";
- break;
- case 1:
- instrName = "stb";
- break;
- case 2:
- instrName = "stw";
- break;
- default:
- instrName = "??? (2[3])";
- state->flow = invalid_instr;
- break;
- }
- decodingClass = CLASS_A4_ST;
- }
- break;
-
- case op_3:
- decodingClass = CLASS_A4_OP3_GENERAL; /* default for opcode 3... */
- switch (FIELDC (state->words[0]))
- {
- case 0:
- instrName = "flag";
- decodingClass = CLASS_A4_FLAG;
- break;
- case 1:
- instrName = "asr";
- break;
- case 2:
- instrName = "lsr";
- break;
- case 3:
- instrName = "ror";
- break;
- case 4:
- instrName = "rrc";
- break;
- case 5:
- instrName = "sexb";
- break;
- case 6:
- instrName = "sexw";
- break;
- case 7:
- instrName = "extb";
- break;
- case 8:
- instrName = "extw";
- break;
- case 0x3f:
- {
- decodingClass = CLASS_A4_OP3_SUBOPC3F;
- switch (FIELDD (state->words[0]))
- {
- case 0:
- instrName = "brk";
- break;
- case 1:
- instrName = "sleep";
- break;
- case 2:
- instrName = "swi";
- break;
- default:
- instrName = "???";
- state->flow=invalid_instr;
- break;
- }
- }
- break;
-
- /* ARC Extension Library Instructions
- NOTE: We assume that extension codes are these instrs. */
- default:
- instrName = instruction_name (state,
- state->_opcode,
- FIELDC (state->words[0]),
- &flags);
- if (!instrName)
- {
- instrName = "???";
- state->flow = invalid_instr;
- }
- if (flags & IGNORE_FIRST_OPD)
- ignoreFirstOpd = 1;
- break;
- }
- break;
-
- case op_BC:
- instrName = "b";
- case op_BLC:
- if (!instrName)
- instrName = "bl";
- case op_LPC:
- if (!instrName)
- instrName = "lp";
- case op_JC:
- if (!instrName)
- {
- if (BITS (state->words[0],9,9))
- {
- instrName = "jl";
- is_linked = 1;
- }
- else
- {
- instrName = "j";
- is_linked = 0;
- }
- }
- condCodeIsPartOfName = 1;
- decodingClass = ((state->_opcode == op_JC) ? CLASS_A4_JC : CLASS_A4_BRANCH );
- state->isBranch = 1;
- break;
-
- case op_ADD:
- case op_ADC:
- case op_AND:
- repeatsOp = (FIELDC (state->words[0]) == FIELDB (state->words[0]));
-
- switch (state->_opcode)
- {
- case op_ADD:
- instrName = (repeatsOp ? "asl" : "add");
- break;
- case op_ADC:
- instrName = (repeatsOp ? "rlc" : "adc");
- break;
- case op_AND:
- instrName = (repeatsOp ? "mov" : "and");
- break;
- }
- break;
-
- case op_SUB: instrName = "sub";
- break;
- case op_SBC: instrName = "sbc";
- break;
- case op_OR: instrName = "or";
- break;
- case op_BIC: instrName = "bic";
- break;
-
- case op_XOR:
- if (state->words[0] == 0x7fffffff)
- {
- /* NOP encoded as xor -1, -1, -1. */
- instrName = "nop";
- decodingClass = CLASS_A4_OP3_SUBOPC3F;
- }
- else
- instrName = "xor";
- break;
-
- default:
- instrName = instruction_name (state,state->_opcode,0,&flags);
- /* if (instrName) printf("FLAGS=0x%x\n", flags); */
- if (!instrName)
- {
- instrName = "???";
- state->flow=invalid_instr;
- }
- if (flags & IGNORE_FIRST_OPD)
- ignoreFirstOpd = 1;
- break;
- }
-
- fieldAisReg = fieldBisReg = fieldCisReg = 1; /* Assume regs for now. */
- flag = cond = is_shimm = is_limm = 0;
- state->nullifyMode = BR_exec_when_no_jump; /* 0 */
- signExtend = addrWriteBack = directMem = 0;
- usesAuxReg = 0;
-
- switch (decodingClass)
- {
- case CLASS_A4_ARITH:
- CHECK_FIELD_A ();
- CHECK_FIELD_B ();
- if (!repeatsOp)
- CHECK_FIELD_C ();
- CHECK_FLAG_COND_NULLIFY ();
-
- write_instr_name ();
- if (!ignoreFirstOpd)
- {
- WRITE_FORMAT_x (A);
- WRITE_FORMAT_COMMA_x (B);
- if (!repeatsOp)
- WRITE_FORMAT_COMMA_x (C);
- WRITE_NOP_COMMENT ();
- arc_sprintf (state, state->operandBuffer, formatString,
- fieldA, fieldB, fieldC);
- }
- else
- {
- WRITE_FORMAT_x (B);
- if (!repeatsOp)
- WRITE_FORMAT_COMMA_x (C);
- arc_sprintf (state, state->operandBuffer, formatString,
- fieldB, fieldC);
- }
- write_comments ();
- break;
-
- case CLASS_A4_OP3_GENERAL:
- CHECK_FIELD_A ();
- CHECK_FIELD_B ();
- CHECK_FLAG_COND_NULLIFY ();
-
- write_instr_name ();
- if (!ignoreFirstOpd)
- {
- WRITE_FORMAT_x (A);
- WRITE_FORMAT_COMMA_x (B);
- WRITE_NOP_COMMENT ();
- arc_sprintf (state, state->operandBuffer, formatString,
- fieldA, fieldB);
- }
- else
- {
- WRITE_FORMAT_x (B);
- arc_sprintf (state, state->operandBuffer, formatString, fieldB);
- }
- write_comments ();
- break;
-
- case CLASS_A4_FLAG:
- CHECK_FIELD_B ();
- CHECK_FLAG_COND_NULLIFY ();
- flag = 0; /* This is the FLAG instruction -- it's redundant. */
-
- write_instr_name ();
- WRITE_FORMAT_x (B);
- arc_sprintf (state, state->operandBuffer, formatString, fieldB);
- write_comments ();
- break;
-
- case CLASS_A4_BRANCH:
- fieldA = BITS (state->words[0],7,26) << 2;
- fieldA = (fieldA << 10) >> 10; /* Make it signed. */
- fieldA += addr + 4;
- CHECK_FLAG_COND_NULLIFY ();
- flag = 0;
-
- write_instr_name ();
- /* This address could be a label we know. Convert it. */
- if (state->_opcode != op_LPC /* LP */)
- {
- add_target (fieldA); /* For debugger. */
- state->flow = state->_opcode == op_BLC /* BL */
- ? direct_call
- : direct_jump;
- /* indirect calls are achieved by "lr blink,[status];
- lr dest<- func addr; j [dest]" */
- }
-
- strcat (formatString, "%s"); /* Address/label name. */
- arc_sprintf (state, state->operandBuffer, formatString,
- post_address (state, fieldA));
- write_comments ();
- break;
-
- case CLASS_A4_JC:
- /* For op_JC -- jump to address specified.
- Also covers jump and link--bit 9 of the instr. word
- selects whether linked, thus "is_linked" is set above. */
- fieldA = 0;
- CHECK_FIELD_B ();
- CHECK_FLAG_COND_NULLIFY ();
-
- if (!fieldBisReg)
- {
- fieldAisReg = 0;
- fieldA = (fieldB >> 25) & 0x7F; /* Flags. */
- fieldB = (fieldB & 0xFFFFFF) << 2;
- state->flow = is_linked ? direct_call : direct_jump;
- add_target (fieldB);
- /* Screwy JLcc requires .jd mode to execute correctly
- but we pretend it is .nd (no delay slot). */
- if (is_linked && state->nullifyMode == BR_exec_when_jump)
- state->nullifyMode = BR_exec_when_no_jump;
- }
- else
- {
- state->flow = is_linked ? indirect_call : indirect_jump;
- /* We should also treat this as indirect call if NOT linked
- but the preceding instruction was a "lr blink,[status]"
- and we have a delay slot with "add blink,blink,2".
- For now we can't detect such. */
- state->register_for_indirect_jump = fieldB;
- }
-
- write_instr_name ();
- strcat (formatString,
- IS_REG (B) ? "[%r]" : "%s"); /* Address/label name. */
- if (fieldA != 0)
- {
- fieldAisReg = 0;
- WRITE_FORMAT_COMMA_x (A);
- }
- if (IS_REG (B))
- arc_sprintf (state, state->operandBuffer, formatString, fieldB, fieldA);
- else
- arc_sprintf (state, state->operandBuffer, formatString,
- post_address (state, fieldB), fieldA);
- write_comments ();
- break;
-
- case CLASS_A4_LD0:
- /* LD instruction.
- B and C can be regs, or one (both?) can be limm. */
- CHECK_FIELD_A ();
- CHECK_FIELD_B ();
- CHECK_FIELD_C ();
- if (dbg)
- printf ("5:b reg %d %d c reg %d %d \n",
- fieldBisReg,fieldB,fieldCisReg,fieldC);
- state->_offset = 0;
- state->_ea_present = 1;
- if (fieldBisReg)
- state->ea_reg1 = fieldB;
- else
- state->_offset += fieldB;
- if (fieldCisReg)
- state->ea_reg2 = fieldC;
- else
- state->_offset += fieldC;
- state->_mem_load = 1;
-
- directMem = BIT (state->words[0], 5);
- addrWriteBack = BIT (state->words[0], 3);
- signExtend = BIT (state->words[0], 0);
-
- write_instr_name ();
- WRITE_FORMAT_x_COMMA_LB(A);
- if (fieldBisReg || fieldB != 0)
- WRITE_FORMAT_x_COMMA (B);
- else
- fieldB = fieldC;
-
- WRITE_FORMAT_x_RB (C);
- arc_sprintf (state, state->operandBuffer, formatString,
- fieldA, fieldB, fieldC);
- write_comments ();
- break;
-
- case CLASS_A4_LD1:
- /* LD instruction. */
- CHECK_FIELD_B ();
- CHECK_FIELD_A ();
- fieldC = FIELDD (state->words[0]);
-
- if (dbg)
- printf ("6:b reg %d %d c 0x%x \n",
- fieldBisReg, fieldB, fieldC);
- state->_ea_present = 1;
- state->_offset = fieldC;
- state->_mem_load = 1;
- if (fieldBisReg)
- state->ea_reg1 = fieldB;
- /* Field B is either a shimm (same as fieldC) or limm (different!)
- Say ea is not present, so only one of us will do the name lookup. */
- else
- state->_offset += fieldB, state->_ea_present = 0;
-
- directMem = BIT (state->words[0],14);
- addrWriteBack = BIT (state->words[0],12);
- signExtend = BIT (state->words[0],9);
-
- write_instr_name ();
- WRITE_FORMAT_x_COMMA_LB (A);
- if (!fieldBisReg)
- {
- fieldB = state->_offset;
- WRITE_FORMAT_x_RB (B);
- }
- else
- {
- WRITE_FORMAT_x (B);
- if (fieldC != 0 && !BIT (state->words[0],13))
- {
- fieldCisReg = 0;
- WRITE_FORMAT_COMMA_x_RB (C);
- }
- else
- WRITE_FORMAT_RB ();
- }
- arc_sprintf (state, state->operandBuffer, formatString,
- fieldA, fieldB, fieldC);
- write_comments ();
- break;
-
- case CLASS_A4_ST:
- /* ST instruction. */
- CHECK_FIELD_B();
- CHECK_FIELD_C();
- fieldA = FIELDD(state->words[0]); /* shimm */
-
- /* [B,A offset] */
- if (dbg) printf("7:b reg %d %x off %x\n",
- fieldBisReg,fieldB,fieldA);
- state->_ea_present = 1;
- state->_offset = fieldA;
- if (fieldBisReg)
- state->ea_reg1 = fieldB;
- /* Field B is either a shimm (same as fieldA) or limm (different!)
- Say ea is not present, so only one of us will do the name lookup.
- (for is_limm we do the name translation here). */
- else
- state->_offset += fieldB, state->_ea_present = 0;
-
- directMem = BIT (state->words[0], 26);
- addrWriteBack = BIT (state->words[0], 24);
-
- write_instr_name ();
- WRITE_FORMAT_x_COMMA_LB(C);
-
- if (!fieldBisReg)
- {
- fieldB = state->_offset;
- WRITE_FORMAT_x_RB (B);
- }
- else
- {
- WRITE_FORMAT_x (B);
- if (fieldBisReg && fieldA != 0)
- {
- fieldAisReg = 0;
- WRITE_FORMAT_COMMA_x_RB(A);
- }
- else
- WRITE_FORMAT_RB();
- }
- arc_sprintf (state, state->operandBuffer, formatString,
- fieldC, fieldB, fieldA);
- write_comments2 (fieldA);
- break;
-
- case CLASS_A4_SR:
- /* SR instruction */
- CHECK_FIELD_B();
- CHECK_FIELD_C();
-
- write_instr_name ();
- WRITE_FORMAT_x_COMMA_LB(C);
- /* Try to print B as an aux reg if it is not a core reg. */
- usesAuxReg = 1;
- WRITE_FORMAT_x (B);
- WRITE_FORMAT_RB ();
- arc_sprintf (state, state->operandBuffer, formatString, fieldC, fieldB);
- write_comments ();
- break;
-
- case CLASS_A4_OP3_SUBOPC3F:
- write_instr_name ();
- state->operandBuffer[0] = '\0';
- break;
-
- case CLASS_A4_LR:
- /* LR instruction */
- CHECK_FIELD_A ();
- CHECK_FIELD_B ();
-
- write_instr_name ();
- WRITE_FORMAT_x_COMMA_LB (A);
- /* Try to print B as an aux reg if it is not a core reg. */
- usesAuxReg = 1;
- WRITE_FORMAT_x (B);
- WRITE_FORMAT_RB ();
- arc_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB);
- write_comments ();
- break;
-
- default:
- mwerror (state, "Bad decoding class in ARC disassembler");
- break;
- }
-
- state->_cond = cond;
- return state->instructionLen = offset;
-}
-
-
-/* Returns the name the user specified core extension register. */
-
-static const char *
-_coreRegName(void * arg ATTRIBUTE_UNUSED, int regval)
-{
- return arcExtMap_coreRegName (regval);
-}
-
-/* Returns the name the user specified AUX extension register. */
-
-static const char *
-_auxRegName(void *_this ATTRIBUTE_UNUSED, int regval)
-{
- return arcExtMap_auxRegName(regval);
-}
-
-/* Returns the name the user specified condition code name. */
-
-static const char *
-_condCodeName(void *_this ATTRIBUTE_UNUSED, int regval)
-{
- return arcExtMap_condCodeName(regval);
-}
-
-/* Returns the name the user specified extension instruction. */
-
-static const char *
-_instName (void *_this ATTRIBUTE_UNUSED, int majop, int minop, int *flags)
-{
- return arcExtMap_instName(majop, minop, flags);
-}
-
-/* Decode an instruction returning the size of the instruction
- in bytes or zero if unrecognized. */
-
-static int
-decodeInstr (bfd_vma address, /* Address of this instruction. */
- disassemble_info * info)
-{
- int status;
- bfd_byte buffer[4];
- struct arcDisState s; /* ARC Disassembler state. */
- void *stream = info->stream; /* Output stream. */
- fprintf_ftype func = info->fprintf_func;
- int bytes;
-
- memset (&s, 0, sizeof(struct arcDisState));
-
- /* read first instruction */
- status = (*info->read_memory_func) (address, buffer, 4, info);
if (status != 0)
{
- (*info->memory_error_func) (status, address, info);
- return 0;
+ (*info->memory_error_func) (status, pc, info);
+ return -1;
}
- if (info->endian == BFD_ENDIAN_LITTLE)
- s.words[0] = bfd_getl32(buffer);
- else
- s.words[0] = bfd_getb32(buffer);
- /* Always read second word in case of limm. */
- /* We ignore the result since last insn may not have a limm. */
- status = (*info->read_memory_func) (address + 4, buffer, 4, info);
- if (info->endian == BFD_ENDIAN_LITTLE)
- s.words[1] = bfd_getl32(buffer);
- else
- s.words[1] = bfd_getb32(buffer);
+ ex_info->dis_info = info;
+ ex_info->valid = (1 << buflen) - 1;
+ ex_info->insn_bytes = buf;
- s._this = &s;
- s.coreRegName = _coreRegName;
- s.auxRegName = _auxRegName;
- s.condCodeName = _condCodeName;
- s.instName = _instName;
-
- /* Disassemble. */
- bytes = dsmOneArcInst (address, (void *)& s);
-
- /* Display the disassembly instruction. */
- (*func) (stream, "%08lx ", s.words[0]);
- (*func) (stream, " ");
- (*func) (stream, "%-10s ", s.instrBuffer);
-
- if (__TRANSLATION_REQUIRED (s))
- {
- bfd_vma addr = s.addresses[s.operandBuffer[1] - '0'];
-
- (*info->print_address_func) ((bfd_vma) addr, info);
- (*func) (stream, "\n");
- }
- else
- (*func) (stream, "%s",s.operandBuffer);
-
- return s.instructionLen;
+ *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
+ return 0;
}
-/* Return the print_insn function to use.
- Side effect: load (possibly empty) extension section */
+/* Utility to print an insn.
+ BUF is the base part of the insn, target byte order, BUFLEN bytes long.
+ The result is the size of the insn in bytes or zero for an unknown insn
+ or -1 if an error occurs fetching data (memory_error_func will have
+ been called). */
-disassembler_ftype
-arc_get_disassembler (void *ptr)
+static int
+print_insn (CGEN_CPU_DESC cd,
+ bfd_vma pc,
+ disassemble_info *info,
+ bfd_byte *buf,
+ unsigned int buflen)
{
- if (ptr)
- build_ARC_extmap (ptr);
- return decodeInstr;
+ CGEN_INSN_INT insn_value;
+ const CGEN_INSN_LIST *insn_list;
+ CGEN_EXTRACT_INFO ex_info;
+ int basesize;
+
+ /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
+ basesize = cd->base_insn_bitsize < buflen * 8 ?
+ cd->base_insn_bitsize : buflen * 8;
+ insn_value = cgen_get_insn_value (cd, buf, basesize);
+
+
+ /* Fill in ex_info fields like read_insn would. Don't actually call
+ read_insn, since the incoming buffer is already read (and possibly
+ modified a la m32r). */
+ ex_info.valid = (1 << buflen) - 1;
+ ex_info.dis_info = info;
+ ex_info.insn_bytes = buf;
+
+ /* The instructions are stored in hash lists.
+ Pick the first one and keep trying until we find the right one. */
+
+ insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value);
+ while (insn_list != NULL)
+ {
+ const CGEN_INSN *insn = insn_list->insn;
+ CGEN_FIELDS fields;
+ int length;
+ unsigned long insn_value_cropped;
+
+#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+ /* Not needed as insn shouldn't be in hash lists if not supported. */
+ /* Supported by this cpu? */
+ if (! arc_cgen_insn_supported (cd, insn))
+ {
+ insn_list = CGEN_DIS_NEXT_INSN (insn_list);
+ continue;
+ }
+#endif
+
+ /* Basic bit mask must be correct. */
+ /* ??? May wish to allow target to defer this check until the extract
+ handler. */
+
+ /* Base size may exceed this instruction's size. Extract the
+ relevant part from the buffer. */
+ if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
+ (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
+ insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
+ info->endian == BFD_ENDIAN_BIG);
+ else
+ insn_value_cropped = insn_value;
+
+ if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
+ == CGEN_INSN_BASE_VALUE (insn))
+ {
+ /* Printing is handled in two passes. The first pass parses the
+ machine insn and extracts the fields. The second pass prints
+ them. */
+
+ /* Make sure the entire insn is loaded into insn_value, if it
+ can fit. */
+ if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
+ (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
+ {
+ unsigned long full_insn_value;
+ int rc = read_insn (cd, pc, info, buf,
+ CGEN_INSN_BITSIZE (insn) / 8,
+ & ex_info, & full_insn_value);
+ if (rc != 0)
+ return rc;
+ length = CGEN_EXTRACT_FN (cd, insn)
+ (cd, insn, &ex_info, full_insn_value, &fields, pc);
+ }
+ else
+ length = CGEN_EXTRACT_FN (cd, insn)
+ (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
+
+ /* Length < 0 -> error. */
+ if (length < 0)
+ return length;
+ if (length > 0)
+ {
+ CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
+ /* Length is in bits, result is in bytes. */
+ return length / 8;
+ }
+ }
+
+ insn_list = CGEN_DIS_NEXT_INSN (insn_list);
+ }
+
+ return 0;
+}
+
+/* Default value for CGEN_PRINT_INSN.
+ The result is the size of the insn in bytes or zero for an unknown insn
+ or -1 if an error occured fetching bytes. */
+
+#ifndef CGEN_PRINT_INSN
+#define CGEN_PRINT_INSN default_print_insn
+#endif
+
+static int
+default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
+{
+ bfd_byte buf[CGEN_MAX_INSN_SIZE];
+ int buflen;
+ int status;
+
+ /* Attempt to read the base part of the insn. */
+ buflen = cd->base_insn_bitsize / 8;
+ status = (*info->read_memory_func) (pc, buf, buflen, info);
+
+ /* Try again with the minimum part, if min < base. */
+ if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
+ {
+ buflen = cd->min_insn_bitsize / 8;
+ status = (*info->read_memory_func) (pc, buf, buflen, info);
+ }
+
+ if (status != 0)
+ {
+ (*info->memory_error_func) (status, pc, info);
+ return -1;
+ }
+
+ return print_insn (cd, pc, info, buf, buflen);
+}
+
+/* Main entry point.
+ Print one instruction from PC on INFO->STREAM.
+ Return the size of the instruction (in bytes). */
+
+typedef struct cpu_desc_list
+{
+ struct cpu_desc_list *next;
+ CGEN_BITSET *isa;
+ int mach;
+ int endian;
+ CGEN_CPU_DESC cd;
+} cpu_desc_list;
+
+int
+print_insn_arc (bfd_vma pc, disassemble_info *info)
+{
+ static cpu_desc_list *cd_list = 0;
+ cpu_desc_list *cl = 0;
+ static CGEN_CPU_DESC cd = 0;
+ static CGEN_BITSET *prev_isa;
+ static int prev_mach;
+ static int prev_endian;
+ int length;
+ CGEN_BITSET *isa;
+ int mach;
+ int endian = (info->endian == BFD_ENDIAN_BIG
+ ? CGEN_ENDIAN_BIG
+ : CGEN_ENDIAN_LITTLE);
+ enum bfd_architecture arch;
+
+ /* ??? gdb will set mach but leave the architecture as "unknown" */
+#ifndef CGEN_BFD_ARCH
+#define CGEN_BFD_ARCH bfd_arch_arc
+#endif
+ arch = info->arch;
+ if (arch == bfd_arch_unknown)
+ arch = CGEN_BFD_ARCH;
+
+ /* There's no standard way to compute the machine or isa number
+ so we leave it to the target. */
+#ifdef CGEN_COMPUTE_MACH
+ mach = CGEN_COMPUTE_MACH (info);
+#else
+ mach = info->mach;
+#endif
+
+#ifdef CGEN_COMPUTE_ISA
+ {
+ static CGEN_BITSET *permanent_isa;
+
+ if (!permanent_isa)
+ permanent_isa = cgen_bitset_create (MAX_ISAS);
+ isa = permanent_isa;
+ cgen_bitset_clear (isa);
+ cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
+ }
+#else
+ isa = info->insn_sets;
+#endif
+
+ /* If we've switched cpu's, try to find a handle we've used before */
+ if (cd
+ && (cgen_bitset_compare (isa, prev_isa) != 0
+ || mach != prev_mach
+ || endian != prev_endian))
+ {
+ cd = 0;
+ for (cl = cd_list; cl; cl = cl->next)
+ {
+ if (cgen_bitset_compare (cl->isa, isa) == 0 &&
+ cl->mach == mach &&
+ cl->endian == endian)
+ {
+ cd = cl->cd;
+ prev_isa = cd->isas;
+ break;
+ }
+ }
+ }
+
+ /* If we haven't initialized yet, initialize the opcode table. */
+ if (! cd)
+ {
+ const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
+ const char *mach_name;
+
+ if (!arch_type)
+ abort ();
+ mach_name = arch_type->printable_name;
+
+ prev_isa = cgen_bitset_copy (isa);
+ prev_mach = mach;
+ prev_endian = endian;
+ cd = arc_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
+ CGEN_CPU_OPEN_BFDMACH, mach_name,
+ CGEN_CPU_OPEN_ENDIAN, prev_endian,
+ CGEN_CPU_OPEN_END);
+ if (!cd)
+ abort ();
+
+ /* Save this away for future reference. */
+ cl = xmalloc (sizeof (struct cpu_desc_list));
+ cl->cd = cd;
+ cl->isa = prev_isa;
+ cl->mach = mach;
+ cl->endian = endian;
+ cl->next = cd_list;
+ cd_list = cl;
+
+ arc_cgen_init_dis (cd);
+ }
+
+ /* We try to have as much common code as possible.
+ But at this point some targets need to take over. */
+ /* ??? Some targets may need a hook elsewhere. Try to avoid this,
+ but if not possible try to move this hook elsewhere rather than
+ have two hooks. */
+ length = CGEN_PRINT_INSN (cd, pc, info);
+ if (length > 0)
+ return length;
+ if (length < 0)
+ return -1;
+
+ (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
+ return cd->default_insn_bitsize / 8;
}
diff --git a/opcodes/arc-dis.h b/opcodes/arc-dis.h
index f0f33aa..c8aa9f3 100644
--- a/opcodes/arc-dis.h
+++ b/opcodes/arc-dis.h
@@ -22,62 +22,9 @@
#ifndef ARCDIS_H
#define ARCDIS_H
-enum
-{
- BR_exec_when_no_jump,
- BR_exec_always,
- BR_exec_when_jump
-};
+int ARCTangent_decodeInstr(bfd_vma address, disassemble_info* info);
+int ARCompact_decodeInstr (bfd_vma address, disassemble_info* info);
-enum Flow
-{
- noflow,
- direct_jump,
- direct_call,
- indirect_jump,
- indirect_call,
- invalid_instr
-};
-
-enum { no_reg = 99 };
-enum { allOperandsSize = 256 };
-
-struct arcDisState
-{
- void *_this;
- int instructionLen;
- void (*err)(void*, const char*);
- const char *(*coreRegName)(void*, int);
- const char *(*auxRegName)(void*, int);
- const char *(*condCodeName)(void*, int);
- const char *(*instName)(void*, int, int, int*);
-
- unsigned char* instruction;
- unsigned index;
- const char *comm[6]; /* instr name, cond, NOP, 3 operands */
- int opWidth;
- int targets[4];
- int addresses[4];
- /* Set as a side-effect of calling the disassembler.
- Used only by the debugger. */
- enum Flow flow;
- int register_for_indirect_jump;
- int ea_reg1, ea_reg2, _offset;
- int _cond, _opcode;
- unsigned long words[2];
- char *commentBuffer;
- char instrBuffer[40];
- char operandBuffer[allOperandsSize];
- char _ea_present;
- char _mem_load;
- char _load_len;
- char nullifyMode;
- unsigned char commNum;
- unsigned char isBranch;
- unsigned char tcnt;
- unsigned char acnt;
-};
-
-#define __TRANSLATION_REQUIRED(state) ((state).acnt != 0)
+#define __TRANSLATION_REQUIRED(state) ((state).acnt != 0)
#endif
diff --git a/opcodes/arc-ext.c b/opcodes/arc-ext.c
index 1e6c1f8..d2d838e 100644
--- a/opcodes/arc-ext.c
+++ b/opcodes/arc-ext.c
@@ -19,54 +19,144 @@
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
-#include "sysdep.h"
#include <stdlib.h>
#include <stdio.h>
#include "bfd.h"
#include "arc-ext.h"
-#include "libiberty.h"
+#include "elf/arc.h"
-/* Extension structure */
+#include "libiberty.h"
+#include "sysdep.h"
+
+/* extension structure */
static struct arcExtMap arc_extension_map;
/* Get the name of an extension instruction. */
const char *
-arcExtMap_instName(int opcode, int minor, int *flags)
+arcExtMap_instName (int opcode, int insn, int *flags)
{
- if (opcode == 3)
- {
- /* FIXME: ??? need to also check 0/1/2 in bit0 for (3f) brk/sleep/swi */
- if (minor < 0x09 || minor == 0x3f)
- return 0;
- else
- opcode = 0x1f - 0x10 + minor - 0x09 + 1;
- }
- else
- if (opcode < 0x10)
- return 0;
- else
- opcode -= 0x10;
- if (!arc_extension_map.instructions[opcode])
- return 0;
- *flags = arc_extension_map.instructions[opcode]->flags;
- return arc_extension_map.instructions[opcode]->name;
+ /* Here the following tasks need to be done. First of all, the opcode
+ stored in the Extension Map is the real opcode. However, the subopcode
+ stored in the instruction to be disassembled is mangled. We pass (in
+ minor opcode), the instruction word. Here we will un-mangle it and get
+ the real subopcode which we can look for in the Extension Map. This
+ function is used both for the ARCTangent and the ARCompact, so we would
+ also need some sort of a way to distinguish between the two
+ architectures. This is because the ARCTangent does not do any of this
+ mangling so we have no issues there. */
+
+ /* If P[22:23] is 0 or 2 then un-mangle using iiiiiI. If it is 1 then use
+ iiiiIi. Now, if P is 3 then check M[5:5] and if it is 0 then un-mangle
+ using iiiiiI else iiiiii. */
+
+ unsigned char minor;
+ struct ExtInstruction *temp;
+
+ if (*flags != E_ARC_MACH_A4) /* ARCompact extension instructions. */
+ {
+ /* 16-bit instructions. */
+ if (0x08 <= opcode && opcode <= 0x0b)
+ {
+ unsigned char I, b, c, i;
+
+ I = (insn & 0xf800) >> 11;
+ b = (insn & 0x0700) >> 8;
+ c = (insn & 0x00e0) >> 5;
+ i = (insn & 0x001f);
+
+ if (i)
+ minor = i;
+ else
+ minor = (c == 0x07) ? b : c;
+ }
+ /* 32-bit instructions. */
+ else
+ {
+ unsigned char P, M, I, A, B;
+
+ P = (insn & 0x00c00000) >> 22;
+ M = (insn & 0x00000020);
+ I = (insn & 0x003f0000) >> 16;
+ A = (insn & 0x0000003f);
+ B = ((insn & 0x07000000) >> 24) | ((insn & 0x00007000) >> 9);
+
+ if (I != 0x2f)
+ {
+#ifndef UNMANGLED
+ switch (P)
+ {
+ case 3:
+ if (M)
+ {
+ minor = I;
+ break;
+ }
+ case 0:
+ case 2:
+ minor = (I >> 1) | ((I & 0x1) << 5);
+ break;
+ case 1:
+ minor = (I >> 1) | (I & 0x1) | ((I & 0x2) << 4);
+ }
+#else
+ minor = I;
+#endif
+ }
+ else
+ {
+ if (A != 0x3f)
+ minor = A;
+ else
+ minor = B;
+ }
+ }
+ }
+ else /* ARCTangent extension instructions. */
+ minor = insn;
+
+ temp = arc_extension_map.instructions[INST_HASH (opcode, minor)];
+ while (temp)
+ {
+ if ((temp->major == opcode) && (temp->minor == minor))
+ {
+ *flags = temp->flags;
+ return temp->name;
+ }
+ temp = temp->next;
+ }
+
+ return NULL;
}
-/* Get the name of an extension core register. */
-
+/* get the name of an extension core register */
const char *
-arcExtMap_coreRegName(int value)
+arcExtMap_coreRegName (int value)
{
if (value < 32)
return 0;
- return arc_extension_map.coreRegisters[value-32];
+ return arc_extension_map.coreRegisters[value-32].name;
}
-/* Get the name of an extension condition code. */
+enum ExtReadWrite
+arcExtMap_coreReadWrite (int value)
+{
+ if (value < 32)
+ return REG_INVALID;
+ return arc_extension_map.coreRegisters[value-32].rw;
+}
+#if 0
+struct ExtAuxRegister *
+arc_ExtMap_auxRegs ()
+{
+ return arc_extension_map.auxRegisters;
+}
+#endif
+
+/* Get the name of an extension condition code. */
const char *
-arcExtMap_condCodeName(int value)
+arcExtMap_condCodeName (int value)
{
if (value < 16)
return 0;
@@ -76,84 +166,85 @@
/* Get the name of an extension aux register. */
const char *
-arcExtMap_auxRegName(long address)
+arcExtMap_auxRegName (long address)
{
- /* walk the list of aux reg names and find the name */
+ /* Walk the list of aux reg names and find the name. */
struct ExtAuxRegister *r;
- for (r = arc_extension_map.auxRegisters; r; r = r->next) {
- if (r->address == address)
- return (const char *) r->name;
- }
+ for (r = arc_extension_map.auxRegisters; r; r = r->next)
+ {
+ if (r->address == address)
+ return (const char *)r->name;
+ }
return 0;
}
+#if 0
/* Recursively free auxilliary register strcture pointers until
the list is empty. */
-
static void
-clean_aux_registers(struct ExtAuxRegister *r)
+clean_aux_registers (struct ExtAuxRegister *r)
{
if (r -> next)
{
- clean_aux_registers( r->next);
- free(r -> name);
- free(r -> next);
- r ->next = NULL;
+ clean_aux_registers (r->next);
+ free (r->name);
+ free (r->next);
+ r->next = NULL;
}
else
- free(r -> name);
+ free (r->name);
}
-/* Free memory that has been allocated for the extensions. */
+/* Free memory that has been allocated for the extensions. */
static void
-cleanup_ext_map(void)
+cleanup_ext_map (void)
{
struct ExtAuxRegister *r;
struct ExtInstruction *insn;
int i;
- /* clean aux reg structure */
+ /* Clean aux reg structure. */
r = arc_extension_map.auxRegisters;
if (r)
{
- (clean_aux_registers(r));
- free(r);
+ (clean_aux_registers (r));
+ free (r);
}
- /* clean instructions */
- for (i = 0; i < NUM_EXT_INST; i++)
+ /* Clean instructions. */
+ for (i = INST_HASH_SIZE - 1; i >= 0; i--)
{
- insn = arc_extension_map.instructions[i];
- if (insn)
- free(insn->name);
+ for (insn = arc_extension_map.instructions[i]; insn ; insn = insn->next)
+ {
+ free (insn->name);
+ free (insn);
+ }
}
- /* clean core reg struct */
+ /* Clean core reg struct. */
for (i = 0; i < NUM_EXT_CORE; i++)
{
- if (arc_extension_map.coreRegisters[i])
- free(arc_extension_map.coreRegisters[i]);
+ if (arc_extension_map.coreRegisters[i].name)
+ free (arc_extension_map.coreRegisters[i].name);
}
for (i = 0; i < NUM_EXT_COND; i++) {
if (arc_extension_map.condCodes[i])
- free(arc_extension_map.condCodes[i]);
+ free (arc_extension_map.condCodes[i]);
}
- memset(&arc_extension_map, 0, sizeof(struct arcExtMap));
+ memset (&arc_extension_map, 0, sizeof (struct arcExtMap));
}
+#endif
int
-arcExtMap_add(void *base, unsigned long length)
+arcExtMap_add (void *base, unsigned long length)
{
unsigned char *block = base;
unsigned char *p = block;
- /* Clean up and reset everything if needed. */
- cleanup_ext_map();
-
while (p && p < (block + length))
{
/* p[0] == length of record
@@ -169,94 +260,96 @@
For aux regs:
p[2..5] = value
p[6]+ = name
- (value is p[2]<<24|p[3]<<16|p[4]<<8|p[5]) */
-
+ (value is p[2]<<24|p[3]<<16|p[4]<<8|p[5]) */
if (p[0] == 0)
return -1;
switch (p[1])
- {
+ { /* type */
case EXT_INSTRUCTION:
{
- char opcode = p[2];
- char minor = p[3];
- char * insn_name = (char *) xmalloc(( (int)*p-5) * sizeof(char));
- struct ExtInstruction * insn =
- (struct ExtInstruction *) xmalloc(sizeof(struct ExtInstruction));
+ char *insn_name = xstrdup ((char *) (p+5));
+ struct ExtInstruction *insn = XNEW (struct ExtInstruction);
+ int major = p[2];
+ int minor = p[3];
+ struct ExtInstruction **bucket
+ = &arc_extension_map.instructions[INST_HASH (major, minor)];
- if (opcode==3)
- opcode = 0x1f - 0x10 + minor - 0x09 + 1;
- else
- opcode -= 0x10;
- insn -> flags = (char) *(p+4);
- strcpy (insn_name, (char *) (p+5));
- insn -> name = insn_name;
- arc_extension_map.instructions[(int) opcode] = insn;
+ insn->name = insn_name;
+ insn->major = major;
+ insn->minor = minor;
+ insn->flags = p[4];
+ insn->next = *bucket;
+ *bucket = insn;
+ break;
}
- break;
-
case EXT_CORE_REGISTER:
{
- char * core_name = (char *) xmalloc(((int)*p-3) * sizeof(char));
+ unsigned char number = p[2];
+ char *name = (char *) p+3;
- strcpy(core_name, (char *) (p+3));
- arc_extension_map.coreRegisters[p[2]-32] = core_name;
+ arc_extension_map.coreRegisters[number-32].number = number;
+ arc_extension_map.coreRegisters[number-32].rw = REG_READWRITE;
+ arc_extension_map.coreRegisters[number-32].name = xstrdup (name);
+ break;
}
- break;
+ case EXT_LONG_CORE_REGISTER:
+ {
+ unsigned char number = p[2];
+ char *name = (char *) p+7;
+ enum ExtReadWrite rw = p[6];
+ arc_extension_map.coreRegisters[number-32].number = number;
+ arc_extension_map.coreRegisters[number-32].rw = rw;
+ arc_extension_map.coreRegisters[number-32].name = xstrdup (name);
+ }
case EXT_COND_CODE:
{
- char * cc_name = (char *) xmalloc( ((int)*p-3) * sizeof(char));
- strcpy(cc_name, (char *) (p+3));
- arc_extension_map.condCodes[p[2]-16] = cc_name;
- }
- break;
+ char *cc_name = xstrdup ((char *) (p+3));
+ arc_extension_map.condCodes[p[2]-16] = cc_name;
+ break;
+ }
case EXT_AUX_REGISTER:
{
- /* trickier -- need to store linked list to these */
- struct ExtAuxRegister *newAuxRegister =
- (struct ExtAuxRegister *)malloc(sizeof(struct ExtAuxRegister));
- char * aux_name = (char *) xmalloc ( ((int)*p-6) * sizeof(char));
+ /* trickier -- need to store linked list to these */
+ struct ExtAuxRegister *newAuxRegister
+ = XNEW (struct ExtAuxRegister);
+ char *aux_name = xstrdup ((char *) (p+6));
- strcpy (aux_name, (char *) (p+6));
newAuxRegister->name = aux_name;
newAuxRegister->address = p[2]<<24 | p[3]<<16 | p[4]<<8 | p[5];
newAuxRegister->next = arc_extension_map.auxRegisters;
arc_extension_map.auxRegisters = newAuxRegister;
+ break;
}
- break;
-
default:
return -1;
-
}
- p += p[0]; /* move to next record */
+ p += p[0]; /* move to next record */
}
-
return 0;
}
-/* Load hw extension descibed in .extArcMap ELF section. */
-
+/* Load extensions described in .arcextmap and .gnu.linkonce.arcextmap.* ELF
+ section. */
void
-build_ARC_extmap (text_bfd)
- bfd *text_bfd;
+build_ARC_extmap (bfd *text_bfd)
{
char *arcExtMap;
bfd_size_type count;
asection *p;
for (p = text_bfd->sections; p != NULL; p = p->next)
- if (!strcmp (p->name, ".arcextmap"))
+ if (!strncmp (p->name,
+ ".gnu.linkonce.arcextmap.",
+ sizeof (".gnu.linkonce.arcextmap.")-1)
+ || !strcmp (p->name,".arcextmap"))
{
count = bfd_get_section_size (p);
arcExtMap = (char *) xmalloc (count);
if (bfd_get_section_contents (text_bfd, p, (PTR) arcExtMap, 0, count))
- {
- arcExtMap_add ((PTR) arcExtMap, count);
- break;
- }
+ arcExtMap_add ((PTR) arcExtMap, count);
free ((PTR) arcExtMap);
}
}
diff --git a/opcodes/arc-ext.h b/opcodes/arc-ext.h
index 8a0deab..1143490 100644
--- a/opcodes/arc-ext.h
+++ b/opcodes/arc-ext.h
@@ -21,43 +21,81 @@
#ifndef ARCEXT_H
#define ARCEXT_H
-enum {EXT_INSTRUCTION = 0,
- EXT_CORE_REGISTER = 1,
- EXT_AUX_REGISTER = 2,
- EXT_COND_CODE = 3};
-enum {NUM_EXT_INST = (0x1f-0x10+1) + (0x3f-0x09+1)};
+enum { INST_HASH_BITS = 6 };
enum {NUM_EXT_CORE = 59-32+1};
enum {NUM_EXT_COND = 0x1f-0x10+1};
-struct ExtInstruction
+enum { INST_HASH_SIZE = 1 << INST_HASH_BITS };
+#define INST_HASH(MAJOR,MINOR) \
+ ((((MAJOR) << 3) ^ (MINOR)) & ((INST_HASH_SIZE) - 1))
+
+enum ExtOperType
+ {
+ EXT_INSTRUCTION,
+ EXT_CORE_REGISTER,
+ EXT_AUX_REGISTER,
+ EXT_COND_CODE,
+ EXT_AC_INSTRUCTION,
+ EXT_LONG_CORE_REGISTER = 0x06
+ };
+
+/* Define this if we do not want to encode instructions based on the
+ ARCompact Programmer's Reference. */
+#define UNMANGLED
+
+struct ExtInstruction
{
+ char major;
+ char minor;
char flags;
char *name;
-};
+ struct ExtInstruction *next;
+};
-struct ExtAuxRegister
+struct ExtAuxRegister
{
long address;
char *name;
- struct ExtAuxRegister *next;
+ struct ExtAuxRegister *next;
};
-struct arcExtMap
+enum ExtReadWrite
+ {
+ REG_INVALID,
+ REG_READ,
+ REG_WRITE,
+ REG_READWRITE
+ };
+
+struct ExtCoreRegister
+{
+ short number;
+ enum ExtReadWrite rw;
+ char *name;
+};
+
+struct arcExtMap
{
struct ExtAuxRegister *auxRegisters;
- struct ExtInstruction *instructions[NUM_EXT_INST];
- char *coreRegisters[NUM_EXT_CORE];
+ struct ExtInstruction *instructions[INST_HASH_SIZE];
+ struct ExtCoreRegister coreRegisters[NUM_EXT_CORE];
char *condCodes[NUM_EXT_COND];
};
extern int arcExtMap_add(void*, unsigned long);
+extern enum ExtReadWrite arcExtMap_coreReadWrite (int);
extern const char *arcExtMap_coreRegName(int);
extern const char *arcExtMap_auxRegName(long);
extern const char *arcExtMap_condCodeName(int);
extern const char *arcExtMap_instName(int, int, int*);
-extern void build_ARC_extmap(bfd *);
+
+/* Ravi:
+ warning: implicit declaration of function `build_ARC_extmap'
+*/
+extern void build_ARC_extmap (bfd *);
+
#define IGNORE_FIRST_OPD 1
-#endif
+#endif /* __arcExtMap_h__ */
diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index 2a5ae71..d64ebbe 100644
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -1,11 +1,12 @@
-/* Opcode table for the ARC.
- Copyright 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2004, 2005, 2007
- Free Software Foundation, Inc.
- Contributed by Doug Evans (dje@cygnus.com).
+/* Instruction opcode table for arc.
- This file is part of libopcodes.
+THIS FILE IS MACHINE GENERATED WITH CGEN.
- This library is free software; you can redistribute it and/or modify
+Copyright 1996-2007 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+ This file is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
@@ -15,1749 +16,3388 @@
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software Foundation,
- Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
#include "sysdep.h"
-#include <stdio.h>
#include "ansidecl.h"
#include "bfd.h"
-#include "opcode/arc.h"
-#include "opintl.h"
+#include "symcat.h"
+#include "arc-desc.h"
+#include "arc-opc.h"
+#include "libiberty.h"
-enum operand {OP_NONE,OP_REG,OP_SHIMM,OP_LIMM};
-
-#define OPERANDS 3
-
-enum operand ls_operand[OPERANDS];
-
-struct arc_opcode *arc_ext_opcodes;
-struct arc_ext_operand_value *arc_ext_operands;
-
-#define LS_VALUE 0
-#define LS_DEST 0
-#define LS_BASE 1
-#define LS_OFFSET 2
-
-/* Given a format letter, yields the index into `arc_operands'.
- eg: arc_operand_map['a'] = REGA. */
-unsigned char arc_operand_map[256];
-
-/* Nonzero if we've seen an 'f' suffix (in certain insns). */
-static int flag_p;
-
-/* Nonzero if we've finished processing the 'f' suffix. */
-static int flagshimm_handled_p;
-
-/* Nonzero if we've seen a 'a' suffix (address writeback). */
-static int addrwb_p;
-
-/* Nonzero if we've seen a 'q' suffix (condition code). */
-static int cond_p;
-
-/* Nonzero if we've inserted a nullify condition. */
-static int nullify_p;
-
-/* The value of the a nullify condition we inserted. */
-static int nullify;
-
-/* Nonzero if we've inserted jumpflags. */
-static int jumpflags_p;
-
-/* Nonzero if we've inserted a shimm. */
-static int shimm_p;
-
-/* The value of the shimm we inserted (each insn only gets one but it can
- appear multiple times). */
-static int shimm;
-
-/* Nonzero if we've inserted a limm (during assembly) or seen a limm
- (during disassembly). */
-static int limm_p;
-
-/* The value of the limm we inserted. Each insn only gets one but it can
- appear multiple times. */
-static long limm;
-
-#define INSERT_FN(fn) \
-static arc_insn fn (arc_insn, const struct arc_operand *, \
- int, const struct arc_operand_value *, long, \
- const char **)
-
-#define EXTRACT_FN(fn) \
-static long fn (arc_insn *, const struct arc_operand *, \
- int, const struct arc_operand_value **, int *)
-
-INSERT_FN (insert_reg);
-INSERT_FN (insert_shimmfinish);
-INSERT_FN (insert_limmfinish);
-INSERT_FN (insert_offset);
-INSERT_FN (insert_base);
-INSERT_FN (insert_st_syntax);
-INSERT_FN (insert_ld_syntax);
-INSERT_FN (insert_addr_wb);
-INSERT_FN (insert_flag);
-INSERT_FN (insert_nullify);
-INSERT_FN (insert_flagfinish);
-INSERT_FN (insert_cond);
-INSERT_FN (insert_forcelimm);
-INSERT_FN (insert_reladdr);
-INSERT_FN (insert_absaddr);
-INSERT_FN (insert_jumpflags);
-INSERT_FN (insert_unopmacro);
-
-EXTRACT_FN (extract_reg);
-EXTRACT_FN (extract_ld_offset);
-EXTRACT_FN (extract_ld_syntax);
-EXTRACT_FN (extract_st_offset);
-EXTRACT_FN (extract_st_syntax);
-EXTRACT_FN (extract_flag);
-EXTRACT_FN (extract_cond);
-EXTRACT_FN (extract_reladdr);
-EXTRACT_FN (extract_jumpflags);
-EXTRACT_FN (extract_unopmacro);
-
-/* Various types of ARC operands, including insn suffixes. */
-
-/* Insn format values:
-
- 'a' REGA register A field
- 'b' REGB register B field
- 'c' REGC register C field
- 'S' SHIMMFINISH finish inserting a shimm value
- 'L' LIMMFINISH finish inserting a limm value
- 'o' OFFSET offset in st insns
- 'O' OFFSET offset in ld insns
- '0' SYNTAX_ST_NE enforce store insn syntax, no errors
- '1' SYNTAX_LD_NE enforce load insn syntax, no errors
- '2' SYNTAX_ST enforce store insn syntax, errors, last pattern only
- '3' SYNTAX_LD enforce load insn syntax, errors, last pattern only
- 's' BASE base in st insn
- 'f' FLAG F flag
- 'F' FLAGFINISH finish inserting the F flag
- 'G' FLAGINSN insert F flag in "flag" insn
- 'n' DELAY N field (nullify field)
- 'q' COND condition code field
- 'Q' FORCELIMM set `cond_p' to 1 to ensure a constant is a limm
- 'B' BRANCH branch address (22 bit pc relative)
- 'J' JUMP jump address (26 bit absolute)
- 'j' JUMPFLAGS optional high order bits of 'J'
- 'z' SIZE1 size field in ld a,[b,c]
- 'Z' SIZE10 size field in ld a,[b,shimm]
- 'y' SIZE22 size field in st c,[b,shimm]
- 'x' SIGN0 sign extend field ld a,[b,c]
- 'X' SIGN9 sign extend field ld a,[b,shimm]
- 'w' ADDRESS3 write-back field in ld a,[b,c]
- 'W' ADDRESS12 write-back field in ld a,[b,shimm]
- 'v' ADDRESS24 write-back field in st c,[b,shimm]
- 'e' CACHEBYPASS5 cache bypass in ld a,[b,c]
- 'E' CACHEBYPASS14 cache bypass in ld a,[b,shimm]
- 'D' CACHEBYPASS26 cache bypass in st c,[b,shimm]
- 'U' UNOPMACRO fake operand to copy REGB to REGC for unop macros
-
- The following modifiers may appear between the % and char (eg: %.f):
-
- '.' MODDOT '.' prefix must be present
- 'r' REG generic register value, for register table
- 'A' AUXREG auxiliary register in lr a,[b], sr c,[b]
-
- Fields are:
-
- CHAR BITS SHIFT FLAGS INSERT_FN EXTRACT_FN */
-
-const struct arc_operand arc_operands[] =
+/* -- opc.c */
+unsigned int
+arc_cgen_dis_hash (const char * buf, int big_p)
{
-/* Place holder (??? not sure if needed). */
-#define UNUSED 0
- { 0, 0, 0, 0, 0, 0 },
+ const unsigned char *ubuf = (unsigned const char *) buf;
+ int b0 = ubuf[0], b1 = ubuf[1], w;
-/* Register A or shimm/limm indicator. */
-#define REGA (UNUSED + 1)
- { 'a', 6, ARC_SHIFT_REGA, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg },
-
-/* Register B or shimm/limm indicator. */
-#define REGB (REGA + 1)
- { 'b', 6, ARC_SHIFT_REGB, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg },
-
-/* Register C or shimm/limm indicator. */
-#define REGC (REGB + 1)
- { 'c', 6, ARC_SHIFT_REGC, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg },
-
-/* Fake operand used to insert shimm value into most instructions. */
-#define SHIMMFINISH (REGC + 1)
- { 'S', 9, 0, ARC_OPERAND_SIGNED + ARC_OPERAND_FAKE, insert_shimmfinish, 0 },
-
-/* Fake operand used to insert limm value into most instructions. */
-#define LIMMFINISH (SHIMMFINISH + 1)
- { 'L', 32, 32, ARC_OPERAND_ADDRESS + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE, insert_limmfinish, 0 },
-
-/* Shimm operand when there is no reg indicator (st). */
-#define ST_OFFSET (LIMMFINISH + 1)
- { 'o', 9, 0, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | ARC_OPERAND_STORE, insert_offset, extract_st_offset },
-
-/* Shimm operand when there is no reg indicator (ld). */
-#define LD_OFFSET (ST_OFFSET + 1)
- { 'O', 9, 0,ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | ARC_OPERAND_LOAD, insert_offset, extract_ld_offset },
-
-/* Operand for base. */
-#define BASE (LD_OFFSET + 1)
- { 's', 6, ARC_SHIFT_REGB, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED, insert_base, extract_reg},
-
-/* 0 enforce syntax for st insns. */
-#define SYNTAX_ST_NE (BASE + 1)
- { '0', 9, 0, ARC_OPERAND_FAKE, insert_st_syntax, extract_st_syntax },
-
-/* 1 enforce syntax for ld insns. */
-#define SYNTAX_LD_NE (SYNTAX_ST_NE + 1)
- { '1', 9, 0, ARC_OPERAND_FAKE, insert_ld_syntax, extract_ld_syntax },
-
-/* 0 enforce syntax for st insns. */
-#define SYNTAX_ST (SYNTAX_LD_NE + 1)
- { '2', 9, 0, ARC_OPERAND_FAKE | ARC_OPERAND_ERROR, insert_st_syntax, extract_st_syntax },
-
-/* 0 enforce syntax for ld insns. */
-#define SYNTAX_LD (SYNTAX_ST + 1)
- { '3', 9, 0, ARC_OPERAND_FAKE | ARC_OPERAND_ERROR, insert_ld_syntax, extract_ld_syntax },
-
-/* Flag update bit (insertion is defered until we know how). */
-#define FLAG (SYNTAX_LD + 1)
- { 'f', 1, 8, ARC_OPERAND_SUFFIX, insert_flag, extract_flag },
-
-/* Fake utility operand to finish 'f' suffix handling. */
-#define FLAGFINISH (FLAG + 1)
- { 'F', 1, 8, ARC_OPERAND_FAKE, insert_flagfinish, 0 },
-
-/* Fake utility operand to set the 'f' flag for the "flag" insn. */
-#define FLAGINSN (FLAGFINISH + 1)
- { 'G', 1, 8, ARC_OPERAND_FAKE, insert_flag, 0 },
-
-/* Branch delay types. */
-#define DELAY (FLAGINSN + 1)
- { 'n', 2, 5, ARC_OPERAND_SUFFIX , insert_nullify, 0 },
-
-/* Conditions. */
-#define COND (DELAY + 1)
- { 'q', 5, 0, ARC_OPERAND_SUFFIX, insert_cond, extract_cond },
-
-/* Set `cond_p' to 1 to ensure a constant is treated as a limm. */
-#define FORCELIMM (COND + 1)
- { 'Q', 0, 0, ARC_OPERAND_FAKE, insert_forcelimm, 0 },
-
-/* Branch address; b, bl, and lp insns. */
-#define BRANCH (FORCELIMM + 1)
- { 'B', 20, 7, (ARC_OPERAND_RELATIVE_BRANCH + ARC_OPERAND_SIGNED) | ARC_OPERAND_ERROR, insert_reladdr, extract_reladdr },
-
-/* Jump address; j insn (this is basically the same as 'L' except that the
- value is right shifted by 2). */
-#define JUMP (BRANCH + 1)
- { 'J', 24, 32, ARC_OPERAND_ERROR | (ARC_OPERAND_ABSOLUTE_BRANCH + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE), insert_absaddr, 0 },
-
-/* Jump flags; j{,l} insn value or'ed into 'J' addr for flag values. */
-#define JUMPFLAGS (JUMP + 1)
- { 'j', 6, 26, ARC_OPERAND_JUMPFLAGS | ARC_OPERAND_ERROR, insert_jumpflags, extract_jumpflags },
-
-/* Size field, stored in bit 1,2. */
-#define SIZE1 (JUMPFLAGS + 1)
- { 'z', 2, 1, ARC_OPERAND_SUFFIX, 0, 0 },
-
-/* Size field, stored in bit 10,11. */
-#define SIZE10 (SIZE1 + 1)
- { 'Z', 2, 10, ARC_OPERAND_SUFFIX, 0, 0 },
-
-/* Size field, stored in bit 22,23. */
-#define SIZE22 (SIZE10 + 1)
- { 'y', 2, 22, ARC_OPERAND_SUFFIX, 0, 0 },
-
-/* Sign extend field, stored in bit 0. */
-#define SIGN0 (SIZE22 + 1)
- { 'x', 1, 0, ARC_OPERAND_SUFFIX, 0, 0 },
-
-/* Sign extend field, stored in bit 9. */
-#define SIGN9 (SIGN0 + 1)
- { 'X', 1, 9, ARC_OPERAND_SUFFIX, 0, 0 },
-
-/* Address write back, stored in bit 3. */
-#define ADDRESS3 (SIGN9 + 1)
- { 'w', 1, 3, ARC_OPERAND_SUFFIX, insert_addr_wb, 0},
-
-/* Address write back, stored in bit 12. */
-#define ADDRESS12 (ADDRESS3 + 1)
- { 'W', 1, 12, ARC_OPERAND_SUFFIX, insert_addr_wb, 0},
-
-/* Address write back, stored in bit 24. */
-#define ADDRESS24 (ADDRESS12 + 1)
- { 'v', 1, 24, ARC_OPERAND_SUFFIX, insert_addr_wb, 0},
-
-/* Cache bypass, stored in bit 5. */
-#define CACHEBYPASS5 (ADDRESS24 + 1)
- { 'e', 1, 5, ARC_OPERAND_SUFFIX, 0, 0 },
-
-/* Cache bypass, stored in bit 14. */
-#define CACHEBYPASS14 (CACHEBYPASS5 + 1)
- { 'E', 1, 14, ARC_OPERAND_SUFFIX, 0, 0 },
-
-/* Cache bypass, stored in bit 26. */
-#define CACHEBYPASS26 (CACHEBYPASS14 + 1)
- { 'D', 1, 26, ARC_OPERAND_SUFFIX, 0, 0 },
-
-/* Unop macro, used to copy REGB to REGC. */
-#define UNOPMACRO (CACHEBYPASS26 + 1)
- { 'U', 6, ARC_SHIFT_REGC, ARC_OPERAND_FAKE, insert_unopmacro, extract_unopmacro },
-
-/* '.' modifier ('.' required). */
-#define MODDOT (UNOPMACRO + 1)
- { '.', 1, 0, ARC_MOD_DOT, 0, 0 },
-
-/* Dummy 'r' modifier for the register table.
- It's called a "dummy" because there's no point in inserting an 'r' into all
- the %a/%b/%c occurrences in the insn table. */
-#define REG (MODDOT + 1)
- { 'r', 6, 0, ARC_MOD_REG, 0, 0 },
-
-/* Known auxiliary register modifier (stored in shimm field). */
-#define AUXREG (REG + 1)
- { 'A', 9, 0, ARC_MOD_AUXREG, 0, 0 },
-
-/* End of list place holder. */
- { 0, 0, 0, 0, 0, 0 }
-};
-
-/* Insert a value into a register field.
- If REG is NULL, then this is actually a constant.
-
- We must also handle auxiliary registers for lr/sr insns. */
-
-static arc_insn
-insert_reg (arc_insn insn,
- const struct arc_operand *operand,
- int mods,
- const struct arc_operand_value *reg,
- long value,
- const char **errmsg)
-{
- static char buf[100];
- enum operand op_type = OP_NONE;
-
- if (reg == NULL)
- {
- /* We have a constant that also requires a value stored in a register
- field. Handle these by updating the register field and saving the
- value for later handling by either %S (shimm) or %L (limm). */
-
- /* Try to use a shimm value before a limm one. */
- if (ARC_SHIMM_CONST_P (value)
- /* If we've seen a conditional suffix we have to use a limm. */
- && !cond_p
- /* If we already have a shimm value that is different than ours
- we have to use a limm. */
- && (!shimm_p || shimm == value))
- {
- int marker;
-
- op_type = OP_SHIMM;
- /* Forget about shimm as dest mlm. */
-
- if ('a' != operand->fmt)
- {
- shimm_p = 1;
- shimm = value;
- flagshimm_handled_p = 1;
- marker = flag_p ? ARC_REG_SHIMM_UPDATE : ARC_REG_SHIMM;
- }
- else
- {
- /* Don't request flag setting on shimm as dest. */
- marker = ARC_REG_SHIMM;
- }
- insn |= marker << operand->shift;
- /* insn |= value & 511; - done later. */
- }
- /* We have to use a limm. If we've already seen one they must match. */
- else if (!limm_p || limm == value)
- {
- op_type = OP_LIMM;
- limm_p = 1;
- limm = value;
- insn |= ARC_REG_LIMM << operand->shift;
- /* The constant is stored later. */
- }
- else
- *errmsg = _("unable to fit different valued constants into instruction");
- }
+ if (big_p)
+ w = (b0 << 8) + b1;
else
+ w = (b1 << 8) + b0;
+
+ switch (w >> 11)
{
- /* We have to handle both normal and auxiliary registers. */
-
- if (reg->type == AUXREG)
- {
- if (!(mods & ARC_MOD_AUXREG))
- *errmsg = _("auxiliary register not allowed here");
- else
- {
- if ((insn & I(-1)) == I(2)) /* Check for use validity. */
- {
- if (reg->flags & ARC_REGISTER_READONLY)
- *errmsg = _("attempt to set readonly register");
- }
- else
- {
- if (reg->flags & ARC_REGISTER_WRITEONLY)
- *errmsg = _("attempt to read writeonly register");
- }
- insn |= ARC_REG_SHIMM << operand->shift;
- insn |= reg->value << arc_operands[reg->type].shift;
- }
- }
- else
- {
- /* check for use validity. */
- if ('a' == operand->fmt || ((insn & I(-1)) < I(2)))
- {
- if (reg->flags & ARC_REGISTER_READONLY)
- *errmsg = _("attempt to set readonly register");
- }
- if ('a' != operand->fmt)
- {
- if (reg->flags & ARC_REGISTER_WRITEONLY)
- *errmsg = _("attempt to read writeonly register");
- }
- /* We should never get an invalid register number here. */
- if ((unsigned int) reg->value > 60)
- {
- sprintf (buf, _("invalid register number `%d'"), reg->value);
- *errmsg = buf;
- }
- insn |= reg->value << operand->shift;
- op_type = OP_REG;
- }
+ case 0x01: /* branches */
+ return ((w >> 6) | w);
+ case 0x04: /* general operations */
+ case 0x05: case 0x06: case 0x07: /* 32 bit extension instructions */
+ return ((w >> 3) & 768) | (w & 255);
+ case 0x0c: /* .s load/add register-register */
+ case 0x0d: /* .s add/sub/shift register-immediate */
+ case 0x0e: /* .s mov/cmp/add with high register */
+ return ((w >> 6) & 992) | (w & 24);
+ case 0x0f: /* 16 bit general operations */
+ return ((w >> 6) & 992) | (w & 31);
+ case 0x17: /* .s shift/subtract/bit immediate */
+ case 0x18: /* .s stack-pointer based */
+ return ((w >> 6) & 992) | ((w >> 5) & 7);
+ case 0x19: /* load/add GP-relative */
+ case 0x1e: /* branch conditionally */
+ return ((w >> 6) & (992 | 24));
+ case 0x1c: /* add/cmp immediate */
+ case 0x1d: /* branch on compare register with zero */
+ return ((w >> 6) & (992 | 2));
+ default:
+ return ((w >> 6) & 992);
}
-
- switch (operand->fmt)
- {
- case 'a':
- ls_operand[LS_DEST] = op_type;
- break;
- case 's':
- ls_operand[LS_BASE] = op_type;
- break;
- case 'c':
- if ((insn & I(-1)) == I(2))
- ls_operand[LS_VALUE] = op_type;
- else
- ls_operand[LS_OFFSET] = op_type;
- break;
- case 'o': case 'O':
- ls_operand[LS_OFFSET] = op_type;
- break;
- }
-
- return insn;
}
-/* Called when we see an 'f' flag. */
+/* -- */
+/* The hash functions are recorded here to help keep assembler code out of
+ the disassembler and vice versa. */
-static arc_insn
-insert_flag (arc_insn insn,
- const struct arc_operand *operand ATTRIBUTE_UNUSED,
- int mods ATTRIBUTE_UNUSED,
- const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
- long value ATTRIBUTE_UNUSED,
- const char **errmsg ATTRIBUTE_UNUSED)
-{
- /* We can't store anything in the insn until we've parsed the registers.
- Just record the fact that we've got this flag. `insert_reg' will use it
- to store the correct value (ARC_REG_SHIMM_UPDATE or bit 0x100). */
- flag_p = 1;
- return insn;
-}
+static int asm_hash_insn_p (const CGEN_INSN *);
+static unsigned int asm_hash_insn (const char *);
+static int dis_hash_insn_p (const CGEN_INSN *);
+static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT, int);
-/* Called when we see an nullify condition. */
+/* Instruction formats. */
-static arc_insn
-insert_nullify (arc_insn insn,
- const struct arc_operand *operand,
- int mods ATTRIBUTE_UNUSED,
- const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
- long value,
- const char **errmsg ATTRIBUTE_UNUSED)
-{
- nullify_p = 1;
- insn |= (value & ((1 << operand->bits) - 1)) << operand->shift;
- nullify = value;
- return insn;
-}
-
-/* Called after completely building an insn to ensure the 'f' flag gets set
- properly. This is needed because we don't know how to set this flag until
- we've parsed the registers. */
-
-static arc_insn
-insert_flagfinish (arc_insn insn,
- const struct arc_operand *operand,
- int mods ATTRIBUTE_UNUSED,
- const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
- long value ATTRIBUTE_UNUSED,
- const char **errmsg ATTRIBUTE_UNUSED)
-{
- if (flag_p && !flagshimm_handled_p)
- {
- if (shimm_p)
- abort ();
- flagshimm_handled_p = 1;
- insn |= (1 << operand->shift);
- }
- return insn;
-}
-
-/* Called when we see a conditional flag (eg: .eq). */
-
-static arc_insn
-insert_cond (arc_insn insn,
- const struct arc_operand *operand,
- int mods ATTRIBUTE_UNUSED,
- const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
- long value,
- const char **errmsg ATTRIBUTE_UNUSED)
-{
- cond_p = 1;
- insn |= (value & ((1 << operand->bits) - 1)) << operand->shift;
- return insn;
-}
-
-/* Used in the "j" instruction to prevent constants from being interpreted as
- shimm values (which the jump insn doesn't accept). This can also be used
- to force the use of limm values in other situations (eg: ld r0,[foo] uses
- this).
- ??? The mechanism is sound. Access to it is a bit klunky right now. */
-
-static arc_insn
-insert_forcelimm (arc_insn insn,
- const struct arc_operand *operand ATTRIBUTE_UNUSED,
- int mods ATTRIBUTE_UNUSED,
- const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
- long value ATTRIBUTE_UNUSED,
- const char **errmsg ATTRIBUTE_UNUSED)
-{
- cond_p = 1;
- return insn;
-}
-
-static arc_insn
-insert_addr_wb (arc_insn insn,
- const struct arc_operand *operand,
- int mods ATTRIBUTE_UNUSED,
- const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
- long value ATTRIBUTE_UNUSED,
- const char **errmsg ATTRIBUTE_UNUSED)
-{
- addrwb_p = 1 << operand->shift;
- return insn;
-}
-
-static arc_insn
-insert_base (arc_insn insn,
- const struct arc_operand *operand,
- int mods,
- const struct arc_operand_value *reg,
- long value,
- const char **errmsg)
-{
- if (reg != NULL)
- {
- arc_insn myinsn;
- myinsn = insert_reg (0, operand,mods, reg, value, errmsg) >> operand->shift;
- insn |= B(myinsn);
- ls_operand[LS_BASE] = OP_REG;
- }
- else if (ARC_SHIMM_CONST_P (value) && !cond_p)
- {
- if (shimm_p && value != shimm)
- {
- /* Convert the previous shimm operand to a limm. */
- limm_p = 1;
- limm = shimm;
- insn &= ~C(-1); /* We know where the value is in insn. */
- insn |= C(ARC_REG_LIMM);
- ls_operand[LS_VALUE] = OP_LIMM;
- }
- insn |= ARC_REG_SHIMM << operand->shift;
- shimm_p = 1;
- shimm = value;
- ls_operand[LS_BASE] = OP_SHIMM;
- ls_operand[LS_OFFSET] = OP_SHIMM;
- }
- else
- {
- if (limm_p && value != limm)
- {
- *errmsg = _("too many long constants");
- return insn;
- }
- limm_p = 1;
- limm = value;
- insn |= B(ARC_REG_LIMM);
- ls_operand[LS_BASE] = OP_LIMM;
- }
-
- return insn;
-}
-
-/* Used in ld/st insns to handle the offset field. We don't try to
- match operand syntax here. we catch bad combinations later. */
-
-static arc_insn
-insert_offset (arc_insn insn,
- const struct arc_operand *operand,
- int mods,
- const struct arc_operand_value *reg,
- long value,
- const char **errmsg)
-{
- long minval, maxval;
-
- if (reg != NULL)
- {
- arc_insn myinsn;
- myinsn = insert_reg (0,operand,mods,reg,value,errmsg) >> operand->shift;
- ls_operand[LS_OFFSET] = OP_REG;
- if (operand->flags & ARC_OPERAND_LOAD) /* Not if store, catch it later. */
- if ((insn & I(-1)) != I(1)) /* Not if opcode == 1, catch it later. */
- insn |= C (myinsn);
- }
- else
- {
- /* This is *way* more general than necessary, but maybe some day it'll
- be useful. */
- if (operand->flags & ARC_OPERAND_SIGNED)
- {
- minval = -(1 << (operand->bits - 1));
- maxval = (1 << (operand->bits - 1)) - 1;
- }
- else
- {
- minval = 0;
- maxval = (1 << operand->bits) - 1;
- }
- if ((cond_p && !limm_p) || (value < minval || value > maxval))
- {
- if (limm_p && value != limm)
- *errmsg = _("too many long constants");
-
- else
- {
- limm_p = 1;
- limm = value;
- if (operand->flags & ARC_OPERAND_STORE)
- insn |= B(ARC_REG_LIMM);
- if (operand->flags & ARC_OPERAND_LOAD)
- insn |= C(ARC_REG_LIMM);
- ls_operand[LS_OFFSET] = OP_LIMM;
- }
- }
- else
- {
- if ((value < minval || value > maxval))
- *errmsg = "need too many limms";
- else if (shimm_p && value != shimm)
- {
- /* Check for bad operand combinations
- before we lose info about them. */
- if ((insn & I(-1)) == I(1))
- {
- *errmsg = _("too many shimms in load");
- goto out;
- }
- if (limm_p && operand->flags & ARC_OPERAND_LOAD)
- {
- *errmsg = _("too many long constants");
- goto out;
- }
- /* Convert what we thought was a shimm to a limm. */
- limm_p = 1;
- limm = shimm;
- if (ls_operand[LS_VALUE] == OP_SHIMM
- && operand->flags & ARC_OPERAND_STORE)
- {
- insn &= ~C(-1);
- insn |= C(ARC_REG_LIMM);
- ls_operand[LS_VALUE] = OP_LIMM;
- }
- if (ls_operand[LS_BASE] == OP_SHIMM
- && operand->flags & ARC_OPERAND_STORE)
- {
- insn &= ~B(-1);
- insn |= B(ARC_REG_LIMM);
- ls_operand[LS_BASE] = OP_LIMM;
- }
- }
- shimm = value;
- shimm_p = 1;
- ls_operand[LS_OFFSET] = OP_SHIMM;
- }
- }
- out:
- return insn;
-}
-
-/* Used in st insns to do final disasemble syntax check. */
-
-static long
-extract_st_syntax (arc_insn *insn,
- const struct arc_operand *operand ATTRIBUTE_UNUSED,
- int mods ATTRIBUTE_UNUSED,
- const struct arc_operand_value **opval ATTRIBUTE_UNUSED,
- int *invalid)
-{
-#define ST_SYNTAX(V,B,O) \
-((ls_operand[LS_VALUE] == (V) && \
- ls_operand[LS_BASE] == (B) && \
- ls_operand[LS_OFFSET] == (O)))
-
- if (!((ST_SYNTAX(OP_REG,OP_REG,OP_NONE) && (insn[0] & 511) == 0)
- || ST_SYNTAX(OP_REG,OP_LIMM,OP_NONE)
- || (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && (insn[0] & 511) == 0)
- || (ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_NONE) && (insn[0] & 511) == 0)
- || ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE)
- || ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_SHIMM)
- || ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_SHIMM)
- || (ST_SYNTAX(OP_LIMM,OP_REG,OP_NONE) && (insn[0] & 511) == 0)
- || ST_SYNTAX(OP_REG,OP_REG,OP_SHIMM)
- || ST_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM)
- || ST_SYNTAX(OP_SHIMM,OP_REG,OP_SHIMM)
- || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_SHIMM)
- || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_NONE)
- || ST_SYNTAX(OP_LIMM,OP_REG,OP_SHIMM)))
- *invalid = 1;
- return 0;
-}
-
-int
-arc_limm_fixup_adjust (arc_insn insn)
-{
- int retval = 0;
-
- /* Check for st shimm,[limm]. */
- if ((insn & (I(-1) | C(-1) | B(-1))) ==
- (I(2) | C(ARC_REG_SHIMM) | B(ARC_REG_LIMM)))
- {
- retval = insn & 0x1ff;
- if (retval & 0x100) /* Sign extend 9 bit offset. */
- retval |= ~0x1ff;
- }
- return -retval; /* Negate offset for return. */
-}
-
-/* Used in st insns to do final syntax check. */
-
-static arc_insn
-insert_st_syntax (arc_insn insn,
- const struct arc_operand *operand ATTRIBUTE_UNUSED,
- int mods ATTRIBUTE_UNUSED,
- const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
- long value ATTRIBUTE_UNUSED,
- const char **errmsg)
-{
- if (ST_SYNTAX (OP_SHIMM,OP_REG,OP_NONE) && shimm != 0)
- {
- /* Change an illegal insn into a legal one, it's easier to
- do it here than to try to handle it during operand scan. */
- limm_p = 1;
- limm = shimm;
- shimm_p = 0;
- shimm = 0;
- insn = insn & ~(C(-1) | 511);
- insn |= ARC_REG_LIMM << ARC_SHIFT_REGC;
- ls_operand[LS_VALUE] = OP_LIMM;
- }
-
- if (ST_SYNTAX (OP_REG, OP_SHIMM, OP_NONE)
- || ST_SYNTAX (OP_LIMM, OP_SHIMM, OP_NONE))
- {
- /* Try to salvage this syntax. */
- if (shimm & 0x1) /* Odd shimms won't work. */
- {
- if (limm_p) /* Do we have a limm already? */
- *errmsg = _("impossible store");
-
- limm_p = 1;
- limm = shimm;
- shimm = 0;
- shimm_p = 0;
- insn = insn & ~(B(-1) | 511);
- insn |= B(ARC_REG_LIMM);
- ls_operand[LS_BASE] = OP_LIMM;
- }
- else
- {
- shimm >>= 1;
- insn = insn & ~511;
- insn |= shimm;
- ls_operand[LS_OFFSET] = OP_SHIMM;
- }
- }
- if (ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE))
- limm += arc_limm_fixup_adjust(insn);
-
- if (! (ST_SYNTAX (OP_REG,OP_REG,OP_NONE)
- || ST_SYNTAX (OP_REG,OP_LIMM,OP_NONE)
- || ST_SYNTAX (OP_REG,OP_REG,OP_SHIMM)
- || ST_SYNTAX (OP_REG,OP_SHIMM,OP_SHIMM)
- || (ST_SYNTAX (OP_SHIMM,OP_SHIMM,OP_NONE) && (shimm == 0))
- || ST_SYNTAX (OP_SHIMM,OP_LIMM,OP_NONE)
- || ST_SYNTAX (OP_SHIMM,OP_REG,OP_NONE)
- || ST_SYNTAX (OP_SHIMM,OP_REG,OP_SHIMM)
- || ST_SYNTAX (OP_SHIMM,OP_SHIMM,OP_SHIMM)
- || ST_SYNTAX (OP_LIMM,OP_SHIMM,OP_SHIMM)
- || ST_SYNTAX (OP_LIMM,OP_REG,OP_NONE)
- || ST_SYNTAX (OP_LIMM,OP_REG,OP_SHIMM)))
- *errmsg = _("st operand error");
- if (addrwb_p)
- {
- if (ls_operand[LS_BASE] != OP_REG)
- *errmsg = _("address writeback not allowed");
- insn |= addrwb_p;
- }
- if (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && shimm)
- *errmsg = _("store value must be zero");
- return insn;
-}
-
-/* Used in ld insns to do final syntax check. */
-
-static arc_insn
-insert_ld_syntax (arc_insn insn,
- const struct arc_operand *operand ATTRIBUTE_UNUSED,
- int mods ATTRIBUTE_UNUSED,
- const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
- long value ATTRIBUTE_UNUSED,
- const char **errmsg)
-{
-#define LD_SYNTAX(D, B, O) \
- ( (ls_operand[LS_DEST] == (D) \
- && ls_operand[LS_BASE] == (B) \
- && ls_operand[LS_OFFSET] == (O)))
-
- int test = insn & I (-1);
-
- if (!(test == I (1)))
- {
- if ((ls_operand[LS_DEST] == OP_SHIMM || ls_operand[LS_BASE] == OP_SHIMM
- || ls_operand[LS_OFFSET] == OP_SHIMM))
- *errmsg = _("invalid load/shimm insn");
- }
- if (!(LD_SYNTAX(OP_REG,OP_REG,OP_NONE)
- || LD_SYNTAX(OP_REG,OP_REG,OP_REG)
- || LD_SYNTAX(OP_REG,OP_REG,OP_SHIMM)
- || (LD_SYNTAX(OP_REG,OP_LIMM,OP_REG) && !(test == I(1)))
- || (LD_SYNTAX(OP_REG,OP_REG,OP_LIMM) && !(test == I(1)))
- || LD_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM)
- || (LD_SYNTAX(OP_REG,OP_LIMM,OP_NONE) && (test == I(1)))))
- *errmsg = _("ld operand error");
- if (addrwb_p)
- {
- if (ls_operand[LS_BASE] != OP_REG)
- *errmsg = _("address writeback not allowed");
- insn |= addrwb_p;
- }
- return insn;
-}
-
-/* Used in ld insns to do final syntax check. */
-
-static long
-extract_ld_syntax (arc_insn *insn,
- const struct arc_operand *operand ATTRIBUTE_UNUSED,
- int mods ATTRIBUTE_UNUSED,
- const struct arc_operand_value **opval ATTRIBUTE_UNUSED,
- int *invalid)
-{
- int test = insn[0] & I(-1);
-
- if (!(test == I(1)))
- {
- if ((ls_operand[LS_DEST] == OP_SHIMM || ls_operand[LS_BASE] == OP_SHIMM
- || ls_operand[LS_OFFSET] == OP_SHIMM))
- *invalid = 1;
- }
- if (!( (LD_SYNTAX (OP_REG, OP_REG, OP_NONE) && (test == I(1)))
- || LD_SYNTAX (OP_REG, OP_REG, OP_REG)
- || LD_SYNTAX (OP_REG, OP_REG, OP_SHIMM)
- || (LD_SYNTAX (OP_REG, OP_REG, OP_LIMM) && !(test == I(1)))
- || (LD_SYNTAX (OP_REG, OP_LIMM, OP_REG) && !(test == I(1)))
- || (LD_SYNTAX (OP_REG, OP_SHIMM, OP_NONE) && (shimm == 0))
- || LD_SYNTAX (OP_REG, OP_SHIMM, OP_SHIMM)
- || (LD_SYNTAX (OP_REG, OP_LIMM, OP_NONE) && (test == I(1)))))
- *invalid = 1;
- return 0;
-}
-
-/* Called at the end of processing normal insns (eg: add) to insert a shimm
- value (if present) into the insn. */
-
-static arc_insn
-insert_shimmfinish (arc_insn insn,
- const struct arc_operand *operand,
- int mods ATTRIBUTE_UNUSED,
- const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
- long value ATTRIBUTE_UNUSED,
- const char **errmsg ATTRIBUTE_UNUSED)
-{
- if (shimm_p)
- insn |= (shimm & ((1 << operand->bits) - 1)) << operand->shift;
- return insn;
-}
-
-/* Called at the end of processing normal insns (eg: add) to insert a limm
- value (if present) into the insn.
-
- Note that this function is only intended to handle instructions (with 4 byte
- immediate operands). It is not intended to handle data. */
-
-/* ??? Actually, there's nothing for us to do as we can't call frag_more, the
- caller must do that. The extract fns take a pointer to two words. The
- insert fns could be converted and then we could do something useful, but
- then the reloc handlers would have to know to work on the second word of
- a 2 word quantity. That's too much so we don't handle them. */
-
-static arc_insn
-insert_limmfinish (arc_insn insn,
- const struct arc_operand *operand ATTRIBUTE_UNUSED,
- int mods ATTRIBUTE_UNUSED,
- const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
- long value ATTRIBUTE_UNUSED,
- const char **errmsg ATTRIBUTE_UNUSED)
-{
- return insn;
-}
-
-static arc_insn
-insert_jumpflags (arc_insn insn,
- const struct arc_operand *operand,
- int mods ATTRIBUTE_UNUSED,
- const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
- long value,
- const char **errmsg)
-{
- if (!flag_p)
- *errmsg = _("jump flags, but no .f seen");
-
- else if (!limm_p)
- *errmsg = _("jump flags, but no limm addr");
-
- else if (limm & 0xfc000000)
- *errmsg = _("flag bits of jump address limm lost");
-
- else if (limm & 0x03000000)
- *errmsg = _("attempt to set HR bits");
-
- else if ((value & ((1 << operand->bits) - 1)) != value)
- *errmsg = _("bad jump flags value");
-
- jumpflags_p = 1;
- limm = ((limm & ((1 << operand->shift) - 1))
- | ((value & ((1 << operand->bits) - 1)) << operand->shift));
- return insn;
-}
-
-/* Called at the end of unary operand macros to copy the B field to C. */
-
-static arc_insn
-insert_unopmacro (arc_insn insn,
- const struct arc_operand *operand,
- int mods ATTRIBUTE_UNUSED,
- const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
- long value ATTRIBUTE_UNUSED,
- const char **errmsg ATTRIBUTE_UNUSED)
-{
- insn |= ((insn >> ARC_SHIFT_REGB) & ARC_MASK_REG) << operand->shift;
- return insn;
-}
-
-/* Insert a relative address for a branch insn (b, bl, or lp). */
-
-static arc_insn
-insert_reladdr (arc_insn insn,
- const struct arc_operand *operand,
- int mods ATTRIBUTE_UNUSED,
- const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
- long value,
- const char **errmsg)
-{
- if (value & 3)
- *errmsg = _("branch address not on 4 byte boundary");
- insn |= ((value >> 2) & ((1 << operand->bits) - 1)) << operand->shift;
- return insn;
-}
-
-/* Insert a limm value as a 26 bit address right shifted 2 into the insn.
-
- Note that this function is only intended to handle instructions (with 4 byte
- immediate operands). It is not intended to handle data. */
-
-/* ??? Actually, there's little for us to do as we can't call frag_more, the
- caller must do that. The extract fns take a pointer to two words. The
- insert fns could be converted and then we could do something useful, but
- then the reloc handlers would have to know to work on the second word of
- a 2 word quantity. That's too much so we don't handle them.
-
- We do check for correct usage of the nullify suffix, or we
- set the default correctly, though. */
-
-static arc_insn
-insert_absaddr (arc_insn insn,
- const struct arc_operand *operand ATTRIBUTE_UNUSED,
- int mods ATTRIBUTE_UNUSED,
- const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
- long value ATTRIBUTE_UNUSED,
- const char **errmsg)
-{
- if (limm_p)
- {
- /* If it is a jump and link, .jd must be specified. */
- if (insn & R (-1, 9, 1))
- {
- if (!nullify_p)
- insn |= 0x02 << 5; /* Default nullify to .jd. */
-
- else if (nullify != 0x02)
- *errmsg = _("must specify .jd or no nullify suffix");
- }
- }
- return insn;
-}
-
-/* Extraction functions.
-
- The suffix extraction functions' return value is redundant since it can be
- obtained from (*OPVAL)->value. However, the boolean suffixes don't have
- a suffix table entry for the "false" case, so values of zero must be
- obtained from the return value (*OPVAL == NULL). */
-
-/* Called by the disassembler before printing an instruction. */
-
-void
-arc_opcode_init_extract (void)
-{
- arc_opcode_init_insert ();
-}
-
-static const struct arc_operand_value *
-lookup_register (int type, long regno)
-{
- const struct arc_operand_value *r,*end;
- struct arc_ext_operand_value *ext_oper = arc_ext_operands;
-
- while (ext_oper)
- {
- if (ext_oper->operand.type == type && ext_oper->operand.value == regno)
- return (&ext_oper->operand);
- ext_oper = ext_oper->next;
- }
-
- if (type == REG)
- return &arc_reg_names[regno];
-
- /* ??? This is a little slow and can be speeded up. */
- for (r = arc_reg_names, end = arc_reg_names + arc_reg_names_count;
- r < end; ++r)
- if (type == r->type && regno == r->value)
- return r;
- return 0;
-}
-
-/* As we're extracting registers, keep an eye out for the 'f' indicator
- (ARC_REG_SHIMM_UPDATE). If we find a register (not a constant marker,
- like ARC_REG_SHIMM), set OPVAL so our caller will know this is a register.
-
- We must also handle auxiliary registers for lr/sr insns. They are just
- constants with special names. */
-
-static long
-extract_reg (arc_insn *insn,
- const struct arc_operand *operand,
- int mods,
- const struct arc_operand_value **opval,
- int *invalid ATTRIBUTE_UNUSED)
-{
- int regno;
- long value;
- enum operand op_type;
-
- /* Get the register number. */
- regno = (*insn >> operand->shift) & ((1 << operand->bits) - 1);
-
- /* Is it a constant marker? */
- if (regno == ARC_REG_SHIMM)
- {
- op_type = OP_SHIMM;
- /* Always return zero if dest is a shimm mlm. */
-
- if ('a' != operand->fmt)
- {
- value = *insn & 511;
- if ((operand->flags & ARC_OPERAND_SIGNED)
- && (value & 256))
- value -= 512;
- if (!flagshimm_handled_p)
- flag_p = 0;
- flagshimm_handled_p = 1;
- }
- else
- value = 0;
- }
- else if (regno == ARC_REG_SHIMM_UPDATE)
- {
- op_type = OP_SHIMM;
-
- /* Always return zero if dest is a shimm mlm. */
- if ('a' != operand->fmt)
- {
- value = *insn & 511;
- if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256))
- value -= 512;
- }
- else
- value = 0;
-
- flag_p = 1;
- flagshimm_handled_p = 1;
- }
- else if (regno == ARC_REG_LIMM)
- {
- op_type = OP_LIMM;
- value = insn[1];
- limm_p = 1;
-
- /* If this is a jump instruction (j,jl), show new pc correctly. */
- if (0x07 == ((*insn & I(-1)) >> 27))
- value = (value & 0xffffff);
- }
-
- /* It's a register, set OPVAL (that's the only way we distinguish registers
- from constants here). */
- else
- {
- const struct arc_operand_value *reg = lookup_register (REG, regno);
-
- op_type = OP_REG;
-
- if (reg == NULL)
- abort ();
- if (opval != NULL)
- *opval = reg;
- value = regno;
- }
-
- /* If this field takes an auxiliary register, see if it's a known one. */
- if ((mods & ARC_MOD_AUXREG)
- && ARC_REG_CONSTANT_P (regno))
- {
- const struct arc_operand_value *reg = lookup_register (AUXREG, value);
-
- /* This is really a constant, but tell the caller it has a special
- name. */
- if (reg != NULL && opval != NULL)
- *opval = reg;
- }
-
- switch(operand->fmt)
- {
- case 'a':
- ls_operand[LS_DEST] = op_type;
- break;
- case 's':
- ls_operand[LS_BASE] = op_type;
- break;
- case 'c':
- if ((insn[0]& I(-1)) == I(2))
- ls_operand[LS_VALUE] = op_type;
- else
- ls_operand[LS_OFFSET] = op_type;
- break;
- case 'o': case 'O':
- ls_operand[LS_OFFSET] = op_type;
- break;
- }
-
- return value;
-}
-
-/* Return the value of the "flag update" field for shimm insns.
- This value is actually stored in the register field. */
-
-static long
-extract_flag (arc_insn *insn,
- const struct arc_operand *operand,
- int mods ATTRIBUTE_UNUSED,
- const struct arc_operand_value **opval,
- int *invalid ATTRIBUTE_UNUSED)
-{
- int f;
- const struct arc_operand_value *val;
-
- if (flagshimm_handled_p)
- f = flag_p != 0;
- else
- f = (*insn & (1 << operand->shift)) != 0;
-
- /* There is no text for zero values. */
- if (f == 0)
- return 0;
- flag_p = 1;
- val = arc_opcode_lookup_suffix (operand, 1);
- if (opval != NULL && val != NULL)
- *opval = val;
- return val->value;
-}
-
-/* Extract the condition code (if it exists).
- If we've seen a shimm value in this insn (meaning that the insn can't have
- a condition code field), then we don't store anything in OPVAL and return
- zero. */
-
-static long
-extract_cond (arc_insn *insn,
- const struct arc_operand *operand,
- int mods ATTRIBUTE_UNUSED,
- const struct arc_operand_value **opval,
- int *invalid ATTRIBUTE_UNUSED)
-{
- long cond;
- const struct arc_operand_value *val;
-
- if (flagshimm_handled_p)
- return 0;
-
- cond = (*insn >> operand->shift) & ((1 << operand->bits) - 1);
- val = arc_opcode_lookup_suffix (operand, cond);
-
- /* Ignore NULL values of `val'. Several condition code values are
- reserved for extensions. */
- if (opval != NULL && val != NULL)
- *opval = val;
- return cond;
-}
-
-/* Extract a branch address.
- We return the value as a real address (not right shifted by 2). */
-
-static long
-extract_reladdr (arc_insn *insn,
- const struct arc_operand *operand,
- int mods ATTRIBUTE_UNUSED,
- const struct arc_operand_value **opval ATTRIBUTE_UNUSED,
- int *invalid ATTRIBUTE_UNUSED)
-{
- long addr;
-
- addr = (*insn >> operand->shift) & ((1 << operand->bits) - 1);
- if ((operand->flags & ARC_OPERAND_SIGNED)
- && (addr & (1 << (operand->bits - 1))))
- addr -= 1 << operand->bits;
- return addr << 2;
-}
-
-/* Extract the flags bits from a j or jl long immediate. */
-
-static long
-extract_jumpflags (arc_insn *insn,
- const struct arc_operand *operand,
- int mods ATTRIBUTE_UNUSED,
- const struct arc_operand_value **opval ATTRIBUTE_UNUSED,
- int *invalid)
-{
- if (!flag_p || !limm_p)
- *invalid = 1;
- return ((flag_p && limm_p)
- ? (insn[1] >> operand->shift) & ((1 << operand->bits) -1): 0);
-}
-
-/* Extract st insn's offset. */
-
-static long
-extract_st_offset (arc_insn *insn,
- const struct arc_operand *operand,
- int mods ATTRIBUTE_UNUSED,
- const struct arc_operand_value **opval ATTRIBUTE_UNUSED,
- int *invalid)
-{
- int value = 0;
-
- if (ls_operand[LS_VALUE] != OP_SHIMM || ls_operand[LS_BASE] != OP_LIMM)
- {
- value = insn[0] & 511;
- if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256))
- value -= 512;
- if (value)
- ls_operand[LS_OFFSET] = OP_SHIMM;
- }
- else
- *invalid = 1;
-
- return value;
-}
-
-/* Extract ld insn's offset. */
-
-static long
-extract_ld_offset (arc_insn *insn,
- const struct arc_operand *operand,
- int mods,
- const struct arc_operand_value **opval,
- int *invalid)
-{
- int test = insn[0] & I(-1);
- int value;
-
- if (test)
- {
- value = insn[0] & 511;
- if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256))
- value -= 512;
- if (value)
- ls_operand[LS_OFFSET] = OP_SHIMM;
-
- return value;
- }
- /* If it isn't in the insn, it's concealed behind reg 'c'. */
- return extract_reg (insn, &arc_operands[arc_operand_map['c']],
- mods, opval, invalid);
-}
-
-/* The only thing this does is set the `invalid' flag if B != C.
- This is needed because the "mov" macro appears before it's real insn "and"
- and we don't want the disassembler to confuse them. */
-
-static long
-extract_unopmacro (arc_insn *insn,
- const struct arc_operand *operand ATTRIBUTE_UNUSED,
- int mods ATTRIBUTE_UNUSED,
- const struct arc_operand_value **opval ATTRIBUTE_UNUSED,
- int *invalid)
-{
- /* This misses the case where B == ARC_REG_SHIMM_UPDATE &&
- C == ARC_REG_SHIMM (or vice versa). No big deal. Those insns will get
- printed as "and"s. */
- if (((*insn >> ARC_SHIFT_REGB) & ARC_MASK_REG)
- != ((*insn >> ARC_SHIFT_REGC) & ARC_MASK_REG))
- if (invalid != NULL)
- *invalid = 1;
- return 0;
-}
-
-/* ARC instructions.
-
- Longer versions of insns must appear before shorter ones (if gas sees
- "lsr r2,r3,1" when it's parsing "lsr %a,%b" it will think the ",1" is
- junk). This isn't necessary for `ld' because of the trailing ']'.
-
- Instructions that are really macros based on other insns must appear
- before the real insn so they're chosen when disassembling. Eg: The `mov'
- insn is really the `and' insn. */
-
-struct arc_opcode arc_opcodes[] =
-{
- /* Base case instruction set (core versions 5-8). */
-
- /* "mov" is really an "and". */
- { "mov%.q%.f %a,%b%F%S%L%U", I(-1), I(12), ARC_MACH_5, 0, 0 },
- /* "asl" is really an "add". */
- { "asl%.q%.f %a,%b%F%S%L%U", I(-1), I(8), ARC_MACH_5, 0, 0 },
- /* "lsl" is really an "add". */
- { "lsl%.q%.f %a,%b%F%S%L%U", I(-1), I(8), ARC_MACH_5, 0, 0 },
- /* "nop" is really an "xor". */
- { "nop", 0x7fffffff, 0x7fffffff, ARC_MACH_5, 0, 0 },
- /* "rlc" is really an "adc". */
- { "rlc%.q%.f %a,%b%F%S%L%U", I(-1), I(9), ARC_MACH_5, 0, 0 },
- { "adc%.q%.f %a,%b,%c%F%S%L", I(-1), I(9), ARC_MACH_5, 0, 0 },
- { "add%.q%.f %a,%b,%c%F%S%L", I(-1), I(8), ARC_MACH_5, 0, 0 },
- { "and%.q%.f %a,%b,%c%F%S%L", I(-1), I(12), ARC_MACH_5, 0, 0 },
- { "asr%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(1), ARC_MACH_5, 0, 0 },
- { "bic%.q%.f %a,%b,%c%F%S%L", I(-1), I(14), ARC_MACH_5, 0, 0 },
- { "b%q%.n %B", I(-1), I(4), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 },
- { "bl%q%.n %B", I(-1), I(5), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 },
- { "extb%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(7), ARC_MACH_5, 0, 0 },
- { "extw%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(8), ARC_MACH_5, 0, 0 },
- { "flag%.q %b%G%S%L", I(-1)|A(-1)|C(-1), I(3)|A(ARC_REG_SHIMM_UPDATE)|C(0), ARC_MACH_5, 0, 0 },
- { "brk", 0x1ffffe00, 0x1ffffe00, ARC_MACH_7, 0, 0 },
- { "sleep", 0x1ffffe01, 0x1ffffe01, ARC_MACH_7, 0, 0 },
- { "swi", 0x1ffffe02, 0x1ffffe02, ARC_MACH_8, 0, 0 },
- /* %Q: force cond_p=1 -> no shimm values. This insn allows an
- optional flags spec. */
- { "j%q%Q%.n%.f %b%F%J,%j", I(-1)|A(-1)|C(-1)|R(-1,7,1), I(7)|A(0)|C(0)|R(0,7,1), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 },
- { "j%q%Q%.n%.f %b%F%J", I(-1)|A(-1)|C(-1)|R(-1,7,1), I(7)|A(0)|C(0)|R(0,7,1), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 },
- /* This insn allows an optional flags spec. */
- { "jl%q%Q%.n%.f %b%F%J,%j", I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1), I(7)|A(0)|C(0)|R(0,7,1)|R(1,9,1), ARC_MACH_6 | ARC_OPCODE_COND_BRANCH, 0, 0 },
- { "jl%q%Q%.n%.f %b%F%J", I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1), I(7)|A(0)|C(0)|R(0,7,1)|R(1,9,1), ARC_MACH_6 | ARC_OPCODE_COND_BRANCH, 0, 0 },
- /* Put opcode 1 ld insns first so shimm gets prefered over limm.
- "[%b]" is before "[%b,%o]" so 0 offsets don't get printed. */
- { "ld%Z%.X%.W%.E %a,[%s]%S%L%1", I(-1)|R(-1,13,1)|R(-1,0,511), I(1)|R(0,13,1)|R(0,0,511), ARC_MACH_5, 0, 0 },
- { "ld%z%.x%.w%.e %a,[%s]%S%L%1", I(-1)|R(-1,4,1)|R(-1,6,7), I(0)|R(0,4,1)|R(0,6,7), ARC_MACH_5, 0, 0 },
- { "ld%z%.x%.w%.e %a,[%s,%O]%S%L%1", I(-1)|R(-1,4,1)|R(-1,6,7), I(0)|R(0,4,1)|R(0,6,7), ARC_MACH_5, 0, 0 },
- { "ld%Z%.X%.W%.E %a,[%s,%O]%S%L%3", I(-1)|R(-1,13,1), I(1)|R(0,13,1), ARC_MACH_5, 0, 0 },
- { "lp%q%.n %B", I(-1), I(6), ARC_MACH_5, 0, 0 },
- { "lr %a,[%Ab]%S%L", I(-1)|C(-1), I(1)|C(0x10), ARC_MACH_5, 0, 0 },
- { "lsr%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(2), ARC_MACH_5, 0, 0 },
- { "or%.q%.f %a,%b,%c%F%S%L", I(-1), I(13), ARC_MACH_5, 0, 0 },
- { "ror%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(3), ARC_MACH_5, 0, 0 },
- { "rrc%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(4), ARC_MACH_5, 0, 0 },
- { "sbc%.q%.f %a,%b,%c%F%S%L", I(-1), I(11), ARC_MACH_5, 0, 0 },
- { "sexb%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(5), ARC_MACH_5, 0, 0 },
- { "sexw%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(6), ARC_MACH_5, 0, 0 },
- { "sr %c,[%Ab]%S%L", I(-1)|A(-1), I(2)|A(0x10), ARC_MACH_5, 0, 0 },
- /* "[%b]" is before "[%b,%o]" so 0 offsets don't get printed. */
- { "st%y%.v%.D %c,[%s]%L%S%0", I(-1)|R(-1,25,1)|R(-1,21,1), I(2)|R(0,25,1)|R(0,21,1), ARC_MACH_5, 0, 0 },
- { "st%y%.v%.D %c,[%s,%o]%S%L%2", I(-1)|R(-1,25,1)|R(-1,21,1), I(2)|R(0,25,1)|R(0,21,1), ARC_MACH_5, 0, 0 },
- { "sub%.q%.f %a,%b,%c%F%S%L", I(-1), I(10), ARC_MACH_5, 0, 0 },
- { "xor%.q%.f %a,%b,%c%F%S%L", I(-1), I(15), ARC_MACH_5, 0, 0 }
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define F(f) & arc_cgen_ifld_table[ARC_##f]
+#else
+#define F(f) & arc_cgen_ifld_table[ARC_/**/f]
+#endif
+static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = {
+ 0, 0, 0x0, { { 0 } }
};
-const int arc_opcodes_count = sizeof (arc_opcodes) / sizeof (arc_opcodes[0]);
-
-const struct arc_operand_value arc_reg_names[] =
-{
- /* Core register set r0-r63. */
-
- /* r0-r28 - general purpose registers. */
- { "r0", 0, REG, 0 }, { "r1", 1, REG, 0 }, { "r2", 2, REG, 0 },
- { "r3", 3, REG, 0 }, { "r4", 4, REG, 0 }, { "r5", 5, REG, 0 },
- { "r6", 6, REG, 0 }, { "r7", 7, REG, 0 }, { "r8", 8, REG, 0 },
- { "r9", 9, REG, 0 }, { "r10", 10, REG, 0 }, { "r11", 11, REG, 0 },
- { "r12", 12, REG, 0 }, { "r13", 13, REG, 0 }, { "r14", 14, REG, 0 },
- { "r15", 15, REG, 0 }, { "r16", 16, REG, 0 }, { "r17", 17, REG, 0 },
- { "r18", 18, REG, 0 }, { "r19", 19, REG, 0 }, { "r20", 20, REG, 0 },
- { "r21", 21, REG, 0 }, { "r22", 22, REG, 0 }, { "r23", 23, REG, 0 },
- { "r24", 24, REG, 0 }, { "r25", 25, REG, 0 }, { "r26", 26, REG, 0 },
- { "r27", 27, REG, 0 }, { "r28", 28, REG, 0 },
- /* Maskable interrupt link register. */
- { "ilink1", 29, REG, 0 },
- /* Maskable interrupt link register. */
- { "ilink2", 30, REG, 0 },
- /* Branch-link register. */
- { "blink", 31, REG, 0 },
-
- /* r32-r59 reserved for extensions. */
- { "r32", 32, REG, 0 }, { "r33", 33, REG, 0 }, { "r34", 34, REG, 0 },
- { "r35", 35, REG, 0 }, { "r36", 36, REG, 0 }, { "r37", 37, REG, 0 },
- { "r38", 38, REG, 0 }, { "r39", 39, REG, 0 }, { "r40", 40, REG, 0 },
- { "r41", 41, REG, 0 }, { "r42", 42, REG, 0 }, { "r43", 43, REG, 0 },
- { "r44", 44, REG, 0 }, { "r45", 45, REG, 0 }, { "r46", 46, REG, 0 },
- { "r47", 47, REG, 0 }, { "r48", 48, REG, 0 }, { "r49", 49, REG, 0 },
- { "r50", 50, REG, 0 }, { "r51", 51, REG, 0 }, { "r52", 52, REG, 0 },
- { "r53", 53, REG, 0 }, { "r54", 54, REG, 0 }, { "r55", 55, REG, 0 },
- { "r56", 56, REG, 0 }, { "r57", 57, REG, 0 }, { "r58", 58, REG, 0 },
- { "r59", 59, REG, 0 },
-
- /* Loop count register (24 bits). */
- { "lp_count", 60, REG, 0 },
- /* Short immediate data indicator setting flags. */
- { "r61", 61, REG, ARC_REGISTER_READONLY },
- /* Long immediate data indicator setting flags. */
- { "r62", 62, REG, ARC_REGISTER_READONLY },
- /* Short immediate data indicator not setting flags. */
- { "r63", 63, REG, ARC_REGISTER_READONLY },
-
- /* Small-data base register. */
- { "gp", 26, REG, 0 },
- /* Frame pointer. */
- { "fp", 27, REG, 0 },
- /* Stack pointer. */
- { "sp", 28, REG, 0 },
-
- { "r29", 29, REG, 0 },
- { "r30", 30, REG, 0 },
- { "r31", 31, REG, 0 },
- { "r60", 60, REG, 0 },
-
- /* Auxiliary register set. */
-
- /* Auxiliary register address map:
- 0xffffffff-0xffffff00 (-1..-256) - customer shimm allocation
- 0xfffffeff-0x80000000 - customer limm allocation
- 0x7fffffff-0x00000100 - ARC limm allocation
- 0x000000ff-0x00000000 - ARC shimm allocation */
-
- /* Base case auxiliary registers (shimm address). */
- { "status", 0x00, AUXREG, 0 },
- { "semaphore", 0x01, AUXREG, 0 },
- { "lp_start", 0x02, AUXREG, 0 },
- { "lp_end", 0x03, AUXREG, 0 },
- { "identity", 0x04, AUXREG, ARC_REGISTER_READONLY },
- { "debug", 0x05, AUXREG, 0 },
+static const CGEN_IFMT ifmt_b_s ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8000000, { { F (F_OPM) }, { F (F_COND_I2) }, { F (F_REL10) }, { F (F_DUMMY) }, { 0 } }
};
-const int arc_reg_names_count =
- sizeof (arc_reg_names) / sizeof (arc_reg_names[0]);
-
-/* The suffix table.
- Operands with the same name must be stored together. */
-
-const struct arc_operand_value arc_suffixes[] =
-{
- /* Entry 0 is special, default values aren't printed by the disassembler. */
- { "", 0, -1, 0 },
-
- /* Base case condition codes. */
- { "al", 0, COND, 0 },
- { "ra", 0, COND, 0 },
- { "eq", 1, COND, 0 },
- { "z", 1, COND, 0 },
- { "ne", 2, COND, 0 },
- { "nz", 2, COND, 0 },
- { "pl", 3, COND, 0 },
- { "p", 3, COND, 0 },
- { "mi", 4, COND, 0 },
- { "n", 4, COND, 0 },
- { "cs", 5, COND, 0 },
- { "c", 5, COND, 0 },
- { "lo", 5, COND, 0 },
- { "cc", 6, COND, 0 },
- { "nc", 6, COND, 0 },
- { "hs", 6, COND, 0 },
- { "vs", 7, COND, 0 },
- { "v", 7, COND, 0 },
- { "vc", 8, COND, 0 },
- { "nv", 8, COND, 0 },
- { "gt", 9, COND, 0 },
- { "ge", 10, COND, 0 },
- { "lt", 11, COND, 0 },
- { "le", 12, COND, 0 },
- { "hi", 13, COND, 0 },
- { "ls", 14, COND, 0 },
- { "pnz", 15, COND, 0 },
-
- /* Condition codes 16-31 reserved for extensions. */
-
- { "f", 1, FLAG, 0 },
-
- { "nd", ARC_DELAY_NONE, DELAY, 0 },
- { "d", ARC_DELAY_NORMAL, DELAY, 0 },
- { "jd", ARC_DELAY_JUMP, DELAY, 0 },
-
- { "b", 1, SIZE1, 0 },
- { "b", 1, SIZE10, 0 },
- { "b", 1, SIZE22, 0 },
- { "w", 2, SIZE1, 0 },
- { "w", 2, SIZE10, 0 },
- { "w", 2, SIZE22, 0 },
- { "x", 1, SIGN0, 0 },
- { "x", 1, SIGN9, 0 },
- { "a", 1, ADDRESS3, 0 },
- { "a", 1, ADDRESS12, 0 },
- { "a", 1, ADDRESS24, 0 },
-
- { "di", 1, CACHEBYPASS5, 0 },
- { "di", 1, CACHEBYPASS14, 0 },
- { "di", 1, CACHEBYPASS26, 0 },
+static const CGEN_IFMT ifmt_bcc_s ATTRIBUTE_UNUSED = {
+ 32, 32, 0xfe000000, { { F (F_OPM) }, { F (F_COND_I2) }, { F (F_COND_I3) }, { F (F_REL7) }, { F (F_DUMMY) }, { 0 } }
};
-const int arc_suffixes_count =
- sizeof (arc_suffixes) / sizeof (arc_suffixes[0]);
+static const CGEN_IFMT ifmt_brcc_s ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8000000, { { F (F_OPM) }, { F (F_OP__B) }, { F (F_BRSCOND) }, { F (F_REL8) }, { F (F_DUMMY) }, { 0 } }
+};
-/* Indexed by first letter of opcode. Points to chain of opcodes with same
- first letter. */
-static struct arc_opcode *opcode_map[26 + 1];
+static const CGEN_IFMT ifmt_bcc_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8010020, { { F (F_OPM) }, { F (F_REL21) }, { F (F_BUF) }, { F (F_DELAY_N) }, { F (F_COND_Q) }, { 0 } }
+};
-/* Indexed by insn code. Points to chain of opcodes with same insn code. */
-static struct arc_opcode *icode_map[32];
-
-/* Configuration flags. */
+static const CGEN_IFMT ifmt_b_l ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8010030, { { F (F_OPM) }, { F (F_REL25) }, { F (F_BUF) }, { F (F_DELAY_N) }, { F (F_RES27) }, { 0 } }
+};
-/* Various ARC_HAVE_XXX bits. */
-static int cpu_type;
+static const CGEN_IFMT ifmt_brcc_RC ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8010030, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_REL9) }, { F (F_BUF) }, { F (F_OP_C) }, { F (F_DELAY_N) }, { F (F_BR) }, { F (F_BRCOND) }, { 0 } }
+};
-/* Translate a bfd_mach_arc_xxx value to a ARC_MACH_XXX value. */
+static const CGEN_IFMT ifmt_brcc_U6 ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8010030, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_REL9) }, { F (F_BUF) }, { F (F_U6) }, { F (F_DELAY_N) }, { F (F_BR) }, { F (F_BRCOND) }, { 0 } }
+};
-int
-arc_get_opcode_mach (int bfd_mach, int big_p)
+static const CGEN_IFMT ifmt_bl_s ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8000000, { { F (F_OPM) }, { F (F_REL13BL) }, { F (F_DUMMY) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_blcc ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8030020, { { F (F_OPM) }, { F (F_REL21BL) }, { F (F_BLUF) }, { F (F_BUF) }, { F (F_DELAY_N) }, { F (F_COND_Q) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bl ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8030030, { { F (F_OPM) }, { F (F_REL25BL) }, { F (F_BLUF) }, { F (F_BUF) }, { F (F_DELAY_N) }, { F (F_RES27) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ld_abs ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf80007c0, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_S9) }, { F (F_LDODI) }, { F (F_LDOAA) }, { F (F_LDOZZX) }, { F (F_OP_A) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ld_abc ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_LDRAA) }, { F (F_LDR6ZZX) }, { F (F_LDRDI) }, { F (F_OP_C) }, { F (F_OP_A) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ld_s_abc ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8180000, { { F (F_OPM) }, { F (F_OP__B) }, { F (F_OP__C) }, { F (F_I16_43) }, { F (F_OP__A) }, { F (F_DUMMY) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ld_s_abu ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8000000, { { F (F_OPM) }, { F (F_OP__B) }, { F (F_OP__C) }, { F (F_U5X4) }, { F (F_DUMMY) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ld_s_absp ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8e00000, { { F (F_OPM) }, { F (F_OP__B) }, { F (F_OP__C) }, { F (F_U5X4) }, { F (F_DUMMY) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ld_s_gprel ATTRIBUTE_UNUSED = {
+ 32, 32, 0xfe000000, { { F (F_OPM) }, { F (F_I16_GP_TYPE) }, { F (F_S9X4) }, { F (F_DUMMY) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ld_s_pcrel ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8000000, { { F (F_OPM) }, { F (F_OP__B) }, { F (F_U8X4) }, { F (F_DUMMY) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldb_s_abu ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8000000, { { F (F_OPM) }, { F (F_OP__B) }, { F (F_OP__C) }, { F (F_U5) }, { F (F_DUMMY) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldb_s_gprel ATTRIBUTE_UNUSED = {
+ 32, 32, 0xfe000000, { { F (F_OPM) }, { F (F_I16_GP_TYPE) }, { F (F_S9X1) }, { F (F_DUMMY) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldw_s_abu ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8000000, { { F (F_OPM) }, { F (F_OP__B) }, { F (F_OP__C) }, { F (F_U5X2) }, { F (F_DUMMY) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldw_s_gprel ATTRIBUTE_UNUSED = {
+ 32, 32, 0xfe000000, { { F (F_OPM) }, { F (F_I16_GP_TYPE) }, { F (F_S9X2) }, { F (F_DUMMY) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_st_abs ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf800001f, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_S9) }, { F (F_LDODI) }, { F (F_OP_C) }, { F (F_STOAA) }, { F (F_STOZZR) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_add_L_s12__RA_ ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_S12) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_add_ccu6__RA_ ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8ff0020, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_U6) }, { F (F_GO_CC_TYPE) }, { F (F_COND_Q) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_add_L_u6__RA_ ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_U6) }, { F (F_OP_A) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_add_L_r_r__RA__RC ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_OP_C) }, { F (F_OP_A) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_add_cc__RA__RC ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8ff0020, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_OP_C) }, { F (F_GO_CC_TYPE) }, { F (F_COND_Q) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_add_s_cbu3 ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8180000, { { F (F_OPM) }, { F (F_OP__B) }, { F (F_OP__C) }, { F (F_I16_43) }, { F (F_U3) }, { F (F_DUMMY) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_add_s_mcah ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8180000, { { F (F_OPM) }, { F (F_OP__B) }, { F (F_OP_H) }, { F (F_I16_43) }, { F (F_DUMMY) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_add_s_asspsp ATTRIBUTE_UNUSED = {
+ 32, 32, 0xffe00000, { { F (F_OPM) }, { F (F_OP__B) }, { F (F_OP__C) }, { F (F_U5X4) }, { F (F_DUMMY) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_add_s_gp ATTRIBUTE_UNUSED = {
+ 32, 32, 0xfe000000, { { F (F_OPM) }, { F (F_I16_GP_TYPE) }, { F (F_S9X4) }, { F (F_DUMMY) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_add_s_r_u7 ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8800000, { { F (F_OPM) }, { F (F_OP__B) }, { F (F_I16ADDCMPU7_TYPE) }, { F (F_U7) }, { F (F_DUMMY) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_I16_GO_SUB_s_go ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf81f0000, { { F (F_OPM) }, { F (F_OP__B) }, { F (F_OP__C) }, { F (F_I16_GO) }, { F (F_DUMMY) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_sub_s_go_sub_ne ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP__B) }, { F (F_OP__C) }, { F (F_I16_GO) }, { F (F_DUMMY) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_sub_s_ssb ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8e00000, { { F (F_OPM) }, { F (F_OP__B) }, { F (F_OP__C) }, { F (F_U5) }, { F (F_DUMMY) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_mov_L_u6_ ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_U6) }, { F (F_OP_A) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_mov_L_r_r__RC ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_OP_C) }, { F (F_OP_A) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_mov_s_r_u7 ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8000000, { { F (F_OPM) }, { F (F_OP__B) }, { F (F_U8) }, { F (F_DUMMY) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_tst_L_s12_ ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_S12) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_tst_ccu6_ ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8ff0020, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_U6) }, { F (F_GO_CC_TYPE) }, { F (F_COND_Q) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_tst_L_u6_ ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_U6) }, { F (F_OP_A) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_tst_L_r_r__RC ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_OP_C) }, { F (F_OP_A) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_tst_cc__RC ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8ff0020, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_OP_C) }, { F (F_GO_CC_TYPE) }, { F (F_COND_Q) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_j_L_r_r___RC_noilink_ ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_OP_CJ) }, { F (F_OP_A) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_j_cc___RC_noilink_ ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8ff0020, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_OP_CJ) }, { F (F_GO_CC_TYPE) }, { F (F_COND_Q) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_j_L_r_r___RC_ilink_ ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_OP_CJ) }, { F (F_OP_A) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_j_cc___RC_ilink_ ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8ff0020, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_OP_CJ) }, { F (F_GO_CC_TYPE) }, { F (F_COND_Q) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_j_L_s12_ ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_S12) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_j_ccu6_ ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8ff0020, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_U6) }, { F (F_GO_CC_TYPE) }, { F (F_COND_Q) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_j_L_u6_ ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_U6) }, { F (F_OP_A) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_j_s__S ATTRIBUTE_UNUSED = {
+ 32, 32, 0xffff0000, { { F (F_OPM) }, { F (F_OP__B) }, { F (F_OP__C) }, { F (F_I16_GO) }, { F (F_DUMMY) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_j_L_r_r_d___RC_ ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_OP_C) }, { F (F_OP_A) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_j_cc_d___RC_ ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8ff0020, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_OP_C) }, { F (F_GO_CC_TYPE) }, { F (F_COND_Q) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_lp_L_s12_ ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_S12X2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_lpcc_ccu6 ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8ff0020, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_U6X2) }, { F (F_GO_CC_TYPE) }, { F (F_COND_Q) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_lr_L_r_r___RC_ ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_OP_C) }, { F (F_OP_A) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_lr_L_s12_ ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_S12) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_lr_L_u6_ ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_U6) }, { F (F_OP_A) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_asl_L_r_r__RC ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8ff003f, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_OP_C) }, { F (F_OP_A) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_asl_L_u6_ ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8ff003f, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_U6) }, { F (F_OP_A) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ex_L_r_r__RC ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8ff003f, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_OP_C) }, { F (F_OP_A) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ex_L_u6_ ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8ff003f, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_U6) }, { F (F_OP_A) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_swi ATTRIBUTE_UNUSED = {
+ 32, 32, 0xffff7fff, { { F (F_OPM) }, { F (F_OP__B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_B_5_3) }, { F (F_OP_C) }, { F (F_OP_A) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_trap_s ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf81f0000, { { F (F_OPM) }, { F (F_TRAPNUM) }, { F (F_I16_GO) }, { F (F_DUMMY) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_brk_s ATTRIBUTE_UNUSED = {
+ 32, 32, 0xffff0000, { { F (F_OPM) }, { F (F_TRAPNUM) }, { F (F_I16_GO) }, { F (F_DUMMY) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_divaw_ccu6__RA_ ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8ff0020, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_U6) }, { F (F_GO_CC_TYPE) }, { F (F_COND_Q) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_divaw_L_u6__RA_ ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_U6) }, { F (F_OP_A) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_divaw_L_r_r__RA__RC ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_OP_C) }, { F (F_OP_A) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_divaw_cc__RA__RC ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8ff0020, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_OP_C) }, { F (F_GO_CC_TYPE) }, { F (F_COND_Q) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_pop_s_b ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP__B) }, { F (F_OP__C) }, { F (F_U5) }, { F (F_DUMMY) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_pop_s_blink ATTRIBUTE_UNUSED = {
+ 32, 32, 0xffff0000, { { F (F_OPM) }, { F (F_OP__B) }, { F (F_OP__C) }, { F (F_U5) }, { F (F_DUMMY) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_current_loop_end ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf8ff003f, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_OP_C) }, { F (F_OP_A) }, { 0 } }
+};
+
+#undef F
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_INSN_##a)
+#else
+#define A(a) (1 << CGEN_INSN_/**/a)
+#endif
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define OPERAND(op) ARC_OPERAND_##op
+#else
+#define OPERAND(op) ARC_OPERAND_/**/op
+#endif
+#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
+#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
+
+/* The instruction table. */
+
+static const CGEN_OPCODE arc_cgen_insn_opcode_table[MAX_INSNS] =
{
- static int mach_type_map[] =
+ /* Special null first entry.
+ A `num' value of zero is thus invalid.
+ Also, the special `invalid' insn resides here. */
+ { { 0, 0, 0, 0 }, {{0}}, 0, {0}},
+/* b$i2cond $label10 */
{
- ARC_MACH_5,
- ARC_MACH_6,
- ARC_MACH_7,
- ARC_MACH_8
- };
- return mach_type_map[bfd_mach - bfd_mach_arc_5] | (big_p ? ARC_MACH_BIG : 0);
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (I2COND), ' ', OP (LABEL10), 0 } },
+ & ifmt_b_s, { 0xf0000000 }
+ },
+/* b$i3cond$_S $label7 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (I3COND), OP (_S), ' ', OP (LABEL7), 0 } },
+ & ifmt_bcc_s, { 0xf6000000 }
+ },
+/* br$RccS$_S $R_b,0,$label8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (RCCS), OP (_S), ' ', OP (R_B), ',', '0', ',', OP (LABEL8), 0 } },
+ & ifmt_brcc_s, { 0xe8000000 }
+ },
+/* b$Qcondb$_L $label21 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDB), OP (_L), ' ', OP (LABEL21), 0 } },
+ & ifmt_bcc_l, { 0x0 }
+ },
+/* b$Qcondb$_L.d $label21 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDB), OP (_L), '.', 'd', ' ', OP (LABEL21), 0 } },
+ & ifmt_bcc_l, { 0x20 }
+ },
+/* b$uncondb$_L $label25 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (UNCONDB), OP (_L), ' ', OP (LABEL25), 0 } },
+ & ifmt_b_l, { 0x10000 }
+ },
+/* b$uncondb$_L.d $label25 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (UNCONDB), OP (_L), '.', 'd', ' ', OP (LABEL25), 0 } },
+ & ifmt_b_l, { 0x10020 }
+ },
+/* b$Rcc $RB,$RC,$label9 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (RCC), ' ', OP (RB), ',', OP (RC), ',', OP (LABEL9), 0 } },
+ & ifmt_brcc_RC, { 0x8010000 }
+ },
+/* b$Rcc.d $RB,$RC,$label9 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (RCC), '.', 'd', ' ', OP (RB), ',', OP (RC), ',', OP (LABEL9), 0 } },
+ & ifmt_brcc_RC, { 0x8010020 }
+ },
+/* b$Rcc $RB,$U6,$label9 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (RCC), ' ', OP (RB), ',', OP (U6), ',', OP (LABEL9), 0 } },
+ & ifmt_brcc_U6, { 0x8010010 }
+ },
+/* b$Rcc.d $RB,$U6,$label9 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (RCC), '.', 'd', ' ', OP (RB), ',', OP (U6), ',', OP (LABEL9), 0 } },
+ & ifmt_brcc_U6, { 0x8010030 }
+ },
+/* bl$uncondj$_S $label13a */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (UNCONDJ), OP (_S), ' ', OP (LABEL13A), 0 } },
+ & ifmt_bl_s, { 0xf8000000 }
+ },
+/* bl$Qcondj$_L $label21 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDJ), OP (_L), ' ', OP (LABEL21), 0 } },
+ & ifmt_blcc, { 0x8000000 }
+ },
+/* bl$Qcondj$_L.d $label21 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDJ), OP (_L), '.', 'd', ' ', OP (LABEL21), 0 } },
+ & ifmt_blcc, { 0x8000020 }
+ },
+/* bl$uncondj$_L $label25a */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (UNCONDJ), OP (_L), ' ', OP (LABEL25A), 0 } },
+ & ifmt_bl, { 0x8020000 }
+ },
+/* bl$uncondj$_L.d $label25a */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (UNCONDJ), OP (_L), '.', 'd', ' ', OP (LABEL25A), 0 } },
+ & ifmt_bl, { 0x8020020 }
+ },
+/* ld$LDODi $RA,[$RB,$s9] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (LDODI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (S9), ']', 0 } },
+ & ifmt_ld_abs, { 0x10000000 }
+ },
+/* ld$_AW$LDODi $RA,[$RB,$s9] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_AW), OP (LDODI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (S9), ']', 0 } },
+ & ifmt_ld_abs, { 0x10000200 }
+ },
+/* ld.ab$LDODi $RA,[$RB,$s9] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (LDODI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (S9), ']', 0 } },
+ & ifmt_ld_abs, { 0x10000400 }
+ },
+/* ld.as$LDODi $RA,[$RB,$s9] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (LDODI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (S9), ']', 0 } },
+ & ifmt_ld_abs, { 0x10000600 }
+ },
+/* ld$LDRDi $RA,[$RB,$RC] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (LDRDI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (RC), ']', 0 } },
+ & ifmt_ld_abc, { 0x20300000 }
+ },
+/* ld$_AW$LDRDi $RA,[$RB,$RC] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_AW), OP (LDRDI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (RC), ']', 0 } },
+ & ifmt_ld_abc, { 0x20700000 }
+ },
+/* ld.ab$LDRDi $RA,[$RB,$RC] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (LDRDI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (RC), ']', 0 } },
+ & ifmt_ld_abc, { 0x20b00000 }
+ },
+/* ld.as$LDRDi $RA,[$RB,$RC] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (LDRDI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (RC), ']', 0 } },
+ & ifmt_ld_abc, { 0x20f00000 }
+ },
+/* ld$_S $R_a,[$R_b,$R_c] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_A), ',', '[', OP (R_B), ',', OP (R_C), ']', 0 } },
+ & ifmt_ld_s_abc, { 0x60000000 }
+ },
+/* ld$_S $R_c,[$R_b,$sc_u5_] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_C), ',', '[', OP (R_B), ',', OP (SC_U5_), ']', 0 } },
+ & ifmt_ld_s_abu, { 0x80000000 }
+ },
+/* ld$_S $R_b,[$SP,$u5x4] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', '[', OP (SP), ',', OP (U5X4), ']', 0 } },
+ & ifmt_ld_s_absp, { 0xc0000000 }
+ },
+/* ld$_S $R_b,[$GP,$sc_s9_] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', '[', OP (GP), ',', OP (SC_S9_), ']', 0 } },
+ & ifmt_ld_s_gprel, { 0xc8000000 }
+ },
+/* ld$_S $R_b,[$PCL,$u8x4] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', '[', OP (PCL), ',', OP (U8X4), ']', 0 } },
+ & ifmt_ld_s_pcrel, { 0xd0000000 }
+ },
+/* ldb$LDODi $RA,[$RB,$s9] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (LDODI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (S9), ']', 0 } },
+ & ifmt_ld_abs, { 0x10000080 }
+ },
+/* ldb$_AW$LDODi $RA,[$RB,$s9] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_AW), OP (LDODI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (S9), ']', 0 } },
+ & ifmt_ld_abs, { 0x10000280 }
+ },
+/* ldb.ab$LDODi $RA,[$RB,$s9] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (LDODI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (S9), ']', 0 } },
+ & ifmt_ld_abs, { 0x10000480 }
+ },
+/* ldb.as$LDODi $RA,[$RB,$s9] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (LDODI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (S9), ']', 0 } },
+ & ifmt_ld_abs, { 0x10000680 }
+ },
+/* ldb$LDRDi $RA,[$RB,$RC] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (LDRDI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (RC), ']', 0 } },
+ & ifmt_ld_abc, { 0x20320000 }
+ },
+/* ldb$_AW$LDRDi $RA,[$RB,$RC] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_AW), OP (LDRDI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (RC), ']', 0 } },
+ & ifmt_ld_abc, { 0x20720000 }
+ },
+/* ldb.ab$LDRDi $RA,[$RB,$RC] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (LDRDI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (RC), ']', 0 } },
+ & ifmt_ld_abc, { 0x20b20000 }
+ },
+/* ldb.as$LDRDi $RA,[$RB,$RC] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (LDRDI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (RC), ']', 0 } },
+ & ifmt_ld_abc, { 0x20f20000 }
+ },
+/* ldb$_S $R_a,[$R_b,$R_c] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_A), ',', '[', OP (R_B), ',', OP (R_C), ']', 0 } },
+ & ifmt_ld_s_abc, { 0x60080000 }
+ },
+/* ldb$_S $R_c,[$R_b,$sc_u5b] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_C), ',', '[', OP (R_B), ',', OP (SC_U5B), ']', 0 } },
+ & ifmt_ldb_s_abu, { 0x88000000 }
+ },
+/* ldb$_S $R_b,[$SP,$u5x4] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', '[', OP (SP), ',', OP (U5X4), ']', 0 } },
+ & ifmt_ld_s_absp, { 0xc0200000 }
+ },
+/* ldb$_S $R_b,[$GP,$sc_s9b] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', '[', OP (GP), ',', OP (SC_S9B), ']', 0 } },
+ & ifmt_ldb_s_gprel, { 0xca000000 }
+ },
+/* ldb.x$LDODi $RA,[$RB,$s9] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (LDODI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (S9), ']', 0 } },
+ & ifmt_ld_abs, { 0x100000c0 }
+ },
+/* ldb$_AW.x$LDODi $RA,[$RB,$s9] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_AW), '.', 'x', OP (LDODI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (S9), ']', 0 } },
+ & ifmt_ld_abs, { 0x100002c0 }
+ },
+/* ldb.ab.x$LDODi $RA,[$RB,$s9] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (LDODI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (S9), ']', 0 } },
+ & ifmt_ld_abs, { 0x100004c0 }
+ },
+/* ldb.as.x$LDODi $RA,[$RB,$s9] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (LDODI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (S9), ']', 0 } },
+ & ifmt_ld_abs, { 0x100006c0 }
+ },
+/* ldb.x$LDRDi $RA,[$RB,$RC] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (LDRDI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (RC), ']', 0 } },
+ & ifmt_ld_abc, { 0x20330000 }
+ },
+/* ldb$_AW.x$LDRDi $RA,[$RB,$RC] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_AW), '.', 'x', OP (LDRDI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (RC), ']', 0 } },
+ & ifmt_ld_abc, { 0x20730000 }
+ },
+/* ldb.ab.x$LDRDi $RA,[$RB,$RC] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (LDRDI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (RC), ']', 0 } },
+ & ifmt_ld_abc, { 0x20b30000 }
+ },
+/* ldb.as.x$LDRDi $RA,[$RB,$RC] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (LDRDI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (RC), ']', 0 } },
+ & ifmt_ld_abc, { 0x20f30000 }
+ },
+/* ldw$LDODi $RA,[$RB,$s9] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (LDODI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (S9), ']', 0 } },
+ & ifmt_ld_abs, { 0x10000100 }
+ },
+/* ldw$_AW$LDODi $RA,[$RB,$s9] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_AW), OP (LDODI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (S9), ']', 0 } },
+ & ifmt_ld_abs, { 0x10000300 }
+ },
+/* ldw.ab$LDODi $RA,[$RB,$s9] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (LDODI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (S9), ']', 0 } },
+ & ifmt_ld_abs, { 0x10000500 }
+ },
+/* ldw.as$LDODi $RA,[$RB,$s9] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (LDODI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (S9), ']', 0 } },
+ & ifmt_ld_abs, { 0x10000700 }
+ },
+/* ldw$LDRDi $RA,[$RB,$RC] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (LDRDI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (RC), ']', 0 } },
+ & ifmt_ld_abc, { 0x20340000 }
+ },
+/* ldw$_AW$LDRDi $RA,[$RB,$RC] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_AW), OP (LDRDI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (RC), ']', 0 } },
+ & ifmt_ld_abc, { 0x20740000 }
+ },
+/* ldw.ab$LDRDi $RA,[$RB,$RC] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (LDRDI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (RC), ']', 0 } },
+ & ifmt_ld_abc, { 0x20b40000 }
+ },
+/* ldw.as$LDRDi $RA,[$RB,$RC] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (LDRDI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (RC), ']', 0 } },
+ & ifmt_ld_abc, { 0x20f40000 }
+ },
+/* ldw$_S $R_a,[$R_b,$R_c] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_A), ',', '[', OP (R_B), ',', OP (R_C), ']', 0 } },
+ & ifmt_ld_s_abc, { 0x60100000 }
+ },
+/* ldw$_S $R_c,[$R_b,$sc_u5w] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_C), ',', '[', OP (R_B), ',', OP (SC_U5W), ']', 0 } },
+ & ifmt_ldw_s_abu, { 0x90000000 }
+ },
+/* ldw$_S $R_b,[$GP,$sc_s9w] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', '[', OP (GP), ',', OP (SC_S9W), ']', 0 } },
+ & ifmt_ldw_s_gprel, { 0xcc000000 }
+ },
+/* ldw.x$LDODi $RA,[$RB,$s9] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (LDODI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (S9), ']', 0 } },
+ & ifmt_ld_abs, { 0x10000140 }
+ },
+/* ldw$_AW.x$LDODi $RA,[$RB,$s9] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_AW), '.', 'x', OP (LDODI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (S9), ']', 0 } },
+ & ifmt_ld_abs, { 0x10000340 }
+ },
+/* ldw.ab.x$LDODi $RA,[$RB,$s9] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (LDODI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (S9), ']', 0 } },
+ & ifmt_ld_abs, { 0x10000540 }
+ },
+/* ldw.as.x$LDODi $RA,[$RB,$s9] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (LDODI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (S9), ']', 0 } },
+ & ifmt_ld_abs, { 0x10000740 }
+ },
+/* ldw.x$LDRDi $RA,[$RB,$RC] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (LDRDI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (RC), ']', 0 } },
+ & ifmt_ld_abc, { 0x20350000 }
+ },
+/* ldw$_AW.x$LDRDi $RA,[$RB,$RC] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_AW), '.', 'x', OP (LDRDI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (RC), ']', 0 } },
+ & ifmt_ld_abc, { 0x20750000 }
+ },
+/* ldw.ab.x$LDRDi $RA,[$RB,$RC] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (LDRDI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (RC), ']', 0 } },
+ & ifmt_ld_abc, { 0x20b50000 }
+ },
+/* ldw.as.x$LDRDi $RA,[$RB,$RC] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (LDRDI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (RC), ']', 0 } },
+ & ifmt_ld_abc, { 0x20f50000 }
+ },
+/* ldw$_S.x $R_c,[$R_b,$sc_u5w] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), '.', 'x', ' ', OP (R_C), ',', '[', OP (R_B), ',', OP (SC_U5W), ']', 0 } },
+ & ifmt_ldw_s_abu, { 0x98000000 }
+ },
+/* st$STODi $RC,[$RB,$s9] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (STODI), ' ', OP (RC), ',', '[', OP (RB), ',', OP (S9), ']', 0 } },
+ & ifmt_st_abs, { 0x18000000 }
+ },
+/* st$_AW$STODi $RC,[$RB,$s9] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_AW), OP (STODI), ' ', OP (RC), ',', '[', OP (RB), ',', OP (S9), ']', 0 } },
+ & ifmt_st_abs, { 0x18000008 }
+ },
+/* st.ab$STODi $RC,[$RB,$s9] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (STODI), ' ', OP (RC), ',', '[', OP (RB), ',', OP (S9), ']', 0 } },
+ & ifmt_st_abs, { 0x18000010 }
+ },
+/* st.as$STODi $RC,[$RB,$s9] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (STODI), ' ', OP (RC), ',', '[', OP (RB), ',', OP (S9), ']', 0 } },
+ & ifmt_st_abs, { 0x18000018 }
+ },
+/* st$_S $R_c,[$R_b,$sc_u5_] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_C), ',', '[', OP (R_B), ',', OP (SC_U5_), ']', 0 } },
+ & ifmt_ld_s_abu, { 0xa0000000 }
+ },
+/* st$_S $R_b,[$SP,$u5x4] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', '[', OP (SP), ',', OP (U5X4), ']', 0 } },
+ & ifmt_ld_s_absp, { 0xc0400000 }
+ },
+/* stb$STODi $RC,[$RB,$s9] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (STODI), ' ', OP (RC), ',', '[', OP (RB), ',', OP (S9), ']', 0 } },
+ & ifmt_st_abs, { 0x18000002 }
+ },
+/* stb$_AW$STODi $RC,[$RB,$s9] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_AW), OP (STODI), ' ', OP (RC), ',', '[', OP (RB), ',', OP (S9), ']', 0 } },
+ & ifmt_st_abs, { 0x1800000a }
+ },
+/* stb.ab$STODi $RC,[$RB,$s9] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (STODI), ' ', OP (RC), ',', '[', OP (RB), ',', OP (S9), ']', 0 } },
+ & ifmt_st_abs, { 0x18000012 }
+ },
+/* stb.as$STODi $RC,[$RB,$s9] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (STODI), ' ', OP (RC), ',', '[', OP (RB), ',', OP (S9), ']', 0 } },
+ & ifmt_st_abs, { 0x1800001a }
+ },
+/* stb$_S $R_c,[$R_b,$sc_u5b] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_C), ',', '[', OP (R_B), ',', OP (SC_U5B), ']', 0 } },
+ & ifmt_ldb_s_abu, { 0xa8000000 }
+ },
+/* stb$_S $R_b,[$SP,$u5x4] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', '[', OP (SP), ',', OP (U5X4), ']', 0 } },
+ & ifmt_ld_s_absp, { 0xc0600000 }
+ },
+/* stw$STODi $RC,[$RB,$s9] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (STODI), ' ', OP (RC), ',', '[', OP (RB), ',', OP (S9), ']', 0 } },
+ & ifmt_st_abs, { 0x18000004 }
+ },
+/* stw$_AW$STODi $RC,[$RB,$s9] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_AW), OP (STODI), ' ', OP (RC), ',', '[', OP (RB), ',', OP (S9), ']', 0 } },
+ & ifmt_st_abs, { 0x1800000c }
+ },
+/* stw.ab$STODi $RC,[$RB,$s9] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (STODI), ' ', OP (RC), ',', '[', OP (RB), ',', OP (S9), ']', 0 } },
+ & ifmt_st_abs, { 0x18000014 }
+ },
+/* stw.as$STODi $RC,[$RB,$s9] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (STODI), ' ', OP (RC), ',', '[', OP (RB), ',', OP (S9), ']', 0 } },
+ & ifmt_st_abs, { 0x1800001c }
+ },
+/* stw$_S $R_c,[$R_b,$sc_u5w] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_C), ',', '[', OP (R_B), ',', OP (SC_U5W), ']', 0 } },
+ & ifmt_ldw_s_abu, { 0xb0000000 }
+ },
+/* add$_L$F $RB,$RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_add_L_s12__RA_, { 0x20800000 }
+ },
+/* add$Qcondi$F $RB,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_ccu6__RA_, { 0x20c00020 }
+ },
+/* add$_L$F $RA,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_L_u6__RA_, { 0x20400000 }
+ },
+/* add$_L$F $RA,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_L_r_r__RA__RC, { 0x20000000 }
+ },
+/* add$Qcondi$F $RB,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_cc__RA__RC, { 0x20c00000 }
+ },
+/* add$_S $R_a,$R_b,$R_c */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_A), ',', OP (R_B), ',', OP (R_C), 0 } },
+ & ifmt_ld_s_abc, { 0x60180000 }
+ },
+/* add$_S $R_c,$R_b,$u3 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_C), ',', OP (R_B), ',', OP (U3), 0 } },
+ & ifmt_add_s_cbu3, { 0x68000000 }
+ },
+/* add$_S $R_b,$R_b,$Rh */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (RH), 0 } },
+ & ifmt_add_s_mcah, { 0x70000000 }
+ },
+/* add$_S $R_b,$SP,$u5x4 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (SP), ',', OP (U5X4), 0 } },
+ & ifmt_ld_s_absp, { 0xc0800000 }
+ },
+/* add$_S $SP,$SP,$u5x4 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (SP), ',', OP (SP), ',', OP (U5X4), 0 } },
+ & ifmt_add_s_asspsp, { 0xc0a00000 }
+ },
+/* add$_S $R0,$GP,$s9x4 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R0), ',', OP (GP), ',', OP (S9X4), 0 } },
+ & ifmt_add_s_gp, { 0xce000000 }
+ },
+/* add$_S $R_b,$R_b,$u7 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (U7), 0 } },
+ & ifmt_add_s_r_u7, { 0xe0000000 }
+ },
+/* adc$_L$F $RB,$RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_add_L_s12__RA_, { 0x20810000 }
+ },
+/* adc$Qcondi$F $RB,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_ccu6__RA_, { 0x20c10020 }
+ },
+/* adc$_L$F $RA,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_L_u6__RA_, { 0x20410000 }
+ },
+/* adc$_L$F $RA,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_L_r_r__RA__RC, { 0x20010000 }
+ },
+/* adc$Qcondi$F $RB,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_cc__RA__RC, { 0x20c10000 }
+ },
+/* sub$_L$F $RB,$RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_add_L_s12__RA_, { 0x20820000 }
+ },
+/* sub$Qcondi$F $RB,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_ccu6__RA_, { 0x20c20020 }
+ },
+/* sub$_L$F $RA,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_L_u6__RA_, { 0x20420000 }
+ },
+/* sub$_L$F $RA,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_L_r_r__RA__RC, { 0x20020000 }
+ },
+/* sub$Qcondi$F $RB,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_cc__RA__RC, { 0x20c20000 }
+ },
+/* sub$_S $R_c,$R_b,$u3 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_C), ',', OP (R_B), ',', OP (U3), 0 } },
+ & ifmt_add_s_cbu3, { 0x68080000 }
+ },
+/* sub$_S $R_b,$R_b,$R_c */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (R_C), 0 } },
+ & ifmt_I16_GO_SUB_s_go, { 0x78020000 }
+ },
+/* sub$_S $NE$R_b,$R_b,$R_b */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (NE), OP (R_B), ',', OP (R_B), ',', OP (R_B), 0 } },
+ & ifmt_sub_s_go_sub_ne, { 0x78c00000 }
+ },
+/* sub$_S $R_b,$R_b,$u5 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (U5), 0 } },
+ & ifmt_sub_s_ssb, { 0xb8600000 }
+ },
+/* sub$_S $SP,$SP,$u5x4 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (SP), ',', OP (SP), ',', OP (U5X4), 0 } },
+ & ifmt_add_s_asspsp, { 0xc1a00000 }
+ },
+/* sbc$_L$F $RB,$RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_add_L_s12__RA_, { 0x20830000 }
+ },
+/* sbc$Qcondi$F $RB,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_ccu6__RA_, { 0x20c30020 }
+ },
+/* sbc$_L$F $RA,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_L_u6__RA_, { 0x20430000 }
+ },
+/* sbc$_L$F $RA,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_L_r_r__RA__RC, { 0x20030000 }
+ },
+/* sbc$Qcondi$F $RB,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_cc__RA__RC, { 0x20c30000 }
+ },
+/* and$_L$F $RB,$RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_add_L_s12__RA_, { 0x20840000 }
+ },
+/* and$Qcondi$F $RB,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_ccu6__RA_, { 0x20c40020 }
+ },
+/* and$_L$F $RA,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_L_u6__RA_, { 0x20440000 }
+ },
+/* and$_L$F $RA,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_L_r_r__RA__RC, { 0x20040000 }
+ },
+/* and$Qcondi$F $RB,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_cc__RA__RC, { 0x20c40000 }
+ },
+/* and$_S $R_b,$R_b,$R_c */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (R_C), 0 } },
+ & ifmt_I16_GO_SUB_s_go, { 0x78040000 }
+ },
+/* or$_L$F $RB,$RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_add_L_s12__RA_, { 0x20850000 }
+ },
+/* or$Qcondi$F $RB,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_ccu6__RA_, { 0x20c50020 }
+ },
+/* or$_L$F $RA,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_L_u6__RA_, { 0x20450000 }
+ },
+/* or$_L$F $RA,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_L_r_r__RA__RC, { 0x20050000 }
+ },
+/* or$Qcondi$F $RB,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_cc__RA__RC, { 0x20c50000 }
+ },
+/* or$_S $R_b,$R_b,$R_c */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (R_C), 0 } },
+ & ifmt_I16_GO_SUB_s_go, { 0x78050000 }
+ },
+/* bic$_L$F $RB,$RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_add_L_s12__RA_, { 0x20860000 }
+ },
+/* bic$Qcondi$F $RB,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_ccu6__RA_, { 0x20c60020 }
+ },
+/* bic$_L$F $RA,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_L_u6__RA_, { 0x20460000 }
+ },
+/* bic$_L$F $RA,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_L_r_r__RA__RC, { 0x20060000 }
+ },
+/* bic$Qcondi$F $RB,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_cc__RA__RC, { 0x20c60000 }
+ },
+/* bic$_S $R_b,$R_b,$R_c */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (R_C), 0 } },
+ & ifmt_I16_GO_SUB_s_go, { 0x78060000 }
+ },
+/* xor$_L$F $RB,$RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_add_L_s12__RA_, { 0x20870000 }
+ },
+/* xor$Qcondi$F $RB,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_ccu6__RA_, { 0x20c70020 }
+ },
+/* xor$_L$F $RA,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_L_u6__RA_, { 0x20470000 }
+ },
+/* xor$_L$F $RA,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_L_r_r__RA__RC, { 0x20070000 }
+ },
+/* xor$Qcondi$F $RB,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_cc__RA__RC, { 0x20c70000 }
+ },
+/* xor$_S $R_b,$R_b,$R_c */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (R_C), 0 } },
+ & ifmt_I16_GO_SUB_s_go, { 0x78070000 }
+ },
+/* max$_L$F $RB,$RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_add_L_s12__RA_, { 0x20880000 }
+ },
+/* max$Qcondi$F $RB,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_ccu6__RA_, { 0x20c80020 }
+ },
+/* max$_L$F $RA,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_L_u6__RA_, { 0x20480000 }
+ },
+/* max$_L$F $RA,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_L_r_r__RA__RC, { 0x20080000 }
+ },
+/* max$Qcondi$F $RB,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_cc__RA__RC, { 0x20c80000 }
+ },
+/* min$_L$F $RB,$RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_add_L_s12__RA_, { 0x20890000 }
+ },
+/* min$Qcondi$F $RB,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_ccu6__RA_, { 0x20c90020 }
+ },
+/* min$_L$F $RA,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_L_u6__RA_, { 0x20490000 }
+ },
+/* min$_L$F $RA,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_L_r_r__RA__RC, { 0x20090000 }
+ },
+/* min$Qcondi$F $RB,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_cc__RA__RC, { 0x20c90000 }
+ },
+/* mov$_L$F $RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_add_L_s12__RA_, { 0x208a0000 }
+ },
+/* mov$Qcondi$F $RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_ccu6__RA_, { 0x20ca0020 }
+ },
+/* mov$_L$F $RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_mov_L_u6_, { 0x204a0000 }
+ },
+/* mov$_L$F $RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_mov_L_r_r__RC, { 0x200a0000 }
+ },
+/* mov$Qcondi$F $RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_cc__RA__RC, { 0x20ca0000 }
+ },
+/* mov$_S $R_b,$Rh */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (RH), 0 } },
+ & ifmt_add_s_mcah, { 0x70080000 }
+ },
+/* mov$_S $Rh,$R_b */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (RH), ',', OP (R_B), 0 } },
+ & ifmt_add_s_mcah, { 0x70180000 }
+ },
+/* mov$_S $R_b,$u7 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (U7), 0 } },
+ & ifmt_mov_s_r_u7, { 0xd8000000 }
+ },
+/* tst$_L$F1 $RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F1), ' ', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_tst_L_s12_, { 0x208b0000 }
+ },
+/* tst$Qcondi$F1 $RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F1), ' ', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_tst_ccu6_, { 0x20cb0020 }
+ },
+/* tst$_L$F1 $RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F1), ' ', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_tst_L_u6_, { 0x204b0000 }
+ },
+/* tst$_L$F1 $RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F1), ' ', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_tst_L_r_r__RC, { 0x200b0000 }
+ },
+/* tst$Qcondi$F1 $RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F1), ' ', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_tst_cc__RC, { 0x20cb0000 }
+ },
+/* tst$_S $R_b,$R_c */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_C), 0 } },
+ & ifmt_I16_GO_SUB_s_go, { 0x780b0000 }
+ },
+/* cmp$_L$F1 $RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F1), ' ', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_tst_L_s12_, { 0x208c0000 }
+ },
+/* cmp$Qcondi$F1 $RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F1), ' ', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_tst_ccu6_, { 0x20cc0020 }
+ },
+/* cmp$_L$F1 $RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F1), ' ', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_tst_L_u6_, { 0x204c0000 }
+ },
+/* cmp$_L$F1 $RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F1), ' ', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_tst_L_r_r__RC, { 0x200c0000 }
+ },
+/* cmp$Qcondi$F1 $RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F1), ' ', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_tst_cc__RC, { 0x20cc0000 }
+ },
+/* cmp$_S $R_b,$Rh */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (RH), 0 } },
+ & ifmt_add_s_mcah, { 0x70100000 }
+ },
+/* cmp$_S $R_b,$u7 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (U7), 0 } },
+ & ifmt_add_s_r_u7, { 0xe0800000 }
+ },
+/* rcmp$_L$F1 $RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F1), ' ', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_tst_L_s12_, { 0x208d0000 }
+ },
+/* rcmp$Qcondi$F1 $RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F1), ' ', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_tst_ccu6_, { 0x20cd0020 }
+ },
+/* rcmp$_L$F1 $RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F1), ' ', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_tst_L_u6_, { 0x204d0000 }
+ },
+/* rcmp$_L$F1 $RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F1), ' ', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_tst_L_r_r__RC, { 0x200d0000 }
+ },
+/* rcmp$Qcondi$F1 $RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F1), ' ', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_tst_cc__RC, { 0x20cd0000 }
+ },
+/* rsub$_L$F $RB,$RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_add_L_s12__RA_, { 0x208e0000 }
+ },
+/* rsub$Qcondi$F $RB,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_ccu6__RA_, { 0x20ce0020 }
+ },
+/* rsub$_L$F $RA,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_L_u6__RA_, { 0x204e0000 }
+ },
+/* rsub$_L$F $RA,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_L_r_r__RA__RC, { 0x200e0000 }
+ },
+/* rsub$Qcondi$F $RB,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_cc__RA__RC, { 0x20ce0000 }
+ },
+/* bset$_L$F $RB,$RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_add_L_s12__RA_, { 0x208f0000 }
+ },
+/* bset$Qcondi$F $RB,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_ccu6__RA_, { 0x20cf0020 }
+ },
+/* bset$_L$F $RA,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_L_u6__RA_, { 0x204f0000 }
+ },
+/* bset$_L$F $RA,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_L_r_r__RA__RC, { 0x200f0000 }
+ },
+/* bset$Qcondi$F $RB,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_cc__RA__RC, { 0x20cf0000 }
+ },
+/* bset$_S $R_b,$R_b,$u5 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (U5), 0 } },
+ & ifmt_sub_s_ssb, { 0xb8800000 }
+ },
+/* bclr$_L$F $RB,$RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_add_L_s12__RA_, { 0x20900000 }
+ },
+/* bclr$Qcondi$F $RB,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_ccu6__RA_, { 0x20d00020 }
+ },
+/* bclr$_L$F $RA,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_L_u6__RA_, { 0x20500000 }
+ },
+/* bclr$_L$F $RA,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_L_r_r__RA__RC, { 0x20100000 }
+ },
+/* bclr$Qcondi$F $RB,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_cc__RA__RC, { 0x20d00000 }
+ },
+/* bclr$_S $R_b,$R_b,$u5 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (U5), 0 } },
+ & ifmt_sub_s_ssb, { 0xb8a00000 }
+ },
+/* btst$_L$F1 $RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F1), ' ', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_tst_L_s12_, { 0x20910000 }
+ },
+/* btst$Qcondi$F1 $RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F1), ' ', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_tst_ccu6_, { 0x20d10020 }
+ },
+/* btst$_L$F1 $RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F1), ' ', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_tst_L_u6_, { 0x20510000 }
+ },
+/* btst$_L$F1 $RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F1), ' ', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_tst_L_r_r__RC, { 0x20110000 }
+ },
+/* btst$Qcondi$F1 $RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F1), ' ', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_tst_cc__RC, { 0x20d10000 }
+ },
+/* btst$_S $R_b,$u5 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (U5), 0 } },
+ & ifmt_sub_s_ssb, { 0xb8e00000 }
+ },
+/* bxor$_L$F $RB,$RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_add_L_s12__RA_, { 0x20920000 }
+ },
+/* bxor$Qcondi$F $RB,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_ccu6__RA_, { 0x20d20020 }
+ },
+/* bxor$_L$F $RA,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_L_u6__RA_, { 0x20520000 }
+ },
+/* bxor$_L$F $RA,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_L_r_r__RA__RC, { 0x20120000 }
+ },
+/* bxor$Qcondi$F $RB,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_cc__RA__RC, { 0x20d20000 }
+ },
+/* bmsk$_L$F $RB,$RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_add_L_s12__RA_, { 0x20930000 }
+ },
+/* bmsk$Qcondi$F $RB,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_ccu6__RA_, { 0x20d30020 }
+ },
+/* bmsk$_L$F $RA,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_L_u6__RA_, { 0x20530000 }
+ },
+/* bmsk$_L$F $RA,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_L_r_r__RA__RC, { 0x20130000 }
+ },
+/* bmsk$Qcondi$F $RB,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_cc__RA__RC, { 0x20d30000 }
+ },
+/* bmsk$_S $R_b,$R_b,$u5 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (U5), 0 } },
+ & ifmt_sub_s_ssb, { 0xb8c00000 }
+ },
+/* add1$_L$F $RB,$RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_add_L_s12__RA_, { 0x20940000 }
+ },
+/* add1$Qcondi$F $RB,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_ccu6__RA_, { 0x20d40020 }
+ },
+/* add1$_L$F $RA,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_L_u6__RA_, { 0x20540000 }
+ },
+/* add1$_L$F $RA,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_L_r_r__RA__RC, { 0x20140000 }
+ },
+/* add1$Qcondi$F $RB,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_cc__RA__RC, { 0x20d40000 }
+ },
+/* add1$_S $R_b,$R_b,$R_c */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (R_C), 0 } },
+ & ifmt_I16_GO_SUB_s_go, { 0x78140000 }
+ },
+/* add2$_L$F $RB,$RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_add_L_s12__RA_, { 0x20950000 }
+ },
+/* add2$Qcondi$F $RB,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_ccu6__RA_, { 0x20d50020 }
+ },
+/* add2$_L$F $RA,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_L_u6__RA_, { 0x20550000 }
+ },
+/* add2$_L$F $RA,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_L_r_r__RA__RC, { 0x20150000 }
+ },
+/* add2$Qcondi$F $RB,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_cc__RA__RC, { 0x20d50000 }
+ },
+/* add2$_S $R_b,$R_b,$R_c */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (R_C), 0 } },
+ & ifmt_I16_GO_SUB_s_go, { 0x78150000 }
+ },
+/* add3$_L$F $RB,$RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_add_L_s12__RA_, { 0x20960000 }
+ },
+/* add3$Qcondi$F $RB,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_ccu6__RA_, { 0x20d60020 }
+ },
+/* add3$_L$F $RA,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_L_u6__RA_, { 0x20560000 }
+ },
+/* add3$_L$F $RA,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_L_r_r__RA__RC, { 0x20160000 }
+ },
+/* add3$Qcondi$F $RB,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_cc__RA__RC, { 0x20d60000 }
+ },
+/* add3$_S $R_b,$R_b,$R_c */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (R_C), 0 } },
+ & ifmt_I16_GO_SUB_s_go, { 0x78160000 }
+ },
+/* sub1$_L$F $RB,$RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_add_L_s12__RA_, { 0x20970000 }
+ },
+/* sub1$Qcondi$F $RB,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_ccu6__RA_, { 0x20d70020 }
+ },
+/* sub1$_L$F $RA,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_L_u6__RA_, { 0x20570000 }
+ },
+/* sub1$_L$F $RA,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_L_r_r__RA__RC, { 0x20170000 }
+ },
+/* sub1$Qcondi$F $RB,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_cc__RA__RC, { 0x20d70000 }
+ },
+/* sub2$_L$F $RB,$RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_add_L_s12__RA_, { 0x20980000 }
+ },
+/* sub2$Qcondi$F $RB,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_ccu6__RA_, { 0x20d80020 }
+ },
+/* sub2$_L$F $RA,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_L_u6__RA_, { 0x20580000 }
+ },
+/* sub2$_L$F $RA,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_L_r_r__RA__RC, { 0x20180000 }
+ },
+/* sub2$Qcondi$F $RB,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_cc__RA__RC, { 0x20d80000 }
+ },
+/* sub3$_L$F $RB,$RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_add_L_s12__RA_, { 0x20990000 }
+ },
+/* sub3$Qcondi$F $RB,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_ccu6__RA_, { 0x20d90020 }
+ },
+/* sub3$_L$F $RA,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_L_u6__RA_, { 0x20590000 }
+ },
+/* sub3$_L$F $RA,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_L_r_r__RA__RC, { 0x20190000 }
+ },
+/* sub3$Qcondi$F $RB,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_cc__RA__RC, { 0x20d90000 }
+ },
+/* mpy$_L$F $RB,$RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_add_L_s12__RA_, { 0x209a0000 }
+ },
+/* mpy$Qcondi$F $RB,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_ccu6__RA_, { 0x20da0020 }
+ },
+/* mpy$_L$F $RA,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_L_u6__RA_, { 0x205a0000 }
+ },
+/* mpy$_L$F $RA,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_L_r_r__RA__RC, { 0x201a0000 }
+ },
+/* mpy$Qcondi$F $RB,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_cc__RA__RC, { 0x20da0000 }
+ },
+/* mpyh$_L$F $RB,$RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_add_L_s12__RA_, { 0x209b0000 }
+ },
+/* mpyh$Qcondi$F $RB,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_ccu6__RA_, { 0x20db0020 }
+ },
+/* mpyh$_L$F $RA,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_L_u6__RA_, { 0x205b0000 }
+ },
+/* mpyh$_L$F $RA,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_L_r_r__RA__RC, { 0x201b0000 }
+ },
+/* mpyh$Qcondi$F $RB,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_cc__RA__RC, { 0x20db0000 }
+ },
+/* mpyhu$_L$F $RB,$RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_add_L_s12__RA_, { 0x209c0000 }
+ },
+/* mpyhu$Qcondi$F $RB,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_ccu6__RA_, { 0x20dc0020 }
+ },
+/* mpyhu$_L$F $RA,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_L_u6__RA_, { 0x205c0000 }
+ },
+/* mpyhu$_L$F $RA,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_L_r_r__RA__RC, { 0x201c0000 }
+ },
+/* mpyhu$Qcondi$F $RB,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_cc__RA__RC, { 0x20dc0000 }
+ },
+/* mpyu$_L$F $RB,$RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_add_L_s12__RA_, { 0x209d0000 }
+ },
+/* mpyu$Qcondi$F $RB,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_ccu6__RA_, { 0x20dd0020 }
+ },
+/* mpyu$_L$F $RA,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_L_u6__RA_, { 0x205d0000 }
+ },
+/* mpyu$_L$F $RA,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_L_r_r__RA__RC, { 0x201d0000 }
+ },
+/* mpyu$Qcondi$F $RB,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_cc__RA__RC, { 0x20dd0000 }
+ },
+/* j$_L$F0 [$RC_noilink] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F0), ' ', '[', OP (RC_NOILINK), ']', 0 } },
+ & ifmt_j_L_r_r___RC_noilink_, { 0x20200000 }
+ },
+/* j$Qcondi$F0 [$RC_noilink] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F0), ' ', '[', OP (RC_NOILINK), ']', 0 } },
+ & ifmt_j_cc___RC_noilink_, { 0x20e00000 }
+ },
+/* j$_L$F1F [$RC_ilink] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F1F), ' ', '[', OP (RC_ILINK), ']', 0 } },
+ & ifmt_j_L_r_r___RC_ilink_, { 0x20200000 }
+ },
+/* j$Qcondi$F1F [$RC_ilink] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F1F), ' ', '[', OP (RC_ILINK), ']', 0 } },
+ & ifmt_j_cc___RC_ilink_, { 0x20e00000 }
+ },
+/* j$_L$F0 $s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F0), ' ', OP (S12), 0 } },
+ & ifmt_j_L_s12_, { 0x20a00000 }
+ },
+/* j$Qcondi$F0 $U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F0), ' ', OP (U6), 0 } },
+ & ifmt_j_ccu6_, { 0x20e00020 }
+ },
+/* j$_L$F0 $U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F0), ' ', OP (U6), 0 } },
+ & ifmt_j_L_u6_, { 0x20600000 }
+ },
+/* j$_S [$R_b] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', '[', OP (R_B), ']', 0 } },
+ & ifmt_sub_s_go_sub_ne, { 0x78000000 }
+ },
+/* j$_S [$R31] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', '[', OP (R31), ']', 0 } },
+ & ifmt_j_s__S, { 0x7ee00000 }
+ },
+/* jeq$_S [$R31] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', '[', OP (R31), ']', 0 } },
+ & ifmt_j_s__S, { 0x7ce00000 }
+ },
+/* jne$_S [$R31] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', '[', OP (R31), ']', 0 } },
+ & ifmt_j_s__S, { 0x7de00000 }
+ },
+/* j$_L$F0.d $s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F0), '.', 'd', ' ', OP (S12), 0 } },
+ & ifmt_j_L_s12_, { 0x20a10000 }
+ },
+/* j$Qcondi$F0.d $U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F0), '.', 'd', ' ', OP (U6), 0 } },
+ & ifmt_j_ccu6_, { 0x20e10020 }
+ },
+/* j$_L$F0.d $U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F0), '.', 'd', ' ', OP (U6), 0 } },
+ & ifmt_j_L_u6_, { 0x20610000 }
+ },
+/* j$_L$F0.d [$RC] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F0), '.', 'd', ' ', '[', OP (RC), ']', 0 } },
+ & ifmt_j_L_r_r_d___RC_, { 0x20210000 }
+ },
+/* j$Qcondi$F0.d [$RC] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F0), '.', 'd', ' ', '[', OP (RC), ']', 0 } },
+ & ifmt_j_cc_d___RC_, { 0x20e10000 }
+ },
+/* j$_S.d [$R_b] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), '.', 'd', ' ', '[', OP (R_B), ']', 0 } },
+ & ifmt_sub_s_go_sub_ne, { 0x78200000 }
+ },
+/* j$_S.d [$R31] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), '.', 'd', ' ', '[', OP (R31), ']', 0 } },
+ & ifmt_j_s__S, { 0x7fe00000 }
+ },
+/* jl$_L$F0 $s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F0), ' ', OP (S12), 0 } },
+ & ifmt_j_L_s12_, { 0x20a20000 }
+ },
+/* jl$Qcondi$F0 $U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F0), ' ', OP (U6), 0 } },
+ & ifmt_j_ccu6_, { 0x20e20020 }
+ },
+/* jl$_L$F0 $U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F0), ' ', OP (U6), 0 } },
+ & ifmt_j_L_u6_, { 0x20620000 }
+ },
+/* jl$_S [$R_b] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', '[', OP (R_B), ']', 0 } },
+ & ifmt_sub_s_go_sub_ne, { 0x78400000 }
+ },
+/* jl$_L$F0 [$RC_noilink] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F0), ' ', '[', OP (RC_NOILINK), ']', 0 } },
+ & ifmt_j_L_r_r___RC_noilink_, { 0x20220000 }
+ },
+/* jl$Qcondi$F0 [$RC_noilink] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F0), ' ', '[', OP (RC_NOILINK), ']', 0 } },
+ & ifmt_j_cc___RC_noilink_, { 0x20e20000 }
+ },
+/* jl$_L$F0.d $s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F0), '.', 'd', ' ', OP (S12), 0 } },
+ & ifmt_j_L_s12_, { 0x20a30000 }
+ },
+/* jl$Qcondi$F0.d $U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F0), '.', 'd', ' ', OP (U6), 0 } },
+ & ifmt_j_ccu6_, { 0x20e30020 }
+ },
+/* jl$_L$F0.d $U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F0), '.', 'd', ' ', OP (U6), 0 } },
+ & ifmt_j_L_u6_, { 0x20630000 }
+ },
+/* jl$_L$F0.d [$RC] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F0), '.', 'd', ' ', '[', OP (RC), ']', 0 } },
+ & ifmt_j_L_r_r_d___RC_, { 0x20230000 }
+ },
+/* jl$Qcondi$F0.d [$RC] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F0), '.', 'd', ' ', '[', OP (RC), ']', 0 } },
+ & ifmt_j_cc_d___RC_, { 0x20e30000 }
+ },
+/* jl$_S.d [$R_b] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), '.', 'd', ' ', '[', OP (R_B), ']', 0 } },
+ & ifmt_sub_s_go_sub_ne, { 0x78600000 }
+ },
+/* lp$_L$F0 $s12x2 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F0), ' ', OP (S12X2), 0 } },
+ & ifmt_lp_L_s12_, { 0x20a80000 }
+ },
+/* lp$Qcondi$F0 $U6x2 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F0), ' ', OP (U6X2), 0 } },
+ & ifmt_lpcc_ccu6, { 0x20e80020 }
+ },
+/* flag$_L$F0 $s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F0), ' ', OP (S12), 0 } },
+ & ifmt_j_L_s12_, { 0x20a90000 }
+ },
+/* flag$Qcondi$F0 $U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F0), ' ', OP (U6), 0 } },
+ & ifmt_j_ccu6_, { 0x20e90020 }
+ },
+/* flag$_L$F0 $U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F0), ' ', OP (U6), 0 } },
+ & ifmt_j_L_u6_, { 0x20690000 }
+ },
+/* flag$_L$F0 $RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F0), ' ', OP (RC), 0 } },
+ & ifmt_j_L_r_r_d___RC_, { 0x20290000 }
+ },
+/* flag$Qcondi$F0 $RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F0), ' ', OP (RC), 0 } },
+ & ifmt_j_cc_d___RC_, { 0x20e90000 }
+ },
+/* lr$_L$F0 $RB,[$RC] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F0), ' ', OP (RB), ',', '[', OP (RC), ']', 0 } },
+ & ifmt_lr_L_r_r___RC_, { 0x202a0000 }
+ },
+/* lr$_L$F0 $RB,[$s12] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F0), ' ', OP (RB), ',', '[', OP (S12), ']', 0 } },
+ & ifmt_lr_L_s12_, { 0x20aa0000 }
+ },
+/* lr$_L$F0 $RB,[$U6] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F0), ' ', OP (RB), ',', '[', OP (U6), ']', 0 } },
+ & ifmt_lr_L_u6_, { 0x206a0000 }
+ },
+/* sr$_L$F0 $RB,[$RC] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F0), ' ', OP (RB), ',', '[', OP (RC), ']', 0 } },
+ & ifmt_lr_L_r_r___RC_, { 0x202b0000 }
+ },
+/* sr$_L$F0 $RB,[$s12] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F0), ' ', OP (RB), ',', '[', OP (S12), ']', 0 } },
+ & ifmt_lr_L_s12_, { 0x20ab0000 }
+ },
+/* sr$_L$F0 $RB,[$U6] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F0), ' ', OP (RB), ',', '[', OP (U6), ']', 0 } },
+ & ifmt_lr_L_u6_, { 0x206b0000 }
+ },
+/* asl$_L$F $RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_asl_L_r_r__RC, { 0x202f0000 }
+ },
+/* asl$_L$F $RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_asl_L_u6_, { 0x206f0000 }
+ },
+/* asl$_S $R_b,$R_b,$R_c */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (R_C), 0 } },
+ & ifmt_I16_GO_SUB_s_go, { 0x781b0000 }
+ },
+/* asr$_L$F $RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_asl_L_r_r__RC, { 0x202f0001 }
+ },
+/* asr$_L$F $RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_asl_L_u6_, { 0x206f0001 }
+ },
+/* asr$_S $R_b,$R_b,$R_c */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (R_C), 0 } },
+ & ifmt_I16_GO_SUB_s_go, { 0x781c0000 }
+ },
+/* lsr$_L$F $RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_asl_L_r_r__RC, { 0x202f0002 }
+ },
+/* lsr$_L$F $RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_asl_L_u6_, { 0x206f0002 }
+ },
+/* lsr$_S $R_b,$R_b,$R_c */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (R_C), 0 } },
+ & ifmt_I16_GO_SUB_s_go, { 0x781d0000 }
+ },
+/* ror$_L$F $RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_asl_L_r_r__RC, { 0x202f0003 }
+ },
+/* ror$_L$F $RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_asl_L_u6_, { 0x206f0003 }
+ },
+/* rrc$_L$F $RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_asl_L_r_r__RC, { 0x202f0004 }
+ },
+/* rrc$_L$F $RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_asl_L_u6_, { 0x206f0004 }
+ },
+/* sexb$_L$F $RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_asl_L_r_r__RC, { 0x202f0005 }
+ },
+/* sexb$_L$F $RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_asl_L_u6_, { 0x206f0005 }
+ },
+/* sexb$_S $R_b,$R_b,$R_c */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (R_C), 0 } },
+ & ifmt_I16_GO_SUB_s_go, { 0x780d0000 }
+ },
+/* sexw$_L$F $RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_asl_L_r_r__RC, { 0x202f0006 }
+ },
+/* sexw$_L$F $RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_asl_L_u6_, { 0x206f0006 }
+ },
+/* sexw$_S $R_b,$R_b,$R_c */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (R_C), 0 } },
+ & ifmt_I16_GO_SUB_s_go, { 0x780e0000 }
+ },
+/* extb$_L$F $RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_asl_L_r_r__RC, { 0x202f0007 }
+ },
+/* extb$_L$F $RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_asl_L_u6_, { 0x206f0007 }
+ },
+/* extb$_S $R_b,$R_b,$R_c */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (R_C), 0 } },
+ & ifmt_I16_GO_SUB_s_go, { 0x780f0000 }
+ },
+/* extw$_L$F $RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_asl_L_r_r__RC, { 0x202f0008 }
+ },
+/* extw$_L$F $RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_asl_L_u6_, { 0x206f0008 }
+ },
+/* extw$_S $R_b,$R_b,$R_c */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (R_C), 0 } },
+ & ifmt_I16_GO_SUB_s_go, { 0x78100000 }
+ },
+/* abs$_L$F $RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_asl_L_r_r__RC, { 0x202f0009 }
+ },
+/* abs$_L$F $RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_asl_L_u6_, { 0x206f0009 }
+ },
+/* abs$_S $R_b,$R_b,$R_c */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (R_C), 0 } },
+ & ifmt_I16_GO_SUB_s_go, { 0x78110000 }
+ },
+/* not$_L$F $RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_asl_L_r_r__RC, { 0x202f000a }
+ },
+/* not$_L$F $RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_asl_L_u6_, { 0x206f000a }
+ },
+/* not$_S $R_b,$R_b,$R_c */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (R_C), 0 } },
+ & ifmt_I16_GO_SUB_s_go, { 0x78120000 }
+ },
+/* rlc$_L$F $RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_asl_L_r_r__RC, { 0x202f000b }
+ },
+/* rlc$_L$F $RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_asl_L_u6_, { 0x206f000b }
+ },
+/* ex$_L$EXDi $RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (EXDI), ' ', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_ex_L_r_r__RC, { 0x202f000c }
+ },
+/* ex$_L$EXDi $RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (EXDI), ' ', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_ex_L_u6_, { 0x206f000c }
+ },
+/* neg$_S $R_b,$R_b,$R_c */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (R_C), 0 } },
+ & ifmt_I16_GO_SUB_s_go, { 0x78130000 }
+ },
+/* swi */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_swi, { 0x226f003f }
+ },
+/* trap$_S $trapnum */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (TRAPNUM), 0 } },
+ & ifmt_trap_s, { 0x781e0000 }
+ },
+/* brk */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_swi, { 0x256f003f }
+ },
+/* brk_s */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_brk_s, { 0x7fff0000 }
+ },
+/* asl$_L$F $RB,$RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_add_L_s12__RA_, { 0x28800000 }
+ },
+/* asl$Qcondi$F $RB,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_ccu6__RA_, { 0x28c00020 }
+ },
+/* asl$_L$F $RA,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_L_u6__RA_, { 0x28400000 }
+ },
+/* asl$_L$F $RA,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_L_r_r__RA__RC, { 0x28000000 }
+ },
+/* asl$Qcondi$F $RB,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_cc__RA__RC, { 0x28c00000 }
+ },
+/* asl$_S $R_c,$R_b,$u3 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_C), ',', OP (R_B), ',', OP (U3), 0 } },
+ & ifmt_add_s_cbu3, { 0x68100000 }
+ },
+/* asl$_S $R_b,$R_b,$u5 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (U5), 0 } },
+ & ifmt_sub_s_ssb, { 0xb8000000 }
+ },
+/* asl$_S $R_b,$R_b,$R_c */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (R_C), 0 } },
+ & ifmt_I16_GO_SUB_s_go, { 0x78180000 }
+ },
+/* lsr$_L$F $RB,$RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_add_L_s12__RA_, { 0x28810000 }
+ },
+/* lsr$Qcondi$F $RB,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_ccu6__RA_, { 0x28c10020 }
+ },
+/* lsr$_L$F $RA,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_L_u6__RA_, { 0x28410000 }
+ },
+/* lsr$_L$F $RA,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_L_r_r__RA__RC, { 0x28010000 }
+ },
+/* lsr$Qcondi$F $RB,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_cc__RA__RC, { 0x28c10000 }
+ },
+/* lsr$_S $R_b,$R_b,$u5 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (U5), 0 } },
+ & ifmt_sub_s_ssb, { 0xb8200000 }
+ },
+/* lsr$_S $R_b,$R_b,$R_c */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (R_C), 0 } },
+ & ifmt_I16_GO_SUB_s_go, { 0x78190000 }
+ },
+/* asr$_L$F $RB,$RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_add_L_s12__RA_, { 0x28820000 }
+ },
+/* asr$Qcondi$F $RB,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_ccu6__RA_, { 0x28c20020 }
+ },
+/* asr$_L$F $RA,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_L_u6__RA_, { 0x28420000 }
+ },
+/* asr$_L$F $RA,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_L_r_r__RA__RC, { 0x28020000 }
+ },
+/* asr$Qcondi$F $RB,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_cc__RA__RC, { 0x28c20000 }
+ },
+/* asr$_S $R_c,$R_b,$u3 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_C), ',', OP (R_B), ',', OP (U3), 0 } },
+ & ifmt_add_s_cbu3, { 0x68180000 }
+ },
+/* asr$_S $R_b,$R_b,$u5 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (U5), 0 } },
+ & ifmt_sub_s_ssb, { 0xb8400000 }
+ },
+/* asr$_S $R_b,$R_b,$R_c */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (R_C), 0 } },
+ & ifmt_I16_GO_SUB_s_go, { 0x781a0000 }
+ },
+/* ror$_L$F $RB,$RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_add_L_s12__RA_, { 0x28830000 }
+ },
+/* ror$Qcondi$F $RB,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_ccu6__RA_, { 0x28c30020 }
+ },
+/* ror$_L$F $RA,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_L_u6__RA_, { 0x28430000 }
+ },
+/* ror$_L$F $RA,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_L_r_r__RA__RC, { 0x28030000 }
+ },
+/* ror$Qcondi$F $RB,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_cc__RA__RC, { 0x28c30000 }
+ },
+/* mul64$_L$F1 $RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F1), ' ', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_tst_L_s12_, { 0x28840000 }
+ },
+/* mul64$Qcondi$F1 $RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F1), ' ', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_tst_ccu6_, { 0x28c40020 }
+ },
+/* mul64$_L$F1 $RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F1), ' ', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_tst_L_u6_, { 0x28440000 }
+ },
+/* mul64$_L$F1 $RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F1), ' ', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_tst_L_r_r__RC, { 0x28040000 }
+ },
+/* mul64$Qcondi$F1 $RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F1), ' ', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_tst_cc__RC, { 0x28c40000 }
+ },
+/* mul64$_S $R_b,$R_c */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_C), 0 } },
+ & ifmt_I16_GO_SUB_s_go, { 0x780c0000 }
+ },
+/* mulu64$_L$F1 $RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F1), ' ', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_tst_L_s12_, { 0x28850000 }
+ },
+/* mulu64$Qcondi$F1 $RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F1), ' ', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_tst_ccu6_, { 0x28c50020 }
+ },
+/* mulu64$_L$F1 $RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F1), ' ', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_tst_L_u6_, { 0x28450000 }
+ },
+/* mulu64$_L$F1 $RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F1), ' ', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_tst_L_r_r__RC, { 0x28050000 }
+ },
+/* mulu64$Qcondi$F1 $RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F1), ' ', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_tst_cc__RC, { 0x28c50000 }
+ },
+/* adds$_L$F $RB,$RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_add_L_s12__RA_, { 0x28860000 }
+ },
+/* adds$Qcondi$F $RB,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_ccu6__RA_, { 0x28c60020 }
+ },
+/* adds$_L$F $RA,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_L_u6__RA_, { 0x28460000 }
+ },
+/* adds$_L$F $RA,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_L_r_r__RA__RC, { 0x28060000 }
+ },
+/* adds$Qcondi$F $RB,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_cc__RA__RC, { 0x28c60000 }
+ },
+/* subs$_L$F $RB,$RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_add_L_s12__RA_, { 0x28870000 }
+ },
+/* subs$Qcondi$F $RB,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_ccu6__RA_, { 0x28c70020 }
+ },
+/* subs$_L$F $RA,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_L_u6__RA_, { 0x28470000 }
+ },
+/* subs$_L$F $RA,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_L_r_r__RA__RC, { 0x28070000 }
+ },
+/* subs$Qcondi$F $RB,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_cc__RA__RC, { 0x28c70000 }
+ },
+/* divaw$_L$F0 $RB,$RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F0), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_lr_L_s12_, { 0x28880000 }
+ },
+/* divaw$Qcondi$F0 $RB,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F0), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_divaw_ccu6__RA_, { 0x28c80020 }
+ },
+/* divaw$_L$F0 $RA,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F0), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_divaw_L_u6__RA_, { 0x28480000 }
+ },
+/* divaw$_L$F0 $RA,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F0), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_divaw_L_r_r__RA__RC, { 0x28080000 }
+ },
+/* divaw$Qcondi$F0 $RB,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F0), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_divaw_cc__RA__RC, { 0x28c80000 }
+ },
+/* asls$_L$F $RB,$RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_add_L_s12__RA_, { 0x288a0000 }
+ },
+/* asls$Qcondi$F $RB,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_ccu6__RA_, { 0x28ca0020 }
+ },
+/* asls$_L$F $RA,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_L_u6__RA_, { 0x284a0000 }
+ },
+/* asls$_L$F $RA,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_L_r_r__RA__RC, { 0x280a0000 }
+ },
+/* asls$Qcondi$F $RB,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_cc__RA__RC, { 0x28ca0000 }
+ },
+/* asrs$_L$F $RB,$RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_add_L_s12__RA_, { 0x288b0000 }
+ },
+/* asrs$Qcondi$F $RB,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_ccu6__RA_, { 0x28cb0020 }
+ },
+/* asrs$_L$F $RA,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_L_u6__RA_, { 0x284b0000 }
+ },
+/* asrs$_L$F $RA,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_L_r_r__RA__RC, { 0x280b0000 }
+ },
+/* asrs$Qcondi$F $RB,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_cc__RA__RC, { 0x28cb0000 }
+ },
+/* addsdw$_L$F $RB,$RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_add_L_s12__RA_, { 0x28a80000 }
+ },
+/* addsdw$Qcondi$F $RB,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_ccu6__RA_, { 0x28e80020 }
+ },
+/* addsdw$_L$F $RA,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_L_u6__RA_, { 0x28680000 }
+ },
+/* addsdw$_L$F $RA,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_L_r_r__RA__RC, { 0x28280000 }
+ },
+/* addsdw$Qcondi$F $RB,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_cc__RA__RC, { 0x28e80000 }
+ },
+/* subsdw$_L$F $RB,$RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_add_L_s12__RA_, { 0x28a90000 }
+ },
+/* subsdw$Qcondi$F $RB,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_ccu6__RA_, { 0x28e90020 }
+ },
+/* subsdw$_L$F $RA,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_L_u6__RA_, { 0x28690000 }
+ },
+/* subsdw$_L$F $RA,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_L_r_r__RA__RC, { 0x28290000 }
+ },
+/* subsdw$Qcondi$F $RB,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_cc__RA__RC, { 0x28e90000 }
+ },
+/* swap$_L$F $RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_asl_L_r_r__RC, { 0x282f0000 }
+ },
+/* swap$_L$F $RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_asl_L_u6_, { 0x286f0000 }
+ },
+/* norm$_L$F $RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_asl_L_r_r__RC, { 0x282f0001 }
+ },
+/* norm$_L$F $RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_asl_L_u6_, { 0x286f0001 }
+ },
+/* rnd16$_L$F $RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_asl_L_r_r__RC, { 0x282f0003 }
+ },
+/* rnd16$_L$F $RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_asl_L_u6_, { 0x286f0003 }
+ },
+/* abssw$_L$F $RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_asl_L_r_r__RC, { 0x282f0004 }
+ },
+/* abssw$_L$F $RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_asl_L_u6_, { 0x286f0004 }
+ },
+/* abss$_L$F $RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_asl_L_r_r__RC, { 0x282f0005 }
+ },
+/* abss$_L$F $RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_asl_L_u6_, { 0x286f0005 }
+ },
+/* negsw$_L$F $RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_asl_L_r_r__RC, { 0x282f0006 }
+ },
+/* negsw$_L$F $RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_asl_L_u6_, { 0x286f0006 }
+ },
+/* negs$_L$F $RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_asl_L_r_r__RC, { 0x282f0007 }
+ },
+/* negs$_L$F $RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_asl_L_u6_, { 0x286f0007 }
+ },
+/* normw$_L$F $RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_asl_L_r_r__RC, { 0x282f0008 }
+ },
+/* normw$_L$F $RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_asl_L_u6_, { 0x286f0008 }
+ },
+/* nop_s */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_j_s__S, { 0x78e00000 }
+ },
+/* unimp_s */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_j_s__S, { 0x79e00000 }
+ },
+/* pop$_S $R_b */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), 0 } },
+ & ifmt_pop_s_b, { 0xc0c10000 }
+ },
+/* pop$_S $R31 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R31), 0 } },
+ & ifmt_pop_s_blink, { 0xc0d10000 }
+ },
+/* push$_S $R_b */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R_B), 0 } },
+ & ifmt_pop_s_b, { 0xc0e10000 }
+ },
+/* push$_S $R31 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_S), ' ', OP (R31), 0 } },
+ & ifmt_pop_s_blink, { 0xc0f10000 }
+ },
+/* mullw$_L$F $RB,$RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_add_L_s12__RA_, { 0x28b10000 }
+ },
+/* mullw$Qcondi$F $RB,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_ccu6__RA_, { 0x28f10020 }
+ },
+/* mullw$_L$F $RA,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_L_u6__RA_, { 0x28710000 }
+ },
+/* mullw$_L$F $RA,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_L_r_r__RA__RC, { 0x28310000 }
+ },
+/* mullw$Qcondi$F $RB,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_cc__RA__RC, { 0x28f10000 }
+ },
+/* maclw$_L$F $RB,$RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_add_L_s12__RA_, { 0x28b30000 }
+ },
+/* maclw$Qcondi$F $RB,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_ccu6__RA_, { 0x28f30020 }
+ },
+/* maclw$_L$F $RA,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_L_u6__RA_, { 0x28730000 }
+ },
+/* maclw$_L$F $RA,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_L_r_r__RA__RC, { 0x28330000 }
+ },
+/* maclw$Qcondi$F $RB,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_cc__RA__RC, { 0x28f30000 }
+ },
+/* machlw$_L$F $RB,$RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_add_L_s12__RA_, { 0x28b60000 }
+ },
+/* machlw$Qcondi$F $RB,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_ccu6__RA_, { 0x28f60020 }
+ },
+/* machlw$_L$F $RA,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_L_u6__RA_, { 0x28760000 }
+ },
+/* machlw$_L$F $RA,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_L_r_r__RA__RC, { 0x28360000 }
+ },
+/* machlw$Qcondi$F $RB,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_cc__RA__RC, { 0x28f60000 }
+ },
+/* mululw$_L$F $RB,$RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_add_L_s12__RA_, { 0x28b00000 }
+ },
+/* mululw$Qcondi$F $RB,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_ccu6__RA_, { 0x28f00020 }
+ },
+/* mululw$_L$F $RA,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_L_u6__RA_, { 0x28700000 }
+ },
+/* mululw$_L$F $RA,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_L_r_r__RA__RC, { 0x28300000 }
+ },
+/* mululw$Qcondi$F $RB,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_cc__RA__RC, { 0x28f00000 }
+ },
+/* machulw$_L$F $RB,$RB,$s12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } },
+ & ifmt_add_L_s12__RA_, { 0x28b50000 }
+ },
+/* machulw$Qcondi$F $RB,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_ccu6__RA_, { 0x28f50020 }
+ },
+/* machulw$_L$F $RA,$RB,$U6 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } },
+ & ifmt_add_L_u6__RA_, { 0x28750000 }
+ },
+/* machulw$_L$F $RA,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_L_r_r__RA__RC, { 0x28350000 }
+ },
+/* machulw$Qcondi$F $RB,$RB,$RC */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } },
+ & ifmt_add_cc__RA__RC, { 0x28f50000 }
+ },
+/* */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_current_loop_end, { 0x202f003e }
+ },
+/* */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_current_loop_end, { 0x202f003e }
+ },
+/* */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_current_loop_end, { 0x202f003e }
+ },
+};
+
+#undef A
+#undef OPERAND
+#undef MNEM
+#undef OP
+
+/* Formats for ALIAS macro-insns. */
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define F(f) & arc_cgen_ifld_table[ARC_##f]
+#else
+#define F(f) & arc_cgen_ifld_table[ARC_/**/f]
+#endif
+#undef F
+
+/* Each non-simple macro entry points to an array of expansion possibilities. */
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_INSN_##a)
+#else
+#define A(a) (1 << CGEN_INSN_/**/a)
+#endif
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define OPERAND(op) ARC_OPERAND_##op
+#else
+#define OPERAND(op) ARC_OPERAND_/**/op
+#endif
+#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
+#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
+
+/* The macro instruction table. */
+
+static const CGEN_IBASE arc_cgen_macro_insn_table[] =
+{
+};
+
+/* The macro instruction opcode table. */
+
+static const CGEN_OPCODE arc_cgen_macro_insn_opcode_table[] =
+{
+};
+
+#undef A
+#undef OPERAND
+#undef MNEM
+#undef OP
+
+#ifndef CGEN_ASM_HASH_P
+#define CGEN_ASM_HASH_P(insn) 1
+#endif
+
+#ifndef CGEN_DIS_HASH_P
+#define CGEN_DIS_HASH_P(insn) 1
+#endif
+
+/* Return non-zero if INSN is to be added to the hash table.
+ Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
+
+static int
+asm_hash_insn_p (insn)
+ const CGEN_INSN *insn ATTRIBUTE_UNUSED;
+{
+ return CGEN_ASM_HASH_P (insn);
}
-/* Initialize any tables that need it.
- Must be called once at start up (or when first needed).
+static int
+dis_hash_insn_p (insn)
+ const CGEN_INSN *insn;
+{
+ /* If building the hash table and the NO-DIS attribute is present,
+ ignore. */
+ if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS))
+ return 0;
+ return CGEN_DIS_HASH_P (insn);
+}
- FLAGS is a set of bits that say what version of the cpu we have,
- and in particular at least (one of) ARC_MACH_XXX. */
+#ifndef CGEN_ASM_HASH
+#define CGEN_ASM_HASH_SIZE 127
+#ifdef CGEN_MNEMONIC_OPERANDS
+#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE)
+#else
+#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/
+#endif
+#endif
+
+/* It doesn't make much sense to provide a default here,
+ but while this is under development we do.
+ BUFFER is a pointer to the bytes of the insn, target order.
+ VALUE is the first base_insn_bitsize bits as an int in host order. */
+
+#ifndef CGEN_DIS_HASH
+#define CGEN_DIS_HASH_SIZE 256
+#define CGEN_DIS_HASH(buf, value, big_p) (*(unsigned char *) (buf))
+#endif
+
+/* The result is the hash value of the insn.
+ Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
+
+static unsigned int
+asm_hash_insn (mnem)
+ const char * mnem;
+{
+ return CGEN_ASM_HASH (mnem);
+}
+
+/* BUF is a pointer to the bytes of the insn, target order.
+ VALUE is the first base_insn_bitsize bits as an int in host order. */
+
+static unsigned int
+dis_hash_insn (buf, value, big_p)
+ const char * buf ATTRIBUTE_UNUSED;
+ CGEN_INSN_INT value ATTRIBUTE_UNUSED;
+ int big_p ATTRIBUTE_UNUSED;
+{
+ return CGEN_DIS_HASH (buf, value, big_p);
+}
+
+/* Set the recorded length of the insn in the CGEN_FIELDS struct. */
+
+static void
+set_fields_bitsize (CGEN_FIELDS *fields, int size)
+{
+ CGEN_FIELDS_BITSIZE (fields) = size;
+}
+
+/* Function to call before using the operand instance table.
+ This plugs the opcode entries and macro instructions into the cpu table. */
void
-arc_opcode_init_tables (int flags)
-{
- static int init_p = 0;
-
- cpu_type = flags;
-
- /* We may be intentionally called more than once (for example gdb will call
- us each time the user switches cpu). These tables only need to be init'd
- once though. */
- if (!init_p)
- {
- int i,n;
-
- memset (arc_operand_map, 0, sizeof (arc_operand_map));
- n = sizeof (arc_operands) / sizeof (arc_operands[0]);
- for (i = 0; i < n; ++i)
- arc_operand_map[arc_operands[i].fmt] = i;
-
- memset (opcode_map, 0, sizeof (opcode_map));
- memset (icode_map, 0, sizeof (icode_map));
- /* Scan the table backwards so macros appear at the front. */
- for (i = arc_opcodes_count - 1; i >= 0; --i)
- {
- int opcode_hash = ARC_HASH_OPCODE (arc_opcodes[i].syntax);
- int icode_hash = ARC_HASH_ICODE (arc_opcodes[i].value);
-
- arc_opcodes[i].next_asm = opcode_map[opcode_hash];
- opcode_map[opcode_hash] = &arc_opcodes[i];
-
- arc_opcodes[i].next_dis = icode_map[icode_hash];
- icode_map[icode_hash] = &arc_opcodes[i];
- }
-
- init_p = 1;
- }
-}
-
-/* Return non-zero if OPCODE is supported on the specified cpu.
- Cpu selection is made when calling `arc_opcode_init_tables'. */
-
-int
-arc_opcode_supported (const struct arc_opcode *opcode)
-{
- if (ARC_OPCODE_CPU (opcode->flags) <= cpu_type)
- return 1;
- return 0;
-}
-
-/* Return the first insn in the chain for assembling INSN. */
-
-const struct arc_opcode *
-arc_opcode_lookup_asm (const char *insn)
-{
- return opcode_map[ARC_HASH_OPCODE (insn)];
-}
-
-/* Return the first insn in the chain for disassembling INSN. */
-
-const struct arc_opcode *
-arc_opcode_lookup_dis (unsigned int insn)
-{
- return icode_map[ARC_HASH_ICODE (insn)];
-}
-
-/* Called by the assembler before parsing an instruction. */
-
-void
-arc_opcode_init_insert (void)
+arc_cgen_init_opcode_table (CGEN_CPU_DESC cd)
{
int i;
+ int num_macros = (sizeof (arc_cgen_macro_insn_table) /
+ sizeof (arc_cgen_macro_insn_table[0]));
+ const CGEN_IBASE *ib = & arc_cgen_macro_insn_table[0];
+ const CGEN_OPCODE *oc = & arc_cgen_macro_insn_opcode_table[0];
+ CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN));
- for(i = 0; i < OPERANDS; i++)
- ls_operand[i] = OP_NONE;
-
- flag_p = 0;
- flagshimm_handled_p = 0;
- cond_p = 0;
- addrwb_p = 0;
- shimm_p = 0;
- limm_p = 0;
- jumpflags_p = 0;
- nullify_p = 0;
- nullify = 0; /* The default is important. */
-}
-
-/* Called by the assembler to see if the insn has a limm operand.
- Also called by the disassembler to see if the insn contains a limm. */
-
-int
-arc_opcode_limm_p (long *limmp)
-{
- if (limmp)
- *limmp = limm;
- return limm_p;
-}
-
-/* Utility for the extraction functions to return the index into
- `arc_suffixes'. */
-
-const struct arc_operand_value *
-arc_opcode_lookup_suffix (const struct arc_operand *type, int value)
-{
- const struct arc_operand_value *v,*end;
- struct arc_ext_operand_value *ext_oper = arc_ext_operands;
-
- while (ext_oper)
+ memset (insns, 0, num_macros * sizeof (CGEN_INSN));
+ for (i = 0; i < num_macros; ++i)
{
- if (type == &arc_operands[ext_oper->operand.type]
- && value == ext_oper->operand.value)
- return (&ext_oper->operand);
- ext_oper = ext_oper->next;
+ insns[i].base = &ib[i];
+ insns[i].opcode = &oc[i];
+ arc_cgen_build_insn_regex (& insns[i]);
+ }
+ cd->macro_insn_table.init_entries = insns;
+ cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE);
+ cd->macro_insn_table.num_init_entries = num_macros;
+
+ oc = & arc_cgen_insn_opcode_table[0];
+ insns = (CGEN_INSN *) cd->insn_table.init_entries;
+ for (i = 0; i < MAX_INSNS; ++i)
+ {
+ insns[i].opcode = &oc[i];
+ arc_cgen_build_insn_regex (& insns[i]);
}
- /* ??? This is a little slow and can be speeded up. */
- for (v = arc_suffixes, end = arc_suffixes + arc_suffixes_count; v < end; ++v)
- if (type == &arc_operands[v->type]
- && value == v->value)
- return v;
- return 0;
-}
+ cd->sizeof_fields = sizeof (CGEN_FIELDS);
+ cd->set_fields_bitsize = set_fields_bitsize;
-int
-arc_insn_is_j (arc_insn insn)
-{
- return (insn & (I(-1))) == I(0x7);
-}
+ cd->asm_hash_p = asm_hash_insn_p;
+ cd->asm_hash = asm_hash_insn;
+ cd->asm_hash_size = CGEN_ASM_HASH_SIZE;
-int
-arc_insn_not_jl (arc_insn insn)
-{
- return ((insn & (I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1)))
- != (I(0x7) | R(-1,9,1)));
-}
-
-int
-arc_operand_type (int opertype)
-{
- switch (opertype)
- {
- case 0:
- return COND;
- break;
- case 1:
- return REG;
- break;
- case 2:
- return AUXREG;
- break;
- }
- return -1;
-}
-
-struct arc_operand_value *
-get_ext_suffix (char *s)
-{
- struct arc_ext_operand_value *suffix = arc_ext_operands;
-
- while (suffix)
- {
- if ((COND == suffix->operand.type)
- && !strcmp(s,suffix->operand.name))
- return(&suffix->operand);
- suffix = suffix->next;
- }
- return NULL;
-}
-
-int
-arc_get_noshortcut_flag (void)
-{
- return ARC_REGISTER_NOSHORT_CUT;
+ cd->dis_hash_p = dis_hash_insn_p;
+ cd->dis_hash = dis_hash_insn;
+ cd->dis_hash_size = CGEN_DIS_HASH_SIZE;
}
diff --git a/opcodes/cgen-dis.c b/opcodes/cgen-dis.c
index 7782683..3db4347 100644
--- a/opcodes/cgen-dis.c
+++ b/opcodes/cgen-dis.c
@@ -125,7 +125,7 @@
buf,
CGEN_INSN_MASK_BITSIZE (insn),
big_p);
- hash = (* cd->dis_hash) (buf, value);
+ hash = (* cd->dis_hash) (buf, value, big_p);
add_insn_to_hash_chain (hentbuf, insn, htable, hash);
}
@@ -162,7 +162,7 @@
buf,
CGEN_INSN_MASK_BITSIZE (ilist->insn),
big_p);
- hash = (* cd->dis_hash) (buf, value);
+ hash = (* cd->dis_hash) (buf, value, big_p);
add_insn_to_hash_chain (hentbuf, ilist->insn, htable, hash);
}
@@ -234,7 +234,8 @@
if (cd->dis_hash_table == NULL)
build_dis_hash_table (cd);
- hash = (* cd->dis_hash) (buf, value);
+ hash
+ = (* cd->dis_hash) (buf, value, CGEN_CPU_ENDIAN (cd) == CGEN_ENDIAN_BIG);
return cd->dis_hash_table[hash];
}
diff --git a/opcodes/configure b/opcodes/configure
index 80b1a74..90c95b9 100755
--- a/opcodes/configure
+++ b/opcodes/configure
@@ -11519,7 +11519,7 @@
archdefs="$archdefs -DARCH_$ad"
case "$arch" in
bfd_alpha_arch) ta="$ta alpha-dis.lo alpha-opc.lo" ;;
- bfd_arc_arch) ta="$ta arc-dis.lo arc-opc.lo arc-ext.lo" ;;
+ bfd_arc_arch) ta="$ta arc-asm.lo arc-desc.lo arc-dis.lo arc-ibld.lo arc-opc.lo arc-opinst.lo arc-ext.lo" using_cgen=yes ;;
bfd_arm_arch) ta="$ta arm-dis.lo" ;;
bfd_avr_arch) ta="$ta avr-dis.lo" ;;
bfd_bfin_arch) ta="$ta bfin-dis.lo" ;;
diff --git a/opcodes/configure.in b/opcodes/configure.in
index 08011be..4c86d79 100644
--- a/opcodes/configure.in
+++ b/opcodes/configure.in
@@ -173,7 +173,7 @@
archdefs="$archdefs -DARCH_$ad"
case "$arch" in
bfd_alpha_arch) ta="$ta alpha-dis.lo alpha-opc.lo" ;;
- bfd_arc_arch) ta="$ta arc-dis.lo arc-opc.lo arc-ext.lo" ;;
+ bfd_arc_arch) ta="$ta arc-asm.lo arc-desc.lo arc-dis.lo arc-ibld.lo arc-opc.lo arc-opinst.lo arc-ext.lo" using_cgen=yes ;;
bfd_arm_arch) ta="$ta arm-dis.lo" ;;
bfd_avr_arch) ta="$ta avr-dis.lo" ;;
bfd_bfin_arch) ta="$ta bfin-dis.lo" ;;
diff --git a/sim/ChangeLog b/sim/ChangeLog
index 0a3741a..f379119 100644
--- a/sim/ChangeLog
+++ b/sim/ChangeLog
@@ -1,3 +1,9 @@
+2009-03-09 J"orn Rennecke <joern.rennecke@arc.com>
+
+ * arc: New directory.
+ * configure.ac: Add arc case.
+ * configure: Regenerate.
+
2008-02-05 DJ Delorie <dj@redhat.com>
* configure.ac (v850): V850 now has a testsuite.
diff --git a/sim/arc/ChangeLog b/sim/arc/ChangeLog
new file mode 100644
index 0000000..a740378
--- /dev/null
+++ b/sim/arc/ChangeLog
@@ -0,0 +1,227 @@
+2008-11-18 J"orn Rennecke <joern.rennecke@arc.com>
+
+ * sem5.c, sem6.c, sem7.c: Regenerate.
+ * sem5-switch.c, sem6-switch.c, sem7-switch.c: Likewise.
+
+2008-09-18 J"orn Rennecke <joern.rennecke@arc.com>
+
+ * sem5.c, sem6.c, sem7.c: Regenerate.
+ * sem5-switch.c, sem6-switch.c, sem7-switch.c: Likewise.
+
+ * sim-if.c (init_stack): Round memory up to multiple of 32 bytes.
+
+2008-09-16 J"orn Rennecke <joern.rennecke@arc.com>
+
+ * decode5,c, decode6,c, decode7.c, sem5.c, sem6.c, sem7.c: Regenerate.
+ * sem5-switch.c, sem6-switch.c, sem7-switch.c: Likewise.
+
+2008-09-13 J"orn Rennecke <joern.rennecke@arc.com>
+
+ * sem5.c, sem6.c, sem7.c: Regenerate.
+ * sem5-switch.c, sem6-switch.c, sem7-switch.c: Likewise.
+
+2008-09-12 J"orn Rennecke <joern.rennecke@arc.com>
+
+ * sem5.c, sem6.c, sem7.c: Regenerate.
+ * sem5-switch.c, sem6-switch.c, sem7-switch.c: Likewise.
+
+2008-09-12 J"orn Rennecke <joern.rennecke@arc.com>
+
+ * decode5.c, decode6.c decode7.c, sem5.c, sem6.c, sem7.c: Regenerate.
+ * sem5-switch.c, sem6-switch.c, sem7-switch.c: Likewise.
+ * decode5.h, decode6.h, decode7.h: Likweise.
+ * model5.c, model6.c, model7.c: Likewise.
+
+2008-09-11 J"orn Rennecke <joern.rennecke@arc.com>
+
+ * decode5.c, decode6.c decode7.c, sem5.c, sem6.c, sem7.c: Regenerate.
+ * sem5-switch.c, sem6-switch.c, sem7-switch.c: Likewise.
+ * decode5.h, decode6.h, decode7.h: Likweise.
+ * model5.c, model6.c, model7.c: Likewise.
+
+2008-07-14 J"orn Rennecke <joern.rennecke@arc.com>
+
+ * decode5.c, decode6.c, decode7.c, sem5.c, sem6.c, sem7.c: Regenerate.
+ * decode5.h, decode6.h, decode7.h: : Likewise.
+ * sem5-switch.c, sem6-switch.c, sem7-switch.c: Likewise.
+ * cpu5.h, cpu6.h, cpu7.h, model5.c, model6.c, model7.c: Likewise.
+
+2008-06-19 J"orn Rennecke <joern.rennecke@arc.com>
+
+ * sim-if.c (init_stack): Round up memsize.
+ (sim_create_inferior): Pass pointer to argv array rather than
+ first element in r1.
+
+2008-03-28 J"orn Rennecke <joern.rennecke@arc.com>
+
+ * decode5.c, decode6.c, decode7.c, sem5.c, sem6.c, sem7.c: Regenerate.
+ * decode5.h, decode6.h, decode7.h: : Likewise.
+ * sem5-switch.c, sem6-switch.c, sem7-switch.c: Likewise.
+ * model5.c, model6.c, model7.c: Likewise.
+ * mloop6.in (xextract-pbb): Model special ARC600 behaviour
+ for branches at loop end.
+
+2008-02-12 J"orn Rennecke <joern.rennecke@arc.com>
+
+ * mloop5.in (xextract-pbb): Interpret at least one insn.
+ * mloop6.in (xextract-pbb): Likewise.
+ * mloop7.in (xextract-pbb): Likewise.
+ * sem5.c, sem6.c, sem7.c: Regenerate.
+ * sem5-switch.c, sem6-switch.c, sem7-switch.c: Likewise.
+
+2007-10-25 J"orn Rennecke <joern.rennecke@arc.com>
+
+ * decode5.c, decode6.c, decode7.c: Regenerate.
+ * decode5.h, decode6.h, decode7.h: Likewise.
+ * sem5.c, sem6.c, sem7.c: Likewise.
+ * sem5-switch.c, sem6-switch.c, sem7-switch.c: Likewise.
+ * cpu5.h, cpu6.h, cpu7.h: Likewise.
+ * model5.c, model6.c, model7.c: Regenerate.
+ * traps.c (arc_breakpoint): New function.
+
+2007-10-18 J"orn Rennecke <joern.rennecke@arc.com>
+
+ * mloop5.in (extract): Supply insn parameter twice to @cpu@_decode.
+ Fix logic that decodes delay slot insn length.
+ * loop6.in, mloop7.in: Likewise.
+ * decode5.c, decode6.c, decode7.c: Regenerate.
+ * decode5.h, decode6.h, decode7.h: Likewise.
+ * sem5.c, sem6.c, sem7.c: Likewise.
+ * sem5-switch.c, sem6-switch.c, sem7-switch.c: Likewise.
+ * cpu5.h, cpu6.h, cpu7.h: Likewise.
+
+2007-10-15 J"orn Rennecke <joern.rennecke@arc.com>
+
+ * mloop7.in (xextract-pbb): Use current_loop_end_after_branch
+ when indicated.
+ * decode5.c, decode6.c, decode7.c: Regenerate.
+ * decode5.h, decode6.h, decode7.h: Likewise.
+ * sem5.c, sem6.c, sem7.c: Likewise.
+ * sem5-switch.c, sem6-switch.c, sem7-switch.c: Likewise.
+ * model5.c, model6.c, model7.c: Regenerate.
+
+ * sim-if.c (init_stack): If argv is zero, don't use it.
+
+2007-10-12 J"orn Rennecke <joern.rennecke@arc.com>
+
+ * mloop-7.in (xextract-pbb): Fix zero-overhead loops for case when
+ branch precedes loop end.
+
+2007-10-04 J"orn Rennecke <joern.rennecke@arc.com>
+
+ * sem5.c, sem6.c, sem7.c: Regenerate.
+ * sem5-switch.c, sem6-switch.c, sem7-switch.c: Likewise.
+
+2007-10-01 J"orn Rennecke <joern.rennecke@arc.com>
+
+ * decode5.c, decode6.c, decode7.c: Regenerate.
+ * sem5.c, sem6.c, sem7.c: Likewise.
+ * sem5-switch.c, sem6-switch.c, sem7-switch.c: Likewise.
+
+2007-09-24 J"orn Rennecke <joern.rennecke@arc.com>
+
+ * decode5.c, decode6.c, decode7.c: Regenerate.
+ * decode5.h, decode6.h, decode7.h: Likewise.
+ * sem5.c, sem6.c, sem7.c: Likewise.
+ * sem-switch5.c, sem-switch6.c, sem-switch7.c: Likewise.
+ * cpu5.h, cpu6.h, cpu7.h, cpu5.c, cpu6.c, cpu7.c: Likewise.
+ * traps.c (arc_trap): Initialize s.arg4.
+ (arc_syscall): Fix tv_usec for TARGET_SYS_gettimeofday.
+ Add TARGET_SYS_setitimer and TARGET_SYS_profil cases.
+
+2007-09-07 J"orn Rennecke <joern.rennecke@arc.com>
+
+ * decode5.c, decode6.c, decode7.c: Regenerate.
+ * decode5.h, decode6.h, decode7.h: Likewise.
+ * sem5.c, sem6.c, sem7.c: Likewise.
+ * sem-switch5.c, sem-switch6.c, sem-switch7.c: Likewise.
+ * cpu5.h, cpu6.h, cpu7.h, cpu5.c, cpu6.c, cpu7.c: Likewise.
+ * model5.c, model6.c, model7.c: Likewise.
+
+2007-08-23 J"orn Rennecke <joern.rennecke@arc.com>
+
+ * sem5.c, sem6.c, sem7.c: Regenerate.
+ * sem5-switch.c, sem6-switch.c, sem7-switch.c: Likewise.
+ * cpu5.h, cpu6.h, cpu7.h, cpu5.c, cpu6.c, cpu7.c: Likewise.
+
+2007-08-22 J"orn Rennecke <joern.rennecke@arc.com>
+
+ * sem5.c, sem6.c, sem7.c: Regenerate.
+ * sem5-switch.c, sem6-switch.c, sem7-switch.c: Likewise.
+
+2007-08-22 J"orn Rennecke <joern.rennecke@arc.com>
+
+ * sem5.c, sem6.c, sem7.c: Regenerate.
+ * sem5-switch.c, sem6-switch.c, sem7-switch.c: Likewise.
+
+2007-08-22 J"orn Rennecke <joern.rennecke@arc.com>
+
+ * sem5.c, sem6.c, sem7.c: Regenerate.
+ * sem5-switch.c, sem6-switch.c, sem7-switch.c: Likewise.
+
+2007-08-22 J"orn Rennecke <joern.rennecke@arc.com>
+
+ * cpu5.h, cpu6.h, cpu7.h: Regenerate.
+
+2007-08-21 J"orn Rennecke <joern.rennecke@arc.com>
+
+ * decode5.c, decode6.c, decode7.c: Regenerate.
+ * sem5.c, sem6.c, sem7.c: Regenerate.
+ * sem-switch5.c, sem-switch6.c, sem-switch7.c: Regenerate.
+ * model5.c, model6.c, model7.c: Regenerate.
+
+2007-08-21 J"orn Rennecke <joern.rennecke@arc.com>
+
+ * sim-if.c (sim_open): Pass endianness obtained from bfd to
+ arc_cgen_cpu_open_1.
+
+2007-08-08 J"orn Rennecke <joern.rennecke@arc.com>
+
+ * decode5.c, decode6.c, decode7.c: Regenerate.
+ * sem5.c, sem6.c, sem7.c: Likewise.
+ * sem5-switch.c, sem6-switch.c, sem7-switch.c: Likewise.
+ * decode5.h, decode6.h, decode7.h: Likewise.
+ * cpu5.h, cpu6.h, cpu7.h, model5.c, model6.c, model7.c: Likewise.
+
+2007-06-20 J"orn Rennecke <joern.rennecke@arc.com>
+
+ * sim-if.c (sim_open): Remove code to canonicalize bfd mach.
+
+2007-06-19 J"orn Rennecke <joern.rennecke@arc.com>
+
+ * decode5.c, decode6.c, decode7.c: Regenerate.
+
+2007-05-15 J"orn Rennecke <joern.rennecke@arc.com>
+
+ * decode5.h, decode6.h, decode7.h: Regenerate.
+ * model5.c, model6.c, model7.c: Likewise.
+ * sim-if.c (sim_open): Call sim_analyze_program before init_stack.
+ Canonicalize bfd mach.
+ * arc5.c (a5f_model_a5_u_exec): Rename to:
+ (a5f_model_A5_u_exec).
+ * arc6.c (arc600f_model_arc600_u_exec): Rename to:
+ (arc600f_model_ARC600_u_exec).
+ * arc7.c (arc700f_model_arc700_u_exec): Rename to:
+ (arc700f_model_ARC700_u_exec).
+
+2007-05-14 J"orn Rennecke <joern.rennecke@arc.com>
+
+ * traps.c (arc_syscall): Use fdbad / fdmap for fstat.
+
+2007-05-02 J"orn Rennecke <joern.rennecke@arc.com>
+
+ * traps.c: Include <sys/stat.h>, <sys/time.h>, "gdb/target-io/arc.h".
+ (arc_trap): Try arc_syscall before cb_syscall.
+ (arc_syscall): Add stat, fstat and gettimeofday.
+
+2007-04-30 J"orn Rennecke <joern.rennecke@arc.com>
+
+ * configure.ac, tconfig.in, Makefile.in, arc-sim.h: New files.
+ * mloop5.in, mloop6.in, mloop7.in, sim-main.h, devices.c: Likewise.
+ * sim-if.c, traps.c, arc5.c, arc6.c, arc7.c: Likewise.
+ * config.in, configure, arch.h, arch.c, decode5.h, decode6.h: Generate.
+ * decode7.h, decode5.c, decode6.c, decode7.c, sem5-switch.c: Likewise.
+ * sem6-switch.c, src/sim/arc/sem7-switch.c, sem5.c, sem6.c: Likewise.
+ * sem7.c, cpu5.h, cpu6.h, cpu7.h, cpuall.h, cpu5.c, cpu6.c: Likewise.
+ * cpu7.c, src/sim/arc/model5.c, model6.c, model7.c: Likewise.
+
diff --git a/sim/arc/Makefile.in b/sim/arc/Makefile.in
new file mode 100644
index 0000000..cb32de2
--- /dev/null
+++ b/sim/arc/Makefile.in
@@ -0,0 +1,193 @@
+# Makefile template for Configure for the arc simulator
+# Copyright (C) 1996, 1997, 1998, 1999, 2000, 2003, 2004
+# Free Software Foundation, Inc.
+# Contributed by Cygnus Support.
+#
+# This file is part of GDB, the GNU debugger.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License along
+# with this program; if not, write to the Free Software Foundation, Inc.,
+# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+## COMMON_PRE_CONFIG_FRAG
+
+ARC5_OBJS = arc5.o cpu5.o decode5.o sem5.o model5.o mloop5.o
+ARC6_OBJS = arc6.o cpu6.o decode6.o sem6.o model6.o mloop6.o
+ARC7_OBJS = arc7.o cpu7.o decode7.o sem7.o model7.o mloop7.o
+TRAPS_OBJ = @traps_obj@
+
+CONFIG_DEVICES = dv-sockser.o
+CONFIG_DEVICES =
+
+SIM_OBJS = \
+ $(SIM_NEW_COMMON_OBJS) \
+ sim-cpu.o \
+ sim-hload.o \
+ sim-hrw.o \
+ sim-model.o \
+ sim-reg.o \
+ cgen-utils.o cgen-trace.o cgen-scache.o \
+ cgen-run.o sim-reason.o sim-engine.o sim-stop.o \
+ sim-if.o arch.o \
+ $(ARC5_OBJS) \
+ $(ARC6_OBJS) \
+ $(ARC7_OBJS) \
+ $(TRAPS_OBJ) \
+ devices.o \
+ $(CONFIG_DEVICES)
+
+# Extra headers included by sim-main.h.
+SIM_EXTRA_DEPS = \
+ $(CGEN_INCLUDE_DEPS) \
+ arch.h cpuall.h arc-sim.h $(srcdir)/../../opcodes/arc-desc.h
+
+SIM_EXTRA_CFLAGS = @sim_extra_cflags@
+
+SIM_RUN_OBJS = nrun.o
+SIM_EXTRA_CLEAN = arc-clean
+
+# This selects the arc newlib/libgloss syscall definitions.
+NL_TARGET = -DNL_TARGET_arc
+
+## COMMON_POST_CONFIG_FRAG
+
+arch = arc
+
+sim-if.o: sim-if.c $(SIM_MAIN_DEPS) $(srcdir)/../common/sim-core.h
+
+arch.o: arch.c $(SIM_MAIN_DEPS)
+
+traps.o: traps.c targ-vals.h $(SIM_MAIN_DEPS)
+traps-linux.o: traps.c syscall.h targ-vals.h $(SIM_MAIN_DEPS)
+devices.o: devices.c $(SIM_MAIN_DEPS)
+
+# ARC objs
+
+ARC5_INCLUDE_DEPS = \
+ $(CGEN_MAIN_CPU_DEPS) \
+ cpu5.h decode5.h eng5.h
+
+arc5.o: arc5.c $(ARC5_INCLUDE_DEPS)
+
+# FIXME: Use of `mono' is wip.
+mloop5.c eng5.h: stamp-5mloop
+stamp-5mloop: $(srcdir)/../common/genmloop.sh mloop5.in Makefile
+ $(SHELL) $(srccom)/genmloop.sh \
+ -mono -fast -pbb -switch sem5-switch.c \
+ -cpu a5f -infile $(srcdir)/mloop5.in \
+ -outfile-suffix 5
+ $(SHELL) $(srcroot)/move-if-change eng5.hin eng5.h
+ $(SHELL) $(srcroot)/move-if-change mloop5.cin mloop5.c
+ touch stamp-5mloop
+mloop5.o: mloop5.c sem5-switch.c $(ARC5_INCLUDE_DEPS)
+
+cpu5.o: cpu5.c $(ARCBF_INCLUDE_DEPS)
+decode5.o: decode5.c $(ARCBF_INCLUDE_DEPS)
+sem5.o: sem5.c $(ARCBF_INCLUDE_DEPS)
+model5.o: model5.c $(ARCBF_INCLUDE_DEPS)
+
+# ARC600 objs
+
+ARC600F_INCLUDE_DEPS = \
+ $(CGEN_MAIN_CPU_DEPS) \
+ cpu6.h decode6.h eng6.h
+
+arc6.o: arc6.c $(ARC600F_INCLUDE_DEPS)
+
+# FIXME: Use of `mono' is wip.
+mloop6.c eng6.h: stamp-6mloop
+stamp-6mloop: $(srcdir)/../common/genmloop.sh mloop6.in Makefile
+ $(SHELL) $(srccom)/genmloop.sh \
+ -mono -fast -pbb -switch sem6-switch.c \
+ -cpu arc600f -infile $(srcdir)/mloop6.in \
+ -outfile-suffix 6
+ $(SHELL) $(srcroot)/move-if-change eng6.hin eng6.h
+ $(SHELL) $(srcroot)/move-if-change mloop6.cin mloop6.c
+ touch stamp-6mloop
+mloop6.o: mloop6.c sem6-switch.c $(ARC600F_INCLUDE_DEPS)
+
+cpu6.o: cpu6.c $(ARC600F_INCLUDE_DEPS)
+decode6.o: decode6.c $(ARC600F_INCLUDE_DEPS)
+sem6.o: sem6.c $(ARC600F_INCLUDE_DEPS)
+model6.o: model6.c $(ARC600F_INCLUDE_DEPS)
+
+# ARC700 objs
+
+ARC700F_INCLUDE_DEPS = \
+ $(CGEN_MAIN_CPU_DEPS) \
+ cpu7.h decode7.h eng7.h
+
+arc7.o: arc7.c $(ARC700F_INCLUDE_DEPS)
+
+# FIXME: Use of `mono' is wip.
+mloop7.c eng7.h: stamp-7mloop
+stamp-7mloop: $(srcdir)/../common/genmloop.sh mloop7.in Makefile
+ $(SHELL) $(srccom)/genmloop.sh \
+ -mono -fast -pbb -switch sem7-switch.c \
+ -cpu arc700f -infile $(srcdir)/mloop7.in \
+ -outfile-suffix 7
+ $(SHELL) $(srcroot)/move-if-change eng7.hin eng7.h
+ $(SHELL) $(srcroot)/move-if-change mloop7.cin mloop7.c
+ touch stamp-7mloop
+
+mloop7.o: mloop7.c sem7-switch.c $(ARC700F_INCLUDE_DEPS)
+cpu7.o: cpu7.c $(ARC700F_INCLUDE_DEPS)
+decode7.o: decode7.c $(ARC700F_INCLUDE_DEPS)
+sem7.o: sem7.c $(ARC700F_INCLUDE_DEPS)
+model7.o: model7.c $(ARC700F_INCLUDE_DEPS)
+
+arc-clean:
+ rm -f mloop5.c eng5.h stamp-5mloop
+ rm -f mloop6.c eng6.h stamp-6mloop
+ rm -f mloop7.c eng7.h stamp-7mloop
+ rm -f stamp-arch stamp-5cpu stamp-6cpu stamp-7cpu
+ rm -f tmp-*
+
+# cgen support, enable with --enable-cgen-maint
+CGEN_MAINT = ; @true
+# The following line is commented in or out depending upon --enable-cgen-maint.
+@CGEN_MAINT@CGEN_MAINT =
+
+stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) $(CGEN_CPU_DIR)/arc.cpu
+ $(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) mach=all \
+ archfile=$(CGEN_CPU_DIR)/arc.cpu \
+ FLAGS="with-scache with-profile=fn"
+ touch stamp-arch
+arch.h arch.c cpuall.h: $(CGEN_MAINT) stamp-arch
+
+stamp-5cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/arc.cpu
+ $(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
+ cpu=a5f mach=a5 SUFFIX=5 \
+ archfile=$(CGEN_CPU_DIR)/arc.cpu \
+ FLAGS="with-scache with-profile=fn" \
+ EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"
+ touch stamp-5cpu
+cpu5.h sem5.c sem5-switch.c model5.c decode5.c decode5.h: $(CGEN_MAINT) stamp-5cpu
+
+stamp-6cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/arc.cpu
+ $(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
+ cpu=arc600f mach=arc600 SUFFIX=6 \
+ archfile=$(CGEN_CPU_DIR)/arc.cpu \
+ FLAGS="with-scache with-profile=fn" \
+ EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"
+ touch stamp-6cpu
+cpu6.h sem6.c sem6-switch.c model6.c decode6.c decode6.h: $(CGEN_MAINT) stamp-6cpu
+
+stamp-7cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/arc.cpu
+ $(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
+ cpu=arc700f mach=arc700 SUFFIX=7 \
+ archfile=$(CGEN_CPU_DIR)/arc.cpu \
+ FLAGS="with-scache with-profile=fn" \
+ EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"
+ touch stamp-7cpu
+cpu7.h sem7.c sem7-switch.c model7.c decode7.c decode7.h: $(CGEN_MAINT) stamp-7cpu
diff --git a/sim/arc/arc-sim.h b/sim/arc/arc-sim.h
new file mode 100644
index 0000000..0eb9bf7
--- /dev/null
+++ b/sim/arc/arc-sim.h
@@ -0,0 +1,124 @@
+/* collection of junk waiting time to sort out
+ Copyright (C) 1996, 1997, 1998, 2003 Free Software Foundation, Inc.
+ Contributed by Cygnus Support.
+
+ This file is part of GDB, the GNU debugger.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2, or (at your option)
+ any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+#ifndef ARC_SIM_H
+#define ARC_SIM_H
+
+/* GDB register numbers. */
+#define STATUS32_REGNUM 61
+#define PC_REGNUM 63
+#define AUX0_REGNUM 64
+#define AUXLAST_REGNUM 2111
+
+extern int arc_decode_gdb_ctrl_regnum (int);
+
+
+/* Misc. profile data. */
+
+typedef struct {
+ /* nop insn slot filler count */
+ unsigned int fillnop_count;
+ /* number of parallel insns */
+ unsigned int parallel_count;
+
+ /* FIXME: generalize this to handle all insn lengths, move to common. */
+ /* number of short insns, not including parallel ones */
+ unsigned int short_count;
+ /* number of long insns */
+ unsigned int long_count;
+
+ /* Working area for computing cycle counts. */
+ unsigned long insn_cycles; /* FIXME: delete */
+ unsigned long cti_stall;
+ unsigned long load_stall;
+ unsigned long biggest_cycles;
+
+ /* Bitmask of registers loaded by previous insn. */
+ unsigned int load_regs;
+ /* Bitmask of registers loaded by current insn. */
+ unsigned int load_regs_pending;
+} ARC_MISC_PROFILE;
+
+/* Initialize the working area. */
+void arc_init_insn_cycles (SIM_CPU *, int);
+/* Update the totals for the insn. */
+void arc_record_insn_cycles (SIM_CPU *, int);
+
+/* This is invoked by the nop pattern in the .cpu file. */
+#define PROFILE_COUNT_FILLNOPS(cpu, addr) \
+do { \
+ if (PROFILE_INSN_P (cpu) \
+ && (addr & 3) != 0) \
+ ++ CPU_ARC_MISC_PROFILE (cpu)->fillnop_count; \
+} while (0)
+
+/* This is invoked by the execute section of mloop{,x}.in. */
+#define PROFILE_COUNT_PARINSNS(cpu) \
+do { \
+ if (PROFILE_INSN_P (cpu)) \
+ ++ CPU_ARC_MISC_PROFILE (cpu)->parallel_count; \
+} while (0)
+
+/* This is invoked by the execute section of mloop{,x}.in. */
+#define PROFILE_COUNT_SHORTINSNS(cpu) \
+do { \
+ if (PROFILE_INSN_P (cpu)) \
+ ++ CPU_ARC_MISC_PROFILE (cpu)->short_count; \
+} while (0)
+
+/* This is invoked by the execute section of mloop{,x}.in. */
+#define PROFILE_COUNT_LONGINSNS(cpu) \
+do { \
+ if (PROFILE_INSN_P (cpu)) \
+ ++ CPU_ARC_MISC_PROFILE (cpu)->long_count; \
+} while (0)
+
+#define GETTWI GETTSI
+#define SETTWI SETTSI
+
+/* Additional execution support. */
+
+
+/* Hardware/device support.
+ ??? Will eventually want to move device stuff to config files. */
+
+/* Exception, Interrupt, and Trap addresses */
+#define EIT_SYSBREAK_ADDR 0x10
+#define EIT_RSVD_INSN_ADDR 0x20
+#define EIT_ADDR_EXCP_ADDR 0x30
+#define EIT_TRAP_BASE_ADDR 0x40
+#define EIT_EXTERN_ADDR 0x80
+#define EIT_RESET_ADDR 0x7ffffff0
+#define EIT_WAKEUP_ADDR 0x7ffffff0
+
+/* Special purpose traps. */
+#define TRAP_SYSCALL 1
+#define TRAP_BREAKPOINT 0
+
+/* sim_core_attach device argument. */
+extern device arc_devices;
+
+/* FIXME: Temporary, until device support ready. */
+struct _device { int foo; };
+
+/* Handle the trap insn. */
+USI arc_trap (SIM_CPU *, PCADDR, int, int);
+
+#endif /* ARC_SIM_H */
diff --git a/sim/arc/arc5.c b/sim/arc/arc5.c
new file mode 100644
index 0000000..8283ea5
--- /dev/null
+++ b/sim/arc/arc5.c
@@ -0,0 +1,108 @@
+/* arc simulator support code
+ Copyright (C) 1996, 1997, 1998, 2003, 2007 Free Software Foundation, Inc.
+
+ This file is part of GDB, the GNU debugger.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2, or (at your option)
+ any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+#define WANT_CPU a5f
+#define WANT_CPU_A5F
+
+#include "sim-main.h"
+#include "cgen-mem.h"
+#include "cgen-ops.h"
+
+/* The contents of BUF are in target byte order. */
+
+int
+a5f_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf,
+ int len)
+{
+ if (rn < 61)
+ SETTWI (buf, a5f_h_cr_get (current_cpu, rn));
+ else if (rn >= AUX0_REGNUM && rn <= AUXLAST_REGNUM)
+ SETTWI (buf, a5f_h_auxr_get (current_cpu, rn - AUX0_REGNUM));
+ else
+ switch (rn)
+ {
+ case PC_REGNUM :
+ SETTWI (buf, a5f_h_pc_get (current_cpu));
+ break;
+ case STATUS32_REGNUM :
+ SETTWI (buf, a5f_h_auxr_get (current_cpu, 10));
+ break;
+ default :
+ return 0;
+ }
+
+ return -1; /*FIXME*/
+}
+
+/* The contents of BUF are in target byte order. */
+
+int
+a5f_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf,
+ int len)
+{
+ if (rn < 61)
+ a5f_h_cr_set (current_cpu, rn, GETTWI (buf));
+ else if (rn >= AUX0_REGNUM && rn <= AUXLAST_REGNUM)
+ a5f_h_auxr_set (current_cpu, rn - AUX0_REGNUM, GETTWI (buf));
+ else
+ switch (rn)
+ {
+ case PC_REGNUM :
+ a5f_h_pc_set (current_cpu, GETTWI (buf));
+ break;
+ case STATUS32_REGNUM :
+ a5f_h_auxr_set (current_cpu, 10, GETTWI (buf));
+ break;
+ default :
+ return 0;
+ }
+
+ return -1; /*FIXME*/
+}
+
+/* Initialize cycle counting for an insn.
+ FIRST_P is non-zero if this is the first insn in a set of parallel
+ insns. */
+
+void
+a5f_model_insn_before (SIM_CPU *cpu, int first_p)
+{
+}
+
+/* Record the cycles computed for an insn.
+ LAST_P is non-zero if this is the last insn in a set of parallel insns,
+ and we update the total cycle count.
+ CYCLES is the cycle count of the insn. */
+
+void
+a5f_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)
+{
+}
+
+int
+a5f_model_A5_u_exec (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT sr, INT sr2, INT dr)
+{
+#if 0
+ check_load_stall (cpu, sr);
+ check_load_stall (cpu, sr2);
+#endif
+ return idesc->timing->units[unit_num].done;
+}
diff --git a/sim/arc/arc6.c b/sim/arc/arc6.c
new file mode 100644
index 0000000..4b3de1b
--- /dev/null
+++ b/sim/arc/arc6.c
@@ -0,0 +1,74 @@
+/* arc simulator support code
+ Copyright (C) 1996, 1997, 1998, 2003, 2007 Free Software Foundation, Inc.
+
+ This file is part of GDB, the GNU debugger.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2, or (at your option)
+ any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+#define WANT_CPU arc600f
+#define WANT_CPU_ARC600F
+
+#include "sim-main.h"
+#include "cgen-mem.h"
+#include "cgen-ops.h"
+
+/* The contents of BUF are in target byte order. */
+
+int
+arc600f_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf,
+ int len)
+{
+ return a5f_fetch_register (current_cpu, rn, buf, len);
+}
+
+/* The contents of BUF are in target byte order. */
+
+int
+arc600f_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf,
+ int len)
+{
+ return a5f_store_register (current_cpu, rn, buf, len);
+}
+
+/* Initialize cycle counting for an insn.
+ FIRST_P is non-zero if this is the first insn in a set of parallel
+ insns. */
+
+void
+arc600f_model_insn_before (SIM_CPU *cpu, int first_p)
+{
+}
+
+/* Record the cycles computed for an insn.
+ LAST_P is non-zero if this is the last insn in a set of parallel insns,
+ and we update the total cycle count.
+ CYCLES is the cycle count of the insn. */
+
+void
+arc600f_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)
+{
+}
+
+int
+arc600f_model_ARC600_u_exec (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT sr, INT sr2, INT dr)
+{
+#if 0
+ check_load_stall (cpu, sr);
+ check_load_stall (cpu, sr2);
+#endif
+ return idesc->timing->units[unit_num].done;
+}
diff --git a/sim/arc/arc7.c b/sim/arc/arc7.c
new file mode 100644
index 0000000..5d612d0
--- /dev/null
+++ b/sim/arc/arc7.c
@@ -0,0 +1,74 @@
+/* arc simulator support code
+ Copyright (C) 1996, 1997, 1998, 2003, 2007 Free Software Foundation, Inc.
+
+ This file is part of GDB, the GNU debugger.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2, or (at your option)
+ any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+#define WANT_CPU arc700f
+#define WANT_CPU_ARC700F
+
+#include "sim-main.h"
+#include "cgen-mem.h"
+#include "cgen-ops.h"
+
+/* The contents of BUF are in target byte order. */
+
+int
+arc700f_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf,
+ int len)
+{
+ return a5f_fetch_register (current_cpu, rn, buf, len);
+}
+
+/* The contents of BUF are in target byte order. */
+
+int
+arc700f_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf,
+ int len)
+{
+ return a5f_store_register (current_cpu, rn, buf, len);
+}
+
+/* Initialize cycle counting for an insn.
+ FIRST_P is non-zero if this is the first insn in a set of parallel
+ insns. */
+
+void
+arc700f_model_insn_before (SIM_CPU *cpu, int first_p)
+{
+}
+
+/* Record the cycles computed for an insn.
+ LAST_P is non-zero if this is the last insn in a set of parallel insns,
+ and we update the total cycle count.
+ CYCLES is the cycle count of the insn. */
+
+void
+arc700f_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)
+{
+}
+
+int
+arc700f_model_ARC700_u_exec (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT sr, INT sr2, INT dr)
+{
+#if 0
+ check_load_stall (cpu, sr);
+ check_load_stall (cpu, sr2);
+#endif
+ return idesc->timing->units[unit_num].done;
+}
diff --git a/sim/arc/arch.c b/sim/arc/arch.c
new file mode 100644
index 0000000..bd52fa8
--- /dev/null
+++ b/sim/arc/arch.c
@@ -0,0 +1,41 @@
+/* Simulator support for arc.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2007 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#include "sim-main.h"
+#include "bfd.h"
+
+const MACH *sim_machs[] =
+{
+#ifdef HAVE_CPU_A5F
+ & a5_mach,
+#endif
+#ifdef HAVE_CPU_ARC600F
+ & arc600_mach,
+#endif
+#ifdef HAVE_CPU_ARC700F
+ & arc700_mach,
+#endif
+ 0
+};
+
diff --git a/sim/arc/arch.h b/sim/arc/arch.h
new file mode 100644
index 0000000..2ee1539
--- /dev/null
+++ b/sim/arc/arch.h
@@ -0,0 +1,45 @@
+/* Simulator header for arc.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2007 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#ifndef ARC_ARCH_H
+#define ARC_ARCH_H
+
+#define TARGET_BIG_ENDIAN 1
+
+/* Enum declaration for model types. */
+typedef enum model_type {
+ MODEL_A5, MODEL_ARC600, MODEL_ARC700, MODEL_MAX
+} MODEL_TYPE;
+
+#define MAX_MODELS ((int) MODEL_MAX)
+
+/* Enum declaration for unit types. */
+typedef enum unit_type {
+ UNIT_NONE, UNIT_A5_U_EXEC, UNIT_ARC600_U_EXEC, UNIT_ARC700_U_EXEC
+ , UNIT_MAX
+} UNIT_TYPE;
+
+#define MAX_UNITS (1)
+
+#endif /* ARC_ARCH_H */
diff --git a/sim/arc/config.in b/sim/arc/config.in
new file mode 100644
index 0000000..350b19e
--- /dev/null
+++ b/sim/arc/config.in
@@ -0,0 +1,96 @@
+/* config.in. Generated from configure.ac by autoheader. */
+
+/* Define to 1 if translation of program messages to the user's native
+ language is requested. */
+#undef ENABLE_NLS
+
+/* Define to 1 if you have the <dlfcn.h> header file. */
+#undef HAVE_DLFCN_H
+
+/* Define to 1 if you have the <errno.h> header file. */
+#undef HAVE_ERRNO_H
+
+/* Define to 1 if you have the <fcntl.h> header file. */
+#undef HAVE_FCNTL_H
+
+/* Define to 1 if you have the <fpu_control.h> header file. */
+#undef HAVE_FPU_CONTROL_H
+
+/* Define to 1 if you have the `getrusage' function. */
+#undef HAVE_GETRUSAGE
+
+/* Define to 1 if you have the <inttypes.h> header file. */
+#undef HAVE_INTTYPES_H
+
+/* Define to 1 if you have the `nsl' library (-lnsl). */
+#undef HAVE_LIBNSL
+
+/* Define to 1 if you have the `socket' library (-lsocket). */
+#undef HAVE_LIBSOCKET
+
+/* Define to 1 if you have the <memory.h> header file. */
+#undef HAVE_MEMORY_H
+
+/* Define to 1 if you have the `sigaction' function. */
+#undef HAVE_SIGACTION
+
+/* Define to 1 if you have the <stdint.h> header file. */
+#undef HAVE_STDINT_H
+
+/* Define to 1 if you have the <stdlib.h> header file. */
+#undef HAVE_STDLIB_H
+
+/* Define to 1 if you have the <strings.h> header file. */
+#undef HAVE_STRINGS_H
+
+/* Define to 1 if you have the <string.h> header file. */
+#undef HAVE_STRING_H
+
+/* Define to 1 if you have the <sys/resource.h> header file. */
+#undef HAVE_SYS_RESOURCE_H
+
+/* Define to 1 if you have the <sys/stat.h> header file. */
+#undef HAVE_SYS_STAT_H
+
+/* Define to 1 if you have the <sys/time.h> header file. */
+#undef HAVE_SYS_TIME_H
+
+/* Define to 1 if you have the <sys/types.h> header file. */
+#undef HAVE_SYS_TYPES_H
+
+/* Define to 1 if you have the `time' function. */
+#undef HAVE_TIME
+
+/* Define to 1 if you have the <time.h> header file. */
+#undef HAVE_TIME_H
+
+/* Define to 1 if you have the <unistd.h> header file. */
+#undef HAVE_UNISTD_H
+
+/* Define to 1 if you have the `__setfpucw' function. */
+#undef HAVE___SETFPUCW
+
+/* Define to the address where bug reports for this package should be sent. */
+#undef PACKAGE_BUGREPORT
+
+/* Define to the full name of this package. */
+#undef PACKAGE_NAME
+
+/* Define to the full name and version of this package. */
+#undef PACKAGE_STRING
+
+/* Define to the one symbol short name of this package. */
+#undef PACKAGE_TARNAME
+
+/* Define to the version of this package. */
+#undef PACKAGE_VERSION
+
+/* Define as the return type of signal handlers (`int' or `void'). */
+#undef RETSIGTYPE
+
+/* Define to 1 if you have the ANSI C header files. */
+#undef STDC_HEADERS
+
+/* Define to 1 if your processor stores words with the most significant byte
+ first (like Motorola and SPARC, unlike Intel and VAX). */
+#undef WORDS_BIGENDIAN
diff --git a/sim/arc/configure b/sim/arc/configure
new file mode 100644
index 0000000..c62c442
--- /dev/null
+++ b/sim/arc/configure
@@ -0,0 +1,6285 @@
+#! /bin/sh
+# Guess values for system-dependent variables and create Makefiles.
+# Generated by GNU Autoconf 2.59.
+#
+# Copyright (C) 2003 Free Software Foundation, Inc.
+# This configure script is free software; the Free Software Foundation
+# gives unlimited permission to copy, distribute and modify it.
+## --------------------- ##
+## M4sh Initialization. ##
+## --------------------- ##
+
+# Be Bourne compatible
+if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then
+ emulate sh
+ NULLCMD=:
+ # Zsh 3.x and 4.x performs word splitting on ${1+"$@"}, which
+ # is contrary to our usage. Disable this feature.
+ alias -g '${1+"$@"}'='"$@"'
+elif test -n "${BASH_VERSION+set}" && (set -o posix) >/dev/null 2>&1; then
+ set -o posix
+fi
+DUALCASE=1; export DUALCASE # for MKS sh
+
+# Support unset when possible.
+if ( (MAIL=60; unset MAIL) || exit) >/dev/null 2>&1; then
+ as_unset=unset
+else
+ as_unset=false
+fi
+
+
+# Work around bugs in pre-3.0 UWIN ksh.
+$as_unset ENV MAIL MAILPATH
+PS1='$ '
+PS2='> '
+PS4='+ '
+
+# NLS nuisances.
+for as_var in \
+ LANG LANGUAGE LC_ADDRESS LC_ALL LC_COLLATE LC_CTYPE LC_IDENTIFICATION \
+ LC_MEASUREMENT LC_MESSAGES LC_MONETARY LC_NAME LC_NUMERIC LC_PAPER \
+ LC_TELEPHONE LC_TIME
+do
+ if (set +x; test -z "`(eval $as_var=C; export $as_var) 2>&1`"); then
+ eval $as_var=C; export $as_var
+ else
+ $as_unset $as_var
+ fi
+done
+
+# Required to use basename.
+if expr a : '\(a\)' >/dev/null 2>&1; then
+ as_expr=expr
+else
+ as_expr=false
+fi
+
+if (basename /) >/dev/null 2>&1 && test "X`basename / 2>&1`" = "X/"; then
+ as_basename=basename
+else
+ as_basename=false
+fi
+
+
+# Name of the executable.
+as_me=`$as_basename "$0" ||
+$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \
+ X"$0" : 'X\(//\)$' \| \
+ X"$0" : 'X\(/\)$' \| \
+ . : '\(.\)' 2>/dev/null ||
+echo X/"$0" |
+ sed '/^.*\/\([^/][^/]*\)\/*$/{ s//\1/; q; }
+ /^X\/\(\/\/\)$/{ s//\1/; q; }
+ /^X\/\(\/\).*/{ s//\1/; q; }
+ s/.*/./; q'`
+
+
+# PATH needs CR, and LINENO needs CR and PATH.
+# Avoid depending upon Character Ranges.
+as_cr_letters='abcdefghijklmnopqrstuvwxyz'
+as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ'
+as_cr_Letters=$as_cr_letters$as_cr_LETTERS
+as_cr_digits='0123456789'
+as_cr_alnum=$as_cr_Letters$as_cr_digits
+
+# The user is always right.
+if test "${PATH_SEPARATOR+set}" != set; then
+ echo "#! /bin/sh" >conf$$.sh
+ echo "exit 0" >>conf$$.sh
+ chmod +x conf$$.sh
+ if (PATH="/nonexistent;."; conf$$.sh) >/dev/null 2>&1; then
+ PATH_SEPARATOR=';'
+ else
+ PATH_SEPARATOR=:
+ fi
+ rm -f conf$$.sh
+fi
+
+
+ as_lineno_1=$LINENO
+ as_lineno_2=$LINENO
+ as_lineno_3=`(expr $as_lineno_1 + 1) 2>/dev/null`
+ test "x$as_lineno_1" != "x$as_lineno_2" &&
+ test "x$as_lineno_3" = "x$as_lineno_2" || {
+ # Find who we are. Look in the path if we contain no path at all
+ # relative or not.
+ case $0 in
+ *[\\/]* ) as_myself=$0 ;;
+ *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break
+done
+
+ ;;
+ esac
+ # We did not find ourselves, most probably we were run as `sh COMMAND'
+ # in which case we are not to be found in the path.
+ if test "x$as_myself" = x; then
+ as_myself=$0
+ fi
+ if test ! -f "$as_myself"; then
+ { echo "$as_me: error: cannot find myself; rerun with an absolute path" >&2
+ { (exit 1); exit 1; }; }
+ fi
+ case $CONFIG_SHELL in
+ '')
+ as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in /bin$PATH_SEPARATOR/usr/bin$PATH_SEPARATOR$PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ for as_base in sh bash ksh sh5; do
+ case $as_dir in
+ /*)
+ if ("$as_dir/$as_base" -c '
+ as_lineno_1=$LINENO
+ as_lineno_2=$LINENO
+ as_lineno_3=`(expr $as_lineno_1 + 1) 2>/dev/null`
+ test "x$as_lineno_1" != "x$as_lineno_2" &&
+ test "x$as_lineno_3" = "x$as_lineno_2" ') 2>/dev/null; then
+ $as_unset BASH_ENV || test "${BASH_ENV+set}" != set || { BASH_ENV=; export BASH_ENV; }
+ $as_unset ENV || test "${ENV+set}" != set || { ENV=; export ENV; }
+ CONFIG_SHELL=$as_dir/$as_base
+ export CONFIG_SHELL
+ exec "$CONFIG_SHELL" "$0" ${1+"$@"}
+ fi;;
+ esac
+ done
+done
+;;
+ esac
+
+ # Create $as_me.lineno as a copy of $as_myself, but with $LINENO
+ # uniformly replaced by the line number. The first 'sed' inserts a
+ # line-number line before each line; the second 'sed' does the real
+ # work. The second script uses 'N' to pair each line-number line
+ # with the numbered line, and appends trailing '-' during
+ # substitution so that $LINENO is not a special case at line end.
+ # (Raja R Harinath suggested sed '=', and Paul Eggert wrote the
+ # second 'sed' script. Blame Lee E. McMahon for sed's syntax. :-)
+ sed '=' <$as_myself |
+ sed '
+ N
+ s,$,-,
+ : loop
+ s,^\(['$as_cr_digits']*\)\(.*\)[$]LINENO\([^'$as_cr_alnum'_]\),\1\2\1\3,
+ t loop
+ s,-$,,
+ s,^['$as_cr_digits']*\n,,
+ ' >$as_me.lineno &&
+ chmod +x $as_me.lineno ||
+ { echo "$as_me: error: cannot create $as_me.lineno; rerun with a POSIX shell" >&2
+ { (exit 1); exit 1; }; }
+
+ # Don't try to exec as it changes $[0], causing all sort of problems
+ # (the dirname of $[0] is not the place where we might find the
+ # original and so on. Autoconf is especially sensible to this).
+ . ./$as_me.lineno
+ # Exit status is that of the last command.
+ exit
+}
+
+
+case `echo "testing\c"; echo 1,2,3`,`echo -n testing; echo 1,2,3` in
+ *c*,-n*) ECHO_N= ECHO_C='
+' ECHO_T=' ' ;;
+ *c*,* ) ECHO_N=-n ECHO_C= ECHO_T= ;;
+ *) ECHO_N= ECHO_C='\c' ECHO_T= ;;
+esac
+
+if expr a : '\(a\)' >/dev/null 2>&1; then
+ as_expr=expr
+else
+ as_expr=false
+fi
+
+rm -f conf$$ conf$$.exe conf$$.file
+echo >conf$$.file
+if ln -s conf$$.file conf$$ 2>/dev/null; then
+ # We could just check for DJGPP; but this test a) works b) is more generic
+ # and c) will remain valid once DJGPP supports symlinks (DJGPP 2.04).
+ if test -f conf$$.exe; then
+ # Don't use ln at all; we don't have any links
+ as_ln_s='cp -p'
+ else
+ as_ln_s='ln -s'
+ fi
+elif ln conf$$.file conf$$ 2>/dev/null; then
+ as_ln_s=ln
+else
+ as_ln_s='cp -p'
+fi
+rm -f conf$$ conf$$.exe conf$$.file
+
+if mkdir -p . 2>/dev/null; then
+ as_mkdir_p=:
+else
+ test -d ./-p && rmdir ./-p
+ as_mkdir_p=false
+fi
+
+as_executable_p="test -f"
+
+# Sed expression to map a string onto a valid CPP name.
+as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'"
+
+# Sed expression to map a string onto a valid variable name.
+as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'"
+
+
+# IFS
+# We need space, tab and new line, in precisely that order.
+as_nl='
+'
+IFS=" $as_nl"
+
+# CDPATH.
+$as_unset CDPATH
+
+
+# Name of the host.
+# hostname on some systems (SVR3.2, Linux) returns a bogus exit status,
+# so uname gets run too.
+ac_hostname=`(hostname || uname -n) 2>/dev/null | sed 1q`
+
+exec 6>&1
+
+#
+# Initializations.
+#
+ac_default_prefix=/usr/local
+ac_config_libobj_dir=.
+cross_compiling=no
+subdirs=
+MFLAGS=
+MAKEFLAGS=
+SHELL=${CONFIG_SHELL-/bin/sh}
+
+# Maximum number of lines to put in a shell here document.
+# This variable seems obsolete. It should probably be removed, and
+# only ac_max_sed_lines should be used.
+: ${ac_max_here_lines=38}
+
+# Identity of this package.
+PACKAGE_NAME=
+PACKAGE_TARNAME=
+PACKAGE_VERSION=
+PACKAGE_STRING=
+PACKAGE_BUGREPORT=
+
+ac_unique_file="Makefile.in"
+# Factoring default headers for most tests.
+ac_includes_default="\
+#include <stdio.h>
+#if HAVE_SYS_TYPES_H
+# include <sys/types.h>
+#endif
+#if HAVE_SYS_STAT_H
+# include <sys/stat.h>
+#endif
+#if STDC_HEADERS
+# include <stdlib.h>
+# include <stddef.h>
+#else
+# if HAVE_STDLIB_H
+# include <stdlib.h>
+# endif
+#endif
+#if HAVE_STRING_H
+# if !STDC_HEADERS && HAVE_MEMORY_H
+# include <memory.h>
+# endif
+# include <string.h>
+#endif
+#if HAVE_STRINGS_H
+# include <strings.h>
+#endif
+#if HAVE_INTTYPES_H
+# include <inttypes.h>
+#else
+# if HAVE_STDINT_H
+# include <stdint.h>
+# endif
+#endif
+#if HAVE_UNISTD_H
+# include <unistd.h>
+#endif"
+
+ac_subst_vars='SHELL PATH_SEPARATOR PACKAGE_NAME PACKAGE_TARNAME PACKAGE_VERSION PACKAGE_STRING PACKAGE_BUGREPORT exec_prefix prefix program_transform_name bindir sbindir libexecdir datadir sysconfdir sharedstatedir localstatedir libdir includedir oldincludedir infodir mandir build_alias host_alias target_alias DEFS ECHO_C ECHO_N ECHO_T LIBS sim_environment sim_alignment sim_assert sim_bitsize sim_endian sim_hostendian sim_float sim_scache sim_default_model sim_hw_cflags sim_hw_objs sim_hw sim_inline sim_packages sim_regparm sim_reserved_bits sim_smp sim_stdcall sim_xor_endian WARN_CFLAGS WERROR_CFLAGS build build_cpu build_vendor build_os host host_cpu host_vendor host_os target target_cpu target_vendor target_os CC CFLAGS LDFLAGS CPPFLAGS ac_ct_CC EXEEXT OBJEXT INSTALL_PROGRAM INSTALL_SCRIPT INSTALL_DATA CC_FOR_BUILD HDEFINES AR RANLIB ac_ct_RANLIB USE_NLS LIBINTL LIBINTL_DEP INCINTL XGETTEXT GMSGFMT POSUB CATALOGS DATADIRNAME INSTOBJEXT GENCAT CATOBJEXT CPP EGREP MAINT sim_bswap sim_cflags sim_debug sim_stdio sim_trace sim_profile CGEN_MAINT cgendir cgen traps_obj sim_extra_cflags cgen_breaks LIBOBJS LTLIBOBJS'
+ac_subst_files=''
+
+# Initialize some variables set by options.
+ac_init_help=
+ac_init_version=false
+# The variables have the same names as the options, with
+# dashes changed to underlines.
+cache_file=/dev/null
+exec_prefix=NONE
+no_create=
+no_recursion=
+prefix=NONE
+program_prefix=NONE
+program_suffix=NONE
+program_transform_name=s,x,x,
+silent=
+site=
+srcdir=
+verbose=
+x_includes=NONE
+x_libraries=NONE
+
+# Installation directory options.
+# These are left unexpanded so users can "make install exec_prefix=/foo"
+# and all the variables that are supposed to be based on exec_prefix
+# by default will actually change.
+# Use braces instead of parens because sh, perl, etc. also accept them.
+bindir='${exec_prefix}/bin'
+sbindir='${exec_prefix}/sbin'
+libexecdir='${exec_prefix}/libexec'
+datadir='${prefix}/share'
+sysconfdir='${prefix}/etc'
+sharedstatedir='${prefix}/com'
+localstatedir='${prefix}/var'
+libdir='${exec_prefix}/lib'
+includedir='${prefix}/include'
+oldincludedir='/usr/include'
+infodir='${prefix}/info'
+mandir='${prefix}/man'
+
+ac_prev=
+for ac_option
+do
+ # If the previous option needs an argument, assign it.
+ if test -n "$ac_prev"; then
+ eval "$ac_prev=\$ac_option"
+ ac_prev=
+ continue
+ fi
+
+ ac_optarg=`expr "x$ac_option" : 'x[^=]*=\(.*\)'`
+
+ # Accept the important Cygnus configure options, so we can diagnose typos.
+
+ case $ac_option in
+
+ -bindir | --bindir | --bindi | --bind | --bin | --bi)
+ ac_prev=bindir ;;
+ -bindir=* | --bindir=* | --bindi=* | --bind=* | --bin=* | --bi=*)
+ bindir=$ac_optarg ;;
+
+ -build | --build | --buil | --bui | --bu)
+ ac_prev=build_alias ;;
+ -build=* | --build=* | --buil=* | --bui=* | --bu=*)
+ build_alias=$ac_optarg ;;
+
+ -cache-file | --cache-file | --cache-fil | --cache-fi \
+ | --cache-f | --cache- | --cache | --cach | --cac | --ca | --c)
+ ac_prev=cache_file ;;
+ -cache-file=* | --cache-file=* | --cache-fil=* | --cache-fi=* \
+ | --cache-f=* | --cache-=* | --cache=* | --cach=* | --cac=* | --ca=* | --c=*)
+ cache_file=$ac_optarg ;;
+
+ --config-cache | -C)
+ cache_file=config.cache ;;
+
+ -datadir | --datadir | --datadi | --datad | --data | --dat | --da)
+ ac_prev=datadir ;;
+ -datadir=* | --datadir=* | --datadi=* | --datad=* | --data=* | --dat=* \
+ | --da=*)
+ datadir=$ac_optarg ;;
+
+ -disable-* | --disable-*)
+ ac_feature=`expr "x$ac_option" : 'x-*disable-\(.*\)'`
+ # Reject names that are not valid shell variable names.
+ expr "x$ac_feature" : ".*[^-_$as_cr_alnum]" >/dev/null &&
+ { echo "$as_me: error: invalid feature name: $ac_feature" >&2
+ { (exit 1); exit 1; }; }
+ ac_feature=`echo $ac_feature | sed 's/-/_/g'`
+ eval "enable_$ac_feature=no" ;;
+
+ -enable-* | --enable-*)
+ ac_feature=`expr "x$ac_option" : 'x-*enable-\([^=]*\)'`
+ # Reject names that are not valid shell variable names.
+ expr "x$ac_feature" : ".*[^-_$as_cr_alnum]" >/dev/null &&
+ { echo "$as_me: error: invalid feature name: $ac_feature" >&2
+ { (exit 1); exit 1; }; }
+ ac_feature=`echo $ac_feature | sed 's/-/_/g'`
+ case $ac_option in
+ *=*) ac_optarg=`echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"`;;
+ *) ac_optarg=yes ;;
+ esac
+ eval "enable_$ac_feature='$ac_optarg'" ;;
+
+ -exec-prefix | --exec_prefix | --exec-prefix | --exec-prefi \
+ | --exec-pref | --exec-pre | --exec-pr | --exec-p | --exec- \
+ | --exec | --exe | --ex)
+ ac_prev=exec_prefix ;;
+ -exec-prefix=* | --exec_prefix=* | --exec-prefix=* | --exec-prefi=* \
+ | --exec-pref=* | --exec-pre=* | --exec-pr=* | --exec-p=* | --exec-=* \
+ | --exec=* | --exe=* | --ex=*)
+ exec_prefix=$ac_optarg ;;
+
+ -gas | --gas | --ga | --g)
+ # Obsolete; use --with-gas.
+ with_gas=yes ;;
+
+ -help | --help | --hel | --he | -h)
+ ac_init_help=long ;;
+ -help=r* | --help=r* | --hel=r* | --he=r* | -hr*)
+ ac_init_help=recursive ;;
+ -help=s* | --help=s* | --hel=s* | --he=s* | -hs*)
+ ac_init_help=short ;;
+
+ -host | --host | --hos | --ho)
+ ac_prev=host_alias ;;
+ -host=* | --host=* | --hos=* | --ho=*)
+ host_alias=$ac_optarg ;;
+
+ -includedir | --includedir | --includedi | --included | --include \
+ | --includ | --inclu | --incl | --inc)
+ ac_prev=includedir ;;
+ -includedir=* | --includedir=* | --includedi=* | --included=* | --include=* \
+ | --includ=* | --inclu=* | --incl=* | --inc=*)
+ includedir=$ac_optarg ;;
+
+ -infodir | --infodir | --infodi | --infod | --info | --inf)
+ ac_prev=infodir ;;
+ -infodir=* | --infodir=* | --infodi=* | --infod=* | --info=* | --inf=*)
+ infodir=$ac_optarg ;;
+
+ -libdir | --libdir | --libdi | --libd)
+ ac_prev=libdir ;;
+ -libdir=* | --libdir=* | --libdi=* | --libd=*)
+ libdir=$ac_optarg ;;
+
+ -libexecdir | --libexecdir | --libexecdi | --libexecd | --libexec \
+ | --libexe | --libex | --libe)
+ ac_prev=libexecdir ;;
+ -libexecdir=* | --libexecdir=* | --libexecdi=* | --libexecd=* | --libexec=* \
+ | --libexe=* | --libex=* | --libe=*)
+ libexecdir=$ac_optarg ;;
+
+ -localstatedir | --localstatedir | --localstatedi | --localstated \
+ | --localstate | --localstat | --localsta | --localst \
+ | --locals | --local | --loca | --loc | --lo)
+ ac_prev=localstatedir ;;
+ -localstatedir=* | --localstatedir=* | --localstatedi=* | --localstated=* \
+ | --localstate=* | --localstat=* | --localsta=* | --localst=* \
+ | --locals=* | --local=* | --loca=* | --loc=* | --lo=*)
+ localstatedir=$ac_optarg ;;
+
+ -mandir | --mandir | --mandi | --mand | --man | --ma | --m)
+ ac_prev=mandir ;;
+ -mandir=* | --mandir=* | --mandi=* | --mand=* | --man=* | --ma=* | --m=*)
+ mandir=$ac_optarg ;;
+
+ -nfp | --nfp | --nf)
+ # Obsolete; use --without-fp.
+ with_fp=no ;;
+
+ -no-create | --no-create | --no-creat | --no-crea | --no-cre \
+ | --no-cr | --no-c | -n)
+ no_create=yes ;;
+
+ -no-recursion | --no-recursion | --no-recursio | --no-recursi \
+ | --no-recurs | --no-recur | --no-recu | --no-rec | --no-re | --no-r)
+ no_recursion=yes ;;
+
+ -oldincludedir | --oldincludedir | --oldincludedi | --oldincluded \
+ | --oldinclude | --oldinclud | --oldinclu | --oldincl | --oldinc \
+ | --oldin | --oldi | --old | --ol | --o)
+ ac_prev=oldincludedir ;;
+ -oldincludedir=* | --oldincludedir=* | --oldincludedi=* | --oldincluded=* \
+ | --oldinclude=* | --oldinclud=* | --oldinclu=* | --oldincl=* | --oldinc=* \
+ | --oldin=* | --oldi=* | --old=* | --ol=* | --o=*)
+ oldincludedir=$ac_optarg ;;
+
+ -prefix | --prefix | --prefi | --pref | --pre | --pr | --p)
+ ac_prev=prefix ;;
+ -prefix=* | --prefix=* | --prefi=* | --pref=* | --pre=* | --pr=* | --p=*)
+ prefix=$ac_optarg ;;
+
+ -program-prefix | --program-prefix | --program-prefi | --program-pref \
+ | --program-pre | --program-pr | --program-p)
+ ac_prev=program_prefix ;;
+ -program-prefix=* | --program-prefix=* | --program-prefi=* \
+ | --program-pref=* | --program-pre=* | --program-pr=* | --program-p=*)
+ program_prefix=$ac_optarg ;;
+
+ -program-suffix | --program-suffix | --program-suffi | --program-suff \
+ | --program-suf | --program-su | --program-s)
+ ac_prev=program_suffix ;;
+ -program-suffix=* | --program-suffix=* | --program-suffi=* \
+ | --program-suff=* | --program-suf=* | --program-su=* | --program-s=*)
+ program_suffix=$ac_optarg ;;
+
+ -program-transform-name | --program-transform-name \
+ | --program-transform-nam | --program-transform-na \
+ | --program-transform-n | --program-transform- \
+ | --program-transform | --program-transfor \
+ | --program-transfo | --program-transf \
+ | --program-trans | --program-tran \
+ | --progr-tra | --program-tr | --program-t)
+ ac_prev=program_transform_name ;;
+ -program-transform-name=* | --program-transform-name=* \
+ | --program-transform-nam=* | --program-transform-na=* \
+ | --program-transform-n=* | --program-transform-=* \
+ | --program-transform=* | --program-transfor=* \
+ | --program-transfo=* | --program-transf=* \
+ | --program-trans=* | --program-tran=* \
+ | --progr-tra=* | --program-tr=* | --program-t=*)
+ program_transform_name=$ac_optarg ;;
+
+ -q | -quiet | --quiet | --quie | --qui | --qu | --q \
+ | -silent | --silent | --silen | --sile | --sil)
+ silent=yes ;;
+
+ -sbindir | --sbindir | --sbindi | --sbind | --sbin | --sbi | --sb)
+ ac_prev=sbindir ;;
+ -sbindir=* | --sbindir=* | --sbindi=* | --sbind=* | --sbin=* \
+ | --sbi=* | --sb=*)
+ sbindir=$ac_optarg ;;
+
+ -sharedstatedir | --sharedstatedir | --sharedstatedi \
+ | --sharedstated | --sharedstate | --sharedstat | --sharedsta \
+ | --sharedst | --shareds | --shared | --share | --shar \
+ | --sha | --sh)
+ ac_prev=sharedstatedir ;;
+ -sharedstatedir=* | --sharedstatedir=* | --sharedstatedi=* \
+ | --sharedstated=* | --sharedstate=* | --sharedstat=* | --sharedsta=* \
+ | --sharedst=* | --shareds=* | --shared=* | --share=* | --shar=* \
+ | --sha=* | --sh=*)
+ sharedstatedir=$ac_optarg ;;
+
+ -site | --site | --sit)
+ ac_prev=site ;;
+ -site=* | --site=* | --sit=*)
+ site=$ac_optarg ;;
+
+ -srcdir | --srcdir | --srcdi | --srcd | --src | --sr)
+ ac_prev=srcdir ;;
+ -srcdir=* | --srcdir=* | --srcdi=* | --srcd=* | --src=* | --sr=*)
+ srcdir=$ac_optarg ;;
+
+ -sysconfdir | --sysconfdir | --sysconfdi | --sysconfd | --sysconf \
+ | --syscon | --sysco | --sysc | --sys | --sy)
+ ac_prev=sysconfdir ;;
+ -sysconfdir=* | --sysconfdir=* | --sysconfdi=* | --sysconfd=* | --sysconf=* \
+ | --syscon=* | --sysco=* | --sysc=* | --sys=* | --sy=*)
+ sysconfdir=$ac_optarg ;;
+
+ -target | --target | --targe | --targ | --tar | --ta | --t)
+ ac_prev=target_alias ;;
+ -target=* | --target=* | --targe=* | --targ=* | --tar=* | --ta=* | --t=*)
+ target_alias=$ac_optarg ;;
+
+ -v | -verbose | --verbose | --verbos | --verbo | --verb)
+ verbose=yes ;;
+
+ -version | --version | --versio | --versi | --vers | -V)
+ ac_init_version=: ;;
+
+ -with-* | --with-*)
+ ac_package=`expr "x$ac_option" : 'x-*with-\([^=]*\)'`
+ # Reject names that are not valid shell variable names.
+ expr "x$ac_package" : ".*[^-_$as_cr_alnum]" >/dev/null &&
+ { echo "$as_me: error: invalid package name: $ac_package" >&2
+ { (exit 1); exit 1; }; }
+ ac_package=`echo $ac_package| sed 's/-/_/g'`
+ case $ac_option in
+ *=*) ac_optarg=`echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"`;;
+ *) ac_optarg=yes ;;
+ esac
+ eval "with_$ac_package='$ac_optarg'" ;;
+
+ -without-* | --without-*)
+ ac_package=`expr "x$ac_option" : 'x-*without-\(.*\)'`
+ # Reject names that are not valid shell variable names.
+ expr "x$ac_package" : ".*[^-_$as_cr_alnum]" >/dev/null &&
+ { echo "$as_me: error: invalid package name: $ac_package" >&2
+ { (exit 1); exit 1; }; }
+ ac_package=`echo $ac_package | sed 's/-/_/g'`
+ eval "with_$ac_package=no" ;;
+
+ --x)
+ # Obsolete; use --with-x.
+ with_x=yes ;;
+
+ -x-includes | --x-includes | --x-include | --x-includ | --x-inclu \
+ | --x-incl | --x-inc | --x-in | --x-i)
+ ac_prev=x_includes ;;
+ -x-includes=* | --x-includes=* | --x-include=* | --x-includ=* | --x-inclu=* \
+ | --x-incl=* | --x-inc=* | --x-in=* | --x-i=*)
+ x_includes=$ac_optarg ;;
+
+ -x-libraries | --x-libraries | --x-librarie | --x-librari \
+ | --x-librar | --x-libra | --x-libr | --x-lib | --x-li | --x-l)
+ ac_prev=x_libraries ;;
+ -x-libraries=* | --x-libraries=* | --x-librarie=* | --x-librari=* \
+ | --x-librar=* | --x-libra=* | --x-libr=* | --x-lib=* | --x-li=* | --x-l=*)
+ x_libraries=$ac_optarg ;;
+
+ -*) { echo "$as_me: error: unrecognized option: $ac_option
+Try \`$0 --help' for more information." >&2
+ { (exit 1); exit 1; }; }
+ ;;
+
+ *=*)
+ ac_envvar=`expr "x$ac_option" : 'x\([^=]*\)='`
+ # Reject names that are not valid shell variable names.
+ expr "x$ac_envvar" : ".*[^_$as_cr_alnum]" >/dev/null &&
+ { echo "$as_me: error: invalid variable name: $ac_envvar" >&2
+ { (exit 1); exit 1; }; }
+ ac_optarg=`echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"`
+ eval "$ac_envvar='$ac_optarg'"
+ export $ac_envvar ;;
+
+ *)
+ # FIXME: should be removed in autoconf 3.0.
+ echo "$as_me: WARNING: you should use --build, --host, --target" >&2
+ expr "x$ac_option" : ".*[^-._$as_cr_alnum]" >/dev/null &&
+ echo "$as_me: WARNING: invalid host type: $ac_option" >&2
+ : ${build_alias=$ac_option} ${host_alias=$ac_option} ${target_alias=$ac_option}
+ ;;
+
+ esac
+done
+
+if test -n "$ac_prev"; then
+ ac_option=--`echo $ac_prev | sed 's/_/-/g'`
+ { echo "$as_me: error: missing argument to $ac_option" >&2
+ { (exit 1); exit 1; }; }
+fi
+
+# Be sure to have absolute paths.
+for ac_var in exec_prefix prefix
+do
+ eval ac_val=$`echo $ac_var`
+ case $ac_val in
+ [\\/$]* | ?:[\\/]* | NONE | '' ) ;;
+ *) { echo "$as_me: error: expected an absolute directory name for --$ac_var: $ac_val" >&2
+ { (exit 1); exit 1; }; };;
+ esac
+done
+
+# Be sure to have absolute paths.
+for ac_var in bindir sbindir libexecdir datadir sysconfdir sharedstatedir \
+ localstatedir libdir includedir oldincludedir infodir mandir
+do
+ eval ac_val=$`echo $ac_var`
+ case $ac_val in
+ [\\/$]* | ?:[\\/]* ) ;;
+ *) { echo "$as_me: error: expected an absolute directory name for --$ac_var: $ac_val" >&2
+ { (exit 1); exit 1; }; };;
+ esac
+done
+
+# There might be people who depend on the old broken behavior: `$host'
+# used to hold the argument of --host etc.
+# FIXME: To remove some day.
+build=$build_alias
+host=$host_alias
+target=$target_alias
+
+# FIXME: To remove some day.
+if test "x$host_alias" != x; then
+ if test "x$build_alias" = x; then
+ cross_compiling=maybe
+ echo "$as_me: WARNING: If you wanted to set the --build type, don't use --host.
+ If a cross compiler is detected then cross compile mode will be used." >&2
+ elif test "x$build_alias" != "x$host_alias"; then
+ cross_compiling=yes
+ fi
+fi
+
+ac_tool_prefix=
+test -n "$host_alias" && ac_tool_prefix=$host_alias-
+
+test "$silent" = yes && exec 6>/dev/null
+
+
+# Find the source files, if location was not specified.
+if test -z "$srcdir"; then
+ ac_srcdir_defaulted=yes
+ # Try the directory containing this script, then its parent.
+ ac_confdir=`(dirname "$0") 2>/dev/null ||
+$as_expr X"$0" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
+ X"$0" : 'X\(//\)[^/]' \| \
+ X"$0" : 'X\(//\)$' \| \
+ X"$0" : 'X\(/\)' \| \
+ . : '\(.\)' 2>/dev/null ||
+echo X"$0" |
+ sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
+ /^X\(\/\/\)[^/].*/{ s//\1/; q; }
+ /^X\(\/\/\)$/{ s//\1/; q; }
+ /^X\(\/\).*/{ s//\1/; q; }
+ s/.*/./; q'`
+ srcdir=$ac_confdir
+ if test ! -r $srcdir/$ac_unique_file; then
+ srcdir=..
+ fi
+else
+ ac_srcdir_defaulted=no
+fi
+if test ! -r $srcdir/$ac_unique_file; then
+ if test "$ac_srcdir_defaulted" = yes; then
+ { echo "$as_me: error: cannot find sources ($ac_unique_file) in $ac_confdir or .." >&2
+ { (exit 1); exit 1; }; }
+ else
+ { echo "$as_me: error: cannot find sources ($ac_unique_file) in $srcdir" >&2
+ { (exit 1); exit 1; }; }
+ fi
+fi
+(cd $srcdir && test -r ./$ac_unique_file) 2>/dev/null ||
+ { echo "$as_me: error: sources are in $srcdir, but \`cd $srcdir' does not work" >&2
+ { (exit 1); exit 1; }; }
+srcdir=`echo "$srcdir" | sed 's%\([^\\/]\)[\\/]*$%\1%'`
+ac_env_build_alias_set=${build_alias+set}
+ac_env_build_alias_value=$build_alias
+ac_cv_env_build_alias_set=${build_alias+set}
+ac_cv_env_build_alias_value=$build_alias
+ac_env_host_alias_set=${host_alias+set}
+ac_env_host_alias_value=$host_alias
+ac_cv_env_host_alias_set=${host_alias+set}
+ac_cv_env_host_alias_value=$host_alias
+ac_env_target_alias_set=${target_alias+set}
+ac_env_target_alias_value=$target_alias
+ac_cv_env_target_alias_set=${target_alias+set}
+ac_cv_env_target_alias_value=$target_alias
+ac_env_CC_set=${CC+set}
+ac_env_CC_value=$CC
+ac_cv_env_CC_set=${CC+set}
+ac_cv_env_CC_value=$CC
+ac_env_CFLAGS_set=${CFLAGS+set}
+ac_env_CFLAGS_value=$CFLAGS
+ac_cv_env_CFLAGS_set=${CFLAGS+set}
+ac_cv_env_CFLAGS_value=$CFLAGS
+ac_env_LDFLAGS_set=${LDFLAGS+set}
+ac_env_LDFLAGS_value=$LDFLAGS
+ac_cv_env_LDFLAGS_set=${LDFLAGS+set}
+ac_cv_env_LDFLAGS_value=$LDFLAGS
+ac_env_CPPFLAGS_set=${CPPFLAGS+set}
+ac_env_CPPFLAGS_value=$CPPFLAGS
+ac_cv_env_CPPFLAGS_set=${CPPFLAGS+set}
+ac_cv_env_CPPFLAGS_value=$CPPFLAGS
+ac_env_CPP_set=${CPP+set}
+ac_env_CPP_value=$CPP
+ac_cv_env_CPP_set=${CPP+set}
+ac_cv_env_CPP_value=$CPP
+
+#
+# Report the --help message.
+#
+if test "$ac_init_help" = "long"; then
+ # Omit some internal or obsolete options to make the list less imposing.
+ # This message is too long to be a string in the A/UX 3.1 sh.
+ cat <<_ACEOF
+\`configure' configures this package to adapt to many kinds of systems.
+
+Usage: $0 [OPTION]... [VAR=VALUE]...
+
+To assign environment variables (e.g., CC, CFLAGS...), specify them as
+VAR=VALUE. See below for descriptions of some of the useful variables.
+
+Defaults for the options are specified in brackets.
+
+Configuration:
+ -h, --help display this help and exit
+ --help=short display options specific to this package
+ --help=recursive display the short help of all the included packages
+ -V, --version display version information and exit
+ -q, --quiet, --silent do not print \`checking...' messages
+ --cache-file=FILE cache test results in FILE [disabled]
+ -C, --config-cache alias for \`--cache-file=config.cache'
+ -n, --no-create do not create output files
+ --srcdir=DIR find the sources in DIR [configure dir or \`..']
+
+_ACEOF
+
+ cat <<_ACEOF
+Installation directories:
+ --prefix=PREFIX install architecture-independent files in PREFIX
+ [$ac_default_prefix]
+ --exec-prefix=EPREFIX install architecture-dependent files in EPREFIX
+ [PREFIX]
+
+By default, \`make install' will install all the files in
+\`$ac_default_prefix/bin', \`$ac_default_prefix/lib' etc. You can specify
+an installation prefix other than \`$ac_default_prefix' using \`--prefix',
+for instance \`--prefix=\$HOME'.
+
+For better control, use the options below.
+
+Fine tuning of the installation directories:
+ --bindir=DIR user executables [EPREFIX/bin]
+ --sbindir=DIR system admin executables [EPREFIX/sbin]
+ --libexecdir=DIR program executables [EPREFIX/libexec]
+ --datadir=DIR read-only architecture-independent data [PREFIX/share]
+ --sysconfdir=DIR read-only single-machine data [PREFIX/etc]
+ --sharedstatedir=DIR modifiable architecture-independent data [PREFIX/com]
+ --localstatedir=DIR modifiable single-machine data [PREFIX/var]
+ --libdir=DIR object code libraries [EPREFIX/lib]
+ --includedir=DIR C header files [PREFIX/include]
+ --oldincludedir=DIR C header files for non-gcc [/usr/include]
+ --infodir=DIR info documentation [PREFIX/info]
+ --mandir=DIR man documentation [PREFIX/man]
+_ACEOF
+
+ cat <<\_ACEOF
+
+Program names:
+ --program-prefix=PREFIX prepend PREFIX to installed program names
+ --program-suffix=SUFFIX append SUFFIX to installed program names
+ --program-transform-name=PROGRAM run sed PROGRAM on installed program names
+
+System types:
+ --build=BUILD configure for building on BUILD [guessed]
+ --host=HOST cross-compile to build programs to run on HOST [BUILD]
+ --target=TARGET configure for building compilers for TARGET [HOST]
+_ACEOF
+fi
+
+if test -n "$ac_init_help"; then
+
+ cat <<\_ACEOF
+
+Optional Features:
+ --disable-FEATURE do not include FEATURE (same as --enable-FEATURE=no)
+ --enable-FEATURE[=ARG] include FEATURE [ARG=yes]
+ --enable-maintainer-mode Enable developer functionality.
+ --enable-sim-bswap Use Host specific BSWAP instruction.
+ --enable-sim-cflags=opts Extra CFLAGS for use in building simulator
+ --enable-sim-debug=opts Enable debugging flags
+ --enable-sim-stdio Specify whether to use stdio for console input/output.
+ --enable-sim-trace=opts Enable tracing flags
+ --enable-sim-profile=opts Enable profiling flags
+ --enable-sim-alignment=align Specify strict, nonstrict or forced alignment of memory accesses.
+ --enable-sim-hostendian=end Specify host byte endian orientation.
+ --enable-sim-scache=size Specify simulator execution cache size.
+ --enable-sim-default-model=model Specify default model to simulate.
+ --enable-sim-environment=environment Specify mixed, user, virtual or operating environment.
+ --enable-sim-inline=inlines Specify which functions should be inlined.
+ --enable-cgen-maint=DIR build cgen generated files
+
+Some influential environment variables:
+ CC C compiler command
+ CFLAGS C compiler flags
+ LDFLAGS linker flags, e.g. -L<lib dir> if you have libraries in a
+ nonstandard directory <lib dir>
+ CPPFLAGS C/C++ preprocessor flags, e.g. -I<include dir> if you have
+ headers in a nonstandard directory <include dir>
+ CPP C preprocessor
+
+Use these variables to override the choices made by `configure' or to help
+it to find libraries and programs with nonstandard names/locations.
+
+_ACEOF
+fi
+
+if test "$ac_init_help" = "recursive"; then
+ # If there are subdirs, report their specific --help.
+ ac_popdir=`pwd`
+ for ac_dir in : $ac_subdirs_all; do test "x$ac_dir" = x: && continue
+ test -d $ac_dir || continue
+ ac_builddir=.
+
+if test "$ac_dir" != .; then
+ ac_dir_suffix=/`echo "$ac_dir" | sed 's,^\.[\\/],,'`
+ # A "../" for each directory in $ac_dir_suffix.
+ ac_top_builddir=`echo "$ac_dir_suffix" | sed 's,/[^\\/]*,../,g'`
+else
+ ac_dir_suffix= ac_top_builddir=
+fi
+
+case $srcdir in
+ .) # No --srcdir option. We are building in place.
+ ac_srcdir=.
+ if test -z "$ac_top_builddir"; then
+ ac_top_srcdir=.
+ else
+ ac_top_srcdir=`echo $ac_top_builddir | sed 's,/$,,'`
+ fi ;;
+ [\\/]* | ?:[\\/]* ) # Absolute path.
+ ac_srcdir=$srcdir$ac_dir_suffix;
+ ac_top_srcdir=$srcdir ;;
+ *) # Relative path.
+ ac_srcdir=$ac_top_builddir$srcdir$ac_dir_suffix
+ ac_top_srcdir=$ac_top_builddir$srcdir ;;
+esac
+
+# Do not use `cd foo && pwd` to compute absolute paths, because
+# the directories may not exist.
+case `pwd` in
+.) ac_abs_builddir="$ac_dir";;
+*)
+ case "$ac_dir" in
+ .) ac_abs_builddir=`pwd`;;
+ [\\/]* | ?:[\\/]* ) ac_abs_builddir="$ac_dir";;
+ *) ac_abs_builddir=`pwd`/"$ac_dir";;
+ esac;;
+esac
+case $ac_abs_builddir in
+.) ac_abs_top_builddir=${ac_top_builddir}.;;
+*)
+ case ${ac_top_builddir}. in
+ .) ac_abs_top_builddir=$ac_abs_builddir;;
+ [\\/]* | ?:[\\/]* ) ac_abs_top_builddir=${ac_top_builddir}.;;
+ *) ac_abs_top_builddir=$ac_abs_builddir/${ac_top_builddir}.;;
+ esac;;
+esac
+case $ac_abs_builddir in
+.) ac_abs_srcdir=$ac_srcdir;;
+*)
+ case $ac_srcdir in
+ .) ac_abs_srcdir=$ac_abs_builddir;;
+ [\\/]* | ?:[\\/]* ) ac_abs_srcdir=$ac_srcdir;;
+ *) ac_abs_srcdir=$ac_abs_builddir/$ac_srcdir;;
+ esac;;
+esac
+case $ac_abs_builddir in
+.) ac_abs_top_srcdir=$ac_top_srcdir;;
+*)
+ case $ac_top_srcdir in
+ .) ac_abs_top_srcdir=$ac_abs_builddir;;
+ [\\/]* | ?:[\\/]* ) ac_abs_top_srcdir=$ac_top_srcdir;;
+ *) ac_abs_top_srcdir=$ac_abs_builddir/$ac_top_srcdir;;
+ esac;;
+esac
+
+ cd $ac_dir
+ # Check for guested configure; otherwise get Cygnus style configure.
+ if test -f $ac_srcdir/configure.gnu; then
+ echo
+ $SHELL $ac_srcdir/configure.gnu --help=recursive
+ elif test -f $ac_srcdir/configure; then
+ echo
+ $SHELL $ac_srcdir/configure --help=recursive
+ elif test -f $ac_srcdir/configure.ac ||
+ test -f $ac_srcdir/configure.in; then
+ echo
+ $ac_configure --help
+ else
+ echo "$as_me: WARNING: no configuration information is in $ac_dir" >&2
+ fi
+ cd $ac_popdir
+ done
+fi
+
+test -n "$ac_init_help" && exit 0
+if $ac_init_version; then
+ cat <<\_ACEOF
+
+Copyright (C) 2003 Free Software Foundation, Inc.
+This configure script is free software; the Free Software Foundation
+gives unlimited permission to copy, distribute and modify it.
+_ACEOF
+ exit 0
+fi
+exec 5>config.log
+cat >&5 <<_ACEOF
+This file contains any messages produced by compilers while
+running configure, to aid debugging if configure makes a mistake.
+
+It was created by $as_me, which was
+generated by GNU Autoconf 2.59. Invocation command line was
+
+ $ $0 $@
+
+_ACEOF
+{
+cat <<_ASUNAME
+## --------- ##
+## Platform. ##
+## --------- ##
+
+hostname = `(hostname || uname -n) 2>/dev/null | sed 1q`
+uname -m = `(uname -m) 2>/dev/null || echo unknown`
+uname -r = `(uname -r) 2>/dev/null || echo unknown`
+uname -s = `(uname -s) 2>/dev/null || echo unknown`
+uname -v = `(uname -v) 2>/dev/null || echo unknown`
+
+/usr/bin/uname -p = `(/usr/bin/uname -p) 2>/dev/null || echo unknown`
+/bin/uname -X = `(/bin/uname -X) 2>/dev/null || echo unknown`
+
+/bin/arch = `(/bin/arch) 2>/dev/null || echo unknown`
+/usr/bin/arch -k = `(/usr/bin/arch -k) 2>/dev/null || echo unknown`
+/usr/convex/getsysinfo = `(/usr/convex/getsysinfo) 2>/dev/null || echo unknown`
+hostinfo = `(hostinfo) 2>/dev/null || echo unknown`
+/bin/machine = `(/bin/machine) 2>/dev/null || echo unknown`
+/usr/bin/oslevel = `(/usr/bin/oslevel) 2>/dev/null || echo unknown`
+/bin/universe = `(/bin/universe) 2>/dev/null || echo unknown`
+
+_ASUNAME
+
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ echo "PATH: $as_dir"
+done
+
+} >&5
+
+cat >&5 <<_ACEOF
+
+
+## ----------- ##
+## Core tests. ##
+## ----------- ##
+
+_ACEOF
+
+
+# Keep a trace of the command line.
+# Strip out --no-create and --no-recursion so they do not pile up.
+# Strip out --silent because we don't want to record it for future runs.
+# Also quote any args containing shell meta-characters.
+# Make two passes to allow for proper duplicate-argument suppression.
+ac_configure_args=
+ac_configure_args0=
+ac_configure_args1=
+ac_sep=
+ac_must_keep_next=false
+for ac_pass in 1 2
+do
+ for ac_arg
+ do
+ case $ac_arg in
+ -no-create | --no-c* | -n | -no-recursion | --no-r*) continue ;;
+ -q | -quiet | --quiet | --quie | --qui | --qu | --q \
+ | -silent | --silent | --silen | --sile | --sil)
+ continue ;;
+ *" "*|*" "*|*[\[\]\~\#\$\^\&\*\(\)\{\}\\\|\;\<\>\?\"\']*)
+ ac_arg=`echo "$ac_arg" | sed "s/'/'\\\\\\\\''/g"` ;;
+ esac
+ case $ac_pass in
+ 1) ac_configure_args0="$ac_configure_args0 '$ac_arg'" ;;
+ 2)
+ ac_configure_args1="$ac_configure_args1 '$ac_arg'"
+ if test $ac_must_keep_next = true; then
+ ac_must_keep_next=false # Got value, back to normal.
+ else
+ case $ac_arg in
+ *=* | --config-cache | -C | -disable-* | --disable-* \
+ | -enable-* | --enable-* | -gas | --g* | -nfp | --nf* \
+ | -q | -quiet | --q* | -silent | --sil* | -v | -verb* \
+ | -with-* | --with-* | -without-* | --without-* | --x)
+ case "$ac_configure_args0 " in
+ "$ac_configure_args1"*" '$ac_arg' "* ) continue ;;
+ esac
+ ;;
+ -* ) ac_must_keep_next=true ;;
+ esac
+ fi
+ ac_configure_args="$ac_configure_args$ac_sep'$ac_arg'"
+ # Get rid of the leading space.
+ ac_sep=" "
+ ;;
+ esac
+ done
+done
+$as_unset ac_configure_args0 || test "${ac_configure_args0+set}" != set || { ac_configure_args0=; export ac_configure_args0; }
+$as_unset ac_configure_args1 || test "${ac_configure_args1+set}" != set || { ac_configure_args1=; export ac_configure_args1; }
+
+# When interrupted or exit'd, cleanup temporary files, and complete
+# config.log. We remove comments because anyway the quotes in there
+# would cause problems or look ugly.
+# WARNING: Be sure not to use single quotes in there, as some shells,
+# such as our DU 5.0 friend, will then `close' the trap.
+trap 'exit_status=$?
+ # Save into config.log some information that might help in debugging.
+ {
+ echo
+
+ cat <<\_ASBOX
+## ---------------- ##
+## Cache variables. ##
+## ---------------- ##
+_ASBOX
+ echo
+ # The following way of writing the cache mishandles newlines in values,
+{
+ (set) 2>&1 |
+ case `(ac_space='"'"' '"'"'; set | grep ac_space) 2>&1` in
+ *ac_space=\ *)
+ sed -n \
+ "s/'"'"'/'"'"'\\\\'"'"''"'"'/g;
+ s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='"'"'\\2'"'"'/p"
+ ;;
+ *)
+ sed -n \
+ "s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1=\\2/p"
+ ;;
+ esac;
+}
+ echo
+
+ cat <<\_ASBOX
+## ----------------- ##
+## Output variables. ##
+## ----------------- ##
+_ASBOX
+ echo
+ for ac_var in $ac_subst_vars
+ do
+ eval ac_val=$`echo $ac_var`
+ echo "$ac_var='"'"'$ac_val'"'"'"
+ done | sort
+ echo
+
+ if test -n "$ac_subst_files"; then
+ cat <<\_ASBOX
+## ------------- ##
+## Output files. ##
+## ------------- ##
+_ASBOX
+ echo
+ for ac_var in $ac_subst_files
+ do
+ eval ac_val=$`echo $ac_var`
+ echo "$ac_var='"'"'$ac_val'"'"'"
+ done | sort
+ echo
+ fi
+
+ if test -s confdefs.h; then
+ cat <<\_ASBOX
+## ----------- ##
+## confdefs.h. ##
+## ----------- ##
+_ASBOX
+ echo
+ sed "/^$/d" confdefs.h | sort
+ echo
+ fi
+ test "$ac_signal" != 0 &&
+ echo "$as_me: caught signal $ac_signal"
+ echo "$as_me: exit $exit_status"
+ } >&5
+ rm -f core *.core &&
+ rm -rf conftest* confdefs* conf$$* $ac_clean_files &&
+ exit $exit_status
+ ' 0
+for ac_signal in 1 2 13 15; do
+ trap 'ac_signal='$ac_signal'; { (exit 1); exit 1; }' $ac_signal
+done
+ac_signal=0
+
+# confdefs.h avoids OS command line length limits that DEFS can exceed.
+rm -rf conftest* confdefs.h
+# AIX cpp loses on an empty file, so make sure it contains at least a newline.
+echo >confdefs.h
+
+# Predefined preprocessor variables.
+
+cat >>confdefs.h <<_ACEOF
+#define PACKAGE_NAME "$PACKAGE_NAME"
+_ACEOF
+
+
+cat >>confdefs.h <<_ACEOF
+#define PACKAGE_TARNAME "$PACKAGE_TARNAME"
+_ACEOF
+
+
+cat >>confdefs.h <<_ACEOF
+#define PACKAGE_VERSION "$PACKAGE_VERSION"
+_ACEOF
+
+
+cat >>confdefs.h <<_ACEOF
+#define PACKAGE_STRING "$PACKAGE_STRING"
+_ACEOF
+
+
+cat >>confdefs.h <<_ACEOF
+#define PACKAGE_BUGREPORT "$PACKAGE_BUGREPORT"
+_ACEOF
+
+
+# Let the site file select an alternate cache file if it wants to.
+# Prefer explicitly selected file to automatically selected ones.
+if test -z "$CONFIG_SITE"; then
+ if test "x$prefix" != xNONE; then
+ CONFIG_SITE="$prefix/share/config.site $prefix/etc/config.site"
+ else
+ CONFIG_SITE="$ac_default_prefix/share/config.site $ac_default_prefix/etc/config.site"
+ fi
+fi
+for ac_site_file in $CONFIG_SITE; do
+ if test -r "$ac_site_file"; then
+ { echo "$as_me:$LINENO: loading site script $ac_site_file" >&5
+echo "$as_me: loading site script $ac_site_file" >&6;}
+ sed 's/^/| /' "$ac_site_file" >&5
+ . "$ac_site_file"
+ fi
+done
+
+if test -r "$cache_file"; then
+ # Some versions of bash will fail to source /dev/null (special
+ # files actually), so we avoid doing that.
+ if test -f "$cache_file"; then
+ { echo "$as_me:$LINENO: loading cache $cache_file" >&5
+echo "$as_me: loading cache $cache_file" >&6;}
+ case $cache_file in
+ [\\/]* | ?:[\\/]* ) . $cache_file;;
+ *) . ./$cache_file;;
+ esac
+ fi
+else
+ { echo "$as_me:$LINENO: creating cache $cache_file" >&5
+echo "$as_me: creating cache $cache_file" >&6;}
+ >$cache_file
+fi
+
+# Check that the precious variables saved in the cache have kept the same
+# value.
+ac_cache_corrupted=false
+for ac_var in `(set) 2>&1 |
+ sed -n 's/^ac_env_\([a-zA-Z_0-9]*\)_set=.*/\1/p'`; do
+ eval ac_old_set=\$ac_cv_env_${ac_var}_set
+ eval ac_new_set=\$ac_env_${ac_var}_set
+ eval ac_old_val="\$ac_cv_env_${ac_var}_value"
+ eval ac_new_val="\$ac_env_${ac_var}_value"
+ case $ac_old_set,$ac_new_set in
+ set,)
+ { echo "$as_me:$LINENO: error: \`$ac_var' was set to \`$ac_old_val' in the previous run" >&5
+echo "$as_me: error: \`$ac_var' was set to \`$ac_old_val' in the previous run" >&2;}
+ ac_cache_corrupted=: ;;
+ ,set)
+ { echo "$as_me:$LINENO: error: \`$ac_var' was not set in the previous run" >&5
+echo "$as_me: error: \`$ac_var' was not set in the previous run" >&2;}
+ ac_cache_corrupted=: ;;
+ ,);;
+ *)
+ if test "x$ac_old_val" != "x$ac_new_val"; then
+ { echo "$as_me:$LINENO: error: \`$ac_var' has changed since the previous run:" >&5
+echo "$as_me: error: \`$ac_var' has changed since the previous run:" >&2;}
+ { echo "$as_me:$LINENO: former value: $ac_old_val" >&5
+echo "$as_me: former value: $ac_old_val" >&2;}
+ { echo "$as_me:$LINENO: current value: $ac_new_val" >&5
+echo "$as_me: current value: $ac_new_val" >&2;}
+ ac_cache_corrupted=:
+ fi;;
+ esac
+ # Pass precious variables to config.status.
+ if test "$ac_new_set" = set; then
+ case $ac_new_val in
+ *" "*|*" "*|*[\[\]\~\#\$\^\&\*\(\)\{\}\\\|\;\<\>\?\"\']*)
+ ac_arg=$ac_var=`echo "$ac_new_val" | sed "s/'/'\\\\\\\\''/g"` ;;
+ *) ac_arg=$ac_var=$ac_new_val ;;
+ esac
+ case " $ac_configure_args " in
+ *" '$ac_arg' "*) ;; # Avoid dups. Use of quotes ensures accuracy.
+ *) ac_configure_args="$ac_configure_args '$ac_arg'" ;;
+ esac
+ fi
+done
+if $ac_cache_corrupted; then
+ { echo "$as_me:$LINENO: error: changes in the environment can compromise the build" >&5
+echo "$as_me: error: changes in the environment can compromise the build" >&2;}
+ { { echo "$as_me:$LINENO: error: run \`make distclean' and/or \`rm $cache_file' and start over" >&5
+echo "$as_me: error: run \`make distclean' and/or \`rm $cache_file' and start over" >&2;}
+ { (exit 1); exit 1; }; }
+fi
+
+ac_ext=c
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
+ac_compiler_gnu=$ac_cv_c_compiler_gnu
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ ac_config_headers="$ac_config_headers config.h:config.in"
+
+
+# This file contains common code used by all simulators.
+#
+# SIM_AC_COMMON invokes AC macros used by all simulators and by the common
+# directory. It is intended to be invoked before any target specific stuff.
+# SIM_AC_OUTPUT is a cover function to AC_OUTPUT to generate the Makefile.
+# It is intended to be invoked last.
+#
+# The simulator's configure.in should look like:
+#
+# dnl Process this file with autoconf to produce a configure script.
+# sinclude(../common/aclocal.m4)
+# AC_PREREQ(2.5)dnl
+# AC_INIT(Makefile.in)
+#
+# SIM_AC_COMMON
+#
+# ... target specific stuff ...
+#
+# SIM_AC_OUTPUT
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+sim_inline="-DDEFAULT_INLINE=0"
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+# intl sister-directory configuration rules.
+#
+
+# The idea behind this macro is that there's no need to repeat all the
+# autoconf probes done by the intl directory - it's already done them
+# for us. In fact, there's no need even to look at the cache for the
+# answers. All we need to do is nab a few pieces of information.
+# The intl directory is set up to make this easy, by generating a
+# small file which can be sourced as a shell script; then we produce
+# the necessary substitutions and definitions for this directory.
+
+
+
+
+
+
+
+# Bugs in autoconf 2.59 break the call to SIM_AC_COMMON, hack around
+# it by inlining the macro's contents.
+# This file contains common code used by all simulators.
+#
+# common.m4 invokes AC macros used by all simulators and by the common
+# directory. It is intended to be included before any target specific
+# stuff. SIM_AC_OUTPUT is a cover function to AC_OUTPUT to generate
+# the Makefile. It is intended to be invoked last.
+#
+# The simulator's configure.in should look like:
+#
+# dnl Process this file with autoconf to produce a configure script.
+# AC_PREREQ(2.5)dnl
+# AC_INIT(Makefile.in)
+# AC_CONFIG_HEADER(config.h:config.in)
+#
+# sinclude(../common/aclocal.m4)
+# sinclude(../common/common.m4)
+#
+# ... target specific stuff ...
+
+ac_aux_dir=
+for ac_dir in $srcdir $srcdir/.. $srcdir/../..; do
+ if test -f $ac_dir/install-sh; then
+ ac_aux_dir=$ac_dir
+ ac_install_sh="$ac_aux_dir/install-sh -c"
+ break
+ elif test -f $ac_dir/install.sh; then
+ ac_aux_dir=$ac_dir
+ ac_install_sh="$ac_aux_dir/install.sh -c"
+ break
+ elif test -f $ac_dir/shtool; then
+ ac_aux_dir=$ac_dir
+ ac_install_sh="$ac_aux_dir/shtool install -c"
+ break
+ fi
+done
+if test -z "$ac_aux_dir"; then
+ { { echo "$as_me:$LINENO: error: cannot find install-sh or install.sh in $srcdir $srcdir/.. $srcdir/../.." >&5
+echo "$as_me: error: cannot find install-sh or install.sh in $srcdir $srcdir/.. $srcdir/../.." >&2;}
+ { (exit 1); exit 1; }; }
+fi
+ac_config_guess="$SHELL $ac_aux_dir/config.guess"
+ac_config_sub="$SHELL $ac_aux_dir/config.sub"
+ac_configure="$SHELL $ac_aux_dir/configure" # This should be Cygnus configure.
+
+# Make sure we can run config.sub.
+$ac_config_sub sun4 >/dev/null 2>&1 ||
+ { { echo "$as_me:$LINENO: error: cannot run $ac_config_sub" >&5
+echo "$as_me: error: cannot run $ac_config_sub" >&2;}
+ { (exit 1); exit 1; }; }
+
+echo "$as_me:$LINENO: checking build system type" >&5
+echo $ECHO_N "checking build system type... $ECHO_C" >&6
+if test "${ac_cv_build+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ ac_cv_build_alias=$build_alias
+test -z "$ac_cv_build_alias" &&
+ ac_cv_build_alias=`$ac_config_guess`
+test -z "$ac_cv_build_alias" &&
+ { { echo "$as_me:$LINENO: error: cannot guess build type; you must specify one" >&5
+echo "$as_me: error: cannot guess build type; you must specify one" >&2;}
+ { (exit 1); exit 1; }; }
+ac_cv_build=`$ac_config_sub $ac_cv_build_alias` ||
+ { { echo "$as_me:$LINENO: error: $ac_config_sub $ac_cv_build_alias failed" >&5
+echo "$as_me: error: $ac_config_sub $ac_cv_build_alias failed" >&2;}
+ { (exit 1); exit 1; }; }
+
+fi
+echo "$as_me:$LINENO: result: $ac_cv_build" >&5
+echo "${ECHO_T}$ac_cv_build" >&6
+build=$ac_cv_build
+build_cpu=`echo $ac_cv_build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
+build_vendor=`echo $ac_cv_build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
+build_os=`echo $ac_cv_build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
+
+
+echo "$as_me:$LINENO: checking host system type" >&5
+echo $ECHO_N "checking host system type... $ECHO_C" >&6
+if test "${ac_cv_host+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ ac_cv_host_alias=$host_alias
+test -z "$ac_cv_host_alias" &&
+ ac_cv_host_alias=$ac_cv_build_alias
+ac_cv_host=`$ac_config_sub $ac_cv_host_alias` ||
+ { { echo "$as_me:$LINENO: error: $ac_config_sub $ac_cv_host_alias failed" >&5
+echo "$as_me: error: $ac_config_sub $ac_cv_host_alias failed" >&2;}
+ { (exit 1); exit 1; }; }
+
+fi
+echo "$as_me:$LINENO: result: $ac_cv_host" >&5
+echo "${ECHO_T}$ac_cv_host" >&6
+host=$ac_cv_host
+host_cpu=`echo $ac_cv_host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
+host_vendor=`echo $ac_cv_host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
+host_os=`echo $ac_cv_host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
+
+
+echo "$as_me:$LINENO: checking target system type" >&5
+echo $ECHO_N "checking target system type... $ECHO_C" >&6
+if test "${ac_cv_target+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ ac_cv_target_alias=$target_alias
+test "x$ac_cv_target_alias" = "x" &&
+ ac_cv_target_alias=$ac_cv_host_alias
+ac_cv_target=`$ac_config_sub $ac_cv_target_alias` ||
+ { { echo "$as_me:$LINENO: error: $ac_config_sub $ac_cv_target_alias failed" >&5
+echo "$as_me: error: $ac_config_sub $ac_cv_target_alias failed" >&2;}
+ { (exit 1); exit 1; }; }
+
+fi
+echo "$as_me:$LINENO: result: $ac_cv_target" >&5
+echo "${ECHO_T}$ac_cv_target" >&6
+target=$ac_cv_target
+target_cpu=`echo $ac_cv_target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
+target_vendor=`echo $ac_cv_target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
+target_os=`echo $ac_cv_target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
+
+
+# The aliases save the names the user supplied, while $host etc.
+# will get canonicalized.
+test -n "$target_alias" &&
+ test "$program_prefix$program_suffix$program_transform_name" = \
+ NONENONEs,x,x, &&
+ program_prefix=${target_alias}-
+test "$program_prefix" != NONE &&
+ program_transform_name="s,^,$program_prefix,;$program_transform_name"
+# Use a double $ so make ignores it.
+test "$program_suffix" != NONE &&
+ program_transform_name="s,\$,$program_suffix,;$program_transform_name"
+# Double any \ or $. echo might interpret backslashes.
+# By default was `s,x,x', remove it if useless.
+cat <<\_ACEOF >conftest.sed
+s/[\\$]/&&/g;s/;s,x,x,$//
+_ACEOF
+program_transform_name=`echo $program_transform_name | sed -f conftest.sed`
+rm conftest.sed
+
+ac_ext=c
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
+ac_compiler_gnu=$ac_cv_c_compiler_gnu
+if test -n "$ac_tool_prefix"; then
+ # Extract the first word of "${ac_tool_prefix}gcc", so it can be a program name with args.
+set dummy ${ac_tool_prefix}gcc; ac_word=$2
+echo "$as_me:$LINENO: checking for $ac_word" >&5
+echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
+if test "${ac_cv_prog_CC+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ if test -n "$CC"; then
+ ac_cv_prog_CC="$CC" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ for ac_exec_ext in '' $ac_executable_extensions; do
+ if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+ ac_cv_prog_CC="${ac_tool_prefix}gcc"
+ echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
+ break 2
+ fi
+done
+done
+
+fi
+fi
+CC=$ac_cv_prog_CC
+if test -n "$CC"; then
+ echo "$as_me:$LINENO: result: $CC" >&5
+echo "${ECHO_T}$CC" >&6
+else
+ echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
+fi
+
+fi
+if test -z "$ac_cv_prog_CC"; then
+ ac_ct_CC=$CC
+ # Extract the first word of "gcc", so it can be a program name with args.
+set dummy gcc; ac_word=$2
+echo "$as_me:$LINENO: checking for $ac_word" >&5
+echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
+if test "${ac_cv_prog_ac_ct_CC+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ if test -n "$ac_ct_CC"; then
+ ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ for ac_exec_ext in '' $ac_executable_extensions; do
+ if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+ ac_cv_prog_ac_ct_CC="gcc"
+ echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
+ break 2
+ fi
+done
+done
+
+fi
+fi
+ac_ct_CC=$ac_cv_prog_ac_ct_CC
+if test -n "$ac_ct_CC"; then
+ echo "$as_me:$LINENO: result: $ac_ct_CC" >&5
+echo "${ECHO_T}$ac_ct_CC" >&6
+else
+ echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
+fi
+
+ CC=$ac_ct_CC
+else
+ CC="$ac_cv_prog_CC"
+fi
+
+if test -z "$CC"; then
+ if test -n "$ac_tool_prefix"; then
+ # Extract the first word of "${ac_tool_prefix}cc", so it can be a program name with args.
+set dummy ${ac_tool_prefix}cc; ac_word=$2
+echo "$as_me:$LINENO: checking for $ac_word" >&5
+echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
+if test "${ac_cv_prog_CC+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ if test -n "$CC"; then
+ ac_cv_prog_CC="$CC" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ for ac_exec_ext in '' $ac_executable_extensions; do
+ if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+ ac_cv_prog_CC="${ac_tool_prefix}cc"
+ echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
+ break 2
+ fi
+done
+done
+
+fi
+fi
+CC=$ac_cv_prog_CC
+if test -n "$CC"; then
+ echo "$as_me:$LINENO: result: $CC" >&5
+echo "${ECHO_T}$CC" >&6
+else
+ echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
+fi
+
+fi
+if test -z "$ac_cv_prog_CC"; then
+ ac_ct_CC=$CC
+ # Extract the first word of "cc", so it can be a program name with args.
+set dummy cc; ac_word=$2
+echo "$as_me:$LINENO: checking for $ac_word" >&5
+echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
+if test "${ac_cv_prog_ac_ct_CC+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ if test -n "$ac_ct_CC"; then
+ ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ for ac_exec_ext in '' $ac_executable_extensions; do
+ if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+ ac_cv_prog_ac_ct_CC="cc"
+ echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
+ break 2
+ fi
+done
+done
+
+fi
+fi
+ac_ct_CC=$ac_cv_prog_ac_ct_CC
+if test -n "$ac_ct_CC"; then
+ echo "$as_me:$LINENO: result: $ac_ct_CC" >&5
+echo "${ECHO_T}$ac_ct_CC" >&6
+else
+ echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
+fi
+
+ CC=$ac_ct_CC
+else
+ CC="$ac_cv_prog_CC"
+fi
+
+fi
+if test -z "$CC"; then
+ # Extract the first word of "cc", so it can be a program name with args.
+set dummy cc; ac_word=$2
+echo "$as_me:$LINENO: checking for $ac_word" >&5
+echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
+if test "${ac_cv_prog_CC+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ if test -n "$CC"; then
+ ac_cv_prog_CC="$CC" # Let the user override the test.
+else
+ ac_prog_rejected=no
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ for ac_exec_ext in '' $ac_executable_extensions; do
+ if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+ if test "$as_dir/$ac_word$ac_exec_ext" = "/usr/ucb/cc"; then
+ ac_prog_rejected=yes
+ continue
+ fi
+ ac_cv_prog_CC="cc"
+ echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
+ break 2
+ fi
+done
+done
+
+if test $ac_prog_rejected = yes; then
+ # We found a bogon in the path, so make sure we never use it.
+ set dummy $ac_cv_prog_CC
+ shift
+ if test $# != 0; then
+ # We chose a different compiler from the bogus one.
+ # However, it has the same basename, so the bogon will be chosen
+ # first if we set CC to just the basename; use the full file name.
+ shift
+ ac_cv_prog_CC="$as_dir/$ac_word${1+' '}$@"
+ fi
+fi
+fi
+fi
+CC=$ac_cv_prog_CC
+if test -n "$CC"; then
+ echo "$as_me:$LINENO: result: $CC" >&5
+echo "${ECHO_T}$CC" >&6
+else
+ echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
+fi
+
+fi
+if test -z "$CC"; then
+ if test -n "$ac_tool_prefix"; then
+ for ac_prog in cl
+ do
+ # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args.
+set dummy $ac_tool_prefix$ac_prog; ac_word=$2
+echo "$as_me:$LINENO: checking for $ac_word" >&5
+echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
+if test "${ac_cv_prog_CC+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ if test -n "$CC"; then
+ ac_cv_prog_CC="$CC" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ for ac_exec_ext in '' $ac_executable_extensions; do
+ if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+ ac_cv_prog_CC="$ac_tool_prefix$ac_prog"
+ echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
+ break 2
+ fi
+done
+done
+
+fi
+fi
+CC=$ac_cv_prog_CC
+if test -n "$CC"; then
+ echo "$as_me:$LINENO: result: $CC" >&5
+echo "${ECHO_T}$CC" >&6
+else
+ echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
+fi
+
+ test -n "$CC" && break
+ done
+fi
+if test -z "$CC"; then
+ ac_ct_CC=$CC
+ for ac_prog in cl
+do
+ # Extract the first word of "$ac_prog", so it can be a program name with args.
+set dummy $ac_prog; ac_word=$2
+echo "$as_me:$LINENO: checking for $ac_word" >&5
+echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
+if test "${ac_cv_prog_ac_ct_CC+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ if test -n "$ac_ct_CC"; then
+ ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ for ac_exec_ext in '' $ac_executable_extensions; do
+ if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+ ac_cv_prog_ac_ct_CC="$ac_prog"
+ echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
+ break 2
+ fi
+done
+done
+
+fi
+fi
+ac_ct_CC=$ac_cv_prog_ac_ct_CC
+if test -n "$ac_ct_CC"; then
+ echo "$as_me:$LINENO: result: $ac_ct_CC" >&5
+echo "${ECHO_T}$ac_ct_CC" >&6
+else
+ echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
+fi
+
+ test -n "$ac_ct_CC" && break
+done
+
+ CC=$ac_ct_CC
+fi
+
+fi
+
+
+test -z "$CC" && { { echo "$as_me:$LINENO: error: no acceptable C compiler found in \$PATH
+See \`config.log' for more details." >&5
+echo "$as_me: error: no acceptable C compiler found in \$PATH
+See \`config.log' for more details." >&2;}
+ { (exit 1); exit 1; }; }
+
+# Provide some information about the compiler.
+echo "$as_me:$LINENO:" \
+ "checking for C compiler version" >&5
+ac_compiler=`set X $ac_compile; echo $2`
+{ (eval echo "$as_me:$LINENO: \"$ac_compiler --version </dev/null >&5\"") >&5
+ (eval $ac_compiler --version </dev/null >&5) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }
+{ (eval echo "$as_me:$LINENO: \"$ac_compiler -v </dev/null >&5\"") >&5
+ (eval $ac_compiler -v </dev/null >&5) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }
+{ (eval echo "$as_me:$LINENO: \"$ac_compiler -V </dev/null >&5\"") >&5
+ (eval $ac_compiler -V </dev/null >&5) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }
+
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+
+int
+main ()
+{
+
+ ;
+ return 0;
+}
+_ACEOF
+ac_clean_files_save=$ac_clean_files
+ac_clean_files="$ac_clean_files a.out a.exe b.out"
+# Try to create an executable without -o first, disregard a.out.
+# It will help us diagnose broken compilers, and finding out an intuition
+# of exeext.
+echo "$as_me:$LINENO: checking for C compiler default output file name" >&5
+echo $ECHO_N "checking for C compiler default output file name... $ECHO_C" >&6
+ac_link_default=`echo "$ac_link" | sed 's/ -o *conftest[^ ]*//'`
+if { (eval echo "$as_me:$LINENO: \"$ac_link_default\"") >&5
+ (eval $ac_link_default) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; then
+ # Find the output, starting from the most likely. This scheme is
+# not robust to junk in `.', hence go to wildcards (a.*) only as a last
+# resort.
+
+# Be careful to initialize this variable, since it used to be cached.
+# Otherwise an old cache value of `no' led to `EXEEXT = no' in a Makefile.
+ac_cv_exeext=
+# b.out is created by i960 compilers.
+for ac_file in a_out.exe a.exe conftest.exe a.out conftest a.* conftest.* b.out
+do
+ test -f "$ac_file" || continue
+ case $ac_file in
+ *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.o | *.obj )
+ ;;
+ conftest.$ac_ext )
+ # This is the source file.
+ ;;
+ [ab].out )
+ # We found the default executable, but exeext='' is most
+ # certainly right.
+ break;;
+ *.* )
+ ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'`
+ # FIXME: I believe we export ac_cv_exeext for Libtool,
+ # but it would be cool to find out if it's true. Does anybody
+ # maintain Libtool? --akim.
+ export ac_cv_exeext
+ break;;
+ * )
+ break;;
+ esac
+done
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+{ { echo "$as_me:$LINENO: error: C compiler cannot create executables
+See \`config.log' for more details." >&5
+echo "$as_me: error: C compiler cannot create executables
+See \`config.log' for more details." >&2;}
+ { (exit 77); exit 77; }; }
+fi
+
+ac_exeext=$ac_cv_exeext
+echo "$as_me:$LINENO: result: $ac_file" >&5
+echo "${ECHO_T}$ac_file" >&6
+
+# Check the compiler produces executables we can run. If not, either
+# the compiler is broken, or we cross compile.
+echo "$as_me:$LINENO: checking whether the C compiler works" >&5
+echo $ECHO_N "checking whether the C compiler works... $ECHO_C" >&6
+# FIXME: These cross compiler hacks should be removed for Autoconf 3.0
+# If not cross compiling, check that we can run a simple program.
+if test "$cross_compiling" != yes; then
+ if { ac_try='./$ac_file'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ cross_compiling=no
+ else
+ if test "$cross_compiling" = maybe; then
+ cross_compiling=yes
+ else
+ { { echo "$as_me:$LINENO: error: cannot run C compiled programs.
+If you meant to cross compile, use \`--host'.
+See \`config.log' for more details." >&5
+echo "$as_me: error: cannot run C compiled programs.
+If you meant to cross compile, use \`--host'.
+See \`config.log' for more details." >&2;}
+ { (exit 1); exit 1; }; }
+ fi
+ fi
+fi
+echo "$as_me:$LINENO: result: yes" >&5
+echo "${ECHO_T}yes" >&6
+
+rm -f a.out a.exe conftest$ac_cv_exeext b.out
+ac_clean_files=$ac_clean_files_save
+# Check the compiler produces executables we can run. If not, either
+# the compiler is broken, or we cross compile.
+echo "$as_me:$LINENO: checking whether we are cross compiling" >&5
+echo $ECHO_N "checking whether we are cross compiling... $ECHO_C" >&6
+echo "$as_me:$LINENO: result: $cross_compiling" >&5
+echo "${ECHO_T}$cross_compiling" >&6
+
+echo "$as_me:$LINENO: checking for suffix of executables" >&5
+echo $ECHO_N "checking for suffix of executables... $ECHO_C" >&6
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+ (eval $ac_link) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; then
+ # If both `conftest.exe' and `conftest' are `present' (well, observable)
+# catch `conftest.exe'. For instance with Cygwin, `ls conftest' will
+# work properly (i.e., refer to `conftest.exe'), while it won't with
+# `rm'.
+for ac_file in conftest.exe conftest conftest.*; do
+ test -f "$ac_file" || continue
+ case $ac_file in
+ *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.o | *.obj ) ;;
+ *.* ) ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'`
+ export ac_cv_exeext
+ break;;
+ * ) break;;
+ esac
+done
+else
+ { { echo "$as_me:$LINENO: error: cannot compute suffix of executables: cannot compile and link
+See \`config.log' for more details." >&5
+echo "$as_me: error: cannot compute suffix of executables: cannot compile and link
+See \`config.log' for more details." >&2;}
+ { (exit 1); exit 1; }; }
+fi
+
+rm -f conftest$ac_cv_exeext
+echo "$as_me:$LINENO: result: $ac_cv_exeext" >&5
+echo "${ECHO_T}$ac_cv_exeext" >&6
+
+rm -f conftest.$ac_ext
+EXEEXT=$ac_cv_exeext
+ac_exeext=$EXEEXT
+echo "$as_me:$LINENO: checking for suffix of object files" >&5
+echo $ECHO_N "checking for suffix of object files... $ECHO_C" >&6
+if test "${ac_cv_objext+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+
+int
+main ()
+{
+
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.o conftest.obj
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+ (eval $ac_compile) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; then
+ for ac_file in `(ls conftest.o conftest.obj; ls conftest.*) 2>/dev/null`; do
+ case $ac_file in
+ *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg ) ;;
+ *) ac_cv_objext=`expr "$ac_file" : '.*\.\(.*\)'`
+ break;;
+ esac
+done
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+{ { echo "$as_me:$LINENO: error: cannot compute suffix of object files: cannot compile
+See \`config.log' for more details." >&5
+echo "$as_me: error: cannot compute suffix of object files: cannot compile
+See \`config.log' for more details." >&2;}
+ { (exit 1); exit 1; }; }
+fi
+
+rm -f conftest.$ac_cv_objext conftest.$ac_ext
+fi
+echo "$as_me:$LINENO: result: $ac_cv_objext" >&5
+echo "${ECHO_T}$ac_cv_objext" >&6
+OBJEXT=$ac_cv_objext
+ac_objext=$OBJEXT
+echo "$as_me:$LINENO: checking whether we are using the GNU C compiler" >&5
+echo $ECHO_N "checking whether we are using the GNU C compiler... $ECHO_C" >&6
+if test "${ac_cv_c_compiler_gnu+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+
+int
+main ()
+{
+#ifndef __GNUC__
+ choke me
+#endif
+
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+ (eval $ac_compile) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_compiler_gnu=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_compiler_gnu=no
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+ac_cv_c_compiler_gnu=$ac_compiler_gnu
+
+fi
+echo "$as_me:$LINENO: result: $ac_cv_c_compiler_gnu" >&5
+echo "${ECHO_T}$ac_cv_c_compiler_gnu" >&6
+GCC=`test $ac_compiler_gnu = yes && echo yes`
+ac_test_CFLAGS=${CFLAGS+set}
+ac_save_CFLAGS=$CFLAGS
+CFLAGS="-g"
+echo "$as_me:$LINENO: checking whether $CC accepts -g" >&5
+echo $ECHO_N "checking whether $CC accepts -g... $ECHO_C" >&6
+if test "${ac_cv_prog_cc_g+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+
+int
+main ()
+{
+
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+ (eval $ac_compile) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_cv_prog_cc_g=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_cv_prog_cc_g=no
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+fi
+echo "$as_me:$LINENO: result: $ac_cv_prog_cc_g" >&5
+echo "${ECHO_T}$ac_cv_prog_cc_g" >&6
+if test "$ac_test_CFLAGS" = set; then
+ CFLAGS=$ac_save_CFLAGS
+elif test $ac_cv_prog_cc_g = yes; then
+ if test "$GCC" = yes; then
+ CFLAGS="-g -O2"
+ else
+ CFLAGS="-g"
+ fi
+else
+ if test "$GCC" = yes; then
+ CFLAGS="-O2"
+ else
+ CFLAGS=
+ fi
+fi
+echo "$as_me:$LINENO: checking for $CC option to accept ANSI C" >&5
+echo $ECHO_N "checking for $CC option to accept ANSI C... $ECHO_C" >&6
+if test "${ac_cv_prog_cc_stdc+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ ac_cv_prog_cc_stdc=no
+ac_save_CC=$CC
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#include <stdarg.h>
+#include <stdio.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+/* Most of the following tests are stolen from RCS 5.7's src/conf.sh. */
+struct buf { int x; };
+FILE * (*rcsopen) (struct buf *, struct stat *, int);
+static char *e (p, i)
+ char **p;
+ int i;
+{
+ return p[i];
+}
+static char *f (char * (*g) (char **, int), char **p, ...)
+{
+ char *s;
+ va_list v;
+ va_start (v,p);
+ s = g (p, va_arg (v,int));
+ va_end (v);
+ return s;
+}
+
+/* OSF 4.0 Compaq cc is some sort of almost-ANSI by default. It has
+ function prototypes and stuff, but not '\xHH' hex character constants.
+ These don't provoke an error unfortunately, instead are silently treated
+ as 'x'. The following induces an error, until -std1 is added to get
+ proper ANSI mode. Curiously '\x00'!='x' always comes out true, for an
+ array size at least. It's necessary to write '\x00'==0 to get something
+ that's true only with -std1. */
+int osf4_cc_array ['\x00' == 0 ? 1 : -1];
+
+int test (int i, double x);
+struct s1 {int (*f) (int a);};
+struct s2 {int (*f) (double a);};
+int pairnames (int, char **, FILE *(*)(struct buf *, struct stat *, int), int, int);
+int argc;
+char **argv;
+int
+main ()
+{
+return f (e, argv, 0) != argv[0] || f (e, argv, 1) != argv[1];
+ ;
+ return 0;
+}
+_ACEOF
+# Don't try gcc -ansi; that turns off useful extensions and
+# breaks some systems' header files.
+# AIX -qlanglvl=ansi
+# Ultrix and OSF/1 -std1
+# HP-UX 10.20 and later -Ae
+# HP-UX older versions -Aa -D_HPUX_SOURCE
+# SVR4 -Xc -D__EXTENSIONS__
+for ac_arg in "" -qlanglvl=ansi -std1 -Ae "-Aa -D_HPUX_SOURCE" "-Xc -D__EXTENSIONS__"
+do
+ CC="$ac_save_CC $ac_arg"
+ rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+ (eval $ac_compile) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_cv_prog_cc_stdc=$ac_arg
+break
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+fi
+rm -f conftest.err conftest.$ac_objext
+done
+rm -f conftest.$ac_ext conftest.$ac_objext
+CC=$ac_save_CC
+
+fi
+
+case "x$ac_cv_prog_cc_stdc" in
+ x|xno)
+ echo "$as_me:$LINENO: result: none needed" >&5
+echo "${ECHO_T}none needed" >&6 ;;
+ *)
+ echo "$as_me:$LINENO: result: $ac_cv_prog_cc_stdc" >&5
+echo "${ECHO_T}$ac_cv_prog_cc_stdc" >&6
+ CC="$CC $ac_cv_prog_cc_stdc" ;;
+esac
+
+# Some people use a C++ compiler to compile C. Since we use `exit',
+# in C++ we need to declare it. In case someone uses the same compiler
+# for both compiling C and C++ we need to have the C++ compiler decide
+# the declaration of exit, since it's the most demanding environment.
+cat >conftest.$ac_ext <<_ACEOF
+#ifndef __cplusplus
+ choke me
+#endif
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+ (eval $ac_compile) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ for ac_declaration in \
+ '' \
+ 'extern "C" void std::exit (int) throw (); using std::exit;' \
+ 'extern "C" void std::exit (int); using std::exit;' \
+ 'extern "C" void exit (int) throw ();' \
+ 'extern "C" void exit (int);' \
+ 'void exit (int);'
+do
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+$ac_declaration
+#include <stdlib.h>
+int
+main ()
+{
+exit (42);
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+ (eval $ac_compile) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ :
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+continue
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+$ac_declaration
+int
+main ()
+{
+exit (42);
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+ (eval $ac_compile) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ break
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+done
+rm -f conftest*
+if test -n "$ac_declaration"; then
+ echo '#ifdef __cplusplus' >>confdefs.h
+ echo $ac_declaration >>confdefs.h
+ echo '#endif' >>confdefs.h
+fi
+
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+ac_ext=c
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
+ac_compiler_gnu=$ac_cv_c_compiler_gnu
+
+# Find a good install program. We prefer a C program (faster),
+# so one script is as good as another. But avoid the broken or
+# incompatible versions:
+# SysV /etc/install, /usr/sbin/install
+# SunOS /usr/etc/install
+# IRIX /sbin/install
+# AIX /bin/install
+# AmigaOS /C/install, which installs bootblocks on floppy discs
+# AIX 4 /usr/bin/installbsd, which doesn't work without a -g flag
+# AFS /usr/afsws/bin/install, which mishandles nonexistent args
+# SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff"
+# OS/2's system install, which has a completely different semantic
+# ./install, which can be erroneously created by make from ./install.sh.
+echo "$as_me:$LINENO: checking for a BSD-compatible install" >&5
+echo $ECHO_N "checking for a BSD-compatible install... $ECHO_C" >&6
+if test -z "$INSTALL"; then
+if test "${ac_cv_path_install+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ # Account for people who put trailing slashes in PATH elements.
+case $as_dir/ in
+ ./ | .// | /cC/* | \
+ /etc/* | /usr/sbin/* | /usr/etc/* | /sbin/* | /usr/afsws/bin/* | \
+ ?:\\/os2\\/install\\/* | ?:\\/OS2\\/INSTALL\\/* | \
+ /usr/ucb/* ) ;;
+ *)
+ # OSF1 and SCO ODT 3.0 have their own names for install.
+ # Don't use installbsd from OSF since it installs stuff as root
+ # by default.
+ for ac_prog in ginstall scoinst install; do
+ for ac_exec_ext in '' $ac_executable_extensions; do
+ if $as_executable_p "$as_dir/$ac_prog$ac_exec_ext"; then
+ if test $ac_prog = install &&
+ grep dspmsg "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then
+ # AIX install. It has an incompatible calling convention.
+ :
+ elif test $ac_prog = install &&
+ grep pwplus "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then
+ # program-specific install script used by HP pwplus--don't use.
+ :
+ else
+ ac_cv_path_install="$as_dir/$ac_prog$ac_exec_ext -c"
+ break 3
+ fi
+ fi
+ done
+ done
+ ;;
+esac
+done
+
+
+fi
+ if test "${ac_cv_path_install+set}" = set; then
+ INSTALL=$ac_cv_path_install
+ else
+ # As a last resort, use the slow shell script. We don't cache a
+ # path for INSTALL within a source directory, because that will
+ # break other packages using the cache if that directory is
+ # removed, or if the path is relative.
+ INSTALL=$ac_install_sh
+ fi
+fi
+echo "$as_me:$LINENO: result: $INSTALL" >&5
+echo "${ECHO_T}$INSTALL" >&6
+
+# Use test -z because SunOS4 sh mishandles braces in ${var-val}.
+# It thinks the first close brace ends the variable substitution.
+test -z "$INSTALL_PROGRAM" && INSTALL_PROGRAM='${INSTALL}'
+
+test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL}'
+
+test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644'
+
+
+# Put a plausible default for CC_FOR_BUILD in Makefile.
+if test "x$cross_compiling" = "xno"; then
+ CC_FOR_BUILD='$(CC)'
+else
+ CC_FOR_BUILD=gcc
+fi
+
+
+
+
+AR=${AR-ar}
+
+if test -n "$ac_tool_prefix"; then
+ # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args.
+set dummy ${ac_tool_prefix}ranlib; ac_word=$2
+echo "$as_me:$LINENO: checking for $ac_word" >&5
+echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
+if test "${ac_cv_prog_RANLIB+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ if test -n "$RANLIB"; then
+ ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ for ac_exec_ext in '' $ac_executable_extensions; do
+ if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+ ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib"
+ echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
+ break 2
+ fi
+done
+done
+
+fi
+fi
+RANLIB=$ac_cv_prog_RANLIB
+if test -n "$RANLIB"; then
+ echo "$as_me:$LINENO: result: $RANLIB" >&5
+echo "${ECHO_T}$RANLIB" >&6
+else
+ echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
+fi
+
+fi
+if test -z "$ac_cv_prog_RANLIB"; then
+ ac_ct_RANLIB=$RANLIB
+ # Extract the first word of "ranlib", so it can be a program name with args.
+set dummy ranlib; ac_word=$2
+echo "$as_me:$LINENO: checking for $ac_word" >&5
+echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
+if test "${ac_cv_prog_ac_ct_RANLIB+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ if test -n "$ac_ct_RANLIB"; then
+ ac_cv_prog_ac_ct_RANLIB="$ac_ct_RANLIB" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ for ac_exec_ext in '' $ac_executable_extensions; do
+ if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+ ac_cv_prog_ac_ct_RANLIB="ranlib"
+ echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
+ break 2
+ fi
+done
+done
+
+ test -z "$ac_cv_prog_ac_ct_RANLIB" && ac_cv_prog_ac_ct_RANLIB=":"
+fi
+fi
+ac_ct_RANLIB=$ac_cv_prog_ac_ct_RANLIB
+if test -n "$ac_ct_RANLIB"; then
+ echo "$as_me:$LINENO: result: $ac_ct_RANLIB" >&5
+echo "${ECHO_T}$ac_ct_RANLIB" >&6
+else
+ echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
+fi
+
+ RANLIB=$ac_ct_RANLIB
+else
+ RANLIB="$ac_cv_prog_RANLIB"
+fi
+
+
+ALL_LINGUAS=
+# If we haven't got the data from the intl directory,
+# assume NLS is disabled.
+USE_NLS=no
+LIBINTL=
+LIBINTL_DEP=
+INCINTL=
+XGETTEXT=
+GMSGFMT=
+POSUB=
+
+if test -f ../../intl/config.intl; then
+ . ../../intl/config.intl
+fi
+echo "$as_me:$LINENO: checking whether NLS is requested" >&5
+echo $ECHO_N "checking whether NLS is requested... $ECHO_C" >&6
+if test x"$USE_NLS" != xyes; then
+ echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
+else
+ echo "$as_me:$LINENO: result: yes" >&5
+echo "${ECHO_T}yes" >&6
+
+cat >>confdefs.h <<\_ACEOF
+#define ENABLE_NLS 1
+_ACEOF
+
+
+ echo "$as_me:$LINENO: checking for catalogs to be installed" >&5
+echo $ECHO_N "checking for catalogs to be installed... $ECHO_C" >&6
+ # Look for .po and .gmo files in the source directory.
+ CATALOGS=
+ XLINGUAS=
+ for cat in $srcdir/po/*.gmo $srcdir/po/*.po; do
+ # If there aren't any .gmo files the shell will give us the
+ # literal string "../path/to/srcdir/po/*.gmo" which has to be
+ # weeded out.
+ case "$cat" in *\**)
+ continue;;
+ esac
+ # The quadruple backslash is collapsed to a double backslash
+ # by the backticks, then collapsed again by the double quotes,
+ # leaving us with one backslash in the sed expression (right
+ # before the dot that mustn't act as a wildcard).
+ cat=`echo $cat | sed -e "s!$srcdir/po/!!" -e "s!\\\\.po!.gmo!"`
+ lang=`echo $cat | sed -e "s!\\\\.gmo!!"`
+ # The user is allowed to set LINGUAS to a list of languages to
+ # install catalogs for. If it's empty that means "all of them."
+ if test "x$LINGUAS" = x; then
+ CATALOGS="$CATALOGS $cat"
+ XLINGUAS="$XLINGUAS $lang"
+ else
+ case "$LINGUAS" in *$lang*)
+ CATALOGS="$CATALOGS $cat"
+ XLINGUAS="$XLINGUAS $lang"
+ ;;
+ esac
+ fi
+ done
+ LINGUAS="$XLINGUAS"
+ echo "$as_me:$LINENO: result: $LINGUAS" >&5
+echo "${ECHO_T}$LINGUAS" >&6
+
+
+ DATADIRNAME=share
+
+ INSTOBJEXT=.mo
+
+ GENCAT=gencat
+
+ CATOBJEXT=.gmo
+
+fi
+
+# Check for common headers.
+# FIXME: Seems to me this can cause problems for i386-windows hosts.
+# At one point there were hardcoded AC_DEFINE's if ${host} = i386-*-windows*.
+
+ac_ext=c
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
+ac_compiler_gnu=$ac_cv_c_compiler_gnu
+echo "$as_me:$LINENO: checking how to run the C preprocessor" >&5
+echo $ECHO_N "checking how to run the C preprocessor... $ECHO_C" >&6
+# On Suns, sometimes $CPP names a directory.
+if test -n "$CPP" && test -d "$CPP"; then
+ CPP=
+fi
+if test -z "$CPP"; then
+ if test "${ac_cv_prog_CPP+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ # Double quotes because CPP needs to be expanded
+ for CPP in "$CC -E" "$CC -E -traditional-cpp" "/lib/cpp"
+ do
+ ac_preproc_ok=false
+for ac_c_preproc_warn_flag in '' yes
+do
+ # Use a header file that comes with gcc, so configuring glibc
+ # with a fresh cross-compiler works.
+ # Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
+ # <limits.h> exists even on freestanding compilers.
+ # On the NeXT, cc -E runs the code through the compiler's parser,
+ # not just through cpp. "Syntax error" is here to catch this case.
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#ifdef __STDC__
+# include <limits.h>
+#else
+# include <assert.h>
+#endif
+ Syntax error
+_ACEOF
+if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
+ (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } >/dev/null; then
+ if test -s conftest.err; then
+ ac_cpp_err=$ac_c_preproc_warn_flag
+ ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
+ else
+ ac_cpp_err=
+ fi
+else
+ ac_cpp_err=yes
+fi
+if test -z "$ac_cpp_err"; then
+ :
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ # Broken: fails on valid input.
+continue
+fi
+rm -f conftest.err conftest.$ac_ext
+
+ # OK, works on sane cases. Now check whether non-existent headers
+ # can be detected and how.
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#include <ac_nonexistent.h>
+_ACEOF
+if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
+ (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } >/dev/null; then
+ if test -s conftest.err; then
+ ac_cpp_err=$ac_c_preproc_warn_flag
+ ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
+ else
+ ac_cpp_err=
+ fi
+else
+ ac_cpp_err=yes
+fi
+if test -z "$ac_cpp_err"; then
+ # Broken: success on invalid input.
+continue
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ # Passes both tests.
+ac_preproc_ok=:
+break
+fi
+rm -f conftest.err conftest.$ac_ext
+
+done
+# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped.
+rm -f conftest.err conftest.$ac_ext
+if $ac_preproc_ok; then
+ break
+fi
+
+ done
+ ac_cv_prog_CPP=$CPP
+
+fi
+ CPP=$ac_cv_prog_CPP
+else
+ ac_cv_prog_CPP=$CPP
+fi
+echo "$as_me:$LINENO: result: $CPP" >&5
+echo "${ECHO_T}$CPP" >&6
+ac_preproc_ok=false
+for ac_c_preproc_warn_flag in '' yes
+do
+ # Use a header file that comes with gcc, so configuring glibc
+ # with a fresh cross-compiler works.
+ # Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
+ # <limits.h> exists even on freestanding compilers.
+ # On the NeXT, cc -E runs the code through the compiler's parser,
+ # not just through cpp. "Syntax error" is here to catch this case.
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#ifdef __STDC__
+# include <limits.h>
+#else
+# include <assert.h>
+#endif
+ Syntax error
+_ACEOF
+if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
+ (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } >/dev/null; then
+ if test -s conftest.err; then
+ ac_cpp_err=$ac_c_preproc_warn_flag
+ ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
+ else
+ ac_cpp_err=
+ fi
+else
+ ac_cpp_err=yes
+fi
+if test -z "$ac_cpp_err"; then
+ :
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ # Broken: fails on valid input.
+continue
+fi
+rm -f conftest.err conftest.$ac_ext
+
+ # OK, works on sane cases. Now check whether non-existent headers
+ # can be detected and how.
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#include <ac_nonexistent.h>
+_ACEOF
+if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
+ (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } >/dev/null; then
+ if test -s conftest.err; then
+ ac_cpp_err=$ac_c_preproc_warn_flag
+ ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
+ else
+ ac_cpp_err=
+ fi
+else
+ ac_cpp_err=yes
+fi
+if test -z "$ac_cpp_err"; then
+ # Broken: success on invalid input.
+continue
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ # Passes both tests.
+ac_preproc_ok=:
+break
+fi
+rm -f conftest.err conftest.$ac_ext
+
+done
+# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped.
+rm -f conftest.err conftest.$ac_ext
+if $ac_preproc_ok; then
+ :
+else
+ { { echo "$as_me:$LINENO: error: C preprocessor \"$CPP\" fails sanity check
+See \`config.log' for more details." >&5
+echo "$as_me: error: C preprocessor \"$CPP\" fails sanity check
+See \`config.log' for more details." >&2;}
+ { (exit 1); exit 1; }; }
+fi
+
+ac_ext=c
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
+ac_compiler_gnu=$ac_cv_c_compiler_gnu
+
+
+echo "$as_me:$LINENO: checking for egrep" >&5
+echo $ECHO_N "checking for egrep... $ECHO_C" >&6
+if test "${ac_cv_prog_egrep+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ if echo a | (grep -E '(a|b)') >/dev/null 2>&1
+ then ac_cv_prog_egrep='grep -E'
+ else ac_cv_prog_egrep='egrep'
+ fi
+fi
+echo "$as_me:$LINENO: result: $ac_cv_prog_egrep" >&5
+echo "${ECHO_T}$ac_cv_prog_egrep" >&6
+ EGREP=$ac_cv_prog_egrep
+
+
+echo "$as_me:$LINENO: checking for ANSI C header files" >&5
+echo $ECHO_N "checking for ANSI C header files... $ECHO_C" >&6
+if test "${ac_cv_header_stdc+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#include <stdlib.h>
+#include <stdarg.h>
+#include <string.h>
+#include <float.h>
+
+int
+main ()
+{
+
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+ (eval $ac_compile) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_cv_header_stdc=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_cv_header_stdc=no
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+
+if test $ac_cv_header_stdc = yes; then
+ # SunOS 4.x string.h does not declare mem*, contrary to ANSI.
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#include <string.h>
+
+_ACEOF
+if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
+ $EGREP "memchr" >/dev/null 2>&1; then
+ :
+else
+ ac_cv_header_stdc=no
+fi
+rm -f conftest*
+
+fi
+
+if test $ac_cv_header_stdc = yes; then
+ # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI.
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#include <stdlib.h>
+
+_ACEOF
+if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
+ $EGREP "free" >/dev/null 2>&1; then
+ :
+else
+ ac_cv_header_stdc=no
+fi
+rm -f conftest*
+
+fi
+
+if test $ac_cv_header_stdc = yes; then
+ # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi.
+ if test "$cross_compiling" = yes; then
+ :
+else
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#include <ctype.h>
+#if ((' ' & 0x0FF) == 0x020)
+# define ISLOWER(c) ('a' <= (c) && (c) <= 'z')
+# define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c))
+#else
+# define ISLOWER(c) \
+ (('a' <= (c) && (c) <= 'i') \
+ || ('j' <= (c) && (c) <= 'r') \
+ || ('s' <= (c) && (c) <= 'z'))
+# define TOUPPER(c) (ISLOWER(c) ? ((c) | 0x40) : (c))
+#endif
+
+#define XOR(e, f) (((e) && !(f)) || (!(e) && (f)))
+int
+main ()
+{
+ int i;
+ for (i = 0; i < 256; i++)
+ if (XOR (islower (i), ISLOWER (i))
+ || toupper (i) != TOUPPER (i))
+ exit(2);
+ exit (0);
+}
+_ACEOF
+rm -f conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+ (eval $ac_link) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } && { ac_try='./conftest$ac_exeext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ :
+else
+ echo "$as_me: program exited with status $ac_status" >&5
+echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+( exit $ac_status )
+ac_cv_header_stdc=no
+fi
+rm -f core *.core gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext
+fi
+fi
+fi
+echo "$as_me:$LINENO: result: $ac_cv_header_stdc" >&5
+echo "${ECHO_T}$ac_cv_header_stdc" >&6
+if test $ac_cv_header_stdc = yes; then
+
+cat >>confdefs.h <<\_ACEOF
+#define STDC_HEADERS 1
+_ACEOF
+
+fi
+
+# On IRIX 5.3, sys/types and inttypes.h are conflicting.
+
+
+
+
+
+
+
+
+
+for ac_header in sys/types.h sys/stat.h stdlib.h string.h memory.h strings.h \
+ inttypes.h stdint.h unistd.h
+do
+as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
+echo "$as_me:$LINENO: checking for $ac_header" >&5
+echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
+if eval "test \"\${$as_ac_Header+set}\" = set"; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+$ac_includes_default
+
+#include <$ac_header>
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+ (eval $ac_compile) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ eval "$as_ac_Header=yes"
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+eval "$as_ac_Header=no"
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+fi
+echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
+echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
+if test `eval echo '${'$as_ac_Header'}'` = yes; then
+ cat >>confdefs.h <<_ACEOF
+#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1
+_ACEOF
+
+fi
+
+done
+
+
+
+
+
+
+
+for ac_header in stdlib.h string.h strings.h unistd.h time.h
+do
+as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
+if eval "test \"\${$as_ac_Header+set}\" = set"; then
+ echo "$as_me:$LINENO: checking for $ac_header" >&5
+echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
+if eval "test \"\${$as_ac_Header+set}\" = set"; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+fi
+echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
+echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
+else
+ # Is the header compilable?
+echo "$as_me:$LINENO: checking $ac_header usability" >&5
+echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+$ac_includes_default
+#include <$ac_header>
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+ (eval $ac_compile) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_header_compiler=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_header_compiler=no
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
+echo "${ECHO_T}$ac_header_compiler" >&6
+
+# Is the header present?
+echo "$as_me:$LINENO: checking $ac_header presence" >&5
+echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#include <$ac_header>
+_ACEOF
+if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
+ (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } >/dev/null; then
+ if test -s conftest.err; then
+ ac_cpp_err=$ac_c_preproc_warn_flag
+ ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
+ else
+ ac_cpp_err=
+ fi
+else
+ ac_cpp_err=yes
+fi
+if test -z "$ac_cpp_err"; then
+ ac_header_preproc=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ ac_header_preproc=no
+fi
+rm -f conftest.err conftest.$ac_ext
+echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
+echo "${ECHO_T}$ac_header_preproc" >&6
+
+# So? What about this header?
+case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
+ yes:no: )
+ { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5
+echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5
+echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;}
+ ac_header_preproc=yes
+ ;;
+ no:yes:* )
+ { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5
+echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: check for missing prerequisite headers?" >&5
+echo "$as_me: WARNING: $ac_header: check for missing prerequisite headers?" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5
+echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&5
+echo "$as_me: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5
+echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5
+echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;}
+ (
+ cat <<\_ASBOX
+## ------------------------------------------ ##
+## Report this to the AC_PACKAGE_NAME lists. ##
+## ------------------------------------------ ##
+_ASBOX
+ ) |
+ sed "s/^/$as_me: WARNING: /" >&2
+ ;;
+esac
+echo "$as_me:$LINENO: checking for $ac_header" >&5
+echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
+if eval "test \"\${$as_ac_Header+set}\" = set"; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ eval "$as_ac_Header=\$ac_header_preproc"
+fi
+echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
+echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
+
+fi
+if test `eval echo '${'$as_ac_Header'}'` = yes; then
+ cat >>confdefs.h <<_ACEOF
+#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1
+_ACEOF
+
+fi
+
+done
+
+
+
+for ac_header in sys/time.h sys/resource.h
+do
+as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
+if eval "test \"\${$as_ac_Header+set}\" = set"; then
+ echo "$as_me:$LINENO: checking for $ac_header" >&5
+echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
+if eval "test \"\${$as_ac_Header+set}\" = set"; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+fi
+echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
+echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
+else
+ # Is the header compilable?
+echo "$as_me:$LINENO: checking $ac_header usability" >&5
+echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+$ac_includes_default
+#include <$ac_header>
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+ (eval $ac_compile) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_header_compiler=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_header_compiler=no
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
+echo "${ECHO_T}$ac_header_compiler" >&6
+
+# Is the header present?
+echo "$as_me:$LINENO: checking $ac_header presence" >&5
+echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#include <$ac_header>
+_ACEOF
+if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
+ (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } >/dev/null; then
+ if test -s conftest.err; then
+ ac_cpp_err=$ac_c_preproc_warn_flag
+ ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
+ else
+ ac_cpp_err=
+ fi
+else
+ ac_cpp_err=yes
+fi
+if test -z "$ac_cpp_err"; then
+ ac_header_preproc=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ ac_header_preproc=no
+fi
+rm -f conftest.err conftest.$ac_ext
+echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
+echo "${ECHO_T}$ac_header_preproc" >&6
+
+# So? What about this header?
+case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
+ yes:no: )
+ { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5
+echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5
+echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;}
+ ac_header_preproc=yes
+ ;;
+ no:yes:* )
+ { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5
+echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: check for missing prerequisite headers?" >&5
+echo "$as_me: WARNING: $ac_header: check for missing prerequisite headers?" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5
+echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&5
+echo "$as_me: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5
+echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5
+echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;}
+ (
+ cat <<\_ASBOX
+## ------------------------------------------ ##
+## Report this to the AC_PACKAGE_NAME lists. ##
+## ------------------------------------------ ##
+_ASBOX
+ ) |
+ sed "s/^/$as_me: WARNING: /" >&2
+ ;;
+esac
+echo "$as_me:$LINENO: checking for $ac_header" >&5
+echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
+if eval "test \"\${$as_ac_Header+set}\" = set"; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ eval "$as_ac_Header=\$ac_header_preproc"
+fi
+echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
+echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
+
+fi
+if test `eval echo '${'$as_ac_Header'}'` = yes; then
+ cat >>confdefs.h <<_ACEOF
+#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1
+_ACEOF
+
+fi
+
+done
+
+
+
+for ac_header in fcntl.h fpu_control.h
+do
+as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
+if eval "test \"\${$as_ac_Header+set}\" = set"; then
+ echo "$as_me:$LINENO: checking for $ac_header" >&5
+echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
+if eval "test \"\${$as_ac_Header+set}\" = set"; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+fi
+echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
+echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
+else
+ # Is the header compilable?
+echo "$as_me:$LINENO: checking $ac_header usability" >&5
+echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+$ac_includes_default
+#include <$ac_header>
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+ (eval $ac_compile) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_header_compiler=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_header_compiler=no
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
+echo "${ECHO_T}$ac_header_compiler" >&6
+
+# Is the header present?
+echo "$as_me:$LINENO: checking $ac_header presence" >&5
+echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#include <$ac_header>
+_ACEOF
+if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
+ (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } >/dev/null; then
+ if test -s conftest.err; then
+ ac_cpp_err=$ac_c_preproc_warn_flag
+ ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
+ else
+ ac_cpp_err=
+ fi
+else
+ ac_cpp_err=yes
+fi
+if test -z "$ac_cpp_err"; then
+ ac_header_preproc=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ ac_header_preproc=no
+fi
+rm -f conftest.err conftest.$ac_ext
+echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
+echo "${ECHO_T}$ac_header_preproc" >&6
+
+# So? What about this header?
+case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
+ yes:no: )
+ { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5
+echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5
+echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;}
+ ac_header_preproc=yes
+ ;;
+ no:yes:* )
+ { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5
+echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: check for missing prerequisite headers?" >&5
+echo "$as_me: WARNING: $ac_header: check for missing prerequisite headers?" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5
+echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&5
+echo "$as_me: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5
+echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5
+echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;}
+ (
+ cat <<\_ASBOX
+## ------------------------------------------ ##
+## Report this to the AC_PACKAGE_NAME lists. ##
+## ------------------------------------------ ##
+_ASBOX
+ ) |
+ sed "s/^/$as_me: WARNING: /" >&2
+ ;;
+esac
+echo "$as_me:$LINENO: checking for $ac_header" >&5
+echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
+if eval "test \"\${$as_ac_Header+set}\" = set"; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ eval "$as_ac_Header=\$ac_header_preproc"
+fi
+echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
+echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
+
+fi
+if test `eval echo '${'$as_ac_Header'}'` = yes; then
+ cat >>confdefs.h <<_ACEOF
+#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1
+_ACEOF
+
+fi
+
+done
+
+
+
+
+for ac_header in dlfcn.h errno.h sys/stat.h
+do
+as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
+if eval "test \"\${$as_ac_Header+set}\" = set"; then
+ echo "$as_me:$LINENO: checking for $ac_header" >&5
+echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
+if eval "test \"\${$as_ac_Header+set}\" = set"; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+fi
+echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
+echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
+else
+ # Is the header compilable?
+echo "$as_me:$LINENO: checking $ac_header usability" >&5
+echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+$ac_includes_default
+#include <$ac_header>
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+ (eval $ac_compile) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_header_compiler=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_header_compiler=no
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
+echo "${ECHO_T}$ac_header_compiler" >&6
+
+# Is the header present?
+echo "$as_me:$LINENO: checking $ac_header presence" >&5
+echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#include <$ac_header>
+_ACEOF
+if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
+ (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } >/dev/null; then
+ if test -s conftest.err; then
+ ac_cpp_err=$ac_c_preproc_warn_flag
+ ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
+ else
+ ac_cpp_err=
+ fi
+else
+ ac_cpp_err=yes
+fi
+if test -z "$ac_cpp_err"; then
+ ac_header_preproc=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ ac_header_preproc=no
+fi
+rm -f conftest.err conftest.$ac_ext
+echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
+echo "${ECHO_T}$ac_header_preproc" >&6
+
+# So? What about this header?
+case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
+ yes:no: )
+ { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5
+echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5
+echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;}
+ ac_header_preproc=yes
+ ;;
+ no:yes:* )
+ { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5
+echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: check for missing prerequisite headers?" >&5
+echo "$as_me: WARNING: $ac_header: check for missing prerequisite headers?" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5
+echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&5
+echo "$as_me: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5
+echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5
+echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;}
+ (
+ cat <<\_ASBOX
+## ------------------------------------------ ##
+## Report this to the AC_PACKAGE_NAME lists. ##
+## ------------------------------------------ ##
+_ASBOX
+ ) |
+ sed "s/^/$as_me: WARNING: /" >&2
+ ;;
+esac
+echo "$as_me:$LINENO: checking for $ac_header" >&5
+echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
+if eval "test \"\${$as_ac_Header+set}\" = set"; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ eval "$as_ac_Header=\$ac_header_preproc"
+fi
+echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
+echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
+
+fi
+if test `eval echo '${'$as_ac_Header'}'` = yes; then
+ cat >>confdefs.h <<_ACEOF
+#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1
+_ACEOF
+
+fi
+
+done
+
+
+
+
+
+for ac_func in getrusage time sigaction __setfpucw
+do
+as_ac_var=`echo "ac_cv_func_$ac_func" | $as_tr_sh`
+echo "$as_me:$LINENO: checking for $ac_func" >&5
+echo $ECHO_N "checking for $ac_func... $ECHO_C" >&6
+if eval "test \"\${$as_ac_var+set}\" = set"; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+/* Define $ac_func to an innocuous variant, in case <limits.h> declares $ac_func.
+ For example, HP-UX 11i <limits.h> declares gettimeofday. */
+#define $ac_func innocuous_$ac_func
+
+/* System header to define __stub macros and hopefully few prototypes,
+ which can conflict with char $ac_func (); below.
+ Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
+ <limits.h> exists even on freestanding compilers. */
+
+#ifdef __STDC__
+# include <limits.h>
+#else
+# include <assert.h>
+#endif
+
+#undef $ac_func
+
+/* Override any gcc2 internal prototype to avoid an error. */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+/* We use char because int might match the return type of a gcc2
+ builtin and then its argument prototype would still apply. */
+char $ac_func ();
+/* The GNU C library defines this for functions which it implements
+ to always fail with ENOSYS. Some functions are actually named
+ something starting with __ and the normal name is an alias. */
+#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
+choke me
+#else
+char (*f) () = $ac_func;
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+int
+main ()
+{
+return f != $ac_func;
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+ (eval $ac_link) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest$ac_exeext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ eval "$as_ac_var=yes"
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+eval "$as_ac_var=no"
+fi
+rm -f conftest.err conftest.$ac_objext \
+ conftest$ac_exeext conftest.$ac_ext
+fi
+echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_var'}'`" >&5
+echo "${ECHO_T}`eval echo '${'$as_ac_var'}'`" >&6
+if test `eval echo '${'$as_ac_var'}'` = yes; then
+ cat >>confdefs.h <<_ACEOF
+#define `echo "HAVE_$ac_func" | $as_tr_cpp` 1
+_ACEOF
+
+fi
+done
+
+
+# Check for socket libraries
+
+echo "$as_me:$LINENO: checking for bind in -lsocket" >&5
+echo $ECHO_N "checking for bind in -lsocket... $ECHO_C" >&6
+if test "${ac_cv_lib_socket_bind+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ ac_check_lib_save_LIBS=$LIBS
+LIBS="-lsocket $LIBS"
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+
+/* Override any gcc2 internal prototype to avoid an error. */
+#ifdef __cplusplus
+extern "C"
+#endif
+/* We use char because int might match the return type of a gcc2
+ builtin and then its argument prototype would still apply. */
+char bind ();
+int
+main ()
+{
+bind ();
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+ (eval $ac_link) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest$ac_exeext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_cv_lib_socket_bind=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_cv_lib_socket_bind=no
+fi
+rm -f conftest.err conftest.$ac_objext \
+ conftest$ac_exeext conftest.$ac_ext
+LIBS=$ac_check_lib_save_LIBS
+fi
+echo "$as_me:$LINENO: result: $ac_cv_lib_socket_bind" >&5
+echo "${ECHO_T}$ac_cv_lib_socket_bind" >&6
+if test $ac_cv_lib_socket_bind = yes; then
+ cat >>confdefs.h <<_ACEOF
+#define HAVE_LIBSOCKET 1
+_ACEOF
+
+ LIBS="-lsocket $LIBS"
+
+fi
+
+
+echo "$as_me:$LINENO: checking for gethostbyname in -lnsl" >&5
+echo $ECHO_N "checking for gethostbyname in -lnsl... $ECHO_C" >&6
+if test "${ac_cv_lib_nsl_gethostbyname+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ ac_check_lib_save_LIBS=$LIBS
+LIBS="-lnsl $LIBS"
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+
+/* Override any gcc2 internal prototype to avoid an error. */
+#ifdef __cplusplus
+extern "C"
+#endif
+/* We use char because int might match the return type of a gcc2
+ builtin and then its argument prototype would still apply. */
+char gethostbyname ();
+int
+main ()
+{
+gethostbyname ();
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+ (eval $ac_link) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest$ac_exeext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_cv_lib_nsl_gethostbyname=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_cv_lib_nsl_gethostbyname=no
+fi
+rm -f conftest.err conftest.$ac_objext \
+ conftest$ac_exeext conftest.$ac_ext
+LIBS=$ac_check_lib_save_LIBS
+fi
+echo "$as_me:$LINENO: result: $ac_cv_lib_nsl_gethostbyname" >&5
+echo "${ECHO_T}$ac_cv_lib_nsl_gethostbyname" >&6
+if test $ac_cv_lib_nsl_gethostbyname = yes; then
+ cat >>confdefs.h <<_ACEOF
+#define HAVE_LIBNSL 1
+_ACEOF
+
+ LIBS="-lnsl $LIBS"
+
+fi
+
+
+. ${srcdir}/../../bfd/configure.host
+
+
+
+USE_MAINTAINER_MODE=no
+# Check whether --enable-maintainer-mode or --disable-maintainer-mode was given.
+if test "${enable_maintainer_mode+set}" = set; then
+ enableval="$enable_maintainer_mode"
+ case "${enableval}" in
+ yes) MAINT="" USE_MAINTAINER_MODE=yes ;;
+ no) MAINT="#" ;;
+ *) { { echo "$as_me:$LINENO: error: \"--enable-maintainer-mode does not take a value\"" >&5
+echo "$as_me: error: \"--enable-maintainer-mode does not take a value\"" >&2;}
+ { (exit 1); exit 1; }; }; MAINT="#" ;;
+esac
+if test x"$silent" != x"yes" && test x"$MAINT" = x""; then
+ echo "Setting maintainer mode" 6>&1
+fi
+else
+ MAINT="#"
+fi;
+
+
+# Check whether --enable-sim-bswap or --disable-sim-bswap was given.
+if test "${enable_sim_bswap+set}" = set; then
+ enableval="$enable_sim_bswap"
+ case "${enableval}" in
+ yes) sim_bswap="-DWITH_BSWAP=1 -DUSE_BSWAP=1";;
+ no) sim_bswap="-DWITH_BSWAP=0";;
+ *) { { echo "$as_me:$LINENO: error: \"--enable-sim-bswap does not take a value\"" >&5
+echo "$as_me: error: \"--enable-sim-bswap does not take a value\"" >&2;}
+ { (exit 1); exit 1; }; }; sim_bswap="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_bswap" != x""; then
+ echo "Setting bswap flags = $sim_bswap" 6>&1
+fi
+else
+ sim_bswap=""
+fi;
+
+
+# Check whether --enable-sim-cflags or --disable-sim-cflags was given.
+if test "${enable_sim_cflags+set}" = set; then
+ enableval="$enable_sim_cflags"
+ case "${enableval}" in
+ yes) sim_cflags="-O2 -fomit-frame-pointer";;
+ trace) { { echo "$as_me:$LINENO: error: \"Please use --enable-sim-debug instead.\"" >&5
+echo "$as_me: error: \"Please use --enable-sim-debug instead.\"" >&2;}
+ { (exit 1); exit 1; }; }; sim_cflags="";;
+ no) sim_cflags="";;
+ *) sim_cflags=`echo "${enableval}" | sed -e "s/,/ /g"`;;
+esac
+if test x"$silent" != x"yes" && test x"$sim_cflags" != x""; then
+ echo "Setting sim cflags = $sim_cflags" 6>&1
+fi
+else
+ sim_cflags=""
+fi;
+
+
+# Check whether --enable-sim-debug or --disable-sim-debug was given.
+if test "${enable_sim_debug+set}" = set; then
+ enableval="$enable_sim_debug"
+ case "${enableval}" in
+ yes) sim_debug="-DDEBUG=7 -DWITH_DEBUG=7";;
+ no) sim_debug="-DDEBUG=0 -DWITH_DEBUG=0";;
+ *) sim_debug="-DDEBUG='(${enableval})' -DWITH_DEBUG='(${enableval})'";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_debug" != x""; then
+ echo "Setting sim debug = $sim_debug" 6>&1
+fi
+else
+ sim_debug=""
+fi;
+
+
+# Check whether --enable-sim-stdio or --disable-sim-stdio was given.
+if test "${enable_sim_stdio+set}" = set; then
+ enableval="$enable_sim_stdio"
+ case "${enableval}" in
+ yes) sim_stdio="-DWITH_STDIO=DO_USE_STDIO";;
+ no) sim_stdio="-DWITH_STDIO=DONT_USE_STDIO";;
+ *) { { echo "$as_me:$LINENO: error: \"Unknown value $enableval passed to --enable-sim-stdio\"" >&5
+echo "$as_me: error: \"Unknown value $enableval passed to --enable-sim-stdio\"" >&2;}
+ { (exit 1); exit 1; }; }; sim_stdio="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_stdio" != x""; then
+ echo "Setting stdio flags = $sim_stdio" 6>&1
+fi
+else
+ sim_stdio=""
+fi;
+
+
+# Check whether --enable-sim-trace or --disable-sim-trace was given.
+if test "${enable_sim_trace+set}" = set; then
+ enableval="$enable_sim_trace"
+ case "${enableval}" in
+ yes) sim_trace="-DTRACE=1 -DWITH_TRACE=-1";;
+ no) sim_trace="-DTRACE=0 -DWITH_TRACE=0";;
+ [-0-9]*)
+ sim_trace="-DTRACE='(${enableval})' -DWITH_TRACE='(${enableval})'";;
+ [a-z]*)
+ sim_trace=""
+ for x in `echo "$enableval" | sed -e "s/,/ /g"`; do
+ if test x"$sim_trace" = x; then
+ sim_trace="-DWITH_TRACE='(TRACE_$x"
+ else
+ sim_trace="${sim_trace}|TRACE_$x"
+ fi
+ done
+ sim_trace="$sim_trace)'" ;;
+esac
+if test x"$silent" != x"yes" && test x"$sim_trace" != x""; then
+ echo "Setting sim trace = $sim_trace" 6>&1
+fi
+else
+ sim_trace=""
+fi;
+
+
+# Check whether --enable-sim-profile or --disable-sim-profile was given.
+if test "${enable_sim_profile+set}" = set; then
+ enableval="$enable_sim_profile"
+ case "${enableval}" in
+ yes) sim_profile="-DPROFILE=1 -DWITH_PROFILE=-1";;
+ no) sim_profile="-DPROFILE=0 -DWITH_PROFILE=0";;
+ [-0-9]*)
+ sim_profile="-DPROFILE='(${enableval})' -DWITH_PROFILE='(${enableval})'";;
+ [a-z]*)
+ sim_profile=""
+ for x in `echo "$enableval" | sed -e "s/,/ /g"`; do
+ if test x"$sim_profile" = x; then
+ sim_profile="-DWITH_PROFILE='(PROFILE_$x"
+ else
+ sim_profile="${sim_profile}|PROFILE_$x"
+ fi
+ done
+ sim_profile="$sim_profile)'" ;;
+esac
+if test x"$silent" != x"yes" && test x"$sim_profile" != x""; then
+ echo "Setting sim profile = $sim_profile" 6>&1
+fi
+else
+ sim_profile="-DPROFILE=1 -DWITH_PROFILE=-1"
+fi;
+
+
+echo "$as_me:$LINENO: checking return type of signal handlers" >&5
+echo $ECHO_N "checking return type of signal handlers... $ECHO_C" >&6
+if test "${ac_cv_type_signal+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#include <sys/types.h>
+#include <signal.h>
+#ifdef signal
+# undef signal
+#endif
+#ifdef __cplusplus
+extern "C" void (*signal (int, void (*)(int)))(int);
+#else
+void (*signal ()) ();
+#endif
+
+int
+main ()
+{
+int i;
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+ (eval $ac_compile) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_cv_type_signal=void
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_cv_type_signal=int
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+fi
+echo "$as_me:$LINENO: result: $ac_cv_type_signal" >&5
+echo "${ECHO_T}$ac_cv_type_signal" >&6
+
+cat >>confdefs.h <<_ACEOF
+#define RETSIGTYPE $ac_cv_type_signal
+_ACEOF
+
+
+
+
+
+sim_link_files=
+sim_link_links=
+
+sim_link_links=tconfig.h
+if test -f ${srcdir}/tconfig.in
+then
+ sim_link_files=tconfig.in
+else
+ sim_link_files=../common/tconfig.in
+fi
+
+# targ-vals.def points to the libc macro description file.
+case "${target}" in
+*-*-*) TARG_VALS_DEF=../common/nltvals.def ;;
+esac
+sim_link_files="${sim_link_files} ${TARG_VALS_DEF}"
+sim_link_links="${sim_link_links} targ-vals.def"
+
+
+#SIM_AC_OPTION_ENDIAN(BIG_ENDIAN)
+wire_alignment="STRICT_ALIGNMENT"
+default_alignment=""
+
+# Check whether --enable-sim-alignment or --disable-sim-alignment was given.
+if test "${enable_sim_alignment+set}" = set; then
+ enableval="$enable_sim_alignment"
+ case "${enableval}" in
+ strict | STRICT) sim_alignment="-DWITH_ALIGNMENT=STRICT_ALIGNMENT";;
+ nonstrict | NONSTRICT) sim_alignment="-DWITH_ALIGNMENT=NONSTRICT_ALIGNMENT";;
+ forced | FORCED) sim_alignment="-DWITH_ALIGNMENT=FORCED_ALIGNMENT";;
+ yes) if test x"$wire_alignment" != x; then
+ sim_alignment="-DWITH_ALIGNMENT=${wire_alignment}"
+ else
+ if test x"$default_alignment" != x; then
+ sim_alignment="-DWITH_ALIGNMENT=${default_alignment}"
+ else
+ echo "No hard-wired alignment for target $target" 1>&6
+ sim_alignment="-DWITH_ALIGNMENT=0"
+ fi
+ fi;;
+ no) if test x"$default_alignment" != x; then
+ sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${default_alignment}"
+ else
+ if test x"$wire_alignment" != x; then
+ sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${wire_alignment}"
+ else
+ echo "No default alignment for target $target" 1>&6
+ sim_alignment="-DWITH_DEFAULT_ALIGNMENT=0"
+ fi
+ fi;;
+ *) { { echo "$as_me:$LINENO: error: \"Unknown value $enableval passed to --enable-sim-alignment\"" >&5
+echo "$as_me: error: \"Unknown value $enableval passed to --enable-sim-alignment\"" >&2;}
+ { (exit 1); exit 1; }; }; sim_alignment="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_alignment" != x""; then
+ echo "Setting alignment flags = $sim_alignment" 6>&1
+fi
+else
+ if test x"$default_alignment" != x; then
+ sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${default_alignment}"
+else
+ if test x"$wire_alignment" != x; then
+ sim_alignment="-DWITH_ALIGNMENT=${wire_alignment}"
+ else
+ sim_alignment=
+ fi
+fi
+fi;
+
+# Check whether --enable-sim-hostendian or --disable-sim-hostendian was given.
+if test "${enable_sim_hostendian+set}" = set; then
+ enableval="$enable_sim_hostendian"
+ case "${enableval}" in
+ no) sim_hostendian="-DWITH_HOST_BYTE_ORDER=0";;
+ b*|B*) sim_hostendian="-DWITH_HOST_BYTE_ORDER=BIG_ENDIAN";;
+ l*|L*) sim_hostendian="-DWITH_HOST_BYTE_ORDER=LITTLE_ENDIAN";;
+ *) { { echo "$as_me:$LINENO: error: \"Unknown value $enableval for --enable-sim-hostendian\"" >&5
+echo "$as_me: error: \"Unknown value $enableval for --enable-sim-hostendian\"" >&2;}
+ { (exit 1); exit 1; }; }; sim_hostendian="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_hostendian" != x""; then
+ echo "Setting hostendian flags = $sim_hostendian" 6>&1
+fi
+else
+
+if test "x$cross_compiling" = "xno"; then
+ echo "$as_me:$LINENO: checking whether byte ordering is bigendian" >&5
+echo $ECHO_N "checking whether byte ordering is bigendian... $ECHO_C" >&6
+if test "${ac_cv_c_bigendian+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ # See if sys/param.h defines the BYTE_ORDER macro.
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#include <sys/types.h>
+#include <sys/param.h>
+
+int
+main ()
+{
+#if !BYTE_ORDER || !BIG_ENDIAN || !LITTLE_ENDIAN
+ bogus endian macros
+#endif
+
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+ (eval $ac_compile) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ # It does; now see whether it defined to BIG_ENDIAN or not.
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#include <sys/types.h>
+#include <sys/param.h>
+
+int
+main ()
+{
+#if BYTE_ORDER != BIG_ENDIAN
+ not big endian
+#endif
+
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+ (eval $ac_compile) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_cv_c_bigendian=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_cv_c_bigendian=no
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+# It does not; compile a test program.
+if test "$cross_compiling" = yes; then
+ # try to guess the endianness by grepping values into an object file
+ ac_cv_c_bigendian=unknown
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+short ascii_mm[] = { 0x4249, 0x4765, 0x6E44, 0x6961, 0x6E53, 0x7953, 0 };
+short ascii_ii[] = { 0x694C, 0x5454, 0x656C, 0x6E45, 0x6944, 0x6E61, 0 };
+void _ascii () { char *s = (char *) ascii_mm; s = (char *) ascii_ii; }
+short ebcdic_ii[] = { 0x89D3, 0xE3E3, 0x8593, 0x95C5, 0x89C4, 0x9581, 0 };
+short ebcdic_mm[] = { 0xC2C9, 0xC785, 0x95C4, 0x8981, 0x95E2, 0xA8E2, 0 };
+void _ebcdic () { char *s = (char *) ebcdic_mm; s = (char *) ebcdic_ii; }
+int
+main ()
+{
+ _ascii (); _ebcdic ();
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+ (eval $ac_compile) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ if grep BIGenDianSyS conftest.$ac_objext >/dev/null ; then
+ ac_cv_c_bigendian=yes
+fi
+if grep LiTTleEnDian conftest.$ac_objext >/dev/null ; then
+ if test "$ac_cv_c_bigendian" = unknown; then
+ ac_cv_c_bigendian=no
+ else
+ # finding both strings is unlikely to happen, but who knows?
+ ac_cv_c_bigendian=unknown
+ fi
+fi
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+else
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+int
+main ()
+{
+ /* Are we little or big endian? From Harbison&Steele. */
+ union
+ {
+ long l;
+ char c[sizeof (long)];
+ } u;
+ u.l = 1;
+ exit (u.c[sizeof (long) - 1] == 1);
+}
+_ACEOF
+rm -f conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+ (eval $ac_link) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } && { ac_try='./conftest$ac_exeext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_cv_c_bigendian=no
+else
+ echo "$as_me: program exited with status $ac_status" >&5
+echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+( exit $ac_status )
+ac_cv_c_bigendian=yes
+fi
+rm -f core *.core gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext
+fi
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+fi
+echo "$as_me:$LINENO: result: $ac_cv_c_bigendian" >&5
+echo "${ECHO_T}$ac_cv_c_bigendian" >&6
+case $ac_cv_c_bigendian in
+ yes)
+
+cat >>confdefs.h <<\_ACEOF
+#define WORDS_BIGENDIAN 1
+_ACEOF
+ ;;
+ no)
+ ;;
+ *)
+ { { echo "$as_me:$LINENO: error: unknown endianness
+presetting ac_cv_c_bigendian=no (or yes) will help" >&5
+echo "$as_me: error: unknown endianness
+presetting ac_cv_c_bigendian=no (or yes) will help" >&2;}
+ { (exit 1); exit 1; }; } ;;
+esac
+
+ if test $ac_cv_c_bigendian = yes; then
+ sim_hostendian="-DWITH_HOST_BYTE_ORDER=BIG_ENDIAN"
+ else
+ sim_hostendian="-DWITH_HOST_BYTE_ORDER=LITTLE_ENDIAN"
+ fi
+else
+ sim_hostendian="-DWITH_HOST_BYTE_ORDER=0"
+fi
+fi;
+
+default_sim_scache="16384"
+# Check whether --enable-sim-scache or --disable-sim-scache was given.
+if test "${enable_sim_scache+set}" = set; then
+ enableval="$enable_sim_scache"
+ case "${enableval}" in
+ yes) sim_scache="-DWITH_SCACHE=${default_sim_scache}";;
+ no) sim_scache="-DWITH_SCACHE=0" ;;
+ [0-9]*) sim_scache="-DWITH_SCACHE=${enableval}";;
+ *) { { echo "$as_me:$LINENO: error: \"Bad value $enableval passed to --enable-sim-scache\"" >&5
+echo "$as_me: error: \"Bad value $enableval passed to --enable-sim-scache\"" >&2;}
+ { (exit 1); exit 1; }; };
+ sim_scache="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_scache" != x""; then
+ echo "Setting scache size = $sim_scache" 6>&1
+fi
+else
+ sim_scache="-DWITH_SCACHE=${default_sim_scache}"
+fi;
+
+
+default_sim_default_model="arc700"
+# Check whether --enable-sim-default-model or --disable-sim-default-model was given.
+if test "${enable_sim_default_model+set}" = set; then
+ enableval="$enable_sim_default_model"
+ case "${enableval}" in
+ yes|no) { { echo "$as_me:$LINENO: error: \"Missing argument to --enable-sim-default-model\"" >&5
+echo "$as_me: error: \"Missing argument to --enable-sim-default-model\"" >&2;}
+ { (exit 1); exit 1; }; };;
+ *) sim_default_model="-DWITH_DEFAULT_MODEL='\"${enableval}\"'";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_default_model" != x""; then
+ echo "Setting default model = $sim_default_model" 6>&1
+fi
+else
+ sim_default_model="-DWITH_DEFAULT_MODEL='\"${default_sim_default_model}\"'"
+fi;
+
+
+# Check whether --enable-sim-environment or --disable-sim-environment was given.
+if test "${enable_sim_environment+set}" = set; then
+ enableval="$enable_sim_environment"
+ case "${enableval}" in
+ all | ALL) sim_environment="-DWITH_ENVIRONMENT=ALL_ENVIRONMENT";;
+ user | USER) sim_environment="-DWITH_ENVIRONMENT=USER_ENVIRONMENT";;
+ virtual | VIRTUAL) sim_environment="-DWITH_ENVIRONMENT=VIRTUAL_ENVIRONMENT";;
+ operating | OPERATING) sim_environment="-DWITH_ENVIRONMENT=OPERATING_ENVIRONMENT";;
+ *) { { echo "$as_me:$LINENO: error: \"Unknown value $enableval passed to --enable-sim-environment\"" >&5
+echo "$as_me: error: \"Unknown value $enableval passed to --enable-sim-environment\"" >&2;}
+ { (exit 1); exit 1; }; };
+ sim_environment="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_environment" != x""; then
+ echo "Setting sim environment = $sim_environment" 6>&1
+fi
+else
+ sim_environment="-DWITH_ENVIRONMENT=ALL_ENVIRONMENT"
+fi;
+
+default_sim_inline=""
+# Check whether --enable-sim-inline or --disable-sim-inline was given.
+if test "${enable_sim_inline+set}" = set; then
+ enableval="$enable_sim_inline"
+ sim_inline=""
+case "$enableval" in
+ no) sim_inline="-DDEFAULT_INLINE=0";;
+ 0) sim_inline="-DDEFAULT_INLINE=0";;
+ yes | 2) sim_inline="-DDEFAULT_INLINE=ALL_C_INLINE";;
+ 1) sim_inline="-DDEFAULT_INLINE=INLINE_LOCALS";;
+ *) for x in `echo "$enableval" | sed -e "s/,/ /g"`; do
+ new_flag=""
+ case "$x" in
+ *_INLINE=*) new_flag="-D$x";;
+ *=*) new_flag=`echo "$x" | sed -e "s/=/_INLINE=/" -e "s/^/-D/"`;;
+ *_INLINE) new_flag="-D$x=ALL_C_INLINE";;
+ *) new_flag="-D$x""_INLINE=ALL_C_INLINE";;
+ esac
+ if test x"$sim_inline" = x""; then
+ sim_inline="$new_flag"
+ else
+ sim_inline="$sim_inline $new_flag"
+ fi
+ done;;
+esac
+if test x"$silent" != x"yes" && test x"$sim_inline" != x""; then
+ echo "Setting inline flags = $sim_inline" 6>&1
+fi
+else
+
+if test "x$cross_compiling" = "xno"; then
+ if test x"$GCC" != "x" -a x"${default_sim_inline}" != "x" ; then
+ sim_inline="${default_sim_inline}"
+ if test x"$silent" != x"yes"; then
+ echo "Setting inline flags = $sim_inline" 6>&1
+ fi
+ else
+ sim_inline=""
+ fi
+else
+ sim_inline="-DDEFAULT_INLINE=0"
+fi
+fi;
+
+cgen_maint=no
+cgen=guile
+cgendir='$(srcdir)/../../cgen'
+# Check whether --enable-cgen-maint or --disable-cgen-maint was given.
+if test "${enable_cgen_maint+set}" = set; then
+ enableval="$enable_cgen_maint"
+ case "${enableval}" in
+ yes) cgen_maint=yes ;;
+ no) cgen_maint=no ;;
+ *)
+ # argument is cgen install directory (not implemented yet).
+ # Having a `share' directory might be more appropriate for the .scm,
+ # .cpu, etc. files.
+ cgendir=${cgen_maint}/lib/cgen
+ cgen=guile
+ ;;
+esac
+fi; if test x${cgen_maint} != xno ; then
+ CGEN_MAINT=''
+else
+ CGEN_MAINT='#'
+fi
+
+
+
+
+
+ case "${target_alias}" in
+ arc*-linux*)
+ traps_obj=traps-linux.o
+ sim_extra_cflags="-DARC_LINUX"
+ ;;
+ *)
+ traps_obj=traps.o
+ sim_extra_cflags="-DARC_ELF"
+ ;;
+ esac
+
+
+
+
+
+ac_sources="$sim_link_files"
+ac_dests="$sim_link_links"
+while test -n "$ac_sources"; do
+ set $ac_dests; ac_dest=$1; shift; ac_dests=$*
+ set $ac_sources; ac_source=$1; shift; ac_sources=$*
+ ac_config_links_1="$ac_config_links_1 $ac_dest:$ac_source"
+done
+ ac_config_links="$ac_config_links $ac_config_links_1"
+
+cgen_breaks=""
+if grep CGEN_MAINT $srcdir/Makefile.in >/dev/null; then
+cgen_breaks="break cgen_rtx_error";
+fi
+
+ ac_config_files="$ac_config_files Makefile.sim:Makefile.in"
+
+ ac_config_files="$ac_config_files Make-common.sim:../common/Make-common.in"
+
+ ac_config_files="$ac_config_files .gdbinit:../common/gdbinit.in"
+
+ ac_config_commands="$ac_config_commands Makefile"
+
+ ac_config_commands="$ac_config_commands stamp-h"
+
+cat >confcache <<\_ACEOF
+# This file is a shell script that caches the results of configure
+# tests run on this system so they can be shared between configure
+# scripts and configure runs, see configure's option --config-cache.
+# It is not useful on other systems. If it contains results you don't
+# want to keep, you may remove or edit it.
+#
+# config.status only pays attention to the cache file if you give it
+# the --recheck option to rerun configure.
+#
+# `ac_cv_env_foo' variables (set or unset) will be overridden when
+# loading this file, other *unset* `ac_cv_foo' will be assigned the
+# following values.
+
+_ACEOF
+
+# The following way of writing the cache mishandles newlines in values,
+# but we know of no workaround that is simple, portable, and efficient.
+# So, don't put newlines in cache variables' values.
+# Ultrix sh set writes to stderr and can't be redirected directly,
+# and sets the high bit in the cache file unless we assign to the vars.
+{
+ (set) 2>&1 |
+ case `(ac_space=' '; set | grep ac_space) 2>&1` in
+ *ac_space=\ *)
+ # `set' does not quote correctly, so add quotes (double-quote
+ # substitution turns \\\\ into \\, and sed turns \\ into \).
+ sed -n \
+ "s/'/'\\\\''/g;
+ s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\\2'/p"
+ ;;
+ *)
+ # `set' quotes correctly as required by POSIX, so do not add quotes.
+ sed -n \
+ "s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1=\\2/p"
+ ;;
+ esac;
+} |
+ sed '
+ t clear
+ : clear
+ s/^\([^=]*\)=\(.*[{}].*\)$/test "${\1+set}" = set || &/
+ t end
+ /^ac_cv_env/!s/^\([^=]*\)=\(.*\)$/\1=${\1=\2}/
+ : end' >>confcache
+if diff $cache_file confcache >/dev/null 2>&1; then :; else
+ if test -w $cache_file; then
+ test "x$cache_file" != "x/dev/null" && echo "updating cache $cache_file"
+ cat confcache >$cache_file
+ else
+ echo "not updating unwritable cache $cache_file"
+ fi
+fi
+rm -f confcache
+
+test "x$prefix" = xNONE && prefix=$ac_default_prefix
+# Let make expand exec_prefix.
+test "x$exec_prefix" = xNONE && exec_prefix='${prefix}'
+
+# VPATH may cause trouble with some makes, so we remove $(srcdir),
+# ${srcdir} and @srcdir@ from VPATH if srcdir is ".", strip leading and
+# trailing colons and then remove the whole line if VPATH becomes empty
+# (actually we leave an empty line to preserve line numbers).
+if test "x$srcdir" = x.; then
+ ac_vpsub='/^[ ]*VPATH[ ]*=/{
+s/:*\$(srcdir):*/:/;
+s/:*\${srcdir}:*/:/;
+s/:*@srcdir@:*/:/;
+s/^\([^=]*=[ ]*\):*/\1/;
+s/:*$//;
+s/^[^=]*=[ ]*$//;
+}'
+fi
+
+DEFS=-DHAVE_CONFIG_H
+
+ac_libobjs=
+ac_ltlibobjs=
+for ac_i in : $LIBOBJS; do test "x$ac_i" = x: && continue
+ # 1. Remove the extension, and $U if already installed.
+ ac_i=`echo "$ac_i" |
+ sed 's/\$U\././;s/\.o$//;s/\.obj$//'`
+ # 2. Add them.
+ ac_libobjs="$ac_libobjs $ac_i\$U.$ac_objext"
+ ac_ltlibobjs="$ac_ltlibobjs $ac_i"'$U.lo'
+done
+LIBOBJS=$ac_libobjs
+
+LTLIBOBJS=$ac_ltlibobjs
+
+
+
+: ${CONFIG_STATUS=./config.status}
+ac_clean_files_save=$ac_clean_files
+ac_clean_files="$ac_clean_files $CONFIG_STATUS"
+{ echo "$as_me:$LINENO: creating $CONFIG_STATUS" >&5
+echo "$as_me: creating $CONFIG_STATUS" >&6;}
+cat >$CONFIG_STATUS <<_ACEOF
+#! $SHELL
+# Generated by $as_me.
+# Run this file to recreate the current configuration.
+# Compiler output produced by configure, useful for debugging
+# configure, is in config.log if it exists.
+
+debug=false
+ac_cs_recheck=false
+ac_cs_silent=false
+SHELL=\${CONFIG_SHELL-$SHELL}
+_ACEOF
+
+cat >>$CONFIG_STATUS <<\_ACEOF
+## --------------------- ##
+## M4sh Initialization. ##
+## --------------------- ##
+
+# Be Bourne compatible
+if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then
+ emulate sh
+ NULLCMD=:
+ # Zsh 3.x and 4.x performs word splitting on ${1+"$@"}, which
+ # is contrary to our usage. Disable this feature.
+ alias -g '${1+"$@"}'='"$@"'
+elif test -n "${BASH_VERSION+set}" && (set -o posix) >/dev/null 2>&1; then
+ set -o posix
+fi
+DUALCASE=1; export DUALCASE # for MKS sh
+
+# Support unset when possible.
+if ( (MAIL=60; unset MAIL) || exit) >/dev/null 2>&1; then
+ as_unset=unset
+else
+ as_unset=false
+fi
+
+
+# Work around bugs in pre-3.0 UWIN ksh.
+$as_unset ENV MAIL MAILPATH
+PS1='$ '
+PS2='> '
+PS4='+ '
+
+# NLS nuisances.
+for as_var in \
+ LANG LANGUAGE LC_ADDRESS LC_ALL LC_COLLATE LC_CTYPE LC_IDENTIFICATION \
+ LC_MEASUREMENT LC_MESSAGES LC_MONETARY LC_NAME LC_NUMERIC LC_PAPER \
+ LC_TELEPHONE LC_TIME
+do
+ if (set +x; test -z "`(eval $as_var=C; export $as_var) 2>&1`"); then
+ eval $as_var=C; export $as_var
+ else
+ $as_unset $as_var
+ fi
+done
+
+# Required to use basename.
+if expr a : '\(a\)' >/dev/null 2>&1; then
+ as_expr=expr
+else
+ as_expr=false
+fi
+
+if (basename /) >/dev/null 2>&1 && test "X`basename / 2>&1`" = "X/"; then
+ as_basename=basename
+else
+ as_basename=false
+fi
+
+
+# Name of the executable.
+as_me=`$as_basename "$0" ||
+$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \
+ X"$0" : 'X\(//\)$' \| \
+ X"$0" : 'X\(/\)$' \| \
+ . : '\(.\)' 2>/dev/null ||
+echo X/"$0" |
+ sed '/^.*\/\([^/][^/]*\)\/*$/{ s//\1/; q; }
+ /^X\/\(\/\/\)$/{ s//\1/; q; }
+ /^X\/\(\/\).*/{ s//\1/; q; }
+ s/.*/./; q'`
+
+
+# PATH needs CR, and LINENO needs CR and PATH.
+# Avoid depending upon Character Ranges.
+as_cr_letters='abcdefghijklmnopqrstuvwxyz'
+as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ'
+as_cr_Letters=$as_cr_letters$as_cr_LETTERS
+as_cr_digits='0123456789'
+as_cr_alnum=$as_cr_Letters$as_cr_digits
+
+# The user is always right.
+if test "${PATH_SEPARATOR+set}" != set; then
+ echo "#! /bin/sh" >conf$$.sh
+ echo "exit 0" >>conf$$.sh
+ chmod +x conf$$.sh
+ if (PATH="/nonexistent;."; conf$$.sh) >/dev/null 2>&1; then
+ PATH_SEPARATOR=';'
+ else
+ PATH_SEPARATOR=:
+ fi
+ rm -f conf$$.sh
+fi
+
+
+ as_lineno_1=$LINENO
+ as_lineno_2=$LINENO
+ as_lineno_3=`(expr $as_lineno_1 + 1) 2>/dev/null`
+ test "x$as_lineno_1" != "x$as_lineno_2" &&
+ test "x$as_lineno_3" = "x$as_lineno_2" || {
+ # Find who we are. Look in the path if we contain no path at all
+ # relative or not.
+ case $0 in
+ *[\\/]* ) as_myself=$0 ;;
+ *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break
+done
+
+ ;;
+ esac
+ # We did not find ourselves, most probably we were run as `sh COMMAND'
+ # in which case we are not to be found in the path.
+ if test "x$as_myself" = x; then
+ as_myself=$0
+ fi
+ if test ! -f "$as_myself"; then
+ { { echo "$as_me:$LINENO: error: cannot find myself; rerun with an absolute path" >&5
+echo "$as_me: error: cannot find myself; rerun with an absolute path" >&2;}
+ { (exit 1); exit 1; }; }
+ fi
+ case $CONFIG_SHELL in
+ '')
+ as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in /bin$PATH_SEPARATOR/usr/bin$PATH_SEPARATOR$PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ for as_base in sh bash ksh sh5; do
+ case $as_dir in
+ /*)
+ if ("$as_dir/$as_base" -c '
+ as_lineno_1=$LINENO
+ as_lineno_2=$LINENO
+ as_lineno_3=`(expr $as_lineno_1 + 1) 2>/dev/null`
+ test "x$as_lineno_1" != "x$as_lineno_2" &&
+ test "x$as_lineno_3" = "x$as_lineno_2" ') 2>/dev/null; then
+ $as_unset BASH_ENV || test "${BASH_ENV+set}" != set || { BASH_ENV=; export BASH_ENV; }
+ $as_unset ENV || test "${ENV+set}" != set || { ENV=; export ENV; }
+ CONFIG_SHELL=$as_dir/$as_base
+ export CONFIG_SHELL
+ exec "$CONFIG_SHELL" "$0" ${1+"$@"}
+ fi;;
+ esac
+ done
+done
+;;
+ esac
+
+ # Create $as_me.lineno as a copy of $as_myself, but with $LINENO
+ # uniformly replaced by the line number. The first 'sed' inserts a
+ # line-number line before each line; the second 'sed' does the real
+ # work. The second script uses 'N' to pair each line-number line
+ # with the numbered line, and appends trailing '-' during
+ # substitution so that $LINENO is not a special case at line end.
+ # (Raja R Harinath suggested sed '=', and Paul Eggert wrote the
+ # second 'sed' script. Blame Lee E. McMahon for sed's syntax. :-)
+ sed '=' <$as_myself |
+ sed '
+ N
+ s,$,-,
+ : loop
+ s,^\(['$as_cr_digits']*\)\(.*\)[$]LINENO\([^'$as_cr_alnum'_]\),\1\2\1\3,
+ t loop
+ s,-$,,
+ s,^['$as_cr_digits']*\n,,
+ ' >$as_me.lineno &&
+ chmod +x $as_me.lineno ||
+ { { echo "$as_me:$LINENO: error: cannot create $as_me.lineno; rerun with a POSIX shell" >&5
+echo "$as_me: error: cannot create $as_me.lineno; rerun with a POSIX shell" >&2;}
+ { (exit 1); exit 1; }; }
+
+ # Don't try to exec as it changes $[0], causing all sort of problems
+ # (the dirname of $[0] is not the place where we might find the
+ # original and so on. Autoconf is especially sensible to this).
+ . ./$as_me.lineno
+ # Exit status is that of the last command.
+ exit
+}
+
+
+case `echo "testing\c"; echo 1,2,3`,`echo -n testing; echo 1,2,3` in
+ *c*,-n*) ECHO_N= ECHO_C='
+' ECHO_T=' ' ;;
+ *c*,* ) ECHO_N=-n ECHO_C= ECHO_T= ;;
+ *) ECHO_N= ECHO_C='\c' ECHO_T= ;;
+esac
+
+if expr a : '\(a\)' >/dev/null 2>&1; then
+ as_expr=expr
+else
+ as_expr=false
+fi
+
+rm -f conf$$ conf$$.exe conf$$.file
+echo >conf$$.file
+if ln -s conf$$.file conf$$ 2>/dev/null; then
+ # We could just check for DJGPP; but this test a) works b) is more generic
+ # and c) will remain valid once DJGPP supports symlinks (DJGPP 2.04).
+ if test -f conf$$.exe; then
+ # Don't use ln at all; we don't have any links
+ as_ln_s='cp -p'
+ else
+ as_ln_s='ln -s'
+ fi
+elif ln conf$$.file conf$$ 2>/dev/null; then
+ as_ln_s=ln
+else
+ as_ln_s='cp -p'
+fi
+rm -f conf$$ conf$$.exe conf$$.file
+
+if mkdir -p . 2>/dev/null; then
+ as_mkdir_p=:
+else
+ test -d ./-p && rmdir ./-p
+ as_mkdir_p=false
+fi
+
+as_executable_p="test -f"
+
+# Sed expression to map a string onto a valid CPP name.
+as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'"
+
+# Sed expression to map a string onto a valid variable name.
+as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'"
+
+
+# IFS
+# We need space, tab and new line, in precisely that order.
+as_nl='
+'
+IFS=" $as_nl"
+
+# CDPATH.
+$as_unset CDPATH
+
+exec 6>&1
+
+# Open the log real soon, to keep \$[0] and so on meaningful, and to
+# report actual input values of CONFIG_FILES etc. instead of their
+# values after options handling. Logging --version etc. is OK.
+exec 5>>config.log
+{
+ echo
+ sed 'h;s/./-/g;s/^.../## /;s/...$/ ##/;p;x;p;x' <<_ASBOX
+## Running $as_me. ##
+_ASBOX
+} >&5
+cat >&5 <<_CSEOF
+
+This file was extended by $as_me, which was
+generated by GNU Autoconf 2.59. Invocation command line was
+
+ CONFIG_FILES = $CONFIG_FILES
+ CONFIG_HEADERS = $CONFIG_HEADERS
+ CONFIG_LINKS = $CONFIG_LINKS
+ CONFIG_COMMANDS = $CONFIG_COMMANDS
+ $ $0 $@
+
+_CSEOF
+echo "on `(hostname || uname -n) 2>/dev/null | sed 1q`" >&5
+echo >&5
+_ACEOF
+
+# Files that config.status was made for.
+if test -n "$ac_config_files"; then
+ echo "config_files=\"$ac_config_files\"" >>$CONFIG_STATUS
+fi
+
+if test -n "$ac_config_headers"; then
+ echo "config_headers=\"$ac_config_headers\"" >>$CONFIG_STATUS
+fi
+
+if test -n "$ac_config_links"; then
+ echo "config_links=\"$ac_config_links\"" >>$CONFIG_STATUS
+fi
+
+if test -n "$ac_config_commands"; then
+ echo "config_commands=\"$ac_config_commands\"" >>$CONFIG_STATUS
+fi
+
+cat >>$CONFIG_STATUS <<\_ACEOF
+
+ac_cs_usage="\
+\`$as_me' instantiates files from templates according to the
+current configuration.
+
+Usage: $0 [OPTIONS] [FILE]...
+
+ -h, --help print this help, then exit
+ -V, --version print version number, then exit
+ -q, --quiet do not print progress messages
+ -d, --debug don't remove temporary files
+ --recheck update $as_me by reconfiguring in the same conditions
+ --file=FILE[:TEMPLATE]
+ instantiate the configuration file FILE
+ --header=FILE[:TEMPLATE]
+ instantiate the configuration header FILE
+
+Configuration files:
+$config_files
+
+Configuration headers:
+$config_headers
+
+Configuration links:
+$config_links
+
+Configuration commands:
+$config_commands
+
+Report bugs to <bug-autoconf@gnu.org>."
+_ACEOF
+
+cat >>$CONFIG_STATUS <<_ACEOF
+ac_cs_version="\\
+config.status
+configured by $0, generated by GNU Autoconf 2.59,
+ with options \\"`echo "$ac_configure_args" | sed 's/[\\""\`\$]/\\\\&/g'`\\"
+
+Copyright (C) 2003 Free Software Foundation, Inc.
+This config.status script is free software; the Free Software Foundation
+gives unlimited permission to copy, distribute and modify it."
+srcdir=$srcdir
+INSTALL="$INSTALL"
+_ACEOF
+
+cat >>$CONFIG_STATUS <<\_ACEOF
+# If no file are specified by the user, then we need to provide default
+# value. By we need to know if files were specified by the user.
+ac_need_defaults=:
+while test $# != 0
+do
+ case $1 in
+ --*=*)
+ ac_option=`expr "x$1" : 'x\([^=]*\)='`
+ ac_optarg=`expr "x$1" : 'x[^=]*=\(.*\)'`
+ ac_shift=:
+ ;;
+ -*)
+ ac_option=$1
+ ac_optarg=$2
+ ac_shift=shift
+ ;;
+ *) # This is not an option, so the user has probably given explicit
+ # arguments.
+ ac_option=$1
+ ac_need_defaults=false;;
+ esac
+
+ case $ac_option in
+ # Handling of the options.
+_ACEOF
+cat >>$CONFIG_STATUS <<\_ACEOF
+ -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r)
+ ac_cs_recheck=: ;;
+ --version | --vers* | -V )
+ echo "$ac_cs_version"; exit 0 ;;
+ --he | --h)
+ # Conflict between --help and --header
+ { { echo "$as_me:$LINENO: error: ambiguous option: $1
+Try \`$0 --help' for more information." >&5
+echo "$as_me: error: ambiguous option: $1
+Try \`$0 --help' for more information." >&2;}
+ { (exit 1); exit 1; }; };;
+ --help | --hel | -h )
+ echo "$ac_cs_usage"; exit 0 ;;
+ --debug | --d* | -d )
+ debug=: ;;
+ --file | --fil | --fi | --f )
+ $ac_shift
+ CONFIG_FILES="$CONFIG_FILES $ac_optarg"
+ ac_need_defaults=false;;
+ --header | --heade | --head | --hea )
+ $ac_shift
+ CONFIG_HEADERS="$CONFIG_HEADERS $ac_optarg"
+ ac_need_defaults=false;;
+ -q | -quiet | --quiet | --quie | --qui | --qu | --q \
+ | -silent | --silent | --silen | --sile | --sil | --si | --s)
+ ac_cs_silent=: ;;
+
+ # This is an error.
+ -*) { { echo "$as_me:$LINENO: error: unrecognized option: $1
+Try \`$0 --help' for more information." >&5
+echo "$as_me: error: unrecognized option: $1
+Try \`$0 --help' for more information." >&2;}
+ { (exit 1); exit 1; }; } ;;
+
+ *) ac_config_targets="$ac_config_targets $1" ;;
+
+ esac
+ shift
+done
+
+ac_configure_extra_args=
+
+if $ac_cs_silent; then
+ exec 6>/dev/null
+ ac_configure_extra_args="$ac_configure_extra_args --silent"
+fi
+
+_ACEOF
+cat >>$CONFIG_STATUS <<_ACEOF
+if \$ac_cs_recheck; then
+ echo "running $SHELL $0 " $ac_configure_args \$ac_configure_extra_args " --no-create --no-recursion" >&6
+ exec $SHELL $0 $ac_configure_args \$ac_configure_extra_args --no-create --no-recursion
+fi
+
+_ACEOF
+
+
+
+
+
+cat >>$CONFIG_STATUS <<\_ACEOF
+for ac_config_target in $ac_config_targets
+do
+ case "$ac_config_target" in
+ # Handling of arguments.
+ "Makefile.sim" ) CONFIG_FILES="$CONFIG_FILES Makefile.sim:Makefile.in" ;;
+ "Make-common.sim" ) CONFIG_FILES="$CONFIG_FILES Make-common.sim:../common/Make-common.in" ;;
+ ".gdbinit" ) CONFIG_FILES="$CONFIG_FILES .gdbinit:../common/gdbinit.in" ;;
+ "$ac_config_links_1" ) CONFIG_LINKS="$CONFIG_LINKS $ac_config_links_1" ;;
+ "Makefile" ) CONFIG_COMMANDS="$CONFIG_COMMANDS Makefile" ;;
+ "stamp-h" ) CONFIG_COMMANDS="$CONFIG_COMMANDS stamp-h" ;;
+ "config.h" ) CONFIG_HEADERS="$CONFIG_HEADERS config.h:config.in" ;;
+ *) { { echo "$as_me:$LINENO: error: invalid argument: $ac_config_target" >&5
+echo "$as_me: error: invalid argument: $ac_config_target" >&2;}
+ { (exit 1); exit 1; }; };;
+ esac
+done
+
+# If the user did not use the arguments to specify the items to instantiate,
+# then the envvar interface is used. Set only those that are not.
+# We use the long form for the default assignment because of an extremely
+# bizarre bug on SunOS 4.1.3.
+if $ac_need_defaults; then
+ test "${CONFIG_FILES+set}" = set || CONFIG_FILES=$config_files
+ test "${CONFIG_HEADERS+set}" = set || CONFIG_HEADERS=$config_headers
+ test "${CONFIG_LINKS+set}" = set || CONFIG_LINKS=$config_links
+ test "${CONFIG_COMMANDS+set}" = set || CONFIG_COMMANDS=$config_commands
+fi
+
+# Have a temporary directory for convenience. Make it in the build tree
+# simply because there is no reason to put it here, and in addition,
+# creating and moving files from /tmp can sometimes cause problems.
+# Create a temporary directory, and hook for its removal unless debugging.
+$debug ||
+{
+ trap 'exit_status=$?; rm -rf $tmp && exit $exit_status' 0
+ trap '{ (exit 1); exit 1; }' 1 2 13 15
+}
+
+# Create a (secure) tmp directory for tmp files.
+
+{
+ tmp=`(umask 077 && mktemp -d -q "./confstatXXXXXX") 2>/dev/null` &&
+ test -n "$tmp" && test -d "$tmp"
+} ||
+{
+ tmp=./confstat$$-$RANDOM
+ (umask 077 && mkdir $tmp)
+} ||
+{
+ echo "$me: cannot create a temporary directory in ." >&2
+ { (exit 1); exit 1; }
+}
+
+_ACEOF
+
+cat >>$CONFIG_STATUS <<_ACEOF
+
+#
+# CONFIG_FILES section.
+#
+
+# No need to generate the scripts if there are no CONFIG_FILES.
+# This happens for instance when ./config.status config.h
+if test -n "\$CONFIG_FILES"; then
+ # Protect against being on the right side of a sed subst in config.status.
+ sed 's/,@/@@/; s/@,/@@/; s/,;t t\$/@;t t/; /@;t t\$/s/[\\\\&,]/\\\\&/g;
+ s/@@/,@/; s/@@/@,/; s/@;t t\$/,;t t/' >\$tmp/subs.sed <<\\CEOF
+s,@SHELL@,$SHELL,;t t
+s,@PATH_SEPARATOR@,$PATH_SEPARATOR,;t t
+s,@PACKAGE_NAME@,$PACKAGE_NAME,;t t
+s,@PACKAGE_TARNAME@,$PACKAGE_TARNAME,;t t
+s,@PACKAGE_VERSION@,$PACKAGE_VERSION,;t t
+s,@PACKAGE_STRING@,$PACKAGE_STRING,;t t
+s,@PACKAGE_BUGREPORT@,$PACKAGE_BUGREPORT,;t t
+s,@exec_prefix@,$exec_prefix,;t t
+s,@prefix@,$prefix,;t t
+s,@program_transform_name@,$program_transform_name,;t t
+s,@bindir@,$bindir,;t t
+s,@sbindir@,$sbindir,;t t
+s,@libexecdir@,$libexecdir,;t t
+s,@datadir@,$datadir,;t t
+s,@sysconfdir@,$sysconfdir,;t t
+s,@sharedstatedir@,$sharedstatedir,;t t
+s,@localstatedir@,$localstatedir,;t t
+s,@libdir@,$libdir,;t t
+s,@includedir@,$includedir,;t t
+s,@oldincludedir@,$oldincludedir,;t t
+s,@infodir@,$infodir,;t t
+s,@mandir@,$mandir,;t t
+s,@build_alias@,$build_alias,;t t
+s,@host_alias@,$host_alias,;t t
+s,@target_alias@,$target_alias,;t t
+s,@DEFS@,$DEFS,;t t
+s,@ECHO_C@,$ECHO_C,;t t
+s,@ECHO_N@,$ECHO_N,;t t
+s,@ECHO_T@,$ECHO_T,;t t
+s,@LIBS@,$LIBS,;t t
+s,@sim_environment@,$sim_environment,;t t
+s,@sim_alignment@,$sim_alignment,;t t
+s,@sim_assert@,$sim_assert,;t t
+s,@sim_bitsize@,$sim_bitsize,;t t
+s,@sim_endian@,$sim_endian,;t t
+s,@sim_hostendian@,$sim_hostendian,;t t
+s,@sim_float@,$sim_float,;t t
+s,@sim_scache@,$sim_scache,;t t
+s,@sim_default_model@,$sim_default_model,;t t
+s,@sim_hw_cflags@,$sim_hw_cflags,;t t
+s,@sim_hw_objs@,$sim_hw_objs,;t t
+s,@sim_hw@,$sim_hw,;t t
+s,@sim_inline@,$sim_inline,;t t
+s,@sim_packages@,$sim_packages,;t t
+s,@sim_regparm@,$sim_regparm,;t t
+s,@sim_reserved_bits@,$sim_reserved_bits,;t t
+s,@sim_smp@,$sim_smp,;t t
+s,@sim_stdcall@,$sim_stdcall,;t t
+s,@sim_xor_endian@,$sim_xor_endian,;t t
+s,@WARN_CFLAGS@,$WARN_CFLAGS,;t t
+s,@WERROR_CFLAGS@,$WERROR_CFLAGS,;t t
+s,@build@,$build,;t t
+s,@build_cpu@,$build_cpu,;t t
+s,@build_vendor@,$build_vendor,;t t
+s,@build_os@,$build_os,;t t
+s,@host@,$host,;t t
+s,@host_cpu@,$host_cpu,;t t
+s,@host_vendor@,$host_vendor,;t t
+s,@host_os@,$host_os,;t t
+s,@target@,$target,;t t
+s,@target_cpu@,$target_cpu,;t t
+s,@target_vendor@,$target_vendor,;t t
+s,@target_os@,$target_os,;t t
+s,@CC@,$CC,;t t
+s,@CFLAGS@,$CFLAGS,;t t
+s,@LDFLAGS@,$LDFLAGS,;t t
+s,@CPPFLAGS@,$CPPFLAGS,;t t
+s,@ac_ct_CC@,$ac_ct_CC,;t t
+s,@EXEEXT@,$EXEEXT,;t t
+s,@OBJEXT@,$OBJEXT,;t t
+s,@INSTALL_PROGRAM@,$INSTALL_PROGRAM,;t t
+s,@INSTALL_SCRIPT@,$INSTALL_SCRIPT,;t t
+s,@INSTALL_DATA@,$INSTALL_DATA,;t t
+s,@CC_FOR_BUILD@,$CC_FOR_BUILD,;t t
+s,@HDEFINES@,$HDEFINES,;t t
+s,@AR@,$AR,;t t
+s,@RANLIB@,$RANLIB,;t t
+s,@ac_ct_RANLIB@,$ac_ct_RANLIB,;t t
+s,@USE_NLS@,$USE_NLS,;t t
+s,@LIBINTL@,$LIBINTL,;t t
+s,@LIBINTL_DEP@,$LIBINTL_DEP,;t t
+s,@INCINTL@,$INCINTL,;t t
+s,@XGETTEXT@,$XGETTEXT,;t t
+s,@GMSGFMT@,$GMSGFMT,;t t
+s,@POSUB@,$POSUB,;t t
+s,@CATALOGS@,$CATALOGS,;t t
+s,@DATADIRNAME@,$DATADIRNAME,;t t
+s,@INSTOBJEXT@,$INSTOBJEXT,;t t
+s,@GENCAT@,$GENCAT,;t t
+s,@CATOBJEXT@,$CATOBJEXT,;t t
+s,@CPP@,$CPP,;t t
+s,@EGREP@,$EGREP,;t t
+s,@MAINT@,$MAINT,;t t
+s,@sim_bswap@,$sim_bswap,;t t
+s,@sim_cflags@,$sim_cflags,;t t
+s,@sim_debug@,$sim_debug,;t t
+s,@sim_stdio@,$sim_stdio,;t t
+s,@sim_trace@,$sim_trace,;t t
+s,@sim_profile@,$sim_profile,;t t
+s,@CGEN_MAINT@,$CGEN_MAINT,;t t
+s,@cgendir@,$cgendir,;t t
+s,@cgen@,$cgen,;t t
+s,@traps_obj@,$traps_obj,;t t
+s,@sim_extra_cflags@,$sim_extra_cflags,;t t
+s,@cgen_breaks@,$cgen_breaks,;t t
+s,@LIBOBJS@,$LIBOBJS,;t t
+s,@LTLIBOBJS@,$LTLIBOBJS,;t t
+CEOF
+
+_ACEOF
+
+ cat >>$CONFIG_STATUS <<\_ACEOF
+ # Split the substitutions into bite-sized pieces for seds with
+ # small command number limits, like on Digital OSF/1 and HP-UX.
+ ac_max_sed_lines=48
+ ac_sed_frag=1 # Number of current file.
+ ac_beg=1 # First line for current file.
+ ac_end=$ac_max_sed_lines # Line after last line for current file.
+ ac_more_lines=:
+ ac_sed_cmds=
+ while $ac_more_lines; do
+ if test $ac_beg -gt 1; then
+ sed "1,${ac_beg}d; ${ac_end}q" $tmp/subs.sed >$tmp/subs.frag
+ else
+ sed "${ac_end}q" $tmp/subs.sed >$tmp/subs.frag
+ fi
+ if test ! -s $tmp/subs.frag; then
+ ac_more_lines=false
+ else
+ # The purpose of the label and of the branching condition is to
+ # speed up the sed processing (if there are no `@' at all, there
+ # is no need to browse any of the substitutions).
+ # These are the two extra sed commands mentioned above.
+ (echo ':t
+ /@[a-zA-Z_][a-zA-Z_0-9]*@/!b' && cat $tmp/subs.frag) >$tmp/subs-$ac_sed_frag.sed
+ if test -z "$ac_sed_cmds"; then
+ ac_sed_cmds="sed -f $tmp/subs-$ac_sed_frag.sed"
+ else
+ ac_sed_cmds="$ac_sed_cmds | sed -f $tmp/subs-$ac_sed_frag.sed"
+ fi
+ ac_sed_frag=`expr $ac_sed_frag + 1`
+ ac_beg=$ac_end
+ ac_end=`expr $ac_end + $ac_max_sed_lines`
+ fi
+ done
+ if test -z "$ac_sed_cmds"; then
+ ac_sed_cmds=cat
+ fi
+fi # test -n "$CONFIG_FILES"
+
+_ACEOF
+cat >>$CONFIG_STATUS <<\_ACEOF
+for ac_file in : $CONFIG_FILES; do test "x$ac_file" = x: && continue
+ # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in".
+ case $ac_file in
+ - | *:- | *:-:* ) # input from stdin
+ cat >$tmp/stdin
+ ac_file_in=`echo "$ac_file" | sed 's,[^:]*:,,'`
+ ac_file=`echo "$ac_file" | sed 's,:.*,,'` ;;
+ *:* ) ac_file_in=`echo "$ac_file" | sed 's,[^:]*:,,'`
+ ac_file=`echo "$ac_file" | sed 's,:.*,,'` ;;
+ * ) ac_file_in=$ac_file.in ;;
+ esac
+
+ # Compute @srcdir@, @top_srcdir@, and @INSTALL@ for subdirectories.
+ ac_dir=`(dirname "$ac_file") 2>/dev/null ||
+$as_expr X"$ac_file" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
+ X"$ac_file" : 'X\(//\)[^/]' \| \
+ X"$ac_file" : 'X\(//\)$' \| \
+ X"$ac_file" : 'X\(/\)' \| \
+ . : '\(.\)' 2>/dev/null ||
+echo X"$ac_file" |
+ sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
+ /^X\(\/\/\)[^/].*/{ s//\1/; q; }
+ /^X\(\/\/\)$/{ s//\1/; q; }
+ /^X\(\/\).*/{ s//\1/; q; }
+ s/.*/./; q'`
+ { if $as_mkdir_p; then
+ mkdir -p "$ac_dir"
+ else
+ as_dir="$ac_dir"
+ as_dirs=
+ while test ! -d "$as_dir"; do
+ as_dirs="$as_dir $as_dirs"
+ as_dir=`(dirname "$as_dir") 2>/dev/null ||
+$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
+ X"$as_dir" : 'X\(//\)[^/]' \| \
+ X"$as_dir" : 'X\(//\)$' \| \
+ X"$as_dir" : 'X\(/\)' \| \
+ . : '\(.\)' 2>/dev/null ||
+echo X"$as_dir" |
+ sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
+ /^X\(\/\/\)[^/].*/{ s//\1/; q; }
+ /^X\(\/\/\)$/{ s//\1/; q; }
+ /^X\(\/\).*/{ s//\1/; q; }
+ s/.*/./; q'`
+ done
+ test ! -n "$as_dirs" || mkdir $as_dirs
+ fi || { { echo "$as_me:$LINENO: error: cannot create directory \"$ac_dir\"" >&5
+echo "$as_me: error: cannot create directory \"$ac_dir\"" >&2;}
+ { (exit 1); exit 1; }; }; }
+
+ ac_builddir=.
+
+if test "$ac_dir" != .; then
+ ac_dir_suffix=/`echo "$ac_dir" | sed 's,^\.[\\/],,'`
+ # A "../" for each directory in $ac_dir_suffix.
+ ac_top_builddir=`echo "$ac_dir_suffix" | sed 's,/[^\\/]*,../,g'`
+else
+ ac_dir_suffix= ac_top_builddir=
+fi
+
+case $srcdir in
+ .) # No --srcdir option. We are building in place.
+ ac_srcdir=.
+ if test -z "$ac_top_builddir"; then
+ ac_top_srcdir=.
+ else
+ ac_top_srcdir=`echo $ac_top_builddir | sed 's,/$,,'`
+ fi ;;
+ [\\/]* | ?:[\\/]* ) # Absolute path.
+ ac_srcdir=$srcdir$ac_dir_suffix;
+ ac_top_srcdir=$srcdir ;;
+ *) # Relative path.
+ ac_srcdir=$ac_top_builddir$srcdir$ac_dir_suffix
+ ac_top_srcdir=$ac_top_builddir$srcdir ;;
+esac
+
+# Do not use `cd foo && pwd` to compute absolute paths, because
+# the directories may not exist.
+case `pwd` in
+.) ac_abs_builddir="$ac_dir";;
+*)
+ case "$ac_dir" in
+ .) ac_abs_builddir=`pwd`;;
+ [\\/]* | ?:[\\/]* ) ac_abs_builddir="$ac_dir";;
+ *) ac_abs_builddir=`pwd`/"$ac_dir";;
+ esac;;
+esac
+case $ac_abs_builddir in
+.) ac_abs_top_builddir=${ac_top_builddir}.;;
+*)
+ case ${ac_top_builddir}. in
+ .) ac_abs_top_builddir=$ac_abs_builddir;;
+ [\\/]* | ?:[\\/]* ) ac_abs_top_builddir=${ac_top_builddir}.;;
+ *) ac_abs_top_builddir=$ac_abs_builddir/${ac_top_builddir}.;;
+ esac;;
+esac
+case $ac_abs_builddir in
+.) ac_abs_srcdir=$ac_srcdir;;
+*)
+ case $ac_srcdir in
+ .) ac_abs_srcdir=$ac_abs_builddir;;
+ [\\/]* | ?:[\\/]* ) ac_abs_srcdir=$ac_srcdir;;
+ *) ac_abs_srcdir=$ac_abs_builddir/$ac_srcdir;;
+ esac;;
+esac
+case $ac_abs_builddir in
+.) ac_abs_top_srcdir=$ac_top_srcdir;;
+*)
+ case $ac_top_srcdir in
+ .) ac_abs_top_srcdir=$ac_abs_builddir;;
+ [\\/]* | ?:[\\/]* ) ac_abs_top_srcdir=$ac_top_srcdir;;
+ *) ac_abs_top_srcdir=$ac_abs_builddir/$ac_top_srcdir;;
+ esac;;
+esac
+
+
+ case $INSTALL in
+ [\\/$]* | ?:[\\/]* ) ac_INSTALL=$INSTALL ;;
+ *) ac_INSTALL=$ac_top_builddir$INSTALL ;;
+ esac
+
+ if test x"$ac_file" != x-; then
+ { echo "$as_me:$LINENO: creating $ac_file" >&5
+echo "$as_me: creating $ac_file" >&6;}
+ rm -f "$ac_file"
+ fi
+ # Let's still pretend it is `configure' which instantiates (i.e., don't
+ # use $as_me), people would be surprised to read:
+ # /* config.h. Generated by config.status. */
+ if test x"$ac_file" = x-; then
+ configure_input=
+ else
+ configure_input="$ac_file. "
+ fi
+ configure_input=$configure_input"Generated from `echo $ac_file_in |
+ sed 's,.*/,,'` by configure."
+
+ # First look for the input files in the build tree, otherwise in the
+ # src tree.
+ ac_file_inputs=`IFS=:
+ for f in $ac_file_in; do
+ case $f in
+ -) echo $tmp/stdin ;;
+ [\\/$]*)
+ # Absolute (can't be DOS-style, as IFS=:)
+ test -f "$f" || { { echo "$as_me:$LINENO: error: cannot find input file: $f" >&5
+echo "$as_me: error: cannot find input file: $f" >&2;}
+ { (exit 1); exit 1; }; }
+ echo "$f";;
+ *) # Relative
+ if test -f "$f"; then
+ # Build tree
+ echo "$f"
+ elif test -f "$srcdir/$f"; then
+ # Source tree
+ echo "$srcdir/$f"
+ else
+ # /dev/null tree
+ { { echo "$as_me:$LINENO: error: cannot find input file: $f" >&5
+echo "$as_me: error: cannot find input file: $f" >&2;}
+ { (exit 1); exit 1; }; }
+ fi;;
+ esac
+ done` || { (exit 1); exit 1; }
+_ACEOF
+cat >>$CONFIG_STATUS <<_ACEOF
+ sed "$ac_vpsub
+$extrasub
+_ACEOF
+cat >>$CONFIG_STATUS <<\_ACEOF
+:t
+/@[a-zA-Z_][a-zA-Z_0-9]*@/!b
+s,@configure_input@,$configure_input,;t t
+s,@srcdir@,$ac_srcdir,;t t
+s,@abs_srcdir@,$ac_abs_srcdir,;t t
+s,@top_srcdir@,$ac_top_srcdir,;t t
+s,@abs_top_srcdir@,$ac_abs_top_srcdir,;t t
+s,@builddir@,$ac_builddir,;t t
+s,@abs_builddir@,$ac_abs_builddir,;t t
+s,@top_builddir@,$ac_top_builddir,;t t
+s,@abs_top_builddir@,$ac_abs_top_builddir,;t t
+s,@INSTALL@,$ac_INSTALL,;t t
+" $ac_file_inputs | (eval "$ac_sed_cmds") >$tmp/out
+ rm -f $tmp/stdin
+ if test x"$ac_file" != x-; then
+ mv $tmp/out $ac_file
+ else
+ cat $tmp/out
+ rm -f $tmp/out
+ fi
+
+done
+_ACEOF
+cat >>$CONFIG_STATUS <<\_ACEOF
+
+#
+# CONFIG_HEADER section.
+#
+
+# These sed commands are passed to sed as "A NAME B NAME C VALUE D", where
+# NAME is the cpp macro being defined and VALUE is the value it is being given.
+#
+# ac_d sets the value in "#define NAME VALUE" lines.
+ac_dA='s,^\([ ]*\)#\([ ]*define[ ][ ]*\)'
+ac_dB='[ ].*$,\1#\2'
+ac_dC=' '
+ac_dD=',;t'
+# ac_u turns "#undef NAME" without trailing blanks into "#define NAME VALUE".
+ac_uA='s,^\([ ]*\)#\([ ]*\)undef\([ ][ ]*\)'
+ac_uB='$,\1#\2define\3'
+ac_uC=' '
+ac_uD=',;t'
+
+for ac_file in : $CONFIG_HEADERS; do test "x$ac_file" = x: && continue
+ # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in".
+ case $ac_file in
+ - | *:- | *:-:* ) # input from stdin
+ cat >$tmp/stdin
+ ac_file_in=`echo "$ac_file" | sed 's,[^:]*:,,'`
+ ac_file=`echo "$ac_file" | sed 's,:.*,,'` ;;
+ *:* ) ac_file_in=`echo "$ac_file" | sed 's,[^:]*:,,'`
+ ac_file=`echo "$ac_file" | sed 's,:.*,,'` ;;
+ * ) ac_file_in=$ac_file.in ;;
+ esac
+
+ test x"$ac_file" != x- && { echo "$as_me:$LINENO: creating $ac_file" >&5
+echo "$as_me: creating $ac_file" >&6;}
+
+ # First look for the input files in the build tree, otherwise in the
+ # src tree.
+ ac_file_inputs=`IFS=:
+ for f in $ac_file_in; do
+ case $f in
+ -) echo $tmp/stdin ;;
+ [\\/$]*)
+ # Absolute (can't be DOS-style, as IFS=:)
+ test -f "$f" || { { echo "$as_me:$LINENO: error: cannot find input file: $f" >&5
+echo "$as_me: error: cannot find input file: $f" >&2;}
+ { (exit 1); exit 1; }; }
+ # Do quote $f, to prevent DOS paths from being IFS'd.
+ echo "$f";;
+ *) # Relative
+ if test -f "$f"; then
+ # Build tree
+ echo "$f"
+ elif test -f "$srcdir/$f"; then
+ # Source tree
+ echo "$srcdir/$f"
+ else
+ # /dev/null tree
+ { { echo "$as_me:$LINENO: error: cannot find input file: $f" >&5
+echo "$as_me: error: cannot find input file: $f" >&2;}
+ { (exit 1); exit 1; }; }
+ fi;;
+ esac
+ done` || { (exit 1); exit 1; }
+ # Remove the trailing spaces.
+ sed 's/[ ]*$//' $ac_file_inputs >$tmp/in
+
+_ACEOF
+
+# Transform confdefs.h into two sed scripts, `conftest.defines' and
+# `conftest.undefs', that substitutes the proper values into
+# config.h.in to produce config.h. The first handles `#define'
+# templates, and the second `#undef' templates.
+# And first: Protect against being on the right side of a sed subst in
+# config.status. Protect against being in an unquoted here document
+# in config.status.
+rm -f conftest.defines conftest.undefs
+# Using a here document instead of a string reduces the quoting nightmare.
+# Putting comments in sed scripts is not portable.
+#
+# `end' is used to avoid that the second main sed command (meant for
+# 0-ary CPP macros) applies to n-ary macro definitions.
+# See the Autoconf documentation for `clear'.
+cat >confdef2sed.sed <<\_ACEOF
+s/[\\&,]/\\&/g
+s,[\\$`],\\&,g
+t clear
+: clear
+s,^[ ]*#[ ]*define[ ][ ]*\([^ (][^ (]*\)\(([^)]*)\)[ ]*\(.*\)$,${ac_dA}\1${ac_dB}\1\2${ac_dC}\3${ac_dD},gp
+t end
+s,^[ ]*#[ ]*define[ ][ ]*\([^ ][^ ]*\)[ ]*\(.*\)$,${ac_dA}\1${ac_dB}\1${ac_dC}\2${ac_dD},gp
+: end
+_ACEOF
+# If some macros were called several times there might be several times
+# the same #defines, which is useless. Nevertheless, we may not want to
+# sort them, since we want the *last* AC-DEFINE to be honored.
+uniq confdefs.h | sed -n -f confdef2sed.sed >conftest.defines
+sed 's/ac_d/ac_u/g' conftest.defines >conftest.undefs
+rm -f confdef2sed.sed
+
+# This sed command replaces #undef with comments. This is necessary, for
+# example, in the case of _POSIX_SOURCE, which is predefined and required
+# on some systems where configure will not decide to define it.
+cat >>conftest.undefs <<\_ACEOF
+s,^[ ]*#[ ]*undef[ ][ ]*[a-zA-Z_][a-zA-Z_0-9]*,/* & */,
+_ACEOF
+
+# Break up conftest.defines because some shells have a limit on the size
+# of here documents, and old seds have small limits too (100 cmds).
+echo ' # Handle all the #define templates only if necessary.' >>$CONFIG_STATUS
+echo ' if grep "^[ ]*#[ ]*define" $tmp/in >/dev/null; then' >>$CONFIG_STATUS
+echo ' # If there are no defines, we may have an empty if/fi' >>$CONFIG_STATUS
+echo ' :' >>$CONFIG_STATUS
+rm -f conftest.tail
+while grep . conftest.defines >/dev/null
+do
+ # Write a limited-size here document to $tmp/defines.sed.
+ echo ' cat >$tmp/defines.sed <<CEOF' >>$CONFIG_STATUS
+ # Speed up: don't consider the non `#define' lines.
+ echo '/^[ ]*#[ ]*define/!b' >>$CONFIG_STATUS
+ # Work around the forget-to-reset-the-flag bug.
+ echo 't clr' >>$CONFIG_STATUS
+ echo ': clr' >>$CONFIG_STATUS
+ sed ${ac_max_here_lines}q conftest.defines >>$CONFIG_STATUS
+ echo 'CEOF
+ sed -f $tmp/defines.sed $tmp/in >$tmp/out
+ rm -f $tmp/in
+ mv $tmp/out $tmp/in
+' >>$CONFIG_STATUS
+ sed 1,${ac_max_here_lines}d conftest.defines >conftest.tail
+ rm -f conftest.defines
+ mv conftest.tail conftest.defines
+done
+rm -f conftest.defines
+echo ' fi # grep' >>$CONFIG_STATUS
+echo >>$CONFIG_STATUS
+
+# Break up conftest.undefs because some shells have a limit on the size
+# of here documents, and old seds have small limits too (100 cmds).
+echo ' # Handle all the #undef templates' >>$CONFIG_STATUS
+rm -f conftest.tail
+while grep . conftest.undefs >/dev/null
+do
+ # Write a limited-size here document to $tmp/undefs.sed.
+ echo ' cat >$tmp/undefs.sed <<CEOF' >>$CONFIG_STATUS
+ # Speed up: don't consider the non `#undef'
+ echo '/^[ ]*#[ ]*undef/!b' >>$CONFIG_STATUS
+ # Work around the forget-to-reset-the-flag bug.
+ echo 't clr' >>$CONFIG_STATUS
+ echo ': clr' >>$CONFIG_STATUS
+ sed ${ac_max_here_lines}q conftest.undefs >>$CONFIG_STATUS
+ echo 'CEOF
+ sed -f $tmp/undefs.sed $tmp/in >$tmp/out
+ rm -f $tmp/in
+ mv $tmp/out $tmp/in
+' >>$CONFIG_STATUS
+ sed 1,${ac_max_here_lines}d conftest.undefs >conftest.tail
+ rm -f conftest.undefs
+ mv conftest.tail conftest.undefs
+done
+rm -f conftest.undefs
+
+cat >>$CONFIG_STATUS <<\_ACEOF
+ # Let's still pretend it is `configure' which instantiates (i.e., don't
+ # use $as_me), people would be surprised to read:
+ # /* config.h. Generated by config.status. */
+ if test x"$ac_file" = x-; then
+ echo "/* Generated by configure. */" >$tmp/config.h
+ else
+ echo "/* $ac_file. Generated by configure. */" >$tmp/config.h
+ fi
+ cat $tmp/in >>$tmp/config.h
+ rm -f $tmp/in
+ if test x"$ac_file" != x-; then
+ if diff $ac_file $tmp/config.h >/dev/null 2>&1; then
+ { echo "$as_me:$LINENO: $ac_file is unchanged" >&5
+echo "$as_me: $ac_file is unchanged" >&6;}
+ else
+ ac_dir=`(dirname "$ac_file") 2>/dev/null ||
+$as_expr X"$ac_file" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
+ X"$ac_file" : 'X\(//\)[^/]' \| \
+ X"$ac_file" : 'X\(//\)$' \| \
+ X"$ac_file" : 'X\(/\)' \| \
+ . : '\(.\)' 2>/dev/null ||
+echo X"$ac_file" |
+ sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
+ /^X\(\/\/\)[^/].*/{ s//\1/; q; }
+ /^X\(\/\/\)$/{ s//\1/; q; }
+ /^X\(\/\).*/{ s//\1/; q; }
+ s/.*/./; q'`
+ { if $as_mkdir_p; then
+ mkdir -p "$ac_dir"
+ else
+ as_dir="$ac_dir"
+ as_dirs=
+ while test ! -d "$as_dir"; do
+ as_dirs="$as_dir $as_dirs"
+ as_dir=`(dirname "$as_dir") 2>/dev/null ||
+$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
+ X"$as_dir" : 'X\(//\)[^/]' \| \
+ X"$as_dir" : 'X\(//\)$' \| \
+ X"$as_dir" : 'X\(/\)' \| \
+ . : '\(.\)' 2>/dev/null ||
+echo X"$as_dir" |
+ sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
+ /^X\(\/\/\)[^/].*/{ s//\1/; q; }
+ /^X\(\/\/\)$/{ s//\1/; q; }
+ /^X\(\/\).*/{ s//\1/; q; }
+ s/.*/./; q'`
+ done
+ test ! -n "$as_dirs" || mkdir $as_dirs
+ fi || { { echo "$as_me:$LINENO: error: cannot create directory \"$ac_dir\"" >&5
+echo "$as_me: error: cannot create directory \"$ac_dir\"" >&2;}
+ { (exit 1); exit 1; }; }; }
+
+ rm -f $ac_file
+ mv $tmp/config.h $ac_file
+ fi
+ else
+ cat $tmp/config.h
+ rm -f $tmp/config.h
+ fi
+done
+_ACEOF
+cat >>$CONFIG_STATUS <<\_ACEOF
+
+#
+# CONFIG_LINKS section.
+#
+
+for ac_file in : $CONFIG_LINKS; do test "x$ac_file" = x: && continue
+ ac_dest=`echo "$ac_file" | sed 's,:.*,,'`
+ ac_source=`echo "$ac_file" | sed 's,[^:]*:,,'`
+
+ { echo "$as_me:$LINENO: linking $srcdir/$ac_source to $ac_dest" >&5
+echo "$as_me: linking $srcdir/$ac_source to $ac_dest" >&6;}
+
+ if test ! -r $srcdir/$ac_source; then
+ { { echo "$as_me:$LINENO: error: $srcdir/$ac_source: file not found" >&5
+echo "$as_me: error: $srcdir/$ac_source: file not found" >&2;}
+ { (exit 1); exit 1; }; }
+ fi
+ rm -f $ac_dest
+
+ # Make relative symlinks.
+ ac_dest_dir=`(dirname "$ac_dest") 2>/dev/null ||
+$as_expr X"$ac_dest" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
+ X"$ac_dest" : 'X\(//\)[^/]' \| \
+ X"$ac_dest" : 'X\(//\)$' \| \
+ X"$ac_dest" : 'X\(/\)' \| \
+ . : '\(.\)' 2>/dev/null ||
+echo X"$ac_dest" |
+ sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
+ /^X\(\/\/\)[^/].*/{ s//\1/; q; }
+ /^X\(\/\/\)$/{ s//\1/; q; }
+ /^X\(\/\).*/{ s//\1/; q; }
+ s/.*/./; q'`
+ { if $as_mkdir_p; then
+ mkdir -p "$ac_dest_dir"
+ else
+ as_dir="$ac_dest_dir"
+ as_dirs=
+ while test ! -d "$as_dir"; do
+ as_dirs="$as_dir $as_dirs"
+ as_dir=`(dirname "$as_dir") 2>/dev/null ||
+$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
+ X"$as_dir" : 'X\(//\)[^/]' \| \
+ X"$as_dir" : 'X\(//\)$' \| \
+ X"$as_dir" : 'X\(/\)' \| \
+ . : '\(.\)' 2>/dev/null ||
+echo X"$as_dir" |
+ sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
+ /^X\(\/\/\)[^/].*/{ s//\1/; q; }
+ /^X\(\/\/\)$/{ s//\1/; q; }
+ /^X\(\/\).*/{ s//\1/; q; }
+ s/.*/./; q'`
+ done
+ test ! -n "$as_dirs" || mkdir $as_dirs
+ fi || { { echo "$as_me:$LINENO: error: cannot create directory \"$ac_dest_dir\"" >&5
+echo "$as_me: error: cannot create directory \"$ac_dest_dir\"" >&2;}
+ { (exit 1); exit 1; }; }; }
+
+ ac_builddir=.
+
+if test "$ac_dest_dir" != .; then
+ ac_dir_suffix=/`echo "$ac_dest_dir" | sed 's,^\.[\\/],,'`
+ # A "../" for each directory in $ac_dir_suffix.
+ ac_top_builddir=`echo "$ac_dir_suffix" | sed 's,/[^\\/]*,../,g'`
+else
+ ac_dir_suffix= ac_top_builddir=
+fi
+
+case $srcdir in
+ .) # No --srcdir option. We are building in place.
+ ac_srcdir=.
+ if test -z "$ac_top_builddir"; then
+ ac_top_srcdir=.
+ else
+ ac_top_srcdir=`echo $ac_top_builddir | sed 's,/$,,'`
+ fi ;;
+ [\\/]* | ?:[\\/]* ) # Absolute path.
+ ac_srcdir=$srcdir$ac_dir_suffix;
+ ac_top_srcdir=$srcdir ;;
+ *) # Relative path.
+ ac_srcdir=$ac_top_builddir$srcdir$ac_dir_suffix
+ ac_top_srcdir=$ac_top_builddir$srcdir ;;
+esac
+
+# Do not use `cd foo && pwd` to compute absolute paths, because
+# the directories may not exist.
+case `pwd` in
+.) ac_abs_builddir="$ac_dest_dir";;
+*)
+ case "$ac_dest_dir" in
+ .) ac_abs_builddir=`pwd`;;
+ [\\/]* | ?:[\\/]* ) ac_abs_builddir="$ac_dest_dir";;
+ *) ac_abs_builddir=`pwd`/"$ac_dest_dir";;
+ esac;;
+esac
+case $ac_abs_builddir in
+.) ac_abs_top_builddir=${ac_top_builddir}.;;
+*)
+ case ${ac_top_builddir}. in
+ .) ac_abs_top_builddir=$ac_abs_builddir;;
+ [\\/]* | ?:[\\/]* ) ac_abs_top_builddir=${ac_top_builddir}.;;
+ *) ac_abs_top_builddir=$ac_abs_builddir/${ac_top_builddir}.;;
+ esac;;
+esac
+case $ac_abs_builddir in
+.) ac_abs_srcdir=$ac_srcdir;;
+*)
+ case $ac_srcdir in
+ .) ac_abs_srcdir=$ac_abs_builddir;;
+ [\\/]* | ?:[\\/]* ) ac_abs_srcdir=$ac_srcdir;;
+ *) ac_abs_srcdir=$ac_abs_builddir/$ac_srcdir;;
+ esac;;
+esac
+case $ac_abs_builddir in
+.) ac_abs_top_srcdir=$ac_top_srcdir;;
+*)
+ case $ac_top_srcdir in
+ .) ac_abs_top_srcdir=$ac_abs_builddir;;
+ [\\/]* | ?:[\\/]* ) ac_abs_top_srcdir=$ac_top_srcdir;;
+ *) ac_abs_top_srcdir=$ac_abs_builddir/$ac_top_srcdir;;
+ esac;;
+esac
+
+
+ case $srcdir in
+ [\\/$]* | ?:[\\/]* ) ac_rel_source=$srcdir/$ac_source ;;
+ *) ac_rel_source=$ac_top_builddir$srcdir/$ac_source ;;
+ esac
+
+ # Try a symlink, then a hard link, then a copy.
+ ln -s $ac_rel_source $ac_dest 2>/dev/null ||
+ ln $srcdir/$ac_source $ac_dest 2>/dev/null ||
+ cp -p $srcdir/$ac_source $ac_dest ||
+ { { echo "$as_me:$LINENO: error: cannot link or copy $srcdir/$ac_source to $ac_dest" >&5
+echo "$as_me: error: cannot link or copy $srcdir/$ac_source to $ac_dest" >&2;}
+ { (exit 1); exit 1; }; }
+done
+_ACEOF
+cat >>$CONFIG_STATUS <<\_ACEOF
+
+#
+# CONFIG_COMMANDS section.
+#
+for ac_file in : $CONFIG_COMMANDS; do test "x$ac_file" = x: && continue
+ ac_dest=`echo "$ac_file" | sed 's,:.*,,'`
+ ac_source=`echo "$ac_file" | sed 's,[^:]*:,,'`
+ ac_dir=`(dirname "$ac_dest") 2>/dev/null ||
+$as_expr X"$ac_dest" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
+ X"$ac_dest" : 'X\(//\)[^/]' \| \
+ X"$ac_dest" : 'X\(//\)$' \| \
+ X"$ac_dest" : 'X\(/\)' \| \
+ . : '\(.\)' 2>/dev/null ||
+echo X"$ac_dest" |
+ sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
+ /^X\(\/\/\)[^/].*/{ s//\1/; q; }
+ /^X\(\/\/\)$/{ s//\1/; q; }
+ /^X\(\/\).*/{ s//\1/; q; }
+ s/.*/./; q'`
+ { if $as_mkdir_p; then
+ mkdir -p "$ac_dir"
+ else
+ as_dir="$ac_dir"
+ as_dirs=
+ while test ! -d "$as_dir"; do
+ as_dirs="$as_dir $as_dirs"
+ as_dir=`(dirname "$as_dir") 2>/dev/null ||
+$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
+ X"$as_dir" : 'X\(//\)[^/]' \| \
+ X"$as_dir" : 'X\(//\)$' \| \
+ X"$as_dir" : 'X\(/\)' \| \
+ . : '\(.\)' 2>/dev/null ||
+echo X"$as_dir" |
+ sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
+ /^X\(\/\/\)[^/].*/{ s//\1/; q; }
+ /^X\(\/\/\)$/{ s//\1/; q; }
+ /^X\(\/\).*/{ s//\1/; q; }
+ s/.*/./; q'`
+ done
+ test ! -n "$as_dirs" || mkdir $as_dirs
+ fi || { { echo "$as_me:$LINENO: error: cannot create directory \"$ac_dir\"" >&5
+echo "$as_me: error: cannot create directory \"$ac_dir\"" >&2;}
+ { (exit 1); exit 1; }; }; }
+
+ ac_builddir=.
+
+if test "$ac_dir" != .; then
+ ac_dir_suffix=/`echo "$ac_dir" | sed 's,^\.[\\/],,'`
+ # A "../" for each directory in $ac_dir_suffix.
+ ac_top_builddir=`echo "$ac_dir_suffix" | sed 's,/[^\\/]*,../,g'`
+else
+ ac_dir_suffix= ac_top_builddir=
+fi
+
+case $srcdir in
+ .) # No --srcdir option. We are building in place.
+ ac_srcdir=.
+ if test -z "$ac_top_builddir"; then
+ ac_top_srcdir=.
+ else
+ ac_top_srcdir=`echo $ac_top_builddir | sed 's,/$,,'`
+ fi ;;
+ [\\/]* | ?:[\\/]* ) # Absolute path.
+ ac_srcdir=$srcdir$ac_dir_suffix;
+ ac_top_srcdir=$srcdir ;;
+ *) # Relative path.
+ ac_srcdir=$ac_top_builddir$srcdir$ac_dir_suffix
+ ac_top_srcdir=$ac_top_builddir$srcdir ;;
+esac
+
+# Do not use `cd foo && pwd` to compute absolute paths, because
+# the directories may not exist.
+case `pwd` in
+.) ac_abs_builddir="$ac_dir";;
+*)
+ case "$ac_dir" in
+ .) ac_abs_builddir=`pwd`;;
+ [\\/]* | ?:[\\/]* ) ac_abs_builddir="$ac_dir";;
+ *) ac_abs_builddir=`pwd`/"$ac_dir";;
+ esac;;
+esac
+case $ac_abs_builddir in
+.) ac_abs_top_builddir=${ac_top_builddir}.;;
+*)
+ case ${ac_top_builddir}. in
+ .) ac_abs_top_builddir=$ac_abs_builddir;;
+ [\\/]* | ?:[\\/]* ) ac_abs_top_builddir=${ac_top_builddir}.;;
+ *) ac_abs_top_builddir=$ac_abs_builddir/${ac_top_builddir}.;;
+ esac;;
+esac
+case $ac_abs_builddir in
+.) ac_abs_srcdir=$ac_srcdir;;
+*)
+ case $ac_srcdir in
+ .) ac_abs_srcdir=$ac_abs_builddir;;
+ [\\/]* | ?:[\\/]* ) ac_abs_srcdir=$ac_srcdir;;
+ *) ac_abs_srcdir=$ac_abs_builddir/$ac_srcdir;;
+ esac;;
+esac
+case $ac_abs_builddir in
+.) ac_abs_top_srcdir=$ac_top_srcdir;;
+*)
+ case $ac_top_srcdir in
+ .) ac_abs_top_srcdir=$ac_abs_builddir;;
+ [\\/]* | ?:[\\/]* ) ac_abs_top_srcdir=$ac_top_srcdir;;
+ *) ac_abs_top_srcdir=$ac_abs_builddir/$ac_top_srcdir;;
+ esac;;
+esac
+
+
+ { echo "$as_me:$LINENO: executing $ac_dest commands" >&5
+echo "$as_me: executing $ac_dest commands" >&6;}
+ case $ac_dest in
+ Makefile ) echo "Merging Makefile.sim+Make-common.sim into Makefile ..."
+ rm -f Makesim1.tmp Makesim2.tmp Makefile
+ sed -n -e '/^## COMMON_PRE_/,/^## End COMMON_PRE_/ p' <Make-common.sim >Makesim1.tmp
+ sed -n -e '/^## COMMON_POST_/,/^## End COMMON_POST_/ p' <Make-common.sim >Makesim2.tmp
+ sed -e '/^## COMMON_PRE_/ r Makesim1.tmp' \
+ -e '/^## COMMON_POST_/ r Makesim2.tmp' \
+ <Makefile.sim >Makefile
+ rm -f Makefile.sim Make-common.sim Makesim1.tmp Makesim2.tmp
+ ;;
+ stamp-h ) echo > stamp-h ;;
+ esac
+done
+_ACEOF
+
+cat >>$CONFIG_STATUS <<\_ACEOF
+
+{ (exit 0); exit 0; }
+_ACEOF
+chmod +x $CONFIG_STATUS
+ac_clean_files=$ac_clean_files_save
+
+
+# configure is writing to config.log, and then calls config.status.
+# config.status does its own redirection, appending to config.log.
+# Unfortunately, on DOS this fails, as config.log is still kept open
+# by configure, so config.status won't be able to write to it; its
+# output is simply discarded. So we exec the FD to /dev/null,
+# effectively closing config.log, so it can be properly (re)opened and
+# appended to by config.status. When coming back to configure, we
+# need to make the FD available again.
+if test "$no_create" != yes; then
+ ac_cs_success=:
+ ac_config_status_args=
+ test "$silent" = yes &&
+ ac_config_status_args="$ac_config_status_args --quiet"
+ exec 5>/dev/null
+ $SHELL $CONFIG_STATUS $ac_config_status_args || ac_cs_success=false
+ exec 5>>config.log
+ # Use ||, not &&, to avoid exiting from the if with $? = 1, which
+ # would make configure fail if this is the last instruction.
+ $ac_cs_success || { (exit 1); exit 1; }
+fi
+
+
diff --git a/sim/arc/configure.ac b/sim/arc/configure.ac
new file mode 100644
index 0000000..76d471e
--- /dev/null
+++ b/sim/arc/configure.ac
@@ -0,0 +1,35 @@
+dnl Process this file with autoconf to produce a configure script.
+AC_PREREQ(2.59)dnl
+AC_INIT(Makefile.in)
+AC_CONFIG_HEADER(config.h:config.in)
+
+sinclude(../common/aclocal.m4)
+
+# Bugs in autoconf 2.59 break the call to SIM_AC_COMMON, hack around
+# it by inlining the macro's contents.
+sinclude(../common/common.m4)
+
+#SIM_AC_OPTION_ENDIAN(BIG_ENDIAN)
+SIM_AC_OPTION_ALIGNMENT(STRICT_ALIGNMENT)
+SIM_AC_OPTION_HOSTENDIAN
+SIM_AC_OPTION_SCACHE(16384)
+SIM_AC_OPTION_DEFAULT_MODEL(arc700)
+SIM_AC_OPTION_ENVIRONMENT
+SIM_AC_OPTION_INLINE()
+SIM_AC_OPTION_CGEN_MAINT
+
+ case "${target_alias}" in
+ arc*-linux*)
+ traps_obj=traps-linux.o
+ sim_extra_cflags="-DARC_LINUX"
+ ;;
+ *)
+ traps_obj=traps.o
+ sim_extra_cflags="-DARC_ELF"
+ ;;
+ esac
+AC_SUBST(traps_obj)
+AC_SUBST(sim_extra_cflags)
+
+
+SIM_AC_OUTPUT
diff --git a/sim/arc/cpu5.c b/sim/arc/cpu5.c
new file mode 100644
index 0000000..8f47630
--- /dev/null
+++ b/sim/arc/cpu5.c
@@ -0,0 +1,501 @@
+/* Misc. support for CPU family a5f.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2007 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#define WANT_CPU a5f
+#define WANT_CPU_A5F
+
+#include "sim-main.h"
+#include "cgen-ops.h"
+
+/* Get the value of h-lbit. */
+
+BI
+a5f_h_lbit_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_lbit);
+}
+
+/* Set a value for h-lbit. */
+
+void
+a5f_h_lbit_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_lbit) = newval;
+}
+
+/* Get the value of h-zbit. */
+
+BI
+a5f_h_zbit_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_zbit);
+}
+
+/* Set a value for h-zbit. */
+
+void
+a5f_h_zbit_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_zbit) = newval;
+}
+
+/* Get the value of h-nbit. */
+
+BI
+a5f_h_nbit_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_nbit);
+}
+
+/* Set a value for h-nbit. */
+
+void
+a5f_h_nbit_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_nbit) = newval;
+}
+
+/* Get the value of h-cbit. */
+
+BI
+a5f_h_cbit_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_cbit);
+}
+
+/* Set a value for h-cbit. */
+
+void
+a5f_h_cbit_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_cbit) = newval;
+}
+
+/* Get the value of h-vbit. */
+
+BI
+a5f_h_vbit_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_vbit);
+}
+
+/* Set a value for h-vbit. */
+
+void
+a5f_h_vbit_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_vbit) = newval;
+}
+
+/* Get the value of h-ubit. */
+
+BI
+a5f_h_ubit_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_ubit);
+}
+
+/* Set a value for h-ubit. */
+
+void
+a5f_h_ubit_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_ubit) = newval;
+}
+
+/* Get the value of h-e1. */
+
+BI
+a5f_h_e1_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_e1);
+}
+
+/* Set a value for h-e1. */
+
+void
+a5f_h_e1_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_e1) = newval;
+}
+
+/* Get the value of h-e2. */
+
+BI
+a5f_h_e2_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_e2);
+}
+
+/* Set a value for h-e2. */
+
+void
+a5f_h_e2_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_e2) = newval;
+}
+
+/* Get the value of h-s1bit. */
+
+BI
+a5f_h_s1bit_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_s1bit);
+}
+
+/* Set a value for h-s1bit. */
+
+void
+a5f_h_s1bit_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_s1bit) = newval;
+}
+
+/* Get the value of h-s2bit. */
+
+BI
+a5f_h_s2bit_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_s2bit);
+}
+
+/* Set a value for h-s2bit. */
+
+void
+a5f_h_s2bit_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_s2bit) = newval;
+}
+
+/* Get the value of h-Qcondb. */
+
+BI
+a5f_h_Qcondb_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_QCONDB (regno);
+}
+
+/* Set a value for h-Qcondb. */
+
+void
+a5f_h_Qcondb_set (SIM_CPU *current_cpu, UINT regno, BI newval)
+{
+ SET_H_QCONDB (regno, newval);
+}
+
+/* Get the value of h-Qcondj. */
+
+BI
+a5f_h_Qcondj_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_QCONDJ (regno);
+}
+
+/* Set a value for h-Qcondj. */
+
+void
+a5f_h_Qcondj_set (SIM_CPU *current_cpu, UINT regno, BI newval)
+{
+ SET_H_QCONDJ (regno, newval);
+}
+
+/* Get the value of h-Qcondi. */
+
+BI
+a5f_h_Qcondi_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_QCONDI (regno);
+}
+
+/* Set a value for h-Qcondi. */
+
+void
+a5f_h_Qcondi_set (SIM_CPU *current_cpu, UINT regno, BI newval)
+{
+ SET_H_QCONDI (regno, newval);
+}
+
+/* Get the value of h-i2cond. */
+
+BI
+a5f_h_i2cond_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_I2COND (regno);
+}
+
+/* Set a value for h-i2cond. */
+
+void
+a5f_h_i2cond_set (SIM_CPU *current_cpu, UINT regno, BI newval)
+{
+ SET_H_I2COND (regno, newval);
+}
+
+/* Get the value of h-i3cond. */
+
+BI
+a5f_h_i3cond_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_I3COND (regno);
+}
+
+/* Set a value for h-i3cond. */
+
+void
+a5f_h_i3cond_set (SIM_CPU *current_cpu, UINT regno, BI newval)
+{
+ SET_H_I3COND (regno, newval);
+}
+
+/* Get the value of h-cr. */
+
+SI
+a5f_h_cr_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_CR (regno);
+}
+
+/* Set a value for h-cr. */
+
+void
+a5f_h_cr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_CR (regno, newval);
+}
+
+/* Get the value of h-cr16. */
+
+SI
+a5f_h_cr16_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_CR16 (regno);
+}
+
+/* Set a value for h-cr16. */
+
+void
+a5f_h_cr16_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_CR16 (regno, newval);
+}
+
+/* Get the value of h-r0. */
+
+SI
+a5f_h_r0_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_R0 (regno);
+}
+
+/* Set a value for h-r0. */
+
+void
+a5f_h_r0_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_R0 (regno, newval);
+}
+
+/* Get the value of h-gp. */
+
+SI
+a5f_h_gp_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_GP (regno);
+}
+
+/* Set a value for h-gp. */
+
+void
+a5f_h_gp_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_GP (regno, newval);
+}
+
+/* Get the value of h-sp. */
+
+SI
+a5f_h_sp_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_SP (regno);
+}
+
+/* Set a value for h-sp. */
+
+void
+a5f_h_sp_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_SP (regno, newval);
+}
+
+/* Get the value of h-pcl. */
+
+SI
+a5f_h_pcl_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_PCL (regno);
+}
+
+/* Set a value for h-pcl. */
+
+void
+a5f_h_pcl_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_PCL (regno, newval);
+}
+
+/* Get the value of h-noilink. */
+
+SI
+a5f_h_noilink_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_NOILINK (regno);
+}
+
+/* Set a value for h-noilink. */
+
+void
+a5f_h_noilink_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_NOILINK (regno, newval);
+}
+
+/* Get the value of h-ilinkx. */
+
+SI
+a5f_h_ilinkx_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_ILINKX (regno);
+}
+
+/* Set a value for h-ilinkx. */
+
+void
+a5f_h_ilinkx_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_ILINKX (regno, newval);
+}
+
+/* Get the value of h-r31. */
+
+SI
+a5f_h_r31_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_R31 (regno);
+}
+
+/* Set a value for h-r31. */
+
+void
+a5f_h_r31_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_R31 (regno, newval);
+}
+
+/* Get the value of h-auxr. */
+
+SI
+a5f_h_auxr_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_AUXR (regno);
+}
+
+/* Set a value for h-auxr. */
+
+void
+a5f_h_auxr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_AUXR (regno, newval);
+}
+
+/* Get the value of h-status32. */
+
+SI
+a5f_h_status32_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_STATUS32 (regno);
+}
+
+/* Set a value for h-status32. */
+
+void
+a5f_h_status32_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_STATUS32 (regno, newval);
+}
+
+/* Get the value of h-timer-expire. */
+
+SI
+a5f_h_timer_expire_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return CPU (h_timer_expire[regno]);
+}
+
+/* Set a value for h-timer-expire. */
+
+void
+a5f_h_timer_expire_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ CPU (h_timer_expire[regno]) = newval;
+}
+
+/* Get the value of h-prof-offset. */
+
+SI
+a5f_h_prof_offset_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return CPU (h_prof_offset[regno]);
+}
+
+/* Set a value for h-prof-offset. */
+
+void
+a5f_h_prof_offset_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ CPU (h_prof_offset[regno]) = newval;
+}
+
+/* Get the value of h-pc. */
+
+USI
+a5f_h_pc_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_pc);
+}
+
+/* Set a value for h-pc. */
+
+void
+a5f_h_pc_set (SIM_CPU *current_cpu, USI newval)
+{
+ CPU (h_pc) = newval;
+}
+
+/* Record trace results for INSN. */
+
+void
+a5f_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,
+ int *indices, TRACE_RECORD *tr)
+{
+}
diff --git a/sim/arc/cpu5.h b/sim/arc/cpu5.h
new file mode 100644
index 0000000..b6dccd0
--- /dev/null
+++ b/sim/arc/cpu5.h
@@ -0,0 +1,2059 @@
+/* CPU family header for a5f.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2007 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#ifndef CPU_A5F_H
+#define CPU_A5F_H
+
+/* Maximum number of instructions that are fetched at a time.
+ This is for LIW type instructions sets (e.g. m32r). */
+#define MAX_LIW_INSNS 1
+
+/* Maximum number of instructions that can be executed in parallel. */
+#define MAX_PARALLEL_INSNS 1
+
+/* CPU state information. */
+typedef struct {
+ /* Hardware elements. */
+ struct {
+ /* loop inhibit bit */
+ BI h_lbit;
+#define GET_H_LBIT() CPU (h_lbit)
+#define SET_H_LBIT(x) (CPU (h_lbit) = (x))
+ /* zerobit */
+ BI h_zbit;
+#define GET_H_ZBIT() CPU (h_zbit)
+#define SET_H_ZBIT(x) (CPU (h_zbit) = (x))
+ /* negative bit */
+ BI h_nbit;
+#define GET_H_NBIT() CPU (h_nbit)
+#define SET_H_NBIT(x) (CPU (h_nbit) = (x))
+ /* carry bit */
+ BI h_cbit;
+#define GET_H_CBIT() CPU (h_cbit)
+#define SET_H_CBIT(x) (CPU (h_cbit) = (x))
+ /* overflow bit */
+ BI h_vbit;
+#define GET_H_VBIT() CPU (h_vbit)
+#define SET_H_VBIT(x) (CPU (h_vbit) = (x))
+ /* user mode bit */
+ BI h_ubit;
+#define GET_H_UBIT() CPU (h_ubit)
+#define SET_H_UBIT(x) (CPU (h_ubit) = (x))
+ /* interupt 1 enable bit */
+ BI h_e1;
+#define GET_H_E1() CPU (h_e1)
+#define SET_H_E1(x) (CPU (h_e1) = (x))
+ /* interupt 2 enable bit */
+ BI h_e2;
+#define GET_H_E2() CPU (h_e2)
+#define SET_H_E2(x) (CPU (h_e2) = (x))
+ /* channel 1 saturate */
+ BI h_s1bit;
+#define GET_H_S1BIT() CPU (h_s1bit)
+#define SET_H_S1BIT(x) (CPU (h_s1bit) = (x))
+ /* channel 2 saturate */
+ BI h_s2bit;
+#define GET_H_S2BIT() CPU (h_s2bit)
+#define SET_H_S2BIT(x) (CPU (h_s2bit) = (x))
+ /* core registers */
+ SI h_cr[64];
+#define GET_H_CR(index) (index == 61) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (CPU (h_cr[index]))
+#define SET_H_CR(index, x) \
+do { \
+ switch ((index))\
+ {\
+ case 62 : {\
+((void) 0); /*nop*/\
+}\
+ break;\
+ case 61 : case 63 : {\
+cgen_rtx_error (current_cpu, "invalid insn");\
+}\
+ break;\
+ default : {\
+CPU (h_cr[(index)]) = (x);\
+}\
+ break;\
+ }\
+;} while (0)
+ /* auxiliary registers */
+ SI h_auxr[64];
+#define GET_H_AUXR(index) (index == 0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (index == 6) ? (ADDSI (CPU (h_pc), 4)) : (index == 10) ? (ORSI (SLLSI (ZEXTBISI (CPU (h_lbit)), 12), ORSI (SLLSI (ZEXTBISI (CPU (h_zbit)), 11), ORSI (SLLSI (ZEXTBISI (CPU (h_nbit)), 10), ORSI (SLLSI (ZEXTBISI (CPU (h_cbit)), 9), ORSI (SLLSI (ZEXTBISI (CPU (h_vbit)), 8), ORSI (SLLSI (ZEXTBISI (CPU (h_e1)), 1), SLLSI (ZEXTBISI (CPU (h_e2)), 2)))))))) : (index == 33) ? (ADDSI (CPU_INSN_COUNT (current_cpu), SUBSI (CPU (h_auxr[((UINT) 35)]), CPU (h_timer_expire[((UINT) 0)])))) : (index == 65) ? (ORSI (SLLSI (ZEXTBISI (CPU (h_s1bit)), 9), SLLSI (ZEXTBISI (CPU (h_s2bit)), 4))) : (CPU (h_auxr[index]))
+#define SET_H_AUXR(index, x) \
+do { \
+ switch ((index))\
+ {\
+ case 0 : {\
+cgen_rtx_error (current_cpu, "invalid insn");\
+}\
+ break;\
+ case 3 : {\
+{\
+CPU (h_auxr[((UINT) 3)]) = (x);\
+scache_flush_cpu (current_cpu);\
+}\
+}\
+ break;\
+ case 4 : case 5 : case 6 : case 10 : case 1027 : case 1040 : case 1041 : case 1046 : {\
+((void) 0); /*nop*/\
+}\
+ break;\
+ case 33 : case 34 : case 35 : {\
+{\
+CPU (h_auxr[(index)]) = (x);\
+CPU (h_timer_expire[((UINT) 0)]) = ADDSI (CPU_INSN_COUNT (current_cpu), SUBSI (CPU (h_auxr[((UINT) 35)]), CPU (h_auxr[((UINT) 33)])));\
+}\
+}\
+ break;\
+ case 65 : {\
+if (ANDSI ((x), 2)) {\
+CPU (h_s1bit) = 0;\
+CPU (h_s2bit) = 0;\
+}\
+}\
+ break;\
+ default : {\
+CPU (h_auxr[(index)]) = (x);\
+}\
+ break;\
+ }\
+;} while (0)
+ /* used internally in simulator to speed up timer expiration check */
+ SI h_timer_expire[1];
+#define GET_H_TIMER_EXPIRE(a1) CPU (h_timer_expire)[a1]
+#define SET_H_TIMER_EXPIRE(a1, x) (CPU (h_timer_expire)[a1] = (x))
+ /* offset to profile counters */
+ SI h_prof_offset[1];
+#define GET_H_PROF_OFFSET(a1) CPU (h_prof_offset)[a1]
+#define SET_H_PROF_OFFSET(a1, x) (CPU (h_prof_offset)[a1] = (x))
+ /* program counter */
+ USI h_pc;
+#define GET_H_PC() CPU (h_pc)
+#define SET_H_PC(x) (CPU (h_pc) = (x))
+ } hardware;
+#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
+} A5F_CPU_DATA;
+
+/* Virtual regs. */
+
+#define GET_H_QCONDB(index) (index == COND_AL) ? (1) : (index == COND_EQ) ? (CPU (h_zbit)) : (index == COND_NE) ? (NOTBI (CPU (h_zbit))) : (index == COND_PL) ? (NOTBI (CPU (h_nbit))) : (index == COND_MI) ? (CPU (h_nbit)) : (index == COND_CS) ? (CPU (h_cbit)) : (index == COND_CC) ? (NOTBI (CPU (h_cbit))) : (index == COND_VS) ? (CPU (h_vbit)) : (index == COND_VC) ? (NOTBI (CPU (h_vbit))) : (index == COND_GT) ? (ANDBI (NOTBI (CPU (h_zbit)), EQBI (CPU (h_nbit), CPU (h_vbit)))) : (index == COND_GE) ? (EQBI (CPU (h_nbit), CPU (h_vbit))) : (index == COND_LT) ? (NEBI (CPU (h_nbit), CPU (h_vbit))) : (index == COND_LE) ? (ORBI (CPU (h_zbit), NEBI (CPU (h_nbit), CPU (h_vbit)))) : (index == COND_HI) ? (ANDBI (NOTBI (CPU (h_cbit)), NOTBI (CPU (h_zbit)))) : (index == COND_LS) ? (ORBI (CPU (h_cbit), CPU (h_zbit))) : (index == COND_PNZ) ? (ANDBI (NOTBI (CPU (h_nbit)), NOTBI (CPU (h_zbit)))) : (((cgen_rtx_error (current_cpu, "invalid insn"), 0), 1))
+#define SET_H_QCONDB(index, x) \
+do { \
+((void) 0); /*nop*/\
+;} while (0)
+#define GET_H_QCONDJ(index) (index == COND_AL) ? (1) : (index == COND_EQ) ? (CPU (h_zbit)) : (index == COND_NE) ? (NOTBI (CPU (h_zbit))) : (index == COND_PL) ? (NOTBI (CPU (h_nbit))) : (index == COND_MI) ? (CPU (h_nbit)) : (index == COND_CS) ? (CPU (h_cbit)) : (index == COND_CC) ? (NOTBI (CPU (h_cbit))) : (index == COND_VS) ? (CPU (h_vbit)) : (index == COND_VC) ? (NOTBI (CPU (h_vbit))) : (index == COND_GT) ? (ANDBI (NOTBI (CPU (h_zbit)), EQBI (CPU (h_nbit), CPU (h_vbit)))) : (index == COND_GE) ? (EQBI (CPU (h_nbit), CPU (h_vbit))) : (index == COND_LT) ? (NEBI (CPU (h_nbit), CPU (h_vbit))) : (index == COND_LE) ? (ORBI (CPU (h_zbit), NEBI (CPU (h_nbit), CPU (h_vbit)))) : (index == COND_HI) ? (ANDBI (NOTBI (CPU (h_cbit)), NOTBI (CPU (h_zbit)))) : (index == COND_LS) ? (ORBI (CPU (h_cbit), CPU (h_zbit))) : (index == COND_PNZ) ? (ANDBI (NOTBI (CPU (h_nbit)), NOTBI (CPU (h_zbit)))) : (((cgen_rtx_error (current_cpu, "invalid insn"), 0), 1))
+#define SET_H_QCONDJ(index, x) \
+do { \
+((void) 0); /*nop*/\
+;} while (0)
+#define GET_H_QCONDI(index) (index == COND_AL) ? (1) : (index == COND_EQ) ? (CPU (h_zbit)) : (index == COND_NE) ? (NOTBI (CPU (h_zbit))) : (index == COND_PL) ? (NOTBI (CPU (h_nbit))) : (index == COND_MI) ? (CPU (h_nbit)) : (index == COND_CS) ? (CPU (h_cbit)) : (index == COND_CC) ? (NOTBI (CPU (h_cbit))) : (index == COND_VS) ? (CPU (h_vbit)) : (index == COND_VC) ? (NOTBI (CPU (h_vbit))) : (index == COND_GT) ? (ANDBI (NOTBI (CPU (h_zbit)), EQBI (CPU (h_nbit), CPU (h_vbit)))) : (index == COND_GE) ? (EQBI (CPU (h_nbit), CPU (h_vbit))) : (index == COND_LT) ? (NEBI (CPU (h_nbit), CPU (h_vbit))) : (index == COND_LE) ? (ORBI (CPU (h_zbit), NEBI (CPU (h_nbit), CPU (h_vbit)))) : (index == COND_HI) ? (ANDBI (NOTBI (CPU (h_cbit)), NOTBI (CPU (h_zbit)))) : (index == COND_LS) ? (ORBI (CPU (h_cbit), CPU (h_zbit))) : (index == COND_PNZ) ? (ANDBI (NOTBI (CPU (h_nbit)), NOTBI (CPU (h_zbit)))) : (((cgen_rtx_error (current_cpu, "invalid insn"), 0), 1))
+#define SET_H_QCONDI(index, x) \
+do { \
+((void) 0); /*nop*/\
+;} while (0)
+#define GET_H_I2COND(index) (index == 0) ? (1) : (index == 1) ? (CPU (h_zbit)) : (index == 2) ? (NOTBI (CPU (h_zbit))) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))
+#define SET_H_I2COND(index, x) \
+do { \
+((void) 0); /*nop*/\
+;} while (0)
+#define GET_H_I3COND(index) (index == COND3_CS) ? (CPU (h_cbit)) : (index == COND3_CC) ? (NOTBI (CPU (h_cbit))) : (index == COND3_GT) ? (ANDBI (NOTBI (CPU (h_zbit)), EQBI (CPU (h_nbit), CPU (h_vbit)))) : (index == COND3_GE) ? (EQBI (CPU (h_nbit), CPU (h_vbit))) : (index == COND3_LT) ? (NEBI (CPU (h_nbit), CPU (h_vbit))) : (index == COND3_LE) ? (ORBI (CPU (h_zbit), NEBI (CPU (h_nbit), CPU (h_vbit)))) : (index == COND3_HI) ? (ANDBI (NOTBI (CPU (h_cbit)), NOTBI (CPU (h_zbit)))) : (index == COND3_LS) ? (ORBI (CPU (h_cbit), CPU (h_zbit))) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))
+#define SET_H_I3COND(index, x) \
+do { \
+((void) 0); /*nop*/\
+;} while (0)
+#define GET_H_CR16(index) (index == 0 || index == 1 || index == 2 || index == 3) ? (CPU (h_cr[index])) : (CPU (h_cr[((index) + (8))]))
+#define SET_H_CR16(index, x) \
+do { \
+ switch ((index))\
+ {\
+ case 0 : case 1 : case 2 : case 3 : {\
+CPU (h_cr[(index)]) = (x);\
+}\
+ break;\
+ default : {\
+CPU (h_cr[(((index)) + (8))]) = (x);\
+}\
+ break;\
+ }\
+;} while (0)
+#define GET_H_R0(index) CPU (h_cr[((UINT) 0)])
+#define SET_H_R0(index, x) \
+do { \
+CPU (h_cr[((UINT) 0)]) = (x);\
+;} while (0)
+#define GET_H_GP(index) CPU (h_cr[((UINT) 26)])
+#define SET_H_GP(index, x) \
+do { \
+CPU (h_cr[((UINT) 26)]) = (x);\
+;} while (0)
+#define GET_H_SP(index) CPU (h_cr[((UINT) 28)])
+#define SET_H_SP(index, x) \
+do { \
+CPU (h_cr[((UINT) 28)]) = (x);\
+;} while (0)
+#define GET_H_PCL(index) CPU (h_cr[((UINT) 63)])
+#define SET_H_PCL(index, x) \
+do { \
+(cgen_rtx_error (current_cpu, "invalid insn"), 0);} while (0)
+#define GET_H_NOILINK(index) CPU (h_cr[index])
+#define SET_H_NOILINK(index, x) \
+do { \
+CPU (h_cr[(index)]) = (x);\
+;} while (0)
+#define GET_H_ILINKX(index) CPU (h_cr[index])
+#define SET_H_ILINKX(index, x) \
+do { \
+CPU (h_cr[(index)]) = (x);\
+;} while (0)
+#define GET_H_R31(index) CPU (h_cr[((UINT) 31)])
+#define SET_H_R31(index, x) \
+do { \
+CPU (h_cr[((UINT) 31)]) = (x);\
+;} while (0)
+#define GET_H_STATUS32(index) GET_H_AUXR (((UINT) 10))
+#define SET_H_STATUS32(index, x) \
+do { \
+{\
+CPU (h_lbit) = ANDSI (SRLSI ((x), 12), 1);\
+CPU (h_zbit) = ANDSI (SRLSI ((x), 11), 1);\
+CPU (h_nbit) = ANDSI (SRLSI ((x), 10), 1);\
+CPU (h_cbit) = ANDSI (SRLSI ((x), 9), 1);\
+CPU (h_vbit) = ANDSI (SRLSI ((x), 8), 1);\
+CPU (h_e1) = ANDSI (SRLSI ((x), 1), 1);\
+CPU (h_e2) = ANDSI (SRLSI ((x), 2), 1);\
+}\
+;} while (0)
+
+/* Cover fns for register access. */
+BI a5f_h_lbit_get (SIM_CPU *);
+void a5f_h_lbit_set (SIM_CPU *, BI);
+BI a5f_h_zbit_get (SIM_CPU *);
+void a5f_h_zbit_set (SIM_CPU *, BI);
+BI a5f_h_nbit_get (SIM_CPU *);
+void a5f_h_nbit_set (SIM_CPU *, BI);
+BI a5f_h_cbit_get (SIM_CPU *);
+void a5f_h_cbit_set (SIM_CPU *, BI);
+BI a5f_h_vbit_get (SIM_CPU *);
+void a5f_h_vbit_set (SIM_CPU *, BI);
+BI a5f_h_ubit_get (SIM_CPU *);
+void a5f_h_ubit_set (SIM_CPU *, BI);
+BI a5f_h_e1_get (SIM_CPU *);
+void a5f_h_e1_set (SIM_CPU *, BI);
+BI a5f_h_e2_get (SIM_CPU *);
+void a5f_h_e2_set (SIM_CPU *, BI);
+BI a5f_h_s1bit_get (SIM_CPU *);
+void a5f_h_s1bit_set (SIM_CPU *, BI);
+BI a5f_h_s2bit_get (SIM_CPU *);
+void a5f_h_s2bit_set (SIM_CPU *, BI);
+BI a5f_h_Qcondb_get (SIM_CPU *, UINT);
+void a5f_h_Qcondb_set (SIM_CPU *, UINT, BI);
+BI a5f_h_Qcondj_get (SIM_CPU *, UINT);
+void a5f_h_Qcondj_set (SIM_CPU *, UINT, BI);
+BI a5f_h_Qcondi_get (SIM_CPU *, UINT);
+void a5f_h_Qcondi_set (SIM_CPU *, UINT, BI);
+BI a5f_h_i2cond_get (SIM_CPU *, UINT);
+void a5f_h_i2cond_set (SIM_CPU *, UINT, BI);
+BI a5f_h_i3cond_get (SIM_CPU *, UINT);
+void a5f_h_i3cond_set (SIM_CPU *, UINT, BI);
+SI a5f_h_cr_get (SIM_CPU *, UINT);
+void a5f_h_cr_set (SIM_CPU *, UINT, SI);
+SI a5f_h_cr16_get (SIM_CPU *, UINT);
+void a5f_h_cr16_set (SIM_CPU *, UINT, SI);
+SI a5f_h_r0_get (SIM_CPU *, UINT);
+void a5f_h_r0_set (SIM_CPU *, UINT, SI);
+SI a5f_h_gp_get (SIM_CPU *, UINT);
+void a5f_h_gp_set (SIM_CPU *, UINT, SI);
+SI a5f_h_sp_get (SIM_CPU *, UINT);
+void a5f_h_sp_set (SIM_CPU *, UINT, SI);
+SI a5f_h_pcl_get (SIM_CPU *, UINT);
+void a5f_h_pcl_set (SIM_CPU *, UINT, SI);
+SI a5f_h_noilink_get (SIM_CPU *, UINT);
+void a5f_h_noilink_set (SIM_CPU *, UINT, SI);
+SI a5f_h_ilinkx_get (SIM_CPU *, UINT);
+void a5f_h_ilinkx_set (SIM_CPU *, UINT, SI);
+SI a5f_h_r31_get (SIM_CPU *, UINT);
+void a5f_h_r31_set (SIM_CPU *, UINT, SI);
+SI a5f_h_auxr_get (SIM_CPU *, UINT);
+void a5f_h_auxr_set (SIM_CPU *, UINT, SI);
+SI a5f_h_status32_get (SIM_CPU *, UINT);
+void a5f_h_status32_set (SIM_CPU *, UINT, SI);
+SI a5f_h_timer_expire_get (SIM_CPU *, UINT);
+void a5f_h_timer_expire_set (SIM_CPU *, UINT, SI);
+SI a5f_h_prof_offset_get (SIM_CPU *, UINT);
+void a5f_h_prof_offset_set (SIM_CPU *, UINT, SI);
+USI a5f_h_pc_get (SIM_CPU *);
+void a5f_h_pc_set (SIM_CPU *, USI);
+
+/* These must be hand-written. */
+extern CPUREG_FETCH_FN a5f_fetch_register;
+extern CPUREG_STORE_FN a5f_store_register;
+
+typedef struct {
+ int empty;
+} MODEL_A5_DATA;
+
+/* Instruction argument buffer. */
+
+union sem_fields {
+ struct { /* no operands */
+ int empty;
+ } fmt_empty;
+ struct { /* */
+ UINT f_trapnum;
+ } sfmt_trap_s;
+ struct { /* */
+ SI f_s9x2;
+ } sfmt_ldw_s_gprel;
+ struct { /* */
+ INT f_s9x1;
+ } sfmt_ldb_s_gprel;
+ struct { /* */
+ SI f_s9x4;
+ } sfmt_ld_s_gprel;
+ struct { /* */
+ IADDR i_label25a;
+ } sfmt_bl;
+ struct { /* */
+ IADDR i_label13a;
+ } sfmt_bl_s;
+ struct { /* */
+ IADDR i_label25;
+ } sfmt_b_l;
+ struct { /* */
+ INT f_s12x2;
+ UINT f_op_B;
+ } sfmt_lp_L_s12_;
+ struct { /* */
+ UINT f_op__b;
+ UINT f_u8;
+ } sfmt_mov_s_r_u7;
+ struct { /* */
+ UINT f_op__b;
+ UINT f_u7;
+ } sfmt_add_s_r_u7;
+ struct { /* */
+ UINT f_op__b;
+ UINT f_op_h;
+ } sfmt_add_s_mcah;
+ struct { /* */
+ SI f_u8x4;
+ UINT f_op__b;
+ } sfmt_ld_s_pcrel;
+ struct { /* */
+ IADDR i_label21a;
+ UINT f_cond_Q;
+ } sfmt_blcc;
+ struct { /* */
+ IADDR i_label21;
+ UINT f_cond_Q;
+ } sfmt_bcc_l;
+ struct { /* */
+ IADDR i_label7;
+ UINT f_cond_i3;
+ } sfmt_bcc_s;
+ struct { /* */
+ IADDR i_label10;
+ UINT f_cond_i2;
+ } sfmt_b_s;
+ struct { /* */
+ SI f_u6x2;
+ UINT f_cond_Q;
+ UINT f_op_B;
+ } sfmt_lpcc_ccu6;
+ struct { /* */
+ UINT f_op__b;
+ UINT f_op__c;
+ UINT f_u3;
+ } sfmt_add_s_cbu3;
+ struct { /* */
+ INT f_s12;
+ UINT f_F;
+ UINT f_op_B;
+ } sfmt_add_L_s12__RA_;
+ struct { /* */
+ INT f_s9;
+ UINT f_op_B;
+ UINT f_op_C;
+ } sfmt_st_abs;
+ struct { /* */
+ SI f_u5x2;
+ UINT f_op__b;
+ UINT f_op__c;
+ } sfmt_ldw_s_abu;
+ struct { /* */
+ UINT f_op__b;
+ UINT f_op__c;
+ UINT f_u5;
+ } sfmt_ldb_s_abu;
+ struct { /* */
+ SI f_u5x4;
+ UINT f_op__b;
+ UINT f_op__c;
+ } sfmt_ld_s_abu;
+ struct { /* */
+ UINT f_op__a;
+ UINT f_op__b;
+ UINT f_op__c;
+ } sfmt_ld_s_abc;
+ struct { /* */
+ INT f_s9;
+ UINT f_op_A;
+ UINT f_op_B;
+ } sfmt_ld_abs;
+ struct { /* */
+ IADDR i_label8;
+ UINT f_brscond;
+ UINT f_op__b;
+ } sfmt_brcc_s;
+ struct { /* */
+ UINT f_F;
+ UINT f_op_A;
+ UINT f_op_B;
+ UINT f_op_C;
+ } sfmt_add_L_r_r__RA__RC;
+ struct { /* */
+ UINT f_F;
+ UINT f_op_A;
+ UINT f_op_B;
+ UINT f_u6;
+ } sfmt_add_L_u6__RA_;
+ struct { /* */
+ UINT f_F;
+ UINT f_cond_Q;
+ UINT f_op_B;
+ UINT f_u6;
+ } sfmt_add_ccu6__RA_;
+ struct { /* */
+ IADDR i_label9;
+ UINT f_brcond;
+ UINT f_op_B;
+ UINT f_u6;
+ } sfmt_brcc_U6;
+ struct { /* */
+ IADDR i_label9;
+ UINT f_brcond;
+ UINT f_op_B;
+ UINT f_op_C;
+ } sfmt_brcc_RC;
+ struct { /* */
+ UINT f_F;
+ UINT f_cond_Q;
+ UINT f_op_B;
+ UINT f_op_C;
+ UINT f_op_Cj;
+ } sfmt_j_cc___RC_noilink_;
+#if WITH_SCACHE_PBB
+ /* Writeback handler. */
+ struct {
+ /* Pointer to argbuf entry for insn whose results need writing back. */
+ const struct argbuf *abuf;
+ } write;
+ /* x-before handler */
+ struct {
+ /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
+ int first_p;
+ } before;
+ /* x-after handler */
+ struct {
+ int empty;
+ } after;
+ /* This entry is used to terminate each pbb. */
+ struct {
+ /* Number of insns in pbb. */
+ int insn_count;
+ /* Next pbb to execute. */
+ SCACHE *next;
+ SCACHE *branch_target;
+ } chain;
+#endif
+};
+
+/* The ARGBUF struct. */
+struct argbuf {
+ /* These are the baseclass definitions. */
+ IADDR addr;
+ const IDESC *idesc;
+ char trace_p;
+ char profile_p;
+ /* ??? Temporary hack for skip insns. */
+ char skip_count;
+ char unused;
+ /* cpu specific data follows */
+ union sem semantic;
+ int written;
+ union sem_fields fields;
+};
+
+/* A cached insn.
+
+ ??? SCACHE used to contain more than just argbuf. We could delete the
+ type entirely and always just use ARGBUF, but for future concerns and as
+ a level of abstraction it is left in. */
+
+struct scache {
+ struct argbuf argbuf;
+};
+
+/* Macros to simplify extraction, reading and semantic code.
+ These define and assign the local vars that contain the insn's fields. */
+
+#define EXTRACT_IFMT_EMPTY_VARS \
+ unsigned int length;
+#define EXTRACT_IFMT_EMPTY_CODE \
+ length = 0; \
+
+#define EXTRACT_IFMT_B_S_VARS \
+ UINT f_opm; \
+ UINT f_cond_i2; \
+ SI f_rel10; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_B_S_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_cond_i2 = EXTRACT_MSB0_UINT (insn, 32, 5, 2); \
+ f_rel10 = ((((EXTRACT_MSB0_INT (insn, 32, 7, 9)) << (1))) + (((pc) & (-4)))); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_BCC_S_VARS \
+ UINT f_opm; \
+ UINT f_cond_i2; \
+ UINT f_cond_i3; \
+ SI f_rel7; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_BCC_S_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_cond_i2 = EXTRACT_MSB0_UINT (insn, 32, 5, 2); \
+ f_cond_i3 = EXTRACT_MSB0_UINT (insn, 32, 7, 3); \
+ f_rel7 = ((((EXTRACT_MSB0_INT (insn, 32, 10, 6)) << (1))) + (((pc) & (-4)))); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_BRCC_S_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_brscond; \
+ SI f_rel8; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_BRCC_S_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_brscond = EXTRACT_MSB0_UINT (insn, 32, 8, 1); \
+ f_rel8 = ((((EXTRACT_MSB0_INT (insn, 32, 9, 7)) << (1))) + (((pc) & (-4)))); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_BCC_L_VARS \
+ UINT f_opm; \
+ UINT f_d21l; \
+ INT f_d21h; \
+ INT f_rel21; \
+ UINT f_buf; \
+ UINT f_delay_N; \
+ UINT f_cond_Q; \
+ unsigned int length;
+#define EXTRACT_IFMT_BCC_L_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_d21l = EXTRACT_MSB0_UINT (insn, 32, 5, 10); \
+ f_d21h = EXTRACT_MSB0_INT (insn, 32, 16, 10); \
+{\
+ f_rel21 = ((((((f_d21l) << (1))) | (((f_d21h) << (11))))) + (((pc) & (-4))));\
+}\
+ f_buf = EXTRACT_MSB0_UINT (insn, 32, 15, 1); \
+ f_delay_N = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_B_L_VARS \
+ UINT f_opm; \
+ UINT f_d21l; \
+ UINT f_d25m; \
+ INT f_d25h; \
+ INT f_rel25; \
+ UINT f_buf; \
+ UINT f_delay_N; \
+ UINT f_res27; \
+ unsigned int length;
+#define EXTRACT_IFMT_B_L_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_d21l = EXTRACT_MSB0_UINT (insn, 32, 5, 10); \
+ f_d25m = EXTRACT_MSB0_UINT (insn, 32, 16, 10); \
+ f_d25h = EXTRACT_MSB0_INT (insn, 32, 28, 4); \
+{\
+ f_rel25 = ((((((((f_d21l) << (1))) | (((f_d25m) << (11))))) | (((f_d25h) << (21))))) + (((pc) & (-4))));\
+}\
+ f_buf = EXTRACT_MSB0_UINT (insn, 32, 15, 1); \
+ f_delay_N = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_res27 = EXTRACT_MSB0_UINT (insn, 32, 27, 1); \
+
+#define EXTRACT_IFMT_BRCC_RC_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_d9l; \
+ INT f_d9h; \
+ INT f_rel9; \
+ UINT f_buf; \
+ UINT f_op_C; \
+ UINT f_delay_N; \
+ UINT f_br; \
+ UINT f_brcond; \
+ unsigned int length;
+#define EXTRACT_IFMT_BRCC_RC_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_d9l = EXTRACT_MSB0_UINT (insn, 32, 8, 7); \
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1); \
+{\
+ f_rel9 = ((((((f_d9l) << (1))) | (((f_d9h) << (8))))) + (((pc) & (-4))));\
+}\
+ f_buf = EXTRACT_MSB0_UINT (insn, 32, 15, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_delay_N = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_br = EXTRACT_MSB0_UINT (insn, 32, 27, 1); \
+ f_brcond = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
+
+#define EXTRACT_IFMT_BRCC_U6_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_d9l; \
+ INT f_d9h; \
+ INT f_rel9; \
+ UINT f_buf; \
+ UINT f_u6; \
+ UINT f_delay_N; \
+ UINT f_br; \
+ UINT f_brcond; \
+ unsigned int length;
+#define EXTRACT_IFMT_BRCC_U6_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_d9l = EXTRACT_MSB0_UINT (insn, 32, 8, 7); \
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1); \
+{\
+ f_rel9 = ((((((f_d9l) << (1))) | (((f_d9h) << (8))))) + (((pc) & (-4))));\
+}\
+ f_buf = EXTRACT_MSB0_UINT (insn, 32, 15, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_delay_N = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_br = EXTRACT_MSB0_UINT (insn, 32, 27, 1); \
+ f_brcond = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
+
+#define EXTRACT_IFMT_BL_S_VARS \
+ UINT f_opm; \
+ SI f_rel13bl; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_BL_S_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_rel13bl = ((((EXTRACT_MSB0_INT (insn, 32, 5, 11)) << (2))) + (((pc) & (-4)))); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_BLCC_VARS \
+ UINT f_opm; \
+ UINT f_d21bl; \
+ INT f_d21h; \
+ INT f_rel21bl; \
+ UINT f_bluf; \
+ UINT f_buf; \
+ UINT f_delay_N; \
+ UINT f_cond_Q; \
+ unsigned int length;
+#define EXTRACT_IFMT_BLCC_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_d21bl = EXTRACT_MSB0_UINT (insn, 32, 5, 9); \
+ f_d21h = EXTRACT_MSB0_INT (insn, 32, 16, 10); \
+{\
+ f_rel21bl = ((((((f_d21bl) << (2))) | (((f_d21h) << (11))))) + (((pc) & (-4))));\
+}\
+ f_bluf = EXTRACT_MSB0_UINT (insn, 32, 14, 1); \
+ f_buf = EXTRACT_MSB0_UINT (insn, 32, 15, 1); \
+ f_delay_N = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_BL_VARS \
+ UINT f_opm; \
+ UINT f_d21bl; \
+ UINT f_d25m; \
+ INT f_d25h; \
+ INT f_rel25bl; \
+ UINT f_bluf; \
+ UINT f_buf; \
+ UINT f_delay_N; \
+ UINT f_res27; \
+ unsigned int length;
+#define EXTRACT_IFMT_BL_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_d21bl = EXTRACT_MSB0_UINT (insn, 32, 5, 9); \
+ f_d25m = EXTRACT_MSB0_UINT (insn, 32, 16, 10); \
+ f_d25h = EXTRACT_MSB0_INT (insn, 32, 28, 4); \
+{\
+ f_rel25bl = ((((((((f_d21bl) << (2))) | (((f_d25m) << (11))))) | (((f_d25h) << (21))))) + (((pc) & (-4))));\
+}\
+ f_bluf = EXTRACT_MSB0_UINT (insn, 32, 14, 1); \
+ f_buf = EXTRACT_MSB0_UINT (insn, 32, 15, 1); \
+ f_delay_N = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_res27 = EXTRACT_MSB0_UINT (insn, 32, 27, 1); \
+
+#define EXTRACT_IFMT_LD_ABS_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_u8; \
+ INT f_d9h; \
+ INT f_s9; \
+ UINT f_LDODi; \
+ UINT f_ldoaa; \
+ UINT f_ldozzx; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_LD_ABS_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8); \
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1); \
+{\
+ f_s9 = ((f_u8) | (((f_d9h) << (8))));\
+}\
+ f_LDODi = EXTRACT_MSB0_UINT (insn, 32, 20, 1); \
+ f_ldoaa = EXTRACT_MSB0_UINT (insn, 32, 21, 2); \
+ f_ldozzx = EXTRACT_MSB0_UINT (insn, 32, 23, 3); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_LD_ABC_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_ldraa; \
+ UINT f_ldr6zzx; \
+ UINT f_LDRDi; \
+ UINT f_op_C; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_LD_ABC_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_ldraa = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_ldr6zzx = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_LDRDi = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_LD_S_ABC_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_op__c; \
+ UINT f_i16_43; \
+ UINT f_op__a; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_LD_S_ABC_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3); \
+ f_i16_43 = EXTRACT_MSB0_UINT (insn, 32, 11, 2); \
+ f_op__a = EXTRACT_MSB0_UINT (insn, 32, 13, 3); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_LD_S_ABU_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_op__c; \
+ SI f_u5x4; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_LD_S_ABU_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3); \
+ f_u5x4 = ((EXTRACT_MSB0_UINT (insn, 32, 11, 5)) << (2)); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_LD_S_ABSP_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_op__c; \
+ SI f_u5x4; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_LD_S_ABSP_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3); \
+ f_u5x4 = ((EXTRACT_MSB0_UINT (insn, 32, 11, 5)) << (2)); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_LD_S_GPREL_VARS \
+ UINT f_opm; \
+ UINT f_i16_gp_type; \
+ SI f_s9x4; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_LD_S_GPREL_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_i16_gp_type = EXTRACT_MSB0_UINT (insn, 32, 5, 2); \
+ f_s9x4 = ((EXTRACT_MSB0_INT (insn, 32, 7, 9)) << (2)); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_LD_S_PCREL_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ SI f_u8x4; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_LD_S_PCREL_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_u8x4 = ((EXTRACT_MSB0_UINT (insn, 32, 8, 8)) << (2)); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_LDB_S_ABU_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_op__c; \
+ UINT f_u5; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_LDB_S_ABU_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3); \
+ f_u5 = EXTRACT_MSB0_UINT (insn, 32, 11, 5); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_LDB_S_GPREL_VARS \
+ UINT f_opm; \
+ UINT f_i16_gp_type; \
+ INT f_s9x1; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_LDB_S_GPREL_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_i16_gp_type = EXTRACT_MSB0_UINT (insn, 32, 5, 2); \
+ f_s9x1 = EXTRACT_MSB0_INT (insn, 32, 7, 9); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_LDW_S_ABU_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_op__c; \
+ SI f_u5x2; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_LDW_S_ABU_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3); \
+ f_u5x2 = ((EXTRACT_MSB0_UINT (insn, 32, 11, 5)) << (1)); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_LDW_S_GPREL_VARS \
+ UINT f_opm; \
+ UINT f_i16_gp_type; \
+ SI f_s9x2; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_LDW_S_GPREL_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_i16_gp_type = EXTRACT_MSB0_UINT (insn, 32, 5, 2); \
+ f_s9x2 = ((EXTRACT_MSB0_INT (insn, 32, 7, 9)) << (1)); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_ST_ABS_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_u8; \
+ INT f_d9h; \
+ INT f_s9; \
+ UINT f_LDODi; \
+ UINT f_op_C; \
+ UINT f_stoaa; \
+ UINT f_stozzr; \
+ unsigned int length;
+#define EXTRACT_IFMT_ST_ABS_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8); \
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1); \
+{\
+ f_s9 = ((f_u8) | (((f_d9h) << (8))));\
+}\
+ f_LDODi = EXTRACT_MSB0_UINT (insn, 32, 20, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_stoaa = EXTRACT_MSB0_UINT (insn, 32, 27, 2); \
+ f_stozzr = EXTRACT_MSB0_UINT (insn, 32, 29, 3); \
+
+#define EXTRACT_IFMT_ADD_L_S12__RA__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ INT f_s12h; \
+ INT f_s12; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADD_L_S12__RA__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6); \
+{\
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));\
+}\
+
+#define EXTRACT_IFMT_ADD_CCU6__RA__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ UINT f_go_cc_type; \
+ UINT f_cond_Q; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADD_CCU6__RA__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_go_cc_type = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_ADD_L_U6__RA__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADD_L_U6__RA__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_ADD_L_R_R__RA__RC_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_C; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADD_L_R_R__RA__RC_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_ADD_CC__RA__RC_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_C; \
+ UINT f_go_cc_type; \
+ UINT f_cond_Q; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADD_CC__RA__RC_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_go_cc_type = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_ADD_S_CBU3_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_op__c; \
+ UINT f_i16_43; \
+ UINT f_u3; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADD_S_CBU3_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3); \
+ f_i16_43 = EXTRACT_MSB0_UINT (insn, 32, 11, 2); \
+ f_u3 = EXTRACT_MSB0_UINT (insn, 32, 13, 3); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_ADD_S_MCAH_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_h_2_0; \
+ UINT f_h_5_3; \
+ UINT f_op_h; \
+ UINT f_i16_43; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADD_S_MCAH_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_h_2_0 = EXTRACT_MSB0_UINT (insn, 32, 8, 3); \
+ f_h_5_3 = EXTRACT_MSB0_UINT (insn, 32, 13, 3); \
+{\
+ f_op_h = ((f_h_2_0) | (((f_h_5_3) << (3))));\
+}\
+ f_i16_43 = EXTRACT_MSB0_UINT (insn, 32, 11, 2); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_ADD_S_ASSPSP_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_op__c; \
+ SI f_u5x4; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADD_S_ASSPSP_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3); \
+ f_u5x4 = ((EXTRACT_MSB0_UINT (insn, 32, 11, 5)) << (2)); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_ADD_S_GP_VARS \
+ UINT f_opm; \
+ UINT f_i16_gp_type; \
+ SI f_s9x4; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADD_S_GP_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_i16_gp_type = EXTRACT_MSB0_UINT (insn, 32, 5, 2); \
+ f_s9x4 = ((EXTRACT_MSB0_INT (insn, 32, 7, 9)) << (2)); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_ADD_S_R_U7_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_i16addcmpu7_type; \
+ UINT f_u7; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADD_S_R_U7_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_i16addcmpu7_type = EXTRACT_MSB0_UINT (insn, 32, 8, 1); \
+ f_u7 = EXTRACT_MSB0_UINT (insn, 32, 9, 7); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_I16_GO_SUB_S_GO_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_op__c; \
+ UINT f_i16_go; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_I16_GO_SUB_S_GO_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3); \
+ f_i16_go = EXTRACT_MSB0_UINT (insn, 32, 11, 5); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_SUB_S_GO_SUB_NE_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_op__c; \
+ UINT f_i16_go; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_SUB_S_GO_SUB_NE_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3); \
+ f_i16_go = EXTRACT_MSB0_UINT (insn, 32, 11, 5); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_SUB_S_SSB_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_op__c; \
+ UINT f_u5; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_SUB_S_SSB_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3); \
+ f_u5 = EXTRACT_MSB0_UINT (insn, 32, 11, 5); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_MOV_L_U6__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOV_L_U6__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_MOV_L_R_R__RC_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_C; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOV_L_R_R__RC_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_MOV_S_R_U7_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_u8; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOV_S_R_U7_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_TST_L_S12__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ INT f_s12h; \
+ INT f_s12; \
+ unsigned int length;
+#define EXTRACT_IFMT_TST_L_S12__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6); \
+{\
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));\
+}\
+
+#define EXTRACT_IFMT_TST_CCU6__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ UINT f_go_cc_type; \
+ UINT f_cond_Q; \
+ unsigned int length;
+#define EXTRACT_IFMT_TST_CCU6__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_go_cc_type = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_TST_L_U6__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_TST_L_U6__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_TST_L_R_R__RC_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_C; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_TST_L_R_R__RC_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_TST_CC__RC_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_C; \
+ UINT f_go_cc_type; \
+ UINT f_cond_Q; \
+ unsigned int length;
+#define EXTRACT_IFMT_TST_CC__RC_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_go_cc_type = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_J_L_R_R___RC_NOILINK__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_Cj; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_J_L_R_R___RC_NOILINK__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_Cj = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_J_CC___RC_NOILINK__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_Cj; \
+ UINT f_go_cc_type; \
+ UINT f_cond_Q; \
+ unsigned int length;
+#define EXTRACT_IFMT_J_CC___RC_NOILINK__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_Cj = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_go_cc_type = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_J_L_R_R___RC_ILINK__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_Cj; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_J_L_R_R___RC_ILINK__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_Cj = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_J_CC___RC_ILINK__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_Cj; \
+ UINT f_go_cc_type; \
+ UINT f_cond_Q; \
+ unsigned int length;
+#define EXTRACT_IFMT_J_CC___RC_ILINK__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_Cj = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_go_cc_type = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_J_L_S12__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ INT f_s12h; \
+ INT f_s12; \
+ unsigned int length;
+#define EXTRACT_IFMT_J_L_S12__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6); \
+{\
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));\
+}\
+
+#define EXTRACT_IFMT_J_CCU6__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ UINT f_go_cc_type; \
+ UINT f_cond_Q; \
+ unsigned int length;
+#define EXTRACT_IFMT_J_CCU6__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_go_cc_type = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_J_L_U6__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_J_L_U6__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_J_S__S_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_op__c; \
+ UINT f_i16_go; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_J_S__S_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3); \
+ f_i16_go = EXTRACT_MSB0_UINT (insn, 32, 11, 5); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_J_L_R_R_D___RC__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_C; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_J_L_R_R_D___RC__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_J_CC_D___RC__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_C; \
+ UINT f_go_cc_type; \
+ UINT f_cond_Q; \
+ unsigned int length;
+#define EXTRACT_IFMT_J_CC_D___RC__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_go_cc_type = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_LP_L_S12__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ INT f_s12h; \
+ INT f_s12x2; \
+ unsigned int length;
+#define EXTRACT_IFMT_LP_L_S12__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6); \
+{\
+ f_s12x2 = ((((f_u6) << (1))) | (((f_s12h) << (7))));\
+}\
+
+#define EXTRACT_IFMT_LPCC_CCU6_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ SI f_u6x2; \
+ UINT f_go_cc_type; \
+ UINT f_cond_Q; \
+ unsigned int length;
+#define EXTRACT_IFMT_LPCC_CCU6_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6x2 = ((EXTRACT_MSB0_UINT (insn, 32, 20, 6)) << (1)); \
+ f_go_cc_type = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_LR_L_R_R___RC__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_C; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_LR_L_R_R___RC__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_LR_L_S12__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ INT f_s12h; \
+ INT f_s12; \
+ unsigned int length;
+#define EXTRACT_IFMT_LR_L_S12__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6); \
+{\
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));\
+}\
+
+#define EXTRACT_IFMT_LR_L_U6__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_LR_L_U6__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_ASL_L_R_R__RC_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_C; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_ASL_L_R_R__RC_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_ASL_L_U6__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_ASL_L_U6__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_SWI_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_B_5_3; \
+ UINT f_op_C; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_SWI_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_TRAP_S_VARS \
+ UINT f_opm; \
+ UINT f_trapnum; \
+ UINT f_i16_go; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_TRAP_S_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_trapnum = EXTRACT_MSB0_UINT (insn, 32, 5, 6); \
+ f_i16_go = EXTRACT_MSB0_UINT (insn, 32, 11, 5); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_BRK_S_VARS \
+ UINT f_opm; \
+ UINT f_trapnum; \
+ UINT f_i16_go; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_BRK_S_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_trapnum = EXTRACT_MSB0_UINT (insn, 32, 5, 6); \
+ f_i16_go = EXTRACT_MSB0_UINT (insn, 32, 11, 5); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_DIVAW_CCU6__RA__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ UINT f_go_cc_type; \
+ UINT f_cond_Q; \
+ unsigned int length;
+#define EXTRACT_IFMT_DIVAW_CCU6__RA__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_go_cc_type = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_DIVAW_L_U6__RA__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_DIVAW_L_U6__RA__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_DIVAW_L_R_R__RA__RC_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_C; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_DIVAW_L_R_R__RA__RC_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_DIVAW_CC__RA__RC_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_C; \
+ UINT f_go_cc_type; \
+ UINT f_cond_Q; \
+ unsigned int length;
+#define EXTRACT_IFMT_DIVAW_CC__RA__RC_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_go_cc_type = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_POP_S_B_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_op__c; \
+ UINT f_u5; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_POP_S_B_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3); \
+ f_u5 = EXTRACT_MSB0_UINT (insn, 32, 11, 5); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_POP_S_BLINK_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_op__c; \
+ UINT f_u5; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_POP_S_BLINK_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3); \
+ f_u5 = EXTRACT_MSB0_UINT (insn, 32, 11, 5); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_CURRENT_LOOP_END_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_C; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_CURRENT_LOOP_END_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+/* Collection of various things for the trace handler to use. */
+
+typedef struct trace_record {
+ IADDR pc;
+ /* FIXME:wip */
+} TRACE_RECORD;
+
+#endif /* CPU_A5F_H */
diff --git a/sim/arc/cpu6.c b/sim/arc/cpu6.c
new file mode 100644
index 0000000..1a6a8c2
--- /dev/null
+++ b/sim/arc/cpu6.c
@@ -0,0 +1,501 @@
+/* Misc. support for CPU family arc600f.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2007 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#define WANT_CPU arc600f
+#define WANT_CPU_ARC600F
+
+#include "sim-main.h"
+#include "cgen-ops.h"
+
+/* Get the value of h-lbit. */
+
+BI
+arc600f_h_lbit_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_lbit);
+}
+
+/* Set a value for h-lbit. */
+
+void
+arc600f_h_lbit_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_lbit) = newval;
+}
+
+/* Get the value of h-zbit. */
+
+BI
+arc600f_h_zbit_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_zbit);
+}
+
+/* Set a value for h-zbit. */
+
+void
+arc600f_h_zbit_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_zbit) = newval;
+}
+
+/* Get the value of h-nbit. */
+
+BI
+arc600f_h_nbit_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_nbit);
+}
+
+/* Set a value for h-nbit. */
+
+void
+arc600f_h_nbit_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_nbit) = newval;
+}
+
+/* Get the value of h-cbit. */
+
+BI
+arc600f_h_cbit_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_cbit);
+}
+
+/* Set a value for h-cbit. */
+
+void
+arc600f_h_cbit_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_cbit) = newval;
+}
+
+/* Get the value of h-vbit. */
+
+BI
+arc600f_h_vbit_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_vbit);
+}
+
+/* Set a value for h-vbit. */
+
+void
+arc600f_h_vbit_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_vbit) = newval;
+}
+
+/* Get the value of h-ubit. */
+
+BI
+arc600f_h_ubit_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_ubit);
+}
+
+/* Set a value for h-ubit. */
+
+void
+arc600f_h_ubit_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_ubit) = newval;
+}
+
+/* Get the value of h-e1. */
+
+BI
+arc600f_h_e1_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_e1);
+}
+
+/* Set a value for h-e1. */
+
+void
+arc600f_h_e1_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_e1) = newval;
+}
+
+/* Get the value of h-e2. */
+
+BI
+arc600f_h_e2_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_e2);
+}
+
+/* Set a value for h-e2. */
+
+void
+arc600f_h_e2_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_e2) = newval;
+}
+
+/* Get the value of h-s1bit. */
+
+BI
+arc600f_h_s1bit_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_s1bit);
+}
+
+/* Set a value for h-s1bit. */
+
+void
+arc600f_h_s1bit_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_s1bit) = newval;
+}
+
+/* Get the value of h-s2bit. */
+
+BI
+arc600f_h_s2bit_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_s2bit);
+}
+
+/* Set a value for h-s2bit. */
+
+void
+arc600f_h_s2bit_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_s2bit) = newval;
+}
+
+/* Get the value of h-Qcondb. */
+
+BI
+arc600f_h_Qcondb_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_QCONDB (regno);
+}
+
+/* Set a value for h-Qcondb. */
+
+void
+arc600f_h_Qcondb_set (SIM_CPU *current_cpu, UINT regno, BI newval)
+{
+ SET_H_QCONDB (regno, newval);
+}
+
+/* Get the value of h-Qcondj. */
+
+BI
+arc600f_h_Qcondj_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_QCONDJ (regno);
+}
+
+/* Set a value for h-Qcondj. */
+
+void
+arc600f_h_Qcondj_set (SIM_CPU *current_cpu, UINT regno, BI newval)
+{
+ SET_H_QCONDJ (regno, newval);
+}
+
+/* Get the value of h-Qcondi. */
+
+BI
+arc600f_h_Qcondi_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_QCONDI (regno);
+}
+
+/* Set a value for h-Qcondi. */
+
+void
+arc600f_h_Qcondi_set (SIM_CPU *current_cpu, UINT regno, BI newval)
+{
+ SET_H_QCONDI (regno, newval);
+}
+
+/* Get the value of h-i2cond. */
+
+BI
+arc600f_h_i2cond_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_I2COND (regno);
+}
+
+/* Set a value for h-i2cond. */
+
+void
+arc600f_h_i2cond_set (SIM_CPU *current_cpu, UINT regno, BI newval)
+{
+ SET_H_I2COND (regno, newval);
+}
+
+/* Get the value of h-i3cond. */
+
+BI
+arc600f_h_i3cond_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_I3COND (regno);
+}
+
+/* Set a value for h-i3cond. */
+
+void
+arc600f_h_i3cond_set (SIM_CPU *current_cpu, UINT regno, BI newval)
+{
+ SET_H_I3COND (regno, newval);
+}
+
+/* Get the value of h-cr. */
+
+SI
+arc600f_h_cr_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_CR (regno);
+}
+
+/* Set a value for h-cr. */
+
+void
+arc600f_h_cr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_CR (regno, newval);
+}
+
+/* Get the value of h-cr16. */
+
+SI
+arc600f_h_cr16_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_CR16 (regno);
+}
+
+/* Set a value for h-cr16. */
+
+void
+arc600f_h_cr16_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_CR16 (regno, newval);
+}
+
+/* Get the value of h-r0. */
+
+SI
+arc600f_h_r0_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_R0 (regno);
+}
+
+/* Set a value for h-r0. */
+
+void
+arc600f_h_r0_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_R0 (regno, newval);
+}
+
+/* Get the value of h-gp. */
+
+SI
+arc600f_h_gp_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_GP (regno);
+}
+
+/* Set a value for h-gp. */
+
+void
+arc600f_h_gp_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_GP (regno, newval);
+}
+
+/* Get the value of h-sp. */
+
+SI
+arc600f_h_sp_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_SP (regno);
+}
+
+/* Set a value for h-sp. */
+
+void
+arc600f_h_sp_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_SP (regno, newval);
+}
+
+/* Get the value of h-pcl. */
+
+SI
+arc600f_h_pcl_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_PCL (regno);
+}
+
+/* Set a value for h-pcl. */
+
+void
+arc600f_h_pcl_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_PCL (regno, newval);
+}
+
+/* Get the value of h-noilink. */
+
+SI
+arc600f_h_noilink_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_NOILINK (regno);
+}
+
+/* Set a value for h-noilink. */
+
+void
+arc600f_h_noilink_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_NOILINK (regno, newval);
+}
+
+/* Get the value of h-ilinkx. */
+
+SI
+arc600f_h_ilinkx_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_ILINKX (regno);
+}
+
+/* Set a value for h-ilinkx. */
+
+void
+arc600f_h_ilinkx_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_ILINKX (regno, newval);
+}
+
+/* Get the value of h-r31. */
+
+SI
+arc600f_h_r31_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_R31 (regno);
+}
+
+/* Set a value for h-r31. */
+
+void
+arc600f_h_r31_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_R31 (regno, newval);
+}
+
+/* Get the value of h-auxr. */
+
+SI
+arc600f_h_auxr_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_AUXR (regno);
+}
+
+/* Set a value for h-auxr. */
+
+void
+arc600f_h_auxr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_AUXR (regno, newval);
+}
+
+/* Get the value of h-status32. */
+
+SI
+arc600f_h_status32_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_STATUS32 (regno);
+}
+
+/* Set a value for h-status32. */
+
+void
+arc600f_h_status32_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_STATUS32 (regno, newval);
+}
+
+/* Get the value of h-timer-expire. */
+
+SI
+arc600f_h_timer_expire_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return CPU (h_timer_expire[regno]);
+}
+
+/* Set a value for h-timer-expire. */
+
+void
+arc600f_h_timer_expire_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ CPU (h_timer_expire[regno]) = newval;
+}
+
+/* Get the value of h-prof-offset. */
+
+SI
+arc600f_h_prof_offset_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return CPU (h_prof_offset[regno]);
+}
+
+/* Set a value for h-prof-offset. */
+
+void
+arc600f_h_prof_offset_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ CPU (h_prof_offset[regno]) = newval;
+}
+
+/* Get the value of h-pc. */
+
+USI
+arc600f_h_pc_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_pc);
+}
+
+/* Set a value for h-pc. */
+
+void
+arc600f_h_pc_set (SIM_CPU *current_cpu, USI newval)
+{
+ CPU (h_pc) = newval;
+}
+
+/* Record trace results for INSN. */
+
+void
+arc600f_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,
+ int *indices, TRACE_RECORD *tr)
+{
+}
diff --git a/sim/arc/cpu6.h b/sim/arc/cpu6.h
new file mode 100644
index 0000000..738edbb
--- /dev/null
+++ b/sim/arc/cpu6.h
@@ -0,0 +1,2059 @@
+/* CPU family header for arc600f.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2007 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#ifndef CPU_ARC600F_H
+#define CPU_ARC600F_H
+
+/* Maximum number of instructions that are fetched at a time.
+ This is for LIW type instructions sets (e.g. m32r). */
+#define MAX_LIW_INSNS 1
+
+/* Maximum number of instructions that can be executed in parallel. */
+#define MAX_PARALLEL_INSNS 1
+
+/* CPU state information. */
+typedef struct {
+ /* Hardware elements. */
+ struct {
+ /* loop inhibit bit */
+ BI h_lbit;
+#define GET_H_LBIT() CPU (h_lbit)
+#define SET_H_LBIT(x) (CPU (h_lbit) = (x))
+ /* zerobit */
+ BI h_zbit;
+#define GET_H_ZBIT() CPU (h_zbit)
+#define SET_H_ZBIT(x) (CPU (h_zbit) = (x))
+ /* negative bit */
+ BI h_nbit;
+#define GET_H_NBIT() CPU (h_nbit)
+#define SET_H_NBIT(x) (CPU (h_nbit) = (x))
+ /* carry bit */
+ BI h_cbit;
+#define GET_H_CBIT() CPU (h_cbit)
+#define SET_H_CBIT(x) (CPU (h_cbit) = (x))
+ /* overflow bit */
+ BI h_vbit;
+#define GET_H_VBIT() CPU (h_vbit)
+#define SET_H_VBIT(x) (CPU (h_vbit) = (x))
+ /* user mode bit */
+ BI h_ubit;
+#define GET_H_UBIT() CPU (h_ubit)
+#define SET_H_UBIT(x) (CPU (h_ubit) = (x))
+ /* interupt 1 enable bit */
+ BI h_e1;
+#define GET_H_E1() CPU (h_e1)
+#define SET_H_E1(x) (CPU (h_e1) = (x))
+ /* interupt 2 enable bit */
+ BI h_e2;
+#define GET_H_E2() CPU (h_e2)
+#define SET_H_E2(x) (CPU (h_e2) = (x))
+ /* channel 1 saturate */
+ BI h_s1bit;
+#define GET_H_S1BIT() CPU (h_s1bit)
+#define SET_H_S1BIT(x) (CPU (h_s1bit) = (x))
+ /* channel 2 saturate */
+ BI h_s2bit;
+#define GET_H_S2BIT() CPU (h_s2bit)
+#define SET_H_S2BIT(x) (CPU (h_s2bit) = (x))
+ /* core registers */
+ SI h_cr[64];
+#define GET_H_CR(index) (index == 61) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (CPU (h_cr[index]))
+#define SET_H_CR(index, x) \
+do { \
+ switch ((index))\
+ {\
+ case 62 : {\
+((void) 0); /*nop*/\
+}\
+ break;\
+ case 61 : case 63 : {\
+cgen_rtx_error (current_cpu, "invalid insn");\
+}\
+ break;\
+ default : {\
+CPU (h_cr[(index)]) = (x);\
+}\
+ break;\
+ }\
+;} while (0)
+ /* auxiliary registers */
+ SI h_auxr[64];
+#define GET_H_AUXR(index) (index == 0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (index == 6) ? (ADDSI (CPU (h_pc), 4)) : (index == 10) ? (ORSI (SLLSI (ZEXTBISI (CPU (h_lbit)), 12), ORSI (SLLSI (ZEXTBISI (CPU (h_zbit)), 11), ORSI (SLLSI (ZEXTBISI (CPU (h_nbit)), 10), ORSI (SLLSI (ZEXTBISI (CPU (h_cbit)), 9), ORSI (SLLSI (ZEXTBISI (CPU (h_vbit)), 8), ORSI (SLLSI (ZEXTBISI (CPU (h_e1)), 1), SLLSI (ZEXTBISI (CPU (h_e2)), 2)))))))) : (index == 33) ? (ADDSI (CPU_INSN_COUNT (current_cpu), SUBSI (CPU (h_auxr[((UINT) 35)]), CPU (h_timer_expire[((UINT) 0)])))) : (index == 65) ? (ORSI (SLLSI (ZEXTBISI (CPU (h_s1bit)), 9), SLLSI (ZEXTBISI (CPU (h_s2bit)), 4))) : (CPU (h_auxr[index]))
+#define SET_H_AUXR(index, x) \
+do { \
+ switch ((index))\
+ {\
+ case 0 : {\
+cgen_rtx_error (current_cpu, "invalid insn");\
+}\
+ break;\
+ case 3 : {\
+{\
+CPU (h_auxr[((UINT) 3)]) = (x);\
+scache_flush_cpu (current_cpu);\
+}\
+}\
+ break;\
+ case 4 : case 5 : case 6 : case 10 : case 1027 : case 1040 : case 1041 : case 1046 : {\
+((void) 0); /*nop*/\
+}\
+ break;\
+ case 33 : case 34 : case 35 : {\
+{\
+CPU (h_auxr[(index)]) = (x);\
+CPU (h_timer_expire[((UINT) 0)]) = ADDSI (CPU_INSN_COUNT (current_cpu), SUBSI (CPU (h_auxr[((UINT) 35)]), CPU (h_auxr[((UINT) 33)])));\
+}\
+}\
+ break;\
+ case 65 : {\
+if (ANDSI ((x), 2)) {\
+CPU (h_s1bit) = 0;\
+CPU (h_s2bit) = 0;\
+}\
+}\
+ break;\
+ default : {\
+CPU (h_auxr[(index)]) = (x);\
+}\
+ break;\
+ }\
+;} while (0)
+ /* used internally in simulator to speed up timer expiration check */
+ SI h_timer_expire[1];
+#define GET_H_TIMER_EXPIRE(a1) CPU (h_timer_expire)[a1]
+#define SET_H_TIMER_EXPIRE(a1, x) (CPU (h_timer_expire)[a1] = (x))
+ /* offset to profile counters */
+ SI h_prof_offset[1];
+#define GET_H_PROF_OFFSET(a1) CPU (h_prof_offset)[a1]
+#define SET_H_PROF_OFFSET(a1, x) (CPU (h_prof_offset)[a1] = (x))
+ /* program counter */
+ USI h_pc;
+#define GET_H_PC() CPU (h_pc)
+#define SET_H_PC(x) (CPU (h_pc) = (x))
+ } hardware;
+#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
+} ARC600F_CPU_DATA;
+
+/* Virtual regs. */
+
+#define GET_H_QCONDB(index) (index == COND_AL) ? (1) : (index == COND_EQ) ? (CPU (h_zbit)) : (index == COND_NE) ? (NOTBI (CPU (h_zbit))) : (index == COND_PL) ? (NOTBI (CPU (h_nbit))) : (index == COND_MI) ? (CPU (h_nbit)) : (index == COND_CS) ? (CPU (h_cbit)) : (index == COND_CC) ? (NOTBI (CPU (h_cbit))) : (index == COND_VS) ? (CPU (h_vbit)) : (index == COND_VC) ? (NOTBI (CPU (h_vbit))) : (index == COND_GT) ? (ANDBI (NOTBI (CPU (h_zbit)), EQBI (CPU (h_nbit), CPU (h_vbit)))) : (index == COND_GE) ? (EQBI (CPU (h_nbit), CPU (h_vbit))) : (index == COND_LT) ? (NEBI (CPU (h_nbit), CPU (h_vbit))) : (index == COND_LE) ? (ORBI (CPU (h_zbit), NEBI (CPU (h_nbit), CPU (h_vbit)))) : (index == COND_HI) ? (ANDBI (NOTBI (CPU (h_cbit)), NOTBI (CPU (h_zbit)))) : (index == COND_LS) ? (ORBI (CPU (h_cbit), CPU (h_zbit))) : (index == COND_PNZ) ? (ANDBI (NOTBI (CPU (h_nbit)), NOTBI (CPU (h_zbit)))) : (((cgen_rtx_error (current_cpu, "invalid insn"), 0), 1))
+#define SET_H_QCONDB(index, x) \
+do { \
+((void) 0); /*nop*/\
+;} while (0)
+#define GET_H_QCONDJ(index) (index == COND_AL) ? (1) : (index == COND_EQ) ? (CPU (h_zbit)) : (index == COND_NE) ? (NOTBI (CPU (h_zbit))) : (index == COND_PL) ? (NOTBI (CPU (h_nbit))) : (index == COND_MI) ? (CPU (h_nbit)) : (index == COND_CS) ? (CPU (h_cbit)) : (index == COND_CC) ? (NOTBI (CPU (h_cbit))) : (index == COND_VS) ? (CPU (h_vbit)) : (index == COND_VC) ? (NOTBI (CPU (h_vbit))) : (index == COND_GT) ? (ANDBI (NOTBI (CPU (h_zbit)), EQBI (CPU (h_nbit), CPU (h_vbit)))) : (index == COND_GE) ? (EQBI (CPU (h_nbit), CPU (h_vbit))) : (index == COND_LT) ? (NEBI (CPU (h_nbit), CPU (h_vbit))) : (index == COND_LE) ? (ORBI (CPU (h_zbit), NEBI (CPU (h_nbit), CPU (h_vbit)))) : (index == COND_HI) ? (ANDBI (NOTBI (CPU (h_cbit)), NOTBI (CPU (h_zbit)))) : (index == COND_LS) ? (ORBI (CPU (h_cbit), CPU (h_zbit))) : (index == COND_PNZ) ? (ANDBI (NOTBI (CPU (h_nbit)), NOTBI (CPU (h_zbit)))) : (((cgen_rtx_error (current_cpu, "invalid insn"), 0), 1))
+#define SET_H_QCONDJ(index, x) \
+do { \
+((void) 0); /*nop*/\
+;} while (0)
+#define GET_H_QCONDI(index) (index == COND_AL) ? (1) : (index == COND_EQ) ? (CPU (h_zbit)) : (index == COND_NE) ? (NOTBI (CPU (h_zbit))) : (index == COND_PL) ? (NOTBI (CPU (h_nbit))) : (index == COND_MI) ? (CPU (h_nbit)) : (index == COND_CS) ? (CPU (h_cbit)) : (index == COND_CC) ? (NOTBI (CPU (h_cbit))) : (index == COND_VS) ? (CPU (h_vbit)) : (index == COND_VC) ? (NOTBI (CPU (h_vbit))) : (index == COND_GT) ? (ANDBI (NOTBI (CPU (h_zbit)), EQBI (CPU (h_nbit), CPU (h_vbit)))) : (index == COND_GE) ? (EQBI (CPU (h_nbit), CPU (h_vbit))) : (index == COND_LT) ? (NEBI (CPU (h_nbit), CPU (h_vbit))) : (index == COND_LE) ? (ORBI (CPU (h_zbit), NEBI (CPU (h_nbit), CPU (h_vbit)))) : (index == COND_HI) ? (ANDBI (NOTBI (CPU (h_cbit)), NOTBI (CPU (h_zbit)))) : (index == COND_LS) ? (ORBI (CPU (h_cbit), CPU (h_zbit))) : (index == COND_PNZ) ? (ANDBI (NOTBI (CPU (h_nbit)), NOTBI (CPU (h_zbit)))) : (((cgen_rtx_error (current_cpu, "invalid insn"), 0), 1))
+#define SET_H_QCONDI(index, x) \
+do { \
+((void) 0); /*nop*/\
+;} while (0)
+#define GET_H_I2COND(index) (index == 0) ? (1) : (index == 1) ? (CPU (h_zbit)) : (index == 2) ? (NOTBI (CPU (h_zbit))) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))
+#define SET_H_I2COND(index, x) \
+do { \
+((void) 0); /*nop*/\
+;} while (0)
+#define GET_H_I3COND(index) (index == COND3_CS) ? (CPU (h_cbit)) : (index == COND3_CC) ? (NOTBI (CPU (h_cbit))) : (index == COND3_GT) ? (ANDBI (NOTBI (CPU (h_zbit)), EQBI (CPU (h_nbit), CPU (h_vbit)))) : (index == COND3_GE) ? (EQBI (CPU (h_nbit), CPU (h_vbit))) : (index == COND3_LT) ? (NEBI (CPU (h_nbit), CPU (h_vbit))) : (index == COND3_LE) ? (ORBI (CPU (h_zbit), NEBI (CPU (h_nbit), CPU (h_vbit)))) : (index == COND3_HI) ? (ANDBI (NOTBI (CPU (h_cbit)), NOTBI (CPU (h_zbit)))) : (index == COND3_LS) ? (ORBI (CPU (h_cbit), CPU (h_zbit))) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))
+#define SET_H_I3COND(index, x) \
+do { \
+((void) 0); /*nop*/\
+;} while (0)
+#define GET_H_CR16(index) (index == 0 || index == 1 || index == 2 || index == 3) ? (CPU (h_cr[index])) : (CPU (h_cr[((index) + (8))]))
+#define SET_H_CR16(index, x) \
+do { \
+ switch ((index))\
+ {\
+ case 0 : case 1 : case 2 : case 3 : {\
+CPU (h_cr[(index)]) = (x);\
+}\
+ break;\
+ default : {\
+CPU (h_cr[(((index)) + (8))]) = (x);\
+}\
+ break;\
+ }\
+;} while (0)
+#define GET_H_R0(index) CPU (h_cr[((UINT) 0)])
+#define SET_H_R0(index, x) \
+do { \
+CPU (h_cr[((UINT) 0)]) = (x);\
+;} while (0)
+#define GET_H_GP(index) CPU (h_cr[((UINT) 26)])
+#define SET_H_GP(index, x) \
+do { \
+CPU (h_cr[((UINT) 26)]) = (x);\
+;} while (0)
+#define GET_H_SP(index) CPU (h_cr[((UINT) 28)])
+#define SET_H_SP(index, x) \
+do { \
+CPU (h_cr[((UINT) 28)]) = (x);\
+;} while (0)
+#define GET_H_PCL(index) CPU (h_cr[((UINT) 63)])
+#define SET_H_PCL(index, x) \
+do { \
+(cgen_rtx_error (current_cpu, "invalid insn"), 0);} while (0)
+#define GET_H_NOILINK(index) CPU (h_cr[index])
+#define SET_H_NOILINK(index, x) \
+do { \
+CPU (h_cr[(index)]) = (x);\
+;} while (0)
+#define GET_H_ILINKX(index) CPU (h_cr[index])
+#define SET_H_ILINKX(index, x) \
+do { \
+CPU (h_cr[(index)]) = (x);\
+;} while (0)
+#define GET_H_R31(index) CPU (h_cr[((UINT) 31)])
+#define SET_H_R31(index, x) \
+do { \
+CPU (h_cr[((UINT) 31)]) = (x);\
+;} while (0)
+#define GET_H_STATUS32(index) GET_H_AUXR (((UINT) 10))
+#define SET_H_STATUS32(index, x) \
+do { \
+{\
+CPU (h_lbit) = ANDSI (SRLSI ((x), 12), 1);\
+CPU (h_zbit) = ANDSI (SRLSI ((x), 11), 1);\
+CPU (h_nbit) = ANDSI (SRLSI ((x), 10), 1);\
+CPU (h_cbit) = ANDSI (SRLSI ((x), 9), 1);\
+CPU (h_vbit) = ANDSI (SRLSI ((x), 8), 1);\
+CPU (h_e1) = ANDSI (SRLSI ((x), 1), 1);\
+CPU (h_e2) = ANDSI (SRLSI ((x), 2), 1);\
+}\
+;} while (0)
+
+/* Cover fns for register access. */
+BI arc600f_h_lbit_get (SIM_CPU *);
+void arc600f_h_lbit_set (SIM_CPU *, BI);
+BI arc600f_h_zbit_get (SIM_CPU *);
+void arc600f_h_zbit_set (SIM_CPU *, BI);
+BI arc600f_h_nbit_get (SIM_CPU *);
+void arc600f_h_nbit_set (SIM_CPU *, BI);
+BI arc600f_h_cbit_get (SIM_CPU *);
+void arc600f_h_cbit_set (SIM_CPU *, BI);
+BI arc600f_h_vbit_get (SIM_CPU *);
+void arc600f_h_vbit_set (SIM_CPU *, BI);
+BI arc600f_h_ubit_get (SIM_CPU *);
+void arc600f_h_ubit_set (SIM_CPU *, BI);
+BI arc600f_h_e1_get (SIM_CPU *);
+void arc600f_h_e1_set (SIM_CPU *, BI);
+BI arc600f_h_e2_get (SIM_CPU *);
+void arc600f_h_e2_set (SIM_CPU *, BI);
+BI arc600f_h_s1bit_get (SIM_CPU *);
+void arc600f_h_s1bit_set (SIM_CPU *, BI);
+BI arc600f_h_s2bit_get (SIM_CPU *);
+void arc600f_h_s2bit_set (SIM_CPU *, BI);
+BI arc600f_h_Qcondb_get (SIM_CPU *, UINT);
+void arc600f_h_Qcondb_set (SIM_CPU *, UINT, BI);
+BI arc600f_h_Qcondj_get (SIM_CPU *, UINT);
+void arc600f_h_Qcondj_set (SIM_CPU *, UINT, BI);
+BI arc600f_h_Qcondi_get (SIM_CPU *, UINT);
+void arc600f_h_Qcondi_set (SIM_CPU *, UINT, BI);
+BI arc600f_h_i2cond_get (SIM_CPU *, UINT);
+void arc600f_h_i2cond_set (SIM_CPU *, UINT, BI);
+BI arc600f_h_i3cond_get (SIM_CPU *, UINT);
+void arc600f_h_i3cond_set (SIM_CPU *, UINT, BI);
+SI arc600f_h_cr_get (SIM_CPU *, UINT);
+void arc600f_h_cr_set (SIM_CPU *, UINT, SI);
+SI arc600f_h_cr16_get (SIM_CPU *, UINT);
+void arc600f_h_cr16_set (SIM_CPU *, UINT, SI);
+SI arc600f_h_r0_get (SIM_CPU *, UINT);
+void arc600f_h_r0_set (SIM_CPU *, UINT, SI);
+SI arc600f_h_gp_get (SIM_CPU *, UINT);
+void arc600f_h_gp_set (SIM_CPU *, UINT, SI);
+SI arc600f_h_sp_get (SIM_CPU *, UINT);
+void arc600f_h_sp_set (SIM_CPU *, UINT, SI);
+SI arc600f_h_pcl_get (SIM_CPU *, UINT);
+void arc600f_h_pcl_set (SIM_CPU *, UINT, SI);
+SI arc600f_h_noilink_get (SIM_CPU *, UINT);
+void arc600f_h_noilink_set (SIM_CPU *, UINT, SI);
+SI arc600f_h_ilinkx_get (SIM_CPU *, UINT);
+void arc600f_h_ilinkx_set (SIM_CPU *, UINT, SI);
+SI arc600f_h_r31_get (SIM_CPU *, UINT);
+void arc600f_h_r31_set (SIM_CPU *, UINT, SI);
+SI arc600f_h_auxr_get (SIM_CPU *, UINT);
+void arc600f_h_auxr_set (SIM_CPU *, UINT, SI);
+SI arc600f_h_status32_get (SIM_CPU *, UINT);
+void arc600f_h_status32_set (SIM_CPU *, UINT, SI);
+SI arc600f_h_timer_expire_get (SIM_CPU *, UINT);
+void arc600f_h_timer_expire_set (SIM_CPU *, UINT, SI);
+SI arc600f_h_prof_offset_get (SIM_CPU *, UINT);
+void arc600f_h_prof_offset_set (SIM_CPU *, UINT, SI);
+USI arc600f_h_pc_get (SIM_CPU *);
+void arc600f_h_pc_set (SIM_CPU *, USI);
+
+/* These must be hand-written. */
+extern CPUREG_FETCH_FN arc600f_fetch_register;
+extern CPUREG_STORE_FN arc600f_store_register;
+
+typedef struct {
+ int empty;
+} MODEL_ARC600_DATA;
+
+/* Instruction argument buffer. */
+
+union sem_fields {
+ struct { /* no operands */
+ int empty;
+ } fmt_empty;
+ struct { /* */
+ UINT f_trapnum;
+ } sfmt_trap_s;
+ struct { /* */
+ SI f_s9x2;
+ } sfmt_ldw_s_gprel;
+ struct { /* */
+ INT f_s9x1;
+ } sfmt_ldb_s_gprel;
+ struct { /* */
+ SI f_s9x4;
+ } sfmt_ld_s_gprel;
+ struct { /* */
+ IADDR i_label25a;
+ } sfmt_bl;
+ struct { /* */
+ IADDR i_label13a;
+ } sfmt_bl_s;
+ struct { /* */
+ IADDR i_label25;
+ } sfmt_b_l;
+ struct { /* */
+ INT f_s12x2;
+ UINT f_op_B;
+ } sfmt_lp_L_s12_;
+ struct { /* */
+ UINT f_op__b;
+ UINT f_u8;
+ } sfmt_mov_s_r_u7;
+ struct { /* */
+ UINT f_op__b;
+ UINT f_u7;
+ } sfmt_add_s_r_u7;
+ struct { /* */
+ UINT f_op__b;
+ UINT f_op_h;
+ } sfmt_add_s_mcah;
+ struct { /* */
+ SI f_u8x4;
+ UINT f_op__b;
+ } sfmt_ld_s_pcrel;
+ struct { /* */
+ IADDR i_label21a;
+ UINT f_cond_Q;
+ } sfmt_blcc;
+ struct { /* */
+ IADDR i_label21;
+ UINT f_cond_Q;
+ } sfmt_bcc_l;
+ struct { /* */
+ IADDR i_label7;
+ UINT f_cond_i3;
+ } sfmt_bcc_s;
+ struct { /* */
+ IADDR i_label10;
+ UINT f_cond_i2;
+ } sfmt_b_s;
+ struct { /* */
+ SI f_u6x2;
+ UINT f_cond_Q;
+ UINT f_op_B;
+ } sfmt_lpcc_ccu6;
+ struct { /* */
+ UINT f_op__b;
+ UINT f_op__c;
+ UINT f_u3;
+ } sfmt_add_s_cbu3;
+ struct { /* */
+ INT f_s12;
+ UINT f_F;
+ UINT f_op_B;
+ } sfmt_add_L_s12__RA_;
+ struct { /* */
+ INT f_s9;
+ UINT f_op_B;
+ UINT f_op_C;
+ } sfmt_st_abs;
+ struct { /* */
+ SI f_u5x2;
+ UINT f_op__b;
+ UINT f_op__c;
+ } sfmt_ldw_s_abu;
+ struct { /* */
+ UINT f_op__b;
+ UINT f_op__c;
+ UINT f_u5;
+ } sfmt_ldb_s_abu;
+ struct { /* */
+ SI f_u5x4;
+ UINT f_op__b;
+ UINT f_op__c;
+ } sfmt_ld_s_abu;
+ struct { /* */
+ UINT f_op__a;
+ UINT f_op__b;
+ UINT f_op__c;
+ } sfmt_ld_s_abc;
+ struct { /* */
+ INT f_s9;
+ UINT f_op_A;
+ UINT f_op_B;
+ } sfmt_ld_abs;
+ struct { /* */
+ IADDR i_label8;
+ UINT f_brscond;
+ UINT f_op__b;
+ } sfmt_brcc_s;
+ struct { /* */
+ UINT f_F;
+ UINT f_op_A;
+ UINT f_op_B;
+ UINT f_op_C;
+ } sfmt_add_L_r_r__RA__RC;
+ struct { /* */
+ UINT f_F;
+ UINT f_op_A;
+ UINT f_op_B;
+ UINT f_u6;
+ } sfmt_add_L_u6__RA_;
+ struct { /* */
+ UINT f_F;
+ UINT f_cond_Q;
+ UINT f_op_B;
+ UINT f_u6;
+ } sfmt_add_ccu6__RA_;
+ struct { /* */
+ IADDR i_label9;
+ UINT f_brcond;
+ UINT f_op_B;
+ UINT f_u6;
+ } sfmt_brcc_U6;
+ struct { /* */
+ IADDR i_label9;
+ UINT f_brcond;
+ UINT f_op_B;
+ UINT f_op_C;
+ } sfmt_brcc_RC;
+ struct { /* */
+ UINT f_F;
+ UINT f_cond_Q;
+ UINT f_op_B;
+ UINT f_op_C;
+ UINT f_op_Cj;
+ } sfmt_j_cc___RC_noilink_;
+#if WITH_SCACHE_PBB
+ /* Writeback handler. */
+ struct {
+ /* Pointer to argbuf entry for insn whose results need writing back. */
+ const struct argbuf *abuf;
+ } write;
+ /* x-before handler */
+ struct {
+ /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
+ int first_p;
+ } before;
+ /* x-after handler */
+ struct {
+ int empty;
+ } after;
+ /* This entry is used to terminate each pbb. */
+ struct {
+ /* Number of insns in pbb. */
+ int insn_count;
+ /* Next pbb to execute. */
+ SCACHE *next;
+ SCACHE *branch_target;
+ } chain;
+#endif
+};
+
+/* The ARGBUF struct. */
+struct argbuf {
+ /* These are the baseclass definitions. */
+ IADDR addr;
+ const IDESC *idesc;
+ char trace_p;
+ char profile_p;
+ /* ??? Temporary hack for skip insns. */
+ char skip_count;
+ char unused;
+ /* cpu specific data follows */
+ union sem semantic;
+ int written;
+ union sem_fields fields;
+};
+
+/* A cached insn.
+
+ ??? SCACHE used to contain more than just argbuf. We could delete the
+ type entirely and always just use ARGBUF, but for future concerns and as
+ a level of abstraction it is left in. */
+
+struct scache {
+ struct argbuf argbuf;
+};
+
+/* Macros to simplify extraction, reading and semantic code.
+ These define and assign the local vars that contain the insn's fields. */
+
+#define EXTRACT_IFMT_EMPTY_VARS \
+ unsigned int length;
+#define EXTRACT_IFMT_EMPTY_CODE \
+ length = 0; \
+
+#define EXTRACT_IFMT_B_S_VARS \
+ UINT f_opm; \
+ UINT f_cond_i2; \
+ SI f_rel10; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_B_S_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_cond_i2 = EXTRACT_MSB0_UINT (insn, 32, 5, 2); \
+ f_rel10 = ((((EXTRACT_MSB0_INT (insn, 32, 7, 9)) << (1))) + (((pc) & (-4)))); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_BCC_S_VARS \
+ UINT f_opm; \
+ UINT f_cond_i2; \
+ UINT f_cond_i3; \
+ SI f_rel7; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_BCC_S_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_cond_i2 = EXTRACT_MSB0_UINT (insn, 32, 5, 2); \
+ f_cond_i3 = EXTRACT_MSB0_UINT (insn, 32, 7, 3); \
+ f_rel7 = ((((EXTRACT_MSB0_INT (insn, 32, 10, 6)) << (1))) + (((pc) & (-4)))); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_BRCC_S_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_brscond; \
+ SI f_rel8; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_BRCC_S_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_brscond = EXTRACT_MSB0_UINT (insn, 32, 8, 1); \
+ f_rel8 = ((((EXTRACT_MSB0_INT (insn, 32, 9, 7)) << (1))) + (((pc) & (-4)))); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_BCC_L_VARS \
+ UINT f_opm; \
+ UINT f_d21l; \
+ INT f_d21h; \
+ INT f_rel21; \
+ UINT f_buf; \
+ UINT f_delay_N; \
+ UINT f_cond_Q; \
+ unsigned int length;
+#define EXTRACT_IFMT_BCC_L_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_d21l = EXTRACT_MSB0_UINT (insn, 32, 5, 10); \
+ f_d21h = EXTRACT_MSB0_INT (insn, 32, 16, 10); \
+{\
+ f_rel21 = ((((((f_d21l) << (1))) | (((f_d21h) << (11))))) + (((pc) & (-4))));\
+}\
+ f_buf = EXTRACT_MSB0_UINT (insn, 32, 15, 1); \
+ f_delay_N = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_B_L_VARS \
+ UINT f_opm; \
+ UINT f_d21l; \
+ UINT f_d25m; \
+ INT f_d25h; \
+ INT f_rel25; \
+ UINT f_buf; \
+ UINT f_delay_N; \
+ UINT f_res27; \
+ unsigned int length;
+#define EXTRACT_IFMT_B_L_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_d21l = EXTRACT_MSB0_UINT (insn, 32, 5, 10); \
+ f_d25m = EXTRACT_MSB0_UINT (insn, 32, 16, 10); \
+ f_d25h = EXTRACT_MSB0_INT (insn, 32, 28, 4); \
+{\
+ f_rel25 = ((((((((f_d21l) << (1))) | (((f_d25m) << (11))))) | (((f_d25h) << (21))))) + (((pc) & (-4))));\
+}\
+ f_buf = EXTRACT_MSB0_UINT (insn, 32, 15, 1); \
+ f_delay_N = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_res27 = EXTRACT_MSB0_UINT (insn, 32, 27, 1); \
+
+#define EXTRACT_IFMT_BRCC_RC_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_d9l; \
+ INT f_d9h; \
+ INT f_rel9; \
+ UINT f_buf; \
+ UINT f_op_C; \
+ UINT f_delay_N; \
+ UINT f_br; \
+ UINT f_brcond; \
+ unsigned int length;
+#define EXTRACT_IFMT_BRCC_RC_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_d9l = EXTRACT_MSB0_UINT (insn, 32, 8, 7); \
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1); \
+{\
+ f_rel9 = ((((((f_d9l) << (1))) | (((f_d9h) << (8))))) + (((pc) & (-4))));\
+}\
+ f_buf = EXTRACT_MSB0_UINT (insn, 32, 15, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_delay_N = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_br = EXTRACT_MSB0_UINT (insn, 32, 27, 1); \
+ f_brcond = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
+
+#define EXTRACT_IFMT_BRCC_U6_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_d9l; \
+ INT f_d9h; \
+ INT f_rel9; \
+ UINT f_buf; \
+ UINT f_u6; \
+ UINT f_delay_N; \
+ UINT f_br; \
+ UINT f_brcond; \
+ unsigned int length;
+#define EXTRACT_IFMT_BRCC_U6_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_d9l = EXTRACT_MSB0_UINT (insn, 32, 8, 7); \
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1); \
+{\
+ f_rel9 = ((((((f_d9l) << (1))) | (((f_d9h) << (8))))) + (((pc) & (-4))));\
+}\
+ f_buf = EXTRACT_MSB0_UINT (insn, 32, 15, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_delay_N = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_br = EXTRACT_MSB0_UINT (insn, 32, 27, 1); \
+ f_brcond = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
+
+#define EXTRACT_IFMT_BL_S_VARS \
+ UINT f_opm; \
+ SI f_rel13bl; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_BL_S_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_rel13bl = ((((EXTRACT_MSB0_INT (insn, 32, 5, 11)) << (2))) + (((pc) & (-4)))); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_BLCC_VARS \
+ UINT f_opm; \
+ UINT f_d21bl; \
+ INT f_d21h; \
+ INT f_rel21bl; \
+ UINT f_bluf; \
+ UINT f_buf; \
+ UINT f_delay_N; \
+ UINT f_cond_Q; \
+ unsigned int length;
+#define EXTRACT_IFMT_BLCC_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_d21bl = EXTRACT_MSB0_UINT (insn, 32, 5, 9); \
+ f_d21h = EXTRACT_MSB0_INT (insn, 32, 16, 10); \
+{\
+ f_rel21bl = ((((((f_d21bl) << (2))) | (((f_d21h) << (11))))) + (((pc) & (-4))));\
+}\
+ f_bluf = EXTRACT_MSB0_UINT (insn, 32, 14, 1); \
+ f_buf = EXTRACT_MSB0_UINT (insn, 32, 15, 1); \
+ f_delay_N = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_BL_VARS \
+ UINT f_opm; \
+ UINT f_d21bl; \
+ UINT f_d25m; \
+ INT f_d25h; \
+ INT f_rel25bl; \
+ UINT f_bluf; \
+ UINT f_buf; \
+ UINT f_delay_N; \
+ UINT f_res27; \
+ unsigned int length;
+#define EXTRACT_IFMT_BL_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_d21bl = EXTRACT_MSB0_UINT (insn, 32, 5, 9); \
+ f_d25m = EXTRACT_MSB0_UINT (insn, 32, 16, 10); \
+ f_d25h = EXTRACT_MSB0_INT (insn, 32, 28, 4); \
+{\
+ f_rel25bl = ((((((((f_d21bl) << (2))) | (((f_d25m) << (11))))) | (((f_d25h) << (21))))) + (((pc) & (-4))));\
+}\
+ f_bluf = EXTRACT_MSB0_UINT (insn, 32, 14, 1); \
+ f_buf = EXTRACT_MSB0_UINT (insn, 32, 15, 1); \
+ f_delay_N = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_res27 = EXTRACT_MSB0_UINT (insn, 32, 27, 1); \
+
+#define EXTRACT_IFMT_LD_ABS_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_u8; \
+ INT f_d9h; \
+ INT f_s9; \
+ UINT f_LDODi; \
+ UINT f_ldoaa; \
+ UINT f_ldozzx; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_LD_ABS_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8); \
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1); \
+{\
+ f_s9 = ((f_u8) | (((f_d9h) << (8))));\
+}\
+ f_LDODi = EXTRACT_MSB0_UINT (insn, 32, 20, 1); \
+ f_ldoaa = EXTRACT_MSB0_UINT (insn, 32, 21, 2); \
+ f_ldozzx = EXTRACT_MSB0_UINT (insn, 32, 23, 3); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_LD_ABC_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_ldraa; \
+ UINT f_ldr6zzx; \
+ UINT f_LDRDi; \
+ UINT f_op_C; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_LD_ABC_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_ldraa = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_ldr6zzx = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_LDRDi = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_LD_S_ABC_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_op__c; \
+ UINT f_i16_43; \
+ UINT f_op__a; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_LD_S_ABC_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3); \
+ f_i16_43 = EXTRACT_MSB0_UINT (insn, 32, 11, 2); \
+ f_op__a = EXTRACT_MSB0_UINT (insn, 32, 13, 3); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_LD_S_ABU_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_op__c; \
+ SI f_u5x4; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_LD_S_ABU_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3); \
+ f_u5x4 = ((EXTRACT_MSB0_UINT (insn, 32, 11, 5)) << (2)); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_LD_S_ABSP_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_op__c; \
+ SI f_u5x4; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_LD_S_ABSP_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3); \
+ f_u5x4 = ((EXTRACT_MSB0_UINT (insn, 32, 11, 5)) << (2)); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_LD_S_GPREL_VARS \
+ UINT f_opm; \
+ UINT f_i16_gp_type; \
+ SI f_s9x4; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_LD_S_GPREL_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_i16_gp_type = EXTRACT_MSB0_UINT (insn, 32, 5, 2); \
+ f_s9x4 = ((EXTRACT_MSB0_INT (insn, 32, 7, 9)) << (2)); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_LD_S_PCREL_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ SI f_u8x4; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_LD_S_PCREL_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_u8x4 = ((EXTRACT_MSB0_UINT (insn, 32, 8, 8)) << (2)); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_LDB_S_ABU_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_op__c; \
+ UINT f_u5; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_LDB_S_ABU_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3); \
+ f_u5 = EXTRACT_MSB0_UINT (insn, 32, 11, 5); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_LDB_S_GPREL_VARS \
+ UINT f_opm; \
+ UINT f_i16_gp_type; \
+ INT f_s9x1; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_LDB_S_GPREL_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_i16_gp_type = EXTRACT_MSB0_UINT (insn, 32, 5, 2); \
+ f_s9x1 = EXTRACT_MSB0_INT (insn, 32, 7, 9); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_LDW_S_ABU_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_op__c; \
+ SI f_u5x2; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_LDW_S_ABU_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3); \
+ f_u5x2 = ((EXTRACT_MSB0_UINT (insn, 32, 11, 5)) << (1)); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_LDW_S_GPREL_VARS \
+ UINT f_opm; \
+ UINT f_i16_gp_type; \
+ SI f_s9x2; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_LDW_S_GPREL_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_i16_gp_type = EXTRACT_MSB0_UINT (insn, 32, 5, 2); \
+ f_s9x2 = ((EXTRACT_MSB0_INT (insn, 32, 7, 9)) << (1)); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_ST_ABS_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_u8; \
+ INT f_d9h; \
+ INT f_s9; \
+ UINT f_LDODi; \
+ UINT f_op_C; \
+ UINT f_stoaa; \
+ UINT f_stozzr; \
+ unsigned int length;
+#define EXTRACT_IFMT_ST_ABS_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8); \
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1); \
+{\
+ f_s9 = ((f_u8) | (((f_d9h) << (8))));\
+}\
+ f_LDODi = EXTRACT_MSB0_UINT (insn, 32, 20, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_stoaa = EXTRACT_MSB0_UINT (insn, 32, 27, 2); \
+ f_stozzr = EXTRACT_MSB0_UINT (insn, 32, 29, 3); \
+
+#define EXTRACT_IFMT_ADD_L_S12__RA__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ INT f_s12h; \
+ INT f_s12; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADD_L_S12__RA__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6); \
+{\
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));\
+}\
+
+#define EXTRACT_IFMT_ADD_CCU6__RA__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ UINT f_go_cc_type; \
+ UINT f_cond_Q; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADD_CCU6__RA__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_go_cc_type = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_ADD_L_U6__RA__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADD_L_U6__RA__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_ADD_L_R_R__RA__RC_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_C; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADD_L_R_R__RA__RC_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_ADD_CC__RA__RC_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_C; \
+ UINT f_go_cc_type; \
+ UINT f_cond_Q; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADD_CC__RA__RC_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_go_cc_type = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_ADD_S_CBU3_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_op__c; \
+ UINT f_i16_43; \
+ UINT f_u3; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADD_S_CBU3_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3); \
+ f_i16_43 = EXTRACT_MSB0_UINT (insn, 32, 11, 2); \
+ f_u3 = EXTRACT_MSB0_UINT (insn, 32, 13, 3); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_ADD_S_MCAH_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_h_2_0; \
+ UINT f_h_5_3; \
+ UINT f_op_h; \
+ UINT f_i16_43; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADD_S_MCAH_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_h_2_0 = EXTRACT_MSB0_UINT (insn, 32, 8, 3); \
+ f_h_5_3 = EXTRACT_MSB0_UINT (insn, 32, 13, 3); \
+{\
+ f_op_h = ((f_h_2_0) | (((f_h_5_3) << (3))));\
+}\
+ f_i16_43 = EXTRACT_MSB0_UINT (insn, 32, 11, 2); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_ADD_S_ASSPSP_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_op__c; \
+ SI f_u5x4; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADD_S_ASSPSP_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3); \
+ f_u5x4 = ((EXTRACT_MSB0_UINT (insn, 32, 11, 5)) << (2)); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_ADD_S_GP_VARS \
+ UINT f_opm; \
+ UINT f_i16_gp_type; \
+ SI f_s9x4; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADD_S_GP_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_i16_gp_type = EXTRACT_MSB0_UINT (insn, 32, 5, 2); \
+ f_s9x4 = ((EXTRACT_MSB0_INT (insn, 32, 7, 9)) << (2)); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_ADD_S_R_U7_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_i16addcmpu7_type; \
+ UINT f_u7; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADD_S_R_U7_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_i16addcmpu7_type = EXTRACT_MSB0_UINT (insn, 32, 8, 1); \
+ f_u7 = EXTRACT_MSB0_UINT (insn, 32, 9, 7); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_I16_GO_SUB_S_GO_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_op__c; \
+ UINT f_i16_go; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_I16_GO_SUB_S_GO_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3); \
+ f_i16_go = EXTRACT_MSB0_UINT (insn, 32, 11, 5); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_SUB_S_GO_SUB_NE_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_op__c; \
+ UINT f_i16_go; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_SUB_S_GO_SUB_NE_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3); \
+ f_i16_go = EXTRACT_MSB0_UINT (insn, 32, 11, 5); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_SUB_S_SSB_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_op__c; \
+ UINT f_u5; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_SUB_S_SSB_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3); \
+ f_u5 = EXTRACT_MSB0_UINT (insn, 32, 11, 5); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_MOV_L_U6__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOV_L_U6__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_MOV_L_R_R__RC_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_C; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOV_L_R_R__RC_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_MOV_S_R_U7_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_u8; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOV_S_R_U7_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_TST_L_S12__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ INT f_s12h; \
+ INT f_s12; \
+ unsigned int length;
+#define EXTRACT_IFMT_TST_L_S12__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6); \
+{\
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));\
+}\
+
+#define EXTRACT_IFMT_TST_CCU6__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ UINT f_go_cc_type; \
+ UINT f_cond_Q; \
+ unsigned int length;
+#define EXTRACT_IFMT_TST_CCU6__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_go_cc_type = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_TST_L_U6__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_TST_L_U6__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_TST_L_R_R__RC_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_C; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_TST_L_R_R__RC_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_TST_CC__RC_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_C; \
+ UINT f_go_cc_type; \
+ UINT f_cond_Q; \
+ unsigned int length;
+#define EXTRACT_IFMT_TST_CC__RC_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_go_cc_type = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_J_L_R_R___RC_NOILINK__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_Cj; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_J_L_R_R___RC_NOILINK__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_Cj = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_J_CC___RC_NOILINK__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_Cj; \
+ UINT f_go_cc_type; \
+ UINT f_cond_Q; \
+ unsigned int length;
+#define EXTRACT_IFMT_J_CC___RC_NOILINK__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_Cj = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_go_cc_type = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_J_L_R_R___RC_ILINK__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_Cj; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_J_L_R_R___RC_ILINK__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_Cj = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_J_CC___RC_ILINK__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_Cj; \
+ UINT f_go_cc_type; \
+ UINT f_cond_Q; \
+ unsigned int length;
+#define EXTRACT_IFMT_J_CC___RC_ILINK__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_Cj = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_go_cc_type = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_J_L_S12__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ INT f_s12h; \
+ INT f_s12; \
+ unsigned int length;
+#define EXTRACT_IFMT_J_L_S12__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6); \
+{\
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));\
+}\
+
+#define EXTRACT_IFMT_J_CCU6__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ UINT f_go_cc_type; \
+ UINT f_cond_Q; \
+ unsigned int length;
+#define EXTRACT_IFMT_J_CCU6__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_go_cc_type = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_J_L_U6__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_J_L_U6__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_J_S__S_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_op__c; \
+ UINT f_i16_go; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_J_S__S_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3); \
+ f_i16_go = EXTRACT_MSB0_UINT (insn, 32, 11, 5); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_J_L_R_R_D___RC__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_C; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_J_L_R_R_D___RC__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_J_CC_D___RC__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_C; \
+ UINT f_go_cc_type; \
+ UINT f_cond_Q; \
+ unsigned int length;
+#define EXTRACT_IFMT_J_CC_D___RC__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_go_cc_type = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_LP_L_S12__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ INT f_s12h; \
+ INT f_s12x2; \
+ unsigned int length;
+#define EXTRACT_IFMT_LP_L_S12__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6); \
+{\
+ f_s12x2 = ((((f_u6) << (1))) | (((f_s12h) << (7))));\
+}\
+
+#define EXTRACT_IFMT_LPCC_CCU6_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ SI f_u6x2; \
+ UINT f_go_cc_type; \
+ UINT f_cond_Q; \
+ unsigned int length;
+#define EXTRACT_IFMT_LPCC_CCU6_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6x2 = ((EXTRACT_MSB0_UINT (insn, 32, 20, 6)) << (1)); \
+ f_go_cc_type = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_LR_L_R_R___RC__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_C; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_LR_L_R_R___RC__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_LR_L_S12__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ INT f_s12h; \
+ INT f_s12; \
+ unsigned int length;
+#define EXTRACT_IFMT_LR_L_S12__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6); \
+{\
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));\
+}\
+
+#define EXTRACT_IFMT_LR_L_U6__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_LR_L_U6__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_ASL_L_R_R__RC_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_C; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_ASL_L_R_R__RC_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_ASL_L_U6__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_ASL_L_U6__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_SWI_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_B_5_3; \
+ UINT f_op_C; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_SWI_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_TRAP_S_VARS \
+ UINT f_opm; \
+ UINT f_trapnum; \
+ UINT f_i16_go; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_TRAP_S_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_trapnum = EXTRACT_MSB0_UINT (insn, 32, 5, 6); \
+ f_i16_go = EXTRACT_MSB0_UINT (insn, 32, 11, 5); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_BRK_S_VARS \
+ UINT f_opm; \
+ UINT f_trapnum; \
+ UINT f_i16_go; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_BRK_S_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_trapnum = EXTRACT_MSB0_UINT (insn, 32, 5, 6); \
+ f_i16_go = EXTRACT_MSB0_UINT (insn, 32, 11, 5); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_DIVAW_CCU6__RA__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ UINT f_go_cc_type; \
+ UINT f_cond_Q; \
+ unsigned int length;
+#define EXTRACT_IFMT_DIVAW_CCU6__RA__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_go_cc_type = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_DIVAW_L_U6__RA__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_DIVAW_L_U6__RA__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_DIVAW_L_R_R__RA__RC_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_C; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_DIVAW_L_R_R__RA__RC_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_DIVAW_CC__RA__RC_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_C; \
+ UINT f_go_cc_type; \
+ UINT f_cond_Q; \
+ unsigned int length;
+#define EXTRACT_IFMT_DIVAW_CC__RA__RC_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_go_cc_type = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_POP_S_B_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_op__c; \
+ UINT f_u5; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_POP_S_B_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3); \
+ f_u5 = EXTRACT_MSB0_UINT (insn, 32, 11, 5); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_POP_S_BLINK_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_op__c; \
+ UINT f_u5; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_POP_S_BLINK_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3); \
+ f_u5 = EXTRACT_MSB0_UINT (insn, 32, 11, 5); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_CURRENT_LOOP_END_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_C; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_CURRENT_LOOP_END_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+/* Collection of various things for the trace handler to use. */
+
+typedef struct trace_record {
+ IADDR pc;
+ /* FIXME:wip */
+} TRACE_RECORD;
+
+#endif /* CPU_ARC600F_H */
diff --git a/sim/arc/cpu7.c b/sim/arc/cpu7.c
new file mode 100644
index 0000000..d1f1a88
--- /dev/null
+++ b/sim/arc/cpu7.c
@@ -0,0 +1,501 @@
+/* Misc. support for CPU family arc700f.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2007 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#define WANT_CPU arc700f
+#define WANT_CPU_ARC700F
+
+#include "sim-main.h"
+#include "cgen-ops.h"
+
+/* Get the value of h-lbit. */
+
+BI
+arc700f_h_lbit_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_lbit);
+}
+
+/* Set a value for h-lbit. */
+
+void
+arc700f_h_lbit_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_lbit) = newval;
+}
+
+/* Get the value of h-zbit. */
+
+BI
+arc700f_h_zbit_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_zbit);
+}
+
+/* Set a value for h-zbit. */
+
+void
+arc700f_h_zbit_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_zbit) = newval;
+}
+
+/* Get the value of h-nbit. */
+
+BI
+arc700f_h_nbit_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_nbit);
+}
+
+/* Set a value for h-nbit. */
+
+void
+arc700f_h_nbit_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_nbit) = newval;
+}
+
+/* Get the value of h-cbit. */
+
+BI
+arc700f_h_cbit_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_cbit);
+}
+
+/* Set a value for h-cbit. */
+
+void
+arc700f_h_cbit_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_cbit) = newval;
+}
+
+/* Get the value of h-vbit. */
+
+BI
+arc700f_h_vbit_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_vbit);
+}
+
+/* Set a value for h-vbit. */
+
+void
+arc700f_h_vbit_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_vbit) = newval;
+}
+
+/* Get the value of h-ubit. */
+
+BI
+arc700f_h_ubit_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_ubit);
+}
+
+/* Set a value for h-ubit. */
+
+void
+arc700f_h_ubit_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_ubit) = newval;
+}
+
+/* Get the value of h-e1. */
+
+BI
+arc700f_h_e1_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_e1);
+}
+
+/* Set a value for h-e1. */
+
+void
+arc700f_h_e1_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_e1) = newval;
+}
+
+/* Get the value of h-e2. */
+
+BI
+arc700f_h_e2_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_e2);
+}
+
+/* Set a value for h-e2. */
+
+void
+arc700f_h_e2_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_e2) = newval;
+}
+
+/* Get the value of h-s1bit. */
+
+BI
+arc700f_h_s1bit_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_s1bit);
+}
+
+/* Set a value for h-s1bit. */
+
+void
+arc700f_h_s1bit_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_s1bit) = newval;
+}
+
+/* Get the value of h-s2bit. */
+
+BI
+arc700f_h_s2bit_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_s2bit);
+}
+
+/* Set a value for h-s2bit. */
+
+void
+arc700f_h_s2bit_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_s2bit) = newval;
+}
+
+/* Get the value of h-Qcondb. */
+
+BI
+arc700f_h_Qcondb_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_QCONDB (regno);
+}
+
+/* Set a value for h-Qcondb. */
+
+void
+arc700f_h_Qcondb_set (SIM_CPU *current_cpu, UINT regno, BI newval)
+{
+ SET_H_QCONDB (regno, newval);
+}
+
+/* Get the value of h-Qcondj. */
+
+BI
+arc700f_h_Qcondj_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_QCONDJ (regno);
+}
+
+/* Set a value for h-Qcondj. */
+
+void
+arc700f_h_Qcondj_set (SIM_CPU *current_cpu, UINT regno, BI newval)
+{
+ SET_H_QCONDJ (regno, newval);
+}
+
+/* Get the value of h-Qcondi. */
+
+BI
+arc700f_h_Qcondi_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_QCONDI (regno);
+}
+
+/* Set a value for h-Qcondi. */
+
+void
+arc700f_h_Qcondi_set (SIM_CPU *current_cpu, UINT regno, BI newval)
+{
+ SET_H_QCONDI (regno, newval);
+}
+
+/* Get the value of h-i2cond. */
+
+BI
+arc700f_h_i2cond_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_I2COND (regno);
+}
+
+/* Set a value for h-i2cond. */
+
+void
+arc700f_h_i2cond_set (SIM_CPU *current_cpu, UINT regno, BI newval)
+{
+ SET_H_I2COND (regno, newval);
+}
+
+/* Get the value of h-i3cond. */
+
+BI
+arc700f_h_i3cond_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_I3COND (regno);
+}
+
+/* Set a value for h-i3cond. */
+
+void
+arc700f_h_i3cond_set (SIM_CPU *current_cpu, UINT regno, BI newval)
+{
+ SET_H_I3COND (regno, newval);
+}
+
+/* Get the value of h-cr. */
+
+SI
+arc700f_h_cr_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_CR (regno);
+}
+
+/* Set a value for h-cr. */
+
+void
+arc700f_h_cr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_CR (regno, newval);
+}
+
+/* Get the value of h-cr16. */
+
+SI
+arc700f_h_cr16_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_CR16 (regno);
+}
+
+/* Set a value for h-cr16. */
+
+void
+arc700f_h_cr16_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_CR16 (regno, newval);
+}
+
+/* Get the value of h-r0. */
+
+SI
+arc700f_h_r0_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_R0 (regno);
+}
+
+/* Set a value for h-r0. */
+
+void
+arc700f_h_r0_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_R0 (regno, newval);
+}
+
+/* Get the value of h-gp. */
+
+SI
+arc700f_h_gp_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_GP (regno);
+}
+
+/* Set a value for h-gp. */
+
+void
+arc700f_h_gp_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_GP (regno, newval);
+}
+
+/* Get the value of h-sp. */
+
+SI
+arc700f_h_sp_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_SP (regno);
+}
+
+/* Set a value for h-sp. */
+
+void
+arc700f_h_sp_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_SP (regno, newval);
+}
+
+/* Get the value of h-pcl. */
+
+SI
+arc700f_h_pcl_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_PCL (regno);
+}
+
+/* Set a value for h-pcl. */
+
+void
+arc700f_h_pcl_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_PCL (regno, newval);
+}
+
+/* Get the value of h-noilink. */
+
+SI
+arc700f_h_noilink_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_NOILINK (regno);
+}
+
+/* Set a value for h-noilink. */
+
+void
+arc700f_h_noilink_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_NOILINK (regno, newval);
+}
+
+/* Get the value of h-ilinkx. */
+
+SI
+arc700f_h_ilinkx_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_ILINKX (regno);
+}
+
+/* Set a value for h-ilinkx. */
+
+void
+arc700f_h_ilinkx_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_ILINKX (regno, newval);
+}
+
+/* Get the value of h-r31. */
+
+SI
+arc700f_h_r31_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_R31 (regno);
+}
+
+/* Set a value for h-r31. */
+
+void
+arc700f_h_r31_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_R31 (regno, newval);
+}
+
+/* Get the value of h-auxr. */
+
+SI
+arc700f_h_auxr_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_AUXR (regno);
+}
+
+/* Set a value for h-auxr. */
+
+void
+arc700f_h_auxr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_AUXR (regno, newval);
+}
+
+/* Get the value of h-status32. */
+
+SI
+arc700f_h_status32_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_STATUS32 (regno);
+}
+
+/* Set a value for h-status32. */
+
+void
+arc700f_h_status32_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_STATUS32 (regno, newval);
+}
+
+/* Get the value of h-timer-expire. */
+
+SI
+arc700f_h_timer_expire_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return CPU (h_timer_expire[regno]);
+}
+
+/* Set a value for h-timer-expire. */
+
+void
+arc700f_h_timer_expire_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ CPU (h_timer_expire[regno]) = newval;
+}
+
+/* Get the value of h-prof-offset. */
+
+SI
+arc700f_h_prof_offset_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return CPU (h_prof_offset[regno]);
+}
+
+/* Set a value for h-prof-offset. */
+
+void
+arc700f_h_prof_offset_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ CPU (h_prof_offset[regno]) = newval;
+}
+
+/* Get the value of h-pc. */
+
+USI
+arc700f_h_pc_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_pc);
+}
+
+/* Set a value for h-pc. */
+
+void
+arc700f_h_pc_set (SIM_CPU *current_cpu, USI newval)
+{
+ CPU (h_pc) = newval;
+}
+
+/* Record trace results for INSN. */
+
+void
+arc700f_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,
+ int *indices, TRACE_RECORD *tr)
+{
+}
diff --git a/sim/arc/cpu7.h b/sim/arc/cpu7.h
new file mode 100644
index 0000000..dd70310
--- /dev/null
+++ b/sim/arc/cpu7.h
@@ -0,0 +1,2109 @@
+/* CPU family header for arc700f.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2007 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#ifndef CPU_ARC700F_H
+#define CPU_ARC700F_H
+
+/* Maximum number of instructions that are fetched at a time.
+ This is for LIW type instructions sets (e.g. m32r). */
+#define MAX_LIW_INSNS 1
+
+/* Maximum number of instructions that can be executed in parallel. */
+#define MAX_PARALLEL_INSNS 1
+
+/* CPU state information. */
+typedef struct {
+ /* Hardware elements. */
+ struct {
+ /* loop inhibit bit */
+ BI h_lbit;
+#define GET_H_LBIT() CPU (h_lbit)
+#define SET_H_LBIT(x) (CPU (h_lbit) = (x))
+ /* zerobit */
+ BI h_zbit;
+#define GET_H_ZBIT() CPU (h_zbit)
+#define SET_H_ZBIT(x) (CPU (h_zbit) = (x))
+ /* negative bit */
+ BI h_nbit;
+#define GET_H_NBIT() CPU (h_nbit)
+#define SET_H_NBIT(x) (CPU (h_nbit) = (x))
+ /* carry bit */
+ BI h_cbit;
+#define GET_H_CBIT() CPU (h_cbit)
+#define SET_H_CBIT(x) (CPU (h_cbit) = (x))
+ /* overflow bit */
+ BI h_vbit;
+#define GET_H_VBIT() CPU (h_vbit)
+#define SET_H_VBIT(x) (CPU (h_vbit) = (x))
+ /* user mode bit */
+ BI h_ubit;
+#define GET_H_UBIT() CPU (h_ubit)
+#define SET_H_UBIT(x) (CPU (h_ubit) = (x))
+ /* interupt 1 enable bit */
+ BI h_e1;
+#define GET_H_E1() CPU (h_e1)
+#define SET_H_E1(x) (CPU (h_e1) = (x))
+ /* interupt 2 enable bit */
+ BI h_e2;
+#define GET_H_E2() CPU (h_e2)
+#define SET_H_E2(x) (CPU (h_e2) = (x))
+ /* channel 1 saturate */
+ BI h_s1bit;
+#define GET_H_S1BIT() CPU (h_s1bit)
+#define SET_H_S1BIT(x) (CPU (h_s1bit) = (x))
+ /* channel 2 saturate */
+ BI h_s2bit;
+#define GET_H_S2BIT() CPU (h_s2bit)
+#define SET_H_S2BIT(x) (CPU (h_s2bit) = (x))
+ /* core registers */
+ SI h_cr[64];
+#define GET_H_CR(index) (index == 61) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (CPU (h_cr[index]))
+#define SET_H_CR(index, x) \
+do { \
+ switch ((index))\
+ {\
+ case 62 : {\
+((void) 0); /*nop*/\
+}\
+ break;\
+ case 61 : case 63 : {\
+cgen_rtx_error (current_cpu, "invalid insn");\
+}\
+ break;\
+ default : {\
+CPU (h_cr[(index)]) = (x);\
+}\
+ break;\
+ }\
+;} while (0)
+ /* auxiliary registers */
+ SI h_auxr[64];
+#define GET_H_AUXR(index) (index == 0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (index == 6) ? (ADDSI (CPU (h_pc), 4)) : (index == 10) ? (ORSI (SLLSI (ZEXTBISI (CPU (h_lbit)), 12), ORSI (SLLSI (ZEXTBISI (CPU (h_zbit)), 11), ORSI (SLLSI (ZEXTBISI (CPU (h_nbit)), 10), ORSI (SLLSI (ZEXTBISI (CPU (h_cbit)), 9), ORSI (SLLSI (ZEXTBISI (CPU (h_vbit)), 8), ORSI (SLLSI (ZEXTBISI (CPU (h_e1)), 1), SLLSI (ZEXTBISI (CPU (h_e2)), 2)))))))) : (index == 33) ? (ADDSI (CPU_INSN_COUNT (current_cpu), SUBSI (CPU (h_auxr[((UINT) 35)]), CPU (h_timer_expire[((UINT) 0)])))) : (index == 65) ? (ORSI (SLLSI (ZEXTBISI (CPU (h_s1bit)), 9), SLLSI (ZEXTBISI (CPU (h_s2bit)), 4))) : (CPU (h_auxr[index]))
+#define SET_H_AUXR(index, x) \
+do { \
+ switch ((index))\
+ {\
+ case 0 : {\
+cgen_rtx_error (current_cpu, "invalid insn");\
+}\
+ break;\
+ case 3 : {\
+{\
+CPU (h_auxr[((UINT) 3)]) = (x);\
+scache_flush_cpu (current_cpu);\
+}\
+}\
+ break;\
+ case 4 : case 5 : case 6 : case 10 : case 1027 : case 1040 : case 1041 : case 1046 : {\
+((void) 0); /*nop*/\
+}\
+ break;\
+ case 33 : case 34 : case 35 : {\
+{\
+CPU (h_auxr[(index)]) = (x);\
+CPU (h_timer_expire[((UINT) 0)]) = ADDSI (CPU_INSN_COUNT (current_cpu), SUBSI (CPU (h_auxr[((UINT) 35)]), CPU (h_auxr[((UINT) 33)])));\
+}\
+}\
+ break;\
+ case 65 : {\
+if (ANDSI ((x), 2)) {\
+CPU (h_s1bit) = 0;\
+CPU (h_s2bit) = 0;\
+}\
+}\
+ break;\
+ default : {\
+CPU (h_auxr[(index)]) = (x);\
+}\
+ break;\
+ }\
+;} while (0)
+ /* used internally in simulator to speed up timer expiration check */
+ SI h_timer_expire[1];
+#define GET_H_TIMER_EXPIRE(a1) CPU (h_timer_expire)[a1]
+#define SET_H_TIMER_EXPIRE(a1, x) (CPU (h_timer_expire)[a1] = (x))
+ /* offset to profile counters */
+ SI h_prof_offset[1];
+#define GET_H_PROF_OFFSET(a1) CPU (h_prof_offset)[a1]
+#define SET_H_PROF_OFFSET(a1, x) (CPU (h_prof_offset)[a1] = (x))
+ /* program counter */
+ USI h_pc;
+#define GET_H_PC() CPU (h_pc)
+#define SET_H_PC(x) (CPU (h_pc) = (x))
+ } hardware;
+#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
+} ARC700F_CPU_DATA;
+
+/* Virtual regs. */
+
+#define GET_H_QCONDB(index) (index == COND_AL) ? (1) : (index == COND_EQ) ? (CPU (h_zbit)) : (index == COND_NE) ? (NOTBI (CPU (h_zbit))) : (index == COND_PL) ? (NOTBI (CPU (h_nbit))) : (index == COND_MI) ? (CPU (h_nbit)) : (index == COND_CS) ? (CPU (h_cbit)) : (index == COND_CC) ? (NOTBI (CPU (h_cbit))) : (index == COND_VS) ? (CPU (h_vbit)) : (index == COND_VC) ? (NOTBI (CPU (h_vbit))) : (index == COND_GT) ? (ANDBI (NOTBI (CPU (h_zbit)), EQBI (CPU (h_nbit), CPU (h_vbit)))) : (index == COND_GE) ? (EQBI (CPU (h_nbit), CPU (h_vbit))) : (index == COND_LT) ? (NEBI (CPU (h_nbit), CPU (h_vbit))) : (index == COND_LE) ? (ORBI (CPU (h_zbit), NEBI (CPU (h_nbit), CPU (h_vbit)))) : (index == COND_HI) ? (ANDBI (NOTBI (CPU (h_cbit)), NOTBI (CPU (h_zbit)))) : (index == COND_LS) ? (ORBI (CPU (h_cbit), CPU (h_zbit))) : (index == COND_PNZ) ? (ANDBI (NOTBI (CPU (h_nbit)), NOTBI (CPU (h_zbit)))) : (((cgen_rtx_error (current_cpu, "invalid insn"), 0), 1))
+#define SET_H_QCONDB(index, x) \
+do { \
+((void) 0); /*nop*/\
+;} while (0)
+#define GET_H_QCONDJ(index) (index == COND_AL) ? (1) : (index == COND_EQ) ? (CPU (h_zbit)) : (index == COND_NE) ? (NOTBI (CPU (h_zbit))) : (index == COND_PL) ? (NOTBI (CPU (h_nbit))) : (index == COND_MI) ? (CPU (h_nbit)) : (index == COND_CS) ? (CPU (h_cbit)) : (index == COND_CC) ? (NOTBI (CPU (h_cbit))) : (index == COND_VS) ? (CPU (h_vbit)) : (index == COND_VC) ? (NOTBI (CPU (h_vbit))) : (index == COND_GT) ? (ANDBI (NOTBI (CPU (h_zbit)), EQBI (CPU (h_nbit), CPU (h_vbit)))) : (index == COND_GE) ? (EQBI (CPU (h_nbit), CPU (h_vbit))) : (index == COND_LT) ? (NEBI (CPU (h_nbit), CPU (h_vbit))) : (index == COND_LE) ? (ORBI (CPU (h_zbit), NEBI (CPU (h_nbit), CPU (h_vbit)))) : (index == COND_HI) ? (ANDBI (NOTBI (CPU (h_cbit)), NOTBI (CPU (h_zbit)))) : (index == COND_LS) ? (ORBI (CPU (h_cbit), CPU (h_zbit))) : (index == COND_PNZ) ? (ANDBI (NOTBI (CPU (h_nbit)), NOTBI (CPU (h_zbit)))) : (((cgen_rtx_error (current_cpu, "invalid insn"), 0), 1))
+#define SET_H_QCONDJ(index, x) \
+do { \
+((void) 0); /*nop*/\
+;} while (0)
+#define GET_H_QCONDI(index) (index == COND_AL) ? (1) : (index == COND_EQ) ? (CPU (h_zbit)) : (index == COND_NE) ? (NOTBI (CPU (h_zbit))) : (index == COND_PL) ? (NOTBI (CPU (h_nbit))) : (index == COND_MI) ? (CPU (h_nbit)) : (index == COND_CS) ? (CPU (h_cbit)) : (index == COND_CC) ? (NOTBI (CPU (h_cbit))) : (index == COND_VS) ? (CPU (h_vbit)) : (index == COND_VC) ? (NOTBI (CPU (h_vbit))) : (index == COND_GT) ? (ANDBI (NOTBI (CPU (h_zbit)), EQBI (CPU (h_nbit), CPU (h_vbit)))) : (index == COND_GE) ? (EQBI (CPU (h_nbit), CPU (h_vbit))) : (index == COND_LT) ? (NEBI (CPU (h_nbit), CPU (h_vbit))) : (index == COND_LE) ? (ORBI (CPU (h_zbit), NEBI (CPU (h_nbit), CPU (h_vbit)))) : (index == COND_HI) ? (ANDBI (NOTBI (CPU (h_cbit)), NOTBI (CPU (h_zbit)))) : (index == COND_LS) ? (ORBI (CPU (h_cbit), CPU (h_zbit))) : (index == COND_PNZ) ? (ANDBI (NOTBI (CPU (h_nbit)), NOTBI (CPU (h_zbit)))) : (((cgen_rtx_error (current_cpu, "invalid insn"), 0), 1))
+#define SET_H_QCONDI(index, x) \
+do { \
+((void) 0); /*nop*/\
+;} while (0)
+#define GET_H_I2COND(index) (index == 0) ? (1) : (index == 1) ? (CPU (h_zbit)) : (index == 2) ? (NOTBI (CPU (h_zbit))) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))
+#define SET_H_I2COND(index, x) \
+do { \
+((void) 0); /*nop*/\
+;} while (0)
+#define GET_H_I3COND(index) (index == COND3_CS) ? (CPU (h_cbit)) : (index == COND3_CC) ? (NOTBI (CPU (h_cbit))) : (index == COND3_GT) ? (ANDBI (NOTBI (CPU (h_zbit)), EQBI (CPU (h_nbit), CPU (h_vbit)))) : (index == COND3_GE) ? (EQBI (CPU (h_nbit), CPU (h_vbit))) : (index == COND3_LT) ? (NEBI (CPU (h_nbit), CPU (h_vbit))) : (index == COND3_LE) ? (ORBI (CPU (h_zbit), NEBI (CPU (h_nbit), CPU (h_vbit)))) : (index == COND3_HI) ? (ANDBI (NOTBI (CPU (h_cbit)), NOTBI (CPU (h_zbit)))) : (index == COND3_LS) ? (ORBI (CPU (h_cbit), CPU (h_zbit))) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))
+#define SET_H_I3COND(index, x) \
+do { \
+((void) 0); /*nop*/\
+;} while (0)
+#define GET_H_CR16(index) (index == 0 || index == 1 || index == 2 || index == 3) ? (CPU (h_cr[index])) : (CPU (h_cr[((index) + (8))]))
+#define SET_H_CR16(index, x) \
+do { \
+ switch ((index))\
+ {\
+ case 0 : case 1 : case 2 : case 3 : {\
+CPU (h_cr[(index)]) = (x);\
+}\
+ break;\
+ default : {\
+CPU (h_cr[(((index)) + (8))]) = (x);\
+}\
+ break;\
+ }\
+;} while (0)
+#define GET_H_R0(index) CPU (h_cr[((UINT) 0)])
+#define SET_H_R0(index, x) \
+do { \
+CPU (h_cr[((UINT) 0)]) = (x);\
+;} while (0)
+#define GET_H_GP(index) CPU (h_cr[((UINT) 26)])
+#define SET_H_GP(index, x) \
+do { \
+CPU (h_cr[((UINT) 26)]) = (x);\
+;} while (0)
+#define GET_H_SP(index) CPU (h_cr[((UINT) 28)])
+#define SET_H_SP(index, x) \
+do { \
+CPU (h_cr[((UINT) 28)]) = (x);\
+;} while (0)
+#define GET_H_PCL(index) CPU (h_cr[((UINT) 63)])
+#define SET_H_PCL(index, x) \
+do { \
+(cgen_rtx_error (current_cpu, "invalid insn"), 0);} while (0)
+#define GET_H_NOILINK(index) CPU (h_cr[index])
+#define SET_H_NOILINK(index, x) \
+do { \
+CPU (h_cr[(index)]) = (x);\
+;} while (0)
+#define GET_H_ILINKX(index) CPU (h_cr[index])
+#define SET_H_ILINKX(index, x) \
+do { \
+CPU (h_cr[(index)]) = (x);\
+;} while (0)
+#define GET_H_R31(index) CPU (h_cr[((UINT) 31)])
+#define SET_H_R31(index, x) \
+do { \
+CPU (h_cr[((UINT) 31)]) = (x);\
+;} while (0)
+#define GET_H_STATUS32(index) GET_H_AUXR (((UINT) 10))
+#define SET_H_STATUS32(index, x) \
+do { \
+{\
+CPU (h_lbit) = ANDSI (SRLSI ((x), 12), 1);\
+CPU (h_zbit) = ANDSI (SRLSI ((x), 11), 1);\
+CPU (h_nbit) = ANDSI (SRLSI ((x), 10), 1);\
+CPU (h_cbit) = ANDSI (SRLSI ((x), 9), 1);\
+CPU (h_vbit) = ANDSI (SRLSI ((x), 8), 1);\
+CPU (h_e1) = ANDSI (SRLSI ((x), 1), 1);\
+CPU (h_e2) = ANDSI (SRLSI ((x), 2), 1);\
+}\
+;} while (0)
+
+/* Cover fns for register access. */
+BI arc700f_h_lbit_get (SIM_CPU *);
+void arc700f_h_lbit_set (SIM_CPU *, BI);
+BI arc700f_h_zbit_get (SIM_CPU *);
+void arc700f_h_zbit_set (SIM_CPU *, BI);
+BI arc700f_h_nbit_get (SIM_CPU *);
+void arc700f_h_nbit_set (SIM_CPU *, BI);
+BI arc700f_h_cbit_get (SIM_CPU *);
+void arc700f_h_cbit_set (SIM_CPU *, BI);
+BI arc700f_h_vbit_get (SIM_CPU *);
+void arc700f_h_vbit_set (SIM_CPU *, BI);
+BI arc700f_h_ubit_get (SIM_CPU *);
+void arc700f_h_ubit_set (SIM_CPU *, BI);
+BI arc700f_h_e1_get (SIM_CPU *);
+void arc700f_h_e1_set (SIM_CPU *, BI);
+BI arc700f_h_e2_get (SIM_CPU *);
+void arc700f_h_e2_set (SIM_CPU *, BI);
+BI arc700f_h_s1bit_get (SIM_CPU *);
+void arc700f_h_s1bit_set (SIM_CPU *, BI);
+BI arc700f_h_s2bit_get (SIM_CPU *);
+void arc700f_h_s2bit_set (SIM_CPU *, BI);
+BI arc700f_h_Qcondb_get (SIM_CPU *, UINT);
+void arc700f_h_Qcondb_set (SIM_CPU *, UINT, BI);
+BI arc700f_h_Qcondj_get (SIM_CPU *, UINT);
+void arc700f_h_Qcondj_set (SIM_CPU *, UINT, BI);
+BI arc700f_h_Qcondi_get (SIM_CPU *, UINT);
+void arc700f_h_Qcondi_set (SIM_CPU *, UINT, BI);
+BI arc700f_h_i2cond_get (SIM_CPU *, UINT);
+void arc700f_h_i2cond_set (SIM_CPU *, UINT, BI);
+BI arc700f_h_i3cond_get (SIM_CPU *, UINT);
+void arc700f_h_i3cond_set (SIM_CPU *, UINT, BI);
+SI arc700f_h_cr_get (SIM_CPU *, UINT);
+void arc700f_h_cr_set (SIM_CPU *, UINT, SI);
+SI arc700f_h_cr16_get (SIM_CPU *, UINT);
+void arc700f_h_cr16_set (SIM_CPU *, UINT, SI);
+SI arc700f_h_r0_get (SIM_CPU *, UINT);
+void arc700f_h_r0_set (SIM_CPU *, UINT, SI);
+SI arc700f_h_gp_get (SIM_CPU *, UINT);
+void arc700f_h_gp_set (SIM_CPU *, UINT, SI);
+SI arc700f_h_sp_get (SIM_CPU *, UINT);
+void arc700f_h_sp_set (SIM_CPU *, UINT, SI);
+SI arc700f_h_pcl_get (SIM_CPU *, UINT);
+void arc700f_h_pcl_set (SIM_CPU *, UINT, SI);
+SI arc700f_h_noilink_get (SIM_CPU *, UINT);
+void arc700f_h_noilink_set (SIM_CPU *, UINT, SI);
+SI arc700f_h_ilinkx_get (SIM_CPU *, UINT);
+void arc700f_h_ilinkx_set (SIM_CPU *, UINT, SI);
+SI arc700f_h_r31_get (SIM_CPU *, UINT);
+void arc700f_h_r31_set (SIM_CPU *, UINT, SI);
+SI arc700f_h_auxr_get (SIM_CPU *, UINT);
+void arc700f_h_auxr_set (SIM_CPU *, UINT, SI);
+SI arc700f_h_status32_get (SIM_CPU *, UINT);
+void arc700f_h_status32_set (SIM_CPU *, UINT, SI);
+SI arc700f_h_timer_expire_get (SIM_CPU *, UINT);
+void arc700f_h_timer_expire_set (SIM_CPU *, UINT, SI);
+SI arc700f_h_prof_offset_get (SIM_CPU *, UINT);
+void arc700f_h_prof_offset_set (SIM_CPU *, UINT, SI);
+USI arc700f_h_pc_get (SIM_CPU *);
+void arc700f_h_pc_set (SIM_CPU *, USI);
+
+/* These must be hand-written. */
+extern CPUREG_FETCH_FN arc700f_fetch_register;
+extern CPUREG_STORE_FN arc700f_store_register;
+
+typedef struct {
+ int empty;
+} MODEL_ARC700_DATA;
+
+/* Instruction argument buffer. */
+
+union sem_fields {
+ struct { /* no operands */
+ int empty;
+ } fmt_empty;
+ struct { /* */
+ UINT f_trapnum;
+ } sfmt_trap_s;
+ struct { /* */
+ SI f_s9x2;
+ } sfmt_ldw_s_gprel;
+ struct { /* */
+ INT f_s9x1;
+ } sfmt_ldb_s_gprel;
+ struct { /* */
+ SI f_s9x4;
+ } sfmt_ld_s_gprel;
+ struct { /* */
+ IADDR i_label25a;
+ } sfmt_bl;
+ struct { /* */
+ IADDR i_label13a;
+ } sfmt_bl_s;
+ struct { /* */
+ IADDR i_label25;
+ } sfmt_b_l;
+ struct { /* */
+ INT f_s12x2;
+ UINT f_op_B;
+ } sfmt_lp_L_s12_;
+ struct { /* */
+ UINT f_op__b;
+ UINT f_u8;
+ } sfmt_mov_s_r_u7;
+ struct { /* */
+ UINT f_op__b;
+ UINT f_u7;
+ } sfmt_add_s_r_u7;
+ struct { /* */
+ UINT f_op__b;
+ UINT f_op_h;
+ } sfmt_add_s_mcah;
+ struct { /* */
+ SI f_u8x4;
+ UINT f_op__b;
+ } sfmt_ld_s_pcrel;
+ struct { /* */
+ IADDR i_label21a;
+ UINT f_cond_Q;
+ } sfmt_blcc;
+ struct { /* */
+ IADDR i_label21;
+ UINT f_cond_Q;
+ } sfmt_bcc_l;
+ struct { /* */
+ IADDR i_label7;
+ UINT f_cond_i3;
+ } sfmt_bcc_s;
+ struct { /* */
+ IADDR i_label10;
+ UINT f_cond_i2;
+ } sfmt_b_s;
+ struct { /* */
+ SI f_u6x2;
+ UINT f_cond_Q;
+ UINT f_op_B;
+ } sfmt_lpcc_ccu6;
+ struct { /* */
+ UINT f_op__b;
+ UINT f_op__c;
+ UINT f_u3;
+ } sfmt_add_s_cbu3;
+ struct { /* */
+ INT f_s12;
+ UINT f_F;
+ UINT f_op_B;
+ } sfmt_add_L_s12__RA_;
+ struct { /* */
+ INT f_s9;
+ UINT f_op_B;
+ UINT f_op_C;
+ } sfmt_st_abs;
+ struct { /* */
+ SI f_u5x2;
+ UINT f_op__b;
+ UINT f_op__c;
+ } sfmt_ldw_s_abu;
+ struct { /* */
+ UINT f_op__b;
+ UINT f_op__c;
+ UINT f_u5;
+ } sfmt_ldb_s_abu;
+ struct { /* */
+ SI f_u5x4;
+ UINT f_op__b;
+ UINT f_op__c;
+ } sfmt_ld_s_abu;
+ struct { /* */
+ UINT f_op__a;
+ UINT f_op__b;
+ UINT f_op__c;
+ } sfmt_ld_s_abc;
+ struct { /* */
+ INT f_s9;
+ UINT f_op_A;
+ UINT f_op_B;
+ } sfmt_ld_abs;
+ struct { /* */
+ IADDR i_label8;
+ UINT f_brscond;
+ UINT f_op__b;
+ } sfmt_brcc_s;
+ struct { /* */
+ UINT f_F;
+ UINT f_op_A;
+ UINT f_op_B;
+ UINT f_op_C;
+ } sfmt_add_L_r_r__RA__RC;
+ struct { /* */
+ UINT f_F;
+ UINT f_op_A;
+ UINT f_op_B;
+ UINT f_u6;
+ } sfmt_add_L_u6__RA_;
+ struct { /* */
+ UINT f_F;
+ UINT f_cond_Q;
+ UINT f_op_B;
+ UINT f_u6;
+ } sfmt_add_ccu6__RA_;
+ struct { /* */
+ IADDR i_label9;
+ UINT f_brcond;
+ UINT f_op_B;
+ UINT f_u6;
+ } sfmt_brcc_U6;
+ struct { /* */
+ IADDR i_label9;
+ UINT f_brcond;
+ UINT f_op_B;
+ UINT f_op_C;
+ } sfmt_brcc_RC;
+ struct { /* */
+ UINT f_F;
+ UINT f_cond_Q;
+ UINT f_op_B;
+ UINT f_op_C;
+ UINT f_op_Cj;
+ } sfmt_j_cc___RC_noilink_;
+#if WITH_SCACHE_PBB
+ /* Writeback handler. */
+ struct {
+ /* Pointer to argbuf entry for insn whose results need writing back. */
+ const struct argbuf *abuf;
+ } write;
+ /* x-before handler */
+ struct {
+ /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
+ int first_p;
+ } before;
+ /* x-after handler */
+ struct {
+ int empty;
+ } after;
+ /* This entry is used to terminate each pbb. */
+ struct {
+ /* Number of insns in pbb. */
+ int insn_count;
+ /* Next pbb to execute. */
+ SCACHE *next;
+ SCACHE *branch_target;
+ } chain;
+#endif
+};
+
+/* The ARGBUF struct. */
+struct argbuf {
+ /* These are the baseclass definitions. */
+ IADDR addr;
+ const IDESC *idesc;
+ char trace_p;
+ char profile_p;
+ /* ??? Temporary hack for skip insns. */
+ char skip_count;
+ char unused;
+ /* cpu specific data follows */
+ union sem semantic;
+ int written;
+ union sem_fields fields;
+};
+
+/* A cached insn.
+
+ ??? SCACHE used to contain more than just argbuf. We could delete the
+ type entirely and always just use ARGBUF, but for future concerns and as
+ a level of abstraction it is left in. */
+
+struct scache {
+ struct argbuf argbuf;
+};
+
+/* Macros to simplify extraction, reading and semantic code.
+ These define and assign the local vars that contain the insn's fields. */
+
+#define EXTRACT_IFMT_EMPTY_VARS \
+ unsigned int length;
+#define EXTRACT_IFMT_EMPTY_CODE \
+ length = 0; \
+
+#define EXTRACT_IFMT_B_S_VARS \
+ UINT f_opm; \
+ UINT f_cond_i2; \
+ SI f_rel10; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_B_S_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_cond_i2 = EXTRACT_MSB0_UINT (insn, 32, 5, 2); \
+ f_rel10 = ((((EXTRACT_MSB0_INT (insn, 32, 7, 9)) << (1))) + (((pc) & (-4)))); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_BCC_S_VARS \
+ UINT f_opm; \
+ UINT f_cond_i2; \
+ UINT f_cond_i3; \
+ SI f_rel7; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_BCC_S_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_cond_i2 = EXTRACT_MSB0_UINT (insn, 32, 5, 2); \
+ f_cond_i3 = EXTRACT_MSB0_UINT (insn, 32, 7, 3); \
+ f_rel7 = ((((EXTRACT_MSB0_INT (insn, 32, 10, 6)) << (1))) + (((pc) & (-4)))); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_BRCC_S_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_brscond; \
+ SI f_rel8; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_BRCC_S_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_brscond = EXTRACT_MSB0_UINT (insn, 32, 8, 1); \
+ f_rel8 = ((((EXTRACT_MSB0_INT (insn, 32, 9, 7)) << (1))) + (((pc) & (-4)))); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_BCC_L_VARS \
+ UINT f_opm; \
+ UINT f_d21l; \
+ INT f_d21h; \
+ INT f_rel21; \
+ UINT f_buf; \
+ UINT f_delay_N; \
+ UINT f_cond_Q; \
+ unsigned int length;
+#define EXTRACT_IFMT_BCC_L_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_d21l = EXTRACT_MSB0_UINT (insn, 32, 5, 10); \
+ f_d21h = EXTRACT_MSB0_INT (insn, 32, 16, 10); \
+{\
+ f_rel21 = ((((((f_d21l) << (1))) | (((f_d21h) << (11))))) + (((pc) & (-4))));\
+}\
+ f_buf = EXTRACT_MSB0_UINT (insn, 32, 15, 1); \
+ f_delay_N = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_B_L_VARS \
+ UINT f_opm; \
+ UINT f_d21l; \
+ UINT f_d25m; \
+ INT f_d25h; \
+ INT f_rel25; \
+ UINT f_buf; \
+ UINT f_delay_N; \
+ UINT f_res27; \
+ unsigned int length;
+#define EXTRACT_IFMT_B_L_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_d21l = EXTRACT_MSB0_UINT (insn, 32, 5, 10); \
+ f_d25m = EXTRACT_MSB0_UINT (insn, 32, 16, 10); \
+ f_d25h = EXTRACT_MSB0_INT (insn, 32, 28, 4); \
+{\
+ f_rel25 = ((((((((f_d21l) << (1))) | (((f_d25m) << (11))))) | (((f_d25h) << (21))))) + (((pc) & (-4))));\
+}\
+ f_buf = EXTRACT_MSB0_UINT (insn, 32, 15, 1); \
+ f_delay_N = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_res27 = EXTRACT_MSB0_UINT (insn, 32, 27, 1); \
+
+#define EXTRACT_IFMT_BRCC_RC_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_d9l; \
+ INT f_d9h; \
+ INT f_rel9; \
+ UINT f_buf; \
+ UINT f_op_C; \
+ UINT f_delay_N; \
+ UINT f_br; \
+ UINT f_brcond; \
+ unsigned int length;
+#define EXTRACT_IFMT_BRCC_RC_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_d9l = EXTRACT_MSB0_UINT (insn, 32, 8, 7); \
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1); \
+{\
+ f_rel9 = ((((((f_d9l) << (1))) | (((f_d9h) << (8))))) + (((pc) & (-4))));\
+}\
+ f_buf = EXTRACT_MSB0_UINT (insn, 32, 15, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_delay_N = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_br = EXTRACT_MSB0_UINT (insn, 32, 27, 1); \
+ f_brcond = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
+
+#define EXTRACT_IFMT_BRCC_U6_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_d9l; \
+ INT f_d9h; \
+ INT f_rel9; \
+ UINT f_buf; \
+ UINT f_u6; \
+ UINT f_delay_N; \
+ UINT f_br; \
+ UINT f_brcond; \
+ unsigned int length;
+#define EXTRACT_IFMT_BRCC_U6_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_d9l = EXTRACT_MSB0_UINT (insn, 32, 8, 7); \
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1); \
+{\
+ f_rel9 = ((((((f_d9l) << (1))) | (((f_d9h) << (8))))) + (((pc) & (-4))));\
+}\
+ f_buf = EXTRACT_MSB0_UINT (insn, 32, 15, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_delay_N = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_br = EXTRACT_MSB0_UINT (insn, 32, 27, 1); \
+ f_brcond = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
+
+#define EXTRACT_IFMT_BL_S_VARS \
+ UINT f_opm; \
+ SI f_rel13bl; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_BL_S_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_rel13bl = ((((EXTRACT_MSB0_INT (insn, 32, 5, 11)) << (2))) + (((pc) & (-4)))); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_BLCC_VARS \
+ UINT f_opm; \
+ UINT f_d21bl; \
+ INT f_d21h; \
+ INT f_rel21bl; \
+ UINT f_bluf; \
+ UINT f_buf; \
+ UINT f_delay_N; \
+ UINT f_cond_Q; \
+ unsigned int length;
+#define EXTRACT_IFMT_BLCC_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_d21bl = EXTRACT_MSB0_UINT (insn, 32, 5, 9); \
+ f_d21h = EXTRACT_MSB0_INT (insn, 32, 16, 10); \
+{\
+ f_rel21bl = ((((((f_d21bl) << (2))) | (((f_d21h) << (11))))) + (((pc) & (-4))));\
+}\
+ f_bluf = EXTRACT_MSB0_UINT (insn, 32, 14, 1); \
+ f_buf = EXTRACT_MSB0_UINT (insn, 32, 15, 1); \
+ f_delay_N = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_BL_VARS \
+ UINT f_opm; \
+ UINT f_d21bl; \
+ UINT f_d25m; \
+ INT f_d25h; \
+ INT f_rel25bl; \
+ UINT f_bluf; \
+ UINT f_buf; \
+ UINT f_delay_N; \
+ UINT f_res27; \
+ unsigned int length;
+#define EXTRACT_IFMT_BL_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_d21bl = EXTRACT_MSB0_UINT (insn, 32, 5, 9); \
+ f_d25m = EXTRACT_MSB0_UINT (insn, 32, 16, 10); \
+ f_d25h = EXTRACT_MSB0_INT (insn, 32, 28, 4); \
+{\
+ f_rel25bl = ((((((((f_d21bl) << (2))) | (((f_d25m) << (11))))) | (((f_d25h) << (21))))) + (((pc) & (-4))));\
+}\
+ f_bluf = EXTRACT_MSB0_UINT (insn, 32, 14, 1); \
+ f_buf = EXTRACT_MSB0_UINT (insn, 32, 15, 1); \
+ f_delay_N = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_res27 = EXTRACT_MSB0_UINT (insn, 32, 27, 1); \
+
+#define EXTRACT_IFMT_LD_ABS_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_u8; \
+ INT f_d9h; \
+ INT f_s9; \
+ UINT f_LDODi; \
+ UINT f_ldoaa; \
+ UINT f_ldozzx; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_LD_ABS_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8); \
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1); \
+{\
+ f_s9 = ((f_u8) | (((f_d9h) << (8))));\
+}\
+ f_LDODi = EXTRACT_MSB0_UINT (insn, 32, 20, 1); \
+ f_ldoaa = EXTRACT_MSB0_UINT (insn, 32, 21, 2); \
+ f_ldozzx = EXTRACT_MSB0_UINT (insn, 32, 23, 3); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_LD_ABC_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_ldraa; \
+ UINT f_ldr6zzx; \
+ UINT f_LDRDi; \
+ UINT f_op_C; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_LD_ABC_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_ldraa = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_ldr6zzx = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_LDRDi = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_LD_S_ABC_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_op__c; \
+ UINT f_i16_43; \
+ UINT f_op__a; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_LD_S_ABC_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3); \
+ f_i16_43 = EXTRACT_MSB0_UINT (insn, 32, 11, 2); \
+ f_op__a = EXTRACT_MSB0_UINT (insn, 32, 13, 3); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_LD_S_ABU_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_op__c; \
+ SI f_u5x4; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_LD_S_ABU_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3); \
+ f_u5x4 = ((EXTRACT_MSB0_UINT (insn, 32, 11, 5)) << (2)); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_LD_S_ABSP_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_op__c; \
+ SI f_u5x4; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_LD_S_ABSP_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3); \
+ f_u5x4 = ((EXTRACT_MSB0_UINT (insn, 32, 11, 5)) << (2)); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_LD_S_GPREL_VARS \
+ UINT f_opm; \
+ UINT f_i16_gp_type; \
+ SI f_s9x4; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_LD_S_GPREL_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_i16_gp_type = EXTRACT_MSB0_UINT (insn, 32, 5, 2); \
+ f_s9x4 = ((EXTRACT_MSB0_INT (insn, 32, 7, 9)) << (2)); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_LD_S_PCREL_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ SI f_u8x4; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_LD_S_PCREL_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_u8x4 = ((EXTRACT_MSB0_UINT (insn, 32, 8, 8)) << (2)); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_LDB_S_ABU_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_op__c; \
+ UINT f_u5; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_LDB_S_ABU_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3); \
+ f_u5 = EXTRACT_MSB0_UINT (insn, 32, 11, 5); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_LDB_S_GPREL_VARS \
+ UINT f_opm; \
+ UINT f_i16_gp_type; \
+ INT f_s9x1; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_LDB_S_GPREL_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_i16_gp_type = EXTRACT_MSB0_UINT (insn, 32, 5, 2); \
+ f_s9x1 = EXTRACT_MSB0_INT (insn, 32, 7, 9); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_LDW_S_ABU_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_op__c; \
+ SI f_u5x2; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_LDW_S_ABU_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3); \
+ f_u5x2 = ((EXTRACT_MSB0_UINT (insn, 32, 11, 5)) << (1)); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_LDW_S_GPREL_VARS \
+ UINT f_opm; \
+ UINT f_i16_gp_type; \
+ SI f_s9x2; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_LDW_S_GPREL_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_i16_gp_type = EXTRACT_MSB0_UINT (insn, 32, 5, 2); \
+ f_s9x2 = ((EXTRACT_MSB0_INT (insn, 32, 7, 9)) << (1)); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_ST_ABS_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_u8; \
+ INT f_d9h; \
+ INT f_s9; \
+ UINT f_LDODi; \
+ UINT f_op_C; \
+ UINT f_stoaa; \
+ UINT f_stozzr; \
+ unsigned int length;
+#define EXTRACT_IFMT_ST_ABS_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8); \
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1); \
+{\
+ f_s9 = ((f_u8) | (((f_d9h) << (8))));\
+}\
+ f_LDODi = EXTRACT_MSB0_UINT (insn, 32, 20, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_stoaa = EXTRACT_MSB0_UINT (insn, 32, 27, 2); \
+ f_stozzr = EXTRACT_MSB0_UINT (insn, 32, 29, 3); \
+
+#define EXTRACT_IFMT_ADD_L_S12__RA__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ INT f_s12h; \
+ INT f_s12; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADD_L_S12__RA__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6); \
+{\
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));\
+}\
+
+#define EXTRACT_IFMT_ADD_CCU6__RA__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ UINT f_go_cc_type; \
+ UINT f_cond_Q; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADD_CCU6__RA__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_go_cc_type = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_ADD_L_U6__RA__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADD_L_U6__RA__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_ADD_L_R_R__RA__RC_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_C; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADD_L_R_R__RA__RC_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_ADD_CC__RA__RC_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_C; \
+ UINT f_go_cc_type; \
+ UINT f_cond_Q; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADD_CC__RA__RC_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_go_cc_type = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_ADD_S_CBU3_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_op__c; \
+ UINT f_i16_43; \
+ UINT f_u3; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADD_S_CBU3_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3); \
+ f_i16_43 = EXTRACT_MSB0_UINT (insn, 32, 11, 2); \
+ f_u3 = EXTRACT_MSB0_UINT (insn, 32, 13, 3); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_ADD_S_MCAH_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_h_2_0; \
+ UINT f_h_5_3; \
+ UINT f_op_h; \
+ UINT f_i16_43; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADD_S_MCAH_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_h_2_0 = EXTRACT_MSB0_UINT (insn, 32, 8, 3); \
+ f_h_5_3 = EXTRACT_MSB0_UINT (insn, 32, 13, 3); \
+{\
+ f_op_h = ((f_h_2_0) | (((f_h_5_3) << (3))));\
+}\
+ f_i16_43 = EXTRACT_MSB0_UINT (insn, 32, 11, 2); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_ADD_S_ASSPSP_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_op__c; \
+ SI f_u5x4; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADD_S_ASSPSP_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3); \
+ f_u5x4 = ((EXTRACT_MSB0_UINT (insn, 32, 11, 5)) << (2)); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_ADD_S_GP_VARS \
+ UINT f_opm; \
+ UINT f_i16_gp_type; \
+ SI f_s9x4; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADD_S_GP_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_i16_gp_type = EXTRACT_MSB0_UINT (insn, 32, 5, 2); \
+ f_s9x4 = ((EXTRACT_MSB0_INT (insn, 32, 7, 9)) << (2)); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_ADD_S_R_U7_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_i16addcmpu7_type; \
+ UINT f_u7; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADD_S_R_U7_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_i16addcmpu7_type = EXTRACT_MSB0_UINT (insn, 32, 8, 1); \
+ f_u7 = EXTRACT_MSB0_UINT (insn, 32, 9, 7); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_I16_GO_SUB_S_GO_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_op__c; \
+ UINT f_i16_go; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_I16_GO_SUB_S_GO_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3); \
+ f_i16_go = EXTRACT_MSB0_UINT (insn, 32, 11, 5); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_SUB_S_GO_SUB_NE_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_op__c; \
+ UINT f_i16_go; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_SUB_S_GO_SUB_NE_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3); \
+ f_i16_go = EXTRACT_MSB0_UINT (insn, 32, 11, 5); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_SUB_S_SSB_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_op__c; \
+ UINT f_u5; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_SUB_S_SSB_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3); \
+ f_u5 = EXTRACT_MSB0_UINT (insn, 32, 11, 5); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_MOV_L_U6__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOV_L_U6__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_MOV_L_R_R__RC_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_C; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOV_L_R_R__RC_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_MOV_S_R_U7_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_u8; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOV_S_R_U7_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_TST_L_S12__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ INT f_s12h; \
+ INT f_s12; \
+ unsigned int length;
+#define EXTRACT_IFMT_TST_L_S12__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6); \
+{\
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));\
+}\
+
+#define EXTRACT_IFMT_TST_CCU6__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ UINT f_go_cc_type; \
+ UINT f_cond_Q; \
+ unsigned int length;
+#define EXTRACT_IFMT_TST_CCU6__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_go_cc_type = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_TST_L_U6__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_TST_L_U6__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_TST_L_R_R__RC_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_C; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_TST_L_R_R__RC_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_TST_CC__RC_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_C; \
+ UINT f_go_cc_type; \
+ UINT f_cond_Q; \
+ unsigned int length;
+#define EXTRACT_IFMT_TST_CC__RC_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_go_cc_type = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_J_L_R_R___RC_NOILINK__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_Cj; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_J_L_R_R___RC_NOILINK__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_Cj = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_J_CC___RC_NOILINK__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_Cj; \
+ UINT f_go_cc_type; \
+ UINT f_cond_Q; \
+ unsigned int length;
+#define EXTRACT_IFMT_J_CC___RC_NOILINK__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_Cj = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_go_cc_type = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_J_L_R_R___RC_ILINK__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_Cj; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_J_L_R_R___RC_ILINK__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_Cj = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_J_CC___RC_ILINK__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_Cj; \
+ UINT f_go_cc_type; \
+ UINT f_cond_Q; \
+ unsigned int length;
+#define EXTRACT_IFMT_J_CC___RC_ILINK__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_Cj = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_go_cc_type = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_J_L_S12__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ INT f_s12h; \
+ INT f_s12; \
+ unsigned int length;
+#define EXTRACT_IFMT_J_L_S12__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6); \
+{\
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));\
+}\
+
+#define EXTRACT_IFMT_J_CCU6__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ UINT f_go_cc_type; \
+ UINT f_cond_Q; \
+ unsigned int length;
+#define EXTRACT_IFMT_J_CCU6__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_go_cc_type = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_J_L_U6__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_J_L_U6__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_J_S__S_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_op__c; \
+ UINT f_i16_go; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_J_S__S_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3); \
+ f_i16_go = EXTRACT_MSB0_UINT (insn, 32, 11, 5); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_J_L_R_R_D___RC__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_C; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_J_L_R_R_D___RC__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_J_CC_D___RC__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_C; \
+ UINT f_go_cc_type; \
+ UINT f_cond_Q; \
+ unsigned int length;
+#define EXTRACT_IFMT_J_CC_D___RC__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_go_cc_type = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_LP_L_S12__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ INT f_s12h; \
+ INT f_s12x2; \
+ unsigned int length;
+#define EXTRACT_IFMT_LP_L_S12__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6); \
+{\
+ f_s12x2 = ((((f_u6) << (1))) | (((f_s12h) << (7))));\
+}\
+
+#define EXTRACT_IFMT_LPCC_CCU6_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ SI f_u6x2; \
+ UINT f_go_cc_type; \
+ UINT f_cond_Q; \
+ unsigned int length;
+#define EXTRACT_IFMT_LPCC_CCU6_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6x2 = ((EXTRACT_MSB0_UINT (insn, 32, 20, 6)) << (1)); \
+ f_go_cc_type = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_LR_L_R_R___RC__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_C; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_LR_L_R_R___RC__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_LR_L_S12__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ INT f_s12h; \
+ INT f_s12; \
+ unsigned int length;
+#define EXTRACT_IFMT_LR_L_S12__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6); \
+{\
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));\
+}\
+
+#define EXTRACT_IFMT_LR_L_U6__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_LR_L_U6__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_ASL_L_R_R__RC_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_C; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_ASL_L_R_R__RC_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_ASL_L_U6__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_ASL_L_U6__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_EX_L_R_R__RC_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_C; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_EX_L_R_R__RC_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_EX_L_U6__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_EX_L_U6__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_SWI_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_B_5_3; \
+ UINT f_op_C; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_SWI_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_TRAP_S_VARS \
+ UINT f_opm; \
+ UINT f_trapnum; \
+ UINT f_i16_go; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_TRAP_S_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_trapnum = EXTRACT_MSB0_UINT (insn, 32, 5, 6); \
+ f_i16_go = EXTRACT_MSB0_UINT (insn, 32, 11, 5); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_BRK_S_VARS \
+ UINT f_opm; \
+ UINT f_trapnum; \
+ UINT f_i16_go; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_BRK_S_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_trapnum = EXTRACT_MSB0_UINT (insn, 32, 5, 6); \
+ f_i16_go = EXTRACT_MSB0_UINT (insn, 32, 11, 5); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_DIVAW_CCU6__RA__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ UINT f_go_cc_type; \
+ UINT f_cond_Q; \
+ unsigned int length;
+#define EXTRACT_IFMT_DIVAW_CCU6__RA__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_go_cc_type = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_DIVAW_L_U6__RA__VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_u6; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_DIVAW_L_U6__RA__CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_DIVAW_L_R_R__RA__RC_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_C; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_DIVAW_L_R_R__RA__RC_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+#define EXTRACT_IFMT_DIVAW_CC__RA__RC_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_C; \
+ UINT f_go_cc_type; \
+ UINT f_cond_Q; \
+ unsigned int length;
+#define EXTRACT_IFMT_DIVAW_CC__RA__RC_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_go_cc_type = EXTRACT_MSB0_UINT (insn, 32, 26, 1); \
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_POP_S_B_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_op__c; \
+ UINT f_u5; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_POP_S_B_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3); \
+ f_u5 = EXTRACT_MSB0_UINT (insn, 32, 11, 5); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_POP_S_BLINK_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_op__c; \
+ UINT f_u5; \
+ UINT f_dummy; \
+ unsigned int length;
+#define EXTRACT_IFMT_POP_S_BLINK_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3); \
+ f_u5 = EXTRACT_MSB0_UINT (insn, 32, 11, 5); \
+ f_dummy = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_CURRENT_LOOP_END_VARS \
+ UINT f_opm; \
+ UINT f_op__b; \
+ UINT f_B_5_3; \
+ UINT f_op_B; \
+ UINT f_go_type; \
+ UINT f_go_op; \
+ UINT f_F; \
+ UINT f_op_C; \
+ UINT f_op_A; \
+ unsigned int length;
+#define EXTRACT_IFMT_CURRENT_LOOP_END_CODE \
+ length = 4; \
+ f_opm = EXTRACT_MSB0_UINT (insn, 32, 0, 5); \
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3); \
+{\
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));\
+}\
+ f_go_type = EXTRACT_MSB0_UINT (insn, 32, 8, 2); \
+ f_go_op = EXTRACT_MSB0_UINT (insn, 32, 10, 6); \
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1); \
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6); \
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6); \
+
+/* Collection of various things for the trace handler to use. */
+
+typedef struct trace_record {
+ IADDR pc;
+ /* FIXME:wip */
+} TRACE_RECORD;
+
+#endif /* CPU_ARC700F_H */
diff --git a/sim/arc/cpuall.h b/sim/arc/cpuall.h
new file mode 100644
index 0000000..106826d
--- /dev/null
+++ b/sim/arc/cpuall.h
@@ -0,0 +1,82 @@
+/* Simulator CPU header for arc.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2007 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#ifndef ARC_CPUALL_H
+#define ARC_CPUALL_H
+
+/* Include files for each cpu family. */
+
+#ifdef WANT_CPU_A5F
+#include "eng5.h"
+#include "cgen-engine.h"
+#include "cpu5.h"
+#include "decode5.h"
+#endif
+
+#ifdef WANT_CPU_ARC600F
+#include "eng6.h"
+#include "cgen-engine.h"
+#include "cpu6.h"
+#include "decode6.h"
+#endif
+
+#ifdef WANT_CPU_ARC700F
+#include "eng7.h"
+#include "cgen-engine.h"
+#include "cpu7.h"
+#include "decode7.h"
+#endif
+
+extern const MACH a5_mach;
+extern const MACH arc600_mach;
+extern const MACH arc700_mach;
+
+#ifndef WANT_CPU
+/* The ARGBUF struct. */
+struct argbuf {
+ /* These are the baseclass definitions. */
+ IADDR addr;
+ const IDESC *idesc;
+ char trace_p;
+ char profile_p;
+ /* ??? Temporary hack for skip insns. */
+ char skip_count;
+ char unused;
+ /* cpu specific data follows */
+};
+#endif
+
+#ifndef WANT_CPU
+/* A cached insn.
+
+ ??? SCACHE used to contain more than just argbuf. We could delete the
+ type entirely and always just use ARGBUF, but for future concerns and as
+ a level of abstraction it is left in. */
+
+struct scache {
+ struct argbuf argbuf;
+};
+#endif
+
+#endif /* ARC_CPUALL_H */
diff --git a/sim/arc/decode5.c b/sim/arc/decode5.c
new file mode 100644
index 0000000..2287ee4
--- /dev/null
+++ b/sim/arc/decode5.c
@@ -0,0 +1,21199 @@
+/* Simulator instruction decoder for a5f.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2007 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#define WANT_CPU a5f
+#define WANT_CPU_A5F
+
+#include "sim-main.h"
+#include "sim-assert.h"
+
+/* The instruction descriptor array.
+ This is computed at runtime. Space for it is not malloc'd to save a
+ teensy bit of cpu in the decoder. Moving it to malloc space is trivial
+ but won't be done until necessary (we don't currently support the runtime
+ addition of instructions nor an SMP machine with different cpus). */
+static IDESC a5f_insn_data[A5F_INSN__MAX];
+
+/* Commas between elements are contained in the macros.
+ Some of these are conditionally compiled out. */
+
+static const struct insn_sem a5f_insn_sem[] =
+{
+ { VIRTUAL_INSN_X_INVALID, A5F_INSN_X_INVALID, A5F_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_AFTER, A5F_INSN_X_AFTER, A5F_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_BEFORE, A5F_INSN_X_BEFORE, A5F_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_CTI_CHAIN, A5F_INSN_X_CTI_CHAIN, A5F_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_CHAIN, A5F_INSN_X_CHAIN, A5F_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_BEGIN, A5F_INSN_X_BEGIN, A5F_SFMT_EMPTY },
+ { ARC_INSN_B_S, A5F_INSN_B_S, A5F_SFMT_B_S },
+ { ARC_INSN_BCC_S, A5F_INSN_BCC_S, A5F_SFMT_BCC_S },
+ { ARC_INSN_BRCC_S, A5F_INSN_BRCC_S, A5F_SFMT_BRCC_S },
+ { ARC_INSN_BCC_L, A5F_INSN_BCC_L, A5F_SFMT_BCC_L },
+ { ARC_INSN_BCC_L_D, A5F_INSN_BCC_L_D, A5F_SFMT_BCC_L },
+ { ARC_INSN_B_L, A5F_INSN_B_L, A5F_SFMT_B_L },
+ { ARC_INSN_B_L_D, A5F_INSN_B_L_D, A5F_SFMT_B_L },
+ { ARC_INSN_BRCC_RC, A5F_INSN_BRCC_RC, A5F_SFMT_BRCC_RC },
+ { ARC_INSN_BRCC_RC_D, A5F_INSN_BRCC_RC_D, A5F_SFMT_BRCC_RC },
+ { ARC_INSN_BRCC_U6, A5F_INSN_BRCC_U6, A5F_SFMT_BRCC_U6 },
+ { ARC_INSN_BRCC_U6_D, A5F_INSN_BRCC_U6_D, A5F_SFMT_BRCC_U6 },
+ { ARC_INSN_BL_S, A5F_INSN_BL_S, A5F_SFMT_BL_S },
+ { ARC_INSN_BLCC, A5F_INSN_BLCC, A5F_SFMT_BLCC },
+ { ARC_INSN_BLCC_D, A5F_INSN_BLCC_D, A5F_SFMT_BLCC },
+ { ARC_INSN_BL, A5F_INSN_BL, A5F_SFMT_BL },
+ { ARC_INSN_BL_D, A5F_INSN_BL_D, A5F_SFMT_BL_D },
+ { ARC_INSN_LD_ABS, A5F_INSN_LD_ABS, A5F_SFMT_LD_ABS },
+ { ARC_INSN_LD__AW_ABS, A5F_INSN_LD__AW_ABS, A5F_SFMT_LD__AW_ABS },
+ { ARC_INSN_LD_AB_ABS, A5F_INSN_LD_AB_ABS, A5F_SFMT_LD__AW_ABS },
+ { ARC_INSN_LD_AS_ABS, A5F_INSN_LD_AS_ABS, A5F_SFMT_LD_ABS },
+ { ARC_INSN_LD_ABC, A5F_INSN_LD_ABC, A5F_SFMT_LD_ABC },
+ { ARC_INSN_LD__AW_ABC, A5F_INSN_LD__AW_ABC, A5F_SFMT_LD__AW_ABC },
+ { ARC_INSN_LD_AB_ABC, A5F_INSN_LD_AB_ABC, A5F_SFMT_LD__AW_ABC },
+ { ARC_INSN_LD_AS_ABC, A5F_INSN_LD_AS_ABC, A5F_SFMT_LD_ABC },
+ { ARC_INSN_LD_S_ABC, A5F_INSN_LD_S_ABC, A5F_SFMT_LD_S_ABC },
+ { ARC_INSN_LD_S_ABU, A5F_INSN_LD_S_ABU, A5F_SFMT_LD_S_ABU },
+ { ARC_INSN_LD_S_ABSP, A5F_INSN_LD_S_ABSP, A5F_SFMT_LD_S_ABSP },
+ { ARC_INSN_LD_S_GPREL, A5F_INSN_LD_S_GPREL, A5F_SFMT_LD_S_GPREL },
+ { ARC_INSN_LD_S_PCREL, A5F_INSN_LD_S_PCREL, A5F_SFMT_LD_S_PCREL },
+ { ARC_INSN_LDB_ABS, A5F_INSN_LDB_ABS, A5F_SFMT_LDB_ABS },
+ { ARC_INSN_LDB__AW_ABS, A5F_INSN_LDB__AW_ABS, A5F_SFMT_LDB__AW_ABS },
+ { ARC_INSN_LDB_AB_ABS, A5F_INSN_LDB_AB_ABS, A5F_SFMT_LDB__AW_ABS },
+ { ARC_INSN_LDB_AS_ABS, A5F_INSN_LDB_AS_ABS, A5F_SFMT_LDB_AS_ABS },
+ { ARC_INSN_LDB_ABC, A5F_INSN_LDB_ABC, A5F_SFMT_LDB_ABC },
+ { ARC_INSN_LDB__AW_ABC, A5F_INSN_LDB__AW_ABC, A5F_SFMT_LDB__AW_ABC },
+ { ARC_INSN_LDB_AB_ABC, A5F_INSN_LDB_AB_ABC, A5F_SFMT_LDB__AW_ABC },
+ { ARC_INSN_LDB_AS_ABC, A5F_INSN_LDB_AS_ABC, A5F_SFMT_LDB_AS_ABC },
+ { ARC_INSN_LDB_S_ABC, A5F_INSN_LDB_S_ABC, A5F_SFMT_LDB_S_ABC },
+ { ARC_INSN_LDB_S_ABU, A5F_INSN_LDB_S_ABU, A5F_SFMT_LDB_S_ABU },
+ { ARC_INSN_LDB_S_ABSP, A5F_INSN_LDB_S_ABSP, A5F_SFMT_LDB_S_ABSP },
+ { ARC_INSN_LDB_S_GPREL, A5F_INSN_LDB_S_GPREL, A5F_SFMT_LDB_S_GPREL },
+ { ARC_INSN_LDB_X_ABS, A5F_INSN_LDB_X_ABS, A5F_SFMT_LDB_ABS },
+ { ARC_INSN_LDB__AW_X_ABS, A5F_INSN_LDB__AW_X_ABS, A5F_SFMT_LDB__AW_ABS },
+ { ARC_INSN_LDB_AB_X_ABS, A5F_INSN_LDB_AB_X_ABS, A5F_SFMT_LDB__AW_ABS },
+ { ARC_INSN_LDB_AS_X_ABS, A5F_INSN_LDB_AS_X_ABS, A5F_SFMT_LDB_AS_ABS },
+ { ARC_INSN_LDB_X_ABC, A5F_INSN_LDB_X_ABC, A5F_SFMT_LDB_ABC },
+ { ARC_INSN_LDB__AW_X_ABC, A5F_INSN_LDB__AW_X_ABC, A5F_SFMT_LDB__AW_ABC },
+ { ARC_INSN_LDB_AB_X_ABC, A5F_INSN_LDB_AB_X_ABC, A5F_SFMT_LDB__AW_ABC },
+ { ARC_INSN_LDB_AS_X_ABC, A5F_INSN_LDB_AS_X_ABC, A5F_SFMT_LDB_AS_ABC },
+ { ARC_INSN_LDW_ABS, A5F_INSN_LDW_ABS, A5F_SFMT_LDW_ABS },
+ { ARC_INSN_LDW__AW_ABS, A5F_INSN_LDW__AW_ABS, A5F_SFMT_LDW__AW_ABS },
+ { ARC_INSN_LDW_AB_ABS, A5F_INSN_LDW_AB_ABS, A5F_SFMT_LDW__AW_ABS },
+ { ARC_INSN_LDW_AS_ABS, A5F_INSN_LDW_AS_ABS, A5F_SFMT_LDW_ABS },
+ { ARC_INSN_LDW_ABC, A5F_INSN_LDW_ABC, A5F_SFMT_LDW_ABC },
+ { ARC_INSN_LDW__AW_ABC, A5F_INSN_LDW__AW_ABC, A5F_SFMT_LDW__AW_ABC },
+ { ARC_INSN_LDW_AB_ABC, A5F_INSN_LDW_AB_ABC, A5F_SFMT_LDW__AW_ABC },
+ { ARC_INSN_LDW_AS_ABC, A5F_INSN_LDW_AS_ABC, A5F_SFMT_LDW_ABC },
+ { ARC_INSN_LDW_S_ABC, A5F_INSN_LDW_S_ABC, A5F_SFMT_LDW_S_ABC },
+ { ARC_INSN_LDW_S_ABU, A5F_INSN_LDW_S_ABU, A5F_SFMT_LDW_S_ABU },
+ { ARC_INSN_LDW_S_GPREL, A5F_INSN_LDW_S_GPREL, A5F_SFMT_LDW_S_GPREL },
+ { ARC_INSN_LDW_X_ABS, A5F_INSN_LDW_X_ABS, A5F_SFMT_LDW_ABS },
+ { ARC_INSN_LDW__AW_X_ABS, A5F_INSN_LDW__AW_X_ABS, A5F_SFMT_LDW__AW_ABS },
+ { ARC_INSN_LDW_AB_X_ABS, A5F_INSN_LDW_AB_X_ABS, A5F_SFMT_LDW__AW_ABS },
+ { ARC_INSN_LDW_AS_X_ABS, A5F_INSN_LDW_AS_X_ABS, A5F_SFMT_LDW_ABS },
+ { ARC_INSN_LDW_X_ABC, A5F_INSN_LDW_X_ABC, A5F_SFMT_LDW_ABC },
+ { ARC_INSN_LDW__AW_X_ABC, A5F_INSN_LDW__AW_X_ABC, A5F_SFMT_LDW__AW_ABC },
+ { ARC_INSN_LDW_AB_X_ABC, A5F_INSN_LDW_AB_X_ABC, A5F_SFMT_LDW__AW_ABC },
+ { ARC_INSN_LDW_AS_X_ABC, A5F_INSN_LDW_AS_X_ABC, A5F_SFMT_LDW_ABC },
+ { ARC_INSN_LDW_S_X_ABU, A5F_INSN_LDW_S_X_ABU, A5F_SFMT_LDW_S_ABU },
+ { ARC_INSN_ST_ABS, A5F_INSN_ST_ABS, A5F_SFMT_ST_ABS },
+ { ARC_INSN_ST__AW_ABS, A5F_INSN_ST__AW_ABS, A5F_SFMT_ST__AW_ABS },
+ { ARC_INSN_ST_AB_ABS, A5F_INSN_ST_AB_ABS, A5F_SFMT_ST__AW_ABS },
+ { ARC_INSN_ST_AS_ABS, A5F_INSN_ST_AS_ABS, A5F_SFMT_ST_ABS },
+ { ARC_INSN_ST_S_ABU, A5F_INSN_ST_S_ABU, A5F_SFMT_ST_S_ABU },
+ { ARC_INSN_ST_S_ABSP, A5F_INSN_ST_S_ABSP, A5F_SFMT_ST_S_ABSP },
+ { ARC_INSN_STB_ABS, A5F_INSN_STB_ABS, A5F_SFMT_STB_ABS },
+ { ARC_INSN_STB__AW_ABS, A5F_INSN_STB__AW_ABS, A5F_SFMT_STB__AW_ABS },
+ { ARC_INSN_STB_AB_ABS, A5F_INSN_STB_AB_ABS, A5F_SFMT_STB__AW_ABS },
+ { ARC_INSN_STB_AS_ABS, A5F_INSN_STB_AS_ABS, A5F_SFMT_STB_AS_ABS },
+ { ARC_INSN_STB_S_ABU, A5F_INSN_STB_S_ABU, A5F_SFMT_STB_S_ABU },
+ { ARC_INSN_STB_S_ABSP, A5F_INSN_STB_S_ABSP, A5F_SFMT_STB_S_ABSP },
+ { ARC_INSN_STW_ABS, A5F_INSN_STW_ABS, A5F_SFMT_STW_ABS },
+ { ARC_INSN_STW__AW_ABS, A5F_INSN_STW__AW_ABS, A5F_SFMT_STW__AW_ABS },
+ { ARC_INSN_STW_AB_ABS, A5F_INSN_STW_AB_ABS, A5F_SFMT_STW__AW_ABS },
+ { ARC_INSN_STW_AS_ABS, A5F_INSN_STW_AS_ABS, A5F_SFMT_STW_ABS },
+ { ARC_INSN_STW_S_ABU, A5F_INSN_STW_S_ABU, A5F_SFMT_STW_S_ABU },
+ { ARC_INSN_ADD_L_S12__RA_, A5F_INSN_ADD_L_S12__RA_, A5F_SFMT_ADD_L_S12__RA_ },
+ { ARC_INSN_ADD_CCU6__RA_, A5F_INSN_ADD_CCU6__RA_, A5F_SFMT_ADD_CCU6__RA_ },
+ { ARC_INSN_ADD_L_U6__RA_, A5F_INSN_ADD_L_U6__RA_, A5F_SFMT_ADD_L_U6__RA_ },
+ { ARC_INSN_ADD_L_R_R__RA__RC, A5F_INSN_ADD_L_R_R__RA__RC, A5F_SFMT_ADD_L_R_R__RA__RC },
+ { ARC_INSN_ADD_CC__RA__RC, A5F_INSN_ADD_CC__RA__RC, A5F_SFMT_ADD_CC__RA__RC },
+ { ARC_INSN_ADD_S_ABC, A5F_INSN_ADD_S_ABC, A5F_SFMT_ADD_S_ABC },
+ { ARC_INSN_ADD_S_CBU3, A5F_INSN_ADD_S_CBU3, A5F_SFMT_ADD_S_CBU3 },
+ { ARC_INSN_ADD_S_MCAH, A5F_INSN_ADD_S_MCAH, A5F_SFMT_ADD_S_MCAH },
+ { ARC_INSN_ADD_S_ABSP, A5F_INSN_ADD_S_ABSP, A5F_SFMT_ADD_S_ABSP },
+ { ARC_INSN_ADD_S_ASSPSP, A5F_INSN_ADD_S_ASSPSP, A5F_SFMT_ADD_S_ASSPSP },
+ { ARC_INSN_ADD_S_GP, A5F_INSN_ADD_S_GP, A5F_SFMT_ADD_S_GP },
+ { ARC_INSN_ADD_S_R_U7, A5F_INSN_ADD_S_R_U7, A5F_SFMT_ADD_S_R_U7 },
+ { ARC_INSN_ADC_L_S12__RA_, A5F_INSN_ADC_L_S12__RA_, A5F_SFMT_ADC_L_S12__RA_ },
+ { ARC_INSN_ADC_CCU6__RA_, A5F_INSN_ADC_CCU6__RA_, A5F_SFMT_ADC_CCU6__RA_ },
+ { ARC_INSN_ADC_L_U6__RA_, A5F_INSN_ADC_L_U6__RA_, A5F_SFMT_ADC_L_U6__RA_ },
+ { ARC_INSN_ADC_L_R_R__RA__RC, A5F_INSN_ADC_L_R_R__RA__RC, A5F_SFMT_ADC_L_R_R__RA__RC },
+ { ARC_INSN_ADC_CC__RA__RC, A5F_INSN_ADC_CC__RA__RC, A5F_SFMT_ADC_CC__RA__RC },
+ { ARC_INSN_SUB_L_S12__RA_, A5F_INSN_SUB_L_S12__RA_, A5F_SFMT_ADD_L_S12__RA_ },
+ { ARC_INSN_SUB_CCU6__RA_, A5F_INSN_SUB_CCU6__RA_, A5F_SFMT_ADD_CCU6__RA_ },
+ { ARC_INSN_SUB_L_U6__RA_, A5F_INSN_SUB_L_U6__RA_, A5F_SFMT_ADD_L_U6__RA_ },
+ { ARC_INSN_SUB_L_R_R__RA__RC, A5F_INSN_SUB_L_R_R__RA__RC, A5F_SFMT_ADD_L_R_R__RA__RC },
+ { ARC_INSN_SUB_CC__RA__RC, A5F_INSN_SUB_CC__RA__RC, A5F_SFMT_ADD_CC__RA__RC },
+ { ARC_INSN_SUB_S_CBU3, A5F_INSN_SUB_S_CBU3, A5F_SFMT_ADD_S_CBU3 },
+ { ARC_INSN_I16_GO_SUB_S_GO, A5F_INSN_I16_GO_SUB_S_GO, A5F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_SUB_S_GO_SUB_NE, A5F_INSN_SUB_S_GO_SUB_NE, A5F_SFMT_SUB_S_GO_SUB_NE },
+ { ARC_INSN_SUB_S_SSB, A5F_INSN_SUB_S_SSB, A5F_SFMT_SUB_S_SSB },
+ { ARC_INSN_SUB_S_ASSPSP, A5F_INSN_SUB_S_ASSPSP, A5F_SFMT_ADD_S_ASSPSP },
+ { ARC_INSN_SBC_L_S12__RA_, A5F_INSN_SBC_L_S12__RA_, A5F_SFMT_ADC_L_S12__RA_ },
+ { ARC_INSN_SBC_CCU6__RA_, A5F_INSN_SBC_CCU6__RA_, A5F_SFMT_ADC_CCU6__RA_ },
+ { ARC_INSN_SBC_L_U6__RA_, A5F_INSN_SBC_L_U6__RA_, A5F_SFMT_ADC_L_U6__RA_ },
+ { ARC_INSN_SBC_L_R_R__RA__RC, A5F_INSN_SBC_L_R_R__RA__RC, A5F_SFMT_ADC_L_R_R__RA__RC },
+ { ARC_INSN_SBC_CC__RA__RC, A5F_INSN_SBC_CC__RA__RC, A5F_SFMT_ADC_CC__RA__RC },
+ { ARC_INSN_AND_L_S12__RA_, A5F_INSN_AND_L_S12__RA_, A5F_SFMT_AND_L_S12__RA_ },
+ { ARC_INSN_AND_CCU6__RA_, A5F_INSN_AND_CCU6__RA_, A5F_SFMT_AND_CCU6__RA_ },
+ { ARC_INSN_AND_L_U6__RA_, A5F_INSN_AND_L_U6__RA_, A5F_SFMT_AND_L_U6__RA_ },
+ { ARC_INSN_AND_L_R_R__RA__RC, A5F_INSN_AND_L_R_R__RA__RC, A5F_SFMT_AND_L_R_R__RA__RC },
+ { ARC_INSN_AND_CC__RA__RC, A5F_INSN_AND_CC__RA__RC, A5F_SFMT_AND_CC__RA__RC },
+ { ARC_INSN_I16_GO_AND_S_GO, A5F_INSN_I16_GO_AND_S_GO, A5F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_OR_L_S12__RA_, A5F_INSN_OR_L_S12__RA_, A5F_SFMT_AND_L_S12__RA_ },
+ { ARC_INSN_OR_CCU6__RA_, A5F_INSN_OR_CCU6__RA_, A5F_SFMT_AND_CCU6__RA_ },
+ { ARC_INSN_OR_L_U6__RA_, A5F_INSN_OR_L_U6__RA_, A5F_SFMT_AND_L_U6__RA_ },
+ { ARC_INSN_OR_L_R_R__RA__RC, A5F_INSN_OR_L_R_R__RA__RC, A5F_SFMT_AND_L_R_R__RA__RC },
+ { ARC_INSN_OR_CC__RA__RC, A5F_INSN_OR_CC__RA__RC, A5F_SFMT_AND_CC__RA__RC },
+ { ARC_INSN_I16_GO_OR_S_GO, A5F_INSN_I16_GO_OR_S_GO, A5F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_BIC_L_S12__RA_, A5F_INSN_BIC_L_S12__RA_, A5F_SFMT_AND_L_S12__RA_ },
+ { ARC_INSN_BIC_CCU6__RA_, A5F_INSN_BIC_CCU6__RA_, A5F_SFMT_AND_CCU6__RA_ },
+ { ARC_INSN_BIC_L_U6__RA_, A5F_INSN_BIC_L_U6__RA_, A5F_SFMT_AND_L_U6__RA_ },
+ { ARC_INSN_BIC_L_R_R__RA__RC, A5F_INSN_BIC_L_R_R__RA__RC, A5F_SFMT_AND_L_R_R__RA__RC },
+ { ARC_INSN_BIC_CC__RA__RC, A5F_INSN_BIC_CC__RA__RC, A5F_SFMT_AND_CC__RA__RC },
+ { ARC_INSN_I16_GO_BIC_S_GO, A5F_INSN_I16_GO_BIC_S_GO, A5F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_XOR_L_S12__RA_, A5F_INSN_XOR_L_S12__RA_, A5F_SFMT_AND_L_S12__RA_ },
+ { ARC_INSN_XOR_CCU6__RA_, A5F_INSN_XOR_CCU6__RA_, A5F_SFMT_AND_CCU6__RA_ },
+ { ARC_INSN_XOR_L_U6__RA_, A5F_INSN_XOR_L_U6__RA_, A5F_SFMT_AND_L_U6__RA_ },
+ { ARC_INSN_XOR_L_R_R__RA__RC, A5F_INSN_XOR_L_R_R__RA__RC, A5F_SFMT_AND_L_R_R__RA__RC },
+ { ARC_INSN_XOR_CC__RA__RC, A5F_INSN_XOR_CC__RA__RC, A5F_SFMT_AND_CC__RA__RC },
+ { ARC_INSN_I16_GO_XOR_S_GO, A5F_INSN_I16_GO_XOR_S_GO, A5F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_MAX_L_S12__RA_, A5F_INSN_MAX_L_S12__RA_, A5F_SFMT_ADD_L_S12__RA_ },
+ { ARC_INSN_MAX_CCU6__RA_, A5F_INSN_MAX_CCU6__RA_, A5F_SFMT_ADD_CCU6__RA_ },
+ { ARC_INSN_MAX_L_U6__RA_, A5F_INSN_MAX_L_U6__RA_, A5F_SFMT_ADD_L_U6__RA_ },
+ { ARC_INSN_MAX_L_R_R__RA__RC, A5F_INSN_MAX_L_R_R__RA__RC, A5F_SFMT_ADD_L_R_R__RA__RC },
+ { ARC_INSN_MAX_CC__RA__RC, A5F_INSN_MAX_CC__RA__RC, A5F_SFMT_ADD_CC__RA__RC },
+ { ARC_INSN_MIN_L_S12__RA_, A5F_INSN_MIN_L_S12__RA_, A5F_SFMT_ADD_L_S12__RA_ },
+ { ARC_INSN_MIN_CCU6__RA_, A5F_INSN_MIN_CCU6__RA_, A5F_SFMT_ADD_CCU6__RA_ },
+ { ARC_INSN_MIN_L_U6__RA_, A5F_INSN_MIN_L_U6__RA_, A5F_SFMT_ADD_L_U6__RA_ },
+ { ARC_INSN_MIN_L_R_R__RA__RC, A5F_INSN_MIN_L_R_R__RA__RC, A5F_SFMT_ADD_L_R_R__RA__RC },
+ { ARC_INSN_MIN_CC__RA__RC, A5F_INSN_MIN_CC__RA__RC, A5F_SFMT_ADD_CC__RA__RC },
+ { ARC_INSN_MOV_L_S12_, A5F_INSN_MOV_L_S12_, A5F_SFMT_MOV_L_S12_ },
+ { ARC_INSN_MOV_CCU6_, A5F_INSN_MOV_CCU6_, A5F_SFMT_MOV_CCU6_ },
+ { ARC_INSN_MOV_L_U6_, A5F_INSN_MOV_L_U6_, A5F_SFMT_MOV_L_U6_ },
+ { ARC_INSN_MOV_L_R_R__RC, A5F_INSN_MOV_L_R_R__RC, A5F_SFMT_MOV_L_R_R__RC },
+ { ARC_INSN_MOV_CC__RC, A5F_INSN_MOV_CC__RC, A5F_SFMT_MOV_CC__RC },
+ { ARC_INSN_MOV_S_MCAH, A5F_INSN_MOV_S_MCAH, A5F_SFMT_MOV_S_MCAH },
+ { ARC_INSN_MOV_S_MCAHB, A5F_INSN_MOV_S_MCAHB, A5F_SFMT_MOV_S_MCAHB },
+ { ARC_INSN_MOV_S_R_U7, A5F_INSN_MOV_S_R_U7, A5F_SFMT_MOV_S_R_U7 },
+ { ARC_INSN_TST_L_S12_, A5F_INSN_TST_L_S12_, A5F_SFMT_TST_L_S12_ },
+ { ARC_INSN_TST_CCU6_, A5F_INSN_TST_CCU6_, A5F_SFMT_TST_CCU6_ },
+ { ARC_INSN_TST_L_U6_, A5F_INSN_TST_L_U6_, A5F_SFMT_TST_L_U6_ },
+ { ARC_INSN_TST_L_R_R__RC, A5F_INSN_TST_L_R_R__RC, A5F_SFMT_TST_L_R_R__RC },
+ { ARC_INSN_TST_CC__RC, A5F_INSN_TST_CC__RC, A5F_SFMT_TST_CC__RC },
+ { ARC_INSN_TST_S_GO, A5F_INSN_TST_S_GO, A5F_SFMT_TST_S_GO },
+ { ARC_INSN_CMP_L_S12_, A5F_INSN_CMP_L_S12_, A5F_SFMT_CMP_L_S12_ },
+ { ARC_INSN_CMP_CCU6_, A5F_INSN_CMP_CCU6_, A5F_SFMT_CMP_CCU6_ },
+ { ARC_INSN_CMP_L_U6_, A5F_INSN_CMP_L_U6_, A5F_SFMT_CMP_L_U6_ },
+ { ARC_INSN_CMP_L_R_R__RC, A5F_INSN_CMP_L_R_R__RC, A5F_SFMT_CMP_L_R_R__RC },
+ { ARC_INSN_CMP_CC__RC, A5F_INSN_CMP_CC__RC, A5F_SFMT_CMP_CC__RC },
+ { ARC_INSN_CMP_S_MCAH, A5F_INSN_CMP_S_MCAH, A5F_SFMT_CMP_S_MCAH },
+ { ARC_INSN_CMP_S_R_U7, A5F_INSN_CMP_S_R_U7, A5F_SFMT_CMP_S_R_U7 },
+ { ARC_INSN_RCMP_L_S12_, A5F_INSN_RCMP_L_S12_, A5F_SFMT_CMP_L_S12_ },
+ { ARC_INSN_RCMP_CCU6_, A5F_INSN_RCMP_CCU6_, A5F_SFMT_CMP_CCU6_ },
+ { ARC_INSN_RCMP_L_U6_, A5F_INSN_RCMP_L_U6_, A5F_SFMT_CMP_L_U6_ },
+ { ARC_INSN_RCMP_L_R_R__RC, A5F_INSN_RCMP_L_R_R__RC, A5F_SFMT_CMP_L_R_R__RC },
+ { ARC_INSN_RCMP_CC__RC, A5F_INSN_RCMP_CC__RC, A5F_SFMT_CMP_CC__RC },
+ { ARC_INSN_RSUB_L_S12__RA_, A5F_INSN_RSUB_L_S12__RA_, A5F_SFMT_ADD_L_S12__RA_ },
+ { ARC_INSN_RSUB_CCU6__RA_, A5F_INSN_RSUB_CCU6__RA_, A5F_SFMT_ADD_CCU6__RA_ },
+ { ARC_INSN_RSUB_L_U6__RA_, A5F_INSN_RSUB_L_U6__RA_, A5F_SFMT_ADD_L_U6__RA_ },
+ { ARC_INSN_RSUB_L_R_R__RA__RC, A5F_INSN_RSUB_L_R_R__RA__RC, A5F_SFMT_ADD_L_R_R__RA__RC },
+ { ARC_INSN_RSUB_CC__RA__RC, A5F_INSN_RSUB_CC__RA__RC, A5F_SFMT_ADD_CC__RA__RC },
+ { ARC_INSN_BSET_L_S12__RA_, A5F_INSN_BSET_L_S12__RA_, A5F_SFMT_AND_L_S12__RA_ },
+ { ARC_INSN_BSET_CCU6__RA_, A5F_INSN_BSET_CCU6__RA_, A5F_SFMT_AND_CCU6__RA_ },
+ { ARC_INSN_BSET_L_U6__RA_, A5F_INSN_BSET_L_U6__RA_, A5F_SFMT_AND_L_U6__RA_ },
+ { ARC_INSN_BSET_L_R_R__RA__RC, A5F_INSN_BSET_L_R_R__RA__RC, A5F_SFMT_AND_L_R_R__RA__RC },
+ { ARC_INSN_BSET_CC__RA__RC, A5F_INSN_BSET_CC__RA__RC, A5F_SFMT_AND_CC__RA__RC },
+ { ARC_INSN_BSET_S_SSB, A5F_INSN_BSET_S_SSB, A5F_SFMT_SUB_S_SSB },
+ { ARC_INSN_BCLR_L_S12__RA_, A5F_INSN_BCLR_L_S12__RA_, A5F_SFMT_AND_L_S12__RA_ },
+ { ARC_INSN_BCLR_CCU6__RA_, A5F_INSN_BCLR_CCU6__RA_, A5F_SFMT_AND_CCU6__RA_ },
+ { ARC_INSN_BCLR_L_U6__RA_, A5F_INSN_BCLR_L_U6__RA_, A5F_SFMT_AND_L_U6__RA_ },
+ { ARC_INSN_BCLR_L_R_R__RA__RC, A5F_INSN_BCLR_L_R_R__RA__RC, A5F_SFMT_AND_L_R_R__RA__RC },
+ { ARC_INSN_BCLR_CC__RA__RC, A5F_INSN_BCLR_CC__RA__RC, A5F_SFMT_AND_CC__RA__RC },
+ { ARC_INSN_BCLR_S_SSB, A5F_INSN_BCLR_S_SSB, A5F_SFMT_SUB_S_SSB },
+ { ARC_INSN_BTST_L_S12_, A5F_INSN_BTST_L_S12_, A5F_SFMT_TST_L_S12_ },
+ { ARC_INSN_BTST_CCU6_, A5F_INSN_BTST_CCU6_, A5F_SFMT_TST_CCU6_ },
+ { ARC_INSN_BTST_L_U6_, A5F_INSN_BTST_L_U6_, A5F_SFMT_TST_L_U6_ },
+ { ARC_INSN_BTST_L_R_R__RC, A5F_INSN_BTST_L_R_R__RC, A5F_SFMT_TST_L_R_R__RC },
+ { ARC_INSN_BTST_CC__RC, A5F_INSN_BTST_CC__RC, A5F_SFMT_TST_CC__RC },
+ { ARC_INSN_BTST_S_SSB, A5F_INSN_BTST_S_SSB, A5F_SFMT_BTST_S_SSB },
+ { ARC_INSN_BXOR_L_S12__RA_, A5F_INSN_BXOR_L_S12__RA_, A5F_SFMT_AND_L_S12__RA_ },
+ { ARC_INSN_BXOR_CCU6__RA_, A5F_INSN_BXOR_CCU6__RA_, A5F_SFMT_AND_CCU6__RA_ },
+ { ARC_INSN_BXOR_L_U6__RA_, A5F_INSN_BXOR_L_U6__RA_, A5F_SFMT_AND_L_U6__RA_ },
+ { ARC_INSN_BXOR_L_R_R__RA__RC, A5F_INSN_BXOR_L_R_R__RA__RC, A5F_SFMT_AND_L_R_R__RA__RC },
+ { ARC_INSN_BXOR_CC__RA__RC, A5F_INSN_BXOR_CC__RA__RC, A5F_SFMT_AND_CC__RA__RC },
+ { ARC_INSN_BMSK_L_S12__RA_, A5F_INSN_BMSK_L_S12__RA_, A5F_SFMT_AND_L_S12__RA_ },
+ { ARC_INSN_BMSK_CCU6__RA_, A5F_INSN_BMSK_CCU6__RA_, A5F_SFMT_AND_CCU6__RA_ },
+ { ARC_INSN_BMSK_L_U6__RA_, A5F_INSN_BMSK_L_U6__RA_, A5F_SFMT_AND_L_U6__RA_ },
+ { ARC_INSN_BMSK_L_R_R__RA__RC, A5F_INSN_BMSK_L_R_R__RA__RC, A5F_SFMT_AND_L_R_R__RA__RC },
+ { ARC_INSN_BMSK_CC__RA__RC, A5F_INSN_BMSK_CC__RA__RC, A5F_SFMT_AND_CC__RA__RC },
+ { ARC_INSN_BMSK_S_SSB, A5F_INSN_BMSK_S_SSB, A5F_SFMT_SUB_S_SSB },
+ { ARC_INSN_ADD1_L_S12__RA_, A5F_INSN_ADD1_L_S12__RA_, A5F_SFMT_ADD_L_S12__RA_ },
+ { ARC_INSN_ADD1_CCU6__RA_, A5F_INSN_ADD1_CCU6__RA_, A5F_SFMT_ADD_CCU6__RA_ },
+ { ARC_INSN_ADD1_L_U6__RA_, A5F_INSN_ADD1_L_U6__RA_, A5F_SFMT_ADD_L_U6__RA_ },
+ { ARC_INSN_ADD1_L_R_R__RA__RC, A5F_INSN_ADD1_L_R_R__RA__RC, A5F_SFMT_ADD_L_R_R__RA__RC },
+ { ARC_INSN_ADD1_CC__RA__RC, A5F_INSN_ADD1_CC__RA__RC, A5F_SFMT_ADD_CC__RA__RC },
+ { ARC_INSN_I16_GO_ADD1_S_GO, A5F_INSN_I16_GO_ADD1_S_GO, A5F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_ADD2_L_S12__RA_, A5F_INSN_ADD2_L_S12__RA_, A5F_SFMT_ADD_L_S12__RA_ },
+ { ARC_INSN_ADD2_CCU6__RA_, A5F_INSN_ADD2_CCU6__RA_, A5F_SFMT_ADD_CCU6__RA_ },
+ { ARC_INSN_ADD2_L_U6__RA_, A5F_INSN_ADD2_L_U6__RA_, A5F_SFMT_ADD_L_U6__RA_ },
+ { ARC_INSN_ADD2_L_R_R__RA__RC, A5F_INSN_ADD2_L_R_R__RA__RC, A5F_SFMT_ADD_L_R_R__RA__RC },
+ { ARC_INSN_ADD2_CC__RA__RC, A5F_INSN_ADD2_CC__RA__RC, A5F_SFMT_ADD_CC__RA__RC },
+ { ARC_INSN_I16_GO_ADD2_S_GO, A5F_INSN_I16_GO_ADD2_S_GO, A5F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_ADD3_L_S12__RA_, A5F_INSN_ADD3_L_S12__RA_, A5F_SFMT_ADD_L_S12__RA_ },
+ { ARC_INSN_ADD3_CCU6__RA_, A5F_INSN_ADD3_CCU6__RA_, A5F_SFMT_ADD_CCU6__RA_ },
+ { ARC_INSN_ADD3_L_U6__RA_, A5F_INSN_ADD3_L_U6__RA_, A5F_SFMT_ADD_L_U6__RA_ },
+ { ARC_INSN_ADD3_L_R_R__RA__RC, A5F_INSN_ADD3_L_R_R__RA__RC, A5F_SFMT_ADD_L_R_R__RA__RC },
+ { ARC_INSN_ADD3_CC__RA__RC, A5F_INSN_ADD3_CC__RA__RC, A5F_SFMT_ADD_CC__RA__RC },
+ { ARC_INSN_I16_GO_ADD3_S_GO, A5F_INSN_I16_GO_ADD3_S_GO, A5F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_SUB1_L_S12__RA_, A5F_INSN_SUB1_L_S12__RA_, A5F_SFMT_ADD_L_S12__RA_ },
+ { ARC_INSN_SUB1_CCU6__RA_, A5F_INSN_SUB1_CCU6__RA_, A5F_SFMT_ADD_CCU6__RA_ },
+ { ARC_INSN_SUB1_L_U6__RA_, A5F_INSN_SUB1_L_U6__RA_, A5F_SFMT_ADD_L_U6__RA_ },
+ { ARC_INSN_SUB1_L_R_R__RA__RC, A5F_INSN_SUB1_L_R_R__RA__RC, A5F_SFMT_ADD_L_R_R__RA__RC },
+ { ARC_INSN_SUB1_CC__RA__RC, A5F_INSN_SUB1_CC__RA__RC, A5F_SFMT_ADD_CC__RA__RC },
+ { ARC_INSN_SUB2_L_S12__RA_, A5F_INSN_SUB2_L_S12__RA_, A5F_SFMT_ADD_L_S12__RA_ },
+ { ARC_INSN_SUB2_CCU6__RA_, A5F_INSN_SUB2_CCU6__RA_, A5F_SFMT_ADD_CCU6__RA_ },
+ { ARC_INSN_SUB2_L_U6__RA_, A5F_INSN_SUB2_L_U6__RA_, A5F_SFMT_ADD_L_U6__RA_ },
+ { ARC_INSN_SUB2_L_R_R__RA__RC, A5F_INSN_SUB2_L_R_R__RA__RC, A5F_SFMT_ADD_L_R_R__RA__RC },
+ { ARC_INSN_SUB2_CC__RA__RC, A5F_INSN_SUB2_CC__RA__RC, A5F_SFMT_ADD_CC__RA__RC },
+ { ARC_INSN_SUB3_L_S12__RA_, A5F_INSN_SUB3_L_S12__RA_, A5F_SFMT_ADD_L_S12__RA_ },
+ { ARC_INSN_SUB3_CCU6__RA_, A5F_INSN_SUB3_CCU6__RA_, A5F_SFMT_ADD_CCU6__RA_ },
+ { ARC_INSN_SUB3_L_U6__RA_, A5F_INSN_SUB3_L_U6__RA_, A5F_SFMT_ADD_L_U6__RA_ },
+ { ARC_INSN_SUB3_L_R_R__RA__RC, A5F_INSN_SUB3_L_R_R__RA__RC, A5F_SFMT_ADD_L_R_R__RA__RC },
+ { ARC_INSN_SUB3_CC__RA__RC, A5F_INSN_SUB3_CC__RA__RC, A5F_SFMT_ADD_CC__RA__RC },
+ { ARC_INSN_MPY_L_S12__RA_, A5F_INSN_MPY_L_S12__RA_, A5F_SFMT_MPY_L_S12__RA_ },
+ { ARC_INSN_MPY_CCU6__RA_, A5F_INSN_MPY_CCU6__RA_, A5F_SFMT_MPY_CCU6__RA_ },
+ { ARC_INSN_MPY_L_U6__RA_, A5F_INSN_MPY_L_U6__RA_, A5F_SFMT_MPY_L_U6__RA_ },
+ { ARC_INSN_MPY_L_R_R__RA__RC, A5F_INSN_MPY_L_R_R__RA__RC, A5F_SFMT_MPY_L_R_R__RA__RC },
+ { ARC_INSN_MPY_CC__RA__RC, A5F_INSN_MPY_CC__RA__RC, A5F_SFMT_MPY_CC__RA__RC },
+ { ARC_INSN_MPYH_L_S12__RA_, A5F_INSN_MPYH_L_S12__RA_, A5F_SFMT_MPY_L_S12__RA_ },
+ { ARC_INSN_MPYH_CCU6__RA_, A5F_INSN_MPYH_CCU6__RA_, A5F_SFMT_MPY_CCU6__RA_ },
+ { ARC_INSN_MPYH_L_U6__RA_, A5F_INSN_MPYH_L_U6__RA_, A5F_SFMT_MPY_L_U6__RA_ },
+ { ARC_INSN_MPYH_L_R_R__RA__RC, A5F_INSN_MPYH_L_R_R__RA__RC, A5F_SFMT_MPY_L_R_R__RA__RC },
+ { ARC_INSN_MPYH_CC__RA__RC, A5F_INSN_MPYH_CC__RA__RC, A5F_SFMT_MPY_CC__RA__RC },
+ { ARC_INSN_MPYHU_L_S12__RA_, A5F_INSN_MPYHU_L_S12__RA_, A5F_SFMT_MPY_L_S12__RA_ },
+ { ARC_INSN_MPYHU_CCU6__RA_, A5F_INSN_MPYHU_CCU6__RA_, A5F_SFMT_MPY_CCU6__RA_ },
+ { ARC_INSN_MPYHU_L_U6__RA_, A5F_INSN_MPYHU_L_U6__RA_, A5F_SFMT_MPY_L_U6__RA_ },
+ { ARC_INSN_MPYHU_L_R_R__RA__RC, A5F_INSN_MPYHU_L_R_R__RA__RC, A5F_SFMT_MPY_L_R_R__RA__RC },
+ { ARC_INSN_MPYHU_CC__RA__RC, A5F_INSN_MPYHU_CC__RA__RC, A5F_SFMT_MPY_CC__RA__RC },
+ { ARC_INSN_MPYU_L_S12__RA_, A5F_INSN_MPYU_L_S12__RA_, A5F_SFMT_MPY_L_S12__RA_ },
+ { ARC_INSN_MPYU_CCU6__RA_, A5F_INSN_MPYU_CCU6__RA_, A5F_SFMT_MPY_CCU6__RA_ },
+ { ARC_INSN_MPYU_L_U6__RA_, A5F_INSN_MPYU_L_U6__RA_, A5F_SFMT_MPY_L_U6__RA_ },
+ { ARC_INSN_MPYU_L_R_R__RA__RC, A5F_INSN_MPYU_L_R_R__RA__RC, A5F_SFMT_MPY_L_R_R__RA__RC },
+ { ARC_INSN_MPYU_CC__RA__RC, A5F_INSN_MPYU_CC__RA__RC, A5F_SFMT_MPY_CC__RA__RC },
+ { ARC_INSN_J_L_R_R___RC_NOILINK_, A5F_INSN_J_L_R_R___RC_NOILINK_, A5F_SFMT_J_L_R_R___RC_NOILINK_ },
+ { ARC_INSN_J_CC___RC_NOILINK_, A5F_INSN_J_CC___RC_NOILINK_, A5F_SFMT_J_CC___RC_NOILINK_ },
+ { ARC_INSN_J_L_R_R___RC_ILINK_, A5F_INSN_J_L_R_R___RC_ILINK_, A5F_SFMT_J_L_R_R___RC_ILINK_ },
+ { ARC_INSN_J_CC___RC_ILINK_, A5F_INSN_J_CC___RC_ILINK_, A5F_SFMT_J_CC___RC_ILINK_ },
+ { ARC_INSN_J_L_S12_, A5F_INSN_J_L_S12_, A5F_SFMT_J_L_S12_ },
+ { ARC_INSN_J_CCU6_, A5F_INSN_J_CCU6_, A5F_SFMT_J_CCU6_ },
+ { ARC_INSN_J_L_U6_, A5F_INSN_J_L_U6_, A5F_SFMT_J_L_U6_ },
+ { ARC_INSN_J_S, A5F_INSN_J_S, A5F_SFMT_J_S },
+ { ARC_INSN_J_S__S, A5F_INSN_J_S__S, A5F_SFMT_J_S__S },
+ { ARC_INSN_J_SEQ__S, A5F_INSN_J_SEQ__S, A5F_SFMT_J_SEQ__S },
+ { ARC_INSN_J_SNE__S, A5F_INSN_J_SNE__S, A5F_SFMT_J_SEQ__S },
+ { ARC_INSN_J_L_S12_D_, A5F_INSN_J_L_S12_D_, A5F_SFMT_J_L_S12_D_ },
+ { ARC_INSN_J_CCU6_D_, A5F_INSN_J_CCU6_D_, A5F_SFMT_J_CCU6_D_ },
+ { ARC_INSN_J_L_U6_D_, A5F_INSN_J_L_U6_D_, A5F_SFMT_J_L_U6_D_ },
+ { ARC_INSN_J_L_R_R_D___RC_, A5F_INSN_J_L_R_R_D___RC_, A5F_SFMT_J_L_R_R_D___RC_ },
+ { ARC_INSN_J_CC_D___RC_, A5F_INSN_J_CC_D___RC_, A5F_SFMT_J_CC_D___RC_ },
+ { ARC_INSN_J_S_D, A5F_INSN_J_S_D, A5F_SFMT_J_S },
+ { ARC_INSN_J_S__S_D, A5F_INSN_J_S__S_D, A5F_SFMT_J_S__S },
+ { ARC_INSN_JL_L_S12_, A5F_INSN_JL_L_S12_, A5F_SFMT_JL_L_S12_ },
+ { ARC_INSN_JL_CCU6_, A5F_INSN_JL_CCU6_, A5F_SFMT_JL_CCU6_ },
+ { ARC_INSN_JL_L_U6_, A5F_INSN_JL_L_U6_, A5F_SFMT_JL_L_U6_ },
+ { ARC_INSN_JL_S, A5F_INSN_JL_S, A5F_SFMT_JL_S },
+ { ARC_INSN_JL_L_R_R___RC_NOILINK_, A5F_INSN_JL_L_R_R___RC_NOILINK_, A5F_SFMT_JL_L_R_R___RC_NOILINK_ },
+ { ARC_INSN_JL_CC___RC_NOILINK_, A5F_INSN_JL_CC___RC_NOILINK_, A5F_SFMT_JL_CC___RC_NOILINK_ },
+ { ARC_INSN_JL_L_S12_D_, A5F_INSN_JL_L_S12_D_, A5F_SFMT_JL_L_S12_ },
+ { ARC_INSN_JL_CCU6_D_, A5F_INSN_JL_CCU6_D_, A5F_SFMT_JL_CCU6_ },
+ { ARC_INSN_JL_L_U6_D_, A5F_INSN_JL_L_U6_D_, A5F_SFMT_JL_L_U6_ },
+ { ARC_INSN_JL_L_R_R_D___RC_, A5F_INSN_JL_L_R_R_D___RC_, A5F_SFMT_JL_L_R_R_D___RC_ },
+ { ARC_INSN_JL_CC_D___RC_, A5F_INSN_JL_CC_D___RC_, A5F_SFMT_JL_CC_D___RC_ },
+ { ARC_INSN_JL_S_D, A5F_INSN_JL_S_D, A5F_SFMT_JL_S_D },
+ { ARC_INSN_LP_L_S12_, A5F_INSN_LP_L_S12_, A5F_SFMT_LP_L_S12_ },
+ { ARC_INSN_LPCC_CCU6, A5F_INSN_LPCC_CCU6, A5F_SFMT_LPCC_CCU6 },
+ { ARC_INSN_FLAG_L_S12_, A5F_INSN_FLAG_L_S12_, A5F_SFMT_FLAG_L_S12_ },
+ { ARC_INSN_FLAG_CCU6_, A5F_INSN_FLAG_CCU6_, A5F_SFMT_FLAG_CCU6_ },
+ { ARC_INSN_FLAG_L_U6_, A5F_INSN_FLAG_L_U6_, A5F_SFMT_FLAG_L_U6_ },
+ { ARC_INSN_FLAG_L_R_R__RC, A5F_INSN_FLAG_L_R_R__RC, A5F_SFMT_FLAG_L_R_R__RC },
+ { ARC_INSN_FLAG_CC__RC, A5F_INSN_FLAG_CC__RC, A5F_SFMT_FLAG_CC__RC },
+ { ARC_INSN_LR_L_R_R___RC_, A5F_INSN_LR_L_R_R___RC_, A5F_SFMT_LR_L_R_R___RC_ },
+ { ARC_INSN_LR_L_S12_, A5F_INSN_LR_L_S12_, A5F_SFMT_LR_L_S12_ },
+ { ARC_INSN_LR_L_U6_, A5F_INSN_LR_L_U6_, A5F_SFMT_LR_L_U6_ },
+ { ARC_INSN_SR_L_R_R___RC_, A5F_INSN_SR_L_R_R___RC_, A5F_SFMT_SR_L_R_R___RC_ },
+ { ARC_INSN_SR_L_S12_, A5F_INSN_SR_L_S12_, A5F_SFMT_SR_L_S12_ },
+ { ARC_INSN_SR_L_U6_, A5F_INSN_SR_L_U6_, A5F_SFMT_SR_L_U6_ },
+ { ARC_INSN_ASL_L_R_R__RC, A5F_INSN_ASL_L_R_R__RC, A5F_SFMT_ASL_L_R_R__RC },
+ { ARC_INSN_ASL_L_U6_, A5F_INSN_ASL_L_U6_, A5F_SFMT_ASL_L_U6_ },
+ { ARC_INSN_I16_GO_ASL_S_GO, A5F_INSN_I16_GO_ASL_S_GO, A5F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_ASR_L_R_R__RC, A5F_INSN_ASR_L_R_R__RC, A5F_SFMT_ASR_L_R_R__RC },
+ { ARC_INSN_ASR_L_U6_, A5F_INSN_ASR_L_U6_, A5F_SFMT_ASR_L_U6_ },
+ { ARC_INSN_I16_GO_ASR_S_GO, A5F_INSN_I16_GO_ASR_S_GO, A5F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_LSR_L_R_R__RC, A5F_INSN_LSR_L_R_R__RC, A5F_SFMT_ASR_L_R_R__RC },
+ { ARC_INSN_LSR_L_U6_, A5F_INSN_LSR_L_U6_, A5F_SFMT_ASR_L_U6_ },
+ { ARC_INSN_I16_GO_LSR_S_GO, A5F_INSN_I16_GO_LSR_S_GO, A5F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_ROR_L_R_R__RC, A5F_INSN_ROR_L_R_R__RC, A5F_SFMT_ASR_L_R_R__RC },
+ { ARC_INSN_ROR_L_U6_, A5F_INSN_ROR_L_U6_, A5F_SFMT_ASR_L_U6_ },
+ { ARC_INSN_RRC_L_R_R__RC, A5F_INSN_RRC_L_R_R__RC, A5F_SFMT_RRC_L_R_R__RC },
+ { ARC_INSN_RRC_L_U6_, A5F_INSN_RRC_L_U6_, A5F_SFMT_RRC_L_U6_ },
+ { ARC_INSN_SEXB_L_R_R__RC, A5F_INSN_SEXB_L_R_R__RC, A5F_SFMT_SEXB_L_R_R__RC },
+ { ARC_INSN_SEXB_L_U6_, A5F_INSN_SEXB_L_U6_, A5F_SFMT_SEXB_L_U6_ },
+ { ARC_INSN_I16_GO_SEXB_S_GO, A5F_INSN_I16_GO_SEXB_S_GO, A5F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_SEXW_L_R_R__RC, A5F_INSN_SEXW_L_R_R__RC, A5F_SFMT_SEXW_L_R_R__RC },
+ { ARC_INSN_SEXW_L_U6_, A5F_INSN_SEXW_L_U6_, A5F_SFMT_SEXW_L_U6_ },
+ { ARC_INSN_I16_GO_SEXW_S_GO, A5F_INSN_I16_GO_SEXW_S_GO, A5F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_EXTB_L_R_R__RC, A5F_INSN_EXTB_L_R_R__RC, A5F_SFMT_SEXB_L_R_R__RC },
+ { ARC_INSN_EXTB_L_U6_, A5F_INSN_EXTB_L_U6_, A5F_SFMT_SEXB_L_U6_ },
+ { ARC_INSN_I16_GO_EXTB_S_GO, A5F_INSN_I16_GO_EXTB_S_GO, A5F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_EXTW_L_R_R__RC, A5F_INSN_EXTW_L_R_R__RC, A5F_SFMT_SEXW_L_R_R__RC },
+ { ARC_INSN_EXTW_L_U6_, A5F_INSN_EXTW_L_U6_, A5F_SFMT_SEXW_L_U6_ },
+ { ARC_INSN_I16_GO_EXTW_S_GO, A5F_INSN_I16_GO_EXTW_S_GO, A5F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_ABS_L_R_R__RC, A5F_INSN_ABS_L_R_R__RC, A5F_SFMT_ABS_L_R_R__RC },
+ { ARC_INSN_ABS_L_U6_, A5F_INSN_ABS_L_U6_, A5F_SFMT_ABS_L_U6_ },
+ { ARC_INSN_I16_GO_ABS_S_GO, A5F_INSN_I16_GO_ABS_S_GO, A5F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_NOT_L_R_R__RC, A5F_INSN_NOT_L_R_R__RC, A5F_SFMT_NOT_L_R_R__RC },
+ { ARC_INSN_NOT_L_U6_, A5F_INSN_NOT_L_U6_, A5F_SFMT_NOT_L_U6_ },
+ { ARC_INSN_I16_GO_NOT_S_GO, A5F_INSN_I16_GO_NOT_S_GO, A5F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_RLC_L_R_R__RC, A5F_INSN_RLC_L_R_R__RC, A5F_SFMT_RRC_L_R_R__RC },
+ { ARC_INSN_RLC_L_U6_, A5F_INSN_RLC_L_U6_, A5F_SFMT_RRC_L_U6_ },
+ { ARC_INSN_I16_GO_NEG_S_GO, A5F_INSN_I16_GO_NEG_S_GO, A5F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_SWI, A5F_INSN_SWI, A5F_SFMT_SWI },
+ { ARC_INSN_TRAP_S, A5F_INSN_TRAP_S, A5F_SFMT_TRAP_S },
+ { ARC_INSN_BRK, A5F_INSN_BRK, A5F_SFMT_BRK },
+ { ARC_INSN_BRK_S, A5F_INSN_BRK_S, A5F_SFMT_BRK },
+ { ARC_INSN_ASL_L_S12__RA_, A5F_INSN_ASL_L_S12__RA_, A5F_SFMT_ASL_L_S12__RA_ },
+ { ARC_INSN_ASL_CCU6__RA_, A5F_INSN_ASL_CCU6__RA_, A5F_SFMT_ASL_CCU6__RA_ },
+ { ARC_INSN_ASL_L_U6__RA_, A5F_INSN_ASL_L_U6__RA_, A5F_SFMT_ASL_L_U6__RA_ },
+ { ARC_INSN_ASL_L_R_R__RA__RC, A5F_INSN_ASL_L_R_R__RA__RC, A5F_SFMT_ASL_L_R_R__RA__RC },
+ { ARC_INSN_ASL_CC__RA__RC, A5F_INSN_ASL_CC__RA__RC, A5F_SFMT_ASL_CC__RA__RC },
+ { ARC_INSN_ASL_S_CBU3, A5F_INSN_ASL_S_CBU3, A5F_SFMT_ADD_S_CBU3 },
+ { ARC_INSN_ASL_S_SSB, A5F_INSN_ASL_S_SSB, A5F_SFMT_SUB_S_SSB },
+ { ARC_INSN_I16_GO_ASLM_S_GO, A5F_INSN_I16_GO_ASLM_S_GO, A5F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_LSR_L_S12__RA_, A5F_INSN_LSR_L_S12__RA_, A5F_SFMT_ASL_L_S12__RA_ },
+ { ARC_INSN_LSR_CCU6__RA_, A5F_INSN_LSR_CCU6__RA_, A5F_SFMT_ASL_CCU6__RA_ },
+ { ARC_INSN_LSR_L_U6__RA_, A5F_INSN_LSR_L_U6__RA_, A5F_SFMT_ASL_L_U6__RA_ },
+ { ARC_INSN_LSR_L_R_R__RA__RC, A5F_INSN_LSR_L_R_R__RA__RC, A5F_SFMT_ASL_L_R_R__RA__RC },
+ { ARC_INSN_LSR_CC__RA__RC, A5F_INSN_LSR_CC__RA__RC, A5F_SFMT_ASL_CC__RA__RC },
+ { ARC_INSN_LSR_S_SSB, A5F_INSN_LSR_S_SSB, A5F_SFMT_SUB_S_SSB },
+ { ARC_INSN_I16_GO_LSRM_S_GO, A5F_INSN_I16_GO_LSRM_S_GO, A5F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_ASR_L_S12__RA_, A5F_INSN_ASR_L_S12__RA_, A5F_SFMT_ASL_L_S12__RA_ },
+ { ARC_INSN_ASR_CCU6__RA_, A5F_INSN_ASR_CCU6__RA_, A5F_SFMT_ASL_CCU6__RA_ },
+ { ARC_INSN_ASR_L_U6__RA_, A5F_INSN_ASR_L_U6__RA_, A5F_SFMT_ASL_L_U6__RA_ },
+ { ARC_INSN_ASR_L_R_R__RA__RC, A5F_INSN_ASR_L_R_R__RA__RC, A5F_SFMT_ASL_L_R_R__RA__RC },
+ { ARC_INSN_ASR_CC__RA__RC, A5F_INSN_ASR_CC__RA__RC, A5F_SFMT_ASL_CC__RA__RC },
+ { ARC_INSN_ASR_S_CBU3, A5F_INSN_ASR_S_CBU3, A5F_SFMT_ADD_S_CBU3 },
+ { ARC_INSN_ASR_S_SSB, A5F_INSN_ASR_S_SSB, A5F_SFMT_SUB_S_SSB },
+ { ARC_INSN_I16_GO_ASRM_S_GO, A5F_INSN_I16_GO_ASRM_S_GO, A5F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_ROR_L_S12__RA_, A5F_INSN_ROR_L_S12__RA_, A5F_SFMT_ASL_L_S12__RA_ },
+ { ARC_INSN_ROR_CCU6__RA_, A5F_INSN_ROR_CCU6__RA_, A5F_SFMT_ASL_CCU6__RA_ },
+ { ARC_INSN_ROR_L_U6__RA_, A5F_INSN_ROR_L_U6__RA_, A5F_SFMT_ASL_L_U6__RA_ },
+ { ARC_INSN_ROR_L_R_R__RA__RC, A5F_INSN_ROR_L_R_R__RA__RC, A5F_SFMT_ASL_L_R_R__RA__RC },
+ { ARC_INSN_ROR_CC__RA__RC, A5F_INSN_ROR_CC__RA__RC, A5F_SFMT_ASL_CC__RA__RC },
+ { ARC_INSN_MUL64_L_S12_, A5F_INSN_MUL64_L_S12_, A5F_SFMT_MUL64_L_S12_ },
+ { ARC_INSN_MUL64_CCU6_, A5F_INSN_MUL64_CCU6_, A5F_SFMT_MUL64_CCU6_ },
+ { ARC_INSN_MUL64_L_U6_, A5F_INSN_MUL64_L_U6_, A5F_SFMT_MUL64_L_U6_ },
+ { ARC_INSN_MUL64_L_R_R__RC, A5F_INSN_MUL64_L_R_R__RC, A5F_SFMT_MUL64_L_R_R__RC },
+ { ARC_INSN_MUL64_CC__RC, A5F_INSN_MUL64_CC__RC, A5F_SFMT_MUL64_CC__RC },
+ { ARC_INSN_MUL64_S_GO, A5F_INSN_MUL64_S_GO, A5F_SFMT_MUL64_S_GO },
+ { ARC_INSN_MULU64_L_S12_, A5F_INSN_MULU64_L_S12_, A5F_SFMT_MUL64_L_S12_ },
+ { ARC_INSN_MULU64_CCU6_, A5F_INSN_MULU64_CCU6_, A5F_SFMT_MUL64_CCU6_ },
+ { ARC_INSN_MULU64_L_U6_, A5F_INSN_MULU64_L_U6_, A5F_SFMT_MUL64_L_U6_ },
+ { ARC_INSN_MULU64_L_R_R__RC, A5F_INSN_MULU64_L_R_R__RC, A5F_SFMT_MUL64_L_R_R__RC },
+ { ARC_INSN_MULU64_CC__RC, A5F_INSN_MULU64_CC__RC, A5F_SFMT_MUL64_CC__RC },
+ { ARC_INSN_ADDS_L_S12__RA_, A5F_INSN_ADDS_L_S12__RA_, A5F_SFMT_ADDS_L_S12__RA_ },
+ { ARC_INSN_ADDS_CCU6__RA_, A5F_INSN_ADDS_CCU6__RA_, A5F_SFMT_ADDS_CCU6__RA_ },
+ { ARC_INSN_ADDS_L_U6__RA_, A5F_INSN_ADDS_L_U6__RA_, A5F_SFMT_ADDS_L_U6__RA_ },
+ { ARC_INSN_ADDS_L_R_R__RA__RC, A5F_INSN_ADDS_L_R_R__RA__RC, A5F_SFMT_ADDS_L_R_R__RA__RC },
+ { ARC_INSN_ADDS_CC__RA__RC, A5F_INSN_ADDS_CC__RA__RC, A5F_SFMT_ADDS_CC__RA__RC },
+ { ARC_INSN_SUBS_L_S12__RA_, A5F_INSN_SUBS_L_S12__RA_, A5F_SFMT_ADDS_L_S12__RA_ },
+ { ARC_INSN_SUBS_CCU6__RA_, A5F_INSN_SUBS_CCU6__RA_, A5F_SFMT_ADDS_CCU6__RA_ },
+ { ARC_INSN_SUBS_L_U6__RA_, A5F_INSN_SUBS_L_U6__RA_, A5F_SFMT_ADDS_L_U6__RA_ },
+ { ARC_INSN_SUBS_L_R_R__RA__RC, A5F_INSN_SUBS_L_R_R__RA__RC, A5F_SFMT_ADDS_L_R_R__RA__RC },
+ { ARC_INSN_SUBS_CC__RA__RC, A5F_INSN_SUBS_CC__RA__RC, A5F_SFMT_ADDS_CC__RA__RC },
+ { ARC_INSN_DIVAW_L_S12__RA_, A5F_INSN_DIVAW_L_S12__RA_, A5F_SFMT_DIVAW_L_S12__RA_ },
+ { ARC_INSN_DIVAW_CCU6__RA_, A5F_INSN_DIVAW_CCU6__RA_, A5F_SFMT_DIVAW_CCU6__RA_ },
+ { ARC_INSN_DIVAW_L_U6__RA_, A5F_INSN_DIVAW_L_U6__RA_, A5F_SFMT_DIVAW_L_U6__RA_ },
+ { ARC_INSN_DIVAW_L_R_R__RA__RC, A5F_INSN_DIVAW_L_R_R__RA__RC, A5F_SFMT_DIVAW_L_R_R__RA__RC },
+ { ARC_INSN_DIVAW_CC__RA__RC, A5F_INSN_DIVAW_CC__RA__RC, A5F_SFMT_DIVAW_CC__RA__RC },
+ { ARC_INSN_ASLS_L_S12__RA_, A5F_INSN_ASLS_L_S12__RA_, A5F_SFMT_ASLS_L_S12__RA_ },
+ { ARC_INSN_ASLS_CCU6__RA_, A5F_INSN_ASLS_CCU6__RA_, A5F_SFMT_ASLS_CCU6__RA_ },
+ { ARC_INSN_ASLS_L_U6__RA_, A5F_INSN_ASLS_L_U6__RA_, A5F_SFMT_ASLS_L_U6__RA_ },
+ { ARC_INSN_ASLS_L_R_R__RA__RC, A5F_INSN_ASLS_L_R_R__RA__RC, A5F_SFMT_ASLS_L_R_R__RA__RC },
+ { ARC_INSN_ASLS_CC__RA__RC, A5F_INSN_ASLS_CC__RA__RC, A5F_SFMT_ASLS_CC__RA__RC },
+ { ARC_INSN_ASRS_L_S12__RA_, A5F_INSN_ASRS_L_S12__RA_, A5F_SFMT_ASLS_L_S12__RA_ },
+ { ARC_INSN_ASRS_CCU6__RA_, A5F_INSN_ASRS_CCU6__RA_, A5F_SFMT_ASLS_CCU6__RA_ },
+ { ARC_INSN_ASRS_L_U6__RA_, A5F_INSN_ASRS_L_U6__RA_, A5F_SFMT_ASLS_L_U6__RA_ },
+ { ARC_INSN_ASRS_L_R_R__RA__RC, A5F_INSN_ASRS_L_R_R__RA__RC, A5F_SFMT_ASLS_L_R_R__RA__RC },
+ { ARC_INSN_ASRS_CC__RA__RC, A5F_INSN_ASRS_CC__RA__RC, A5F_SFMT_ASLS_CC__RA__RC },
+ { ARC_INSN_ADDSDW_L_S12__RA_, A5F_INSN_ADDSDW_L_S12__RA_, A5F_SFMT_ASLS_L_S12__RA_ },
+ { ARC_INSN_ADDSDW_CCU6__RA_, A5F_INSN_ADDSDW_CCU6__RA_, A5F_SFMT_ASLS_CCU6__RA_ },
+ { ARC_INSN_ADDSDW_L_U6__RA_, A5F_INSN_ADDSDW_L_U6__RA_, A5F_SFMT_ASLS_L_U6__RA_ },
+ { ARC_INSN_ADDSDW_L_R_R__RA__RC, A5F_INSN_ADDSDW_L_R_R__RA__RC, A5F_SFMT_ASLS_L_R_R__RA__RC },
+ { ARC_INSN_ADDSDW_CC__RA__RC, A5F_INSN_ADDSDW_CC__RA__RC, A5F_SFMT_ASLS_CC__RA__RC },
+ { ARC_INSN_SUBSDW_L_S12__RA_, A5F_INSN_SUBSDW_L_S12__RA_, A5F_SFMT_ASLS_L_S12__RA_ },
+ { ARC_INSN_SUBSDW_CCU6__RA_, A5F_INSN_SUBSDW_CCU6__RA_, A5F_SFMT_ASLS_CCU6__RA_ },
+ { ARC_INSN_SUBSDW_L_U6__RA_, A5F_INSN_SUBSDW_L_U6__RA_, A5F_SFMT_ASLS_L_U6__RA_ },
+ { ARC_INSN_SUBSDW_L_R_R__RA__RC, A5F_INSN_SUBSDW_L_R_R__RA__RC, A5F_SFMT_ASLS_L_R_R__RA__RC },
+ { ARC_INSN_SUBSDW_CC__RA__RC, A5F_INSN_SUBSDW_CC__RA__RC, A5F_SFMT_ASLS_CC__RA__RC },
+ { ARC_INSN_SWAP_L_R_R__RC, A5F_INSN_SWAP_L_R_R__RC, A5F_SFMT_SWAP_L_R_R__RC },
+ { ARC_INSN_SWAP_L_U6_, A5F_INSN_SWAP_L_U6_, A5F_SFMT_SWAP_L_U6_ },
+ { ARC_INSN_NORM_L_R_R__RC, A5F_INSN_NORM_L_R_R__RC, A5F_SFMT_SWAP_L_R_R__RC },
+ { ARC_INSN_NORM_L_U6_, A5F_INSN_NORM_L_U6_, A5F_SFMT_NORM_L_U6_ },
+ { ARC_INSN_RND16_L_R_R__RC, A5F_INSN_RND16_L_R_R__RC, A5F_SFMT_RND16_L_R_R__RC },
+ { ARC_INSN_RND16_L_U6_, A5F_INSN_RND16_L_U6_, A5F_SFMT_RND16_L_U6_ },
+ { ARC_INSN_ABSSW_L_R_R__RC, A5F_INSN_ABSSW_L_R_R__RC, A5F_SFMT_ABSSW_L_R_R__RC },
+ { ARC_INSN_ABSSW_L_U6_, A5F_INSN_ABSSW_L_U6_, A5F_SFMT_ABSSW_L_U6_ },
+ { ARC_INSN_ABSS_L_R_R__RC, A5F_INSN_ABSS_L_R_R__RC, A5F_SFMT_RND16_L_R_R__RC },
+ { ARC_INSN_ABSS_L_U6_, A5F_INSN_ABSS_L_U6_, A5F_SFMT_ABSS_L_U6_ },
+ { ARC_INSN_NEGSW_L_R_R__RC, A5F_INSN_NEGSW_L_R_R__RC, A5F_SFMT_ABSSW_L_R_R__RC },
+ { ARC_INSN_NEGSW_L_U6_, A5F_INSN_NEGSW_L_U6_, A5F_SFMT_ABSSW_L_U6_ },
+ { ARC_INSN_NEGS_L_R_R__RC, A5F_INSN_NEGS_L_R_R__RC, A5F_SFMT_RND16_L_R_R__RC },
+ { ARC_INSN_NEGS_L_U6_, A5F_INSN_NEGS_L_U6_, A5F_SFMT_RND16_L_U6_ },
+ { ARC_INSN_NORMW_L_R_R__RC, A5F_INSN_NORMW_L_R_R__RC, A5F_SFMT_SWAP_L_R_R__RC },
+ { ARC_INSN_NORMW_L_U6_, A5F_INSN_NORMW_L_U6_, A5F_SFMT_SWAP_L_U6_ },
+ { ARC_INSN_NOP_S, A5F_INSN_NOP_S, A5F_SFMT_NOP_S },
+ { ARC_INSN_UNIMP_S, A5F_INSN_UNIMP_S, A5F_SFMT_NOP_S },
+ { ARC_INSN_POP_S_B, A5F_INSN_POP_S_B, A5F_SFMT_POP_S_B },
+ { ARC_INSN_POP_S_BLINK, A5F_INSN_POP_S_BLINK, A5F_SFMT_POP_S_BLINK },
+ { ARC_INSN_PUSH_S_B, A5F_INSN_PUSH_S_B, A5F_SFMT_PUSH_S_B },
+ { ARC_INSN_PUSH_S_BLINK, A5F_INSN_PUSH_S_BLINK, A5F_SFMT_PUSH_S_BLINK },
+ { ARC_INSN_MULLW_L_S12__RA_, A5F_INSN_MULLW_L_S12__RA_, A5F_SFMT_MULLW_L_S12__RA_ },
+ { ARC_INSN_MULLW_CCU6__RA_, A5F_INSN_MULLW_CCU6__RA_, A5F_SFMT_MULLW_CCU6__RA_ },
+ { ARC_INSN_MULLW_L_U6__RA_, A5F_INSN_MULLW_L_U6__RA_, A5F_SFMT_MULLW_L_U6__RA_ },
+ { ARC_INSN_MULLW_L_R_R__RA__RC, A5F_INSN_MULLW_L_R_R__RA__RC, A5F_SFMT_MULLW_L_R_R__RA__RC },
+ { ARC_INSN_MULLW_CC__RA__RC, A5F_INSN_MULLW_CC__RA__RC, A5F_SFMT_MULLW_CC__RA__RC },
+ { ARC_INSN_MACLW_L_S12__RA_, A5F_INSN_MACLW_L_S12__RA_, A5F_SFMT_MACLW_L_S12__RA_ },
+ { ARC_INSN_MACLW_CCU6__RA_, A5F_INSN_MACLW_CCU6__RA_, A5F_SFMT_MACLW_CCU6__RA_ },
+ { ARC_INSN_MACLW_L_U6__RA_, A5F_INSN_MACLW_L_U6__RA_, A5F_SFMT_MACLW_L_U6__RA_ },
+ { ARC_INSN_MACLW_L_R_R__RA__RC, A5F_INSN_MACLW_L_R_R__RA__RC, A5F_SFMT_MACLW_L_R_R__RA__RC },
+ { ARC_INSN_MACLW_CC__RA__RC, A5F_INSN_MACLW_CC__RA__RC, A5F_SFMT_MACLW_CC__RA__RC },
+ { ARC_INSN_MACHLW_L_S12__RA_, A5F_INSN_MACHLW_L_S12__RA_, A5F_SFMT_MACLW_L_S12__RA_ },
+ { ARC_INSN_MACHLW_CCU6__RA_, A5F_INSN_MACHLW_CCU6__RA_, A5F_SFMT_MACLW_CCU6__RA_ },
+ { ARC_INSN_MACHLW_L_U6__RA_, A5F_INSN_MACHLW_L_U6__RA_, A5F_SFMT_MACLW_L_U6__RA_ },
+ { ARC_INSN_MACHLW_L_R_R__RA__RC, A5F_INSN_MACHLW_L_R_R__RA__RC, A5F_SFMT_MACLW_L_R_R__RA__RC },
+ { ARC_INSN_MACHLW_CC__RA__RC, A5F_INSN_MACHLW_CC__RA__RC, A5F_SFMT_MACLW_CC__RA__RC },
+ { ARC_INSN_MULULW_L_S12__RA_, A5F_INSN_MULULW_L_S12__RA_, A5F_SFMT_MULLW_L_S12__RA_ },
+ { ARC_INSN_MULULW_CCU6__RA_, A5F_INSN_MULULW_CCU6__RA_, A5F_SFMT_MULLW_CCU6__RA_ },
+ { ARC_INSN_MULULW_L_U6__RA_, A5F_INSN_MULULW_L_U6__RA_, A5F_SFMT_MULLW_L_U6__RA_ },
+ { ARC_INSN_MULULW_L_R_R__RA__RC, A5F_INSN_MULULW_L_R_R__RA__RC, A5F_SFMT_MULLW_L_R_R__RA__RC },
+ { ARC_INSN_MULULW_CC__RA__RC, A5F_INSN_MULULW_CC__RA__RC, A5F_SFMT_MULLW_CC__RA__RC },
+ { ARC_INSN_MACHULW_L_S12__RA_, A5F_INSN_MACHULW_L_S12__RA_, A5F_SFMT_MACHULW_L_S12__RA_ },
+ { ARC_INSN_MACHULW_CCU6__RA_, A5F_INSN_MACHULW_CCU6__RA_, A5F_SFMT_MACHULW_CCU6__RA_ },
+ { ARC_INSN_MACHULW_L_U6__RA_, A5F_INSN_MACHULW_L_U6__RA_, A5F_SFMT_MACHULW_L_U6__RA_ },
+ { ARC_INSN_MACHULW_L_R_R__RA__RC, A5F_INSN_MACHULW_L_R_R__RA__RC, A5F_SFMT_MACHULW_L_R_R__RA__RC },
+ { ARC_INSN_MACHULW_CC__RA__RC, A5F_INSN_MACHULW_CC__RA__RC, A5F_SFMT_MACHULW_CC__RA__RC },
+ { ARC_INSN_CURRENT_LOOP_END, A5F_INSN_CURRENT_LOOP_END, A5F_SFMT_CURRENT_LOOP_END },
+ { ARC_INSN_CURRENT_LOOP_END_AFTER_BRANCH, A5F_INSN_CURRENT_LOOP_END_AFTER_BRANCH, A5F_SFMT_CURRENT_LOOP_END_AFTER_BRANCH },
+ { ARC_INSN_ARC600_CURRENT_LOOP_END_AFTER_BRANCH, A5F_INSN_ARC600_CURRENT_LOOP_END_AFTER_BRANCH, A5F_SFMT_CURRENT_LOOP_END_AFTER_BRANCH },
+};
+
+static const struct insn_sem a5f_insn_sem_invalid = {
+ VIRTUAL_INSN_X_INVALID, A5F_INSN_X_INVALID, A5F_SFMT_EMPTY
+};
+
+/* Initialize an IDESC from the compile-time computable parts. */
+
+static INLINE void
+init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
+{
+ const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries;
+
+ id->num = t->index;
+ id->sfmt = t->sfmt;
+ if ((int) t->type <= 0)
+ id->idata = & cgen_virtual_insn_table[- (int) t->type];
+ else
+ id->idata = & insn_table[t->type];
+ id->attrs = CGEN_INSN_ATTRS (id->idata);
+ /* Oh my god, a magic number. */
+ id->length = CGEN_INSN_BITSIZE (id->idata) / 8;
+
+#if WITH_PROFILE_MODEL_P
+ id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index];
+ {
+ SIM_DESC sd = CPU_STATE (cpu);
+ SIM_ASSERT (t->index == id->timing->num);
+ }
+#endif
+
+ /* Semantic pointers are initialized elsewhere. */
+}
+
+/* Initialize the instruction descriptor table. */
+
+void
+a5f_init_idesc_table (SIM_CPU *cpu)
+{
+ IDESC *id,*tabend;
+ const struct insn_sem *t,*tend;
+ int tabsize = A5F_INSN__MAX;
+ IDESC *table = a5f_insn_data;
+
+ memset (table, 0, tabsize * sizeof (IDESC));
+
+ /* First set all entries to the `invalid insn'. */
+ t = & a5f_insn_sem_invalid;
+ for (id = table, tabend = table + tabsize; id < tabend; ++id)
+ init_idesc (cpu, id, t);
+
+ /* Now fill in the values for the chosen cpu. */
+ for (t = a5f_insn_sem, tend = t + sizeof (a5f_insn_sem) / sizeof (*t);
+ t != tend; ++t)
+ {
+ init_idesc (cpu, & table[t->index], t);
+ }
+
+ /* Link the IDESC table into the cpu. */
+ CPU_IDESC (cpu) = table;
+}
+
+/* Given an instruction, return a pointer to its IDESC entry. */
+
+const IDESC *
+a5f_decode (SIM_CPU *current_cpu, IADDR pc,
+ CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn,
+ ARGBUF *abuf)
+{
+ /* Result of decoder. */
+ A5F_INSN_TYPE itype;
+
+ {
+ CGEN_INSN_INT insn = base_insn;
+
+ {
+ unsigned int val = (((insn >> 20) & (1 << 10)) | ((insn >> 19) & (3 << 8)) | ((insn >> 16) & (255 << 0)));
+ switch (val)
+ {
+ case 0 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20000000)
+ { itype = A5F_INSN_ADD_L_R_R__RA__RC; goto extract_sfmt_add_L_r_r__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20010000)
+ { itype = A5F_INSN_ADC_L_R_R__RA__RC; goto extract_sfmt_adc_L_r_r__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 2 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20020000)
+ { itype = A5F_INSN_SUB_L_R_R__RA__RC; goto extract_sfmt_add_L_r_r__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 3 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20030000)
+ { itype = A5F_INSN_SBC_L_R_R__RA__RC; goto extract_sfmt_adc_L_r_r__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 4 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20040000)
+ { itype = A5F_INSN_AND_L_R_R__RA__RC; goto extract_sfmt_and_L_r_r__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 5 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20050000)
+ { itype = A5F_INSN_OR_L_R_R__RA__RC; goto extract_sfmt_and_L_r_r__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 6 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20060000)
+ { itype = A5F_INSN_BIC_L_R_R__RA__RC; goto extract_sfmt_and_L_r_r__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 7 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20070000)
+ { itype = A5F_INSN_XOR_L_R_R__RA__RC; goto extract_sfmt_and_L_r_r__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 8 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20080000)
+ { itype = A5F_INSN_MAX_L_R_R__RA__RC; goto extract_sfmt_add_L_r_r__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 9 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20090000)
+ { itype = A5F_INSN_MIN_L_R_R__RA__RC; goto extract_sfmt_add_L_r_r__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 10 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x200a0000)
+ { itype = A5F_INSN_MOV_L_R_R__RC; goto extract_sfmt_mov_L_r_r__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 11 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x200b0000)
+ { itype = A5F_INSN_TST_L_R_R__RC; goto extract_sfmt_tst_L_r_r__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 12 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x200c0000)
+ { itype = A5F_INSN_CMP_L_R_R__RC; goto extract_sfmt_cmp_L_r_r__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 13 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x200d0000)
+ { itype = A5F_INSN_RCMP_L_R_R__RC; goto extract_sfmt_cmp_L_r_r__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 14 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x200e0000)
+ { itype = A5F_INSN_RSUB_L_R_R__RA__RC; goto extract_sfmt_add_L_r_r__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 15 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x200f0000)
+ { itype = A5F_INSN_BSET_L_R_R__RA__RC; goto extract_sfmt_and_L_r_r__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 16 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20100000)
+ { itype = A5F_INSN_BCLR_L_R_R__RA__RC; goto extract_sfmt_and_L_r_r__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 17 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20110000)
+ { itype = A5F_INSN_BTST_L_R_R__RC; goto extract_sfmt_tst_L_r_r__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 18 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20120000)
+ { itype = A5F_INSN_BXOR_L_R_R__RA__RC; goto extract_sfmt_and_L_r_r__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 19 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20130000)
+ { itype = A5F_INSN_BMSK_L_R_R__RA__RC; goto extract_sfmt_and_L_r_r__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 20 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20140000)
+ { itype = A5F_INSN_ADD1_L_R_R__RA__RC; goto extract_sfmt_add_L_r_r__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 21 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20150000)
+ { itype = A5F_INSN_ADD2_L_R_R__RA__RC; goto extract_sfmt_add_L_r_r__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 22 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20160000)
+ { itype = A5F_INSN_ADD3_L_R_R__RA__RC; goto extract_sfmt_add_L_r_r__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 23 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20170000)
+ { itype = A5F_INSN_SUB1_L_R_R__RA__RC; goto extract_sfmt_add_L_r_r__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 24 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20180000)
+ { itype = A5F_INSN_SUB2_L_R_R__RA__RC; goto extract_sfmt_add_L_r_r__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 25 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20190000)
+ { itype = A5F_INSN_SUB3_L_R_R__RA__RC; goto extract_sfmt_add_L_r_r__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 26 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x201a0000)
+ { itype = A5F_INSN_MPY_L_R_R__RA__RC; goto extract_sfmt_mpy_L_r_r__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 27 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x201b0000)
+ { itype = A5F_INSN_MPYH_L_R_R__RA__RC; goto extract_sfmt_mpy_L_r_r__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 28 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x201c0000)
+ { itype = A5F_INSN_MPYHU_L_R_R__RA__RC; goto extract_sfmt_mpy_L_r_r__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 29 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x201d0000)
+ { itype = A5F_INSN_MPYU_L_R_R__RA__RC; goto extract_sfmt_mpy_L_r_r__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 30 : /* fall through */
+ case 36 : /* fall through */
+ case 38 : /* fall through */
+ case 40 : /* fall through */
+ case 44 : /* fall through */
+ case 46 : /* fall through */
+ case 54 : /* fall through */
+ case 56 : /* fall through */
+ case 58 : /* fall through */
+ case 60 : /* fall through */
+ case 62 : /* fall through */
+ case 94 : /* fall through */
+ case 100 : /* fall through */
+ case 102 : /* fall through */
+ case 104 : /* fall through */
+ case 108 : /* fall through */
+ case 110 : /* fall through */
+ case 118 : /* fall through */
+ case 120 : /* fall through */
+ case 122 : /* fall through */
+ case 124 : /* fall through */
+ case 126 : /* fall through */
+ case 158 : /* fall through */
+ case 164 : /* fall through */
+ case 166 : /* fall through */
+ case 172 : /* fall through */
+ case 174 : /* fall through */
+ case 182 : /* fall through */
+ case 184 : /* fall through */
+ case 186 : /* fall through */
+ case 188 : /* fall through */
+ case 190 : /* fall through */
+ case 222 : /* fall through */
+ case 228 : /* fall through */
+ case 230 : /* fall through */
+ case 234 : /* fall through */
+ case 236 : /* fall through */
+ case 238 : /* fall through */
+ case 246 : /* fall through */
+ case 248 : /* fall through */
+ case 250 : /* fall through */
+ case 252 : /* fall through */
+ case 254 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 31 : /* fall through */
+ case 37 : /* fall through */
+ case 39 : /* fall through */
+ case 45 : /* fall through */
+ case 49 : /* fall through */
+ case 55 : /* fall through */
+ case 57 : /* fall through */
+ case 59 : /* fall through */
+ case 61 : /* fall through */
+ case 63 : /* fall through */
+ case 95 : /* fall through */
+ case 101 : /* fall through */
+ case 103 : /* fall through */
+ case 109 : /* fall through */
+ case 113 : /* fall through */
+ case 119 : /* fall through */
+ case 121 : /* fall through */
+ case 123 : /* fall through */
+ case 125 : /* fall through */
+ case 127 : /* fall through */
+ case 159 : /* fall through */
+ case 165 : /* fall through */
+ case 167 : /* fall through */
+ case 173 : /* fall through */
+ case 175 : /* fall through */
+ case 177 : /* fall through */
+ case 183 : /* fall through */
+ case 185 : /* fall through */
+ case 187 : /* fall through */
+ case 189 : /* fall through */
+ case 191 : /* fall through */
+ case 223 : /* fall through */
+ case 229 : /* fall through */
+ case 231 : /* fall through */
+ case 235 : /* fall through */
+ case 237 : /* fall through */
+ case 239 : /* fall through */
+ case 241 : /* fall through */
+ case 247 : /* fall through */
+ case 249 : /* fall through */
+ case 251 : /* fall through */
+ case 253 : /* fall through */
+ case 255 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 32 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20200000)
+ { itype = A5F_INSN_J_L_R_R___RC_ILINK_; goto extract_sfmt_j_L_r_r___RC_ilink_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 33 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20210000)
+ { itype = A5F_INSN_J_L_R_R_D___RC_; goto extract_sfmt_j_L_r_r_d___RC_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 34 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20220000)
+ { itype = A5F_INSN_JL_L_R_R___RC_NOILINK_; goto extract_sfmt_jl_L_r_r___RC_noilink_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 35 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20230000)
+ { itype = A5F_INSN_JL_L_R_R_D___RC_; goto extract_sfmt_jl_L_r_r_d___RC_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 41 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20290000)
+ { itype = A5F_INSN_FLAG_L_R_R__RC; goto extract_sfmt_flag_L_r_r__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 42 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x202a0000)
+ { itype = A5F_INSN_LR_L_R_R___RC_; goto extract_sfmt_lr_L_r_r___RC_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 43 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x202b0000)
+ { itype = A5F_INSN_SR_L_R_R___RC_; goto extract_sfmt_sr_L_r_r___RC_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 47 :
+ {
+ unsigned int val = (((insn >> 23) & (1 << 6)) | ((insn >> 0) & (63 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 16 : /* fall through */
+ case 17 : /* fall through */
+ case 18 : /* fall through */
+ case 19 : /* fall through */
+ case 20 : /* fall through */
+ case 21 : /* fall through */
+ case 22 : /* fall through */
+ case 23 : /* fall through */
+ case 24 : /* fall through */
+ case 25 : /* fall through */
+ case 26 : /* fall through */
+ case 27 : /* fall through */
+ case 28 : /* fall through */
+ case 29 : /* fall through */
+ case 30 : /* fall through */
+ case 31 : /* fall through */
+ case 48 : /* fall through */
+ case 49 : /* fall through */
+ case 50 : /* fall through */
+ case 51 : /* fall through */
+ case 52 : /* fall through */
+ case 53 : /* fall through */
+ case 54 : /* fall through */
+ case 55 : /* fall through */
+ case 56 : /* fall through */
+ case 57 : /* fall through */
+ case 58 : /* fall through */
+ case 59 : /* fall through */
+ case 60 : /* fall through */
+ case 61 : /* fall through */
+ case 62 : /* fall through */
+ case 63 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 32 : /* fall through */
+ case 33 : /* fall through */
+ case 34 : /* fall through */
+ case 35 : /* fall through */
+ case 36 : /* fall through */
+ case 37 : /* fall through */
+ case 38 : /* fall through */
+ case 39 : /* fall through */
+ case 40 : /* fall through */
+ case 41 : /* fall through */
+ case 42 : /* fall through */
+ case 43 : /* fall through */
+ case 44 : /* fall through */
+ case 45 : /* fall through */
+ case 46 : /* fall through */
+ case 47 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 64 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x202f0000)
+ { itype = A5F_INSN_ASL_L_R_R__RC; goto extract_sfmt_asl_L_r_r__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 65 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x202f0001)
+ { itype = A5F_INSN_ASR_L_R_R__RC; goto extract_sfmt_asr_L_r_r__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 66 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x202f0002)
+ { itype = A5F_INSN_LSR_L_R_R__RC; goto extract_sfmt_asr_L_r_r__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 67 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x202f0003)
+ { itype = A5F_INSN_ROR_L_R_R__RC; goto extract_sfmt_asr_L_r_r__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 68 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x202f0004)
+ { itype = A5F_INSN_RRC_L_R_R__RC; goto extract_sfmt_rrc_L_r_r__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 69 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x202f0005)
+ { itype = A5F_INSN_SEXB_L_R_R__RC; goto extract_sfmt_sexb_L_r_r__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 70 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x202f0006)
+ { itype = A5F_INSN_SEXW_L_R_R__RC; goto extract_sfmt_sexw_L_r_r__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 71 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x202f0007)
+ { itype = A5F_INSN_EXTB_L_R_R__RC; goto extract_sfmt_sexb_L_r_r__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 72 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x202f0008)
+ { itype = A5F_INSN_EXTW_L_R_R__RC; goto extract_sfmt_sexw_L_r_r__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 73 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x202f0009)
+ { itype = A5F_INSN_ABS_L_R_R__RC; goto extract_sfmt_abs_L_r_r__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 74 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x202f000a)
+ { itype = A5F_INSN_NOT_L_R_R__RC; goto extract_sfmt_not_L_r_r__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 75 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x202f000b)
+ { itype = A5F_INSN_RLC_L_R_R__RC; goto extract_sfmt_rrc_L_r_r__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 76 : /* fall through */
+ case 77 : /* fall through */
+ case 78 : /* fall through */
+ case 79 : /* fall through */
+ case 80 : /* fall through */
+ case 81 : /* fall through */
+ case 82 : /* fall through */
+ case 83 : /* fall through */
+ case 84 : /* fall through */
+ case 85 : /* fall through */
+ case 86 : /* fall through */
+ case 87 : /* fall through */
+ case 88 : /* fall through */
+ case 89 : /* fall through */
+ case 90 : /* fall through */
+ case 91 : /* fall through */
+ case 92 : /* fall through */
+ case 93 : /* fall through */
+ case 94 : /* fall through */
+ case 95 : /* fall through */
+ case 96 : /* fall through */
+ case 97 : /* fall through */
+ case 98 : /* fall through */
+ case 99 : /* fall through */
+ case 100 : /* fall through */
+ case 101 : /* fall through */
+ case 102 : /* fall through */
+ case 103 : /* fall through */
+ case 104 : /* fall through */
+ case 105 : /* fall through */
+ case 106 : /* fall through */
+ case 107 : /* fall through */
+ case 108 : /* fall through */
+ case 109 : /* fall through */
+ case 110 : /* fall through */
+ case 111 : /* fall through */
+ case 112 : /* fall through */
+ case 113 : /* fall through */
+ case 114 : /* fall through */
+ case 115 : /* fall through */
+ case 116 : /* fall through */
+ case 117 : /* fall through */
+ case 118 : /* fall through */
+ case 119 : /* fall through */
+ case 120 : /* fall through */
+ case 121 : /* fall through */
+ case 122 : /* fall through */
+ case 123 : /* fall through */
+ case 124 : /* fall through */
+ case 125 : /* fall through */
+ case 127 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 126 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x202f003e)
+ { itype = A5F_INSN_CURRENT_LOOP_END; goto extract_sfmt_current_loop_end; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 48 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20300000)
+ { itype = A5F_INSN_LD_ABC; goto extract_sfmt_ld_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 50 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20320000)
+ { itype = A5F_INSN_LDB_ABC; goto extract_sfmt_ldb_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 51 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20330000)
+ { itype = A5F_INSN_LDB_X_ABC; goto extract_sfmt_ldb_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 52 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20340000)
+ { itype = A5F_INSN_LDW_ABC; goto extract_sfmt_ldw_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 53 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20350000)
+ { itype = A5F_INSN_LDW_X_ABC; goto extract_sfmt_ldw_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 64 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20400000)
+ { itype = A5F_INSN_ADD_L_U6__RA_; goto extract_sfmt_add_L_u6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 65 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20410000)
+ { itype = A5F_INSN_ADC_L_U6__RA_; goto extract_sfmt_adc_L_u6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 66 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20420000)
+ { itype = A5F_INSN_SUB_L_U6__RA_; goto extract_sfmt_add_L_u6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 67 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20430000)
+ { itype = A5F_INSN_SBC_L_U6__RA_; goto extract_sfmt_adc_L_u6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 68 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20440000)
+ { itype = A5F_INSN_AND_L_U6__RA_; goto extract_sfmt_and_L_u6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 69 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20450000)
+ { itype = A5F_INSN_OR_L_U6__RA_; goto extract_sfmt_and_L_u6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 70 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20460000)
+ { itype = A5F_INSN_BIC_L_U6__RA_; goto extract_sfmt_and_L_u6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 71 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20470000)
+ { itype = A5F_INSN_XOR_L_U6__RA_; goto extract_sfmt_and_L_u6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 72 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20480000)
+ { itype = A5F_INSN_MAX_L_U6__RA_; goto extract_sfmt_add_L_u6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 73 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20490000)
+ { itype = A5F_INSN_MIN_L_U6__RA_; goto extract_sfmt_add_L_u6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 74 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x204a0000)
+ { itype = A5F_INSN_MOV_L_U6_; goto extract_sfmt_mov_L_u6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 75 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x204b0000)
+ { itype = A5F_INSN_TST_L_U6_; goto extract_sfmt_tst_L_u6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 76 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x204c0000)
+ { itype = A5F_INSN_CMP_L_U6_; goto extract_sfmt_cmp_L_u6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 77 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x204d0000)
+ { itype = A5F_INSN_RCMP_L_U6_; goto extract_sfmt_cmp_L_u6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 78 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x204e0000)
+ { itype = A5F_INSN_RSUB_L_U6__RA_; goto extract_sfmt_add_L_u6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 79 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x204f0000)
+ { itype = A5F_INSN_BSET_L_U6__RA_; goto extract_sfmt_and_L_u6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 80 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20500000)
+ { itype = A5F_INSN_BCLR_L_U6__RA_; goto extract_sfmt_and_L_u6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 81 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20510000)
+ { itype = A5F_INSN_BTST_L_U6_; goto extract_sfmt_tst_L_u6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 82 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20520000)
+ { itype = A5F_INSN_BXOR_L_U6__RA_; goto extract_sfmt_and_L_u6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 83 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20530000)
+ { itype = A5F_INSN_BMSK_L_U6__RA_; goto extract_sfmt_and_L_u6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 84 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20540000)
+ { itype = A5F_INSN_ADD1_L_U6__RA_; goto extract_sfmt_add_L_u6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 85 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20550000)
+ { itype = A5F_INSN_ADD2_L_U6__RA_; goto extract_sfmt_add_L_u6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 86 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20560000)
+ { itype = A5F_INSN_ADD3_L_U6__RA_; goto extract_sfmt_add_L_u6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 87 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20570000)
+ { itype = A5F_INSN_SUB1_L_U6__RA_; goto extract_sfmt_add_L_u6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 88 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20580000)
+ { itype = A5F_INSN_SUB2_L_U6__RA_; goto extract_sfmt_add_L_u6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 89 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20590000)
+ { itype = A5F_INSN_SUB3_L_U6__RA_; goto extract_sfmt_add_L_u6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 90 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x205a0000)
+ { itype = A5F_INSN_MPY_L_U6__RA_; goto extract_sfmt_mpy_L_u6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 91 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x205b0000)
+ { itype = A5F_INSN_MPYH_L_U6__RA_; goto extract_sfmt_mpy_L_u6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 92 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x205c0000)
+ { itype = A5F_INSN_MPYHU_L_U6__RA_; goto extract_sfmt_mpy_L_u6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 93 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x205d0000)
+ { itype = A5F_INSN_MPYU_L_U6__RA_; goto extract_sfmt_mpy_L_u6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 96 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20600000)
+ { itype = A5F_INSN_J_L_U6_; goto extract_sfmt_j_L_u6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 97 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20610000)
+ { itype = A5F_INSN_J_L_U6_D_; goto extract_sfmt_j_L_u6_d_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 98 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20620000)
+ { itype = A5F_INSN_JL_L_U6_; goto extract_sfmt_jl_L_u6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 99 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20630000)
+ { itype = A5F_INSN_JL_L_U6_D_; goto extract_sfmt_jl_L_u6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 105 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20690000)
+ { itype = A5F_INSN_FLAG_L_U6_; goto extract_sfmt_flag_L_u6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 106 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x206a0000)
+ { itype = A5F_INSN_LR_L_U6_; goto extract_sfmt_lr_L_u6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 107 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x206b0000)
+ { itype = A5F_INSN_SR_L_U6_; goto extract_sfmt_sr_L_u6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 111 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff003f) == 0x206f0000)
+ { itype = A5F_INSN_ASL_L_U6_; goto extract_sfmt_asl_L_u6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff003f) == 0x206f0001)
+ { itype = A5F_INSN_ASR_L_U6_; goto extract_sfmt_asr_L_u6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 2 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff003f) == 0x206f0002)
+ { itype = A5F_INSN_LSR_L_U6_; goto extract_sfmt_asr_L_u6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 3 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff003f) == 0x206f0003)
+ { itype = A5F_INSN_ROR_L_U6_; goto extract_sfmt_asr_L_u6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 4 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff003f) == 0x206f0004)
+ { itype = A5F_INSN_RRC_L_U6_; goto extract_sfmt_rrc_L_u6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 5 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff003f) == 0x206f0005)
+ { itype = A5F_INSN_SEXB_L_U6_; goto extract_sfmt_sexb_L_u6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 6 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff003f) == 0x206f0006)
+ { itype = A5F_INSN_SEXW_L_U6_; goto extract_sfmt_sexw_L_u6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 7 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff003f) == 0x206f0007)
+ { itype = A5F_INSN_EXTB_L_U6_; goto extract_sfmt_sexb_L_u6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 8 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff003f) == 0x206f0008)
+ { itype = A5F_INSN_EXTW_L_U6_; goto extract_sfmt_sexw_L_u6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 9 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff003f) == 0x206f0009)
+ { itype = A5F_INSN_ABS_L_U6_; goto extract_sfmt_abs_L_u6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 10 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff003f) == 0x206f000a)
+ { itype = A5F_INSN_NOT_L_U6_; goto extract_sfmt_not_L_u6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 11 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff003f) == 0x206f000b)
+ { itype = A5F_INSN_RLC_L_U6_; goto extract_sfmt_rrc_L_u6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 15 :
+ {
+ unsigned int val = (((insn >> 25) & (1 << 6)) | ((insn >> 24) & (1 << 5)) | ((insn >> 22) & (7 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 4 : /* fall through */
+ case 8 : /* fall through */
+ case 12 : /* fall through */
+ case 16 : /* fall through */
+ case 20 : /* fall through */
+ case 24 : /* fall through */
+ case 28 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 6 : /* fall through */
+ case 10 : /* fall through */
+ case 14 : /* fall through */
+ case 18 : /* fall through */
+ case 22 : /* fall through */
+ case 26 : /* fall through */
+ case 30 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 43 :
+ if ((entire_insn & 0xffff7fff) == 0x226f003f)
+ { itype = A5F_INSN_SWI; goto extract_sfmt_swi; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 55 :
+ if ((entire_insn & 0xffff7fff) == 0x256f003f)
+ { itype = A5F_INSN_BRK; goto extract_sfmt_brk; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 64 : /* fall through */
+ case 65 : /* fall through */
+ case 66 : /* fall through */
+ case 67 : /* fall through */
+ case 68 : /* fall through */
+ case 69 : /* fall through */
+ case 70 : /* fall through */
+ case 71 : /* fall through */
+ case 72 : /* fall through */
+ case 73 : /* fall through */
+ case 74 : /* fall through */
+ case 75 : /* fall through */
+ case 76 : /* fall through */
+ case 77 : /* fall through */
+ case 78 : /* fall through */
+ case 79 : /* fall through */
+ case 80 : /* fall through */
+ case 81 : /* fall through */
+ case 82 : /* fall through */
+ case 83 : /* fall through */
+ case 84 : /* fall through */
+ case 85 : /* fall through */
+ case 86 : /* fall through */
+ case 87 : /* fall through */
+ case 88 : /* fall through */
+ case 89 : /* fall through */
+ case 90 : /* fall through */
+ case 91 : /* fall through */
+ case 92 : /* fall through */
+ case 93 : /* fall through */
+ case 94 : /* fall through */
+ case 95 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 96 : /* fall through */
+ case 97 : /* fall through */
+ case 98 : /* fall through */
+ case 99 : /* fall through */
+ case 100 : /* fall through */
+ case 101 : /* fall through */
+ case 102 : /* fall through */
+ case 103 : /* fall through */
+ case 104 : /* fall through */
+ case 105 : /* fall through */
+ case 106 : /* fall through */
+ case 107 : /* fall through */
+ case 108 : /* fall through */
+ case 109 : /* fall through */
+ case 110 : /* fall through */
+ case 111 : /* fall through */
+ case 112 : /* fall through */
+ case 113 : /* fall through */
+ case 114 : /* fall through */
+ case 115 : /* fall through */
+ case 116 : /* fall through */
+ case 117 : /* fall through */
+ case 118 : /* fall through */
+ case 119 : /* fall through */
+ case 120 : /* fall through */
+ case 121 : /* fall through */
+ case 122 : /* fall through */
+ case 123 : /* fall through */
+ case 124 : /* fall through */
+ case 125 : /* fall through */
+ case 126 : /* fall through */
+ case 127 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 112 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20700000)
+ { itype = A5F_INSN_LD__AW_ABC; goto extract_sfmt_ld__AW_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 114 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20720000)
+ { itype = A5F_INSN_LDB__AW_ABC; goto extract_sfmt_ldb__AW_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 115 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20730000)
+ { itype = A5F_INSN_LDB__AW_X_ABC; goto extract_sfmt_ldb__AW_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 116 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20740000)
+ { itype = A5F_INSN_LDW__AW_ABC; goto extract_sfmt_ldw__AW_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 117 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20750000)
+ { itype = A5F_INSN_LDW__AW_X_ABC; goto extract_sfmt_ldw__AW_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 128 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20800000)
+ { itype = A5F_INSN_ADD_L_S12__RA_; goto extract_sfmt_add_L_s12__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 129 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20810000)
+ { itype = A5F_INSN_ADC_L_S12__RA_; goto extract_sfmt_adc_L_s12__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 130 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20820000)
+ { itype = A5F_INSN_SUB_L_S12__RA_; goto extract_sfmt_add_L_s12__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 131 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20830000)
+ { itype = A5F_INSN_SBC_L_S12__RA_; goto extract_sfmt_adc_L_s12__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 132 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20840000)
+ { itype = A5F_INSN_AND_L_S12__RA_; goto extract_sfmt_and_L_s12__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 133 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20850000)
+ { itype = A5F_INSN_OR_L_S12__RA_; goto extract_sfmt_and_L_s12__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 134 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20860000)
+ { itype = A5F_INSN_BIC_L_S12__RA_; goto extract_sfmt_and_L_s12__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 135 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20870000)
+ { itype = A5F_INSN_XOR_L_S12__RA_; goto extract_sfmt_and_L_s12__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 136 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20880000)
+ { itype = A5F_INSN_MAX_L_S12__RA_; goto extract_sfmt_add_L_s12__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 137 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20890000)
+ { itype = A5F_INSN_MIN_L_S12__RA_; goto extract_sfmt_add_L_s12__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 138 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x208a0000)
+ { itype = A5F_INSN_MOV_L_S12_; goto extract_sfmt_mov_L_s12_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 139 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x208b0000)
+ { itype = A5F_INSN_TST_L_S12_; goto extract_sfmt_tst_L_s12_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 140 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x208c0000)
+ { itype = A5F_INSN_CMP_L_S12_; goto extract_sfmt_cmp_L_s12_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 141 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x208d0000)
+ { itype = A5F_INSN_RCMP_L_S12_; goto extract_sfmt_cmp_L_s12_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 142 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x208e0000)
+ { itype = A5F_INSN_RSUB_L_S12__RA_; goto extract_sfmt_add_L_s12__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 143 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x208f0000)
+ { itype = A5F_INSN_BSET_L_S12__RA_; goto extract_sfmt_and_L_s12__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 144 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20900000)
+ { itype = A5F_INSN_BCLR_L_S12__RA_; goto extract_sfmt_and_L_s12__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 145 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20910000)
+ { itype = A5F_INSN_BTST_L_S12_; goto extract_sfmt_tst_L_s12_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 146 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20920000)
+ { itype = A5F_INSN_BXOR_L_S12__RA_; goto extract_sfmt_and_L_s12__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 147 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20930000)
+ { itype = A5F_INSN_BMSK_L_S12__RA_; goto extract_sfmt_and_L_s12__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 148 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20940000)
+ { itype = A5F_INSN_ADD1_L_S12__RA_; goto extract_sfmt_add_L_s12__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 149 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20950000)
+ { itype = A5F_INSN_ADD2_L_S12__RA_; goto extract_sfmt_add_L_s12__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 150 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20960000)
+ { itype = A5F_INSN_ADD3_L_S12__RA_; goto extract_sfmt_add_L_s12__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 151 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20970000)
+ { itype = A5F_INSN_SUB1_L_S12__RA_; goto extract_sfmt_add_L_s12__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 152 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20980000)
+ { itype = A5F_INSN_SUB2_L_S12__RA_; goto extract_sfmt_add_L_s12__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 153 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20990000)
+ { itype = A5F_INSN_SUB3_L_S12__RA_; goto extract_sfmt_add_L_s12__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 154 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x209a0000)
+ { itype = A5F_INSN_MPY_L_S12__RA_; goto extract_sfmt_mpy_L_s12__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 155 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x209b0000)
+ { itype = A5F_INSN_MPYH_L_S12__RA_; goto extract_sfmt_mpy_L_s12__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 156 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x209c0000)
+ { itype = A5F_INSN_MPYHU_L_S12__RA_; goto extract_sfmt_mpy_L_s12__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 157 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x209d0000)
+ { itype = A5F_INSN_MPYU_L_S12__RA_; goto extract_sfmt_mpy_L_s12__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 160 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20a00000)
+ { itype = A5F_INSN_J_L_S12_; goto extract_sfmt_j_L_s12_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 161 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20a10000)
+ { itype = A5F_INSN_J_L_S12_D_; goto extract_sfmt_j_L_s12_d_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 162 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20a20000)
+ { itype = A5F_INSN_JL_L_S12_; goto extract_sfmt_jl_L_s12_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 163 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20a30000)
+ { itype = A5F_INSN_JL_L_S12_D_; goto extract_sfmt_jl_L_s12_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 168 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20a80000)
+ { itype = A5F_INSN_LP_L_S12_; goto extract_sfmt_lp_L_s12_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 169 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20a90000)
+ { itype = A5F_INSN_FLAG_L_S12_; goto extract_sfmt_flag_L_s12_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 170 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20aa0000)
+ { itype = A5F_INSN_LR_L_S12_; goto extract_sfmt_lr_L_s12_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 171 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20ab0000)
+ { itype = A5F_INSN_SR_L_S12_; goto extract_sfmt_sr_L_s12_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 176 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20b00000)
+ { itype = A5F_INSN_LD_AB_ABC; goto extract_sfmt_ld__AW_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 178 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20b20000)
+ { itype = A5F_INSN_LDB_AB_ABC; goto extract_sfmt_ldb__AW_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 179 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20b30000)
+ { itype = A5F_INSN_LDB_AB_X_ABC; goto extract_sfmt_ldb__AW_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 180 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20b40000)
+ { itype = A5F_INSN_LDW_AB_ABC; goto extract_sfmt_ldw__AW_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 181 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20b50000)
+ { itype = A5F_INSN_LDW_AB_X_ABC; goto extract_sfmt_ldw__AW_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 192 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c00000)
+ { itype = A5F_INSN_ADD_CC__RA__RC; goto extract_sfmt_add_cc__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c00020)
+ { itype = A5F_INSN_ADD_CCU6__RA_; goto extract_sfmt_add_ccu6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 193 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c10000)
+ { itype = A5F_INSN_ADC_CC__RA__RC; goto extract_sfmt_adc_cc__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c10020)
+ { itype = A5F_INSN_ADC_CCU6__RA_; goto extract_sfmt_adc_ccu6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 194 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c20000)
+ { itype = A5F_INSN_SUB_CC__RA__RC; goto extract_sfmt_add_cc__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c20020)
+ { itype = A5F_INSN_SUB_CCU6__RA_; goto extract_sfmt_add_ccu6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 195 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c30000)
+ { itype = A5F_INSN_SBC_CC__RA__RC; goto extract_sfmt_adc_cc__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c30020)
+ { itype = A5F_INSN_SBC_CCU6__RA_; goto extract_sfmt_adc_ccu6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 196 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c40000)
+ { itype = A5F_INSN_AND_CC__RA__RC; goto extract_sfmt_and_cc__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c40020)
+ { itype = A5F_INSN_AND_CCU6__RA_; goto extract_sfmt_and_ccu6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 197 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c50000)
+ { itype = A5F_INSN_OR_CC__RA__RC; goto extract_sfmt_and_cc__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c50020)
+ { itype = A5F_INSN_OR_CCU6__RA_; goto extract_sfmt_and_ccu6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 198 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c60000)
+ { itype = A5F_INSN_BIC_CC__RA__RC; goto extract_sfmt_and_cc__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c60020)
+ { itype = A5F_INSN_BIC_CCU6__RA_; goto extract_sfmt_and_ccu6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 199 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c70000)
+ { itype = A5F_INSN_XOR_CC__RA__RC; goto extract_sfmt_and_cc__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c70020)
+ { itype = A5F_INSN_XOR_CCU6__RA_; goto extract_sfmt_and_ccu6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 200 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c80000)
+ { itype = A5F_INSN_MAX_CC__RA__RC; goto extract_sfmt_add_cc__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c80020)
+ { itype = A5F_INSN_MAX_CCU6__RA_; goto extract_sfmt_add_ccu6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 201 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c90000)
+ { itype = A5F_INSN_MIN_CC__RA__RC; goto extract_sfmt_add_cc__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c90020)
+ { itype = A5F_INSN_MIN_CCU6__RA_; goto extract_sfmt_add_ccu6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 202 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20ca0000)
+ { itype = A5F_INSN_MOV_CC__RC; goto extract_sfmt_mov_cc__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20ca0020)
+ { itype = A5F_INSN_MOV_CCU6_; goto extract_sfmt_mov_ccu6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 203 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20cb0000)
+ { itype = A5F_INSN_TST_CC__RC; goto extract_sfmt_tst_cc__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20cb0020)
+ { itype = A5F_INSN_TST_CCU6_; goto extract_sfmt_tst_ccu6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 204 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20cc0000)
+ { itype = A5F_INSN_CMP_CC__RC; goto extract_sfmt_cmp_cc__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20cc0020)
+ { itype = A5F_INSN_CMP_CCU6_; goto extract_sfmt_cmp_ccu6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 205 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20cd0000)
+ { itype = A5F_INSN_RCMP_CC__RC; goto extract_sfmt_cmp_cc__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20cd0020)
+ { itype = A5F_INSN_RCMP_CCU6_; goto extract_sfmt_cmp_ccu6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 206 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20ce0000)
+ { itype = A5F_INSN_RSUB_CC__RA__RC; goto extract_sfmt_add_cc__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20ce0020)
+ { itype = A5F_INSN_RSUB_CCU6__RA_; goto extract_sfmt_add_ccu6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 207 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20cf0000)
+ { itype = A5F_INSN_BSET_CC__RA__RC; goto extract_sfmt_and_cc__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20cf0020)
+ { itype = A5F_INSN_BSET_CCU6__RA_; goto extract_sfmt_and_ccu6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 208 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d00000)
+ { itype = A5F_INSN_BCLR_CC__RA__RC; goto extract_sfmt_and_cc__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d00020)
+ { itype = A5F_INSN_BCLR_CCU6__RA_; goto extract_sfmt_and_ccu6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 209 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d10000)
+ { itype = A5F_INSN_BTST_CC__RC; goto extract_sfmt_tst_cc__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d10020)
+ { itype = A5F_INSN_BTST_CCU6_; goto extract_sfmt_tst_ccu6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 210 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d20000)
+ { itype = A5F_INSN_BXOR_CC__RA__RC; goto extract_sfmt_and_cc__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d20020)
+ { itype = A5F_INSN_BXOR_CCU6__RA_; goto extract_sfmt_and_ccu6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 211 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d30000)
+ { itype = A5F_INSN_BMSK_CC__RA__RC; goto extract_sfmt_and_cc__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d30020)
+ { itype = A5F_INSN_BMSK_CCU6__RA_; goto extract_sfmt_and_ccu6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 212 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d40000)
+ { itype = A5F_INSN_ADD1_CC__RA__RC; goto extract_sfmt_add_cc__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d40020)
+ { itype = A5F_INSN_ADD1_CCU6__RA_; goto extract_sfmt_add_ccu6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 213 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d50000)
+ { itype = A5F_INSN_ADD2_CC__RA__RC; goto extract_sfmt_add_cc__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d50020)
+ { itype = A5F_INSN_ADD2_CCU6__RA_; goto extract_sfmt_add_ccu6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 214 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d60000)
+ { itype = A5F_INSN_ADD3_CC__RA__RC; goto extract_sfmt_add_cc__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d60020)
+ { itype = A5F_INSN_ADD3_CCU6__RA_; goto extract_sfmt_add_ccu6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 215 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d70000)
+ { itype = A5F_INSN_SUB1_CC__RA__RC; goto extract_sfmt_add_cc__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d70020)
+ { itype = A5F_INSN_SUB1_CCU6__RA_; goto extract_sfmt_add_ccu6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 216 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d80000)
+ { itype = A5F_INSN_SUB2_CC__RA__RC; goto extract_sfmt_add_cc__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d80020)
+ { itype = A5F_INSN_SUB2_CCU6__RA_; goto extract_sfmt_add_ccu6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 217 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d90000)
+ { itype = A5F_INSN_SUB3_CC__RA__RC; goto extract_sfmt_add_cc__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d90020)
+ { itype = A5F_INSN_SUB3_CCU6__RA_; goto extract_sfmt_add_ccu6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 218 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20da0000)
+ { itype = A5F_INSN_MPY_CC__RA__RC; goto extract_sfmt_mpy_cc__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20da0020)
+ { itype = A5F_INSN_MPY_CCU6__RA_; goto extract_sfmt_mpy_ccu6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 219 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20db0000)
+ { itype = A5F_INSN_MPYH_CC__RA__RC; goto extract_sfmt_mpy_cc__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20db0020)
+ { itype = A5F_INSN_MPYH_CCU6__RA_; goto extract_sfmt_mpy_ccu6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 220 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20dc0000)
+ { itype = A5F_INSN_MPYHU_CC__RA__RC; goto extract_sfmt_mpy_cc__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20dc0020)
+ { itype = A5F_INSN_MPYHU_CCU6__RA_; goto extract_sfmt_mpy_ccu6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 221 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20dd0000)
+ { itype = A5F_INSN_MPYU_CC__RA__RC; goto extract_sfmt_mpy_cc__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20dd0020)
+ { itype = A5F_INSN_MPYU_CCU6__RA_; goto extract_sfmt_mpy_ccu6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 224 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20e00000)
+ { itype = A5F_INSN_J_CC___RC_ILINK_; goto extract_sfmt_j_cc___RC_ilink_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20e00020)
+ { itype = A5F_INSN_J_CCU6_; goto extract_sfmt_j_ccu6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 225 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20e10000)
+ { itype = A5F_INSN_J_CC_D___RC_; goto extract_sfmt_j_cc_d___RC_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20e10020)
+ { itype = A5F_INSN_J_CCU6_D_; goto extract_sfmt_j_ccu6_d_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 226 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20e20000)
+ { itype = A5F_INSN_JL_CC___RC_NOILINK_; goto extract_sfmt_jl_cc___RC_noilink_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20e20020)
+ { itype = A5F_INSN_JL_CCU6_; goto extract_sfmt_jl_ccu6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 227 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20e30000)
+ { itype = A5F_INSN_JL_CC_D___RC_; goto extract_sfmt_jl_cc_d___RC_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20e30020)
+ { itype = A5F_INSN_JL_CCU6_D_; goto extract_sfmt_jl_ccu6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 232 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20e80020)
+ { itype = A5F_INSN_LPCC_CCU6; goto extract_sfmt_lpcc_ccu6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 233 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20e90000)
+ { itype = A5F_INSN_FLAG_CC__RC; goto extract_sfmt_flag_cc__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20e90020)
+ { itype = A5F_INSN_FLAG_CCU6_; goto extract_sfmt_flag_ccu6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 240 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20f00000)
+ { itype = A5F_INSN_LD_AS_ABC; goto extract_sfmt_ld_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 242 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20f20000)
+ { itype = A5F_INSN_LDB_AS_ABC; goto extract_sfmt_ldb_as_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 243 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20f30000)
+ { itype = A5F_INSN_LDB_AS_X_ABC; goto extract_sfmt_ldb_as_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 244 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = A5F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = A5F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20f40000)
+ { itype = A5F_INSN_LDW_AS_ABC; goto extract_sfmt_ldw_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 245 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = A5F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = A5F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20f50000)
+ { itype = A5F_INSN_LDW_AS_X_ABC; goto extract_sfmt_ldw_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = A5F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = A5F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 256 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = A5F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = A5F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28000000)
+ { itype = A5F_INSN_ASL_L_R_R__RA__RC; goto extract_sfmt_asl_L_r_r__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 257 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = A5F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = A5F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = A5F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = A5F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28010000)
+ { itype = A5F_INSN_LSR_L_R_R__RA__RC; goto extract_sfmt_asl_L_r_r__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 258 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = A5F_INSN_BL; goto extract_sfmt_bl; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = A5F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28020000)
+ { itype = A5F_INSN_ASR_L_R_R__RA__RC; goto extract_sfmt_asl_L_r_r__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 259 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = A5F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = A5F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = A5F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = A5F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28030000)
+ { itype = A5F_INSN_ROR_L_R_R__RA__RC; goto extract_sfmt_asl_L_r_r__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 260 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = A5F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = A5F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28040000)
+ { itype = A5F_INSN_MUL64_L_R_R__RC; goto extract_sfmt_mul64_L_r_r__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 261 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = A5F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = A5F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = A5F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = A5F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28050000)
+ { itype = A5F_INSN_MULU64_L_R_R__RC; goto extract_sfmt_mul64_L_r_r__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 262 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = A5F_INSN_BL; goto extract_sfmt_bl; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = A5F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28060000)
+ { itype = A5F_INSN_ADDS_L_R_R__RA__RC; goto extract_sfmt_adds_L_r_r__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 263 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = A5F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = A5F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = A5F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = A5F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28070000)
+ { itype = A5F_INSN_SUBS_L_R_R__RA__RC; goto extract_sfmt_adds_L_r_r__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 264 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = A5F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = A5F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28080000)
+ { itype = A5F_INSN_DIVAW_L_R_R__RA__RC; goto extract_sfmt_divaw_L_r_r__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 265 : /* fall through */
+ case 269 : /* fall through */
+ case 271 : /* fall through */
+ case 273 : /* fall through */
+ case 275 : /* fall through */
+ case 277 : /* fall through */
+ case 279 : /* fall through */
+ case 281 : /* fall through */
+ case 283 : /* fall through */
+ case 285 : /* fall through */
+ case 287 : /* fall through */
+ case 289 : /* fall through */
+ case 291 : /* fall through */
+ case 293 : /* fall through */
+ case 295 : /* fall through */
+ case 299 : /* fall through */
+ case 301 : /* fall through */
+ case 311 : /* fall through */
+ case 313 : /* fall through */
+ case 315 : /* fall through */
+ case 317 : /* fall through */
+ case 319 : /* fall through */
+ case 329 : /* fall through */
+ case 333 : /* fall through */
+ case 335 : /* fall through */
+ case 337 : /* fall through */
+ case 339 : /* fall through */
+ case 341 : /* fall through */
+ case 343 : /* fall through */
+ case 345 : /* fall through */
+ case 347 : /* fall through */
+ case 349 : /* fall through */
+ case 351 : /* fall through */
+ case 353 : /* fall through */
+ case 355 : /* fall through */
+ case 357 : /* fall through */
+ case 359 : /* fall through */
+ case 363 : /* fall through */
+ case 365 : /* fall through */
+ case 375 : /* fall through */
+ case 377 : /* fall through */
+ case 379 : /* fall through */
+ case 381 : /* fall through */
+ case 383 : /* fall through */
+ case 393 : /* fall through */
+ case 397 : /* fall through */
+ case 399 : /* fall through */
+ case 401 : /* fall through */
+ case 403 : /* fall through */
+ case 405 : /* fall through */
+ case 407 : /* fall through */
+ case 409 : /* fall through */
+ case 411 : /* fall through */
+ case 413 : /* fall through */
+ case 415 : /* fall through */
+ case 417 : /* fall through */
+ case 419 : /* fall through */
+ case 421 : /* fall through */
+ case 423 : /* fall through */
+ case 427 : /* fall through */
+ case 429 : /* fall through */
+ case 431 : /* fall through */
+ case 439 : /* fall through */
+ case 441 : /* fall through */
+ case 443 : /* fall through */
+ case 445 : /* fall through */
+ case 447 : /* fall through */
+ case 457 : /* fall through */
+ case 461 : /* fall through */
+ case 463 : /* fall through */
+ case 465 : /* fall through */
+ case 467 : /* fall through */
+ case 469 : /* fall through */
+ case 471 : /* fall through */
+ case 473 : /* fall through */
+ case 475 : /* fall through */
+ case 477 : /* fall through */
+ case 479 : /* fall through */
+ case 481 : /* fall through */
+ case 483 : /* fall through */
+ case 485 : /* fall through */
+ case 487 : /* fall through */
+ case 491 : /* fall through */
+ case 493 : /* fall through */
+ case 495 : /* fall through */
+ case 503 : /* fall through */
+ case 505 : /* fall through */
+ case 507 : /* fall through */
+ case 509 : /* fall through */
+ case 511 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = A5F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = A5F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = A5F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = A5F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 266 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = A5F_INSN_BL; goto extract_sfmt_bl; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = A5F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x280a0000)
+ { itype = A5F_INSN_ASLS_L_R_R__RA__RC; goto extract_sfmt_asls_L_r_r__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 267 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = A5F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = A5F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = A5F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = A5F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x280b0000)
+ { itype = A5F_INSN_ASRS_L_R_R__RA__RC; goto extract_sfmt_asls_L_r_r__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 268 : /* fall through */
+ case 272 : /* fall through */
+ case 276 : /* fall through */
+ case 280 : /* fall through */
+ case 284 : /* fall through */
+ case 288 : /* fall through */
+ case 292 : /* fall through */
+ case 300 : /* fall through */
+ case 308 : /* fall through */
+ case 312 : /* fall through */
+ case 316 : /* fall through */
+ case 332 : /* fall through */
+ case 336 : /* fall through */
+ case 340 : /* fall through */
+ case 344 : /* fall through */
+ case 348 : /* fall through */
+ case 352 : /* fall through */
+ case 356 : /* fall through */
+ case 364 : /* fall through */
+ case 372 : /* fall through */
+ case 376 : /* fall through */
+ case 380 : /* fall through */
+ case 396 : /* fall through */
+ case 400 : /* fall through */
+ case 404 : /* fall through */
+ case 408 : /* fall through */
+ case 412 : /* fall through */
+ case 416 : /* fall through */
+ case 420 : /* fall through */
+ case 428 : /* fall through */
+ case 436 : /* fall through */
+ case 440 : /* fall through */
+ case 444 : /* fall through */
+ case 460 : /* fall through */
+ case 464 : /* fall through */
+ case 468 : /* fall through */
+ case 472 : /* fall through */
+ case 476 : /* fall through */
+ case 480 : /* fall through */
+ case 484 : /* fall through */
+ case 492 : /* fall through */
+ case 500 : /* fall through */
+ case 504 : /* fall through */
+ case 508 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = A5F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = A5F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 270 : /* fall through */
+ case 274 : /* fall through */
+ case 278 : /* fall through */
+ case 282 : /* fall through */
+ case 286 : /* fall through */
+ case 290 : /* fall through */
+ case 294 : /* fall through */
+ case 298 : /* fall through */
+ case 302 : /* fall through */
+ case 306 : /* fall through */
+ case 314 : /* fall through */
+ case 318 : /* fall through */
+ case 334 : /* fall through */
+ case 338 : /* fall through */
+ case 342 : /* fall through */
+ case 346 : /* fall through */
+ case 350 : /* fall through */
+ case 354 : /* fall through */
+ case 358 : /* fall through */
+ case 362 : /* fall through */
+ case 366 : /* fall through */
+ case 370 : /* fall through */
+ case 378 : /* fall through */
+ case 382 : /* fall through */
+ case 398 : /* fall through */
+ case 402 : /* fall through */
+ case 406 : /* fall through */
+ case 410 : /* fall through */
+ case 414 : /* fall through */
+ case 418 : /* fall through */
+ case 422 : /* fall through */
+ case 426 : /* fall through */
+ case 430 : /* fall through */
+ case 434 : /* fall through */
+ case 442 : /* fall through */
+ case 446 : /* fall through */
+ case 462 : /* fall through */
+ case 466 : /* fall through */
+ case 470 : /* fall through */
+ case 474 : /* fall through */
+ case 478 : /* fall through */
+ case 482 : /* fall through */
+ case 486 : /* fall through */
+ case 490 : /* fall through */
+ case 494 : /* fall through */
+ case 498 : /* fall through */
+ case 506 : /* fall through */
+ case 510 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = A5F_INSN_BL; goto extract_sfmt_bl; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = A5F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 296 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = A5F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = A5F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28280000)
+ { itype = A5F_INSN_ADDSDW_L_R_R__RA__RC; goto extract_sfmt_asls_L_r_r__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 297 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = A5F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = A5F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = A5F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = A5F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28290000)
+ { itype = A5F_INSN_SUBSDW_L_R_R__RA__RC; goto extract_sfmt_asls_L_r_r__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 303 :
+ {
+ unsigned int val = (((insn >> 25) & (1 << 6)) | ((insn >> 24) & (1 << 5)) | ((insn >> 1) & (3 << 3)) | ((insn >> 0) & (7 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = A5F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = A5F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 16 : /* fall through */
+ case 17 : /* fall through */
+ case 18 : /* fall through */
+ case 19 : /* fall through */
+ case 20 : /* fall through */
+ case 21 : /* fall through */
+ case 22 : /* fall through */
+ case 23 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = A5F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 24 : /* fall through */
+ case 25 : /* fall through */
+ case 26 : /* fall through */
+ case 27 : /* fall through */
+ case 28 : /* fall through */
+ case 29 : /* fall through */
+ case 30 : /* fall through */
+ case 31 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = A5F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 32 :
+ {
+ unsigned int val = (((insn >> 3) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x282f0000)
+ { itype = A5F_INSN_SWAP_L_R_R__RC; goto extract_sfmt_swap_L_r_r__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8ff003f) == 0x282f0008)
+ { itype = A5F_INSN_NORMW_L_R_R__RC; goto extract_sfmt_swap_L_r_r__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 33 :
+ if ((entire_insn & 0xf8ff003f) == 0x282f0001)
+ { itype = A5F_INSN_NORM_L_R_R__RC; goto extract_sfmt_swap_L_r_r__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 35 :
+ if ((entire_insn & 0xf8ff003f) == 0x282f0003)
+ { itype = A5F_INSN_RND16_L_R_R__RC; goto extract_sfmt_rnd16_L_r_r__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 36 :
+ if ((entire_insn & 0xf8ff003f) == 0x282f0004)
+ { itype = A5F_INSN_ABSSW_L_R_R__RC; goto extract_sfmt_abssw_L_r_r__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 37 :
+ if ((entire_insn & 0xf8ff003f) == 0x282f0005)
+ { itype = A5F_INSN_ABSS_L_R_R__RC; goto extract_sfmt_rnd16_L_r_r__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 38 :
+ if ((entire_insn & 0xf8ff003f) == 0x282f0006)
+ { itype = A5F_INSN_NEGSW_L_R_R__RC; goto extract_sfmt_abssw_L_r_r__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 39 :
+ if ((entire_insn & 0xf8ff003f) == 0x282f0007)
+ { itype = A5F_INSN_NEGS_L_R_R__RC; goto extract_sfmt_rnd16_L_r_r__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 64 : /* fall through */
+ case 65 : /* fall through */
+ case 66 : /* fall through */
+ case 67 : /* fall through */
+ case 68 : /* fall through */
+ case 69 : /* fall through */
+ case 70 : /* fall through */
+ case 71 : /* fall through */
+ case 72 : /* fall through */
+ case 73 : /* fall through */
+ case 74 : /* fall through */
+ case 75 : /* fall through */
+ case 76 : /* fall through */
+ case 77 : /* fall through */
+ case 78 : /* fall through */
+ case 79 : /* fall through */
+ case 80 : /* fall through */
+ case 81 : /* fall through */
+ case 82 : /* fall through */
+ case 83 : /* fall through */
+ case 84 : /* fall through */
+ case 85 : /* fall through */
+ case 86 : /* fall through */
+ case 87 : /* fall through */
+ case 88 : /* fall through */
+ case 89 : /* fall through */
+ case 90 : /* fall through */
+ case 91 : /* fall through */
+ case 92 : /* fall through */
+ case 93 : /* fall through */
+ case 94 : /* fall through */
+ case 95 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 96 : /* fall through */
+ case 97 : /* fall through */
+ case 98 : /* fall through */
+ case 99 : /* fall through */
+ case 100 : /* fall through */
+ case 101 : /* fall through */
+ case 102 : /* fall through */
+ case 103 : /* fall through */
+ case 104 : /* fall through */
+ case 105 : /* fall through */
+ case 106 : /* fall through */
+ case 107 : /* fall through */
+ case 108 : /* fall through */
+ case 109 : /* fall through */
+ case 110 : /* fall through */
+ case 111 : /* fall through */
+ case 112 : /* fall through */
+ case 113 : /* fall through */
+ case 114 : /* fall through */
+ case 115 : /* fall through */
+ case 116 : /* fall through */
+ case 117 : /* fall through */
+ case 118 : /* fall through */
+ case 119 : /* fall through */
+ case 120 : /* fall through */
+ case 121 : /* fall through */
+ case 122 : /* fall through */
+ case 123 : /* fall through */
+ case 124 : /* fall through */
+ case 125 : /* fall through */
+ case 126 : /* fall through */
+ case 127 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 304 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = A5F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = A5F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28300000)
+ { itype = A5F_INSN_MULULW_L_R_R__RA__RC; goto extract_sfmt_mullw_L_r_r__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 305 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = A5F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = A5F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = A5F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = A5F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28310000)
+ { itype = A5F_INSN_MULLW_L_R_R__RA__RC; goto extract_sfmt_mullw_L_r_r__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 307 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = A5F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = A5F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = A5F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = A5F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28330000)
+ { itype = A5F_INSN_MACLW_L_R_R__RA__RC; goto extract_sfmt_maclw_L_r_r__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 309 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = A5F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = A5F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = A5F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = A5F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28350000)
+ { itype = A5F_INSN_MACHULW_L_R_R__RA__RC; goto extract_sfmt_machulw_L_r_r__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 310 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = A5F_INSN_BL; goto extract_sfmt_bl; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = A5F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28360000)
+ { itype = A5F_INSN_MACHLW_L_R_R__RA__RC; goto extract_sfmt_maclw_L_r_r__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 320 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = A5F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = A5F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28400000)
+ { itype = A5F_INSN_ASL_L_U6__RA_; goto extract_sfmt_asl_L_u6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 321 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = A5F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = A5F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = A5F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = A5F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28410000)
+ { itype = A5F_INSN_LSR_L_U6__RA_; goto extract_sfmt_asl_L_u6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 322 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = A5F_INSN_BL; goto extract_sfmt_bl; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = A5F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28420000)
+ { itype = A5F_INSN_ASR_L_U6__RA_; goto extract_sfmt_asl_L_u6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 323 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = A5F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = A5F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = A5F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = A5F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28430000)
+ { itype = A5F_INSN_ROR_L_U6__RA_; goto extract_sfmt_asl_L_u6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 324 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = A5F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = A5F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28440000)
+ { itype = A5F_INSN_MUL64_L_U6_; goto extract_sfmt_mul64_L_u6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 325 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = A5F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = A5F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = A5F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = A5F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28450000)
+ { itype = A5F_INSN_MULU64_L_U6_; goto extract_sfmt_mul64_L_u6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 326 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = A5F_INSN_BL; goto extract_sfmt_bl; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = A5F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28460000)
+ { itype = A5F_INSN_ADDS_L_U6__RA_; goto extract_sfmt_adds_L_u6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 327 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = A5F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = A5F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = A5F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = A5F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28470000)
+ { itype = A5F_INSN_SUBS_L_U6__RA_; goto extract_sfmt_adds_L_u6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 328 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = A5F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = A5F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28480000)
+ { itype = A5F_INSN_DIVAW_L_U6__RA_; goto extract_sfmt_divaw_L_u6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 330 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = A5F_INSN_BL; goto extract_sfmt_bl; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = A5F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x284a0000)
+ { itype = A5F_INSN_ASLS_L_U6__RA_; goto extract_sfmt_asls_L_u6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 331 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = A5F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = A5F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = A5F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = A5F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x284b0000)
+ { itype = A5F_INSN_ASRS_L_U6__RA_; goto extract_sfmt_asls_L_u6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 360 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = A5F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = A5F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28680000)
+ { itype = A5F_INSN_ADDSDW_L_U6__RA_; goto extract_sfmt_asls_L_u6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 361 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = A5F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = A5F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = A5F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = A5F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28690000)
+ { itype = A5F_INSN_SUBSDW_L_U6__RA_; goto extract_sfmt_asls_L_u6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 367 :
+ {
+ unsigned int val = (((insn >> 25) & (1 << 6)) | ((insn >> 24) & (1 << 5)) | ((insn >> 1) & (3 << 3)) | ((insn >> 0) & (7 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = A5F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = A5F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 16 : /* fall through */
+ case 17 : /* fall through */
+ case 18 : /* fall through */
+ case 19 : /* fall through */
+ case 20 : /* fall through */
+ case 21 : /* fall through */
+ case 22 : /* fall through */
+ case 23 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = A5F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 24 : /* fall through */
+ case 25 : /* fall through */
+ case 26 : /* fall through */
+ case 27 : /* fall through */
+ case 28 : /* fall through */
+ case 29 : /* fall through */
+ case 30 : /* fall through */
+ case 31 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = A5F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 32 :
+ {
+ unsigned int val = (((insn >> 3) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x286f0000)
+ { itype = A5F_INSN_SWAP_L_U6_; goto extract_sfmt_swap_L_u6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8ff003f) == 0x286f0008)
+ { itype = A5F_INSN_NORMW_L_U6_; goto extract_sfmt_swap_L_u6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 33 :
+ if ((entire_insn & 0xf8ff003f) == 0x286f0001)
+ { itype = A5F_INSN_NORM_L_U6_; goto extract_sfmt_norm_L_u6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 35 :
+ if ((entire_insn & 0xf8ff003f) == 0x286f0003)
+ { itype = A5F_INSN_RND16_L_U6_; goto extract_sfmt_rnd16_L_u6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 36 :
+ if ((entire_insn & 0xf8ff003f) == 0x286f0004)
+ { itype = A5F_INSN_ABSSW_L_U6_; goto extract_sfmt_abssw_L_u6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 37 :
+ if ((entire_insn & 0xf8ff003f) == 0x286f0005)
+ { itype = A5F_INSN_ABSS_L_U6_; goto extract_sfmt_abss_L_u6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 38 :
+ if ((entire_insn & 0xf8ff003f) == 0x286f0006)
+ { itype = A5F_INSN_NEGSW_L_U6_; goto extract_sfmt_abssw_L_u6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 39 :
+ if ((entire_insn & 0xf8ff003f) == 0x286f0007)
+ { itype = A5F_INSN_NEGS_L_U6_; goto extract_sfmt_rnd16_L_u6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 64 : /* fall through */
+ case 65 : /* fall through */
+ case 66 : /* fall through */
+ case 67 : /* fall through */
+ case 68 : /* fall through */
+ case 69 : /* fall through */
+ case 70 : /* fall through */
+ case 71 : /* fall through */
+ case 72 : /* fall through */
+ case 73 : /* fall through */
+ case 74 : /* fall through */
+ case 75 : /* fall through */
+ case 76 : /* fall through */
+ case 77 : /* fall through */
+ case 78 : /* fall through */
+ case 79 : /* fall through */
+ case 80 : /* fall through */
+ case 81 : /* fall through */
+ case 82 : /* fall through */
+ case 83 : /* fall through */
+ case 84 : /* fall through */
+ case 85 : /* fall through */
+ case 86 : /* fall through */
+ case 87 : /* fall through */
+ case 88 : /* fall through */
+ case 89 : /* fall through */
+ case 90 : /* fall through */
+ case 91 : /* fall through */
+ case 92 : /* fall through */
+ case 93 : /* fall through */
+ case 94 : /* fall through */
+ case 95 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 96 : /* fall through */
+ case 97 : /* fall through */
+ case 98 : /* fall through */
+ case 99 : /* fall through */
+ case 100 : /* fall through */
+ case 101 : /* fall through */
+ case 102 : /* fall through */
+ case 103 : /* fall through */
+ case 104 : /* fall through */
+ case 105 : /* fall through */
+ case 106 : /* fall through */
+ case 107 : /* fall through */
+ case 108 : /* fall through */
+ case 109 : /* fall through */
+ case 110 : /* fall through */
+ case 111 : /* fall through */
+ case 112 : /* fall through */
+ case 113 : /* fall through */
+ case 114 : /* fall through */
+ case 115 : /* fall through */
+ case 116 : /* fall through */
+ case 117 : /* fall through */
+ case 118 : /* fall through */
+ case 119 : /* fall through */
+ case 120 : /* fall through */
+ case 121 : /* fall through */
+ case 122 : /* fall through */
+ case 123 : /* fall through */
+ case 124 : /* fall through */
+ case 125 : /* fall through */
+ case 126 : /* fall through */
+ case 127 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 368 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = A5F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = A5F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28700000)
+ { itype = A5F_INSN_MULULW_L_U6__RA_; goto extract_sfmt_mullw_L_u6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 369 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = A5F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = A5F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = A5F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = A5F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28710000)
+ { itype = A5F_INSN_MULLW_L_U6__RA_; goto extract_sfmt_mullw_L_u6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 371 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = A5F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = A5F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = A5F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = A5F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28730000)
+ { itype = A5F_INSN_MACLW_L_U6__RA_; goto extract_sfmt_maclw_L_u6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 373 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = A5F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = A5F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = A5F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = A5F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28750000)
+ { itype = A5F_INSN_MACHULW_L_U6__RA_; goto extract_sfmt_machulw_L_u6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 374 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = A5F_INSN_BL; goto extract_sfmt_bl; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = A5F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28760000)
+ { itype = A5F_INSN_MACHLW_L_U6__RA_; goto extract_sfmt_maclw_L_u6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 384 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = A5F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = A5F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28800000)
+ { itype = A5F_INSN_ASL_L_S12__RA_; goto extract_sfmt_asl_L_s12__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 385 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = A5F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = A5F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = A5F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = A5F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28810000)
+ { itype = A5F_INSN_LSR_L_S12__RA_; goto extract_sfmt_asl_L_s12__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 386 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = A5F_INSN_BL; goto extract_sfmt_bl; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = A5F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28820000)
+ { itype = A5F_INSN_ASR_L_S12__RA_; goto extract_sfmt_asl_L_s12__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 387 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = A5F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = A5F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = A5F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = A5F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28830000)
+ { itype = A5F_INSN_ROR_L_S12__RA_; goto extract_sfmt_asl_L_s12__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 388 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = A5F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = A5F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28840000)
+ { itype = A5F_INSN_MUL64_L_S12_; goto extract_sfmt_mul64_L_s12_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 389 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = A5F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = A5F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = A5F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = A5F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28850000)
+ { itype = A5F_INSN_MULU64_L_S12_; goto extract_sfmt_mul64_L_s12_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 390 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = A5F_INSN_BL; goto extract_sfmt_bl; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = A5F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28860000)
+ { itype = A5F_INSN_ADDS_L_S12__RA_; goto extract_sfmt_adds_L_s12__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 391 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = A5F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = A5F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = A5F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = A5F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28870000)
+ { itype = A5F_INSN_SUBS_L_S12__RA_; goto extract_sfmt_adds_L_s12__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 392 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = A5F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = A5F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28880000)
+ { itype = A5F_INSN_DIVAW_L_S12__RA_; goto extract_sfmt_divaw_L_s12__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 394 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = A5F_INSN_BL; goto extract_sfmt_bl; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = A5F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x288a0000)
+ { itype = A5F_INSN_ASLS_L_S12__RA_; goto extract_sfmt_asls_L_s12__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 395 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = A5F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = A5F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = A5F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = A5F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x288b0000)
+ { itype = A5F_INSN_ASRS_L_S12__RA_; goto extract_sfmt_asls_L_s12__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 424 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = A5F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = A5F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28a80000)
+ { itype = A5F_INSN_ADDSDW_L_S12__RA_; goto extract_sfmt_asls_L_s12__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 425 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = A5F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = A5F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = A5F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = A5F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28a90000)
+ { itype = A5F_INSN_SUBSDW_L_S12__RA_; goto extract_sfmt_asls_L_s12__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 432 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = A5F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = A5F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28b00000)
+ { itype = A5F_INSN_MULULW_L_S12__RA_; goto extract_sfmt_mullw_L_s12__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 433 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = A5F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = A5F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = A5F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = A5F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28b10000)
+ { itype = A5F_INSN_MULLW_L_S12__RA_; goto extract_sfmt_mullw_L_s12__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 435 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = A5F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = A5F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = A5F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = A5F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28b30000)
+ { itype = A5F_INSN_MACLW_L_S12__RA_; goto extract_sfmt_maclw_L_s12__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 437 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = A5F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = A5F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = A5F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = A5F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28b50000)
+ { itype = A5F_INSN_MACHULW_L_S12__RA_; goto extract_sfmt_machulw_L_s12__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 438 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = A5F_INSN_BL; goto extract_sfmt_bl; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = A5F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28b60000)
+ { itype = A5F_INSN_MACHLW_L_S12__RA_; goto extract_sfmt_maclw_L_s12__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 448 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = A5F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = A5F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c00000)
+ { itype = A5F_INSN_ASL_CC__RA__RC; goto extract_sfmt_asl_cc__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c00020)
+ { itype = A5F_INSN_ASL_CCU6__RA_; goto extract_sfmt_asl_ccu6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 449 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = A5F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = A5F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = A5F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = A5F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c10000)
+ { itype = A5F_INSN_LSR_CC__RA__RC; goto extract_sfmt_asl_cc__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c10020)
+ { itype = A5F_INSN_LSR_CCU6__RA_; goto extract_sfmt_asl_ccu6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 450 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = A5F_INSN_BL; goto extract_sfmt_bl; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = A5F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c20000)
+ { itype = A5F_INSN_ASR_CC__RA__RC; goto extract_sfmt_asl_cc__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c20020)
+ { itype = A5F_INSN_ASR_CCU6__RA_; goto extract_sfmt_asl_ccu6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 451 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = A5F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = A5F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = A5F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = A5F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c30000)
+ { itype = A5F_INSN_ROR_CC__RA__RC; goto extract_sfmt_asl_cc__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c30020)
+ { itype = A5F_INSN_ROR_CCU6__RA_; goto extract_sfmt_asl_ccu6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 452 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = A5F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = A5F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c40000)
+ { itype = A5F_INSN_MUL64_CC__RC; goto extract_sfmt_mul64_cc__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c40020)
+ { itype = A5F_INSN_MUL64_CCU6_; goto extract_sfmt_mul64_ccu6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 453 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = A5F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = A5F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = A5F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = A5F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c50000)
+ { itype = A5F_INSN_MULU64_CC__RC; goto extract_sfmt_mul64_cc__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c50020)
+ { itype = A5F_INSN_MULU64_CCU6_; goto extract_sfmt_mul64_ccu6_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 454 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = A5F_INSN_BL; goto extract_sfmt_bl; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = A5F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c60000)
+ { itype = A5F_INSN_ADDS_CC__RA__RC; goto extract_sfmt_adds_cc__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c60020)
+ { itype = A5F_INSN_ADDS_CCU6__RA_; goto extract_sfmt_adds_ccu6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 455 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = A5F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = A5F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = A5F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = A5F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c70000)
+ { itype = A5F_INSN_SUBS_CC__RA__RC; goto extract_sfmt_adds_cc__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c70020)
+ { itype = A5F_INSN_SUBS_CCU6__RA_; goto extract_sfmt_adds_ccu6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 456 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = A5F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = A5F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c80000)
+ { itype = A5F_INSN_DIVAW_CC__RA__RC; goto extract_sfmt_divaw_cc__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c80020)
+ { itype = A5F_INSN_DIVAW_CCU6__RA_; goto extract_sfmt_divaw_ccu6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 458 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = A5F_INSN_BL; goto extract_sfmt_bl; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = A5F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x28ca0000)
+ { itype = A5F_INSN_ASLS_CC__RA__RC; goto extract_sfmt_asls_cc__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x28ca0020)
+ { itype = A5F_INSN_ASLS_CCU6__RA_; goto extract_sfmt_asls_ccu6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 459 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = A5F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = A5F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = A5F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = A5F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8ff0020) == 0x28cb0000)
+ { itype = A5F_INSN_ASRS_CC__RA__RC; goto extract_sfmt_asls_cc__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0020) == 0x28cb0020)
+ { itype = A5F_INSN_ASRS_CCU6__RA_; goto extract_sfmt_asls_ccu6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 488 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = A5F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = A5F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x28e80000)
+ { itype = A5F_INSN_ADDSDW_CC__RA__RC; goto extract_sfmt_asls_cc__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x28e80020)
+ { itype = A5F_INSN_ADDSDW_CCU6__RA_; goto extract_sfmt_asls_ccu6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 489 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = A5F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = A5F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = A5F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = A5F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8ff0020) == 0x28e90000)
+ { itype = A5F_INSN_SUBSDW_CC__RA__RC; goto extract_sfmt_asls_cc__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0020) == 0x28e90020)
+ { itype = A5F_INSN_SUBSDW_CCU6__RA_; goto extract_sfmt_asls_ccu6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 496 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = A5F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = A5F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x28f00000)
+ { itype = A5F_INSN_MULULW_CC__RA__RC; goto extract_sfmt_mullw_cc__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x28f00020)
+ { itype = A5F_INSN_MULULW_CCU6__RA_; goto extract_sfmt_mullw_ccu6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 497 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = A5F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = A5F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = A5F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = A5F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8ff0020) == 0x28f10000)
+ { itype = A5F_INSN_MULLW_CC__RA__RC; goto extract_sfmt_mullw_cc__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0020) == 0x28f10020)
+ { itype = A5F_INSN_MULLW_CCU6__RA_; goto extract_sfmt_mullw_ccu6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 499 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = A5F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = A5F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = A5F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = A5F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8ff0020) == 0x28f30000)
+ { itype = A5F_INSN_MACLW_CC__RA__RC; goto extract_sfmt_maclw_cc__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0020) == 0x28f30020)
+ { itype = A5F_INSN_MACLW_CCU6__RA_; goto extract_sfmt_maclw_ccu6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 501 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = A5F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = A5F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = A5F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = A5F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8ff0020) == 0x28f50000)
+ { itype = A5F_INSN_MACHULW_CC__RA__RC; goto extract_sfmt_machulw_cc__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0020) == 0x28f50020)
+ { itype = A5F_INSN_MACHULW_CCU6__RA_; goto extract_sfmt_machulw_ccu6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 502 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = A5F_INSN_BL; goto extract_sfmt_bl; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = A5F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x28f60000)
+ { itype = A5F_INSN_MACHLW_CC__RA__RC; goto extract_sfmt_maclw_cc__RA__RC; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x28f60020)
+ { itype = A5F_INSN_MACHLW_CCU6__RA_; goto extract_sfmt_maclw_ccu6__RA_; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = A5F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = A5F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 512 : /* fall through */
+ case 513 : /* fall through */
+ case 514 : /* fall through */
+ case 515 : /* fall through */
+ case 516 : /* fall through */
+ case 517 : /* fall through */
+ case 518 : /* fall through */
+ case 519 : /* fall through */
+ case 520 : /* fall through */
+ case 521 : /* fall through */
+ case 522 : /* fall through */
+ case 523 : /* fall through */
+ case 524 : /* fall through */
+ case 525 : /* fall through */
+ case 526 : /* fall through */
+ case 527 : /* fall through */
+ case 528 : /* fall through */
+ case 529 : /* fall through */
+ case 530 : /* fall through */
+ case 531 : /* fall through */
+ case 532 : /* fall through */
+ case 533 : /* fall through */
+ case 534 : /* fall through */
+ case 535 : /* fall through */
+ case 536 : /* fall through */
+ case 537 : /* fall through */
+ case 538 : /* fall through */
+ case 539 : /* fall through */
+ case 540 : /* fall through */
+ case 541 : /* fall through */
+ case 542 : /* fall through */
+ case 543 : /* fall through */
+ case 544 : /* fall through */
+ case 545 : /* fall through */
+ case 546 : /* fall through */
+ case 547 : /* fall through */
+ case 548 : /* fall through */
+ case 549 : /* fall through */
+ case 550 : /* fall through */
+ case 551 : /* fall through */
+ case 552 : /* fall through */
+ case 553 : /* fall through */
+ case 554 : /* fall through */
+ case 555 : /* fall through */
+ case 556 : /* fall through */
+ case 557 : /* fall through */
+ case 558 : /* fall through */
+ case 559 : /* fall through */
+ case 560 : /* fall through */
+ case 561 : /* fall through */
+ case 562 : /* fall through */
+ case 563 : /* fall through */
+ case 564 : /* fall through */
+ case 565 : /* fall through */
+ case 566 : /* fall through */
+ case 567 : /* fall through */
+ case 568 : /* fall through */
+ case 569 : /* fall through */
+ case 570 : /* fall through */
+ case 571 : /* fall through */
+ case 572 : /* fall through */
+ case 573 : /* fall through */
+ case 574 : /* fall through */
+ case 575 : /* fall through */
+ case 576 : /* fall through */
+ case 577 : /* fall through */
+ case 578 : /* fall through */
+ case 579 : /* fall through */
+ case 580 : /* fall through */
+ case 581 : /* fall through */
+ case 582 : /* fall through */
+ case 583 : /* fall through */
+ case 584 : /* fall through */
+ case 585 : /* fall through */
+ case 586 : /* fall through */
+ case 587 : /* fall through */
+ case 588 : /* fall through */
+ case 589 : /* fall through */
+ case 590 : /* fall through */
+ case 591 : /* fall through */
+ case 592 : /* fall through */
+ case 593 : /* fall through */
+ case 594 : /* fall through */
+ case 595 : /* fall through */
+ case 596 : /* fall through */
+ case 597 : /* fall through */
+ case 598 : /* fall through */
+ case 599 : /* fall through */
+ case 600 : /* fall through */
+ case 601 : /* fall through */
+ case 602 : /* fall through */
+ case 603 : /* fall through */
+ case 604 : /* fall through */
+ case 605 : /* fall through */
+ case 606 : /* fall through */
+ case 607 : /* fall through */
+ case 608 : /* fall through */
+ case 609 : /* fall through */
+ case 610 : /* fall through */
+ case 611 : /* fall through */
+ case 612 : /* fall through */
+ case 613 : /* fall through */
+ case 614 : /* fall through */
+ case 615 : /* fall through */
+ case 616 : /* fall through */
+ case 617 : /* fall through */
+ case 618 : /* fall through */
+ case 619 : /* fall through */
+ case 620 : /* fall through */
+ case 621 : /* fall through */
+ case 622 : /* fall through */
+ case 623 : /* fall through */
+ case 624 : /* fall through */
+ case 625 : /* fall through */
+ case 626 : /* fall through */
+ case 627 : /* fall through */
+ case 628 : /* fall through */
+ case 629 : /* fall through */
+ case 630 : /* fall through */
+ case 631 : /* fall through */
+ case 632 : /* fall through */
+ case 633 : /* fall through */
+ case 634 : /* fall through */
+ case 635 : /* fall through */
+ case 636 : /* fall through */
+ case 637 : /* fall through */
+ case 638 : /* fall through */
+ case 639 : /* fall through */
+ case 640 : /* fall through */
+ case 641 : /* fall through */
+ case 642 : /* fall through */
+ case 643 : /* fall through */
+ case 644 : /* fall through */
+ case 645 : /* fall through */
+ case 646 : /* fall through */
+ case 647 : /* fall through */
+ case 648 : /* fall through */
+ case 649 : /* fall through */
+ case 650 : /* fall through */
+ case 651 : /* fall through */
+ case 652 : /* fall through */
+ case 653 : /* fall through */
+ case 654 : /* fall through */
+ case 655 : /* fall through */
+ case 656 : /* fall through */
+ case 657 : /* fall through */
+ case 658 : /* fall through */
+ case 659 : /* fall through */
+ case 660 : /* fall through */
+ case 661 : /* fall through */
+ case 662 : /* fall through */
+ case 663 : /* fall through */
+ case 664 : /* fall through */
+ case 665 : /* fall through */
+ case 666 : /* fall through */
+ case 667 : /* fall through */
+ case 668 : /* fall through */
+ case 669 : /* fall through */
+ case 670 : /* fall through */
+ case 671 : /* fall through */
+ case 672 : /* fall through */
+ case 673 : /* fall through */
+ case 674 : /* fall through */
+ case 675 : /* fall through */
+ case 676 : /* fall through */
+ case 677 : /* fall through */
+ case 678 : /* fall through */
+ case 679 : /* fall through */
+ case 680 : /* fall through */
+ case 681 : /* fall through */
+ case 682 : /* fall through */
+ case 683 : /* fall through */
+ case 684 : /* fall through */
+ case 685 : /* fall through */
+ case 686 : /* fall through */
+ case 687 : /* fall through */
+ case 688 : /* fall through */
+ case 689 : /* fall through */
+ case 690 : /* fall through */
+ case 691 : /* fall through */
+ case 692 : /* fall through */
+ case 693 : /* fall through */
+ case 694 : /* fall through */
+ case 695 : /* fall through */
+ case 696 : /* fall through */
+ case 697 : /* fall through */
+ case 698 : /* fall through */
+ case 699 : /* fall through */
+ case 700 : /* fall through */
+ case 701 : /* fall through */
+ case 702 : /* fall through */
+ case 703 : /* fall through */
+ case 704 : /* fall through */
+ case 705 : /* fall through */
+ case 706 : /* fall through */
+ case 707 : /* fall through */
+ case 708 : /* fall through */
+ case 709 : /* fall through */
+ case 710 : /* fall through */
+ case 711 : /* fall through */
+ case 712 : /* fall through */
+ case 713 : /* fall through */
+ case 714 : /* fall through */
+ case 715 : /* fall through */
+ case 716 : /* fall through */
+ case 717 : /* fall through */
+ case 718 : /* fall through */
+ case 719 : /* fall through */
+ case 720 : /* fall through */
+ case 721 : /* fall through */
+ case 722 : /* fall through */
+ case 723 : /* fall through */
+ case 724 : /* fall through */
+ case 725 : /* fall through */
+ case 726 : /* fall through */
+ case 727 : /* fall through */
+ case 728 : /* fall through */
+ case 729 : /* fall through */
+ case 730 : /* fall through */
+ case 731 : /* fall through */
+ case 732 : /* fall through */
+ case 733 : /* fall through */
+ case 734 : /* fall through */
+ case 735 : /* fall through */
+ case 736 : /* fall through */
+ case 737 : /* fall through */
+ case 738 : /* fall through */
+ case 739 : /* fall through */
+ case 740 : /* fall through */
+ case 741 : /* fall through */
+ case 742 : /* fall through */
+ case 743 : /* fall through */
+ case 744 : /* fall through */
+ case 745 : /* fall through */
+ case 746 : /* fall through */
+ case 747 : /* fall through */
+ case 748 : /* fall through */
+ case 749 : /* fall through */
+ case 750 : /* fall through */
+ case 751 : /* fall through */
+ case 752 : /* fall through */
+ case 753 : /* fall through */
+ case 754 : /* fall through */
+ case 755 : /* fall through */
+ case 756 : /* fall through */
+ case 757 : /* fall through */
+ case 758 : /* fall through */
+ case 759 : /* fall through */
+ case 760 : /* fall through */
+ case 761 : /* fall through */
+ case 762 : /* fall through */
+ case 763 : /* fall through */
+ case 764 : /* fall through */
+ case 765 : /* fall through */
+ case 766 : /* fall through */
+ case 767 :
+ {
+ unsigned int val = (((insn >> 25) & (1 << 6)) | ((insn >> 24) & (1 << 5)) | ((insn >> 6) & (31 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf80007c0) == 0x10000000)
+ { itype = A5F_INSN_LD_ABS; goto extract_sfmt_ld_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf80007c0) == 0x10000080)
+ { itype = A5F_INSN_LDB_ABS; goto extract_sfmt_ldb_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf80007c0) == 0x100000c0)
+ { itype = A5F_INSN_LDB_X_ABS; goto extract_sfmt_ldb_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xf80007c0) == 0x10000100)
+ { itype = A5F_INSN_LDW_ABS; goto extract_sfmt_ldw_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xf80007c0) == 0x10000140)
+ { itype = A5F_INSN_LDW_X_ABS; goto extract_sfmt_ldw_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 :
+ if ((entire_insn & 0xf80007c0) == 0x10000200)
+ { itype = A5F_INSN_LD__AW_ABS; goto extract_sfmt_ld__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 10 :
+ if ((entire_insn & 0xf80007c0) == 0x10000280)
+ { itype = A5F_INSN_LDB__AW_ABS; goto extract_sfmt_ldb__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 11 :
+ if ((entire_insn & 0xf80007c0) == 0x100002c0)
+ { itype = A5F_INSN_LDB__AW_X_ABS; goto extract_sfmt_ldb__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 :
+ if ((entire_insn & 0xf80007c0) == 0x10000300)
+ { itype = A5F_INSN_LDW__AW_ABS; goto extract_sfmt_ldw__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 13 :
+ if ((entire_insn & 0xf80007c0) == 0x10000340)
+ { itype = A5F_INSN_LDW__AW_X_ABS; goto extract_sfmt_ldw__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 16 :
+ if ((entire_insn & 0xf80007c0) == 0x10000400)
+ { itype = A5F_INSN_LD_AB_ABS; goto extract_sfmt_ld__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 18 :
+ if ((entire_insn & 0xf80007c0) == 0x10000480)
+ { itype = A5F_INSN_LDB_AB_ABS; goto extract_sfmt_ldb__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 19 :
+ if ((entire_insn & 0xf80007c0) == 0x100004c0)
+ { itype = A5F_INSN_LDB_AB_X_ABS; goto extract_sfmt_ldb__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 20 :
+ if ((entire_insn & 0xf80007c0) == 0x10000500)
+ { itype = A5F_INSN_LDW_AB_ABS; goto extract_sfmt_ldw__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 21 :
+ if ((entire_insn & 0xf80007c0) == 0x10000540)
+ { itype = A5F_INSN_LDW_AB_X_ABS; goto extract_sfmt_ldw__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 24 :
+ if ((entire_insn & 0xf80007c0) == 0x10000600)
+ { itype = A5F_INSN_LD_AS_ABS; goto extract_sfmt_ld_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 26 :
+ if ((entire_insn & 0xf80007c0) == 0x10000680)
+ { itype = A5F_INSN_LDB_AS_ABS; goto extract_sfmt_ldb_as_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 27 :
+ if ((entire_insn & 0xf80007c0) == 0x100006c0)
+ { itype = A5F_INSN_LDB_AS_X_ABS; goto extract_sfmt_ldb_as_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 28 :
+ if ((entire_insn & 0xf80007c0) == 0x10000700)
+ { itype = A5F_INSN_LDW_AS_ABS; goto extract_sfmt_ldw_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 29 :
+ if ((entire_insn & 0xf80007c0) == 0x10000740)
+ { itype = A5F_INSN_LDW_AS_X_ABS; goto extract_sfmt_ldw_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 64 : /* fall through */
+ case 65 : /* fall through */
+ case 66 : /* fall through */
+ case 67 : /* fall through */
+ case 68 : /* fall through */
+ case 69 : /* fall through */
+ case 70 : /* fall through */
+ case 71 : /* fall through */
+ case 72 : /* fall through */
+ case 73 : /* fall through */
+ case 74 : /* fall through */
+ case 75 : /* fall through */
+ case 76 : /* fall through */
+ case 77 : /* fall through */
+ case 78 : /* fall through */
+ case 79 : /* fall through */
+ case 80 : /* fall through */
+ case 81 : /* fall through */
+ case 82 : /* fall through */
+ case 83 : /* fall through */
+ case 84 : /* fall through */
+ case 85 : /* fall through */
+ case 86 : /* fall through */
+ case 87 : /* fall through */
+ case 88 : /* fall through */
+ case 89 : /* fall through */
+ case 90 : /* fall through */
+ case 91 : /* fall through */
+ case 92 : /* fall through */
+ case 93 : /* fall through */
+ case 94 : /* fall through */
+ case 95 :
+ if ((entire_insn & 0xf8000000) == 0x90000000)
+ { itype = A5F_INSN_LDW_S_ABU; goto extract_sfmt_ldw_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 96 : /* fall through */
+ case 97 : /* fall through */
+ case 98 : /* fall through */
+ case 99 : /* fall through */
+ case 100 : /* fall through */
+ case 101 : /* fall through */
+ case 102 : /* fall through */
+ case 103 : /* fall through */
+ case 104 : /* fall through */
+ case 105 : /* fall through */
+ case 106 : /* fall through */
+ case 107 : /* fall through */
+ case 108 : /* fall through */
+ case 109 : /* fall through */
+ case 110 : /* fall through */
+ case 111 : /* fall through */
+ case 112 : /* fall through */
+ case 113 : /* fall through */
+ case 114 : /* fall through */
+ case 115 : /* fall through */
+ case 116 : /* fall through */
+ case 117 : /* fall through */
+ case 118 : /* fall through */
+ case 119 : /* fall through */
+ case 120 : /* fall through */
+ case 121 : /* fall through */
+ case 122 : /* fall through */
+ case 123 : /* fall through */
+ case 124 : /* fall through */
+ case 125 : /* fall through */
+ case 126 : /* fall through */
+ case 127 :
+ if ((entire_insn & 0xf8000000) == 0xb0000000)
+ { itype = A5F_INSN_STW_S_ABU; goto extract_sfmt_stw_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 768 : /* fall through */
+ case 769 : /* fall through */
+ case 770 : /* fall through */
+ case 771 : /* fall through */
+ case 772 : /* fall through */
+ case 773 : /* fall through */
+ case 774 : /* fall through */
+ case 775 : /* fall through */
+ case 776 : /* fall through */
+ case 777 : /* fall through */
+ case 778 : /* fall through */
+ case 779 : /* fall through */
+ case 780 : /* fall through */
+ case 781 : /* fall through */
+ case 782 : /* fall through */
+ case 783 : /* fall through */
+ case 784 : /* fall through */
+ case 785 : /* fall through */
+ case 786 : /* fall through */
+ case 787 : /* fall through */
+ case 788 : /* fall through */
+ case 789 : /* fall through */
+ case 790 : /* fall through */
+ case 791 : /* fall through */
+ case 792 : /* fall through */
+ case 793 : /* fall through */
+ case 794 : /* fall through */
+ case 795 : /* fall through */
+ case 796 : /* fall through */
+ case 797 : /* fall through */
+ case 798 : /* fall through */
+ case 799 :
+ {
+ unsigned int val = (((insn >> 26) & (1 << 5)) | ((insn >> 25) & (1 << 4)) | ((insn >> 1) & (15 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf800001f) == 0x18000000)
+ { itype = A5F_INSN_ST_ABS; goto extract_sfmt_st_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf800001f) == 0x18000002)
+ { itype = A5F_INSN_STB_ABS; goto extract_sfmt_stb_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf800001f) == 0x18000004)
+ { itype = A5F_INSN_STW_ABS; goto extract_sfmt_stw_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xf800001f) == 0x18000008)
+ { itype = A5F_INSN_ST__AW_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xf800001f) == 0x1800000a)
+ { itype = A5F_INSN_STB__AW_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 :
+ if ((entire_insn & 0xf800001f) == 0x1800000c)
+ { itype = A5F_INSN_STW__AW_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 :
+ if ((entire_insn & 0xf800001f) == 0x18000010)
+ { itype = A5F_INSN_ST_AB_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 9 :
+ if ((entire_insn & 0xf800001f) == 0x18000012)
+ { itype = A5F_INSN_STB_AB_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 10 :
+ if ((entire_insn & 0xf800001f) == 0x18000014)
+ { itype = A5F_INSN_STW_AB_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 :
+ if ((entire_insn & 0xf800001f) == 0x18000018)
+ { itype = A5F_INSN_ST_AS_ABS; goto extract_sfmt_st_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 13 :
+ if ((entire_insn & 0xf800001f) == 0x1800001a)
+ { itype = A5F_INSN_STB_AS_ABS; goto extract_sfmt_stb_as_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 14 :
+ if ((entire_insn & 0xf800001f) == 0x1800001c)
+ { itype = A5F_INSN_STW_AS_ABS; goto extract_sfmt_stw_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 32 : /* fall through */
+ case 33 : /* fall through */
+ case 34 : /* fall through */
+ case 35 : /* fall through */
+ case 36 : /* fall through */
+ case 37 : /* fall through */
+ case 38 : /* fall through */
+ case 39 : /* fall through */
+ case 40 : /* fall through */
+ case 41 : /* fall through */
+ case 42 : /* fall through */
+ case 43 : /* fall through */
+ case 44 : /* fall through */
+ case 45 : /* fall through */
+ case 46 : /* fall through */
+ case 47 :
+ if ((entire_insn & 0xf8000000) == 0x98000000)
+ { itype = A5F_INSN_LDW_S_X_ABU; goto extract_sfmt_ldw_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 48 : /* fall through */
+ case 49 : /* fall through */
+ case 50 : /* fall through */
+ case 51 : /* fall through */
+ case 52 : /* fall through */
+ case 53 : /* fall through */
+ case 54 : /* fall through */
+ case 55 : /* fall through */
+ case 56 : /* fall through */
+ case 57 : /* fall through */
+ case 58 : /* fall through */
+ case 59 : /* fall through */
+ case 60 : /* fall through */
+ case 61 : /* fall through */
+ case 62 : /* fall through */
+ case 63 :
+ if ((entire_insn & 0xf8e00000) == 0xb8000000)
+ { itype = A5F_INSN_ASL_S_SSB; goto extract_sfmt_sub_s_ssb; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 800 : /* fall through */
+ case 801 : /* fall through */
+ case 802 : /* fall through */
+ case 803 : /* fall through */
+ case 804 : /* fall through */
+ case 805 : /* fall through */
+ case 806 : /* fall through */
+ case 807 : /* fall through */
+ case 808 : /* fall through */
+ case 809 : /* fall through */
+ case 810 : /* fall through */
+ case 811 : /* fall through */
+ case 812 : /* fall through */
+ case 813 : /* fall through */
+ case 814 : /* fall through */
+ case 815 : /* fall through */
+ case 816 : /* fall through */
+ case 817 : /* fall through */
+ case 818 : /* fall through */
+ case 819 : /* fall through */
+ case 820 : /* fall through */
+ case 821 : /* fall through */
+ case 822 : /* fall through */
+ case 823 : /* fall through */
+ case 824 : /* fall through */
+ case 825 : /* fall through */
+ case 826 : /* fall through */
+ case 827 : /* fall through */
+ case 828 : /* fall through */
+ case 829 : /* fall through */
+ case 830 : /* fall through */
+ case 831 :
+ {
+ unsigned int val = (((insn >> 26) & (1 << 5)) | ((insn >> 25) & (1 << 4)) | ((insn >> 1) & (15 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf800001f) == 0x18000000)
+ { itype = A5F_INSN_ST_ABS; goto extract_sfmt_st_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf800001f) == 0x18000002)
+ { itype = A5F_INSN_STB_ABS; goto extract_sfmt_stb_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf800001f) == 0x18000004)
+ { itype = A5F_INSN_STW_ABS; goto extract_sfmt_stw_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xf800001f) == 0x18000008)
+ { itype = A5F_INSN_ST__AW_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xf800001f) == 0x1800000a)
+ { itype = A5F_INSN_STB__AW_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 :
+ if ((entire_insn & 0xf800001f) == 0x1800000c)
+ { itype = A5F_INSN_STW__AW_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 :
+ if ((entire_insn & 0xf800001f) == 0x18000010)
+ { itype = A5F_INSN_ST_AB_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 9 :
+ if ((entire_insn & 0xf800001f) == 0x18000012)
+ { itype = A5F_INSN_STB_AB_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 10 :
+ if ((entire_insn & 0xf800001f) == 0x18000014)
+ { itype = A5F_INSN_STW_AB_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 :
+ if ((entire_insn & 0xf800001f) == 0x18000018)
+ { itype = A5F_INSN_ST_AS_ABS; goto extract_sfmt_st_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 13 :
+ if ((entire_insn & 0xf800001f) == 0x1800001a)
+ { itype = A5F_INSN_STB_AS_ABS; goto extract_sfmt_stb_as_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 14 :
+ if ((entire_insn & 0xf800001f) == 0x1800001c)
+ { itype = A5F_INSN_STW_AS_ABS; goto extract_sfmt_stw_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 32 : /* fall through */
+ case 33 : /* fall through */
+ case 34 : /* fall through */
+ case 35 : /* fall through */
+ case 36 : /* fall through */
+ case 37 : /* fall through */
+ case 38 : /* fall through */
+ case 39 : /* fall through */
+ case 40 : /* fall through */
+ case 41 : /* fall through */
+ case 42 : /* fall through */
+ case 43 : /* fall through */
+ case 44 : /* fall through */
+ case 45 : /* fall through */
+ case 46 : /* fall through */
+ case 47 :
+ if ((entire_insn & 0xf8000000) == 0x98000000)
+ { itype = A5F_INSN_LDW_S_X_ABU; goto extract_sfmt_ldw_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 48 : /* fall through */
+ case 49 : /* fall through */
+ case 50 : /* fall through */
+ case 51 : /* fall through */
+ case 52 : /* fall through */
+ case 53 : /* fall through */
+ case 54 : /* fall through */
+ case 55 : /* fall through */
+ case 56 : /* fall through */
+ case 57 : /* fall through */
+ case 58 : /* fall through */
+ case 59 : /* fall through */
+ case 60 : /* fall through */
+ case 61 : /* fall through */
+ case 62 : /* fall through */
+ case 63 :
+ if ((entire_insn & 0xf8e00000) == 0xb8200000)
+ { itype = A5F_INSN_LSR_S_SSB; goto extract_sfmt_sub_s_ssb; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 832 : /* fall through */
+ case 833 : /* fall through */
+ case 834 : /* fall through */
+ case 835 : /* fall through */
+ case 836 : /* fall through */
+ case 837 : /* fall through */
+ case 838 : /* fall through */
+ case 839 : /* fall through */
+ case 840 : /* fall through */
+ case 841 : /* fall through */
+ case 842 : /* fall through */
+ case 843 : /* fall through */
+ case 844 : /* fall through */
+ case 845 : /* fall through */
+ case 846 : /* fall through */
+ case 847 : /* fall through */
+ case 848 : /* fall through */
+ case 849 : /* fall through */
+ case 850 : /* fall through */
+ case 851 : /* fall through */
+ case 852 : /* fall through */
+ case 853 : /* fall through */
+ case 854 : /* fall through */
+ case 855 : /* fall through */
+ case 856 : /* fall through */
+ case 857 : /* fall through */
+ case 858 : /* fall through */
+ case 859 : /* fall through */
+ case 860 : /* fall through */
+ case 861 : /* fall through */
+ case 862 : /* fall through */
+ case 863 :
+ {
+ unsigned int val = (((insn >> 26) & (1 << 5)) | ((insn >> 25) & (1 << 4)) | ((insn >> 1) & (15 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf800001f) == 0x18000000)
+ { itype = A5F_INSN_ST_ABS; goto extract_sfmt_st_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf800001f) == 0x18000002)
+ { itype = A5F_INSN_STB_ABS; goto extract_sfmt_stb_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf800001f) == 0x18000004)
+ { itype = A5F_INSN_STW_ABS; goto extract_sfmt_stw_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xf800001f) == 0x18000008)
+ { itype = A5F_INSN_ST__AW_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xf800001f) == 0x1800000a)
+ { itype = A5F_INSN_STB__AW_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 :
+ if ((entire_insn & 0xf800001f) == 0x1800000c)
+ { itype = A5F_INSN_STW__AW_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 :
+ if ((entire_insn & 0xf800001f) == 0x18000010)
+ { itype = A5F_INSN_ST_AB_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 9 :
+ if ((entire_insn & 0xf800001f) == 0x18000012)
+ { itype = A5F_INSN_STB_AB_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 10 :
+ if ((entire_insn & 0xf800001f) == 0x18000014)
+ { itype = A5F_INSN_STW_AB_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 :
+ if ((entire_insn & 0xf800001f) == 0x18000018)
+ { itype = A5F_INSN_ST_AS_ABS; goto extract_sfmt_st_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 13 :
+ if ((entire_insn & 0xf800001f) == 0x1800001a)
+ { itype = A5F_INSN_STB_AS_ABS; goto extract_sfmt_stb_as_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 14 :
+ if ((entire_insn & 0xf800001f) == 0x1800001c)
+ { itype = A5F_INSN_STW_AS_ABS; goto extract_sfmt_stw_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 32 : /* fall through */
+ case 33 : /* fall through */
+ case 34 : /* fall through */
+ case 35 : /* fall through */
+ case 36 : /* fall through */
+ case 37 : /* fall through */
+ case 38 : /* fall through */
+ case 39 : /* fall through */
+ case 40 : /* fall through */
+ case 41 : /* fall through */
+ case 42 : /* fall through */
+ case 43 : /* fall through */
+ case 44 : /* fall through */
+ case 45 : /* fall through */
+ case 46 : /* fall through */
+ case 47 :
+ if ((entire_insn & 0xf8000000) == 0x98000000)
+ { itype = A5F_INSN_LDW_S_X_ABU; goto extract_sfmt_ldw_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 48 : /* fall through */
+ case 49 : /* fall through */
+ case 50 : /* fall through */
+ case 51 : /* fall through */
+ case 52 : /* fall through */
+ case 53 : /* fall through */
+ case 54 : /* fall through */
+ case 55 : /* fall through */
+ case 56 : /* fall through */
+ case 57 : /* fall through */
+ case 58 : /* fall through */
+ case 59 : /* fall through */
+ case 60 : /* fall through */
+ case 61 : /* fall through */
+ case 62 : /* fall through */
+ case 63 :
+ if ((entire_insn & 0xf8e00000) == 0xb8400000)
+ { itype = A5F_INSN_ASR_S_SSB; goto extract_sfmt_sub_s_ssb; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 864 : /* fall through */
+ case 865 : /* fall through */
+ case 866 : /* fall through */
+ case 867 : /* fall through */
+ case 868 : /* fall through */
+ case 869 : /* fall through */
+ case 870 : /* fall through */
+ case 871 : /* fall through */
+ case 872 : /* fall through */
+ case 873 : /* fall through */
+ case 874 : /* fall through */
+ case 875 : /* fall through */
+ case 876 : /* fall through */
+ case 877 : /* fall through */
+ case 878 : /* fall through */
+ case 879 : /* fall through */
+ case 880 : /* fall through */
+ case 881 : /* fall through */
+ case 882 : /* fall through */
+ case 883 : /* fall through */
+ case 884 : /* fall through */
+ case 885 : /* fall through */
+ case 886 : /* fall through */
+ case 887 : /* fall through */
+ case 888 : /* fall through */
+ case 889 : /* fall through */
+ case 890 : /* fall through */
+ case 891 : /* fall through */
+ case 892 : /* fall through */
+ case 893 : /* fall through */
+ case 894 : /* fall through */
+ case 895 :
+ {
+ unsigned int val = (((insn >> 26) & (1 << 5)) | ((insn >> 25) & (1 << 4)) | ((insn >> 1) & (15 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf800001f) == 0x18000000)
+ { itype = A5F_INSN_ST_ABS; goto extract_sfmt_st_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf800001f) == 0x18000002)
+ { itype = A5F_INSN_STB_ABS; goto extract_sfmt_stb_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf800001f) == 0x18000004)
+ { itype = A5F_INSN_STW_ABS; goto extract_sfmt_stw_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xf800001f) == 0x18000008)
+ { itype = A5F_INSN_ST__AW_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xf800001f) == 0x1800000a)
+ { itype = A5F_INSN_STB__AW_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 :
+ if ((entire_insn & 0xf800001f) == 0x1800000c)
+ { itype = A5F_INSN_STW__AW_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 :
+ if ((entire_insn & 0xf800001f) == 0x18000010)
+ { itype = A5F_INSN_ST_AB_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 9 :
+ if ((entire_insn & 0xf800001f) == 0x18000012)
+ { itype = A5F_INSN_STB_AB_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 10 :
+ if ((entire_insn & 0xf800001f) == 0x18000014)
+ { itype = A5F_INSN_STW_AB_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 :
+ if ((entire_insn & 0xf800001f) == 0x18000018)
+ { itype = A5F_INSN_ST_AS_ABS; goto extract_sfmt_st_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 13 :
+ if ((entire_insn & 0xf800001f) == 0x1800001a)
+ { itype = A5F_INSN_STB_AS_ABS; goto extract_sfmt_stb_as_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 14 :
+ if ((entire_insn & 0xf800001f) == 0x1800001c)
+ { itype = A5F_INSN_STW_AS_ABS; goto extract_sfmt_stw_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 32 : /* fall through */
+ case 33 : /* fall through */
+ case 34 : /* fall through */
+ case 35 : /* fall through */
+ case 36 : /* fall through */
+ case 37 : /* fall through */
+ case 38 : /* fall through */
+ case 39 : /* fall through */
+ case 40 : /* fall through */
+ case 41 : /* fall through */
+ case 42 : /* fall through */
+ case 43 : /* fall through */
+ case 44 : /* fall through */
+ case 45 : /* fall through */
+ case 46 : /* fall through */
+ case 47 :
+ if ((entire_insn & 0xf8000000) == 0x98000000)
+ { itype = A5F_INSN_LDW_S_X_ABU; goto extract_sfmt_ldw_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 48 : /* fall through */
+ case 49 : /* fall through */
+ case 50 : /* fall through */
+ case 51 : /* fall through */
+ case 52 : /* fall through */
+ case 53 : /* fall through */
+ case 54 : /* fall through */
+ case 55 : /* fall through */
+ case 56 : /* fall through */
+ case 57 : /* fall through */
+ case 58 : /* fall through */
+ case 59 : /* fall through */
+ case 60 : /* fall through */
+ case 61 : /* fall through */
+ case 62 : /* fall through */
+ case 63 :
+ if ((entire_insn & 0xf8e00000) == 0xb8600000)
+ { itype = A5F_INSN_SUB_S_SSB; goto extract_sfmt_sub_s_ssb; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 896 : /* fall through */
+ case 897 : /* fall through */
+ case 898 : /* fall through */
+ case 899 : /* fall through */
+ case 900 : /* fall through */
+ case 901 : /* fall through */
+ case 902 : /* fall through */
+ case 903 : /* fall through */
+ case 904 : /* fall through */
+ case 905 : /* fall through */
+ case 906 : /* fall through */
+ case 907 : /* fall through */
+ case 908 : /* fall through */
+ case 909 : /* fall through */
+ case 910 : /* fall through */
+ case 911 : /* fall through */
+ case 912 : /* fall through */
+ case 913 : /* fall through */
+ case 914 : /* fall through */
+ case 915 : /* fall through */
+ case 916 : /* fall through */
+ case 917 : /* fall through */
+ case 918 : /* fall through */
+ case 919 : /* fall through */
+ case 920 : /* fall through */
+ case 921 : /* fall through */
+ case 922 : /* fall through */
+ case 923 : /* fall through */
+ case 924 : /* fall through */
+ case 925 : /* fall through */
+ case 926 : /* fall through */
+ case 927 :
+ {
+ unsigned int val = (((insn >> 26) & (1 << 5)) | ((insn >> 25) & (1 << 4)) | ((insn >> 1) & (15 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf800001f) == 0x18000000)
+ { itype = A5F_INSN_ST_ABS; goto extract_sfmt_st_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf800001f) == 0x18000002)
+ { itype = A5F_INSN_STB_ABS; goto extract_sfmt_stb_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf800001f) == 0x18000004)
+ { itype = A5F_INSN_STW_ABS; goto extract_sfmt_stw_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xf800001f) == 0x18000008)
+ { itype = A5F_INSN_ST__AW_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xf800001f) == 0x1800000a)
+ { itype = A5F_INSN_STB__AW_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 :
+ if ((entire_insn & 0xf800001f) == 0x1800000c)
+ { itype = A5F_INSN_STW__AW_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 :
+ if ((entire_insn & 0xf800001f) == 0x18000010)
+ { itype = A5F_INSN_ST_AB_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 9 :
+ if ((entire_insn & 0xf800001f) == 0x18000012)
+ { itype = A5F_INSN_STB_AB_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 10 :
+ if ((entire_insn & 0xf800001f) == 0x18000014)
+ { itype = A5F_INSN_STW_AB_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 :
+ if ((entire_insn & 0xf800001f) == 0x18000018)
+ { itype = A5F_INSN_ST_AS_ABS; goto extract_sfmt_st_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 13 :
+ if ((entire_insn & 0xf800001f) == 0x1800001a)
+ { itype = A5F_INSN_STB_AS_ABS; goto extract_sfmt_stb_as_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 14 :
+ if ((entire_insn & 0xf800001f) == 0x1800001c)
+ { itype = A5F_INSN_STW_AS_ABS; goto extract_sfmt_stw_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 32 : /* fall through */
+ case 33 : /* fall through */
+ case 34 : /* fall through */
+ case 35 : /* fall through */
+ case 36 : /* fall through */
+ case 37 : /* fall through */
+ case 38 : /* fall through */
+ case 39 : /* fall through */
+ case 40 : /* fall through */
+ case 41 : /* fall through */
+ case 42 : /* fall through */
+ case 43 : /* fall through */
+ case 44 : /* fall through */
+ case 45 : /* fall through */
+ case 46 : /* fall through */
+ case 47 :
+ if ((entire_insn & 0xf8000000) == 0x98000000)
+ { itype = A5F_INSN_LDW_S_X_ABU; goto extract_sfmt_ldw_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 48 : /* fall through */
+ case 49 : /* fall through */
+ case 50 : /* fall through */
+ case 51 : /* fall through */
+ case 52 : /* fall through */
+ case 53 : /* fall through */
+ case 54 : /* fall through */
+ case 55 : /* fall through */
+ case 56 : /* fall through */
+ case 57 : /* fall through */
+ case 58 : /* fall through */
+ case 59 : /* fall through */
+ case 60 : /* fall through */
+ case 61 : /* fall through */
+ case 62 : /* fall through */
+ case 63 :
+ if ((entire_insn & 0xf8e00000) == 0xb8800000)
+ { itype = A5F_INSN_BSET_S_SSB; goto extract_sfmt_sub_s_ssb; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 928 : /* fall through */
+ case 929 : /* fall through */
+ case 930 : /* fall through */
+ case 931 : /* fall through */
+ case 932 : /* fall through */
+ case 933 : /* fall through */
+ case 934 : /* fall through */
+ case 935 : /* fall through */
+ case 936 : /* fall through */
+ case 937 : /* fall through */
+ case 938 : /* fall through */
+ case 939 : /* fall through */
+ case 940 : /* fall through */
+ case 941 : /* fall through */
+ case 942 : /* fall through */
+ case 943 : /* fall through */
+ case 944 : /* fall through */
+ case 945 : /* fall through */
+ case 946 : /* fall through */
+ case 947 : /* fall through */
+ case 948 : /* fall through */
+ case 949 : /* fall through */
+ case 950 : /* fall through */
+ case 951 : /* fall through */
+ case 952 : /* fall through */
+ case 953 : /* fall through */
+ case 954 : /* fall through */
+ case 955 : /* fall through */
+ case 956 : /* fall through */
+ case 957 : /* fall through */
+ case 958 : /* fall through */
+ case 959 :
+ {
+ unsigned int val = (((insn >> 26) & (1 << 5)) | ((insn >> 25) & (1 << 4)) | ((insn >> 1) & (15 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf800001f) == 0x18000000)
+ { itype = A5F_INSN_ST_ABS; goto extract_sfmt_st_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf800001f) == 0x18000002)
+ { itype = A5F_INSN_STB_ABS; goto extract_sfmt_stb_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf800001f) == 0x18000004)
+ { itype = A5F_INSN_STW_ABS; goto extract_sfmt_stw_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xf800001f) == 0x18000008)
+ { itype = A5F_INSN_ST__AW_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xf800001f) == 0x1800000a)
+ { itype = A5F_INSN_STB__AW_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 :
+ if ((entire_insn & 0xf800001f) == 0x1800000c)
+ { itype = A5F_INSN_STW__AW_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 :
+ if ((entire_insn & 0xf800001f) == 0x18000010)
+ { itype = A5F_INSN_ST_AB_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 9 :
+ if ((entire_insn & 0xf800001f) == 0x18000012)
+ { itype = A5F_INSN_STB_AB_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 10 :
+ if ((entire_insn & 0xf800001f) == 0x18000014)
+ { itype = A5F_INSN_STW_AB_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 :
+ if ((entire_insn & 0xf800001f) == 0x18000018)
+ { itype = A5F_INSN_ST_AS_ABS; goto extract_sfmt_st_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 13 :
+ if ((entire_insn & 0xf800001f) == 0x1800001a)
+ { itype = A5F_INSN_STB_AS_ABS; goto extract_sfmt_stb_as_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 14 :
+ if ((entire_insn & 0xf800001f) == 0x1800001c)
+ { itype = A5F_INSN_STW_AS_ABS; goto extract_sfmt_stw_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 32 : /* fall through */
+ case 33 : /* fall through */
+ case 34 : /* fall through */
+ case 35 : /* fall through */
+ case 36 : /* fall through */
+ case 37 : /* fall through */
+ case 38 : /* fall through */
+ case 39 : /* fall through */
+ case 40 : /* fall through */
+ case 41 : /* fall through */
+ case 42 : /* fall through */
+ case 43 : /* fall through */
+ case 44 : /* fall through */
+ case 45 : /* fall through */
+ case 46 : /* fall through */
+ case 47 :
+ if ((entire_insn & 0xf8000000) == 0x98000000)
+ { itype = A5F_INSN_LDW_S_X_ABU; goto extract_sfmt_ldw_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 48 : /* fall through */
+ case 49 : /* fall through */
+ case 50 : /* fall through */
+ case 51 : /* fall through */
+ case 52 : /* fall through */
+ case 53 : /* fall through */
+ case 54 : /* fall through */
+ case 55 : /* fall through */
+ case 56 : /* fall through */
+ case 57 : /* fall through */
+ case 58 : /* fall through */
+ case 59 : /* fall through */
+ case 60 : /* fall through */
+ case 61 : /* fall through */
+ case 62 : /* fall through */
+ case 63 :
+ if ((entire_insn & 0xf8e00000) == 0xb8a00000)
+ { itype = A5F_INSN_BCLR_S_SSB; goto extract_sfmt_sub_s_ssb; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 960 : /* fall through */
+ case 961 : /* fall through */
+ case 962 : /* fall through */
+ case 963 : /* fall through */
+ case 964 : /* fall through */
+ case 965 : /* fall through */
+ case 966 : /* fall through */
+ case 967 : /* fall through */
+ case 968 : /* fall through */
+ case 969 : /* fall through */
+ case 970 : /* fall through */
+ case 971 : /* fall through */
+ case 972 : /* fall through */
+ case 973 : /* fall through */
+ case 974 : /* fall through */
+ case 975 : /* fall through */
+ case 976 : /* fall through */
+ case 977 : /* fall through */
+ case 978 : /* fall through */
+ case 979 : /* fall through */
+ case 980 : /* fall through */
+ case 981 : /* fall through */
+ case 982 : /* fall through */
+ case 983 : /* fall through */
+ case 984 : /* fall through */
+ case 985 : /* fall through */
+ case 986 : /* fall through */
+ case 987 : /* fall through */
+ case 988 : /* fall through */
+ case 989 : /* fall through */
+ case 990 : /* fall through */
+ case 991 :
+ {
+ unsigned int val = (((insn >> 26) & (1 << 5)) | ((insn >> 25) & (1 << 4)) | ((insn >> 1) & (15 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf800001f) == 0x18000000)
+ { itype = A5F_INSN_ST_ABS; goto extract_sfmt_st_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf800001f) == 0x18000002)
+ { itype = A5F_INSN_STB_ABS; goto extract_sfmt_stb_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf800001f) == 0x18000004)
+ { itype = A5F_INSN_STW_ABS; goto extract_sfmt_stw_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xf800001f) == 0x18000008)
+ { itype = A5F_INSN_ST__AW_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xf800001f) == 0x1800000a)
+ { itype = A5F_INSN_STB__AW_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 :
+ if ((entire_insn & 0xf800001f) == 0x1800000c)
+ { itype = A5F_INSN_STW__AW_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 :
+ if ((entire_insn & 0xf800001f) == 0x18000010)
+ { itype = A5F_INSN_ST_AB_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 9 :
+ if ((entire_insn & 0xf800001f) == 0x18000012)
+ { itype = A5F_INSN_STB_AB_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 10 :
+ if ((entire_insn & 0xf800001f) == 0x18000014)
+ { itype = A5F_INSN_STW_AB_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 :
+ if ((entire_insn & 0xf800001f) == 0x18000018)
+ { itype = A5F_INSN_ST_AS_ABS; goto extract_sfmt_st_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 13 :
+ if ((entire_insn & 0xf800001f) == 0x1800001a)
+ { itype = A5F_INSN_STB_AS_ABS; goto extract_sfmt_stb_as_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 14 :
+ if ((entire_insn & 0xf800001f) == 0x1800001c)
+ { itype = A5F_INSN_STW_AS_ABS; goto extract_sfmt_stw_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 32 : /* fall through */
+ case 33 : /* fall through */
+ case 34 : /* fall through */
+ case 35 : /* fall through */
+ case 36 : /* fall through */
+ case 37 : /* fall through */
+ case 38 : /* fall through */
+ case 39 : /* fall through */
+ case 40 : /* fall through */
+ case 41 : /* fall through */
+ case 42 : /* fall through */
+ case 43 : /* fall through */
+ case 44 : /* fall through */
+ case 45 : /* fall through */
+ case 46 : /* fall through */
+ case 47 :
+ if ((entire_insn & 0xf8000000) == 0x98000000)
+ { itype = A5F_INSN_LDW_S_X_ABU; goto extract_sfmt_ldw_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 48 : /* fall through */
+ case 49 : /* fall through */
+ case 50 : /* fall through */
+ case 51 : /* fall through */
+ case 52 : /* fall through */
+ case 53 : /* fall through */
+ case 54 : /* fall through */
+ case 55 : /* fall through */
+ case 56 : /* fall through */
+ case 57 : /* fall through */
+ case 58 : /* fall through */
+ case 59 : /* fall through */
+ case 60 : /* fall through */
+ case 61 : /* fall through */
+ case 62 : /* fall through */
+ case 63 :
+ if ((entire_insn & 0xf8e00000) == 0xb8c00000)
+ { itype = A5F_INSN_BMSK_S_SSB; goto extract_sfmt_sub_s_ssb; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 992 : /* fall through */
+ case 993 : /* fall through */
+ case 994 : /* fall through */
+ case 995 : /* fall through */
+ case 996 : /* fall through */
+ case 997 : /* fall through */
+ case 998 : /* fall through */
+ case 999 : /* fall through */
+ case 1000 : /* fall through */
+ case 1001 : /* fall through */
+ case 1002 : /* fall through */
+ case 1003 : /* fall through */
+ case 1004 : /* fall through */
+ case 1005 : /* fall through */
+ case 1006 : /* fall through */
+ case 1007 : /* fall through */
+ case 1008 : /* fall through */
+ case 1009 : /* fall through */
+ case 1010 : /* fall through */
+ case 1011 : /* fall through */
+ case 1012 : /* fall through */
+ case 1013 : /* fall through */
+ case 1014 : /* fall through */
+ case 1015 : /* fall through */
+ case 1016 : /* fall through */
+ case 1017 : /* fall through */
+ case 1018 : /* fall through */
+ case 1019 : /* fall through */
+ case 1020 : /* fall through */
+ case 1021 : /* fall through */
+ case 1022 : /* fall through */
+ case 1023 :
+ {
+ unsigned int val = (((insn >> 26) & (1 << 5)) | ((insn >> 25) & (1 << 4)) | ((insn >> 1) & (15 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf800001f) == 0x18000000)
+ { itype = A5F_INSN_ST_ABS; goto extract_sfmt_st_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf800001f) == 0x18000002)
+ { itype = A5F_INSN_STB_ABS; goto extract_sfmt_stb_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf800001f) == 0x18000004)
+ { itype = A5F_INSN_STW_ABS; goto extract_sfmt_stw_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xf800001f) == 0x18000008)
+ { itype = A5F_INSN_ST__AW_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xf800001f) == 0x1800000a)
+ { itype = A5F_INSN_STB__AW_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 :
+ if ((entire_insn & 0xf800001f) == 0x1800000c)
+ { itype = A5F_INSN_STW__AW_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 :
+ if ((entire_insn & 0xf800001f) == 0x18000010)
+ { itype = A5F_INSN_ST_AB_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 9 :
+ if ((entire_insn & 0xf800001f) == 0x18000012)
+ { itype = A5F_INSN_STB_AB_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 10 :
+ if ((entire_insn & 0xf800001f) == 0x18000014)
+ { itype = A5F_INSN_STW_AB_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 :
+ if ((entire_insn & 0xf800001f) == 0x18000018)
+ { itype = A5F_INSN_ST_AS_ABS; goto extract_sfmt_st_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 13 :
+ if ((entire_insn & 0xf800001f) == 0x1800001a)
+ { itype = A5F_INSN_STB_AS_ABS; goto extract_sfmt_stb_as_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 14 :
+ if ((entire_insn & 0xf800001f) == 0x1800001c)
+ { itype = A5F_INSN_STW_AS_ABS; goto extract_sfmt_stw_abs; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 32 : /* fall through */
+ case 33 : /* fall through */
+ case 34 : /* fall through */
+ case 35 : /* fall through */
+ case 36 : /* fall through */
+ case 37 : /* fall through */
+ case 38 : /* fall through */
+ case 39 : /* fall through */
+ case 40 : /* fall through */
+ case 41 : /* fall through */
+ case 42 : /* fall through */
+ case 43 : /* fall through */
+ case 44 : /* fall through */
+ case 45 : /* fall through */
+ case 46 : /* fall through */
+ case 47 :
+ if ((entire_insn & 0xf8000000) == 0x98000000)
+ { itype = A5F_INSN_LDW_S_X_ABU; goto extract_sfmt_ldw_s_abu; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 48 : /* fall through */
+ case 49 : /* fall through */
+ case 50 : /* fall through */
+ case 51 : /* fall through */
+ case 52 : /* fall through */
+ case 53 : /* fall through */
+ case 54 : /* fall through */
+ case 55 : /* fall through */
+ case 56 : /* fall through */
+ case 57 : /* fall through */
+ case 58 : /* fall through */
+ case 59 : /* fall through */
+ case 60 : /* fall through */
+ case 61 : /* fall through */
+ case 62 : /* fall through */
+ case 63 :
+ if ((entire_insn & 0xf8e00000) == 0xb8e00000)
+ { itype = A5F_INSN_BTST_S_SSB; goto extract_sfmt_btst_s_ssb; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1024 : /* fall through */
+ case 1025 : /* fall through */
+ case 1026 : /* fall through */
+ case 1027 : /* fall through */
+ case 1028 : /* fall through */
+ case 1029 : /* fall through */
+ case 1030 : /* fall through */
+ case 1031 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60000000)
+ { itype = A5F_INSN_LD_S_ABC; goto extract_sfmt_ld_s_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0000000)
+ { itype = A5F_INSN_LD_S_ABSP; goto extract_sfmt_ld_s_absp; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = A5F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1032 : /* fall through */
+ case 1033 : /* fall through */
+ case 1034 : /* fall through */
+ case 1035 : /* fall through */
+ case 1036 : /* fall through */
+ case 1037 : /* fall through */
+ case 1038 : /* fall through */
+ case 1039 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60080000)
+ { itype = A5F_INSN_LDB_S_ABC; goto extract_sfmt_ldb_s_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0000000)
+ { itype = A5F_INSN_LD_S_ABSP; goto extract_sfmt_ld_s_absp; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = A5F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1040 : /* fall through */
+ case 1041 : /* fall through */
+ case 1042 : /* fall through */
+ case 1043 : /* fall through */
+ case 1044 : /* fall through */
+ case 1045 : /* fall through */
+ case 1046 : /* fall through */
+ case 1047 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60100000)
+ { itype = A5F_INSN_LDW_S_ABC; goto extract_sfmt_ldw_s_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0000000)
+ { itype = A5F_INSN_LD_S_ABSP; goto extract_sfmt_ld_s_absp; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = A5F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1048 : /* fall through */
+ case 1049 : /* fall through */
+ case 1050 : /* fall through */
+ case 1051 : /* fall through */
+ case 1052 : /* fall through */
+ case 1053 : /* fall through */
+ case 1054 : /* fall through */
+ case 1055 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60180000)
+ { itype = A5F_INSN_ADD_S_ABC; goto extract_sfmt_add_s_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0000000)
+ { itype = A5F_INSN_LD_S_ABSP; goto extract_sfmt_ld_s_absp; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = A5F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1056 : /* fall through */
+ case 1057 : /* fall through */
+ case 1058 : /* fall through */
+ case 1059 : /* fall through */
+ case 1060 : /* fall through */
+ case 1061 : /* fall through */
+ case 1062 : /* fall through */
+ case 1063 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60000000)
+ { itype = A5F_INSN_LD_S_ABC; goto extract_sfmt_ld_s_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0200000)
+ { itype = A5F_INSN_LDB_S_ABSP; goto extract_sfmt_ldb_s_absp; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = A5F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1064 : /* fall through */
+ case 1065 : /* fall through */
+ case 1066 : /* fall through */
+ case 1067 : /* fall through */
+ case 1068 : /* fall through */
+ case 1069 : /* fall through */
+ case 1070 : /* fall through */
+ case 1071 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60080000)
+ { itype = A5F_INSN_LDB_S_ABC; goto extract_sfmt_ldb_s_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0200000)
+ { itype = A5F_INSN_LDB_S_ABSP; goto extract_sfmt_ldb_s_absp; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = A5F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1072 : /* fall through */
+ case 1073 : /* fall through */
+ case 1074 : /* fall through */
+ case 1075 : /* fall through */
+ case 1076 : /* fall through */
+ case 1077 : /* fall through */
+ case 1078 : /* fall through */
+ case 1079 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60100000)
+ { itype = A5F_INSN_LDW_S_ABC; goto extract_sfmt_ldw_s_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0200000)
+ { itype = A5F_INSN_LDB_S_ABSP; goto extract_sfmt_ldb_s_absp; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = A5F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1080 : /* fall through */
+ case 1081 : /* fall through */
+ case 1082 : /* fall through */
+ case 1083 : /* fall through */
+ case 1084 : /* fall through */
+ case 1085 : /* fall through */
+ case 1086 : /* fall through */
+ case 1087 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60180000)
+ { itype = A5F_INSN_ADD_S_ABC; goto extract_sfmt_add_s_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0200000)
+ { itype = A5F_INSN_LDB_S_ABSP; goto extract_sfmt_ldb_s_absp; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = A5F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1088 : /* fall through */
+ case 1089 : /* fall through */
+ case 1090 : /* fall through */
+ case 1091 : /* fall through */
+ case 1092 : /* fall through */
+ case 1093 : /* fall through */
+ case 1094 : /* fall through */
+ case 1095 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60000000)
+ { itype = A5F_INSN_LD_S_ABC; goto extract_sfmt_ld_s_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0400000)
+ { itype = A5F_INSN_ST_S_ABSP; goto extract_sfmt_st_s_absp; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = A5F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1096 : /* fall through */
+ case 1097 : /* fall through */
+ case 1098 : /* fall through */
+ case 1099 : /* fall through */
+ case 1100 : /* fall through */
+ case 1101 : /* fall through */
+ case 1102 : /* fall through */
+ case 1103 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60080000)
+ { itype = A5F_INSN_LDB_S_ABC; goto extract_sfmt_ldb_s_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0400000)
+ { itype = A5F_INSN_ST_S_ABSP; goto extract_sfmt_st_s_absp; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = A5F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1104 : /* fall through */
+ case 1105 : /* fall through */
+ case 1106 : /* fall through */
+ case 1107 : /* fall through */
+ case 1108 : /* fall through */
+ case 1109 : /* fall through */
+ case 1110 : /* fall through */
+ case 1111 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60100000)
+ { itype = A5F_INSN_LDW_S_ABC; goto extract_sfmt_ldw_s_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0400000)
+ { itype = A5F_INSN_ST_S_ABSP; goto extract_sfmt_st_s_absp; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = A5F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1112 : /* fall through */
+ case 1113 : /* fall through */
+ case 1114 : /* fall through */
+ case 1115 : /* fall through */
+ case 1116 : /* fall through */
+ case 1117 : /* fall through */
+ case 1118 : /* fall through */
+ case 1119 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60180000)
+ { itype = A5F_INSN_ADD_S_ABC; goto extract_sfmt_add_s_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0400000)
+ { itype = A5F_INSN_ST_S_ABSP; goto extract_sfmt_st_s_absp; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = A5F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1120 : /* fall through */
+ case 1121 : /* fall through */
+ case 1122 : /* fall through */
+ case 1123 : /* fall through */
+ case 1124 : /* fall through */
+ case 1125 : /* fall through */
+ case 1126 : /* fall through */
+ case 1127 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60000000)
+ { itype = A5F_INSN_LD_S_ABC; goto extract_sfmt_ld_s_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0600000)
+ { itype = A5F_INSN_STB_S_ABSP; goto extract_sfmt_stb_s_absp; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = A5F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1128 : /* fall through */
+ case 1129 : /* fall through */
+ case 1130 : /* fall through */
+ case 1131 : /* fall through */
+ case 1132 : /* fall through */
+ case 1133 : /* fall through */
+ case 1134 : /* fall through */
+ case 1135 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60080000)
+ { itype = A5F_INSN_LDB_S_ABC; goto extract_sfmt_ldb_s_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0600000)
+ { itype = A5F_INSN_STB_S_ABSP; goto extract_sfmt_stb_s_absp; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = A5F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1136 : /* fall through */
+ case 1137 : /* fall through */
+ case 1138 : /* fall through */
+ case 1139 : /* fall through */
+ case 1140 : /* fall through */
+ case 1141 : /* fall through */
+ case 1142 : /* fall through */
+ case 1143 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60100000)
+ { itype = A5F_INSN_LDW_S_ABC; goto extract_sfmt_ldw_s_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0600000)
+ { itype = A5F_INSN_STB_S_ABSP; goto extract_sfmt_stb_s_absp; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = A5F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1144 : /* fall through */
+ case 1145 : /* fall through */
+ case 1146 : /* fall through */
+ case 1147 : /* fall through */
+ case 1148 : /* fall through */
+ case 1149 : /* fall through */
+ case 1150 : /* fall through */
+ case 1151 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60180000)
+ { itype = A5F_INSN_ADD_S_ABC; goto extract_sfmt_add_s_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0600000)
+ { itype = A5F_INSN_STB_S_ABSP; goto extract_sfmt_stb_s_absp; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = A5F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1152 : /* fall through */
+ case 1153 : /* fall through */
+ case 1154 : /* fall through */
+ case 1155 : /* fall through */
+ case 1156 : /* fall through */
+ case 1157 : /* fall through */
+ case 1158 : /* fall through */
+ case 1159 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60000000)
+ { itype = A5F_INSN_LD_S_ABC; goto extract_sfmt_ld_s_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0800000)
+ { itype = A5F_INSN_ADD_S_ABSP; goto extract_sfmt_add_s_absp; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = A5F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1160 : /* fall through */
+ case 1161 : /* fall through */
+ case 1162 : /* fall through */
+ case 1163 : /* fall through */
+ case 1164 : /* fall through */
+ case 1165 : /* fall through */
+ case 1166 : /* fall through */
+ case 1167 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60080000)
+ { itype = A5F_INSN_LDB_S_ABC; goto extract_sfmt_ldb_s_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0800000)
+ { itype = A5F_INSN_ADD_S_ABSP; goto extract_sfmt_add_s_absp; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = A5F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1168 : /* fall through */
+ case 1169 : /* fall through */
+ case 1170 : /* fall through */
+ case 1171 : /* fall through */
+ case 1172 : /* fall through */
+ case 1173 : /* fall through */
+ case 1174 : /* fall through */
+ case 1175 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60100000)
+ { itype = A5F_INSN_LDW_S_ABC; goto extract_sfmt_ldw_s_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0800000)
+ { itype = A5F_INSN_ADD_S_ABSP; goto extract_sfmt_add_s_absp; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = A5F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1176 : /* fall through */
+ case 1177 : /* fall through */
+ case 1178 : /* fall through */
+ case 1179 : /* fall through */
+ case 1180 : /* fall through */
+ case 1181 : /* fall through */
+ case 1182 : /* fall through */
+ case 1183 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60180000)
+ { itype = A5F_INSN_ADD_S_ABC; goto extract_sfmt_add_s_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0800000)
+ { itype = A5F_INSN_ADD_S_ABSP; goto extract_sfmt_add_s_absp; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = A5F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1184 : /* fall through */
+ case 1185 : /* fall through */
+ case 1186 : /* fall through */
+ case 1187 : /* fall through */
+ case 1188 : /* fall through */
+ case 1189 : /* fall through */
+ case 1190 : /* fall through */
+ case 1191 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 24) & (1 << 0)));
+ switch (val)
+ {
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8180000) == 0x60000000)
+ { itype = A5F_INSN_LD_S_ABC; goto extract_sfmt_ld_s_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xffe00000) == 0xc0a00000)
+ { itype = A5F_INSN_ADD_S_ASSPSP; goto extract_sfmt_add_s_asspsp; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xffe00000) == 0xc1a00000)
+ { itype = A5F_INSN_SUB_S_ASSPSP; goto extract_sfmt_add_s_asspsp; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = A5F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1192 : /* fall through */
+ case 1193 : /* fall through */
+ case 1194 : /* fall through */
+ case 1195 : /* fall through */
+ case 1196 : /* fall through */
+ case 1197 : /* fall through */
+ case 1198 : /* fall through */
+ case 1199 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 24) & (1 << 0)));
+ switch (val)
+ {
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8180000) == 0x60080000)
+ { itype = A5F_INSN_LDB_S_ABC; goto extract_sfmt_ldb_s_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xffe00000) == 0xc0a00000)
+ { itype = A5F_INSN_ADD_S_ASSPSP; goto extract_sfmt_add_s_asspsp; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xffe00000) == 0xc1a00000)
+ { itype = A5F_INSN_SUB_S_ASSPSP; goto extract_sfmt_add_s_asspsp; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = A5F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1200 : /* fall through */
+ case 1201 : /* fall through */
+ case 1202 : /* fall through */
+ case 1203 : /* fall through */
+ case 1204 : /* fall through */
+ case 1205 : /* fall through */
+ case 1206 : /* fall through */
+ case 1207 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 24) & (1 << 0)));
+ switch (val)
+ {
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8180000) == 0x60100000)
+ { itype = A5F_INSN_LDW_S_ABC; goto extract_sfmt_ldw_s_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xffe00000) == 0xc0a00000)
+ { itype = A5F_INSN_ADD_S_ASSPSP; goto extract_sfmt_add_s_asspsp; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xffe00000) == 0xc1a00000)
+ { itype = A5F_INSN_SUB_S_ASSPSP; goto extract_sfmt_add_s_asspsp; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = A5F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1208 : /* fall through */
+ case 1209 : /* fall through */
+ case 1210 : /* fall through */
+ case 1211 : /* fall through */
+ case 1212 : /* fall through */
+ case 1213 : /* fall through */
+ case 1214 : /* fall through */
+ case 1215 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 24) & (1 << 0)));
+ switch (val)
+ {
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8180000) == 0x60180000)
+ { itype = A5F_INSN_ADD_S_ABC; goto extract_sfmt_add_s_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xffe00000) == 0xc0a00000)
+ { itype = A5F_INSN_ADD_S_ASSPSP; goto extract_sfmt_add_s_asspsp; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xffe00000) == 0xc1a00000)
+ { itype = A5F_INSN_SUB_S_ASSPSP; goto extract_sfmt_add_s_asspsp; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = A5F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1216 : /* fall through */
+ case 1218 : /* fall through */
+ case 1219 : /* fall through */
+ case 1220 : /* fall through */
+ case 1221 : /* fall through */
+ case 1222 : /* fall through */
+ case 1223 : /* fall through */
+ case 1248 : /* fall through */
+ case 1250 : /* fall through */
+ case 1251 : /* fall through */
+ case 1252 : /* fall through */
+ case 1253 : /* fall through */
+ case 1254 : /* fall through */
+ case 1255 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8180000) == 0x60000000)
+ { itype = A5F_INSN_LD_S_ABC; goto extract_sfmt_ld_s_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = A5F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1217 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60000000)
+ { itype = A5F_INSN_LD_S_ABC; goto extract_sfmt_ld_s_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0000) == 0xc0c10000)
+ { itype = A5F_INSN_POP_S_B; goto extract_sfmt_pop_s_b; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = A5F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1224 : /* fall through */
+ case 1225 : /* fall through */
+ case 1226 : /* fall through */
+ case 1227 : /* fall through */
+ case 1228 : /* fall through */
+ case 1229 : /* fall through */
+ case 1230 : /* fall through */
+ case 1231 : /* fall through */
+ case 1256 : /* fall through */
+ case 1257 : /* fall through */
+ case 1258 : /* fall through */
+ case 1259 : /* fall through */
+ case 1260 : /* fall through */
+ case 1261 : /* fall through */
+ case 1262 : /* fall through */
+ case 1263 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8180000) == 0x60080000)
+ { itype = A5F_INSN_LDB_S_ABC; goto extract_sfmt_ldb_s_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = A5F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1232 : /* fall through */
+ case 1234 : /* fall through */
+ case 1235 : /* fall through */
+ case 1236 : /* fall through */
+ case 1237 : /* fall through */
+ case 1238 : /* fall through */
+ case 1239 : /* fall through */
+ case 1264 : /* fall through */
+ case 1266 : /* fall through */
+ case 1267 : /* fall through */
+ case 1268 : /* fall through */
+ case 1269 : /* fall through */
+ case 1270 : /* fall through */
+ case 1271 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8180000) == 0x60100000)
+ { itype = A5F_INSN_LDW_S_ABC; goto extract_sfmt_ldw_s_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = A5F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1233 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60100000)
+ { itype = A5F_INSN_LDW_S_ABC; goto extract_sfmt_ldw_s_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xffff0000) == 0xc0d10000)
+ { itype = A5F_INSN_POP_S_BLINK; goto extract_sfmt_pop_s_blink; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = A5F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1240 : /* fall through */
+ case 1241 : /* fall through */
+ case 1242 : /* fall through */
+ case 1243 : /* fall through */
+ case 1244 : /* fall through */
+ case 1245 : /* fall through */
+ case 1246 : /* fall through */
+ case 1247 : /* fall through */
+ case 1272 : /* fall through */
+ case 1273 : /* fall through */
+ case 1274 : /* fall through */
+ case 1275 : /* fall through */
+ case 1276 : /* fall through */
+ case 1277 : /* fall through */
+ case 1278 : /* fall through */
+ case 1279 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8180000) == 0x60180000)
+ { itype = A5F_INSN_ADD_S_ABC; goto extract_sfmt_add_s_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = A5F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1249 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60000000)
+ { itype = A5F_INSN_LD_S_ABC; goto extract_sfmt_ld_s_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0000) == 0xc0e10000)
+ { itype = A5F_INSN_PUSH_S_B; goto extract_sfmt_push_s_b; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = A5F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1265 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60100000)
+ { itype = A5F_INSN_LDW_S_ABC; goto extract_sfmt_ldw_s_abc; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xffff0000) == 0xc0f10000)
+ { itype = A5F_INSN_PUSH_S_BLINK; goto extract_sfmt_push_s_blink; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = A5F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1280 : /* fall through */
+ case 1281 : /* fall through */
+ case 1282 : /* fall through */
+ case 1283 : /* fall through */
+ case 1284 : /* fall through */
+ case 1285 : /* fall through */
+ case 1286 : /* fall through */
+ case 1287 : /* fall through */
+ case 1312 : /* fall through */
+ case 1313 : /* fall through */
+ case 1314 : /* fall through */
+ case 1315 : /* fall through */
+ case 1316 : /* fall through */
+ case 1317 : /* fall through */
+ case 1318 : /* fall through */
+ case 1319 : /* fall through */
+ case 1344 : /* fall through */
+ case 1345 : /* fall through */
+ case 1346 : /* fall through */
+ case 1347 : /* fall through */
+ case 1348 : /* fall through */
+ case 1349 : /* fall through */
+ case 1350 : /* fall through */
+ case 1351 : /* fall through */
+ case 1376 : /* fall through */
+ case 1377 : /* fall through */
+ case 1378 : /* fall through */
+ case 1379 : /* fall through */
+ case 1380 : /* fall through */
+ case 1381 : /* fall through */
+ case 1382 : /* fall through */
+ case 1383 : /* fall through */
+ case 1408 : /* fall through */
+ case 1409 : /* fall through */
+ case 1410 : /* fall through */
+ case 1411 : /* fall through */
+ case 1412 : /* fall through */
+ case 1413 : /* fall through */
+ case 1414 : /* fall through */
+ case 1415 : /* fall through */
+ case 1440 : /* fall through */
+ case 1441 : /* fall through */
+ case 1442 : /* fall through */
+ case 1443 : /* fall through */
+ case 1444 : /* fall through */
+ case 1445 : /* fall through */
+ case 1446 : /* fall through */
+ case 1447 : /* fall through */
+ case 1472 : /* fall through */
+ case 1473 : /* fall through */
+ case 1474 : /* fall through */
+ case 1475 : /* fall through */
+ case 1476 : /* fall through */
+ case 1477 : /* fall through */
+ case 1478 : /* fall through */
+ case 1479 : /* fall through */
+ case 1504 : /* fall through */
+ case 1505 : /* fall through */
+ case 1506 : /* fall through */
+ case 1507 : /* fall through */
+ case 1508 : /* fall through */
+ case 1509 : /* fall through */
+ case 1510 : /* fall through */
+ case 1511 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 25) & (3 << 0)));
+ switch (val)
+ {
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8180000) == 0x68000000)
+ { itype = A5F_INSN_ADD_S_CBU3; goto extract_sfmt_add_s_cbu3; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 :
+ if ((entire_insn & 0xfe000000) == 0xc8000000)
+ { itype = A5F_INSN_LD_S_GPREL; goto extract_sfmt_ld_s_gprel; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 9 :
+ if ((entire_insn & 0xfe000000) == 0xca000000)
+ { itype = A5F_INSN_LDB_S_GPREL; goto extract_sfmt_ldb_s_gprel; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 10 :
+ if ((entire_insn & 0xfe000000) == 0xcc000000)
+ { itype = A5F_INSN_LDW_S_GPREL; goto extract_sfmt_ldw_s_gprel; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 11 :
+ if ((entire_insn & 0xfe000000) == 0xce000000)
+ { itype = A5F_INSN_ADD_S_GP; goto extract_sfmt_add_s_gp; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xe8000000)
+ { itype = A5F_INSN_BRCC_S; goto extract_sfmt_brcc_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1288 : /* fall through */
+ case 1289 : /* fall through */
+ case 1290 : /* fall through */
+ case 1291 : /* fall through */
+ case 1292 : /* fall through */
+ case 1293 : /* fall through */
+ case 1294 : /* fall through */
+ case 1295 : /* fall through */
+ case 1320 : /* fall through */
+ case 1321 : /* fall through */
+ case 1322 : /* fall through */
+ case 1323 : /* fall through */
+ case 1324 : /* fall through */
+ case 1325 : /* fall through */
+ case 1326 : /* fall through */
+ case 1327 : /* fall through */
+ case 1352 : /* fall through */
+ case 1353 : /* fall through */
+ case 1354 : /* fall through */
+ case 1355 : /* fall through */
+ case 1356 : /* fall through */
+ case 1357 : /* fall through */
+ case 1358 : /* fall through */
+ case 1359 : /* fall through */
+ case 1384 : /* fall through */
+ case 1385 : /* fall through */
+ case 1386 : /* fall through */
+ case 1387 : /* fall through */
+ case 1388 : /* fall through */
+ case 1389 : /* fall through */
+ case 1390 : /* fall through */
+ case 1391 : /* fall through */
+ case 1416 : /* fall through */
+ case 1417 : /* fall through */
+ case 1418 : /* fall through */
+ case 1419 : /* fall through */
+ case 1420 : /* fall through */
+ case 1421 : /* fall through */
+ case 1422 : /* fall through */
+ case 1423 : /* fall through */
+ case 1448 : /* fall through */
+ case 1449 : /* fall through */
+ case 1450 : /* fall through */
+ case 1451 : /* fall through */
+ case 1452 : /* fall through */
+ case 1453 : /* fall through */
+ case 1454 : /* fall through */
+ case 1455 : /* fall through */
+ case 1480 : /* fall through */
+ case 1481 : /* fall through */
+ case 1482 : /* fall through */
+ case 1483 : /* fall through */
+ case 1484 : /* fall through */
+ case 1485 : /* fall through */
+ case 1486 : /* fall through */
+ case 1487 : /* fall through */
+ case 1512 : /* fall through */
+ case 1513 : /* fall through */
+ case 1514 : /* fall through */
+ case 1515 : /* fall through */
+ case 1516 : /* fall through */
+ case 1517 : /* fall through */
+ case 1518 : /* fall through */
+ case 1519 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 25) & (3 << 0)));
+ switch (val)
+ {
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8180000) == 0x68080000)
+ { itype = A5F_INSN_SUB_S_CBU3; goto extract_sfmt_add_s_cbu3; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 :
+ if ((entire_insn & 0xfe000000) == 0xc8000000)
+ { itype = A5F_INSN_LD_S_GPREL; goto extract_sfmt_ld_s_gprel; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 9 :
+ if ((entire_insn & 0xfe000000) == 0xca000000)
+ { itype = A5F_INSN_LDB_S_GPREL; goto extract_sfmt_ldb_s_gprel; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 10 :
+ if ((entire_insn & 0xfe000000) == 0xcc000000)
+ { itype = A5F_INSN_LDW_S_GPREL; goto extract_sfmt_ldw_s_gprel; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 11 :
+ if ((entire_insn & 0xfe000000) == 0xce000000)
+ { itype = A5F_INSN_ADD_S_GP; goto extract_sfmt_add_s_gp; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xe8000000)
+ { itype = A5F_INSN_BRCC_S; goto extract_sfmt_brcc_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1296 : /* fall through */
+ case 1297 : /* fall through */
+ case 1298 : /* fall through */
+ case 1299 : /* fall through */
+ case 1300 : /* fall through */
+ case 1301 : /* fall through */
+ case 1302 : /* fall through */
+ case 1303 : /* fall through */
+ case 1328 : /* fall through */
+ case 1329 : /* fall through */
+ case 1330 : /* fall through */
+ case 1331 : /* fall through */
+ case 1332 : /* fall through */
+ case 1333 : /* fall through */
+ case 1334 : /* fall through */
+ case 1335 : /* fall through */
+ case 1360 : /* fall through */
+ case 1361 : /* fall through */
+ case 1362 : /* fall through */
+ case 1363 : /* fall through */
+ case 1364 : /* fall through */
+ case 1365 : /* fall through */
+ case 1366 : /* fall through */
+ case 1367 : /* fall through */
+ case 1392 : /* fall through */
+ case 1393 : /* fall through */
+ case 1394 : /* fall through */
+ case 1395 : /* fall through */
+ case 1396 : /* fall through */
+ case 1397 : /* fall through */
+ case 1398 : /* fall through */
+ case 1399 : /* fall through */
+ case 1424 : /* fall through */
+ case 1425 : /* fall through */
+ case 1426 : /* fall through */
+ case 1427 : /* fall through */
+ case 1428 : /* fall through */
+ case 1429 : /* fall through */
+ case 1430 : /* fall through */
+ case 1431 : /* fall through */
+ case 1456 : /* fall through */
+ case 1457 : /* fall through */
+ case 1458 : /* fall through */
+ case 1459 : /* fall through */
+ case 1460 : /* fall through */
+ case 1461 : /* fall through */
+ case 1462 : /* fall through */
+ case 1463 : /* fall through */
+ case 1488 : /* fall through */
+ case 1489 : /* fall through */
+ case 1490 : /* fall through */
+ case 1491 : /* fall through */
+ case 1492 : /* fall through */
+ case 1493 : /* fall through */
+ case 1494 : /* fall through */
+ case 1495 : /* fall through */
+ case 1520 : /* fall through */
+ case 1521 : /* fall through */
+ case 1522 : /* fall through */
+ case 1523 : /* fall through */
+ case 1524 : /* fall through */
+ case 1525 : /* fall through */
+ case 1526 : /* fall through */
+ case 1527 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 25) & (3 << 0)));
+ switch (val)
+ {
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8180000) == 0x68100000)
+ { itype = A5F_INSN_ASL_S_CBU3; goto extract_sfmt_add_s_cbu3; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 :
+ if ((entire_insn & 0xfe000000) == 0xc8000000)
+ { itype = A5F_INSN_LD_S_GPREL; goto extract_sfmt_ld_s_gprel; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 9 :
+ if ((entire_insn & 0xfe000000) == 0xca000000)
+ { itype = A5F_INSN_LDB_S_GPREL; goto extract_sfmt_ldb_s_gprel; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 10 :
+ if ((entire_insn & 0xfe000000) == 0xcc000000)
+ { itype = A5F_INSN_LDW_S_GPREL; goto extract_sfmt_ldw_s_gprel; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 11 :
+ if ((entire_insn & 0xfe000000) == 0xce000000)
+ { itype = A5F_INSN_ADD_S_GP; goto extract_sfmt_add_s_gp; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xe8000000)
+ { itype = A5F_INSN_BRCC_S; goto extract_sfmt_brcc_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1304 : /* fall through */
+ case 1305 : /* fall through */
+ case 1306 : /* fall through */
+ case 1307 : /* fall through */
+ case 1308 : /* fall through */
+ case 1309 : /* fall through */
+ case 1310 : /* fall through */
+ case 1311 : /* fall through */
+ case 1336 : /* fall through */
+ case 1337 : /* fall through */
+ case 1338 : /* fall through */
+ case 1339 : /* fall through */
+ case 1340 : /* fall through */
+ case 1341 : /* fall through */
+ case 1342 : /* fall through */
+ case 1343 : /* fall through */
+ case 1368 : /* fall through */
+ case 1369 : /* fall through */
+ case 1370 : /* fall through */
+ case 1371 : /* fall through */
+ case 1372 : /* fall through */
+ case 1373 : /* fall through */
+ case 1374 : /* fall through */
+ case 1375 : /* fall through */
+ case 1400 : /* fall through */
+ case 1401 : /* fall through */
+ case 1402 : /* fall through */
+ case 1403 : /* fall through */
+ case 1404 : /* fall through */
+ case 1405 : /* fall through */
+ case 1406 : /* fall through */
+ case 1407 : /* fall through */
+ case 1432 : /* fall through */
+ case 1433 : /* fall through */
+ case 1434 : /* fall through */
+ case 1435 : /* fall through */
+ case 1436 : /* fall through */
+ case 1437 : /* fall through */
+ case 1438 : /* fall through */
+ case 1439 : /* fall through */
+ case 1464 : /* fall through */
+ case 1465 : /* fall through */
+ case 1466 : /* fall through */
+ case 1467 : /* fall through */
+ case 1468 : /* fall through */
+ case 1469 : /* fall through */
+ case 1470 : /* fall through */
+ case 1471 : /* fall through */
+ case 1496 : /* fall through */
+ case 1497 : /* fall through */
+ case 1498 : /* fall through */
+ case 1499 : /* fall through */
+ case 1500 : /* fall through */
+ case 1501 : /* fall through */
+ case 1502 : /* fall through */
+ case 1503 : /* fall through */
+ case 1528 : /* fall through */
+ case 1529 : /* fall through */
+ case 1530 : /* fall through */
+ case 1531 : /* fall through */
+ case 1532 : /* fall through */
+ case 1533 : /* fall through */
+ case 1534 : /* fall through */
+ case 1535 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 25) & (3 << 0)));
+ switch (val)
+ {
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8180000) == 0x68180000)
+ { itype = A5F_INSN_ASR_S_CBU3; goto extract_sfmt_add_s_cbu3; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 :
+ if ((entire_insn & 0xfe000000) == 0xc8000000)
+ { itype = A5F_INSN_LD_S_GPREL; goto extract_sfmt_ld_s_gprel; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 9 :
+ if ((entire_insn & 0xfe000000) == 0xca000000)
+ { itype = A5F_INSN_LDB_S_GPREL; goto extract_sfmt_ldb_s_gprel; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 10 :
+ if ((entire_insn & 0xfe000000) == 0xcc000000)
+ { itype = A5F_INSN_LDW_S_GPREL; goto extract_sfmt_ldw_s_gprel; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 11 :
+ if ((entire_insn & 0xfe000000) == 0xce000000)
+ { itype = A5F_INSN_ADD_S_GP; goto extract_sfmt_add_s_gp; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xe8000000)
+ { itype = A5F_INSN_BRCC_S; goto extract_sfmt_brcc_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1536 : /* fall through */
+ case 1537 : /* fall through */
+ case 1538 : /* fall through */
+ case 1539 : /* fall through */
+ case 1540 : /* fall through */
+ case 1541 : /* fall through */
+ case 1542 : /* fall through */
+ case 1543 : /* fall through */
+ case 1568 : /* fall through */
+ case 1569 : /* fall through */
+ case 1570 : /* fall through */
+ case 1571 : /* fall through */
+ case 1572 : /* fall through */
+ case 1573 : /* fall through */
+ case 1574 : /* fall through */
+ case 1575 : /* fall through */
+ case 1600 : /* fall through */
+ case 1601 : /* fall through */
+ case 1602 : /* fall through */
+ case 1603 : /* fall through */
+ case 1604 : /* fall through */
+ case 1605 : /* fall through */
+ case 1606 : /* fall through */
+ case 1607 : /* fall through */
+ case 1632 : /* fall through */
+ case 1633 : /* fall through */
+ case 1634 : /* fall through */
+ case 1635 : /* fall through */
+ case 1636 : /* fall through */
+ case 1637 : /* fall through */
+ case 1638 : /* fall through */
+ case 1639 : /* fall through */
+ case 1664 : /* fall through */
+ case 1665 : /* fall through */
+ case 1666 : /* fall through */
+ case 1667 : /* fall through */
+ case 1668 : /* fall through */
+ case 1669 : /* fall through */
+ case 1670 : /* fall through */
+ case 1671 : /* fall through */
+ case 1696 : /* fall through */
+ case 1697 : /* fall through */
+ case 1698 : /* fall through */
+ case 1699 : /* fall through */
+ case 1700 : /* fall through */
+ case 1701 : /* fall through */
+ case 1702 : /* fall through */
+ case 1703 : /* fall through */
+ case 1728 : /* fall through */
+ case 1729 : /* fall through */
+ case 1730 : /* fall through */
+ case 1731 : /* fall through */
+ case 1732 : /* fall through */
+ case 1733 : /* fall through */
+ case 1734 : /* fall through */
+ case 1735 : /* fall through */
+ case 1760 : /* fall through */
+ case 1761 : /* fall through */
+ case 1762 : /* fall through */
+ case 1763 : /* fall through */
+ case 1764 : /* fall through */
+ case 1765 : /* fall through */
+ case 1766 : /* fall through */
+ case 1767 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x70000000)
+ { itype = A5F_INSN_ADD_S_MCAH; goto extract_sfmt_add_s_mcah; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd0000000)
+ { itype = A5F_INSN_LD_S_PCREL; goto extract_sfmt_ld_s_pcrel; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ {
+ unsigned int val = (((insn >> 25) & (3 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xf0000000)
+ { itype = A5F_INSN_B_S; goto extract_sfmt_b_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xfe000000) == 0xf6000000)
+ { itype = A5F_INSN_BCC_S; goto extract_sfmt_bcc_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1544 : /* fall through */
+ case 1545 : /* fall through */
+ case 1546 : /* fall through */
+ case 1547 : /* fall through */
+ case 1548 : /* fall through */
+ case 1549 : /* fall through */
+ case 1550 : /* fall through */
+ case 1551 : /* fall through */
+ case 1576 : /* fall through */
+ case 1577 : /* fall through */
+ case 1578 : /* fall through */
+ case 1579 : /* fall through */
+ case 1580 : /* fall through */
+ case 1581 : /* fall through */
+ case 1582 : /* fall through */
+ case 1583 : /* fall through */
+ case 1608 : /* fall through */
+ case 1609 : /* fall through */
+ case 1610 : /* fall through */
+ case 1611 : /* fall through */
+ case 1612 : /* fall through */
+ case 1613 : /* fall through */
+ case 1614 : /* fall through */
+ case 1615 : /* fall through */
+ case 1640 : /* fall through */
+ case 1641 : /* fall through */
+ case 1642 : /* fall through */
+ case 1643 : /* fall through */
+ case 1644 : /* fall through */
+ case 1645 : /* fall through */
+ case 1646 : /* fall through */
+ case 1647 : /* fall through */
+ case 1672 : /* fall through */
+ case 1673 : /* fall through */
+ case 1674 : /* fall through */
+ case 1675 : /* fall through */
+ case 1676 : /* fall through */
+ case 1677 : /* fall through */
+ case 1678 : /* fall through */
+ case 1679 : /* fall through */
+ case 1704 : /* fall through */
+ case 1705 : /* fall through */
+ case 1706 : /* fall through */
+ case 1707 : /* fall through */
+ case 1708 : /* fall through */
+ case 1709 : /* fall through */
+ case 1710 : /* fall through */
+ case 1711 : /* fall through */
+ case 1736 : /* fall through */
+ case 1737 : /* fall through */
+ case 1738 : /* fall through */
+ case 1739 : /* fall through */
+ case 1740 : /* fall through */
+ case 1741 : /* fall through */
+ case 1742 : /* fall through */
+ case 1743 : /* fall through */
+ case 1768 : /* fall through */
+ case 1769 : /* fall through */
+ case 1770 : /* fall through */
+ case 1771 : /* fall through */
+ case 1772 : /* fall through */
+ case 1773 : /* fall through */
+ case 1774 : /* fall through */
+ case 1775 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x70080000)
+ { itype = A5F_INSN_MOV_S_MCAH; goto extract_sfmt_mov_s_mcah; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd0000000)
+ { itype = A5F_INSN_LD_S_PCREL; goto extract_sfmt_ld_s_pcrel; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ {
+ unsigned int val = (((insn >> 25) & (3 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xf0000000)
+ { itype = A5F_INSN_B_S; goto extract_sfmt_b_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xfe000000) == 0xf6000000)
+ { itype = A5F_INSN_BCC_S; goto extract_sfmt_bcc_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1552 : /* fall through */
+ case 1553 : /* fall through */
+ case 1554 : /* fall through */
+ case 1555 : /* fall through */
+ case 1556 : /* fall through */
+ case 1557 : /* fall through */
+ case 1558 : /* fall through */
+ case 1559 : /* fall through */
+ case 1584 : /* fall through */
+ case 1585 : /* fall through */
+ case 1586 : /* fall through */
+ case 1587 : /* fall through */
+ case 1588 : /* fall through */
+ case 1589 : /* fall through */
+ case 1590 : /* fall through */
+ case 1591 : /* fall through */
+ case 1616 : /* fall through */
+ case 1617 : /* fall through */
+ case 1618 : /* fall through */
+ case 1619 : /* fall through */
+ case 1620 : /* fall through */
+ case 1621 : /* fall through */
+ case 1622 : /* fall through */
+ case 1623 : /* fall through */
+ case 1648 : /* fall through */
+ case 1649 : /* fall through */
+ case 1650 : /* fall through */
+ case 1651 : /* fall through */
+ case 1652 : /* fall through */
+ case 1653 : /* fall through */
+ case 1654 : /* fall through */
+ case 1655 : /* fall through */
+ case 1680 : /* fall through */
+ case 1681 : /* fall through */
+ case 1682 : /* fall through */
+ case 1683 : /* fall through */
+ case 1684 : /* fall through */
+ case 1685 : /* fall through */
+ case 1686 : /* fall through */
+ case 1687 : /* fall through */
+ case 1712 : /* fall through */
+ case 1713 : /* fall through */
+ case 1714 : /* fall through */
+ case 1715 : /* fall through */
+ case 1716 : /* fall through */
+ case 1717 : /* fall through */
+ case 1718 : /* fall through */
+ case 1719 : /* fall through */
+ case 1744 : /* fall through */
+ case 1745 : /* fall through */
+ case 1746 : /* fall through */
+ case 1747 : /* fall through */
+ case 1748 : /* fall through */
+ case 1749 : /* fall through */
+ case 1750 : /* fall through */
+ case 1751 : /* fall through */
+ case 1776 : /* fall through */
+ case 1777 : /* fall through */
+ case 1778 : /* fall through */
+ case 1779 : /* fall through */
+ case 1780 : /* fall through */
+ case 1781 : /* fall through */
+ case 1782 : /* fall through */
+ case 1783 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x70100000)
+ { itype = A5F_INSN_CMP_S_MCAH; goto extract_sfmt_cmp_s_mcah; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd0000000)
+ { itype = A5F_INSN_LD_S_PCREL; goto extract_sfmt_ld_s_pcrel; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ {
+ unsigned int val = (((insn >> 25) & (3 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xf0000000)
+ { itype = A5F_INSN_B_S; goto extract_sfmt_b_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xfe000000) == 0xf6000000)
+ { itype = A5F_INSN_BCC_S; goto extract_sfmt_bcc_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1560 : /* fall through */
+ case 1561 : /* fall through */
+ case 1562 : /* fall through */
+ case 1563 : /* fall through */
+ case 1564 : /* fall through */
+ case 1565 : /* fall through */
+ case 1566 : /* fall through */
+ case 1567 : /* fall through */
+ case 1592 : /* fall through */
+ case 1593 : /* fall through */
+ case 1594 : /* fall through */
+ case 1595 : /* fall through */
+ case 1596 : /* fall through */
+ case 1597 : /* fall through */
+ case 1598 : /* fall through */
+ case 1599 : /* fall through */
+ case 1624 : /* fall through */
+ case 1625 : /* fall through */
+ case 1626 : /* fall through */
+ case 1627 : /* fall through */
+ case 1628 : /* fall through */
+ case 1629 : /* fall through */
+ case 1630 : /* fall through */
+ case 1631 : /* fall through */
+ case 1656 : /* fall through */
+ case 1657 : /* fall through */
+ case 1658 : /* fall through */
+ case 1659 : /* fall through */
+ case 1660 : /* fall through */
+ case 1661 : /* fall through */
+ case 1662 : /* fall through */
+ case 1663 : /* fall through */
+ case 1688 : /* fall through */
+ case 1689 : /* fall through */
+ case 1690 : /* fall through */
+ case 1691 : /* fall through */
+ case 1692 : /* fall through */
+ case 1693 : /* fall through */
+ case 1694 : /* fall through */
+ case 1695 : /* fall through */
+ case 1720 : /* fall through */
+ case 1721 : /* fall through */
+ case 1722 : /* fall through */
+ case 1723 : /* fall through */
+ case 1724 : /* fall through */
+ case 1725 : /* fall through */
+ case 1726 : /* fall through */
+ case 1727 : /* fall through */
+ case 1752 : /* fall through */
+ case 1753 : /* fall through */
+ case 1754 : /* fall through */
+ case 1755 : /* fall through */
+ case 1756 : /* fall through */
+ case 1757 : /* fall through */
+ case 1758 : /* fall through */
+ case 1759 : /* fall through */
+ case 1784 : /* fall through */
+ case 1785 : /* fall through */
+ case 1786 : /* fall through */
+ case 1787 : /* fall through */
+ case 1788 : /* fall through */
+ case 1789 : /* fall through */
+ case 1790 : /* fall through */
+ case 1791 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x70180000)
+ { itype = A5F_INSN_MOV_S_MCAHB; goto extract_sfmt_mov_s_mcahb; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd0000000)
+ { itype = A5F_INSN_LD_S_PCREL; goto extract_sfmt_ld_s_pcrel; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ {
+ unsigned int val = (((insn >> 25) & (3 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xf0000000)
+ { itype = A5F_INSN_B_S; goto extract_sfmt_b_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xfe000000) == 0xf6000000)
+ { itype = A5F_INSN_BCC_S; goto extract_sfmt_bcc_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1792 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8ff0000) == 0x78000000)
+ { itype = A5F_INSN_J_S; goto extract_sfmt_j_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = A5F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = A5F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1793 : /* fall through */
+ case 1795 : /* fall through */
+ case 1800 : /* fall through */
+ case 1801 : /* fall through */
+ case 1802 : /* fall through */
+ case 1815 : /* fall through */
+ case 1823 : /* fall through */
+ case 1825 : /* fall through */
+ case 1827 : /* fall through */
+ case 1832 : /* fall through */
+ case 1833 : /* fall through */
+ case 1834 : /* fall through */
+ case 1847 : /* fall through */
+ case 1855 : /* fall through */
+ case 1857 : /* fall through */
+ case 1859 : /* fall through */
+ case 1864 : /* fall through */
+ case 1865 : /* fall through */
+ case 1866 : /* fall through */
+ case 1879 : /* fall through */
+ case 1887 : /* fall through */
+ case 1889 : /* fall through */
+ case 1891 : /* fall through */
+ case 1896 : /* fall through */
+ case 1897 : /* fall through */
+ case 1898 : /* fall through */
+ case 1911 : /* fall through */
+ case 1919 : /* fall through */
+ case 1920 : /* fall through */
+ case 1921 : /* fall through */
+ case 1923 : /* fall through */
+ case 1928 : /* fall through */
+ case 1929 : /* fall through */
+ case 1930 : /* fall through */
+ case 1943 : /* fall through */
+ case 1951 : /* fall through */
+ case 1952 : /* fall through */
+ case 1953 : /* fall through */
+ case 1955 : /* fall through */
+ case 1960 : /* fall through */
+ case 1961 : /* fall through */
+ case 1962 : /* fall through */
+ case 1975 : /* fall through */
+ case 1983 : /* fall through */
+ case 1985 : /* fall through */
+ case 1987 : /* fall through */
+ case 1992 : /* fall through */
+ case 1993 : /* fall through */
+ case 1994 : /* fall through */
+ case 2007 : /* fall through */
+ case 2015 : /* fall through */
+ case 2017 : /* fall through */
+ case 2019 : /* fall through */
+ case 2024 : /* fall through */
+ case 2025 : /* fall through */
+ case 2026 : /* fall through */
+ case 2039 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = A5F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = A5F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1794 : /* fall through */
+ case 1826 : /* fall through */
+ case 1858 : /* fall through */
+ case 1890 : /* fall through */
+ case 1922 : /* fall through */
+ case 1954 : /* fall through */
+ case 1986 : /* fall through */
+ case 2018 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x78020000)
+ { itype = A5F_INSN_I16_GO_SUB_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = A5F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = A5F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1796 : /* fall through */
+ case 1828 : /* fall through */
+ case 1860 : /* fall through */
+ case 1892 : /* fall through */
+ case 1924 : /* fall through */
+ case 1956 : /* fall through */
+ case 1988 : /* fall through */
+ case 2020 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x78040000)
+ { itype = A5F_INSN_I16_GO_AND_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = A5F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = A5F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1797 : /* fall through */
+ case 1829 : /* fall through */
+ case 1861 : /* fall through */
+ case 1893 : /* fall through */
+ case 1925 : /* fall through */
+ case 1957 : /* fall through */
+ case 1989 : /* fall through */
+ case 2021 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x78050000)
+ { itype = A5F_INSN_I16_GO_OR_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = A5F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = A5F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1798 : /* fall through */
+ case 1830 : /* fall through */
+ case 1862 : /* fall through */
+ case 1894 : /* fall through */
+ case 1926 : /* fall through */
+ case 1958 : /* fall through */
+ case 1990 : /* fall through */
+ case 2022 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x78060000)
+ { itype = A5F_INSN_I16_GO_BIC_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = A5F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = A5F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1799 : /* fall through */
+ case 1831 : /* fall through */
+ case 1863 : /* fall through */
+ case 1895 : /* fall through */
+ case 1927 : /* fall through */
+ case 1959 : /* fall through */
+ case 1991 : /* fall through */
+ case 2023 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x78070000)
+ { itype = A5F_INSN_I16_GO_XOR_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = A5F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = A5F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1803 : /* fall through */
+ case 1835 : /* fall through */
+ case 1867 : /* fall through */
+ case 1899 : /* fall through */
+ case 1931 : /* fall through */
+ case 1963 : /* fall through */
+ case 1995 : /* fall through */
+ case 2027 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x780b0000)
+ { itype = A5F_INSN_TST_S_GO; goto extract_sfmt_tst_s_go; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = A5F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = A5F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1804 : /* fall through */
+ case 1836 : /* fall through */
+ case 1868 : /* fall through */
+ case 1900 : /* fall through */
+ case 1932 : /* fall through */
+ case 1964 : /* fall through */
+ case 1996 : /* fall through */
+ case 2028 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x780c0000)
+ { itype = A5F_INSN_MUL64_S_GO; goto extract_sfmt_mul64_s_go; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = A5F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = A5F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1805 : /* fall through */
+ case 1837 : /* fall through */
+ case 1869 : /* fall through */
+ case 1901 : /* fall through */
+ case 1933 : /* fall through */
+ case 1965 : /* fall through */
+ case 1997 : /* fall through */
+ case 2029 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x780d0000)
+ { itype = A5F_INSN_I16_GO_SEXB_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = A5F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = A5F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1806 : /* fall through */
+ case 1838 : /* fall through */
+ case 1870 : /* fall through */
+ case 1902 : /* fall through */
+ case 1934 : /* fall through */
+ case 1966 : /* fall through */
+ case 1998 : /* fall through */
+ case 2030 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x780e0000)
+ { itype = A5F_INSN_I16_GO_SEXW_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = A5F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = A5F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1807 : /* fall through */
+ case 1839 : /* fall through */
+ case 1871 : /* fall through */
+ case 1903 : /* fall through */
+ case 1935 : /* fall through */
+ case 1967 : /* fall through */
+ case 1999 : /* fall through */
+ case 2031 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x780f0000)
+ { itype = A5F_INSN_I16_GO_EXTB_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = A5F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = A5F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1808 : /* fall through */
+ case 1840 : /* fall through */
+ case 1872 : /* fall through */
+ case 1904 : /* fall through */
+ case 1936 : /* fall through */
+ case 1968 : /* fall through */
+ case 2000 : /* fall through */
+ case 2032 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x78100000)
+ { itype = A5F_INSN_I16_GO_EXTW_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = A5F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = A5F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1809 : /* fall through */
+ case 1841 : /* fall through */
+ case 1873 : /* fall through */
+ case 1905 : /* fall through */
+ case 1937 : /* fall through */
+ case 1969 : /* fall through */
+ case 2001 : /* fall through */
+ case 2033 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x78110000)
+ { itype = A5F_INSN_I16_GO_ABS_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = A5F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = A5F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1810 : /* fall through */
+ case 1842 : /* fall through */
+ case 1874 : /* fall through */
+ case 1906 : /* fall through */
+ case 1938 : /* fall through */
+ case 1970 : /* fall through */
+ case 2002 : /* fall through */
+ case 2034 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x78120000)
+ { itype = A5F_INSN_I16_GO_NOT_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = A5F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = A5F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1811 : /* fall through */
+ case 1843 : /* fall through */
+ case 1875 : /* fall through */
+ case 1907 : /* fall through */
+ case 1939 : /* fall through */
+ case 1971 : /* fall through */
+ case 2003 : /* fall through */
+ case 2035 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x78130000)
+ { itype = A5F_INSN_I16_GO_NEG_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = A5F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = A5F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1812 : /* fall through */
+ case 1844 : /* fall through */
+ case 1876 : /* fall through */
+ case 1908 : /* fall through */
+ case 1940 : /* fall through */
+ case 1972 : /* fall through */
+ case 2004 : /* fall through */
+ case 2036 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x78140000)
+ { itype = A5F_INSN_I16_GO_ADD1_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = A5F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = A5F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1813 : /* fall through */
+ case 1845 : /* fall through */
+ case 1877 : /* fall through */
+ case 1909 : /* fall through */
+ case 1941 : /* fall through */
+ case 1973 : /* fall through */
+ case 2005 : /* fall through */
+ case 2037 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x78150000)
+ { itype = A5F_INSN_I16_GO_ADD2_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = A5F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = A5F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1814 : /* fall through */
+ case 1846 : /* fall through */
+ case 1878 : /* fall through */
+ case 1910 : /* fall through */
+ case 1942 : /* fall through */
+ case 1974 : /* fall through */
+ case 2006 : /* fall through */
+ case 2038 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x78160000)
+ { itype = A5F_INSN_I16_GO_ADD3_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = A5F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = A5F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1816 : /* fall through */
+ case 1848 : /* fall through */
+ case 1880 : /* fall through */
+ case 1912 : /* fall through */
+ case 1944 : /* fall through */
+ case 1976 : /* fall through */
+ case 2008 : /* fall through */
+ case 2040 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x78180000)
+ { itype = A5F_INSN_I16_GO_ASLM_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = A5F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = A5F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1817 : /* fall through */
+ case 1849 : /* fall through */
+ case 1881 : /* fall through */
+ case 1913 : /* fall through */
+ case 1945 : /* fall through */
+ case 1977 : /* fall through */
+ case 2009 : /* fall through */
+ case 2041 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x78190000)
+ { itype = A5F_INSN_I16_GO_LSRM_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = A5F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = A5F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1818 : /* fall through */
+ case 1850 : /* fall through */
+ case 1882 : /* fall through */
+ case 1914 : /* fall through */
+ case 1946 : /* fall through */
+ case 1978 : /* fall through */
+ case 2010 : /* fall through */
+ case 2042 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x781a0000)
+ { itype = A5F_INSN_I16_GO_ASRM_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = A5F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = A5F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1819 : /* fall through */
+ case 1851 : /* fall through */
+ case 1883 : /* fall through */
+ case 1915 : /* fall through */
+ case 1947 : /* fall through */
+ case 1979 : /* fall through */
+ case 2011 : /* fall through */
+ case 2043 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x781b0000)
+ { itype = A5F_INSN_I16_GO_ASL_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = A5F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = A5F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1820 : /* fall through */
+ case 1852 : /* fall through */
+ case 1884 : /* fall through */
+ case 1916 : /* fall through */
+ case 1948 : /* fall through */
+ case 1980 : /* fall through */
+ case 2012 : /* fall through */
+ case 2044 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x781c0000)
+ { itype = A5F_INSN_I16_GO_ASR_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = A5F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = A5F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1821 : /* fall through */
+ case 1853 : /* fall through */
+ case 1885 : /* fall through */
+ case 1917 : /* fall through */
+ case 1949 : /* fall through */
+ case 1981 : /* fall through */
+ case 2013 : /* fall through */
+ case 2045 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x781d0000)
+ { itype = A5F_INSN_I16_GO_LSR_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = A5F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = A5F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1822 : /* fall through */
+ case 1854 : /* fall through */
+ case 1886 : /* fall through */
+ case 1918 : /* fall through */
+ case 1950 : /* fall through */
+ case 1982 : /* fall through */
+ case 2014 : /* fall through */
+ case 2046 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x781e0000)
+ { itype = A5F_INSN_TRAP_S; goto extract_sfmt_trap_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = A5F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = A5F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1824 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8ff0000) == 0x78200000)
+ { itype = A5F_INSN_J_S_D; goto extract_sfmt_j_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = A5F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = A5F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1856 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8ff0000) == 0x78400000)
+ { itype = A5F_INSN_JL_S; goto extract_sfmt_jl_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = A5F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = A5F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1888 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8ff0000) == 0x78600000)
+ { itype = A5F_INSN_JL_S_D; goto extract_sfmt_jl_s_d; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = A5F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = A5F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1984 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8ff0000) == 0x78c00000)
+ { itype = A5F_INSN_SUB_S_GO_SUB_NE; goto extract_sfmt_sub_s_go_sub_ne; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = A5F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = A5F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 2016 :
+ {
+ unsigned int val = (((insn >> 27) & (1 << 4)) | ((insn >> 26) & (1 << 3)) | ((insn >> 24) & (7 << 0)));
+ switch (val)
+ {
+ case 8 :
+ if ((entire_insn & 0xffff0000) == 0x78e00000)
+ { itype = A5F_INSN_NOP_S; goto extract_sfmt_nop_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 9 :
+ if ((entire_insn & 0xffff0000) == 0x79e00000)
+ { itype = A5F_INSN_UNIMP_S; goto extract_sfmt_nop_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 :
+ if ((entire_insn & 0xffff0000) == 0x7ce00000)
+ { itype = A5F_INSN_J_SEQ__S; goto extract_sfmt_j_seq__S; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 13 :
+ if ((entire_insn & 0xffff0000) == 0x7de00000)
+ { itype = A5F_INSN_J_SNE__S; goto extract_sfmt_j_seq__S; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 14 :
+ if ((entire_insn & 0xffff0000) == 0x7ee00000)
+ { itype = A5F_INSN_J_S__S; goto extract_sfmt_j_s__S; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 15 :
+ if ((entire_insn & 0xffff0000) == 0x7fe00000)
+ { itype = A5F_INSN_J_S__S_D; goto extract_sfmt_j_s__S; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 16 : /* fall through */
+ case 17 : /* fall through */
+ case 18 : /* fall through */
+ case 19 : /* fall through */
+ case 20 : /* fall through */
+ case 21 : /* fall through */
+ case 22 : /* fall through */
+ case 23 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = A5F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 24 : /* fall through */
+ case 25 : /* fall through */
+ case 26 : /* fall through */
+ case 27 : /* fall through */
+ case 28 : /* fall through */
+ case 29 : /* fall through */
+ case 30 : /* fall through */
+ case 31 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = A5F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 2047 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xffff0000) == 0x7fff0000)
+ { itype = A5F_INSN_BRK_S; goto extract_sfmt_brk; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = A5F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = A5F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ default : itype = A5F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ }
+
+ /* The instruction has been decoded, now extract the fields. */
+
+ extract_sfmt_empty:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_b_s:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_b_s.f
+ UINT f_cond_i2;
+ SI f_rel10;
+
+ f_cond_i2 = EXTRACT_MSB0_UINT (insn, 32, 5, 2);
+ f_rel10 = ((((EXTRACT_MSB0_INT (insn, 32, 7, 9)) << (1))) + (((pc) & (-4))));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_i2) = f_cond_i2;
+ FLD (i_label10) = f_rel10;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_b_s", "f_cond_i2 0x%x", 'x', f_cond_i2, "label10 0x%x", 'x', f_rel10, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_bcc_s:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_bcc_s.f
+ UINT f_cond_i3;
+ SI f_rel7;
+
+ f_cond_i3 = EXTRACT_MSB0_UINT (insn, 32, 7, 3);
+ f_rel7 = ((((EXTRACT_MSB0_INT (insn, 32, 10, 6)) << (1))) + (((pc) & (-4))));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_i3) = f_cond_i3;
+ FLD (i_label7) = f_rel7;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcc_s", "f_cond_i3 0x%x", 'x', f_cond_i3, "label7 0x%x", 'x', f_rel7, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_brcc_s:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_brcc_s.f
+ UINT f_op__b;
+ UINT f_brscond;
+ SI f_rel8;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_brscond = EXTRACT_MSB0_UINT (insn, 32, 8, 1);
+ f_rel8 = ((((EXTRACT_MSB0_INT (insn, 32, 9, 7)) << (1))) + (((pc) & (-4))));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_brscond) = f_brscond;
+ FLD (i_label8) = f_rel8;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_brcc_s", "f_op__b 0x%x", 'x', f_op__b, "f_brscond 0x%x", 'x', f_brscond, "label8 0x%x", 'x', f_rel8, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_bcc_l:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_bcc_l.f
+ UINT f_d21l;
+ INT f_d21h;
+ UINT f_cond_Q;
+ INT f_rel21;
+
+ f_d21l = EXTRACT_MSB0_UINT (insn, 32, 5, 10);
+ f_d21h = EXTRACT_MSB0_INT (insn, 32, 16, 10);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_rel21 = ((((((f_d21l) << (1))) | (((f_d21h) << (11))))) + (((pc) & (-4))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (i_label21) = f_rel21;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcc_l", "f_cond_Q 0x%x", 'x', f_cond_Q, "label21 0x%x", 'x', f_rel21, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_b_l:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_b_l.f
+ UINT f_d21l;
+ UINT f_d25m;
+ INT f_d25h;
+ INT f_rel25;
+
+ f_d21l = EXTRACT_MSB0_UINT (insn, 32, 5, 10);
+ f_d25m = EXTRACT_MSB0_UINT (insn, 32, 16, 10);
+ f_d25h = EXTRACT_MSB0_INT (insn, 32, 28, 4);
+{
+ f_rel25 = ((((((((f_d21l) << (1))) | (((f_d25m) << (11))))) | (((f_d25h) << (21))))) + (((pc) & (-4))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_label25) = f_rel25;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_b_l", "label25 0x%x", 'x', f_rel25, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_brcc_RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_brcc_RC.f
+ UINT f_op__b;
+ UINT f_d9l;
+ INT f_d9h;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_brcond;
+ UINT f_op_B;
+ INT f_rel9;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_d9l = EXTRACT_MSB0_UINT (insn, 32, 8, 7);
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_brcond = EXTRACT_MSB0_UINT (insn, 32, 28, 4);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_rel9 = ((((((f_d9l) << (1))) | (((f_d9h) << (8))))) + (((pc) & (-4))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_brcond) = f_brcond;
+ FLD (i_label9) = f_rel9;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_brcc_RC", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_brcond 0x%x", 'x', f_brcond, "label9 0x%x", 'x', f_rel9, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_brcc_U6:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_brcc_U6.f
+ UINT f_op__b;
+ UINT f_d9l;
+ INT f_d9h;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_brcond;
+ UINT f_op_B;
+ INT f_rel9;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_d9l = EXTRACT_MSB0_UINT (insn, 32, 8, 7);
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_brcond = EXTRACT_MSB0_UINT (insn, 32, 28, 4);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_rel9 = ((((((f_d9l) << (1))) | (((f_d9h) << (8))))) + (((pc) & (-4))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_brcond) = f_brcond;
+ FLD (f_u6) = f_u6;
+ FLD (i_label9) = f_rel9;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_brcc_U6", "f_op_B 0x%x", 'x', f_op_B, "f_brcond 0x%x", 'x', f_brcond, "f_u6 0x%x", 'x', f_u6, "label9 0x%x", 'x', f_rel9, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_bl_s:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_bl_s.f
+ SI f_rel13bl;
+
+ f_rel13bl = ((((EXTRACT_MSB0_INT (insn, 32, 5, 11)) << (2))) + (((pc) & (-4))));
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_label13a) = f_rel13bl;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl_s", "label13a 0x%x", 'x', f_rel13bl, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_blcc:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_blcc.f
+ UINT f_d21bl;
+ INT f_d21h;
+ UINT f_cond_Q;
+ INT f_rel21bl;
+
+ f_d21bl = EXTRACT_MSB0_UINT (insn, 32, 5, 9);
+ f_d21h = EXTRACT_MSB0_INT (insn, 32, 16, 10);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_rel21bl = ((((((f_d21bl) << (2))) | (((f_d21h) << (11))))) + (((pc) & (-4))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (i_label21a) = f_rel21bl;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_blcc", "f_cond_Q 0x%x", 'x', f_cond_Q, "label21a 0x%x", 'x', f_rel21bl, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_bl:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_bl.f
+ UINT f_d21bl;
+ UINT f_d25m;
+ INT f_d25h;
+ INT f_rel25bl;
+
+ f_d21bl = EXTRACT_MSB0_UINT (insn, 32, 5, 9);
+ f_d25m = EXTRACT_MSB0_UINT (insn, 32, 16, 10);
+ f_d25h = EXTRACT_MSB0_INT (insn, 32, 28, 4);
+{
+ f_rel25bl = ((((((((f_d21bl) << (2))) | (((f_d25m) << (11))))) | (((f_d25h) << (21))))) + (((pc) & (-4))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_label25a) = f_rel25bl;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl", "label25a 0x%x", 'x', f_rel25bl, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_bl_d:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_bl.f
+ UINT f_d21bl;
+ UINT f_d25m;
+ INT f_d25h;
+ INT f_rel25bl;
+
+ f_d21bl = EXTRACT_MSB0_UINT (insn, 32, 5, 9);
+ f_d25m = EXTRACT_MSB0_UINT (insn, 32, 16, 10);
+ f_d25h = EXTRACT_MSB0_INT (insn, 32, 28, 4);
+{
+ f_rel25bl = ((((((((f_d21bl) << (2))) | (((f_d25m) << (11))))) | (((f_d25h) << (21))))) + (((pc) & (-4))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_label25a) = f_rel25bl;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl_d", "label25a 0x%x", 'x', f_rel25bl, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ld_abs:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ UINT f_op__b;
+ UINT f_u8;
+ INT f_d9h;
+ UINT f_B_5_3;
+ UINT f_op_A;
+ UINT f_op_B;
+ INT f_s9;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8);
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s9 = ((f_u8) | (((f_d9h) << (8))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s9) = f_s9;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_abs", "f_op_B 0x%x", 'x', f_op_B, "f_s9 0x%x", 'x', f_s9, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ld__AW_abs:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ UINT f_op__b;
+ UINT f_u8;
+ INT f_d9h;
+ UINT f_B_5_3;
+ UINT f_op_A;
+ UINT f_op_B;
+ INT f_s9;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8);
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s9 = ((f_u8) | (((f_d9h) << (8))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s9) = f_s9;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld__AW_abs", "f_op_B 0x%x", 'x', f_op_B, "f_s9 0x%x", 'x', f_s9, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ld_abc:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_abc", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ld__AW_abc:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld__AW_abc", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ld_s_abc:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ UINT f_op__b;
+ UINT f_op__c;
+ UINT f_op__a;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_op__a = EXTRACT_MSB0_UINT (insn, 32, 13, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_op__c) = f_op__c;
+ FLD (f_op__a) = f_op__a;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_s_abc", "f_op__b 0x%x", 'x', f_op__b, "f_op__c 0x%x", 'x', f_op__c, "f_op__a 0x%x", 'x', f_op__a, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ld_s_abu:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ UINT f_op__b;
+ UINT f_op__c;
+ SI f_u5x4;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_u5x4 = ((EXTRACT_MSB0_UINT (insn, 32, 11, 5)) << (2));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_u5x4) = f_u5x4;
+ FLD (f_op__c) = f_op__c;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_s_abu", "f_op__b 0x%x", 'x', f_op__b, "f_u5x4 0x%x", 'x', f_u5x4, "f_op__c 0x%x", 'x', f_op__c, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ld_s_absp:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ UINT f_op__b;
+ SI f_u5x4;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u5x4 = ((EXTRACT_MSB0_UINT (insn, 32, 11, 5)) << (2));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_u5x4) = f_u5x4;
+ FLD (f_op__b) = f_op__b;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_s_absp", "f_u5x4 0x%x", 'x', f_u5x4, "f_op__b 0x%x", 'x', f_op__b, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ld_s_gprel:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_gprel.f
+ SI f_s9x4;
+
+ f_s9x4 = ((EXTRACT_MSB0_INT (insn, 32, 7, 9)) << (2));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_s9x4) = f_s9x4;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_s_gprel", "f_s9x4 0x%x", 'x', f_s9x4, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ld_s_pcrel:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_pcrel.f
+ UINT f_op__b;
+ SI f_u8x4;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u8x4 = ((EXTRACT_MSB0_UINT (insn, 32, 8, 8)) << (2));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_u8x4) = f_u8x4;
+ FLD (f_op__b) = f_op__b;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_s_pcrel", "f_u8x4 0x%x", 'x', f_u8x4, "f_op__b 0x%x", 'x', f_op__b, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldb_abs:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ UINT f_op__b;
+ UINT f_u8;
+ INT f_d9h;
+ UINT f_B_5_3;
+ UINT f_op_A;
+ UINT f_op_B;
+ INT f_s9;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8);
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s9 = ((f_u8) | (((f_d9h) << (8))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s9) = f_s9;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_abs", "f_op_B 0x%x", 'x', f_op_B, "f_s9 0x%x", 'x', f_s9, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldb__AW_abs:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ UINT f_op__b;
+ UINT f_u8;
+ INT f_d9h;
+ UINT f_B_5_3;
+ UINT f_op_A;
+ UINT f_op_B;
+ INT f_s9;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8);
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s9 = ((f_u8) | (((f_d9h) << (8))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s9) = f_s9;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb__AW_abs", "f_op_B 0x%x", 'x', f_op_B, "f_s9 0x%x", 'x', f_s9, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldb_as_abs:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_as_abs", "f_op_B 0x%x", 'x', f_op_B, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldb_abc:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_abc", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldb__AW_abc:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb__AW_abc", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldb_as_abc:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_as_abc", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldb_s_abc:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ UINT f_op__b;
+ UINT f_op__c;
+ UINT f_op__a;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_op__a = EXTRACT_MSB0_UINT (insn, 32, 13, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_op__c) = f_op__c;
+ FLD (f_op__a) = f_op__a;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_s_abc", "f_op__b 0x%x", 'x', f_op__b, "f_op__c 0x%x", 'x', f_op__c, "f_op__a 0x%x", 'x', f_op__a, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldb_s_abu:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ UINT f_op__b;
+ UINT f_op__c;
+ UINT f_u5;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_u5 = EXTRACT_MSB0_UINT (insn, 32, 11, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_u5) = f_u5;
+ FLD (f_op__c) = f_op__c;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_s_abu", "f_op__b 0x%x", 'x', f_op__b, "f_u5 0x%x", 'x', f_u5, "f_op__c 0x%x", 'x', f_op__c, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldb_s_absp:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ UINT f_op__b;
+ SI f_u5x4;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u5x4 = ((EXTRACT_MSB0_UINT (insn, 32, 11, 5)) << (2));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_u5x4) = f_u5x4;
+ FLD (f_op__b) = f_op__b;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_s_absp", "f_u5x4 0x%x", 'x', f_u5x4, "f_op__b 0x%x", 'x', f_op__b, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldb_s_gprel:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ldb_s_gprel.f
+ INT f_s9x1;
+
+ f_s9x1 = EXTRACT_MSB0_INT (insn, 32, 7, 9);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_s9x1) = f_s9x1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_s_gprel", "f_s9x1 0x%x", 'x', f_s9x1, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldw_abs:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ UINT f_op__b;
+ UINT f_u8;
+ INT f_d9h;
+ UINT f_B_5_3;
+ UINT f_op_A;
+ UINT f_op_B;
+ INT f_s9;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8);
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s9 = ((f_u8) | (((f_d9h) << (8))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s9) = f_s9;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldw_abs", "f_op_B 0x%x", 'x', f_op_B, "f_s9 0x%x", 'x', f_s9, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldw__AW_abs:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ UINT f_op__b;
+ UINT f_u8;
+ INT f_d9h;
+ UINT f_B_5_3;
+ UINT f_op_A;
+ UINT f_op_B;
+ INT f_s9;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8);
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s9 = ((f_u8) | (((f_d9h) << (8))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s9) = f_s9;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldw__AW_abs", "f_op_B 0x%x", 'x', f_op_B, "f_s9 0x%x", 'x', f_s9, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldw_abc:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldw_abc", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldw__AW_abc:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldw__AW_abc", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldw_s_abc:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ UINT f_op__b;
+ UINT f_op__c;
+ UINT f_op__a;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_op__a = EXTRACT_MSB0_UINT (insn, 32, 13, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_op__c) = f_op__c;
+ FLD (f_op__a) = f_op__a;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldw_s_abc", "f_op__b 0x%x", 'x', f_op__b, "f_op__c 0x%x", 'x', f_op__c, "f_op__a 0x%x", 'x', f_op__a, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldw_s_abu:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ldw_s_abu.f
+ UINT f_op__b;
+ UINT f_op__c;
+ SI f_u5x2;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_u5x2 = ((EXTRACT_MSB0_UINT (insn, 32, 11, 5)) << (1));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_u5x2) = f_u5x2;
+ FLD (f_op__c) = f_op__c;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldw_s_abu", "f_op__b 0x%x", 'x', f_op__b, "f_u5x2 0x%x", 'x', f_u5x2, "f_op__c 0x%x", 'x', f_op__c, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldw_s_gprel:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ldw_s_gprel.f
+ SI f_s9x2;
+
+ f_s9x2 = ((EXTRACT_MSB0_INT (insn, 32, 7, 9)) << (1));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_s9x2) = f_s9x2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldw_s_gprel", "f_s9x2 0x%x", 'x', f_s9x2, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_st_abs:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_u8;
+ INT f_d9h;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+ INT f_s9;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8);
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s9 = ((f_u8) | (((f_d9h) << (8))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_s9) = f_s9;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_abs", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_s9 0x%x", 'x', f_s9, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_st__AW_abs:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_u8;
+ INT f_d9h;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+ INT f_s9;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8);
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s9 = ((f_u8) | (((f_d9h) << (8))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_s9) = f_s9;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st__AW_abs", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_s9 0x%x", 'x', f_s9, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_st_s_abu:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ UINT f_op__b;
+ UINT f_op__c;
+ SI f_u5x4;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_u5x4 = ((EXTRACT_MSB0_UINT (insn, 32, 11, 5)) << (2));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_op__c) = f_op__c;
+ FLD (f_u5x4) = f_u5x4;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_s_abu", "f_op__b 0x%x", 'x', f_op__b, "f_op__c 0x%x", 'x', f_op__c, "f_u5x4 0x%x", 'x', f_u5x4, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_st_s_absp:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ UINT f_op__b;
+ SI f_u5x4;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u5x4 = ((EXTRACT_MSB0_UINT (insn, 32, 11, 5)) << (2));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_u5x4) = f_u5x4;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_s_absp", "f_op__b 0x%x", 'x', f_op__b, "f_u5x4 0x%x", 'x', f_u5x4, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stb_abs:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_u8;
+ INT f_d9h;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+ INT f_s9;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8);
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s9 = ((f_u8) | (((f_d9h) << (8))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_s9) = f_s9;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_abs", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_s9 0x%x", 'x', f_s9, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stb__AW_abs:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_u8;
+ INT f_d9h;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+ INT f_s9;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8);
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s9 = ((f_u8) | (((f_d9h) << (8))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_s9) = f_s9;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb__AW_abs", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_s9 0x%x", 'x', f_s9, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stb_as_abs:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_as_abs", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stb_s_abu:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ UINT f_op__b;
+ UINT f_op__c;
+ UINT f_u5;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_u5 = EXTRACT_MSB0_UINT (insn, 32, 11, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_op__c) = f_op__c;
+ FLD (f_u5) = f_u5;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_s_abu", "f_op__b 0x%x", 'x', f_op__b, "f_op__c 0x%x", 'x', f_op__c, "f_u5 0x%x", 'x', f_u5, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stb_s_absp:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ UINT f_op__b;
+ SI f_u5x4;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u5x4 = ((EXTRACT_MSB0_UINT (insn, 32, 11, 5)) << (2));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_u5x4) = f_u5x4;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_s_absp", "f_op__b 0x%x", 'x', f_op__b, "f_u5x4 0x%x", 'x', f_u5x4, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stw_abs:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_u8;
+ INT f_d9h;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+ INT f_s9;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8);
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s9 = ((f_u8) | (((f_d9h) << (8))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_s9) = f_s9;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stw_abs", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_s9 0x%x", 'x', f_s9, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stw__AW_abs:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_u8;
+ INT f_d9h;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+ INT f_s9;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8);
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s9 = ((f_u8) | (((f_d9h) << (8))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_s9) = f_s9;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stw__AW_abs", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_s9 0x%x", 'x', f_s9, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stw_s_abu:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ldw_s_abu.f
+ UINT f_op__b;
+ UINT f_op__c;
+ SI f_u5x2;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_u5x2 = ((EXTRACT_MSB0_UINT (insn, 32, 11, 5)) << (1));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_op__c) = f_op__c;
+ FLD (f_u5x2) = f_u5x2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stw_s_abu", "f_op__b 0x%x", 'x', f_op__b, "f_op__c 0x%x", 'x', f_op__c, "f_u5x2 0x%x", 'x', f_u5x2, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_L_s12__RA_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_L_s12__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_ccu6__RA_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_ccu6__RA_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_L_u6__RA_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_L_u6__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_L_r_r__RA__RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_L_r_r__RA__RC", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_cc__RA__RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_cc__RA__RC", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_s_abc:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ UINT f_op__b;
+ UINT f_op__c;
+ UINT f_op__a;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_op__a = EXTRACT_MSB0_UINT (insn, 32, 13, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_op__c) = f_op__c;
+ FLD (f_op__a) = f_op__a;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_s_abc", "f_op__b 0x%x", 'x', f_op__b, "f_op__c 0x%x", 'x', f_op__c, "f_op__a 0x%x", 'x', f_op__a, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_s_cbu3:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ UINT f_op__b;
+ UINT f_op__c;
+ UINT f_u3;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_u3 = EXTRACT_MSB0_UINT (insn, 32, 13, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_u3) = f_u3;
+ FLD (f_op__c) = f_op__c;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_s_cbu3", "f_op__b 0x%x", 'x', f_op__b, "f_u3 0x%x", 'x', f_u3, "f_op__c 0x%x", 'x', f_op__c, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_s_mcah:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ UINT f_op__b;
+ UINT f_h_2_0;
+ UINT f_h_5_3;
+ UINT f_op_h;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_h_2_0 = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_h_5_3 = EXTRACT_MSB0_UINT (insn, 32, 13, 3);
+{
+ f_op_h = ((f_h_2_0) | (((f_h_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_op_h) = f_op_h;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_s_mcah", "f_op__b 0x%x", 'x', f_op__b, "f_op_h 0x%x", 'x', f_op_h, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_s_absp:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ UINT f_op__b;
+ SI f_u5x4;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u5x4 = ((EXTRACT_MSB0_UINT (insn, 32, 11, 5)) << (2));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_u5x4) = f_u5x4;
+ FLD (f_op__b) = f_op__b;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_s_absp", "f_u5x4 0x%x", 'x', f_u5x4, "f_op__b 0x%x", 'x', f_op__b, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_s_asspsp:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ SI f_u5x4;
+
+ f_u5x4 = ((EXTRACT_MSB0_UINT (insn, 32, 11, 5)) << (2));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_u5x4) = f_u5x4;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_s_asspsp", "f_u5x4 0x%x", 'x', f_u5x4, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_s_gp:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_gprel.f
+ SI f_s9x4;
+
+ f_s9x4 = ((EXTRACT_MSB0_INT (insn, 32, 7, 9)) << (2));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_s9x4) = f_s9x4;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_s_gp", "f_s9x4 0x%x", 'x', f_s9x4, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_s_r_u7:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_s_r_u7.f
+ UINT f_op__b;
+ UINT f_u7;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u7 = EXTRACT_MSB0_UINT (insn, 32, 9, 7);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_u7) = f_u7;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_s_r_u7", "f_op__b 0x%x", 'x', f_op__b, "f_u7 0x%x", 'x', f_u7, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_adc_L_s12__RA_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_adc_L_s12__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_adc_ccu6__RA_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_adc_ccu6__RA_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_adc_L_u6__RA_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_adc_L_u6__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_adc_L_r_r__RA__RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_adc_L_r_r__RA__RC", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_adc_cc__RA__RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_adc_cc__RA__RC", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_I16_GO_SUB_s_go:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ UINT f_op__b;
+ UINT f_op__c;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_op__c) = f_op__c;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_I16_GO_SUB_s_go", "f_op__b 0x%x", 'x', f_op__b, "f_op__c 0x%x", 'x', f_op__c, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sub_s_go_sub_ne:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ UINT f_op__b;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sub_s_go_sub_ne", "f_op__b 0x%x", 'x', f_op__b, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sub_s_ssb:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ UINT f_op__b;
+ UINT f_u5;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u5 = EXTRACT_MSB0_UINT (insn, 32, 11, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_u5) = f_u5;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sub_s_ssb", "f_op__b 0x%x", 'x', f_op__b, "f_u5 0x%x", 'x', f_u5, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_and_L_s12__RA_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and_L_s12__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_and_ccu6__RA_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and_ccu6__RA_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_and_L_u6__RA_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and_L_u6__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_and_L_r_r__RA__RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and_L_r_r__RA__RC", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_and_cc__RA__RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and_cc__RA__RC", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mov_L_s12_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_s12) = f_s12;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mov_L_s12_", "f_F 0x%x", 'x', f_F, "f_s12 0x%x", 'x', f_s12, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mov_ccu6_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mov_ccu6_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mov_L_u6_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mov_L_u6_", "f_F 0x%x", 'x', f_F, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mov_L_r_r__RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mov_L_r_r__RC", "f_F 0x%x", 'x', f_F, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mov_cc__RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mov_cc__RC", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mov_s_mcah:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ UINT f_op__b;
+ UINT f_h_2_0;
+ UINT f_h_5_3;
+ UINT f_op_h;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_h_2_0 = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_h_5_3 = EXTRACT_MSB0_UINT (insn, 32, 13, 3);
+{
+ f_op_h = ((f_h_2_0) | (((f_h_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_h) = f_op_h;
+ FLD (f_op__b) = f_op__b;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mov_s_mcah", "f_op_h 0x%x", 'x', f_op_h, "f_op__b 0x%x", 'x', f_op__b, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mov_s_mcahb:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ UINT f_op__b;
+ UINT f_h_2_0;
+ UINT f_h_5_3;
+ UINT f_op_h;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_h_2_0 = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_h_5_3 = EXTRACT_MSB0_UINT (insn, 32, 13, 3);
+{
+ f_op_h = ((f_h_2_0) | (((f_h_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_op_h) = f_op_h;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mov_s_mcahb", "f_op__b 0x%x", 'x', f_op__b, "f_op_h 0x%x", 'x', f_op_h, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mov_s_r_u7:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ UINT f_op__b;
+ UINT f_u8;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_u8) = f_u8;
+ FLD (f_op__b) = f_op__b;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mov_s_r_u7", "f_u8 0x%x", 'x', f_u8, "f_op__b 0x%x", 'x', f_op__b, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_tst_L_s12_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_tst_L_s12_", "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_tst_ccu6_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_tst_ccu6_", "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_tst_L_u6_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_tst_L_u6_", "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_tst_L_r_r__RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_tst_L_r_r__RC", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_tst_cc__RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_tst_cc__RC", "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_tst_s_go:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ UINT f_op__b;
+ UINT f_op__c;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_op__c) = f_op__c;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_tst_s_go", "f_op__b 0x%x", 'x', f_op__b, "f_op__c 0x%x", 'x', f_op__c, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmp_L_s12_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp_L_s12_", "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmp_ccu6_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp_ccu6_", "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmp_L_u6_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp_L_u6_", "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmp_L_r_r__RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp_L_r_r__RC", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmp_cc__RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp_cc__RC", "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmp_s_mcah:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ UINT f_op__b;
+ UINT f_h_2_0;
+ UINT f_h_5_3;
+ UINT f_op_h;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_h_2_0 = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_h_5_3 = EXTRACT_MSB0_UINT (insn, 32, 13, 3);
+{
+ f_op_h = ((f_h_2_0) | (((f_h_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_op_h) = f_op_h;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp_s_mcah", "f_op__b 0x%x", 'x', f_op__b, "f_op_h 0x%x", 'x', f_op_h, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmp_s_r_u7:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_s_r_u7.f
+ UINT f_op__b;
+ UINT f_u7;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u7 = EXTRACT_MSB0_UINT (insn, 32, 9, 7);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_u7) = f_u7;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp_s_r_u7", "f_op__b 0x%x", 'x', f_op__b, "f_u7 0x%x", 'x', f_u7, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_btst_s_ssb:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ UINT f_op__b;
+ UINT f_u5;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u5 = EXTRACT_MSB0_UINT (insn, 32, 11, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_u5) = f_u5;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_btst_s_ssb", "f_op__b 0x%x", 'x', f_op__b, "f_u5 0x%x", 'x', f_u5, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mpy_L_s12__RA_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mpy_L_s12__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mpy_ccu6__RA_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mpy_ccu6__RA_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mpy_L_u6__RA_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mpy_L_u6__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mpy_L_r_r__RA__RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mpy_L_r_r__RA__RC", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mpy_cc__RA__RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mpy_cc__RA__RC", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_L_r_r___RC_noilink_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_Cj;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_Cj = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_Cj) = f_op_Cj;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_L_r_r___RC_noilink_", "f_F 0x%x", 'x', f_F, "f_op_Cj 0x%x", 'x', f_op_Cj, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_cc___RC_noilink_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_Cj;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_Cj = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_Cj) = f_op_Cj;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_cc___RC_noilink_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_Cj 0x%x", 'x', f_op_Cj, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_L_r_r___RC_ilink_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_Cj;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_Cj = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_Cj) = f_op_Cj;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_L_r_r___RC_ilink_", "f_F 0x%x", 'x', f_F, "f_op_Cj 0x%x", 'x', f_op_Cj, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_cc___RC_ilink_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_Cj;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_Cj = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_Cj) = f_op_Cj;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_cc___RC_ilink_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_Cj 0x%x", 'x', f_op_Cj, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_L_s12_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_L_s12_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_ccu6_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_ccu6_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_L_u6_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_L_u6_", "f_F 0x%x", 'x', f_F, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_s:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ UINT f_op__b;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_s", "f_op__b 0x%x", 'x', f_op__b, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_s__S:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_s__S", (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_seq__S:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_seq__S", (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_L_s12_d_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_L_s12_d_", "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_ccu6_d_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_ccu6_d_", "f_cond_Q 0x%x", 'x', f_cond_Q, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_L_u6_d_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_L_u6_d_", "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_L_r_r_d___RC_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_L_r_r_d___RC_", "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_cc_d___RC_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_cc_d___RC_", "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_jl_L_s12_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl_L_s12_", "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_jl_ccu6_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl_ccu6_", "f_cond_Q 0x%x", 'x', f_cond_Q, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_jl_L_u6_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl_L_u6_", "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_jl_s:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ UINT f_op__b;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl_s", "f_op__b 0x%x", 'x', f_op__b, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_jl_L_r_r___RC_noilink_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_Cj;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_Cj = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_Cj) = f_op_Cj;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl_L_r_r___RC_noilink_", "f_op_Cj 0x%x", 'x', f_op_Cj, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_jl_cc___RC_noilink_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_Cj;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_Cj = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_Cj) = f_op_Cj;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl_cc___RC_noilink_", "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_Cj 0x%x", 'x', f_op_Cj, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_jl_L_r_r_d___RC_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl_L_r_r_d___RC_", "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_jl_cc_d___RC_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl_cc_d___RC_", "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_jl_s_d:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ UINT f_op__b;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl_s_d", "f_op__b 0x%x", 'x', f_op__b, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lp_L_s12_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_lp_L_s12_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12x2;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12x2 = ((((f_u6) << (1))) | (((f_s12h) << (7))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12x2) = f_s12x2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lp_L_s12_", "f_op_B 0x%x", 'x', f_op_B, "f_s12x2 0x%x", 'x', f_s12x2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lpcc_ccu6:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_lpcc_ccu6.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ SI f_u6x2;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6x2 = ((EXTRACT_MSB0_UINT (insn, 32, 20, 6)) << (1));
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_u6x2) = f_u6x2;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lpcc_ccu6", "f_cond_Q 0x%x", 'x', f_cond_Q, "f_u6x2 0x%x", 'x', f_u6x2, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_flag_L_s12_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_flag_L_s12_", "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_flag_ccu6_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_flag_ccu6_", "f_cond_Q 0x%x", 'x', f_cond_Q, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_flag_L_u6_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_flag_L_u6_", "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_flag_L_r_r__RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_flag_L_r_r__RC", "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_flag_cc__RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_flag_cc__RC", "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lr_L_r_r___RC_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lr_L_r_r___RC_", "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lr_L_s12_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lr_L_s12_", "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lr_L_u6_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lr_L_u6_", "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sr_L_r_r___RC_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sr_L_r_r___RC_", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sr_L_s12_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sr_L_s12_", "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sr_L_u6_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sr_L_u6_", "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asl_L_r_r__RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asl_L_r_r__RC", "f_F 0x%x", 'x', f_F, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asl_L_u6_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asl_L_u6_", "f_F 0x%x", 'x', f_F, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asr_L_r_r__RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asr_L_r_r__RC", "f_F 0x%x", 'x', f_F, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asr_L_u6_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asr_L_u6_", "f_F 0x%x", 'x', f_F, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_rrc_L_r_r__RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rrc_L_r_r__RC", "f_F 0x%x", 'x', f_F, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_rrc_L_u6_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rrc_L_u6_", "f_F 0x%x", 'x', f_F, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sexb_L_r_r__RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sexb_L_r_r__RC", "f_F 0x%x", 'x', f_F, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sexb_L_u6_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sexb_L_u6_", "f_F 0x%x", 'x', f_F, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sexw_L_r_r__RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sexw_L_r_r__RC", "f_F 0x%x", 'x', f_F, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sexw_L_u6_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sexw_L_u6_", "f_F 0x%x", 'x', f_F, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_abs_L_r_r__RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_abs_L_r_r__RC", "f_F 0x%x", 'x', f_F, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_abs_L_u6_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_abs_L_u6_", "f_F 0x%x", 'x', f_F, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_not_L_r_r__RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_not_L_r_r__RC", "f_F 0x%x", 'x', f_F, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_not_L_u6_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_not_L_u6_", "f_F 0x%x", 'x', f_F, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_swi:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_swi", (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_trap_s:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_trap_s.f
+ UINT f_trapnum;
+
+ f_trapnum = EXTRACT_MSB0_UINT (insn, 32, 5, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_trapnum) = f_trapnum;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_trap_s", "f_trapnum 0x%x", 'x', f_trapnum, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_brk:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_brk", (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asl_L_s12__RA_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asl_L_s12__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asl_ccu6__RA_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asl_ccu6__RA_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asl_L_u6__RA_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asl_L_u6__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asl_L_r_r__RA__RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asl_L_r_r__RA__RC", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asl_cc__RA__RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asl_cc__RA__RC", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mul64_L_s12_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mul64_L_s12_", "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mul64_ccu6_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mul64_ccu6_", "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mul64_L_u6_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mul64_L_u6_", "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mul64_L_r_r__RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mul64_L_r_r__RC", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mul64_cc__RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mul64_cc__RC", "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mul64_s_go:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ UINT f_op__b;
+ UINT f_op__c;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_op__c) = f_op__c;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mul64_s_go", "f_op__b 0x%x", 'x', f_op__b, "f_op__c 0x%x", 'x', f_op__c, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_adds_L_s12__RA_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_adds_L_s12__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_adds_ccu6__RA_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_adds_ccu6__RA_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_adds_L_u6__RA_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_adds_L_u6__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_adds_L_r_r__RA__RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_adds_L_r_r__RA__RC", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_adds_cc__RA__RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_adds_cc__RA__RC", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_divaw_L_s12__RA_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_divaw_L_s12__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_divaw_ccu6__RA_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_divaw_ccu6__RA_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_divaw_L_u6__RA_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_divaw_L_u6__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_divaw_L_r_r__RA__RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_divaw_L_r_r__RA__RC", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_divaw_cc__RA__RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_divaw_cc__RA__RC", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asls_L_s12__RA_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asls_L_s12__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asls_ccu6__RA_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asls_ccu6__RA_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asls_L_u6__RA_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asls_L_u6__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asls_L_r_r__RA__RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asls_L_r_r__RA__RC", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asls_cc__RA__RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asls_cc__RA__RC", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_swap_L_r_r__RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_swap_L_r_r__RC", "f_F 0x%x", 'x', f_F, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_swap_L_u6_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_swap_L_u6_", "f_F 0x%x", 'x', f_F, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_norm_L_u6_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_norm_L_u6_", "f_F 0x%x", 'x', f_F, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_rnd16_L_r_r__RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rnd16_L_r_r__RC", "f_F 0x%x", 'x', f_F, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_rnd16_L_u6_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rnd16_L_u6_", "f_F 0x%x", 'x', f_F, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_abssw_L_r_r__RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_abssw_L_r_r__RC", "f_F 0x%x", 'x', f_F, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_abssw_L_u6_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_abssw_L_u6_", "f_F 0x%x", 'x', f_F, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_abss_L_u6_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_abss_L_u6_", "f_F 0x%x", 'x', f_F, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_nop_s:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nop_s", (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_pop_s_b:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ UINT f_op__b;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_pop_s_b", "f_op__b 0x%x", 'x', f_op__b, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_pop_s_blink:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_pop_s_blink", (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_push_s_b:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ UINT f_op__b;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_push_s_b", "f_op__b 0x%x", 'x', f_op__b, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_push_s_blink:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_push_s_blink", (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mullw_L_s12__RA_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mullw_L_s12__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mullw_ccu6__RA_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mullw_ccu6__RA_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mullw_L_u6__RA_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mullw_L_u6__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mullw_L_r_r__RA__RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mullw_L_r_r__RA__RC", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mullw_cc__RA__RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mullw_cc__RA__RC", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_maclw_L_s12__RA_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_maclw_L_s12__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_maclw_ccu6__RA_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_maclw_ccu6__RA_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_maclw_L_u6__RA_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_maclw_L_u6__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_maclw_L_r_r__RA__RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_maclw_L_r_r__RA__RC", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_maclw_cc__RA__RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_maclw_cc__RA__RC", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_machulw_L_s12__RA_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machulw_L_s12__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_machulw_ccu6__RA_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machulw_ccu6__RA_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_machulw_L_u6__RA_:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machulw_L_u6__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_machulw_L_r_r__RA__RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machulw_L_r_r__RA__RC", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_machulw_cc__RA__RC:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machulw_cc__RA__RC", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_current_loop_end:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_current_loop_end", (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_current_loop_end_after_branch:
+ {
+ const IDESC *idesc = &a5f_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_current_loop_end_after_branch", (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+}
diff --git a/sim/arc/decode5.h b/sim/arc/decode5.h
new file mode 100644
index 0000000..1e6d5e0
--- /dev/null
+++ b/sim/arc/decode5.h
@@ -0,0 +1,225 @@
+/* Decode header for a5f.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2007 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#ifndef A5F_DECODE_H
+#define A5F_DECODE_H
+
+extern const IDESC *a5f_decode (SIM_CPU *, IADDR,
+ CGEN_INSN_INT, CGEN_INSN_INT,
+ ARGBUF *);
+extern void a5f_init_idesc_table (SIM_CPU *);
+extern void a5f_sem_init_idesc_table (SIM_CPU *);
+extern void a5f_semf_init_idesc_table (SIM_CPU *);
+
+/* Enum declaration for instructions in cpu family a5f. */
+typedef enum a5f_insn_type {
+ A5F_INSN_X_INVALID, A5F_INSN_X_AFTER, A5F_INSN_X_BEFORE, A5F_INSN_X_CTI_CHAIN
+ , A5F_INSN_X_CHAIN, A5F_INSN_X_BEGIN, A5F_INSN_B_S, A5F_INSN_BCC_S
+ , A5F_INSN_BRCC_S, A5F_INSN_BCC_L, A5F_INSN_BCC_L_D, A5F_INSN_B_L
+ , A5F_INSN_B_L_D, A5F_INSN_BRCC_RC, A5F_INSN_BRCC_RC_D, A5F_INSN_BRCC_U6
+ , A5F_INSN_BRCC_U6_D, A5F_INSN_BL_S, A5F_INSN_BLCC, A5F_INSN_BLCC_D
+ , A5F_INSN_BL, A5F_INSN_BL_D, A5F_INSN_LD_ABS, A5F_INSN_LD__AW_ABS
+ , A5F_INSN_LD_AB_ABS, A5F_INSN_LD_AS_ABS, A5F_INSN_LD_ABC, A5F_INSN_LD__AW_ABC
+ , A5F_INSN_LD_AB_ABC, A5F_INSN_LD_AS_ABC, A5F_INSN_LD_S_ABC, A5F_INSN_LD_S_ABU
+ , A5F_INSN_LD_S_ABSP, A5F_INSN_LD_S_GPREL, A5F_INSN_LD_S_PCREL, A5F_INSN_LDB_ABS
+ , A5F_INSN_LDB__AW_ABS, A5F_INSN_LDB_AB_ABS, A5F_INSN_LDB_AS_ABS, A5F_INSN_LDB_ABC
+ , A5F_INSN_LDB__AW_ABC, A5F_INSN_LDB_AB_ABC, A5F_INSN_LDB_AS_ABC, A5F_INSN_LDB_S_ABC
+ , A5F_INSN_LDB_S_ABU, A5F_INSN_LDB_S_ABSP, A5F_INSN_LDB_S_GPREL, A5F_INSN_LDB_X_ABS
+ , A5F_INSN_LDB__AW_X_ABS, A5F_INSN_LDB_AB_X_ABS, A5F_INSN_LDB_AS_X_ABS, A5F_INSN_LDB_X_ABC
+ , A5F_INSN_LDB__AW_X_ABC, A5F_INSN_LDB_AB_X_ABC, A5F_INSN_LDB_AS_X_ABC, A5F_INSN_LDW_ABS
+ , A5F_INSN_LDW__AW_ABS, A5F_INSN_LDW_AB_ABS, A5F_INSN_LDW_AS_ABS, A5F_INSN_LDW_ABC
+ , A5F_INSN_LDW__AW_ABC, A5F_INSN_LDW_AB_ABC, A5F_INSN_LDW_AS_ABC, A5F_INSN_LDW_S_ABC
+ , A5F_INSN_LDW_S_ABU, A5F_INSN_LDW_S_GPREL, A5F_INSN_LDW_X_ABS, A5F_INSN_LDW__AW_X_ABS
+ , A5F_INSN_LDW_AB_X_ABS, A5F_INSN_LDW_AS_X_ABS, A5F_INSN_LDW_X_ABC, A5F_INSN_LDW__AW_X_ABC
+ , A5F_INSN_LDW_AB_X_ABC, A5F_INSN_LDW_AS_X_ABC, A5F_INSN_LDW_S_X_ABU, A5F_INSN_ST_ABS
+ , A5F_INSN_ST__AW_ABS, A5F_INSN_ST_AB_ABS, A5F_INSN_ST_AS_ABS, A5F_INSN_ST_S_ABU
+ , A5F_INSN_ST_S_ABSP, A5F_INSN_STB_ABS, A5F_INSN_STB__AW_ABS, A5F_INSN_STB_AB_ABS
+ , A5F_INSN_STB_AS_ABS, A5F_INSN_STB_S_ABU, A5F_INSN_STB_S_ABSP, A5F_INSN_STW_ABS
+ , A5F_INSN_STW__AW_ABS, A5F_INSN_STW_AB_ABS, A5F_INSN_STW_AS_ABS, A5F_INSN_STW_S_ABU
+ , A5F_INSN_ADD_L_S12__RA_, A5F_INSN_ADD_CCU6__RA_, A5F_INSN_ADD_L_U6__RA_, A5F_INSN_ADD_L_R_R__RA__RC
+ , A5F_INSN_ADD_CC__RA__RC, A5F_INSN_ADD_S_ABC, A5F_INSN_ADD_S_CBU3, A5F_INSN_ADD_S_MCAH
+ , A5F_INSN_ADD_S_ABSP, A5F_INSN_ADD_S_ASSPSP, A5F_INSN_ADD_S_GP, A5F_INSN_ADD_S_R_U7
+ , A5F_INSN_ADC_L_S12__RA_, A5F_INSN_ADC_CCU6__RA_, A5F_INSN_ADC_L_U6__RA_, A5F_INSN_ADC_L_R_R__RA__RC
+ , A5F_INSN_ADC_CC__RA__RC, A5F_INSN_SUB_L_S12__RA_, A5F_INSN_SUB_CCU6__RA_, A5F_INSN_SUB_L_U6__RA_
+ , A5F_INSN_SUB_L_R_R__RA__RC, A5F_INSN_SUB_CC__RA__RC, A5F_INSN_SUB_S_CBU3, A5F_INSN_I16_GO_SUB_S_GO
+ , A5F_INSN_SUB_S_GO_SUB_NE, A5F_INSN_SUB_S_SSB, A5F_INSN_SUB_S_ASSPSP, A5F_INSN_SBC_L_S12__RA_
+ , A5F_INSN_SBC_CCU6__RA_, A5F_INSN_SBC_L_U6__RA_, A5F_INSN_SBC_L_R_R__RA__RC, A5F_INSN_SBC_CC__RA__RC
+ , A5F_INSN_AND_L_S12__RA_, A5F_INSN_AND_CCU6__RA_, A5F_INSN_AND_L_U6__RA_, A5F_INSN_AND_L_R_R__RA__RC
+ , A5F_INSN_AND_CC__RA__RC, A5F_INSN_I16_GO_AND_S_GO, A5F_INSN_OR_L_S12__RA_, A5F_INSN_OR_CCU6__RA_
+ , A5F_INSN_OR_L_U6__RA_, A5F_INSN_OR_L_R_R__RA__RC, A5F_INSN_OR_CC__RA__RC, A5F_INSN_I16_GO_OR_S_GO
+ , A5F_INSN_BIC_L_S12__RA_, A5F_INSN_BIC_CCU6__RA_, A5F_INSN_BIC_L_U6__RA_, A5F_INSN_BIC_L_R_R__RA__RC
+ , A5F_INSN_BIC_CC__RA__RC, A5F_INSN_I16_GO_BIC_S_GO, A5F_INSN_XOR_L_S12__RA_, A5F_INSN_XOR_CCU6__RA_
+ , A5F_INSN_XOR_L_U6__RA_, A5F_INSN_XOR_L_R_R__RA__RC, A5F_INSN_XOR_CC__RA__RC, A5F_INSN_I16_GO_XOR_S_GO
+ , A5F_INSN_MAX_L_S12__RA_, A5F_INSN_MAX_CCU6__RA_, A5F_INSN_MAX_L_U6__RA_, A5F_INSN_MAX_L_R_R__RA__RC
+ , A5F_INSN_MAX_CC__RA__RC, A5F_INSN_MIN_L_S12__RA_, A5F_INSN_MIN_CCU6__RA_, A5F_INSN_MIN_L_U6__RA_
+ , A5F_INSN_MIN_L_R_R__RA__RC, A5F_INSN_MIN_CC__RA__RC, A5F_INSN_MOV_L_S12_, A5F_INSN_MOV_CCU6_
+ , A5F_INSN_MOV_L_U6_, A5F_INSN_MOV_L_R_R__RC, A5F_INSN_MOV_CC__RC, A5F_INSN_MOV_S_MCAH
+ , A5F_INSN_MOV_S_MCAHB, A5F_INSN_MOV_S_R_U7, A5F_INSN_TST_L_S12_, A5F_INSN_TST_CCU6_
+ , A5F_INSN_TST_L_U6_, A5F_INSN_TST_L_R_R__RC, A5F_INSN_TST_CC__RC, A5F_INSN_TST_S_GO
+ , A5F_INSN_CMP_L_S12_, A5F_INSN_CMP_CCU6_, A5F_INSN_CMP_L_U6_, A5F_INSN_CMP_L_R_R__RC
+ , A5F_INSN_CMP_CC__RC, A5F_INSN_CMP_S_MCAH, A5F_INSN_CMP_S_R_U7, A5F_INSN_RCMP_L_S12_
+ , A5F_INSN_RCMP_CCU6_, A5F_INSN_RCMP_L_U6_, A5F_INSN_RCMP_L_R_R__RC, A5F_INSN_RCMP_CC__RC
+ , A5F_INSN_RSUB_L_S12__RA_, A5F_INSN_RSUB_CCU6__RA_, A5F_INSN_RSUB_L_U6__RA_, A5F_INSN_RSUB_L_R_R__RA__RC
+ , A5F_INSN_RSUB_CC__RA__RC, A5F_INSN_BSET_L_S12__RA_, A5F_INSN_BSET_CCU6__RA_, A5F_INSN_BSET_L_U6__RA_
+ , A5F_INSN_BSET_L_R_R__RA__RC, A5F_INSN_BSET_CC__RA__RC, A5F_INSN_BSET_S_SSB, A5F_INSN_BCLR_L_S12__RA_
+ , A5F_INSN_BCLR_CCU6__RA_, A5F_INSN_BCLR_L_U6__RA_, A5F_INSN_BCLR_L_R_R__RA__RC, A5F_INSN_BCLR_CC__RA__RC
+ , A5F_INSN_BCLR_S_SSB, A5F_INSN_BTST_L_S12_, A5F_INSN_BTST_CCU6_, A5F_INSN_BTST_L_U6_
+ , A5F_INSN_BTST_L_R_R__RC, A5F_INSN_BTST_CC__RC, A5F_INSN_BTST_S_SSB, A5F_INSN_BXOR_L_S12__RA_
+ , A5F_INSN_BXOR_CCU6__RA_, A5F_INSN_BXOR_L_U6__RA_, A5F_INSN_BXOR_L_R_R__RA__RC, A5F_INSN_BXOR_CC__RA__RC
+ , A5F_INSN_BMSK_L_S12__RA_, A5F_INSN_BMSK_CCU6__RA_, A5F_INSN_BMSK_L_U6__RA_, A5F_INSN_BMSK_L_R_R__RA__RC
+ , A5F_INSN_BMSK_CC__RA__RC, A5F_INSN_BMSK_S_SSB, A5F_INSN_ADD1_L_S12__RA_, A5F_INSN_ADD1_CCU6__RA_
+ , A5F_INSN_ADD1_L_U6__RA_, A5F_INSN_ADD1_L_R_R__RA__RC, A5F_INSN_ADD1_CC__RA__RC, A5F_INSN_I16_GO_ADD1_S_GO
+ , A5F_INSN_ADD2_L_S12__RA_, A5F_INSN_ADD2_CCU6__RA_, A5F_INSN_ADD2_L_U6__RA_, A5F_INSN_ADD2_L_R_R__RA__RC
+ , A5F_INSN_ADD2_CC__RA__RC, A5F_INSN_I16_GO_ADD2_S_GO, A5F_INSN_ADD3_L_S12__RA_, A5F_INSN_ADD3_CCU6__RA_
+ , A5F_INSN_ADD3_L_U6__RA_, A5F_INSN_ADD3_L_R_R__RA__RC, A5F_INSN_ADD3_CC__RA__RC, A5F_INSN_I16_GO_ADD3_S_GO
+ , A5F_INSN_SUB1_L_S12__RA_, A5F_INSN_SUB1_CCU6__RA_, A5F_INSN_SUB1_L_U6__RA_, A5F_INSN_SUB1_L_R_R__RA__RC
+ , A5F_INSN_SUB1_CC__RA__RC, A5F_INSN_SUB2_L_S12__RA_, A5F_INSN_SUB2_CCU6__RA_, A5F_INSN_SUB2_L_U6__RA_
+ , A5F_INSN_SUB2_L_R_R__RA__RC, A5F_INSN_SUB2_CC__RA__RC, A5F_INSN_SUB3_L_S12__RA_, A5F_INSN_SUB3_CCU6__RA_
+ , A5F_INSN_SUB3_L_U6__RA_, A5F_INSN_SUB3_L_R_R__RA__RC, A5F_INSN_SUB3_CC__RA__RC, A5F_INSN_MPY_L_S12__RA_
+ , A5F_INSN_MPY_CCU6__RA_, A5F_INSN_MPY_L_U6__RA_, A5F_INSN_MPY_L_R_R__RA__RC, A5F_INSN_MPY_CC__RA__RC
+ , A5F_INSN_MPYH_L_S12__RA_, A5F_INSN_MPYH_CCU6__RA_, A5F_INSN_MPYH_L_U6__RA_, A5F_INSN_MPYH_L_R_R__RA__RC
+ , A5F_INSN_MPYH_CC__RA__RC, A5F_INSN_MPYHU_L_S12__RA_, A5F_INSN_MPYHU_CCU6__RA_, A5F_INSN_MPYHU_L_U6__RA_
+ , A5F_INSN_MPYHU_L_R_R__RA__RC, A5F_INSN_MPYHU_CC__RA__RC, A5F_INSN_MPYU_L_S12__RA_, A5F_INSN_MPYU_CCU6__RA_
+ , A5F_INSN_MPYU_L_U6__RA_, A5F_INSN_MPYU_L_R_R__RA__RC, A5F_INSN_MPYU_CC__RA__RC, A5F_INSN_J_L_R_R___RC_NOILINK_
+ , A5F_INSN_J_CC___RC_NOILINK_, A5F_INSN_J_L_R_R___RC_ILINK_, A5F_INSN_J_CC___RC_ILINK_, A5F_INSN_J_L_S12_
+ , A5F_INSN_J_CCU6_, A5F_INSN_J_L_U6_, A5F_INSN_J_S, A5F_INSN_J_S__S
+ , A5F_INSN_J_SEQ__S, A5F_INSN_J_SNE__S, A5F_INSN_J_L_S12_D_, A5F_INSN_J_CCU6_D_
+ , A5F_INSN_J_L_U6_D_, A5F_INSN_J_L_R_R_D___RC_, A5F_INSN_J_CC_D___RC_, A5F_INSN_J_S_D
+ , A5F_INSN_J_S__S_D, A5F_INSN_JL_L_S12_, A5F_INSN_JL_CCU6_, A5F_INSN_JL_L_U6_
+ , A5F_INSN_JL_S, A5F_INSN_JL_L_R_R___RC_NOILINK_, A5F_INSN_JL_CC___RC_NOILINK_, A5F_INSN_JL_L_S12_D_
+ , A5F_INSN_JL_CCU6_D_, A5F_INSN_JL_L_U6_D_, A5F_INSN_JL_L_R_R_D___RC_, A5F_INSN_JL_CC_D___RC_
+ , A5F_INSN_JL_S_D, A5F_INSN_LP_L_S12_, A5F_INSN_LPCC_CCU6, A5F_INSN_FLAG_L_S12_
+ , A5F_INSN_FLAG_CCU6_, A5F_INSN_FLAG_L_U6_, A5F_INSN_FLAG_L_R_R__RC, A5F_INSN_FLAG_CC__RC
+ , A5F_INSN_LR_L_R_R___RC_, A5F_INSN_LR_L_S12_, A5F_INSN_LR_L_U6_, A5F_INSN_SR_L_R_R___RC_
+ , A5F_INSN_SR_L_S12_, A5F_INSN_SR_L_U6_, A5F_INSN_ASL_L_R_R__RC, A5F_INSN_ASL_L_U6_
+ , A5F_INSN_I16_GO_ASL_S_GO, A5F_INSN_ASR_L_R_R__RC, A5F_INSN_ASR_L_U6_, A5F_INSN_I16_GO_ASR_S_GO
+ , A5F_INSN_LSR_L_R_R__RC, A5F_INSN_LSR_L_U6_, A5F_INSN_I16_GO_LSR_S_GO, A5F_INSN_ROR_L_R_R__RC
+ , A5F_INSN_ROR_L_U6_, A5F_INSN_RRC_L_R_R__RC, A5F_INSN_RRC_L_U6_, A5F_INSN_SEXB_L_R_R__RC
+ , A5F_INSN_SEXB_L_U6_, A5F_INSN_I16_GO_SEXB_S_GO, A5F_INSN_SEXW_L_R_R__RC, A5F_INSN_SEXW_L_U6_
+ , A5F_INSN_I16_GO_SEXW_S_GO, A5F_INSN_EXTB_L_R_R__RC, A5F_INSN_EXTB_L_U6_, A5F_INSN_I16_GO_EXTB_S_GO
+ , A5F_INSN_EXTW_L_R_R__RC, A5F_INSN_EXTW_L_U6_, A5F_INSN_I16_GO_EXTW_S_GO, A5F_INSN_ABS_L_R_R__RC
+ , A5F_INSN_ABS_L_U6_, A5F_INSN_I16_GO_ABS_S_GO, A5F_INSN_NOT_L_R_R__RC, A5F_INSN_NOT_L_U6_
+ , A5F_INSN_I16_GO_NOT_S_GO, A5F_INSN_RLC_L_R_R__RC, A5F_INSN_RLC_L_U6_, A5F_INSN_I16_GO_NEG_S_GO
+ , A5F_INSN_SWI, A5F_INSN_TRAP_S, A5F_INSN_BRK, A5F_INSN_BRK_S
+ , A5F_INSN_ASL_L_S12__RA_, A5F_INSN_ASL_CCU6__RA_, A5F_INSN_ASL_L_U6__RA_, A5F_INSN_ASL_L_R_R__RA__RC
+ , A5F_INSN_ASL_CC__RA__RC, A5F_INSN_ASL_S_CBU3, A5F_INSN_ASL_S_SSB, A5F_INSN_I16_GO_ASLM_S_GO
+ , A5F_INSN_LSR_L_S12__RA_, A5F_INSN_LSR_CCU6__RA_, A5F_INSN_LSR_L_U6__RA_, A5F_INSN_LSR_L_R_R__RA__RC
+ , A5F_INSN_LSR_CC__RA__RC, A5F_INSN_LSR_S_SSB, A5F_INSN_I16_GO_LSRM_S_GO, A5F_INSN_ASR_L_S12__RA_
+ , A5F_INSN_ASR_CCU6__RA_, A5F_INSN_ASR_L_U6__RA_, A5F_INSN_ASR_L_R_R__RA__RC, A5F_INSN_ASR_CC__RA__RC
+ , A5F_INSN_ASR_S_CBU3, A5F_INSN_ASR_S_SSB, A5F_INSN_I16_GO_ASRM_S_GO, A5F_INSN_ROR_L_S12__RA_
+ , A5F_INSN_ROR_CCU6__RA_, A5F_INSN_ROR_L_U6__RA_, A5F_INSN_ROR_L_R_R__RA__RC, A5F_INSN_ROR_CC__RA__RC
+ , A5F_INSN_MUL64_L_S12_, A5F_INSN_MUL64_CCU6_, A5F_INSN_MUL64_L_U6_, A5F_INSN_MUL64_L_R_R__RC
+ , A5F_INSN_MUL64_CC__RC, A5F_INSN_MUL64_S_GO, A5F_INSN_MULU64_L_S12_, A5F_INSN_MULU64_CCU6_
+ , A5F_INSN_MULU64_L_U6_, A5F_INSN_MULU64_L_R_R__RC, A5F_INSN_MULU64_CC__RC, A5F_INSN_ADDS_L_S12__RA_
+ , A5F_INSN_ADDS_CCU6__RA_, A5F_INSN_ADDS_L_U6__RA_, A5F_INSN_ADDS_L_R_R__RA__RC, A5F_INSN_ADDS_CC__RA__RC
+ , A5F_INSN_SUBS_L_S12__RA_, A5F_INSN_SUBS_CCU6__RA_, A5F_INSN_SUBS_L_U6__RA_, A5F_INSN_SUBS_L_R_R__RA__RC
+ , A5F_INSN_SUBS_CC__RA__RC, A5F_INSN_DIVAW_L_S12__RA_, A5F_INSN_DIVAW_CCU6__RA_, A5F_INSN_DIVAW_L_U6__RA_
+ , A5F_INSN_DIVAW_L_R_R__RA__RC, A5F_INSN_DIVAW_CC__RA__RC, A5F_INSN_ASLS_L_S12__RA_, A5F_INSN_ASLS_CCU6__RA_
+ , A5F_INSN_ASLS_L_U6__RA_, A5F_INSN_ASLS_L_R_R__RA__RC, A5F_INSN_ASLS_CC__RA__RC, A5F_INSN_ASRS_L_S12__RA_
+ , A5F_INSN_ASRS_CCU6__RA_, A5F_INSN_ASRS_L_U6__RA_, A5F_INSN_ASRS_L_R_R__RA__RC, A5F_INSN_ASRS_CC__RA__RC
+ , A5F_INSN_ADDSDW_L_S12__RA_, A5F_INSN_ADDSDW_CCU6__RA_, A5F_INSN_ADDSDW_L_U6__RA_, A5F_INSN_ADDSDW_L_R_R__RA__RC
+ , A5F_INSN_ADDSDW_CC__RA__RC, A5F_INSN_SUBSDW_L_S12__RA_, A5F_INSN_SUBSDW_CCU6__RA_, A5F_INSN_SUBSDW_L_U6__RA_
+ , A5F_INSN_SUBSDW_L_R_R__RA__RC, A5F_INSN_SUBSDW_CC__RA__RC, A5F_INSN_SWAP_L_R_R__RC, A5F_INSN_SWAP_L_U6_
+ , A5F_INSN_NORM_L_R_R__RC, A5F_INSN_NORM_L_U6_, A5F_INSN_RND16_L_R_R__RC, A5F_INSN_RND16_L_U6_
+ , A5F_INSN_ABSSW_L_R_R__RC, A5F_INSN_ABSSW_L_U6_, A5F_INSN_ABSS_L_R_R__RC, A5F_INSN_ABSS_L_U6_
+ , A5F_INSN_NEGSW_L_R_R__RC, A5F_INSN_NEGSW_L_U6_, A5F_INSN_NEGS_L_R_R__RC, A5F_INSN_NEGS_L_U6_
+ , A5F_INSN_NORMW_L_R_R__RC, A5F_INSN_NORMW_L_U6_, A5F_INSN_NOP_S, A5F_INSN_UNIMP_S
+ , A5F_INSN_POP_S_B, A5F_INSN_POP_S_BLINK, A5F_INSN_PUSH_S_B, A5F_INSN_PUSH_S_BLINK
+ , A5F_INSN_MULLW_L_S12__RA_, A5F_INSN_MULLW_CCU6__RA_, A5F_INSN_MULLW_L_U6__RA_, A5F_INSN_MULLW_L_R_R__RA__RC
+ , A5F_INSN_MULLW_CC__RA__RC, A5F_INSN_MACLW_L_S12__RA_, A5F_INSN_MACLW_CCU6__RA_, A5F_INSN_MACLW_L_U6__RA_
+ , A5F_INSN_MACLW_L_R_R__RA__RC, A5F_INSN_MACLW_CC__RA__RC, A5F_INSN_MACHLW_L_S12__RA_, A5F_INSN_MACHLW_CCU6__RA_
+ , A5F_INSN_MACHLW_L_U6__RA_, A5F_INSN_MACHLW_L_R_R__RA__RC, A5F_INSN_MACHLW_CC__RA__RC, A5F_INSN_MULULW_L_S12__RA_
+ , A5F_INSN_MULULW_CCU6__RA_, A5F_INSN_MULULW_L_U6__RA_, A5F_INSN_MULULW_L_R_R__RA__RC, A5F_INSN_MULULW_CC__RA__RC
+ , A5F_INSN_MACHULW_L_S12__RA_, A5F_INSN_MACHULW_CCU6__RA_, A5F_INSN_MACHULW_L_U6__RA_, A5F_INSN_MACHULW_L_R_R__RA__RC
+ , A5F_INSN_MACHULW_CC__RA__RC, A5F_INSN_CURRENT_LOOP_END, A5F_INSN_CURRENT_LOOP_END_AFTER_BRANCH, A5F_INSN_ARC600_CURRENT_LOOP_END_AFTER_BRANCH
+ , A5F_INSN__MAX
+} A5F_INSN_TYPE;
+
+/* Enum declaration for semantic formats in cpu family a5f. */
+typedef enum a5f_sfmt_type {
+ A5F_SFMT_EMPTY, A5F_SFMT_B_S, A5F_SFMT_BCC_S, A5F_SFMT_BRCC_S
+ , A5F_SFMT_BCC_L, A5F_SFMT_B_L, A5F_SFMT_BRCC_RC, A5F_SFMT_BRCC_U6
+ , A5F_SFMT_BL_S, A5F_SFMT_BLCC, A5F_SFMT_BL, A5F_SFMT_BL_D
+ , A5F_SFMT_LD_ABS, A5F_SFMT_LD__AW_ABS, A5F_SFMT_LD_ABC, A5F_SFMT_LD__AW_ABC
+ , A5F_SFMT_LD_S_ABC, A5F_SFMT_LD_S_ABU, A5F_SFMT_LD_S_ABSP, A5F_SFMT_LD_S_GPREL
+ , A5F_SFMT_LD_S_PCREL, A5F_SFMT_LDB_ABS, A5F_SFMT_LDB__AW_ABS, A5F_SFMT_LDB_AS_ABS
+ , A5F_SFMT_LDB_ABC, A5F_SFMT_LDB__AW_ABC, A5F_SFMT_LDB_AS_ABC, A5F_SFMT_LDB_S_ABC
+ , A5F_SFMT_LDB_S_ABU, A5F_SFMT_LDB_S_ABSP, A5F_SFMT_LDB_S_GPREL, A5F_SFMT_LDW_ABS
+ , A5F_SFMT_LDW__AW_ABS, A5F_SFMT_LDW_ABC, A5F_SFMT_LDW__AW_ABC, A5F_SFMT_LDW_S_ABC
+ , A5F_SFMT_LDW_S_ABU, A5F_SFMT_LDW_S_GPREL, A5F_SFMT_ST_ABS, A5F_SFMT_ST__AW_ABS
+ , A5F_SFMT_ST_S_ABU, A5F_SFMT_ST_S_ABSP, A5F_SFMT_STB_ABS, A5F_SFMT_STB__AW_ABS
+ , A5F_SFMT_STB_AS_ABS, A5F_SFMT_STB_S_ABU, A5F_SFMT_STB_S_ABSP, A5F_SFMT_STW_ABS
+ , A5F_SFMT_STW__AW_ABS, A5F_SFMT_STW_S_ABU, A5F_SFMT_ADD_L_S12__RA_, A5F_SFMT_ADD_CCU6__RA_
+ , A5F_SFMT_ADD_L_U6__RA_, A5F_SFMT_ADD_L_R_R__RA__RC, A5F_SFMT_ADD_CC__RA__RC, A5F_SFMT_ADD_S_ABC
+ , A5F_SFMT_ADD_S_CBU3, A5F_SFMT_ADD_S_MCAH, A5F_SFMT_ADD_S_ABSP, A5F_SFMT_ADD_S_ASSPSP
+ , A5F_SFMT_ADD_S_GP, A5F_SFMT_ADD_S_R_U7, A5F_SFMT_ADC_L_S12__RA_, A5F_SFMT_ADC_CCU6__RA_
+ , A5F_SFMT_ADC_L_U6__RA_, A5F_SFMT_ADC_L_R_R__RA__RC, A5F_SFMT_ADC_CC__RA__RC, A5F_SFMT_I16_GO_SUB_S_GO
+ , A5F_SFMT_SUB_S_GO_SUB_NE, A5F_SFMT_SUB_S_SSB, A5F_SFMT_AND_L_S12__RA_, A5F_SFMT_AND_CCU6__RA_
+ , A5F_SFMT_AND_L_U6__RA_, A5F_SFMT_AND_L_R_R__RA__RC, A5F_SFMT_AND_CC__RA__RC, A5F_SFMT_MOV_L_S12_
+ , A5F_SFMT_MOV_CCU6_, A5F_SFMT_MOV_L_U6_, A5F_SFMT_MOV_L_R_R__RC, A5F_SFMT_MOV_CC__RC
+ , A5F_SFMT_MOV_S_MCAH, A5F_SFMT_MOV_S_MCAHB, A5F_SFMT_MOV_S_R_U7, A5F_SFMT_TST_L_S12_
+ , A5F_SFMT_TST_CCU6_, A5F_SFMT_TST_L_U6_, A5F_SFMT_TST_L_R_R__RC, A5F_SFMT_TST_CC__RC
+ , A5F_SFMT_TST_S_GO, A5F_SFMT_CMP_L_S12_, A5F_SFMT_CMP_CCU6_, A5F_SFMT_CMP_L_U6_
+ , A5F_SFMT_CMP_L_R_R__RC, A5F_SFMT_CMP_CC__RC, A5F_SFMT_CMP_S_MCAH, A5F_SFMT_CMP_S_R_U7
+ , A5F_SFMT_BTST_S_SSB, A5F_SFMT_MPY_L_S12__RA_, A5F_SFMT_MPY_CCU6__RA_, A5F_SFMT_MPY_L_U6__RA_
+ , A5F_SFMT_MPY_L_R_R__RA__RC, A5F_SFMT_MPY_CC__RA__RC, A5F_SFMT_J_L_R_R___RC_NOILINK_, A5F_SFMT_J_CC___RC_NOILINK_
+ , A5F_SFMT_J_L_R_R___RC_ILINK_, A5F_SFMT_J_CC___RC_ILINK_, A5F_SFMT_J_L_S12_, A5F_SFMT_J_CCU6_
+ , A5F_SFMT_J_L_U6_, A5F_SFMT_J_S, A5F_SFMT_J_S__S, A5F_SFMT_J_SEQ__S
+ , A5F_SFMT_J_L_S12_D_, A5F_SFMT_J_CCU6_D_, A5F_SFMT_J_L_U6_D_, A5F_SFMT_J_L_R_R_D___RC_
+ , A5F_SFMT_J_CC_D___RC_, A5F_SFMT_JL_L_S12_, A5F_SFMT_JL_CCU6_, A5F_SFMT_JL_L_U6_
+ , A5F_SFMT_JL_S, A5F_SFMT_JL_L_R_R___RC_NOILINK_, A5F_SFMT_JL_CC___RC_NOILINK_, A5F_SFMT_JL_L_R_R_D___RC_
+ , A5F_SFMT_JL_CC_D___RC_, A5F_SFMT_JL_S_D, A5F_SFMT_LP_L_S12_, A5F_SFMT_LPCC_CCU6
+ , A5F_SFMT_FLAG_L_S12_, A5F_SFMT_FLAG_CCU6_, A5F_SFMT_FLAG_L_U6_, A5F_SFMT_FLAG_L_R_R__RC
+ , A5F_SFMT_FLAG_CC__RC, A5F_SFMT_LR_L_R_R___RC_, A5F_SFMT_LR_L_S12_, A5F_SFMT_LR_L_U6_
+ , A5F_SFMT_SR_L_R_R___RC_, A5F_SFMT_SR_L_S12_, A5F_SFMT_SR_L_U6_, A5F_SFMT_ASL_L_R_R__RC
+ , A5F_SFMT_ASL_L_U6_, A5F_SFMT_ASR_L_R_R__RC, A5F_SFMT_ASR_L_U6_, A5F_SFMT_RRC_L_R_R__RC
+ , A5F_SFMT_RRC_L_U6_, A5F_SFMT_SEXB_L_R_R__RC, A5F_SFMT_SEXB_L_U6_, A5F_SFMT_SEXW_L_R_R__RC
+ , A5F_SFMT_SEXW_L_U6_, A5F_SFMT_ABS_L_R_R__RC, A5F_SFMT_ABS_L_U6_, A5F_SFMT_NOT_L_R_R__RC
+ , A5F_SFMT_NOT_L_U6_, A5F_SFMT_SWI, A5F_SFMT_TRAP_S, A5F_SFMT_BRK
+ , A5F_SFMT_ASL_L_S12__RA_, A5F_SFMT_ASL_CCU6__RA_, A5F_SFMT_ASL_L_U6__RA_, A5F_SFMT_ASL_L_R_R__RA__RC
+ , A5F_SFMT_ASL_CC__RA__RC, A5F_SFMT_MUL64_L_S12_, A5F_SFMT_MUL64_CCU6_, A5F_SFMT_MUL64_L_U6_
+ , A5F_SFMT_MUL64_L_R_R__RC, A5F_SFMT_MUL64_CC__RC, A5F_SFMT_MUL64_S_GO, A5F_SFMT_ADDS_L_S12__RA_
+ , A5F_SFMT_ADDS_CCU6__RA_, A5F_SFMT_ADDS_L_U6__RA_, A5F_SFMT_ADDS_L_R_R__RA__RC, A5F_SFMT_ADDS_CC__RA__RC
+ , A5F_SFMT_DIVAW_L_S12__RA_, A5F_SFMT_DIVAW_CCU6__RA_, A5F_SFMT_DIVAW_L_U6__RA_, A5F_SFMT_DIVAW_L_R_R__RA__RC
+ , A5F_SFMT_DIVAW_CC__RA__RC, A5F_SFMT_ASLS_L_S12__RA_, A5F_SFMT_ASLS_CCU6__RA_, A5F_SFMT_ASLS_L_U6__RA_
+ , A5F_SFMT_ASLS_L_R_R__RA__RC, A5F_SFMT_ASLS_CC__RA__RC, A5F_SFMT_SWAP_L_R_R__RC, A5F_SFMT_SWAP_L_U6_
+ , A5F_SFMT_NORM_L_U6_, A5F_SFMT_RND16_L_R_R__RC, A5F_SFMT_RND16_L_U6_, A5F_SFMT_ABSSW_L_R_R__RC
+ , A5F_SFMT_ABSSW_L_U6_, A5F_SFMT_ABSS_L_U6_, A5F_SFMT_NOP_S, A5F_SFMT_POP_S_B
+ , A5F_SFMT_POP_S_BLINK, A5F_SFMT_PUSH_S_B, A5F_SFMT_PUSH_S_BLINK, A5F_SFMT_MULLW_L_S12__RA_
+ , A5F_SFMT_MULLW_CCU6__RA_, A5F_SFMT_MULLW_L_U6__RA_, A5F_SFMT_MULLW_L_R_R__RA__RC, A5F_SFMT_MULLW_CC__RA__RC
+ , A5F_SFMT_MACLW_L_S12__RA_, A5F_SFMT_MACLW_CCU6__RA_, A5F_SFMT_MACLW_L_U6__RA_, A5F_SFMT_MACLW_L_R_R__RA__RC
+ , A5F_SFMT_MACLW_CC__RA__RC, A5F_SFMT_MACHULW_L_S12__RA_, A5F_SFMT_MACHULW_CCU6__RA_, A5F_SFMT_MACHULW_L_U6__RA_
+ , A5F_SFMT_MACHULW_L_R_R__RA__RC, A5F_SFMT_MACHULW_CC__RA__RC, A5F_SFMT_CURRENT_LOOP_END, A5F_SFMT_CURRENT_LOOP_END_AFTER_BRANCH
+} A5F_SFMT_TYPE;
+
+/* Function unit handlers (user written). */
+
+extern int a5f_model_A5_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*b*/, INT /*c*/, INT /*a*/);
+
+/* Profiling before/after handlers (user written) */
+
+extern void a5f_model_insn_before (SIM_CPU *, int /*first_p*/);
+extern void a5f_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
+
+#endif /* A5F_DECODE_H */
diff --git a/sim/arc/decode6.c b/sim/arc/decode6.c
new file mode 100644
index 0000000..5f5815b
--- /dev/null
+++ b/sim/arc/decode6.c
@@ -0,0 +1,21199 @@
+/* Simulator instruction decoder for arc600f.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2007 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#define WANT_CPU arc600f
+#define WANT_CPU_ARC600F
+
+#include "sim-main.h"
+#include "sim-assert.h"
+
+/* The instruction descriptor array.
+ This is computed at runtime. Space for it is not malloc'd to save a
+ teensy bit of cpu in the decoder. Moving it to malloc space is trivial
+ but won't be done until necessary (we don't currently support the runtime
+ addition of instructions nor an SMP machine with different cpus). */
+static IDESC arc600f_insn_data[ARC600F_INSN__MAX];
+
+/* Commas between elements are contained in the macros.
+ Some of these are conditionally compiled out. */
+
+static const struct insn_sem arc600f_insn_sem[] =
+{
+ { VIRTUAL_INSN_X_INVALID, ARC600F_INSN_X_INVALID, ARC600F_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_AFTER, ARC600F_INSN_X_AFTER, ARC600F_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_BEFORE, ARC600F_INSN_X_BEFORE, ARC600F_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_CTI_CHAIN, ARC600F_INSN_X_CTI_CHAIN, ARC600F_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_CHAIN, ARC600F_INSN_X_CHAIN, ARC600F_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_BEGIN, ARC600F_INSN_X_BEGIN, ARC600F_SFMT_EMPTY },
+ { ARC_INSN_B_S, ARC600F_INSN_B_S, ARC600F_SFMT_B_S },
+ { ARC_INSN_BCC_S, ARC600F_INSN_BCC_S, ARC600F_SFMT_BCC_S },
+ { ARC_INSN_BRCC_S, ARC600F_INSN_BRCC_S, ARC600F_SFMT_BRCC_S },
+ { ARC_INSN_BCC_L, ARC600F_INSN_BCC_L, ARC600F_SFMT_BCC_L },
+ { ARC_INSN_BCC_L_D, ARC600F_INSN_BCC_L_D, ARC600F_SFMT_BCC_L },
+ { ARC_INSN_B_L, ARC600F_INSN_B_L, ARC600F_SFMT_B_L },
+ { ARC_INSN_B_L_D, ARC600F_INSN_B_L_D, ARC600F_SFMT_B_L },
+ { ARC_INSN_BRCC_RC, ARC600F_INSN_BRCC_RC, ARC600F_SFMT_BRCC_RC },
+ { ARC_INSN_BRCC_RC_D, ARC600F_INSN_BRCC_RC_D, ARC600F_SFMT_BRCC_RC },
+ { ARC_INSN_BRCC_U6, ARC600F_INSN_BRCC_U6, ARC600F_SFMT_BRCC_U6 },
+ { ARC_INSN_BRCC_U6_D, ARC600F_INSN_BRCC_U6_D, ARC600F_SFMT_BRCC_U6 },
+ { ARC_INSN_BL_S, ARC600F_INSN_BL_S, ARC600F_SFMT_BL_S },
+ { ARC_INSN_BLCC, ARC600F_INSN_BLCC, ARC600F_SFMT_BLCC },
+ { ARC_INSN_BLCC_D, ARC600F_INSN_BLCC_D, ARC600F_SFMT_BLCC },
+ { ARC_INSN_BL, ARC600F_INSN_BL, ARC600F_SFMT_BL },
+ { ARC_INSN_BL_D, ARC600F_INSN_BL_D, ARC600F_SFMT_BL_D },
+ { ARC_INSN_LD_ABS, ARC600F_INSN_LD_ABS, ARC600F_SFMT_LD_ABS },
+ { ARC_INSN_LD__AW_ABS, ARC600F_INSN_LD__AW_ABS, ARC600F_SFMT_LD__AW_ABS },
+ { ARC_INSN_LD_AB_ABS, ARC600F_INSN_LD_AB_ABS, ARC600F_SFMT_LD__AW_ABS },
+ { ARC_INSN_LD_AS_ABS, ARC600F_INSN_LD_AS_ABS, ARC600F_SFMT_LD_ABS },
+ { ARC_INSN_LD_ABC, ARC600F_INSN_LD_ABC, ARC600F_SFMT_LD_ABC },
+ { ARC_INSN_LD__AW_ABC, ARC600F_INSN_LD__AW_ABC, ARC600F_SFMT_LD__AW_ABC },
+ { ARC_INSN_LD_AB_ABC, ARC600F_INSN_LD_AB_ABC, ARC600F_SFMT_LD__AW_ABC },
+ { ARC_INSN_LD_AS_ABC, ARC600F_INSN_LD_AS_ABC, ARC600F_SFMT_LD_ABC },
+ { ARC_INSN_LD_S_ABC, ARC600F_INSN_LD_S_ABC, ARC600F_SFMT_LD_S_ABC },
+ { ARC_INSN_LD_S_ABU, ARC600F_INSN_LD_S_ABU, ARC600F_SFMT_LD_S_ABU },
+ { ARC_INSN_LD_S_ABSP, ARC600F_INSN_LD_S_ABSP, ARC600F_SFMT_LD_S_ABSP },
+ { ARC_INSN_LD_S_GPREL, ARC600F_INSN_LD_S_GPREL, ARC600F_SFMT_LD_S_GPREL },
+ { ARC_INSN_LD_S_PCREL, ARC600F_INSN_LD_S_PCREL, ARC600F_SFMT_LD_S_PCREL },
+ { ARC_INSN_LDB_ABS, ARC600F_INSN_LDB_ABS, ARC600F_SFMT_LDB_ABS },
+ { ARC_INSN_LDB__AW_ABS, ARC600F_INSN_LDB__AW_ABS, ARC600F_SFMT_LDB__AW_ABS },
+ { ARC_INSN_LDB_AB_ABS, ARC600F_INSN_LDB_AB_ABS, ARC600F_SFMT_LDB__AW_ABS },
+ { ARC_INSN_LDB_AS_ABS, ARC600F_INSN_LDB_AS_ABS, ARC600F_SFMT_LDB_AS_ABS },
+ { ARC_INSN_LDB_ABC, ARC600F_INSN_LDB_ABC, ARC600F_SFMT_LDB_ABC },
+ { ARC_INSN_LDB__AW_ABC, ARC600F_INSN_LDB__AW_ABC, ARC600F_SFMT_LDB__AW_ABC },
+ { ARC_INSN_LDB_AB_ABC, ARC600F_INSN_LDB_AB_ABC, ARC600F_SFMT_LDB__AW_ABC },
+ { ARC_INSN_LDB_AS_ABC, ARC600F_INSN_LDB_AS_ABC, ARC600F_SFMT_LDB_AS_ABC },
+ { ARC_INSN_LDB_S_ABC, ARC600F_INSN_LDB_S_ABC, ARC600F_SFMT_LDB_S_ABC },
+ { ARC_INSN_LDB_S_ABU, ARC600F_INSN_LDB_S_ABU, ARC600F_SFMT_LDB_S_ABU },
+ { ARC_INSN_LDB_S_ABSP, ARC600F_INSN_LDB_S_ABSP, ARC600F_SFMT_LDB_S_ABSP },
+ { ARC_INSN_LDB_S_GPREL, ARC600F_INSN_LDB_S_GPREL, ARC600F_SFMT_LDB_S_GPREL },
+ { ARC_INSN_LDB_X_ABS, ARC600F_INSN_LDB_X_ABS, ARC600F_SFMT_LDB_ABS },
+ { ARC_INSN_LDB__AW_X_ABS, ARC600F_INSN_LDB__AW_X_ABS, ARC600F_SFMT_LDB__AW_ABS },
+ { ARC_INSN_LDB_AB_X_ABS, ARC600F_INSN_LDB_AB_X_ABS, ARC600F_SFMT_LDB__AW_ABS },
+ { ARC_INSN_LDB_AS_X_ABS, ARC600F_INSN_LDB_AS_X_ABS, ARC600F_SFMT_LDB_AS_ABS },
+ { ARC_INSN_LDB_X_ABC, ARC600F_INSN_LDB_X_ABC, ARC600F_SFMT_LDB_ABC },
+ { ARC_INSN_LDB__AW_X_ABC, ARC600F_INSN_LDB__AW_X_ABC, ARC600F_SFMT_LDB__AW_ABC },
+ { ARC_INSN_LDB_AB_X_ABC, ARC600F_INSN_LDB_AB_X_ABC, ARC600F_SFMT_LDB__AW_ABC },
+ { ARC_INSN_LDB_AS_X_ABC, ARC600F_INSN_LDB_AS_X_ABC, ARC600F_SFMT_LDB_AS_ABC },
+ { ARC_INSN_LDW_ABS, ARC600F_INSN_LDW_ABS, ARC600F_SFMT_LDW_ABS },
+ { ARC_INSN_LDW__AW_ABS, ARC600F_INSN_LDW__AW_ABS, ARC600F_SFMT_LDW__AW_ABS },
+ { ARC_INSN_LDW_AB_ABS, ARC600F_INSN_LDW_AB_ABS, ARC600F_SFMT_LDW__AW_ABS },
+ { ARC_INSN_LDW_AS_ABS, ARC600F_INSN_LDW_AS_ABS, ARC600F_SFMT_LDW_ABS },
+ { ARC_INSN_LDW_ABC, ARC600F_INSN_LDW_ABC, ARC600F_SFMT_LDW_ABC },
+ { ARC_INSN_LDW__AW_ABC, ARC600F_INSN_LDW__AW_ABC, ARC600F_SFMT_LDW__AW_ABC },
+ { ARC_INSN_LDW_AB_ABC, ARC600F_INSN_LDW_AB_ABC, ARC600F_SFMT_LDW__AW_ABC },
+ { ARC_INSN_LDW_AS_ABC, ARC600F_INSN_LDW_AS_ABC, ARC600F_SFMT_LDW_ABC },
+ { ARC_INSN_LDW_S_ABC, ARC600F_INSN_LDW_S_ABC, ARC600F_SFMT_LDW_S_ABC },
+ { ARC_INSN_LDW_S_ABU, ARC600F_INSN_LDW_S_ABU, ARC600F_SFMT_LDW_S_ABU },
+ { ARC_INSN_LDW_S_GPREL, ARC600F_INSN_LDW_S_GPREL, ARC600F_SFMT_LDW_S_GPREL },
+ { ARC_INSN_LDW_X_ABS, ARC600F_INSN_LDW_X_ABS, ARC600F_SFMT_LDW_ABS },
+ { ARC_INSN_LDW__AW_X_ABS, ARC600F_INSN_LDW__AW_X_ABS, ARC600F_SFMT_LDW__AW_ABS },
+ { ARC_INSN_LDW_AB_X_ABS, ARC600F_INSN_LDW_AB_X_ABS, ARC600F_SFMT_LDW__AW_ABS },
+ { ARC_INSN_LDW_AS_X_ABS, ARC600F_INSN_LDW_AS_X_ABS, ARC600F_SFMT_LDW_ABS },
+ { ARC_INSN_LDW_X_ABC, ARC600F_INSN_LDW_X_ABC, ARC600F_SFMT_LDW_ABC },
+ { ARC_INSN_LDW__AW_X_ABC, ARC600F_INSN_LDW__AW_X_ABC, ARC600F_SFMT_LDW__AW_ABC },
+ { ARC_INSN_LDW_AB_X_ABC, ARC600F_INSN_LDW_AB_X_ABC, ARC600F_SFMT_LDW__AW_ABC },
+ { ARC_INSN_LDW_AS_X_ABC, ARC600F_INSN_LDW_AS_X_ABC, ARC600F_SFMT_LDW_ABC },
+ { ARC_INSN_LDW_S_X_ABU, ARC600F_INSN_LDW_S_X_ABU, ARC600F_SFMT_LDW_S_ABU },
+ { ARC_INSN_ST_ABS, ARC600F_INSN_ST_ABS, ARC600F_SFMT_ST_ABS },
+ { ARC_INSN_ST__AW_ABS, ARC600F_INSN_ST__AW_ABS, ARC600F_SFMT_ST__AW_ABS },
+ { ARC_INSN_ST_AB_ABS, ARC600F_INSN_ST_AB_ABS, ARC600F_SFMT_ST__AW_ABS },
+ { ARC_INSN_ST_AS_ABS, ARC600F_INSN_ST_AS_ABS, ARC600F_SFMT_ST_ABS },
+ { ARC_INSN_ST_S_ABU, ARC600F_INSN_ST_S_ABU, ARC600F_SFMT_ST_S_ABU },
+ { ARC_INSN_ST_S_ABSP, ARC600F_INSN_ST_S_ABSP, ARC600F_SFMT_ST_S_ABSP },
+ { ARC_INSN_STB_ABS, ARC600F_INSN_STB_ABS, ARC600F_SFMT_STB_ABS },
+ { ARC_INSN_STB__AW_ABS, ARC600F_INSN_STB__AW_ABS, ARC600F_SFMT_STB__AW_ABS },
+ { ARC_INSN_STB_AB_ABS, ARC600F_INSN_STB_AB_ABS, ARC600F_SFMT_STB__AW_ABS },
+ { ARC_INSN_STB_AS_ABS, ARC600F_INSN_STB_AS_ABS, ARC600F_SFMT_STB_AS_ABS },
+ { ARC_INSN_STB_S_ABU, ARC600F_INSN_STB_S_ABU, ARC600F_SFMT_STB_S_ABU },
+ { ARC_INSN_STB_S_ABSP, ARC600F_INSN_STB_S_ABSP, ARC600F_SFMT_STB_S_ABSP },
+ { ARC_INSN_STW_ABS, ARC600F_INSN_STW_ABS, ARC600F_SFMT_STW_ABS },
+ { ARC_INSN_STW__AW_ABS, ARC600F_INSN_STW__AW_ABS, ARC600F_SFMT_STW__AW_ABS },
+ { ARC_INSN_STW_AB_ABS, ARC600F_INSN_STW_AB_ABS, ARC600F_SFMT_STW__AW_ABS },
+ { ARC_INSN_STW_AS_ABS, ARC600F_INSN_STW_AS_ABS, ARC600F_SFMT_STW_ABS },
+ { ARC_INSN_STW_S_ABU, ARC600F_INSN_STW_S_ABU, ARC600F_SFMT_STW_S_ABU },
+ { ARC_INSN_ADD_L_S12__RA_, ARC600F_INSN_ADD_L_S12__RA_, ARC600F_SFMT_ADD_L_S12__RA_ },
+ { ARC_INSN_ADD_CCU6__RA_, ARC600F_INSN_ADD_CCU6__RA_, ARC600F_SFMT_ADD_CCU6__RA_ },
+ { ARC_INSN_ADD_L_U6__RA_, ARC600F_INSN_ADD_L_U6__RA_, ARC600F_SFMT_ADD_L_U6__RA_ },
+ { ARC_INSN_ADD_L_R_R__RA__RC, ARC600F_INSN_ADD_L_R_R__RA__RC, ARC600F_SFMT_ADD_L_R_R__RA__RC },
+ { ARC_INSN_ADD_CC__RA__RC, ARC600F_INSN_ADD_CC__RA__RC, ARC600F_SFMT_ADD_CC__RA__RC },
+ { ARC_INSN_ADD_S_ABC, ARC600F_INSN_ADD_S_ABC, ARC600F_SFMT_ADD_S_ABC },
+ { ARC_INSN_ADD_S_CBU3, ARC600F_INSN_ADD_S_CBU3, ARC600F_SFMT_ADD_S_CBU3 },
+ { ARC_INSN_ADD_S_MCAH, ARC600F_INSN_ADD_S_MCAH, ARC600F_SFMT_ADD_S_MCAH },
+ { ARC_INSN_ADD_S_ABSP, ARC600F_INSN_ADD_S_ABSP, ARC600F_SFMT_ADD_S_ABSP },
+ { ARC_INSN_ADD_S_ASSPSP, ARC600F_INSN_ADD_S_ASSPSP, ARC600F_SFMT_ADD_S_ASSPSP },
+ { ARC_INSN_ADD_S_GP, ARC600F_INSN_ADD_S_GP, ARC600F_SFMT_ADD_S_GP },
+ { ARC_INSN_ADD_S_R_U7, ARC600F_INSN_ADD_S_R_U7, ARC600F_SFMT_ADD_S_R_U7 },
+ { ARC_INSN_ADC_L_S12__RA_, ARC600F_INSN_ADC_L_S12__RA_, ARC600F_SFMT_ADC_L_S12__RA_ },
+ { ARC_INSN_ADC_CCU6__RA_, ARC600F_INSN_ADC_CCU6__RA_, ARC600F_SFMT_ADC_CCU6__RA_ },
+ { ARC_INSN_ADC_L_U6__RA_, ARC600F_INSN_ADC_L_U6__RA_, ARC600F_SFMT_ADC_L_U6__RA_ },
+ { ARC_INSN_ADC_L_R_R__RA__RC, ARC600F_INSN_ADC_L_R_R__RA__RC, ARC600F_SFMT_ADC_L_R_R__RA__RC },
+ { ARC_INSN_ADC_CC__RA__RC, ARC600F_INSN_ADC_CC__RA__RC, ARC600F_SFMT_ADC_CC__RA__RC },
+ { ARC_INSN_SUB_L_S12__RA_, ARC600F_INSN_SUB_L_S12__RA_, ARC600F_SFMT_ADD_L_S12__RA_ },
+ { ARC_INSN_SUB_CCU6__RA_, ARC600F_INSN_SUB_CCU6__RA_, ARC600F_SFMT_ADD_CCU6__RA_ },
+ { ARC_INSN_SUB_L_U6__RA_, ARC600F_INSN_SUB_L_U6__RA_, ARC600F_SFMT_ADD_L_U6__RA_ },
+ { ARC_INSN_SUB_L_R_R__RA__RC, ARC600F_INSN_SUB_L_R_R__RA__RC, ARC600F_SFMT_ADD_L_R_R__RA__RC },
+ { ARC_INSN_SUB_CC__RA__RC, ARC600F_INSN_SUB_CC__RA__RC, ARC600F_SFMT_ADD_CC__RA__RC },
+ { ARC_INSN_SUB_S_CBU3, ARC600F_INSN_SUB_S_CBU3, ARC600F_SFMT_ADD_S_CBU3 },
+ { ARC_INSN_I16_GO_SUB_S_GO, ARC600F_INSN_I16_GO_SUB_S_GO, ARC600F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_SUB_S_GO_SUB_NE, ARC600F_INSN_SUB_S_GO_SUB_NE, ARC600F_SFMT_SUB_S_GO_SUB_NE },
+ { ARC_INSN_SUB_S_SSB, ARC600F_INSN_SUB_S_SSB, ARC600F_SFMT_SUB_S_SSB },
+ { ARC_INSN_SUB_S_ASSPSP, ARC600F_INSN_SUB_S_ASSPSP, ARC600F_SFMT_ADD_S_ASSPSP },
+ { ARC_INSN_SBC_L_S12__RA_, ARC600F_INSN_SBC_L_S12__RA_, ARC600F_SFMT_ADC_L_S12__RA_ },
+ { ARC_INSN_SBC_CCU6__RA_, ARC600F_INSN_SBC_CCU6__RA_, ARC600F_SFMT_ADC_CCU6__RA_ },
+ { ARC_INSN_SBC_L_U6__RA_, ARC600F_INSN_SBC_L_U6__RA_, ARC600F_SFMT_ADC_L_U6__RA_ },
+ { ARC_INSN_SBC_L_R_R__RA__RC, ARC600F_INSN_SBC_L_R_R__RA__RC, ARC600F_SFMT_ADC_L_R_R__RA__RC },
+ { ARC_INSN_SBC_CC__RA__RC, ARC600F_INSN_SBC_CC__RA__RC, ARC600F_SFMT_ADC_CC__RA__RC },
+ { ARC_INSN_AND_L_S12__RA_, ARC600F_INSN_AND_L_S12__RA_, ARC600F_SFMT_AND_L_S12__RA_ },
+ { ARC_INSN_AND_CCU6__RA_, ARC600F_INSN_AND_CCU6__RA_, ARC600F_SFMT_AND_CCU6__RA_ },
+ { ARC_INSN_AND_L_U6__RA_, ARC600F_INSN_AND_L_U6__RA_, ARC600F_SFMT_AND_L_U6__RA_ },
+ { ARC_INSN_AND_L_R_R__RA__RC, ARC600F_INSN_AND_L_R_R__RA__RC, ARC600F_SFMT_AND_L_R_R__RA__RC },
+ { ARC_INSN_AND_CC__RA__RC, ARC600F_INSN_AND_CC__RA__RC, ARC600F_SFMT_AND_CC__RA__RC },
+ { ARC_INSN_I16_GO_AND_S_GO, ARC600F_INSN_I16_GO_AND_S_GO, ARC600F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_OR_L_S12__RA_, ARC600F_INSN_OR_L_S12__RA_, ARC600F_SFMT_AND_L_S12__RA_ },
+ { ARC_INSN_OR_CCU6__RA_, ARC600F_INSN_OR_CCU6__RA_, ARC600F_SFMT_AND_CCU6__RA_ },
+ { ARC_INSN_OR_L_U6__RA_, ARC600F_INSN_OR_L_U6__RA_, ARC600F_SFMT_AND_L_U6__RA_ },
+ { ARC_INSN_OR_L_R_R__RA__RC, ARC600F_INSN_OR_L_R_R__RA__RC, ARC600F_SFMT_AND_L_R_R__RA__RC },
+ { ARC_INSN_OR_CC__RA__RC, ARC600F_INSN_OR_CC__RA__RC, ARC600F_SFMT_AND_CC__RA__RC },
+ { ARC_INSN_I16_GO_OR_S_GO, ARC600F_INSN_I16_GO_OR_S_GO, ARC600F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_BIC_L_S12__RA_, ARC600F_INSN_BIC_L_S12__RA_, ARC600F_SFMT_AND_L_S12__RA_ },
+ { ARC_INSN_BIC_CCU6__RA_, ARC600F_INSN_BIC_CCU6__RA_, ARC600F_SFMT_AND_CCU6__RA_ },
+ { ARC_INSN_BIC_L_U6__RA_, ARC600F_INSN_BIC_L_U6__RA_, ARC600F_SFMT_AND_L_U6__RA_ },
+ { ARC_INSN_BIC_L_R_R__RA__RC, ARC600F_INSN_BIC_L_R_R__RA__RC, ARC600F_SFMT_AND_L_R_R__RA__RC },
+ { ARC_INSN_BIC_CC__RA__RC, ARC600F_INSN_BIC_CC__RA__RC, ARC600F_SFMT_AND_CC__RA__RC },
+ { ARC_INSN_I16_GO_BIC_S_GO, ARC600F_INSN_I16_GO_BIC_S_GO, ARC600F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_XOR_L_S12__RA_, ARC600F_INSN_XOR_L_S12__RA_, ARC600F_SFMT_AND_L_S12__RA_ },
+ { ARC_INSN_XOR_CCU6__RA_, ARC600F_INSN_XOR_CCU6__RA_, ARC600F_SFMT_AND_CCU6__RA_ },
+ { ARC_INSN_XOR_L_U6__RA_, ARC600F_INSN_XOR_L_U6__RA_, ARC600F_SFMT_AND_L_U6__RA_ },
+ { ARC_INSN_XOR_L_R_R__RA__RC, ARC600F_INSN_XOR_L_R_R__RA__RC, ARC600F_SFMT_AND_L_R_R__RA__RC },
+ { ARC_INSN_XOR_CC__RA__RC, ARC600F_INSN_XOR_CC__RA__RC, ARC600F_SFMT_AND_CC__RA__RC },
+ { ARC_INSN_I16_GO_XOR_S_GO, ARC600F_INSN_I16_GO_XOR_S_GO, ARC600F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_MAX_L_S12__RA_, ARC600F_INSN_MAX_L_S12__RA_, ARC600F_SFMT_ADD_L_S12__RA_ },
+ { ARC_INSN_MAX_CCU6__RA_, ARC600F_INSN_MAX_CCU6__RA_, ARC600F_SFMT_ADD_CCU6__RA_ },
+ { ARC_INSN_MAX_L_U6__RA_, ARC600F_INSN_MAX_L_U6__RA_, ARC600F_SFMT_ADD_L_U6__RA_ },
+ { ARC_INSN_MAX_L_R_R__RA__RC, ARC600F_INSN_MAX_L_R_R__RA__RC, ARC600F_SFMT_ADD_L_R_R__RA__RC },
+ { ARC_INSN_MAX_CC__RA__RC, ARC600F_INSN_MAX_CC__RA__RC, ARC600F_SFMT_ADD_CC__RA__RC },
+ { ARC_INSN_MIN_L_S12__RA_, ARC600F_INSN_MIN_L_S12__RA_, ARC600F_SFMT_ADD_L_S12__RA_ },
+ { ARC_INSN_MIN_CCU6__RA_, ARC600F_INSN_MIN_CCU6__RA_, ARC600F_SFMT_ADD_CCU6__RA_ },
+ { ARC_INSN_MIN_L_U6__RA_, ARC600F_INSN_MIN_L_U6__RA_, ARC600F_SFMT_ADD_L_U6__RA_ },
+ { ARC_INSN_MIN_L_R_R__RA__RC, ARC600F_INSN_MIN_L_R_R__RA__RC, ARC600F_SFMT_ADD_L_R_R__RA__RC },
+ { ARC_INSN_MIN_CC__RA__RC, ARC600F_INSN_MIN_CC__RA__RC, ARC600F_SFMT_ADD_CC__RA__RC },
+ { ARC_INSN_MOV_L_S12_, ARC600F_INSN_MOV_L_S12_, ARC600F_SFMT_MOV_L_S12_ },
+ { ARC_INSN_MOV_CCU6_, ARC600F_INSN_MOV_CCU6_, ARC600F_SFMT_MOV_CCU6_ },
+ { ARC_INSN_MOV_L_U6_, ARC600F_INSN_MOV_L_U6_, ARC600F_SFMT_MOV_L_U6_ },
+ { ARC_INSN_MOV_L_R_R__RC, ARC600F_INSN_MOV_L_R_R__RC, ARC600F_SFMT_MOV_L_R_R__RC },
+ { ARC_INSN_MOV_CC__RC, ARC600F_INSN_MOV_CC__RC, ARC600F_SFMT_MOV_CC__RC },
+ { ARC_INSN_MOV_S_MCAH, ARC600F_INSN_MOV_S_MCAH, ARC600F_SFMT_MOV_S_MCAH },
+ { ARC_INSN_MOV_S_MCAHB, ARC600F_INSN_MOV_S_MCAHB, ARC600F_SFMT_MOV_S_MCAHB },
+ { ARC_INSN_MOV_S_R_U7, ARC600F_INSN_MOV_S_R_U7, ARC600F_SFMT_MOV_S_R_U7 },
+ { ARC_INSN_TST_L_S12_, ARC600F_INSN_TST_L_S12_, ARC600F_SFMT_TST_L_S12_ },
+ { ARC_INSN_TST_CCU6_, ARC600F_INSN_TST_CCU6_, ARC600F_SFMT_TST_CCU6_ },
+ { ARC_INSN_TST_L_U6_, ARC600F_INSN_TST_L_U6_, ARC600F_SFMT_TST_L_U6_ },
+ { ARC_INSN_TST_L_R_R__RC, ARC600F_INSN_TST_L_R_R__RC, ARC600F_SFMT_TST_L_R_R__RC },
+ { ARC_INSN_TST_CC__RC, ARC600F_INSN_TST_CC__RC, ARC600F_SFMT_TST_CC__RC },
+ { ARC_INSN_TST_S_GO, ARC600F_INSN_TST_S_GO, ARC600F_SFMT_TST_S_GO },
+ { ARC_INSN_CMP_L_S12_, ARC600F_INSN_CMP_L_S12_, ARC600F_SFMT_CMP_L_S12_ },
+ { ARC_INSN_CMP_CCU6_, ARC600F_INSN_CMP_CCU6_, ARC600F_SFMT_CMP_CCU6_ },
+ { ARC_INSN_CMP_L_U6_, ARC600F_INSN_CMP_L_U6_, ARC600F_SFMT_CMP_L_U6_ },
+ { ARC_INSN_CMP_L_R_R__RC, ARC600F_INSN_CMP_L_R_R__RC, ARC600F_SFMT_CMP_L_R_R__RC },
+ { ARC_INSN_CMP_CC__RC, ARC600F_INSN_CMP_CC__RC, ARC600F_SFMT_CMP_CC__RC },
+ { ARC_INSN_CMP_S_MCAH, ARC600F_INSN_CMP_S_MCAH, ARC600F_SFMT_CMP_S_MCAH },
+ { ARC_INSN_CMP_S_R_U7, ARC600F_INSN_CMP_S_R_U7, ARC600F_SFMT_CMP_S_R_U7 },
+ { ARC_INSN_RCMP_L_S12_, ARC600F_INSN_RCMP_L_S12_, ARC600F_SFMT_CMP_L_S12_ },
+ { ARC_INSN_RCMP_CCU6_, ARC600F_INSN_RCMP_CCU6_, ARC600F_SFMT_CMP_CCU6_ },
+ { ARC_INSN_RCMP_L_U6_, ARC600F_INSN_RCMP_L_U6_, ARC600F_SFMT_CMP_L_U6_ },
+ { ARC_INSN_RCMP_L_R_R__RC, ARC600F_INSN_RCMP_L_R_R__RC, ARC600F_SFMT_CMP_L_R_R__RC },
+ { ARC_INSN_RCMP_CC__RC, ARC600F_INSN_RCMP_CC__RC, ARC600F_SFMT_CMP_CC__RC },
+ { ARC_INSN_RSUB_L_S12__RA_, ARC600F_INSN_RSUB_L_S12__RA_, ARC600F_SFMT_ADD_L_S12__RA_ },
+ { ARC_INSN_RSUB_CCU6__RA_, ARC600F_INSN_RSUB_CCU6__RA_, ARC600F_SFMT_ADD_CCU6__RA_ },
+ { ARC_INSN_RSUB_L_U6__RA_, ARC600F_INSN_RSUB_L_U6__RA_, ARC600F_SFMT_ADD_L_U6__RA_ },
+ { ARC_INSN_RSUB_L_R_R__RA__RC, ARC600F_INSN_RSUB_L_R_R__RA__RC, ARC600F_SFMT_ADD_L_R_R__RA__RC },
+ { ARC_INSN_RSUB_CC__RA__RC, ARC600F_INSN_RSUB_CC__RA__RC, ARC600F_SFMT_ADD_CC__RA__RC },
+ { ARC_INSN_BSET_L_S12__RA_, ARC600F_INSN_BSET_L_S12__RA_, ARC600F_SFMT_AND_L_S12__RA_ },
+ { ARC_INSN_BSET_CCU6__RA_, ARC600F_INSN_BSET_CCU6__RA_, ARC600F_SFMT_AND_CCU6__RA_ },
+ { ARC_INSN_BSET_L_U6__RA_, ARC600F_INSN_BSET_L_U6__RA_, ARC600F_SFMT_AND_L_U6__RA_ },
+ { ARC_INSN_BSET_L_R_R__RA__RC, ARC600F_INSN_BSET_L_R_R__RA__RC, ARC600F_SFMT_AND_L_R_R__RA__RC },
+ { ARC_INSN_BSET_CC__RA__RC, ARC600F_INSN_BSET_CC__RA__RC, ARC600F_SFMT_AND_CC__RA__RC },
+ { ARC_INSN_BSET_S_SSB, ARC600F_INSN_BSET_S_SSB, ARC600F_SFMT_SUB_S_SSB },
+ { ARC_INSN_BCLR_L_S12__RA_, ARC600F_INSN_BCLR_L_S12__RA_, ARC600F_SFMT_AND_L_S12__RA_ },
+ { ARC_INSN_BCLR_CCU6__RA_, ARC600F_INSN_BCLR_CCU6__RA_, ARC600F_SFMT_AND_CCU6__RA_ },
+ { ARC_INSN_BCLR_L_U6__RA_, ARC600F_INSN_BCLR_L_U6__RA_, ARC600F_SFMT_AND_L_U6__RA_ },
+ { ARC_INSN_BCLR_L_R_R__RA__RC, ARC600F_INSN_BCLR_L_R_R__RA__RC, ARC600F_SFMT_AND_L_R_R__RA__RC },
+ { ARC_INSN_BCLR_CC__RA__RC, ARC600F_INSN_BCLR_CC__RA__RC, ARC600F_SFMT_AND_CC__RA__RC },
+ { ARC_INSN_BCLR_S_SSB, ARC600F_INSN_BCLR_S_SSB, ARC600F_SFMT_SUB_S_SSB },
+ { ARC_INSN_BTST_L_S12_, ARC600F_INSN_BTST_L_S12_, ARC600F_SFMT_TST_L_S12_ },
+ { ARC_INSN_BTST_CCU6_, ARC600F_INSN_BTST_CCU6_, ARC600F_SFMT_TST_CCU6_ },
+ { ARC_INSN_BTST_L_U6_, ARC600F_INSN_BTST_L_U6_, ARC600F_SFMT_TST_L_U6_ },
+ { ARC_INSN_BTST_L_R_R__RC, ARC600F_INSN_BTST_L_R_R__RC, ARC600F_SFMT_TST_L_R_R__RC },
+ { ARC_INSN_BTST_CC__RC, ARC600F_INSN_BTST_CC__RC, ARC600F_SFMT_TST_CC__RC },
+ { ARC_INSN_BTST_S_SSB, ARC600F_INSN_BTST_S_SSB, ARC600F_SFMT_BTST_S_SSB },
+ { ARC_INSN_BXOR_L_S12__RA_, ARC600F_INSN_BXOR_L_S12__RA_, ARC600F_SFMT_AND_L_S12__RA_ },
+ { ARC_INSN_BXOR_CCU6__RA_, ARC600F_INSN_BXOR_CCU6__RA_, ARC600F_SFMT_AND_CCU6__RA_ },
+ { ARC_INSN_BXOR_L_U6__RA_, ARC600F_INSN_BXOR_L_U6__RA_, ARC600F_SFMT_AND_L_U6__RA_ },
+ { ARC_INSN_BXOR_L_R_R__RA__RC, ARC600F_INSN_BXOR_L_R_R__RA__RC, ARC600F_SFMT_AND_L_R_R__RA__RC },
+ { ARC_INSN_BXOR_CC__RA__RC, ARC600F_INSN_BXOR_CC__RA__RC, ARC600F_SFMT_AND_CC__RA__RC },
+ { ARC_INSN_BMSK_L_S12__RA_, ARC600F_INSN_BMSK_L_S12__RA_, ARC600F_SFMT_AND_L_S12__RA_ },
+ { ARC_INSN_BMSK_CCU6__RA_, ARC600F_INSN_BMSK_CCU6__RA_, ARC600F_SFMT_AND_CCU6__RA_ },
+ { ARC_INSN_BMSK_L_U6__RA_, ARC600F_INSN_BMSK_L_U6__RA_, ARC600F_SFMT_AND_L_U6__RA_ },
+ { ARC_INSN_BMSK_L_R_R__RA__RC, ARC600F_INSN_BMSK_L_R_R__RA__RC, ARC600F_SFMT_AND_L_R_R__RA__RC },
+ { ARC_INSN_BMSK_CC__RA__RC, ARC600F_INSN_BMSK_CC__RA__RC, ARC600F_SFMT_AND_CC__RA__RC },
+ { ARC_INSN_BMSK_S_SSB, ARC600F_INSN_BMSK_S_SSB, ARC600F_SFMT_SUB_S_SSB },
+ { ARC_INSN_ADD1_L_S12__RA_, ARC600F_INSN_ADD1_L_S12__RA_, ARC600F_SFMT_ADD_L_S12__RA_ },
+ { ARC_INSN_ADD1_CCU6__RA_, ARC600F_INSN_ADD1_CCU6__RA_, ARC600F_SFMT_ADD_CCU6__RA_ },
+ { ARC_INSN_ADD1_L_U6__RA_, ARC600F_INSN_ADD1_L_U6__RA_, ARC600F_SFMT_ADD_L_U6__RA_ },
+ { ARC_INSN_ADD1_L_R_R__RA__RC, ARC600F_INSN_ADD1_L_R_R__RA__RC, ARC600F_SFMT_ADD_L_R_R__RA__RC },
+ { ARC_INSN_ADD1_CC__RA__RC, ARC600F_INSN_ADD1_CC__RA__RC, ARC600F_SFMT_ADD_CC__RA__RC },
+ { ARC_INSN_I16_GO_ADD1_S_GO, ARC600F_INSN_I16_GO_ADD1_S_GO, ARC600F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_ADD2_L_S12__RA_, ARC600F_INSN_ADD2_L_S12__RA_, ARC600F_SFMT_ADD_L_S12__RA_ },
+ { ARC_INSN_ADD2_CCU6__RA_, ARC600F_INSN_ADD2_CCU6__RA_, ARC600F_SFMT_ADD_CCU6__RA_ },
+ { ARC_INSN_ADD2_L_U6__RA_, ARC600F_INSN_ADD2_L_U6__RA_, ARC600F_SFMT_ADD_L_U6__RA_ },
+ { ARC_INSN_ADD2_L_R_R__RA__RC, ARC600F_INSN_ADD2_L_R_R__RA__RC, ARC600F_SFMT_ADD_L_R_R__RA__RC },
+ { ARC_INSN_ADD2_CC__RA__RC, ARC600F_INSN_ADD2_CC__RA__RC, ARC600F_SFMT_ADD_CC__RA__RC },
+ { ARC_INSN_I16_GO_ADD2_S_GO, ARC600F_INSN_I16_GO_ADD2_S_GO, ARC600F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_ADD3_L_S12__RA_, ARC600F_INSN_ADD3_L_S12__RA_, ARC600F_SFMT_ADD_L_S12__RA_ },
+ { ARC_INSN_ADD3_CCU6__RA_, ARC600F_INSN_ADD3_CCU6__RA_, ARC600F_SFMT_ADD_CCU6__RA_ },
+ { ARC_INSN_ADD3_L_U6__RA_, ARC600F_INSN_ADD3_L_U6__RA_, ARC600F_SFMT_ADD_L_U6__RA_ },
+ { ARC_INSN_ADD3_L_R_R__RA__RC, ARC600F_INSN_ADD3_L_R_R__RA__RC, ARC600F_SFMT_ADD_L_R_R__RA__RC },
+ { ARC_INSN_ADD3_CC__RA__RC, ARC600F_INSN_ADD3_CC__RA__RC, ARC600F_SFMT_ADD_CC__RA__RC },
+ { ARC_INSN_I16_GO_ADD3_S_GO, ARC600F_INSN_I16_GO_ADD3_S_GO, ARC600F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_SUB1_L_S12__RA_, ARC600F_INSN_SUB1_L_S12__RA_, ARC600F_SFMT_ADD_L_S12__RA_ },
+ { ARC_INSN_SUB1_CCU6__RA_, ARC600F_INSN_SUB1_CCU6__RA_, ARC600F_SFMT_ADD_CCU6__RA_ },
+ { ARC_INSN_SUB1_L_U6__RA_, ARC600F_INSN_SUB1_L_U6__RA_, ARC600F_SFMT_ADD_L_U6__RA_ },
+ { ARC_INSN_SUB1_L_R_R__RA__RC, ARC600F_INSN_SUB1_L_R_R__RA__RC, ARC600F_SFMT_ADD_L_R_R__RA__RC },
+ { ARC_INSN_SUB1_CC__RA__RC, ARC600F_INSN_SUB1_CC__RA__RC, ARC600F_SFMT_ADD_CC__RA__RC },
+ { ARC_INSN_SUB2_L_S12__RA_, ARC600F_INSN_SUB2_L_S12__RA_, ARC600F_SFMT_ADD_L_S12__RA_ },
+ { ARC_INSN_SUB2_CCU6__RA_, ARC600F_INSN_SUB2_CCU6__RA_, ARC600F_SFMT_ADD_CCU6__RA_ },
+ { ARC_INSN_SUB2_L_U6__RA_, ARC600F_INSN_SUB2_L_U6__RA_, ARC600F_SFMT_ADD_L_U6__RA_ },
+ { ARC_INSN_SUB2_L_R_R__RA__RC, ARC600F_INSN_SUB2_L_R_R__RA__RC, ARC600F_SFMT_ADD_L_R_R__RA__RC },
+ { ARC_INSN_SUB2_CC__RA__RC, ARC600F_INSN_SUB2_CC__RA__RC, ARC600F_SFMT_ADD_CC__RA__RC },
+ { ARC_INSN_SUB3_L_S12__RA_, ARC600F_INSN_SUB3_L_S12__RA_, ARC600F_SFMT_ADD_L_S12__RA_ },
+ { ARC_INSN_SUB3_CCU6__RA_, ARC600F_INSN_SUB3_CCU6__RA_, ARC600F_SFMT_ADD_CCU6__RA_ },
+ { ARC_INSN_SUB3_L_U6__RA_, ARC600F_INSN_SUB3_L_U6__RA_, ARC600F_SFMT_ADD_L_U6__RA_ },
+ { ARC_INSN_SUB3_L_R_R__RA__RC, ARC600F_INSN_SUB3_L_R_R__RA__RC, ARC600F_SFMT_ADD_L_R_R__RA__RC },
+ { ARC_INSN_SUB3_CC__RA__RC, ARC600F_INSN_SUB3_CC__RA__RC, ARC600F_SFMT_ADD_CC__RA__RC },
+ { ARC_INSN_MPY_L_S12__RA_, ARC600F_INSN_MPY_L_S12__RA_, ARC600F_SFMT_MPY_L_S12__RA_ },
+ { ARC_INSN_MPY_CCU6__RA_, ARC600F_INSN_MPY_CCU6__RA_, ARC600F_SFMT_MPY_CCU6__RA_ },
+ { ARC_INSN_MPY_L_U6__RA_, ARC600F_INSN_MPY_L_U6__RA_, ARC600F_SFMT_MPY_L_U6__RA_ },
+ { ARC_INSN_MPY_L_R_R__RA__RC, ARC600F_INSN_MPY_L_R_R__RA__RC, ARC600F_SFMT_MPY_L_R_R__RA__RC },
+ { ARC_INSN_MPY_CC__RA__RC, ARC600F_INSN_MPY_CC__RA__RC, ARC600F_SFMT_MPY_CC__RA__RC },
+ { ARC_INSN_MPYH_L_S12__RA_, ARC600F_INSN_MPYH_L_S12__RA_, ARC600F_SFMT_MPY_L_S12__RA_ },
+ { ARC_INSN_MPYH_CCU6__RA_, ARC600F_INSN_MPYH_CCU6__RA_, ARC600F_SFMT_MPY_CCU6__RA_ },
+ { ARC_INSN_MPYH_L_U6__RA_, ARC600F_INSN_MPYH_L_U6__RA_, ARC600F_SFMT_MPY_L_U6__RA_ },
+ { ARC_INSN_MPYH_L_R_R__RA__RC, ARC600F_INSN_MPYH_L_R_R__RA__RC, ARC600F_SFMT_MPY_L_R_R__RA__RC },
+ { ARC_INSN_MPYH_CC__RA__RC, ARC600F_INSN_MPYH_CC__RA__RC, ARC600F_SFMT_MPY_CC__RA__RC },
+ { ARC_INSN_MPYHU_L_S12__RA_, ARC600F_INSN_MPYHU_L_S12__RA_, ARC600F_SFMT_MPY_L_S12__RA_ },
+ { ARC_INSN_MPYHU_CCU6__RA_, ARC600F_INSN_MPYHU_CCU6__RA_, ARC600F_SFMT_MPY_CCU6__RA_ },
+ { ARC_INSN_MPYHU_L_U6__RA_, ARC600F_INSN_MPYHU_L_U6__RA_, ARC600F_SFMT_MPY_L_U6__RA_ },
+ { ARC_INSN_MPYHU_L_R_R__RA__RC, ARC600F_INSN_MPYHU_L_R_R__RA__RC, ARC600F_SFMT_MPY_L_R_R__RA__RC },
+ { ARC_INSN_MPYHU_CC__RA__RC, ARC600F_INSN_MPYHU_CC__RA__RC, ARC600F_SFMT_MPY_CC__RA__RC },
+ { ARC_INSN_MPYU_L_S12__RA_, ARC600F_INSN_MPYU_L_S12__RA_, ARC600F_SFMT_MPY_L_S12__RA_ },
+ { ARC_INSN_MPYU_CCU6__RA_, ARC600F_INSN_MPYU_CCU6__RA_, ARC600F_SFMT_MPY_CCU6__RA_ },
+ { ARC_INSN_MPYU_L_U6__RA_, ARC600F_INSN_MPYU_L_U6__RA_, ARC600F_SFMT_MPY_L_U6__RA_ },
+ { ARC_INSN_MPYU_L_R_R__RA__RC, ARC600F_INSN_MPYU_L_R_R__RA__RC, ARC600F_SFMT_MPY_L_R_R__RA__RC },
+ { ARC_INSN_MPYU_CC__RA__RC, ARC600F_INSN_MPYU_CC__RA__RC, ARC600F_SFMT_MPY_CC__RA__RC },
+ { ARC_INSN_J_L_R_R___RC_NOILINK_, ARC600F_INSN_J_L_R_R___RC_NOILINK_, ARC600F_SFMT_J_L_R_R___RC_NOILINK_ },
+ { ARC_INSN_J_CC___RC_NOILINK_, ARC600F_INSN_J_CC___RC_NOILINK_, ARC600F_SFMT_J_CC___RC_NOILINK_ },
+ { ARC_INSN_J_L_R_R___RC_ILINK_, ARC600F_INSN_J_L_R_R___RC_ILINK_, ARC600F_SFMT_J_L_R_R___RC_ILINK_ },
+ { ARC_INSN_J_CC___RC_ILINK_, ARC600F_INSN_J_CC___RC_ILINK_, ARC600F_SFMT_J_CC___RC_ILINK_ },
+ { ARC_INSN_J_L_S12_, ARC600F_INSN_J_L_S12_, ARC600F_SFMT_J_L_S12_ },
+ { ARC_INSN_J_CCU6_, ARC600F_INSN_J_CCU6_, ARC600F_SFMT_J_CCU6_ },
+ { ARC_INSN_J_L_U6_, ARC600F_INSN_J_L_U6_, ARC600F_SFMT_J_L_U6_ },
+ { ARC_INSN_J_S, ARC600F_INSN_J_S, ARC600F_SFMT_J_S },
+ { ARC_INSN_J_S__S, ARC600F_INSN_J_S__S, ARC600F_SFMT_J_S__S },
+ { ARC_INSN_J_SEQ__S, ARC600F_INSN_J_SEQ__S, ARC600F_SFMT_J_SEQ__S },
+ { ARC_INSN_J_SNE__S, ARC600F_INSN_J_SNE__S, ARC600F_SFMT_J_SEQ__S },
+ { ARC_INSN_J_L_S12_D_, ARC600F_INSN_J_L_S12_D_, ARC600F_SFMT_J_L_S12_D_ },
+ { ARC_INSN_J_CCU6_D_, ARC600F_INSN_J_CCU6_D_, ARC600F_SFMT_J_CCU6_D_ },
+ { ARC_INSN_J_L_U6_D_, ARC600F_INSN_J_L_U6_D_, ARC600F_SFMT_J_L_U6_D_ },
+ { ARC_INSN_J_L_R_R_D___RC_, ARC600F_INSN_J_L_R_R_D___RC_, ARC600F_SFMT_J_L_R_R_D___RC_ },
+ { ARC_INSN_J_CC_D___RC_, ARC600F_INSN_J_CC_D___RC_, ARC600F_SFMT_J_CC_D___RC_ },
+ { ARC_INSN_J_S_D, ARC600F_INSN_J_S_D, ARC600F_SFMT_J_S },
+ { ARC_INSN_J_S__S_D, ARC600F_INSN_J_S__S_D, ARC600F_SFMT_J_S__S },
+ { ARC_INSN_JL_L_S12_, ARC600F_INSN_JL_L_S12_, ARC600F_SFMT_JL_L_S12_ },
+ { ARC_INSN_JL_CCU6_, ARC600F_INSN_JL_CCU6_, ARC600F_SFMT_JL_CCU6_ },
+ { ARC_INSN_JL_L_U6_, ARC600F_INSN_JL_L_U6_, ARC600F_SFMT_JL_L_U6_ },
+ { ARC_INSN_JL_S, ARC600F_INSN_JL_S, ARC600F_SFMT_JL_S },
+ { ARC_INSN_JL_L_R_R___RC_NOILINK_, ARC600F_INSN_JL_L_R_R___RC_NOILINK_, ARC600F_SFMT_JL_L_R_R___RC_NOILINK_ },
+ { ARC_INSN_JL_CC___RC_NOILINK_, ARC600F_INSN_JL_CC___RC_NOILINK_, ARC600F_SFMT_JL_CC___RC_NOILINK_ },
+ { ARC_INSN_JL_L_S12_D_, ARC600F_INSN_JL_L_S12_D_, ARC600F_SFMT_JL_L_S12_ },
+ { ARC_INSN_JL_CCU6_D_, ARC600F_INSN_JL_CCU6_D_, ARC600F_SFMT_JL_CCU6_ },
+ { ARC_INSN_JL_L_U6_D_, ARC600F_INSN_JL_L_U6_D_, ARC600F_SFMT_JL_L_U6_ },
+ { ARC_INSN_JL_L_R_R_D___RC_, ARC600F_INSN_JL_L_R_R_D___RC_, ARC600F_SFMT_JL_L_R_R_D___RC_ },
+ { ARC_INSN_JL_CC_D___RC_, ARC600F_INSN_JL_CC_D___RC_, ARC600F_SFMT_JL_CC_D___RC_ },
+ { ARC_INSN_JL_S_D, ARC600F_INSN_JL_S_D, ARC600F_SFMT_JL_S_D },
+ { ARC_INSN_LP_L_S12_, ARC600F_INSN_LP_L_S12_, ARC600F_SFMT_LP_L_S12_ },
+ { ARC_INSN_LPCC_CCU6, ARC600F_INSN_LPCC_CCU6, ARC600F_SFMT_LPCC_CCU6 },
+ { ARC_INSN_FLAG_L_S12_, ARC600F_INSN_FLAG_L_S12_, ARC600F_SFMT_FLAG_L_S12_ },
+ { ARC_INSN_FLAG_CCU6_, ARC600F_INSN_FLAG_CCU6_, ARC600F_SFMT_FLAG_CCU6_ },
+ { ARC_INSN_FLAG_L_U6_, ARC600F_INSN_FLAG_L_U6_, ARC600F_SFMT_FLAG_L_U6_ },
+ { ARC_INSN_FLAG_L_R_R__RC, ARC600F_INSN_FLAG_L_R_R__RC, ARC600F_SFMT_FLAG_L_R_R__RC },
+ { ARC_INSN_FLAG_CC__RC, ARC600F_INSN_FLAG_CC__RC, ARC600F_SFMT_FLAG_CC__RC },
+ { ARC_INSN_LR_L_R_R___RC_, ARC600F_INSN_LR_L_R_R___RC_, ARC600F_SFMT_LR_L_R_R___RC_ },
+ { ARC_INSN_LR_L_S12_, ARC600F_INSN_LR_L_S12_, ARC600F_SFMT_LR_L_S12_ },
+ { ARC_INSN_LR_L_U6_, ARC600F_INSN_LR_L_U6_, ARC600F_SFMT_LR_L_U6_ },
+ { ARC_INSN_SR_L_R_R___RC_, ARC600F_INSN_SR_L_R_R___RC_, ARC600F_SFMT_SR_L_R_R___RC_ },
+ { ARC_INSN_SR_L_S12_, ARC600F_INSN_SR_L_S12_, ARC600F_SFMT_SR_L_S12_ },
+ { ARC_INSN_SR_L_U6_, ARC600F_INSN_SR_L_U6_, ARC600F_SFMT_SR_L_U6_ },
+ { ARC_INSN_ASL_L_R_R__RC, ARC600F_INSN_ASL_L_R_R__RC, ARC600F_SFMT_ASL_L_R_R__RC },
+ { ARC_INSN_ASL_L_U6_, ARC600F_INSN_ASL_L_U6_, ARC600F_SFMT_ASL_L_U6_ },
+ { ARC_INSN_I16_GO_ASL_S_GO, ARC600F_INSN_I16_GO_ASL_S_GO, ARC600F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_ASR_L_R_R__RC, ARC600F_INSN_ASR_L_R_R__RC, ARC600F_SFMT_ASR_L_R_R__RC },
+ { ARC_INSN_ASR_L_U6_, ARC600F_INSN_ASR_L_U6_, ARC600F_SFMT_ASR_L_U6_ },
+ { ARC_INSN_I16_GO_ASR_S_GO, ARC600F_INSN_I16_GO_ASR_S_GO, ARC600F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_LSR_L_R_R__RC, ARC600F_INSN_LSR_L_R_R__RC, ARC600F_SFMT_ASR_L_R_R__RC },
+ { ARC_INSN_LSR_L_U6_, ARC600F_INSN_LSR_L_U6_, ARC600F_SFMT_ASR_L_U6_ },
+ { ARC_INSN_I16_GO_LSR_S_GO, ARC600F_INSN_I16_GO_LSR_S_GO, ARC600F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_ROR_L_R_R__RC, ARC600F_INSN_ROR_L_R_R__RC, ARC600F_SFMT_ASR_L_R_R__RC },
+ { ARC_INSN_ROR_L_U6_, ARC600F_INSN_ROR_L_U6_, ARC600F_SFMT_ASR_L_U6_ },
+ { ARC_INSN_RRC_L_R_R__RC, ARC600F_INSN_RRC_L_R_R__RC, ARC600F_SFMT_RRC_L_R_R__RC },
+ { ARC_INSN_RRC_L_U6_, ARC600F_INSN_RRC_L_U6_, ARC600F_SFMT_RRC_L_U6_ },
+ { ARC_INSN_SEXB_L_R_R__RC, ARC600F_INSN_SEXB_L_R_R__RC, ARC600F_SFMT_SEXB_L_R_R__RC },
+ { ARC_INSN_SEXB_L_U6_, ARC600F_INSN_SEXB_L_U6_, ARC600F_SFMT_SEXB_L_U6_ },
+ { ARC_INSN_I16_GO_SEXB_S_GO, ARC600F_INSN_I16_GO_SEXB_S_GO, ARC600F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_SEXW_L_R_R__RC, ARC600F_INSN_SEXW_L_R_R__RC, ARC600F_SFMT_SEXW_L_R_R__RC },
+ { ARC_INSN_SEXW_L_U6_, ARC600F_INSN_SEXW_L_U6_, ARC600F_SFMT_SEXW_L_U6_ },
+ { ARC_INSN_I16_GO_SEXW_S_GO, ARC600F_INSN_I16_GO_SEXW_S_GO, ARC600F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_EXTB_L_R_R__RC, ARC600F_INSN_EXTB_L_R_R__RC, ARC600F_SFMT_SEXB_L_R_R__RC },
+ { ARC_INSN_EXTB_L_U6_, ARC600F_INSN_EXTB_L_U6_, ARC600F_SFMT_SEXB_L_U6_ },
+ { ARC_INSN_I16_GO_EXTB_S_GO, ARC600F_INSN_I16_GO_EXTB_S_GO, ARC600F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_EXTW_L_R_R__RC, ARC600F_INSN_EXTW_L_R_R__RC, ARC600F_SFMT_SEXW_L_R_R__RC },
+ { ARC_INSN_EXTW_L_U6_, ARC600F_INSN_EXTW_L_U6_, ARC600F_SFMT_SEXW_L_U6_ },
+ { ARC_INSN_I16_GO_EXTW_S_GO, ARC600F_INSN_I16_GO_EXTW_S_GO, ARC600F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_ABS_L_R_R__RC, ARC600F_INSN_ABS_L_R_R__RC, ARC600F_SFMT_ABS_L_R_R__RC },
+ { ARC_INSN_ABS_L_U6_, ARC600F_INSN_ABS_L_U6_, ARC600F_SFMT_ABS_L_U6_ },
+ { ARC_INSN_I16_GO_ABS_S_GO, ARC600F_INSN_I16_GO_ABS_S_GO, ARC600F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_NOT_L_R_R__RC, ARC600F_INSN_NOT_L_R_R__RC, ARC600F_SFMT_NOT_L_R_R__RC },
+ { ARC_INSN_NOT_L_U6_, ARC600F_INSN_NOT_L_U6_, ARC600F_SFMT_NOT_L_U6_ },
+ { ARC_INSN_I16_GO_NOT_S_GO, ARC600F_INSN_I16_GO_NOT_S_GO, ARC600F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_RLC_L_R_R__RC, ARC600F_INSN_RLC_L_R_R__RC, ARC600F_SFMT_RRC_L_R_R__RC },
+ { ARC_INSN_RLC_L_U6_, ARC600F_INSN_RLC_L_U6_, ARC600F_SFMT_RRC_L_U6_ },
+ { ARC_INSN_I16_GO_NEG_S_GO, ARC600F_INSN_I16_GO_NEG_S_GO, ARC600F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_SWI, ARC600F_INSN_SWI, ARC600F_SFMT_SWI },
+ { ARC_INSN_TRAP_S, ARC600F_INSN_TRAP_S, ARC600F_SFMT_TRAP_S },
+ { ARC_INSN_BRK, ARC600F_INSN_BRK, ARC600F_SFMT_BRK },
+ { ARC_INSN_BRK_S, ARC600F_INSN_BRK_S, ARC600F_SFMT_BRK },
+ { ARC_INSN_ASL_L_S12__RA_, ARC600F_INSN_ASL_L_S12__RA_, ARC600F_SFMT_ASL_L_S12__RA_ },
+ { ARC_INSN_ASL_CCU6__RA_, ARC600F_INSN_ASL_CCU6__RA_, ARC600F_SFMT_ASL_CCU6__RA_ },
+ { ARC_INSN_ASL_L_U6__RA_, ARC600F_INSN_ASL_L_U6__RA_, ARC600F_SFMT_ASL_L_U6__RA_ },
+ { ARC_INSN_ASL_L_R_R__RA__RC, ARC600F_INSN_ASL_L_R_R__RA__RC, ARC600F_SFMT_ASL_L_R_R__RA__RC },
+ { ARC_INSN_ASL_CC__RA__RC, ARC600F_INSN_ASL_CC__RA__RC, ARC600F_SFMT_ASL_CC__RA__RC },
+ { ARC_INSN_ASL_S_CBU3, ARC600F_INSN_ASL_S_CBU3, ARC600F_SFMT_ADD_S_CBU3 },
+ { ARC_INSN_ASL_S_SSB, ARC600F_INSN_ASL_S_SSB, ARC600F_SFMT_SUB_S_SSB },
+ { ARC_INSN_I16_GO_ASLM_S_GO, ARC600F_INSN_I16_GO_ASLM_S_GO, ARC600F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_LSR_L_S12__RA_, ARC600F_INSN_LSR_L_S12__RA_, ARC600F_SFMT_ASL_L_S12__RA_ },
+ { ARC_INSN_LSR_CCU6__RA_, ARC600F_INSN_LSR_CCU6__RA_, ARC600F_SFMT_ASL_CCU6__RA_ },
+ { ARC_INSN_LSR_L_U6__RA_, ARC600F_INSN_LSR_L_U6__RA_, ARC600F_SFMT_ASL_L_U6__RA_ },
+ { ARC_INSN_LSR_L_R_R__RA__RC, ARC600F_INSN_LSR_L_R_R__RA__RC, ARC600F_SFMT_ASL_L_R_R__RA__RC },
+ { ARC_INSN_LSR_CC__RA__RC, ARC600F_INSN_LSR_CC__RA__RC, ARC600F_SFMT_ASL_CC__RA__RC },
+ { ARC_INSN_LSR_S_SSB, ARC600F_INSN_LSR_S_SSB, ARC600F_SFMT_SUB_S_SSB },
+ { ARC_INSN_I16_GO_LSRM_S_GO, ARC600F_INSN_I16_GO_LSRM_S_GO, ARC600F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_ASR_L_S12__RA_, ARC600F_INSN_ASR_L_S12__RA_, ARC600F_SFMT_ASL_L_S12__RA_ },
+ { ARC_INSN_ASR_CCU6__RA_, ARC600F_INSN_ASR_CCU6__RA_, ARC600F_SFMT_ASL_CCU6__RA_ },
+ { ARC_INSN_ASR_L_U6__RA_, ARC600F_INSN_ASR_L_U6__RA_, ARC600F_SFMT_ASL_L_U6__RA_ },
+ { ARC_INSN_ASR_L_R_R__RA__RC, ARC600F_INSN_ASR_L_R_R__RA__RC, ARC600F_SFMT_ASL_L_R_R__RA__RC },
+ { ARC_INSN_ASR_CC__RA__RC, ARC600F_INSN_ASR_CC__RA__RC, ARC600F_SFMT_ASL_CC__RA__RC },
+ { ARC_INSN_ASR_S_CBU3, ARC600F_INSN_ASR_S_CBU3, ARC600F_SFMT_ADD_S_CBU3 },
+ { ARC_INSN_ASR_S_SSB, ARC600F_INSN_ASR_S_SSB, ARC600F_SFMT_SUB_S_SSB },
+ { ARC_INSN_I16_GO_ASRM_S_GO, ARC600F_INSN_I16_GO_ASRM_S_GO, ARC600F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_ROR_L_S12__RA_, ARC600F_INSN_ROR_L_S12__RA_, ARC600F_SFMT_ASL_L_S12__RA_ },
+ { ARC_INSN_ROR_CCU6__RA_, ARC600F_INSN_ROR_CCU6__RA_, ARC600F_SFMT_ASL_CCU6__RA_ },
+ { ARC_INSN_ROR_L_U6__RA_, ARC600F_INSN_ROR_L_U6__RA_, ARC600F_SFMT_ASL_L_U6__RA_ },
+ { ARC_INSN_ROR_L_R_R__RA__RC, ARC600F_INSN_ROR_L_R_R__RA__RC, ARC600F_SFMT_ASL_L_R_R__RA__RC },
+ { ARC_INSN_ROR_CC__RA__RC, ARC600F_INSN_ROR_CC__RA__RC, ARC600F_SFMT_ASL_CC__RA__RC },
+ { ARC_INSN_MUL64_L_S12_, ARC600F_INSN_MUL64_L_S12_, ARC600F_SFMT_MUL64_L_S12_ },
+ { ARC_INSN_MUL64_CCU6_, ARC600F_INSN_MUL64_CCU6_, ARC600F_SFMT_MUL64_CCU6_ },
+ { ARC_INSN_MUL64_L_U6_, ARC600F_INSN_MUL64_L_U6_, ARC600F_SFMT_MUL64_L_U6_ },
+ { ARC_INSN_MUL64_L_R_R__RC, ARC600F_INSN_MUL64_L_R_R__RC, ARC600F_SFMT_MUL64_L_R_R__RC },
+ { ARC_INSN_MUL64_CC__RC, ARC600F_INSN_MUL64_CC__RC, ARC600F_SFMT_MUL64_CC__RC },
+ { ARC_INSN_MUL64_S_GO, ARC600F_INSN_MUL64_S_GO, ARC600F_SFMT_MUL64_S_GO },
+ { ARC_INSN_MULU64_L_S12_, ARC600F_INSN_MULU64_L_S12_, ARC600F_SFMT_MUL64_L_S12_ },
+ { ARC_INSN_MULU64_CCU6_, ARC600F_INSN_MULU64_CCU6_, ARC600F_SFMT_MUL64_CCU6_ },
+ { ARC_INSN_MULU64_L_U6_, ARC600F_INSN_MULU64_L_U6_, ARC600F_SFMT_MUL64_L_U6_ },
+ { ARC_INSN_MULU64_L_R_R__RC, ARC600F_INSN_MULU64_L_R_R__RC, ARC600F_SFMT_MUL64_L_R_R__RC },
+ { ARC_INSN_MULU64_CC__RC, ARC600F_INSN_MULU64_CC__RC, ARC600F_SFMT_MUL64_CC__RC },
+ { ARC_INSN_ADDS_L_S12__RA_, ARC600F_INSN_ADDS_L_S12__RA_, ARC600F_SFMT_ADDS_L_S12__RA_ },
+ { ARC_INSN_ADDS_CCU6__RA_, ARC600F_INSN_ADDS_CCU6__RA_, ARC600F_SFMT_ADDS_CCU6__RA_ },
+ { ARC_INSN_ADDS_L_U6__RA_, ARC600F_INSN_ADDS_L_U6__RA_, ARC600F_SFMT_ADDS_L_U6__RA_ },
+ { ARC_INSN_ADDS_L_R_R__RA__RC, ARC600F_INSN_ADDS_L_R_R__RA__RC, ARC600F_SFMT_ADDS_L_R_R__RA__RC },
+ { ARC_INSN_ADDS_CC__RA__RC, ARC600F_INSN_ADDS_CC__RA__RC, ARC600F_SFMT_ADDS_CC__RA__RC },
+ { ARC_INSN_SUBS_L_S12__RA_, ARC600F_INSN_SUBS_L_S12__RA_, ARC600F_SFMT_ADDS_L_S12__RA_ },
+ { ARC_INSN_SUBS_CCU6__RA_, ARC600F_INSN_SUBS_CCU6__RA_, ARC600F_SFMT_ADDS_CCU6__RA_ },
+ { ARC_INSN_SUBS_L_U6__RA_, ARC600F_INSN_SUBS_L_U6__RA_, ARC600F_SFMT_ADDS_L_U6__RA_ },
+ { ARC_INSN_SUBS_L_R_R__RA__RC, ARC600F_INSN_SUBS_L_R_R__RA__RC, ARC600F_SFMT_ADDS_L_R_R__RA__RC },
+ { ARC_INSN_SUBS_CC__RA__RC, ARC600F_INSN_SUBS_CC__RA__RC, ARC600F_SFMT_ADDS_CC__RA__RC },
+ { ARC_INSN_DIVAW_L_S12__RA_, ARC600F_INSN_DIVAW_L_S12__RA_, ARC600F_SFMT_DIVAW_L_S12__RA_ },
+ { ARC_INSN_DIVAW_CCU6__RA_, ARC600F_INSN_DIVAW_CCU6__RA_, ARC600F_SFMT_DIVAW_CCU6__RA_ },
+ { ARC_INSN_DIVAW_L_U6__RA_, ARC600F_INSN_DIVAW_L_U6__RA_, ARC600F_SFMT_DIVAW_L_U6__RA_ },
+ { ARC_INSN_DIVAW_L_R_R__RA__RC, ARC600F_INSN_DIVAW_L_R_R__RA__RC, ARC600F_SFMT_DIVAW_L_R_R__RA__RC },
+ { ARC_INSN_DIVAW_CC__RA__RC, ARC600F_INSN_DIVAW_CC__RA__RC, ARC600F_SFMT_DIVAW_CC__RA__RC },
+ { ARC_INSN_ASLS_L_S12__RA_, ARC600F_INSN_ASLS_L_S12__RA_, ARC600F_SFMT_ASLS_L_S12__RA_ },
+ { ARC_INSN_ASLS_CCU6__RA_, ARC600F_INSN_ASLS_CCU6__RA_, ARC600F_SFMT_ASLS_CCU6__RA_ },
+ { ARC_INSN_ASLS_L_U6__RA_, ARC600F_INSN_ASLS_L_U6__RA_, ARC600F_SFMT_ASLS_L_U6__RA_ },
+ { ARC_INSN_ASLS_L_R_R__RA__RC, ARC600F_INSN_ASLS_L_R_R__RA__RC, ARC600F_SFMT_ASLS_L_R_R__RA__RC },
+ { ARC_INSN_ASLS_CC__RA__RC, ARC600F_INSN_ASLS_CC__RA__RC, ARC600F_SFMT_ASLS_CC__RA__RC },
+ { ARC_INSN_ASRS_L_S12__RA_, ARC600F_INSN_ASRS_L_S12__RA_, ARC600F_SFMT_ASLS_L_S12__RA_ },
+ { ARC_INSN_ASRS_CCU6__RA_, ARC600F_INSN_ASRS_CCU6__RA_, ARC600F_SFMT_ASLS_CCU6__RA_ },
+ { ARC_INSN_ASRS_L_U6__RA_, ARC600F_INSN_ASRS_L_U6__RA_, ARC600F_SFMT_ASLS_L_U6__RA_ },
+ { ARC_INSN_ASRS_L_R_R__RA__RC, ARC600F_INSN_ASRS_L_R_R__RA__RC, ARC600F_SFMT_ASLS_L_R_R__RA__RC },
+ { ARC_INSN_ASRS_CC__RA__RC, ARC600F_INSN_ASRS_CC__RA__RC, ARC600F_SFMT_ASLS_CC__RA__RC },
+ { ARC_INSN_ADDSDW_L_S12__RA_, ARC600F_INSN_ADDSDW_L_S12__RA_, ARC600F_SFMT_ASLS_L_S12__RA_ },
+ { ARC_INSN_ADDSDW_CCU6__RA_, ARC600F_INSN_ADDSDW_CCU6__RA_, ARC600F_SFMT_ASLS_CCU6__RA_ },
+ { ARC_INSN_ADDSDW_L_U6__RA_, ARC600F_INSN_ADDSDW_L_U6__RA_, ARC600F_SFMT_ASLS_L_U6__RA_ },
+ { ARC_INSN_ADDSDW_L_R_R__RA__RC, ARC600F_INSN_ADDSDW_L_R_R__RA__RC, ARC600F_SFMT_ASLS_L_R_R__RA__RC },
+ { ARC_INSN_ADDSDW_CC__RA__RC, ARC600F_INSN_ADDSDW_CC__RA__RC, ARC600F_SFMT_ASLS_CC__RA__RC },
+ { ARC_INSN_SUBSDW_L_S12__RA_, ARC600F_INSN_SUBSDW_L_S12__RA_, ARC600F_SFMT_ASLS_L_S12__RA_ },
+ { ARC_INSN_SUBSDW_CCU6__RA_, ARC600F_INSN_SUBSDW_CCU6__RA_, ARC600F_SFMT_ASLS_CCU6__RA_ },
+ { ARC_INSN_SUBSDW_L_U6__RA_, ARC600F_INSN_SUBSDW_L_U6__RA_, ARC600F_SFMT_ASLS_L_U6__RA_ },
+ { ARC_INSN_SUBSDW_L_R_R__RA__RC, ARC600F_INSN_SUBSDW_L_R_R__RA__RC, ARC600F_SFMT_ASLS_L_R_R__RA__RC },
+ { ARC_INSN_SUBSDW_CC__RA__RC, ARC600F_INSN_SUBSDW_CC__RA__RC, ARC600F_SFMT_ASLS_CC__RA__RC },
+ { ARC_INSN_SWAP_L_R_R__RC, ARC600F_INSN_SWAP_L_R_R__RC, ARC600F_SFMT_SWAP_L_R_R__RC },
+ { ARC_INSN_SWAP_L_U6_, ARC600F_INSN_SWAP_L_U6_, ARC600F_SFMT_SWAP_L_U6_ },
+ { ARC_INSN_NORM_L_R_R__RC, ARC600F_INSN_NORM_L_R_R__RC, ARC600F_SFMT_SWAP_L_R_R__RC },
+ { ARC_INSN_NORM_L_U6_, ARC600F_INSN_NORM_L_U6_, ARC600F_SFMT_NORM_L_U6_ },
+ { ARC_INSN_RND16_L_R_R__RC, ARC600F_INSN_RND16_L_R_R__RC, ARC600F_SFMT_RND16_L_R_R__RC },
+ { ARC_INSN_RND16_L_U6_, ARC600F_INSN_RND16_L_U6_, ARC600F_SFMT_RND16_L_U6_ },
+ { ARC_INSN_ABSSW_L_R_R__RC, ARC600F_INSN_ABSSW_L_R_R__RC, ARC600F_SFMT_ABSSW_L_R_R__RC },
+ { ARC_INSN_ABSSW_L_U6_, ARC600F_INSN_ABSSW_L_U6_, ARC600F_SFMT_ABSSW_L_U6_ },
+ { ARC_INSN_ABSS_L_R_R__RC, ARC600F_INSN_ABSS_L_R_R__RC, ARC600F_SFMT_RND16_L_R_R__RC },
+ { ARC_INSN_ABSS_L_U6_, ARC600F_INSN_ABSS_L_U6_, ARC600F_SFMT_ABSS_L_U6_ },
+ { ARC_INSN_NEGSW_L_R_R__RC, ARC600F_INSN_NEGSW_L_R_R__RC, ARC600F_SFMT_ABSSW_L_R_R__RC },
+ { ARC_INSN_NEGSW_L_U6_, ARC600F_INSN_NEGSW_L_U6_, ARC600F_SFMT_ABSSW_L_U6_ },
+ { ARC_INSN_NEGS_L_R_R__RC, ARC600F_INSN_NEGS_L_R_R__RC, ARC600F_SFMT_RND16_L_R_R__RC },
+ { ARC_INSN_NEGS_L_U6_, ARC600F_INSN_NEGS_L_U6_, ARC600F_SFMT_RND16_L_U6_ },
+ { ARC_INSN_NORMW_L_R_R__RC, ARC600F_INSN_NORMW_L_R_R__RC, ARC600F_SFMT_SWAP_L_R_R__RC },
+ { ARC_INSN_NORMW_L_U6_, ARC600F_INSN_NORMW_L_U6_, ARC600F_SFMT_SWAP_L_U6_ },
+ { ARC_INSN_NOP_S, ARC600F_INSN_NOP_S, ARC600F_SFMT_NOP_S },
+ { ARC_INSN_UNIMP_S, ARC600F_INSN_UNIMP_S, ARC600F_SFMT_NOP_S },
+ { ARC_INSN_POP_S_B, ARC600F_INSN_POP_S_B, ARC600F_SFMT_POP_S_B },
+ { ARC_INSN_POP_S_BLINK, ARC600F_INSN_POP_S_BLINK, ARC600F_SFMT_POP_S_BLINK },
+ { ARC_INSN_PUSH_S_B, ARC600F_INSN_PUSH_S_B, ARC600F_SFMT_PUSH_S_B },
+ { ARC_INSN_PUSH_S_BLINK, ARC600F_INSN_PUSH_S_BLINK, ARC600F_SFMT_PUSH_S_BLINK },
+ { ARC_INSN_MULLW_L_S12__RA_, ARC600F_INSN_MULLW_L_S12__RA_, ARC600F_SFMT_MULLW_L_S12__RA_ },
+ { ARC_INSN_MULLW_CCU6__RA_, ARC600F_INSN_MULLW_CCU6__RA_, ARC600F_SFMT_MULLW_CCU6__RA_ },
+ { ARC_INSN_MULLW_L_U6__RA_, ARC600F_INSN_MULLW_L_U6__RA_, ARC600F_SFMT_MULLW_L_U6__RA_ },
+ { ARC_INSN_MULLW_L_R_R__RA__RC, ARC600F_INSN_MULLW_L_R_R__RA__RC, ARC600F_SFMT_MULLW_L_R_R__RA__RC },
+ { ARC_INSN_MULLW_CC__RA__RC, ARC600F_INSN_MULLW_CC__RA__RC, ARC600F_SFMT_MULLW_CC__RA__RC },
+ { ARC_INSN_MACLW_L_S12__RA_, ARC600F_INSN_MACLW_L_S12__RA_, ARC600F_SFMT_MACLW_L_S12__RA_ },
+ { ARC_INSN_MACLW_CCU6__RA_, ARC600F_INSN_MACLW_CCU6__RA_, ARC600F_SFMT_MACLW_CCU6__RA_ },
+ { ARC_INSN_MACLW_L_U6__RA_, ARC600F_INSN_MACLW_L_U6__RA_, ARC600F_SFMT_MACLW_L_U6__RA_ },
+ { ARC_INSN_MACLW_L_R_R__RA__RC, ARC600F_INSN_MACLW_L_R_R__RA__RC, ARC600F_SFMT_MACLW_L_R_R__RA__RC },
+ { ARC_INSN_MACLW_CC__RA__RC, ARC600F_INSN_MACLW_CC__RA__RC, ARC600F_SFMT_MACLW_CC__RA__RC },
+ { ARC_INSN_MACHLW_L_S12__RA_, ARC600F_INSN_MACHLW_L_S12__RA_, ARC600F_SFMT_MACLW_L_S12__RA_ },
+ { ARC_INSN_MACHLW_CCU6__RA_, ARC600F_INSN_MACHLW_CCU6__RA_, ARC600F_SFMT_MACLW_CCU6__RA_ },
+ { ARC_INSN_MACHLW_L_U6__RA_, ARC600F_INSN_MACHLW_L_U6__RA_, ARC600F_SFMT_MACLW_L_U6__RA_ },
+ { ARC_INSN_MACHLW_L_R_R__RA__RC, ARC600F_INSN_MACHLW_L_R_R__RA__RC, ARC600F_SFMT_MACLW_L_R_R__RA__RC },
+ { ARC_INSN_MACHLW_CC__RA__RC, ARC600F_INSN_MACHLW_CC__RA__RC, ARC600F_SFMT_MACLW_CC__RA__RC },
+ { ARC_INSN_MULULW_L_S12__RA_, ARC600F_INSN_MULULW_L_S12__RA_, ARC600F_SFMT_MULLW_L_S12__RA_ },
+ { ARC_INSN_MULULW_CCU6__RA_, ARC600F_INSN_MULULW_CCU6__RA_, ARC600F_SFMT_MULLW_CCU6__RA_ },
+ { ARC_INSN_MULULW_L_U6__RA_, ARC600F_INSN_MULULW_L_U6__RA_, ARC600F_SFMT_MULLW_L_U6__RA_ },
+ { ARC_INSN_MULULW_L_R_R__RA__RC, ARC600F_INSN_MULULW_L_R_R__RA__RC, ARC600F_SFMT_MULLW_L_R_R__RA__RC },
+ { ARC_INSN_MULULW_CC__RA__RC, ARC600F_INSN_MULULW_CC__RA__RC, ARC600F_SFMT_MULLW_CC__RA__RC },
+ { ARC_INSN_MACHULW_L_S12__RA_, ARC600F_INSN_MACHULW_L_S12__RA_, ARC600F_SFMT_MACHULW_L_S12__RA_ },
+ { ARC_INSN_MACHULW_CCU6__RA_, ARC600F_INSN_MACHULW_CCU6__RA_, ARC600F_SFMT_MACHULW_CCU6__RA_ },
+ { ARC_INSN_MACHULW_L_U6__RA_, ARC600F_INSN_MACHULW_L_U6__RA_, ARC600F_SFMT_MACHULW_L_U6__RA_ },
+ { ARC_INSN_MACHULW_L_R_R__RA__RC, ARC600F_INSN_MACHULW_L_R_R__RA__RC, ARC600F_SFMT_MACHULW_L_R_R__RA__RC },
+ { ARC_INSN_MACHULW_CC__RA__RC, ARC600F_INSN_MACHULW_CC__RA__RC, ARC600F_SFMT_MACHULW_CC__RA__RC },
+ { ARC_INSN_CURRENT_LOOP_END, ARC600F_INSN_CURRENT_LOOP_END, ARC600F_SFMT_CURRENT_LOOP_END },
+ { ARC_INSN_CURRENT_LOOP_END_AFTER_BRANCH, ARC600F_INSN_CURRENT_LOOP_END_AFTER_BRANCH, ARC600F_SFMT_CURRENT_LOOP_END_AFTER_BRANCH },
+ { ARC_INSN_ARC600_CURRENT_LOOP_END_AFTER_BRANCH, ARC600F_INSN_ARC600_CURRENT_LOOP_END_AFTER_BRANCH, ARC600F_SFMT_CURRENT_LOOP_END_AFTER_BRANCH },
+};
+
+static const struct insn_sem arc600f_insn_sem_invalid = {
+ VIRTUAL_INSN_X_INVALID, ARC600F_INSN_X_INVALID, ARC600F_SFMT_EMPTY
+};
+
+/* Initialize an IDESC from the compile-time computable parts. */
+
+static INLINE void
+init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
+{
+ const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries;
+
+ id->num = t->index;
+ id->sfmt = t->sfmt;
+ if ((int) t->type <= 0)
+ id->idata = & cgen_virtual_insn_table[- (int) t->type];
+ else
+ id->idata = & insn_table[t->type];
+ id->attrs = CGEN_INSN_ATTRS (id->idata);
+ /* Oh my god, a magic number. */
+ id->length = CGEN_INSN_BITSIZE (id->idata) / 8;
+
+#if WITH_PROFILE_MODEL_P
+ id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index];
+ {
+ SIM_DESC sd = CPU_STATE (cpu);
+ SIM_ASSERT (t->index == id->timing->num);
+ }
+#endif
+
+ /* Semantic pointers are initialized elsewhere. */
+}
+
+/* Initialize the instruction descriptor table. */
+
+void
+arc600f_init_idesc_table (SIM_CPU *cpu)
+{
+ IDESC *id,*tabend;
+ const struct insn_sem *t,*tend;
+ int tabsize = ARC600F_INSN__MAX;
+ IDESC *table = arc600f_insn_data;
+
+ memset (table, 0, tabsize * sizeof (IDESC));
+
+ /* First set all entries to the `invalid insn'. */
+ t = & arc600f_insn_sem_invalid;
+ for (id = table, tabend = table + tabsize; id < tabend; ++id)
+ init_idesc (cpu, id, t);
+
+ /* Now fill in the values for the chosen cpu. */
+ for (t = arc600f_insn_sem, tend = t + sizeof (arc600f_insn_sem) / sizeof (*t);
+ t != tend; ++t)
+ {
+ init_idesc (cpu, & table[t->index], t);
+ }
+
+ /* Link the IDESC table into the cpu. */
+ CPU_IDESC (cpu) = table;
+}
+
+/* Given an instruction, return a pointer to its IDESC entry. */
+
+const IDESC *
+arc600f_decode (SIM_CPU *current_cpu, IADDR pc,
+ CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn,
+ ARGBUF *abuf)
+{
+ /* Result of decoder. */
+ ARC600F_INSN_TYPE itype;
+
+ {
+ CGEN_INSN_INT insn = base_insn;
+
+ {
+ unsigned int val = (((insn >> 20) & (1 << 10)) | ((insn >> 19) & (3 << 8)) | ((insn >> 16) & (255 << 0)));
+ switch (val)
+ {
+ case 0 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20000000)
+ { itype = ARC600F_INSN_ADD_L_R_R__RA__RC; goto extract_sfmt_add_L_r_r__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20010000)
+ { itype = ARC600F_INSN_ADC_L_R_R__RA__RC; goto extract_sfmt_adc_L_r_r__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 2 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20020000)
+ { itype = ARC600F_INSN_SUB_L_R_R__RA__RC; goto extract_sfmt_add_L_r_r__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 3 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20030000)
+ { itype = ARC600F_INSN_SBC_L_R_R__RA__RC; goto extract_sfmt_adc_L_r_r__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 4 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20040000)
+ { itype = ARC600F_INSN_AND_L_R_R__RA__RC; goto extract_sfmt_and_L_r_r__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 5 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20050000)
+ { itype = ARC600F_INSN_OR_L_R_R__RA__RC; goto extract_sfmt_and_L_r_r__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 6 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20060000)
+ { itype = ARC600F_INSN_BIC_L_R_R__RA__RC; goto extract_sfmt_and_L_r_r__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 7 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20070000)
+ { itype = ARC600F_INSN_XOR_L_R_R__RA__RC; goto extract_sfmt_and_L_r_r__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 8 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20080000)
+ { itype = ARC600F_INSN_MAX_L_R_R__RA__RC; goto extract_sfmt_add_L_r_r__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 9 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20090000)
+ { itype = ARC600F_INSN_MIN_L_R_R__RA__RC; goto extract_sfmt_add_L_r_r__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 10 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x200a0000)
+ { itype = ARC600F_INSN_MOV_L_R_R__RC; goto extract_sfmt_mov_L_r_r__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 11 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x200b0000)
+ { itype = ARC600F_INSN_TST_L_R_R__RC; goto extract_sfmt_tst_L_r_r__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 12 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x200c0000)
+ { itype = ARC600F_INSN_CMP_L_R_R__RC; goto extract_sfmt_cmp_L_r_r__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 13 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x200d0000)
+ { itype = ARC600F_INSN_RCMP_L_R_R__RC; goto extract_sfmt_cmp_L_r_r__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 14 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x200e0000)
+ { itype = ARC600F_INSN_RSUB_L_R_R__RA__RC; goto extract_sfmt_add_L_r_r__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 15 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x200f0000)
+ { itype = ARC600F_INSN_BSET_L_R_R__RA__RC; goto extract_sfmt_and_L_r_r__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 16 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20100000)
+ { itype = ARC600F_INSN_BCLR_L_R_R__RA__RC; goto extract_sfmt_and_L_r_r__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 17 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20110000)
+ { itype = ARC600F_INSN_BTST_L_R_R__RC; goto extract_sfmt_tst_L_r_r__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 18 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20120000)
+ { itype = ARC600F_INSN_BXOR_L_R_R__RA__RC; goto extract_sfmt_and_L_r_r__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 19 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20130000)
+ { itype = ARC600F_INSN_BMSK_L_R_R__RA__RC; goto extract_sfmt_and_L_r_r__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 20 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20140000)
+ { itype = ARC600F_INSN_ADD1_L_R_R__RA__RC; goto extract_sfmt_add_L_r_r__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 21 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20150000)
+ { itype = ARC600F_INSN_ADD2_L_R_R__RA__RC; goto extract_sfmt_add_L_r_r__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 22 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20160000)
+ { itype = ARC600F_INSN_ADD3_L_R_R__RA__RC; goto extract_sfmt_add_L_r_r__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 23 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20170000)
+ { itype = ARC600F_INSN_SUB1_L_R_R__RA__RC; goto extract_sfmt_add_L_r_r__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 24 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20180000)
+ { itype = ARC600F_INSN_SUB2_L_R_R__RA__RC; goto extract_sfmt_add_L_r_r__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 25 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20190000)
+ { itype = ARC600F_INSN_SUB3_L_R_R__RA__RC; goto extract_sfmt_add_L_r_r__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 26 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x201a0000)
+ { itype = ARC600F_INSN_MPY_L_R_R__RA__RC; goto extract_sfmt_mpy_L_r_r__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 27 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x201b0000)
+ { itype = ARC600F_INSN_MPYH_L_R_R__RA__RC; goto extract_sfmt_mpy_L_r_r__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 28 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x201c0000)
+ { itype = ARC600F_INSN_MPYHU_L_R_R__RA__RC; goto extract_sfmt_mpy_L_r_r__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 29 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x201d0000)
+ { itype = ARC600F_INSN_MPYU_L_R_R__RA__RC; goto extract_sfmt_mpy_L_r_r__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 30 : /* fall through */
+ case 36 : /* fall through */
+ case 38 : /* fall through */
+ case 40 : /* fall through */
+ case 44 : /* fall through */
+ case 46 : /* fall through */
+ case 54 : /* fall through */
+ case 56 : /* fall through */
+ case 58 : /* fall through */
+ case 60 : /* fall through */
+ case 62 : /* fall through */
+ case 94 : /* fall through */
+ case 100 : /* fall through */
+ case 102 : /* fall through */
+ case 104 : /* fall through */
+ case 108 : /* fall through */
+ case 110 : /* fall through */
+ case 118 : /* fall through */
+ case 120 : /* fall through */
+ case 122 : /* fall through */
+ case 124 : /* fall through */
+ case 126 : /* fall through */
+ case 158 : /* fall through */
+ case 164 : /* fall through */
+ case 166 : /* fall through */
+ case 172 : /* fall through */
+ case 174 : /* fall through */
+ case 182 : /* fall through */
+ case 184 : /* fall through */
+ case 186 : /* fall through */
+ case 188 : /* fall through */
+ case 190 : /* fall through */
+ case 222 : /* fall through */
+ case 228 : /* fall through */
+ case 230 : /* fall through */
+ case 234 : /* fall through */
+ case 236 : /* fall through */
+ case 238 : /* fall through */
+ case 246 : /* fall through */
+ case 248 : /* fall through */
+ case 250 : /* fall through */
+ case 252 : /* fall through */
+ case 254 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 31 : /* fall through */
+ case 37 : /* fall through */
+ case 39 : /* fall through */
+ case 45 : /* fall through */
+ case 49 : /* fall through */
+ case 55 : /* fall through */
+ case 57 : /* fall through */
+ case 59 : /* fall through */
+ case 61 : /* fall through */
+ case 63 : /* fall through */
+ case 95 : /* fall through */
+ case 101 : /* fall through */
+ case 103 : /* fall through */
+ case 109 : /* fall through */
+ case 113 : /* fall through */
+ case 119 : /* fall through */
+ case 121 : /* fall through */
+ case 123 : /* fall through */
+ case 125 : /* fall through */
+ case 127 : /* fall through */
+ case 159 : /* fall through */
+ case 165 : /* fall through */
+ case 167 : /* fall through */
+ case 173 : /* fall through */
+ case 175 : /* fall through */
+ case 177 : /* fall through */
+ case 183 : /* fall through */
+ case 185 : /* fall through */
+ case 187 : /* fall through */
+ case 189 : /* fall through */
+ case 191 : /* fall through */
+ case 223 : /* fall through */
+ case 229 : /* fall through */
+ case 231 : /* fall through */
+ case 235 : /* fall through */
+ case 237 : /* fall through */
+ case 239 : /* fall through */
+ case 241 : /* fall through */
+ case 247 : /* fall through */
+ case 249 : /* fall through */
+ case 251 : /* fall through */
+ case 253 : /* fall through */
+ case 255 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 32 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20200000)
+ { itype = ARC600F_INSN_J_L_R_R___RC_ILINK_; goto extract_sfmt_j_L_r_r___RC_ilink_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 33 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20210000)
+ { itype = ARC600F_INSN_J_L_R_R_D___RC_; goto extract_sfmt_j_L_r_r_d___RC_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 34 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20220000)
+ { itype = ARC600F_INSN_JL_L_R_R___RC_NOILINK_; goto extract_sfmt_jl_L_r_r___RC_noilink_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 35 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20230000)
+ { itype = ARC600F_INSN_JL_L_R_R_D___RC_; goto extract_sfmt_jl_L_r_r_d___RC_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 41 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20290000)
+ { itype = ARC600F_INSN_FLAG_L_R_R__RC; goto extract_sfmt_flag_L_r_r__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 42 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x202a0000)
+ { itype = ARC600F_INSN_LR_L_R_R___RC_; goto extract_sfmt_lr_L_r_r___RC_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 43 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x202b0000)
+ { itype = ARC600F_INSN_SR_L_R_R___RC_; goto extract_sfmt_sr_L_r_r___RC_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 47 :
+ {
+ unsigned int val = (((insn >> 23) & (1 << 6)) | ((insn >> 0) & (63 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 16 : /* fall through */
+ case 17 : /* fall through */
+ case 18 : /* fall through */
+ case 19 : /* fall through */
+ case 20 : /* fall through */
+ case 21 : /* fall through */
+ case 22 : /* fall through */
+ case 23 : /* fall through */
+ case 24 : /* fall through */
+ case 25 : /* fall through */
+ case 26 : /* fall through */
+ case 27 : /* fall through */
+ case 28 : /* fall through */
+ case 29 : /* fall through */
+ case 30 : /* fall through */
+ case 31 : /* fall through */
+ case 48 : /* fall through */
+ case 49 : /* fall through */
+ case 50 : /* fall through */
+ case 51 : /* fall through */
+ case 52 : /* fall through */
+ case 53 : /* fall through */
+ case 54 : /* fall through */
+ case 55 : /* fall through */
+ case 56 : /* fall through */
+ case 57 : /* fall through */
+ case 58 : /* fall through */
+ case 59 : /* fall through */
+ case 60 : /* fall through */
+ case 61 : /* fall through */
+ case 62 : /* fall through */
+ case 63 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 32 : /* fall through */
+ case 33 : /* fall through */
+ case 34 : /* fall through */
+ case 35 : /* fall through */
+ case 36 : /* fall through */
+ case 37 : /* fall through */
+ case 38 : /* fall through */
+ case 39 : /* fall through */
+ case 40 : /* fall through */
+ case 41 : /* fall through */
+ case 42 : /* fall through */
+ case 43 : /* fall through */
+ case 44 : /* fall through */
+ case 45 : /* fall through */
+ case 46 : /* fall through */
+ case 47 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 64 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x202f0000)
+ { itype = ARC600F_INSN_ASL_L_R_R__RC; goto extract_sfmt_asl_L_r_r__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 65 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x202f0001)
+ { itype = ARC600F_INSN_ASR_L_R_R__RC; goto extract_sfmt_asr_L_r_r__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 66 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x202f0002)
+ { itype = ARC600F_INSN_LSR_L_R_R__RC; goto extract_sfmt_asr_L_r_r__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 67 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x202f0003)
+ { itype = ARC600F_INSN_ROR_L_R_R__RC; goto extract_sfmt_asr_L_r_r__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 68 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x202f0004)
+ { itype = ARC600F_INSN_RRC_L_R_R__RC; goto extract_sfmt_rrc_L_r_r__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 69 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x202f0005)
+ { itype = ARC600F_INSN_SEXB_L_R_R__RC; goto extract_sfmt_sexb_L_r_r__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 70 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x202f0006)
+ { itype = ARC600F_INSN_SEXW_L_R_R__RC; goto extract_sfmt_sexw_L_r_r__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 71 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x202f0007)
+ { itype = ARC600F_INSN_EXTB_L_R_R__RC; goto extract_sfmt_sexb_L_r_r__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 72 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x202f0008)
+ { itype = ARC600F_INSN_EXTW_L_R_R__RC; goto extract_sfmt_sexw_L_r_r__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 73 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x202f0009)
+ { itype = ARC600F_INSN_ABS_L_R_R__RC; goto extract_sfmt_abs_L_r_r__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 74 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x202f000a)
+ { itype = ARC600F_INSN_NOT_L_R_R__RC; goto extract_sfmt_not_L_r_r__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 75 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x202f000b)
+ { itype = ARC600F_INSN_RLC_L_R_R__RC; goto extract_sfmt_rrc_L_r_r__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 76 : /* fall through */
+ case 77 : /* fall through */
+ case 78 : /* fall through */
+ case 79 : /* fall through */
+ case 80 : /* fall through */
+ case 81 : /* fall through */
+ case 82 : /* fall through */
+ case 83 : /* fall through */
+ case 84 : /* fall through */
+ case 85 : /* fall through */
+ case 86 : /* fall through */
+ case 87 : /* fall through */
+ case 88 : /* fall through */
+ case 89 : /* fall through */
+ case 90 : /* fall through */
+ case 91 : /* fall through */
+ case 92 : /* fall through */
+ case 93 : /* fall through */
+ case 94 : /* fall through */
+ case 95 : /* fall through */
+ case 96 : /* fall through */
+ case 97 : /* fall through */
+ case 98 : /* fall through */
+ case 99 : /* fall through */
+ case 100 : /* fall through */
+ case 101 : /* fall through */
+ case 102 : /* fall through */
+ case 103 : /* fall through */
+ case 104 : /* fall through */
+ case 105 : /* fall through */
+ case 106 : /* fall through */
+ case 107 : /* fall through */
+ case 108 : /* fall through */
+ case 109 : /* fall through */
+ case 110 : /* fall through */
+ case 111 : /* fall through */
+ case 112 : /* fall through */
+ case 113 : /* fall through */
+ case 114 : /* fall through */
+ case 115 : /* fall through */
+ case 116 : /* fall through */
+ case 117 : /* fall through */
+ case 118 : /* fall through */
+ case 119 : /* fall through */
+ case 120 : /* fall through */
+ case 121 : /* fall through */
+ case 122 : /* fall through */
+ case 123 : /* fall through */
+ case 124 : /* fall through */
+ case 125 : /* fall through */
+ case 127 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 126 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x202f003e)
+ { itype = ARC600F_INSN_CURRENT_LOOP_END; goto extract_sfmt_current_loop_end; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 48 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20300000)
+ { itype = ARC600F_INSN_LD_ABC; goto extract_sfmt_ld_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 50 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20320000)
+ { itype = ARC600F_INSN_LDB_ABC; goto extract_sfmt_ldb_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 51 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20330000)
+ { itype = ARC600F_INSN_LDB_X_ABC; goto extract_sfmt_ldb_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 52 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20340000)
+ { itype = ARC600F_INSN_LDW_ABC; goto extract_sfmt_ldw_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 53 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20350000)
+ { itype = ARC600F_INSN_LDW_X_ABC; goto extract_sfmt_ldw_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 64 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20400000)
+ { itype = ARC600F_INSN_ADD_L_U6__RA_; goto extract_sfmt_add_L_u6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 65 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20410000)
+ { itype = ARC600F_INSN_ADC_L_U6__RA_; goto extract_sfmt_adc_L_u6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 66 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20420000)
+ { itype = ARC600F_INSN_SUB_L_U6__RA_; goto extract_sfmt_add_L_u6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 67 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20430000)
+ { itype = ARC600F_INSN_SBC_L_U6__RA_; goto extract_sfmt_adc_L_u6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 68 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20440000)
+ { itype = ARC600F_INSN_AND_L_U6__RA_; goto extract_sfmt_and_L_u6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 69 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20450000)
+ { itype = ARC600F_INSN_OR_L_U6__RA_; goto extract_sfmt_and_L_u6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 70 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20460000)
+ { itype = ARC600F_INSN_BIC_L_U6__RA_; goto extract_sfmt_and_L_u6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 71 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20470000)
+ { itype = ARC600F_INSN_XOR_L_U6__RA_; goto extract_sfmt_and_L_u6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 72 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20480000)
+ { itype = ARC600F_INSN_MAX_L_U6__RA_; goto extract_sfmt_add_L_u6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 73 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20490000)
+ { itype = ARC600F_INSN_MIN_L_U6__RA_; goto extract_sfmt_add_L_u6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 74 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x204a0000)
+ { itype = ARC600F_INSN_MOV_L_U6_; goto extract_sfmt_mov_L_u6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 75 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x204b0000)
+ { itype = ARC600F_INSN_TST_L_U6_; goto extract_sfmt_tst_L_u6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 76 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x204c0000)
+ { itype = ARC600F_INSN_CMP_L_U6_; goto extract_sfmt_cmp_L_u6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 77 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x204d0000)
+ { itype = ARC600F_INSN_RCMP_L_U6_; goto extract_sfmt_cmp_L_u6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 78 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x204e0000)
+ { itype = ARC600F_INSN_RSUB_L_U6__RA_; goto extract_sfmt_add_L_u6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 79 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x204f0000)
+ { itype = ARC600F_INSN_BSET_L_U6__RA_; goto extract_sfmt_and_L_u6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 80 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20500000)
+ { itype = ARC600F_INSN_BCLR_L_U6__RA_; goto extract_sfmt_and_L_u6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 81 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20510000)
+ { itype = ARC600F_INSN_BTST_L_U6_; goto extract_sfmt_tst_L_u6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 82 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20520000)
+ { itype = ARC600F_INSN_BXOR_L_U6__RA_; goto extract_sfmt_and_L_u6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 83 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20530000)
+ { itype = ARC600F_INSN_BMSK_L_U6__RA_; goto extract_sfmt_and_L_u6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 84 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20540000)
+ { itype = ARC600F_INSN_ADD1_L_U6__RA_; goto extract_sfmt_add_L_u6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 85 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20550000)
+ { itype = ARC600F_INSN_ADD2_L_U6__RA_; goto extract_sfmt_add_L_u6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 86 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20560000)
+ { itype = ARC600F_INSN_ADD3_L_U6__RA_; goto extract_sfmt_add_L_u6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 87 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20570000)
+ { itype = ARC600F_INSN_SUB1_L_U6__RA_; goto extract_sfmt_add_L_u6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 88 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20580000)
+ { itype = ARC600F_INSN_SUB2_L_U6__RA_; goto extract_sfmt_add_L_u6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 89 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20590000)
+ { itype = ARC600F_INSN_SUB3_L_U6__RA_; goto extract_sfmt_add_L_u6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 90 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x205a0000)
+ { itype = ARC600F_INSN_MPY_L_U6__RA_; goto extract_sfmt_mpy_L_u6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 91 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x205b0000)
+ { itype = ARC600F_INSN_MPYH_L_U6__RA_; goto extract_sfmt_mpy_L_u6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 92 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x205c0000)
+ { itype = ARC600F_INSN_MPYHU_L_U6__RA_; goto extract_sfmt_mpy_L_u6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 93 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x205d0000)
+ { itype = ARC600F_INSN_MPYU_L_U6__RA_; goto extract_sfmt_mpy_L_u6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 96 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20600000)
+ { itype = ARC600F_INSN_J_L_U6_; goto extract_sfmt_j_L_u6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 97 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20610000)
+ { itype = ARC600F_INSN_J_L_U6_D_; goto extract_sfmt_j_L_u6_d_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 98 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20620000)
+ { itype = ARC600F_INSN_JL_L_U6_; goto extract_sfmt_jl_L_u6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 99 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20630000)
+ { itype = ARC600F_INSN_JL_L_U6_D_; goto extract_sfmt_jl_L_u6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 105 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20690000)
+ { itype = ARC600F_INSN_FLAG_L_U6_; goto extract_sfmt_flag_L_u6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 106 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x206a0000)
+ { itype = ARC600F_INSN_LR_L_U6_; goto extract_sfmt_lr_L_u6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 107 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x206b0000)
+ { itype = ARC600F_INSN_SR_L_U6_; goto extract_sfmt_sr_L_u6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 111 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff003f) == 0x206f0000)
+ { itype = ARC600F_INSN_ASL_L_U6_; goto extract_sfmt_asl_L_u6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff003f) == 0x206f0001)
+ { itype = ARC600F_INSN_ASR_L_U6_; goto extract_sfmt_asr_L_u6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 2 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff003f) == 0x206f0002)
+ { itype = ARC600F_INSN_LSR_L_U6_; goto extract_sfmt_asr_L_u6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 3 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff003f) == 0x206f0003)
+ { itype = ARC600F_INSN_ROR_L_U6_; goto extract_sfmt_asr_L_u6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 4 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff003f) == 0x206f0004)
+ { itype = ARC600F_INSN_RRC_L_U6_; goto extract_sfmt_rrc_L_u6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 5 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff003f) == 0x206f0005)
+ { itype = ARC600F_INSN_SEXB_L_U6_; goto extract_sfmt_sexb_L_u6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 6 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff003f) == 0x206f0006)
+ { itype = ARC600F_INSN_SEXW_L_U6_; goto extract_sfmt_sexw_L_u6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 7 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff003f) == 0x206f0007)
+ { itype = ARC600F_INSN_EXTB_L_U6_; goto extract_sfmt_sexb_L_u6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 8 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff003f) == 0x206f0008)
+ { itype = ARC600F_INSN_EXTW_L_U6_; goto extract_sfmt_sexw_L_u6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 9 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff003f) == 0x206f0009)
+ { itype = ARC600F_INSN_ABS_L_U6_; goto extract_sfmt_abs_L_u6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 10 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff003f) == 0x206f000a)
+ { itype = ARC600F_INSN_NOT_L_U6_; goto extract_sfmt_not_L_u6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 11 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff003f) == 0x206f000b)
+ { itype = ARC600F_INSN_RLC_L_U6_; goto extract_sfmt_rrc_L_u6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 15 :
+ {
+ unsigned int val = (((insn >> 25) & (1 << 6)) | ((insn >> 24) & (1 << 5)) | ((insn >> 22) & (7 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 4 : /* fall through */
+ case 8 : /* fall through */
+ case 12 : /* fall through */
+ case 16 : /* fall through */
+ case 20 : /* fall through */
+ case 24 : /* fall through */
+ case 28 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 6 : /* fall through */
+ case 10 : /* fall through */
+ case 14 : /* fall through */
+ case 18 : /* fall through */
+ case 22 : /* fall through */
+ case 26 : /* fall through */
+ case 30 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 43 :
+ if ((entire_insn & 0xffff7fff) == 0x226f003f)
+ { itype = ARC600F_INSN_SWI; goto extract_sfmt_swi; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 55 :
+ if ((entire_insn & 0xffff7fff) == 0x256f003f)
+ { itype = ARC600F_INSN_BRK; goto extract_sfmt_brk; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 64 : /* fall through */
+ case 65 : /* fall through */
+ case 66 : /* fall through */
+ case 67 : /* fall through */
+ case 68 : /* fall through */
+ case 69 : /* fall through */
+ case 70 : /* fall through */
+ case 71 : /* fall through */
+ case 72 : /* fall through */
+ case 73 : /* fall through */
+ case 74 : /* fall through */
+ case 75 : /* fall through */
+ case 76 : /* fall through */
+ case 77 : /* fall through */
+ case 78 : /* fall through */
+ case 79 : /* fall through */
+ case 80 : /* fall through */
+ case 81 : /* fall through */
+ case 82 : /* fall through */
+ case 83 : /* fall through */
+ case 84 : /* fall through */
+ case 85 : /* fall through */
+ case 86 : /* fall through */
+ case 87 : /* fall through */
+ case 88 : /* fall through */
+ case 89 : /* fall through */
+ case 90 : /* fall through */
+ case 91 : /* fall through */
+ case 92 : /* fall through */
+ case 93 : /* fall through */
+ case 94 : /* fall through */
+ case 95 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 96 : /* fall through */
+ case 97 : /* fall through */
+ case 98 : /* fall through */
+ case 99 : /* fall through */
+ case 100 : /* fall through */
+ case 101 : /* fall through */
+ case 102 : /* fall through */
+ case 103 : /* fall through */
+ case 104 : /* fall through */
+ case 105 : /* fall through */
+ case 106 : /* fall through */
+ case 107 : /* fall through */
+ case 108 : /* fall through */
+ case 109 : /* fall through */
+ case 110 : /* fall through */
+ case 111 : /* fall through */
+ case 112 : /* fall through */
+ case 113 : /* fall through */
+ case 114 : /* fall through */
+ case 115 : /* fall through */
+ case 116 : /* fall through */
+ case 117 : /* fall through */
+ case 118 : /* fall through */
+ case 119 : /* fall through */
+ case 120 : /* fall through */
+ case 121 : /* fall through */
+ case 122 : /* fall through */
+ case 123 : /* fall through */
+ case 124 : /* fall through */
+ case 125 : /* fall through */
+ case 126 : /* fall through */
+ case 127 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 112 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20700000)
+ { itype = ARC600F_INSN_LD__AW_ABC; goto extract_sfmt_ld__AW_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 114 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20720000)
+ { itype = ARC600F_INSN_LDB__AW_ABC; goto extract_sfmt_ldb__AW_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 115 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20730000)
+ { itype = ARC600F_INSN_LDB__AW_X_ABC; goto extract_sfmt_ldb__AW_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 116 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20740000)
+ { itype = ARC600F_INSN_LDW__AW_ABC; goto extract_sfmt_ldw__AW_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 117 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20750000)
+ { itype = ARC600F_INSN_LDW__AW_X_ABC; goto extract_sfmt_ldw__AW_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 128 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20800000)
+ { itype = ARC600F_INSN_ADD_L_S12__RA_; goto extract_sfmt_add_L_s12__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 129 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20810000)
+ { itype = ARC600F_INSN_ADC_L_S12__RA_; goto extract_sfmt_adc_L_s12__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 130 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20820000)
+ { itype = ARC600F_INSN_SUB_L_S12__RA_; goto extract_sfmt_add_L_s12__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 131 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20830000)
+ { itype = ARC600F_INSN_SBC_L_S12__RA_; goto extract_sfmt_adc_L_s12__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 132 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20840000)
+ { itype = ARC600F_INSN_AND_L_S12__RA_; goto extract_sfmt_and_L_s12__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 133 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20850000)
+ { itype = ARC600F_INSN_OR_L_S12__RA_; goto extract_sfmt_and_L_s12__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 134 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20860000)
+ { itype = ARC600F_INSN_BIC_L_S12__RA_; goto extract_sfmt_and_L_s12__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 135 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20870000)
+ { itype = ARC600F_INSN_XOR_L_S12__RA_; goto extract_sfmt_and_L_s12__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 136 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20880000)
+ { itype = ARC600F_INSN_MAX_L_S12__RA_; goto extract_sfmt_add_L_s12__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 137 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20890000)
+ { itype = ARC600F_INSN_MIN_L_S12__RA_; goto extract_sfmt_add_L_s12__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 138 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x208a0000)
+ { itype = ARC600F_INSN_MOV_L_S12_; goto extract_sfmt_mov_L_s12_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 139 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x208b0000)
+ { itype = ARC600F_INSN_TST_L_S12_; goto extract_sfmt_tst_L_s12_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 140 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x208c0000)
+ { itype = ARC600F_INSN_CMP_L_S12_; goto extract_sfmt_cmp_L_s12_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 141 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x208d0000)
+ { itype = ARC600F_INSN_RCMP_L_S12_; goto extract_sfmt_cmp_L_s12_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 142 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x208e0000)
+ { itype = ARC600F_INSN_RSUB_L_S12__RA_; goto extract_sfmt_add_L_s12__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 143 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x208f0000)
+ { itype = ARC600F_INSN_BSET_L_S12__RA_; goto extract_sfmt_and_L_s12__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 144 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20900000)
+ { itype = ARC600F_INSN_BCLR_L_S12__RA_; goto extract_sfmt_and_L_s12__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 145 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20910000)
+ { itype = ARC600F_INSN_BTST_L_S12_; goto extract_sfmt_tst_L_s12_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 146 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20920000)
+ { itype = ARC600F_INSN_BXOR_L_S12__RA_; goto extract_sfmt_and_L_s12__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 147 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20930000)
+ { itype = ARC600F_INSN_BMSK_L_S12__RA_; goto extract_sfmt_and_L_s12__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 148 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20940000)
+ { itype = ARC600F_INSN_ADD1_L_S12__RA_; goto extract_sfmt_add_L_s12__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 149 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20950000)
+ { itype = ARC600F_INSN_ADD2_L_S12__RA_; goto extract_sfmt_add_L_s12__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 150 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20960000)
+ { itype = ARC600F_INSN_ADD3_L_S12__RA_; goto extract_sfmt_add_L_s12__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 151 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20970000)
+ { itype = ARC600F_INSN_SUB1_L_S12__RA_; goto extract_sfmt_add_L_s12__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 152 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20980000)
+ { itype = ARC600F_INSN_SUB2_L_S12__RA_; goto extract_sfmt_add_L_s12__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 153 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20990000)
+ { itype = ARC600F_INSN_SUB3_L_S12__RA_; goto extract_sfmt_add_L_s12__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 154 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x209a0000)
+ { itype = ARC600F_INSN_MPY_L_S12__RA_; goto extract_sfmt_mpy_L_s12__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 155 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x209b0000)
+ { itype = ARC600F_INSN_MPYH_L_S12__RA_; goto extract_sfmt_mpy_L_s12__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 156 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x209c0000)
+ { itype = ARC600F_INSN_MPYHU_L_S12__RA_; goto extract_sfmt_mpy_L_s12__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 157 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x209d0000)
+ { itype = ARC600F_INSN_MPYU_L_S12__RA_; goto extract_sfmt_mpy_L_s12__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 160 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20a00000)
+ { itype = ARC600F_INSN_J_L_S12_; goto extract_sfmt_j_L_s12_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 161 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20a10000)
+ { itype = ARC600F_INSN_J_L_S12_D_; goto extract_sfmt_j_L_s12_d_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 162 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20a20000)
+ { itype = ARC600F_INSN_JL_L_S12_; goto extract_sfmt_jl_L_s12_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 163 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20a30000)
+ { itype = ARC600F_INSN_JL_L_S12_D_; goto extract_sfmt_jl_L_s12_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 168 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20a80000)
+ { itype = ARC600F_INSN_LP_L_S12_; goto extract_sfmt_lp_L_s12_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 169 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20a90000)
+ { itype = ARC600F_INSN_FLAG_L_S12_; goto extract_sfmt_flag_L_s12_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 170 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20aa0000)
+ { itype = ARC600F_INSN_LR_L_S12_; goto extract_sfmt_lr_L_s12_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 171 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20ab0000)
+ { itype = ARC600F_INSN_SR_L_S12_; goto extract_sfmt_sr_L_s12_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 176 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20b00000)
+ { itype = ARC600F_INSN_LD_AB_ABC; goto extract_sfmt_ld__AW_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 178 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20b20000)
+ { itype = ARC600F_INSN_LDB_AB_ABC; goto extract_sfmt_ldb__AW_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 179 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20b30000)
+ { itype = ARC600F_INSN_LDB_AB_X_ABC; goto extract_sfmt_ldb__AW_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 180 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20b40000)
+ { itype = ARC600F_INSN_LDW_AB_ABC; goto extract_sfmt_ldw__AW_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 181 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20b50000)
+ { itype = ARC600F_INSN_LDW_AB_X_ABC; goto extract_sfmt_ldw__AW_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 192 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c00000)
+ { itype = ARC600F_INSN_ADD_CC__RA__RC; goto extract_sfmt_add_cc__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c00020)
+ { itype = ARC600F_INSN_ADD_CCU6__RA_; goto extract_sfmt_add_ccu6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 193 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c10000)
+ { itype = ARC600F_INSN_ADC_CC__RA__RC; goto extract_sfmt_adc_cc__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c10020)
+ { itype = ARC600F_INSN_ADC_CCU6__RA_; goto extract_sfmt_adc_ccu6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 194 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c20000)
+ { itype = ARC600F_INSN_SUB_CC__RA__RC; goto extract_sfmt_add_cc__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c20020)
+ { itype = ARC600F_INSN_SUB_CCU6__RA_; goto extract_sfmt_add_ccu6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 195 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c30000)
+ { itype = ARC600F_INSN_SBC_CC__RA__RC; goto extract_sfmt_adc_cc__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c30020)
+ { itype = ARC600F_INSN_SBC_CCU6__RA_; goto extract_sfmt_adc_ccu6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 196 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c40000)
+ { itype = ARC600F_INSN_AND_CC__RA__RC; goto extract_sfmt_and_cc__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c40020)
+ { itype = ARC600F_INSN_AND_CCU6__RA_; goto extract_sfmt_and_ccu6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 197 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c50000)
+ { itype = ARC600F_INSN_OR_CC__RA__RC; goto extract_sfmt_and_cc__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c50020)
+ { itype = ARC600F_INSN_OR_CCU6__RA_; goto extract_sfmt_and_ccu6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 198 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c60000)
+ { itype = ARC600F_INSN_BIC_CC__RA__RC; goto extract_sfmt_and_cc__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c60020)
+ { itype = ARC600F_INSN_BIC_CCU6__RA_; goto extract_sfmt_and_ccu6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 199 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c70000)
+ { itype = ARC600F_INSN_XOR_CC__RA__RC; goto extract_sfmt_and_cc__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c70020)
+ { itype = ARC600F_INSN_XOR_CCU6__RA_; goto extract_sfmt_and_ccu6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 200 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c80000)
+ { itype = ARC600F_INSN_MAX_CC__RA__RC; goto extract_sfmt_add_cc__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c80020)
+ { itype = ARC600F_INSN_MAX_CCU6__RA_; goto extract_sfmt_add_ccu6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 201 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c90000)
+ { itype = ARC600F_INSN_MIN_CC__RA__RC; goto extract_sfmt_add_cc__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c90020)
+ { itype = ARC600F_INSN_MIN_CCU6__RA_; goto extract_sfmt_add_ccu6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 202 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20ca0000)
+ { itype = ARC600F_INSN_MOV_CC__RC; goto extract_sfmt_mov_cc__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20ca0020)
+ { itype = ARC600F_INSN_MOV_CCU6_; goto extract_sfmt_mov_ccu6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 203 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20cb0000)
+ { itype = ARC600F_INSN_TST_CC__RC; goto extract_sfmt_tst_cc__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20cb0020)
+ { itype = ARC600F_INSN_TST_CCU6_; goto extract_sfmt_tst_ccu6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 204 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20cc0000)
+ { itype = ARC600F_INSN_CMP_CC__RC; goto extract_sfmt_cmp_cc__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20cc0020)
+ { itype = ARC600F_INSN_CMP_CCU6_; goto extract_sfmt_cmp_ccu6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 205 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20cd0000)
+ { itype = ARC600F_INSN_RCMP_CC__RC; goto extract_sfmt_cmp_cc__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20cd0020)
+ { itype = ARC600F_INSN_RCMP_CCU6_; goto extract_sfmt_cmp_ccu6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 206 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20ce0000)
+ { itype = ARC600F_INSN_RSUB_CC__RA__RC; goto extract_sfmt_add_cc__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20ce0020)
+ { itype = ARC600F_INSN_RSUB_CCU6__RA_; goto extract_sfmt_add_ccu6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 207 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20cf0000)
+ { itype = ARC600F_INSN_BSET_CC__RA__RC; goto extract_sfmt_and_cc__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20cf0020)
+ { itype = ARC600F_INSN_BSET_CCU6__RA_; goto extract_sfmt_and_ccu6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 208 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d00000)
+ { itype = ARC600F_INSN_BCLR_CC__RA__RC; goto extract_sfmt_and_cc__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d00020)
+ { itype = ARC600F_INSN_BCLR_CCU6__RA_; goto extract_sfmt_and_ccu6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 209 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d10000)
+ { itype = ARC600F_INSN_BTST_CC__RC; goto extract_sfmt_tst_cc__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d10020)
+ { itype = ARC600F_INSN_BTST_CCU6_; goto extract_sfmt_tst_ccu6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 210 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d20000)
+ { itype = ARC600F_INSN_BXOR_CC__RA__RC; goto extract_sfmt_and_cc__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d20020)
+ { itype = ARC600F_INSN_BXOR_CCU6__RA_; goto extract_sfmt_and_ccu6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 211 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d30000)
+ { itype = ARC600F_INSN_BMSK_CC__RA__RC; goto extract_sfmt_and_cc__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d30020)
+ { itype = ARC600F_INSN_BMSK_CCU6__RA_; goto extract_sfmt_and_ccu6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 212 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d40000)
+ { itype = ARC600F_INSN_ADD1_CC__RA__RC; goto extract_sfmt_add_cc__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d40020)
+ { itype = ARC600F_INSN_ADD1_CCU6__RA_; goto extract_sfmt_add_ccu6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 213 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d50000)
+ { itype = ARC600F_INSN_ADD2_CC__RA__RC; goto extract_sfmt_add_cc__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d50020)
+ { itype = ARC600F_INSN_ADD2_CCU6__RA_; goto extract_sfmt_add_ccu6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 214 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d60000)
+ { itype = ARC600F_INSN_ADD3_CC__RA__RC; goto extract_sfmt_add_cc__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d60020)
+ { itype = ARC600F_INSN_ADD3_CCU6__RA_; goto extract_sfmt_add_ccu6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 215 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d70000)
+ { itype = ARC600F_INSN_SUB1_CC__RA__RC; goto extract_sfmt_add_cc__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d70020)
+ { itype = ARC600F_INSN_SUB1_CCU6__RA_; goto extract_sfmt_add_ccu6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 216 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d80000)
+ { itype = ARC600F_INSN_SUB2_CC__RA__RC; goto extract_sfmt_add_cc__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d80020)
+ { itype = ARC600F_INSN_SUB2_CCU6__RA_; goto extract_sfmt_add_ccu6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 217 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d90000)
+ { itype = ARC600F_INSN_SUB3_CC__RA__RC; goto extract_sfmt_add_cc__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d90020)
+ { itype = ARC600F_INSN_SUB3_CCU6__RA_; goto extract_sfmt_add_ccu6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 218 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20da0000)
+ { itype = ARC600F_INSN_MPY_CC__RA__RC; goto extract_sfmt_mpy_cc__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20da0020)
+ { itype = ARC600F_INSN_MPY_CCU6__RA_; goto extract_sfmt_mpy_ccu6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 219 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20db0000)
+ { itype = ARC600F_INSN_MPYH_CC__RA__RC; goto extract_sfmt_mpy_cc__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20db0020)
+ { itype = ARC600F_INSN_MPYH_CCU6__RA_; goto extract_sfmt_mpy_ccu6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 220 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20dc0000)
+ { itype = ARC600F_INSN_MPYHU_CC__RA__RC; goto extract_sfmt_mpy_cc__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20dc0020)
+ { itype = ARC600F_INSN_MPYHU_CCU6__RA_; goto extract_sfmt_mpy_ccu6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 221 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20dd0000)
+ { itype = ARC600F_INSN_MPYU_CC__RA__RC; goto extract_sfmt_mpy_cc__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20dd0020)
+ { itype = ARC600F_INSN_MPYU_CCU6__RA_; goto extract_sfmt_mpy_ccu6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 224 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20e00000)
+ { itype = ARC600F_INSN_J_CC___RC_ILINK_; goto extract_sfmt_j_cc___RC_ilink_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20e00020)
+ { itype = ARC600F_INSN_J_CCU6_; goto extract_sfmt_j_ccu6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 225 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20e10000)
+ { itype = ARC600F_INSN_J_CC_D___RC_; goto extract_sfmt_j_cc_d___RC_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20e10020)
+ { itype = ARC600F_INSN_J_CCU6_D_; goto extract_sfmt_j_ccu6_d_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 226 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20e20000)
+ { itype = ARC600F_INSN_JL_CC___RC_NOILINK_; goto extract_sfmt_jl_cc___RC_noilink_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20e20020)
+ { itype = ARC600F_INSN_JL_CCU6_; goto extract_sfmt_jl_ccu6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 227 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20e30000)
+ { itype = ARC600F_INSN_JL_CC_D___RC_; goto extract_sfmt_jl_cc_d___RC_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20e30020)
+ { itype = ARC600F_INSN_JL_CCU6_D_; goto extract_sfmt_jl_ccu6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 232 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20e80020)
+ { itype = ARC600F_INSN_LPCC_CCU6; goto extract_sfmt_lpcc_ccu6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 233 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20e90000)
+ { itype = ARC600F_INSN_FLAG_CC__RC; goto extract_sfmt_flag_cc__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20e90020)
+ { itype = ARC600F_INSN_FLAG_CCU6_; goto extract_sfmt_flag_ccu6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 240 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20f00000)
+ { itype = ARC600F_INSN_LD_AS_ABC; goto extract_sfmt_ld_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 242 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20f20000)
+ { itype = ARC600F_INSN_LDB_AS_ABC; goto extract_sfmt_ldb_as_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 243 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20f30000)
+ { itype = ARC600F_INSN_LDB_AS_X_ABC; goto extract_sfmt_ldb_as_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 244 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC600F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC600F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20f40000)
+ { itype = ARC600F_INSN_LDW_AS_ABC; goto extract_sfmt_ldw_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 245 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC600F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC600F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20f50000)
+ { itype = ARC600F_INSN_LDW_AS_X_ABC; goto extract_sfmt_ldw_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC600F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC600F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 256 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = ARC600F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = ARC600F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28000000)
+ { itype = ARC600F_INSN_ASL_L_R_R__RA__RC; goto extract_sfmt_asl_L_r_r__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 257 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC600F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC600F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC600F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC600F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28010000)
+ { itype = ARC600F_INSN_LSR_L_R_R__RA__RC; goto extract_sfmt_asl_L_r_r__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 258 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = ARC600F_INSN_BL; goto extract_sfmt_bl; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = ARC600F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28020000)
+ { itype = ARC600F_INSN_ASR_L_R_R__RA__RC; goto extract_sfmt_asl_L_r_r__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 259 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC600F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC600F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC600F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC600F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28030000)
+ { itype = ARC600F_INSN_ROR_L_R_R__RA__RC; goto extract_sfmt_asl_L_r_r__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 260 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = ARC600F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = ARC600F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28040000)
+ { itype = ARC600F_INSN_MUL64_L_R_R__RC; goto extract_sfmt_mul64_L_r_r__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 261 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC600F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC600F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC600F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC600F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28050000)
+ { itype = ARC600F_INSN_MULU64_L_R_R__RC; goto extract_sfmt_mul64_L_r_r__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 262 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = ARC600F_INSN_BL; goto extract_sfmt_bl; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = ARC600F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28060000)
+ { itype = ARC600F_INSN_ADDS_L_R_R__RA__RC; goto extract_sfmt_adds_L_r_r__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 263 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC600F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC600F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC600F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC600F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28070000)
+ { itype = ARC600F_INSN_SUBS_L_R_R__RA__RC; goto extract_sfmt_adds_L_r_r__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 264 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = ARC600F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = ARC600F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28080000)
+ { itype = ARC600F_INSN_DIVAW_L_R_R__RA__RC; goto extract_sfmt_divaw_L_r_r__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 265 : /* fall through */
+ case 269 : /* fall through */
+ case 271 : /* fall through */
+ case 273 : /* fall through */
+ case 275 : /* fall through */
+ case 277 : /* fall through */
+ case 279 : /* fall through */
+ case 281 : /* fall through */
+ case 283 : /* fall through */
+ case 285 : /* fall through */
+ case 287 : /* fall through */
+ case 289 : /* fall through */
+ case 291 : /* fall through */
+ case 293 : /* fall through */
+ case 295 : /* fall through */
+ case 299 : /* fall through */
+ case 301 : /* fall through */
+ case 311 : /* fall through */
+ case 313 : /* fall through */
+ case 315 : /* fall through */
+ case 317 : /* fall through */
+ case 319 : /* fall through */
+ case 329 : /* fall through */
+ case 333 : /* fall through */
+ case 335 : /* fall through */
+ case 337 : /* fall through */
+ case 339 : /* fall through */
+ case 341 : /* fall through */
+ case 343 : /* fall through */
+ case 345 : /* fall through */
+ case 347 : /* fall through */
+ case 349 : /* fall through */
+ case 351 : /* fall through */
+ case 353 : /* fall through */
+ case 355 : /* fall through */
+ case 357 : /* fall through */
+ case 359 : /* fall through */
+ case 363 : /* fall through */
+ case 365 : /* fall through */
+ case 375 : /* fall through */
+ case 377 : /* fall through */
+ case 379 : /* fall through */
+ case 381 : /* fall through */
+ case 383 : /* fall through */
+ case 393 : /* fall through */
+ case 397 : /* fall through */
+ case 399 : /* fall through */
+ case 401 : /* fall through */
+ case 403 : /* fall through */
+ case 405 : /* fall through */
+ case 407 : /* fall through */
+ case 409 : /* fall through */
+ case 411 : /* fall through */
+ case 413 : /* fall through */
+ case 415 : /* fall through */
+ case 417 : /* fall through */
+ case 419 : /* fall through */
+ case 421 : /* fall through */
+ case 423 : /* fall through */
+ case 427 : /* fall through */
+ case 429 : /* fall through */
+ case 431 : /* fall through */
+ case 439 : /* fall through */
+ case 441 : /* fall through */
+ case 443 : /* fall through */
+ case 445 : /* fall through */
+ case 447 : /* fall through */
+ case 457 : /* fall through */
+ case 461 : /* fall through */
+ case 463 : /* fall through */
+ case 465 : /* fall through */
+ case 467 : /* fall through */
+ case 469 : /* fall through */
+ case 471 : /* fall through */
+ case 473 : /* fall through */
+ case 475 : /* fall through */
+ case 477 : /* fall through */
+ case 479 : /* fall through */
+ case 481 : /* fall through */
+ case 483 : /* fall through */
+ case 485 : /* fall through */
+ case 487 : /* fall through */
+ case 491 : /* fall through */
+ case 493 : /* fall through */
+ case 495 : /* fall through */
+ case 503 : /* fall through */
+ case 505 : /* fall through */
+ case 507 : /* fall through */
+ case 509 : /* fall through */
+ case 511 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC600F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC600F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC600F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC600F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 266 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = ARC600F_INSN_BL; goto extract_sfmt_bl; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = ARC600F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x280a0000)
+ { itype = ARC600F_INSN_ASLS_L_R_R__RA__RC; goto extract_sfmt_asls_L_r_r__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 267 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC600F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC600F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC600F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC600F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x280b0000)
+ { itype = ARC600F_INSN_ASRS_L_R_R__RA__RC; goto extract_sfmt_asls_L_r_r__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 268 : /* fall through */
+ case 272 : /* fall through */
+ case 276 : /* fall through */
+ case 280 : /* fall through */
+ case 284 : /* fall through */
+ case 288 : /* fall through */
+ case 292 : /* fall through */
+ case 300 : /* fall through */
+ case 308 : /* fall through */
+ case 312 : /* fall through */
+ case 316 : /* fall through */
+ case 332 : /* fall through */
+ case 336 : /* fall through */
+ case 340 : /* fall through */
+ case 344 : /* fall through */
+ case 348 : /* fall through */
+ case 352 : /* fall through */
+ case 356 : /* fall through */
+ case 364 : /* fall through */
+ case 372 : /* fall through */
+ case 376 : /* fall through */
+ case 380 : /* fall through */
+ case 396 : /* fall through */
+ case 400 : /* fall through */
+ case 404 : /* fall through */
+ case 408 : /* fall through */
+ case 412 : /* fall through */
+ case 416 : /* fall through */
+ case 420 : /* fall through */
+ case 428 : /* fall through */
+ case 436 : /* fall through */
+ case 440 : /* fall through */
+ case 444 : /* fall through */
+ case 460 : /* fall through */
+ case 464 : /* fall through */
+ case 468 : /* fall through */
+ case 472 : /* fall through */
+ case 476 : /* fall through */
+ case 480 : /* fall through */
+ case 484 : /* fall through */
+ case 492 : /* fall through */
+ case 500 : /* fall through */
+ case 504 : /* fall through */
+ case 508 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = ARC600F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = ARC600F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 270 : /* fall through */
+ case 274 : /* fall through */
+ case 278 : /* fall through */
+ case 282 : /* fall through */
+ case 286 : /* fall through */
+ case 290 : /* fall through */
+ case 294 : /* fall through */
+ case 298 : /* fall through */
+ case 302 : /* fall through */
+ case 306 : /* fall through */
+ case 314 : /* fall through */
+ case 318 : /* fall through */
+ case 334 : /* fall through */
+ case 338 : /* fall through */
+ case 342 : /* fall through */
+ case 346 : /* fall through */
+ case 350 : /* fall through */
+ case 354 : /* fall through */
+ case 358 : /* fall through */
+ case 362 : /* fall through */
+ case 366 : /* fall through */
+ case 370 : /* fall through */
+ case 378 : /* fall through */
+ case 382 : /* fall through */
+ case 398 : /* fall through */
+ case 402 : /* fall through */
+ case 406 : /* fall through */
+ case 410 : /* fall through */
+ case 414 : /* fall through */
+ case 418 : /* fall through */
+ case 422 : /* fall through */
+ case 426 : /* fall through */
+ case 430 : /* fall through */
+ case 434 : /* fall through */
+ case 442 : /* fall through */
+ case 446 : /* fall through */
+ case 462 : /* fall through */
+ case 466 : /* fall through */
+ case 470 : /* fall through */
+ case 474 : /* fall through */
+ case 478 : /* fall through */
+ case 482 : /* fall through */
+ case 486 : /* fall through */
+ case 490 : /* fall through */
+ case 494 : /* fall through */
+ case 498 : /* fall through */
+ case 506 : /* fall through */
+ case 510 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = ARC600F_INSN_BL; goto extract_sfmt_bl; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = ARC600F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 296 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = ARC600F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = ARC600F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28280000)
+ { itype = ARC600F_INSN_ADDSDW_L_R_R__RA__RC; goto extract_sfmt_asls_L_r_r__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 297 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC600F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC600F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC600F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC600F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28290000)
+ { itype = ARC600F_INSN_SUBSDW_L_R_R__RA__RC; goto extract_sfmt_asls_L_r_r__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 303 :
+ {
+ unsigned int val = (((insn >> 25) & (1 << 6)) | ((insn >> 24) & (1 << 5)) | ((insn >> 1) & (3 << 3)) | ((insn >> 0) & (7 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC600F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC600F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 16 : /* fall through */
+ case 17 : /* fall through */
+ case 18 : /* fall through */
+ case 19 : /* fall through */
+ case 20 : /* fall through */
+ case 21 : /* fall through */
+ case 22 : /* fall through */
+ case 23 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC600F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 24 : /* fall through */
+ case 25 : /* fall through */
+ case 26 : /* fall through */
+ case 27 : /* fall through */
+ case 28 : /* fall through */
+ case 29 : /* fall through */
+ case 30 : /* fall through */
+ case 31 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC600F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 32 :
+ {
+ unsigned int val = (((insn >> 3) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x282f0000)
+ { itype = ARC600F_INSN_SWAP_L_R_R__RC; goto extract_sfmt_swap_L_r_r__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8ff003f) == 0x282f0008)
+ { itype = ARC600F_INSN_NORMW_L_R_R__RC; goto extract_sfmt_swap_L_r_r__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 33 :
+ if ((entire_insn & 0xf8ff003f) == 0x282f0001)
+ { itype = ARC600F_INSN_NORM_L_R_R__RC; goto extract_sfmt_swap_L_r_r__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 35 :
+ if ((entire_insn & 0xf8ff003f) == 0x282f0003)
+ { itype = ARC600F_INSN_RND16_L_R_R__RC; goto extract_sfmt_rnd16_L_r_r__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 36 :
+ if ((entire_insn & 0xf8ff003f) == 0x282f0004)
+ { itype = ARC600F_INSN_ABSSW_L_R_R__RC; goto extract_sfmt_abssw_L_r_r__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 37 :
+ if ((entire_insn & 0xf8ff003f) == 0x282f0005)
+ { itype = ARC600F_INSN_ABSS_L_R_R__RC; goto extract_sfmt_rnd16_L_r_r__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 38 :
+ if ((entire_insn & 0xf8ff003f) == 0x282f0006)
+ { itype = ARC600F_INSN_NEGSW_L_R_R__RC; goto extract_sfmt_abssw_L_r_r__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 39 :
+ if ((entire_insn & 0xf8ff003f) == 0x282f0007)
+ { itype = ARC600F_INSN_NEGS_L_R_R__RC; goto extract_sfmt_rnd16_L_r_r__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 64 : /* fall through */
+ case 65 : /* fall through */
+ case 66 : /* fall through */
+ case 67 : /* fall through */
+ case 68 : /* fall through */
+ case 69 : /* fall through */
+ case 70 : /* fall through */
+ case 71 : /* fall through */
+ case 72 : /* fall through */
+ case 73 : /* fall through */
+ case 74 : /* fall through */
+ case 75 : /* fall through */
+ case 76 : /* fall through */
+ case 77 : /* fall through */
+ case 78 : /* fall through */
+ case 79 : /* fall through */
+ case 80 : /* fall through */
+ case 81 : /* fall through */
+ case 82 : /* fall through */
+ case 83 : /* fall through */
+ case 84 : /* fall through */
+ case 85 : /* fall through */
+ case 86 : /* fall through */
+ case 87 : /* fall through */
+ case 88 : /* fall through */
+ case 89 : /* fall through */
+ case 90 : /* fall through */
+ case 91 : /* fall through */
+ case 92 : /* fall through */
+ case 93 : /* fall through */
+ case 94 : /* fall through */
+ case 95 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 96 : /* fall through */
+ case 97 : /* fall through */
+ case 98 : /* fall through */
+ case 99 : /* fall through */
+ case 100 : /* fall through */
+ case 101 : /* fall through */
+ case 102 : /* fall through */
+ case 103 : /* fall through */
+ case 104 : /* fall through */
+ case 105 : /* fall through */
+ case 106 : /* fall through */
+ case 107 : /* fall through */
+ case 108 : /* fall through */
+ case 109 : /* fall through */
+ case 110 : /* fall through */
+ case 111 : /* fall through */
+ case 112 : /* fall through */
+ case 113 : /* fall through */
+ case 114 : /* fall through */
+ case 115 : /* fall through */
+ case 116 : /* fall through */
+ case 117 : /* fall through */
+ case 118 : /* fall through */
+ case 119 : /* fall through */
+ case 120 : /* fall through */
+ case 121 : /* fall through */
+ case 122 : /* fall through */
+ case 123 : /* fall through */
+ case 124 : /* fall through */
+ case 125 : /* fall through */
+ case 126 : /* fall through */
+ case 127 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 304 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = ARC600F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = ARC600F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28300000)
+ { itype = ARC600F_INSN_MULULW_L_R_R__RA__RC; goto extract_sfmt_mullw_L_r_r__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 305 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC600F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC600F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC600F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC600F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28310000)
+ { itype = ARC600F_INSN_MULLW_L_R_R__RA__RC; goto extract_sfmt_mullw_L_r_r__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 307 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC600F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC600F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC600F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC600F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28330000)
+ { itype = ARC600F_INSN_MACLW_L_R_R__RA__RC; goto extract_sfmt_maclw_L_r_r__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 309 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC600F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC600F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC600F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC600F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28350000)
+ { itype = ARC600F_INSN_MACHULW_L_R_R__RA__RC; goto extract_sfmt_machulw_L_r_r__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 310 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = ARC600F_INSN_BL; goto extract_sfmt_bl; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = ARC600F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28360000)
+ { itype = ARC600F_INSN_MACHLW_L_R_R__RA__RC; goto extract_sfmt_maclw_L_r_r__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 320 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = ARC600F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = ARC600F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28400000)
+ { itype = ARC600F_INSN_ASL_L_U6__RA_; goto extract_sfmt_asl_L_u6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 321 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC600F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC600F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC600F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC600F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28410000)
+ { itype = ARC600F_INSN_LSR_L_U6__RA_; goto extract_sfmt_asl_L_u6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 322 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = ARC600F_INSN_BL; goto extract_sfmt_bl; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = ARC600F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28420000)
+ { itype = ARC600F_INSN_ASR_L_U6__RA_; goto extract_sfmt_asl_L_u6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 323 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC600F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC600F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC600F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC600F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28430000)
+ { itype = ARC600F_INSN_ROR_L_U6__RA_; goto extract_sfmt_asl_L_u6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 324 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = ARC600F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = ARC600F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28440000)
+ { itype = ARC600F_INSN_MUL64_L_U6_; goto extract_sfmt_mul64_L_u6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 325 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC600F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC600F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC600F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC600F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28450000)
+ { itype = ARC600F_INSN_MULU64_L_U6_; goto extract_sfmt_mul64_L_u6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 326 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = ARC600F_INSN_BL; goto extract_sfmt_bl; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = ARC600F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28460000)
+ { itype = ARC600F_INSN_ADDS_L_U6__RA_; goto extract_sfmt_adds_L_u6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 327 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC600F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC600F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC600F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC600F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28470000)
+ { itype = ARC600F_INSN_SUBS_L_U6__RA_; goto extract_sfmt_adds_L_u6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 328 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = ARC600F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = ARC600F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28480000)
+ { itype = ARC600F_INSN_DIVAW_L_U6__RA_; goto extract_sfmt_divaw_L_u6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 330 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = ARC600F_INSN_BL; goto extract_sfmt_bl; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = ARC600F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x284a0000)
+ { itype = ARC600F_INSN_ASLS_L_U6__RA_; goto extract_sfmt_asls_L_u6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 331 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC600F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC600F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC600F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC600F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x284b0000)
+ { itype = ARC600F_INSN_ASRS_L_U6__RA_; goto extract_sfmt_asls_L_u6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 360 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = ARC600F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = ARC600F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28680000)
+ { itype = ARC600F_INSN_ADDSDW_L_U6__RA_; goto extract_sfmt_asls_L_u6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 361 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC600F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC600F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC600F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC600F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28690000)
+ { itype = ARC600F_INSN_SUBSDW_L_U6__RA_; goto extract_sfmt_asls_L_u6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 367 :
+ {
+ unsigned int val = (((insn >> 25) & (1 << 6)) | ((insn >> 24) & (1 << 5)) | ((insn >> 1) & (3 << 3)) | ((insn >> 0) & (7 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC600F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC600F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 16 : /* fall through */
+ case 17 : /* fall through */
+ case 18 : /* fall through */
+ case 19 : /* fall through */
+ case 20 : /* fall through */
+ case 21 : /* fall through */
+ case 22 : /* fall through */
+ case 23 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC600F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 24 : /* fall through */
+ case 25 : /* fall through */
+ case 26 : /* fall through */
+ case 27 : /* fall through */
+ case 28 : /* fall through */
+ case 29 : /* fall through */
+ case 30 : /* fall through */
+ case 31 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC600F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 32 :
+ {
+ unsigned int val = (((insn >> 3) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x286f0000)
+ { itype = ARC600F_INSN_SWAP_L_U6_; goto extract_sfmt_swap_L_u6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8ff003f) == 0x286f0008)
+ { itype = ARC600F_INSN_NORMW_L_U6_; goto extract_sfmt_swap_L_u6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 33 :
+ if ((entire_insn & 0xf8ff003f) == 0x286f0001)
+ { itype = ARC600F_INSN_NORM_L_U6_; goto extract_sfmt_norm_L_u6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 35 :
+ if ((entire_insn & 0xf8ff003f) == 0x286f0003)
+ { itype = ARC600F_INSN_RND16_L_U6_; goto extract_sfmt_rnd16_L_u6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 36 :
+ if ((entire_insn & 0xf8ff003f) == 0x286f0004)
+ { itype = ARC600F_INSN_ABSSW_L_U6_; goto extract_sfmt_abssw_L_u6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 37 :
+ if ((entire_insn & 0xf8ff003f) == 0x286f0005)
+ { itype = ARC600F_INSN_ABSS_L_U6_; goto extract_sfmt_abss_L_u6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 38 :
+ if ((entire_insn & 0xf8ff003f) == 0x286f0006)
+ { itype = ARC600F_INSN_NEGSW_L_U6_; goto extract_sfmt_abssw_L_u6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 39 :
+ if ((entire_insn & 0xf8ff003f) == 0x286f0007)
+ { itype = ARC600F_INSN_NEGS_L_U6_; goto extract_sfmt_rnd16_L_u6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 64 : /* fall through */
+ case 65 : /* fall through */
+ case 66 : /* fall through */
+ case 67 : /* fall through */
+ case 68 : /* fall through */
+ case 69 : /* fall through */
+ case 70 : /* fall through */
+ case 71 : /* fall through */
+ case 72 : /* fall through */
+ case 73 : /* fall through */
+ case 74 : /* fall through */
+ case 75 : /* fall through */
+ case 76 : /* fall through */
+ case 77 : /* fall through */
+ case 78 : /* fall through */
+ case 79 : /* fall through */
+ case 80 : /* fall through */
+ case 81 : /* fall through */
+ case 82 : /* fall through */
+ case 83 : /* fall through */
+ case 84 : /* fall through */
+ case 85 : /* fall through */
+ case 86 : /* fall through */
+ case 87 : /* fall through */
+ case 88 : /* fall through */
+ case 89 : /* fall through */
+ case 90 : /* fall through */
+ case 91 : /* fall through */
+ case 92 : /* fall through */
+ case 93 : /* fall through */
+ case 94 : /* fall through */
+ case 95 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 96 : /* fall through */
+ case 97 : /* fall through */
+ case 98 : /* fall through */
+ case 99 : /* fall through */
+ case 100 : /* fall through */
+ case 101 : /* fall through */
+ case 102 : /* fall through */
+ case 103 : /* fall through */
+ case 104 : /* fall through */
+ case 105 : /* fall through */
+ case 106 : /* fall through */
+ case 107 : /* fall through */
+ case 108 : /* fall through */
+ case 109 : /* fall through */
+ case 110 : /* fall through */
+ case 111 : /* fall through */
+ case 112 : /* fall through */
+ case 113 : /* fall through */
+ case 114 : /* fall through */
+ case 115 : /* fall through */
+ case 116 : /* fall through */
+ case 117 : /* fall through */
+ case 118 : /* fall through */
+ case 119 : /* fall through */
+ case 120 : /* fall through */
+ case 121 : /* fall through */
+ case 122 : /* fall through */
+ case 123 : /* fall through */
+ case 124 : /* fall through */
+ case 125 : /* fall through */
+ case 126 : /* fall through */
+ case 127 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 368 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = ARC600F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = ARC600F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28700000)
+ { itype = ARC600F_INSN_MULULW_L_U6__RA_; goto extract_sfmt_mullw_L_u6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 369 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC600F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC600F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC600F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC600F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28710000)
+ { itype = ARC600F_INSN_MULLW_L_U6__RA_; goto extract_sfmt_mullw_L_u6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 371 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC600F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC600F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC600F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC600F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28730000)
+ { itype = ARC600F_INSN_MACLW_L_U6__RA_; goto extract_sfmt_maclw_L_u6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 373 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC600F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC600F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC600F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC600F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28750000)
+ { itype = ARC600F_INSN_MACHULW_L_U6__RA_; goto extract_sfmt_machulw_L_u6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 374 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = ARC600F_INSN_BL; goto extract_sfmt_bl; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = ARC600F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28760000)
+ { itype = ARC600F_INSN_MACHLW_L_U6__RA_; goto extract_sfmt_maclw_L_u6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 384 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = ARC600F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = ARC600F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28800000)
+ { itype = ARC600F_INSN_ASL_L_S12__RA_; goto extract_sfmt_asl_L_s12__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 385 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC600F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC600F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC600F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC600F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28810000)
+ { itype = ARC600F_INSN_LSR_L_S12__RA_; goto extract_sfmt_asl_L_s12__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 386 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = ARC600F_INSN_BL; goto extract_sfmt_bl; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = ARC600F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28820000)
+ { itype = ARC600F_INSN_ASR_L_S12__RA_; goto extract_sfmt_asl_L_s12__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 387 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC600F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC600F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC600F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC600F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28830000)
+ { itype = ARC600F_INSN_ROR_L_S12__RA_; goto extract_sfmt_asl_L_s12__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 388 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = ARC600F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = ARC600F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28840000)
+ { itype = ARC600F_INSN_MUL64_L_S12_; goto extract_sfmt_mul64_L_s12_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 389 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC600F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC600F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC600F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC600F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28850000)
+ { itype = ARC600F_INSN_MULU64_L_S12_; goto extract_sfmt_mul64_L_s12_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 390 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = ARC600F_INSN_BL; goto extract_sfmt_bl; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = ARC600F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28860000)
+ { itype = ARC600F_INSN_ADDS_L_S12__RA_; goto extract_sfmt_adds_L_s12__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 391 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC600F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC600F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC600F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC600F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28870000)
+ { itype = ARC600F_INSN_SUBS_L_S12__RA_; goto extract_sfmt_adds_L_s12__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 392 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = ARC600F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = ARC600F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28880000)
+ { itype = ARC600F_INSN_DIVAW_L_S12__RA_; goto extract_sfmt_divaw_L_s12__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 394 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = ARC600F_INSN_BL; goto extract_sfmt_bl; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = ARC600F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x288a0000)
+ { itype = ARC600F_INSN_ASLS_L_S12__RA_; goto extract_sfmt_asls_L_s12__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 395 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC600F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC600F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC600F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC600F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x288b0000)
+ { itype = ARC600F_INSN_ASRS_L_S12__RA_; goto extract_sfmt_asls_L_s12__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 424 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = ARC600F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = ARC600F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28a80000)
+ { itype = ARC600F_INSN_ADDSDW_L_S12__RA_; goto extract_sfmt_asls_L_s12__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 425 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC600F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC600F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC600F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC600F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28a90000)
+ { itype = ARC600F_INSN_SUBSDW_L_S12__RA_; goto extract_sfmt_asls_L_s12__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 432 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = ARC600F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = ARC600F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28b00000)
+ { itype = ARC600F_INSN_MULULW_L_S12__RA_; goto extract_sfmt_mullw_L_s12__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 433 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC600F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC600F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC600F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC600F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28b10000)
+ { itype = ARC600F_INSN_MULLW_L_S12__RA_; goto extract_sfmt_mullw_L_s12__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 435 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC600F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC600F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC600F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC600F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28b30000)
+ { itype = ARC600F_INSN_MACLW_L_S12__RA_; goto extract_sfmt_maclw_L_s12__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 437 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC600F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC600F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC600F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC600F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28b50000)
+ { itype = ARC600F_INSN_MACHULW_L_S12__RA_; goto extract_sfmt_machulw_L_s12__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 438 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = ARC600F_INSN_BL; goto extract_sfmt_bl; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = ARC600F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28b60000)
+ { itype = ARC600F_INSN_MACHLW_L_S12__RA_; goto extract_sfmt_maclw_L_s12__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 448 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = ARC600F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = ARC600F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c00000)
+ { itype = ARC600F_INSN_ASL_CC__RA__RC; goto extract_sfmt_asl_cc__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c00020)
+ { itype = ARC600F_INSN_ASL_CCU6__RA_; goto extract_sfmt_asl_ccu6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 449 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC600F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC600F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC600F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC600F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c10000)
+ { itype = ARC600F_INSN_LSR_CC__RA__RC; goto extract_sfmt_asl_cc__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c10020)
+ { itype = ARC600F_INSN_LSR_CCU6__RA_; goto extract_sfmt_asl_ccu6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 450 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = ARC600F_INSN_BL; goto extract_sfmt_bl; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = ARC600F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c20000)
+ { itype = ARC600F_INSN_ASR_CC__RA__RC; goto extract_sfmt_asl_cc__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c20020)
+ { itype = ARC600F_INSN_ASR_CCU6__RA_; goto extract_sfmt_asl_ccu6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 451 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC600F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC600F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC600F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC600F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c30000)
+ { itype = ARC600F_INSN_ROR_CC__RA__RC; goto extract_sfmt_asl_cc__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c30020)
+ { itype = ARC600F_INSN_ROR_CCU6__RA_; goto extract_sfmt_asl_ccu6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 452 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = ARC600F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = ARC600F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c40000)
+ { itype = ARC600F_INSN_MUL64_CC__RC; goto extract_sfmt_mul64_cc__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c40020)
+ { itype = ARC600F_INSN_MUL64_CCU6_; goto extract_sfmt_mul64_ccu6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 453 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC600F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC600F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC600F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC600F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c50000)
+ { itype = ARC600F_INSN_MULU64_CC__RC; goto extract_sfmt_mul64_cc__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c50020)
+ { itype = ARC600F_INSN_MULU64_CCU6_; goto extract_sfmt_mul64_ccu6_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 454 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = ARC600F_INSN_BL; goto extract_sfmt_bl; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = ARC600F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c60000)
+ { itype = ARC600F_INSN_ADDS_CC__RA__RC; goto extract_sfmt_adds_cc__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c60020)
+ { itype = ARC600F_INSN_ADDS_CCU6__RA_; goto extract_sfmt_adds_ccu6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 455 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC600F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC600F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC600F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC600F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c70000)
+ { itype = ARC600F_INSN_SUBS_CC__RA__RC; goto extract_sfmt_adds_cc__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c70020)
+ { itype = ARC600F_INSN_SUBS_CCU6__RA_; goto extract_sfmt_adds_ccu6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 456 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = ARC600F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = ARC600F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c80000)
+ { itype = ARC600F_INSN_DIVAW_CC__RA__RC; goto extract_sfmt_divaw_cc__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c80020)
+ { itype = ARC600F_INSN_DIVAW_CCU6__RA_; goto extract_sfmt_divaw_ccu6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 458 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = ARC600F_INSN_BL; goto extract_sfmt_bl; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = ARC600F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x28ca0000)
+ { itype = ARC600F_INSN_ASLS_CC__RA__RC; goto extract_sfmt_asls_cc__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x28ca0020)
+ { itype = ARC600F_INSN_ASLS_CCU6__RA_; goto extract_sfmt_asls_ccu6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 459 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC600F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC600F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC600F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC600F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8ff0020) == 0x28cb0000)
+ { itype = ARC600F_INSN_ASRS_CC__RA__RC; goto extract_sfmt_asls_cc__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0020) == 0x28cb0020)
+ { itype = ARC600F_INSN_ASRS_CCU6__RA_; goto extract_sfmt_asls_ccu6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 488 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = ARC600F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = ARC600F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x28e80000)
+ { itype = ARC600F_INSN_ADDSDW_CC__RA__RC; goto extract_sfmt_asls_cc__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x28e80020)
+ { itype = ARC600F_INSN_ADDSDW_CCU6__RA_; goto extract_sfmt_asls_ccu6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 489 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC600F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC600F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC600F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC600F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8ff0020) == 0x28e90000)
+ { itype = ARC600F_INSN_SUBSDW_CC__RA__RC; goto extract_sfmt_asls_cc__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0020) == 0x28e90020)
+ { itype = ARC600F_INSN_SUBSDW_CCU6__RA_; goto extract_sfmt_asls_ccu6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 496 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = ARC600F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = ARC600F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x28f00000)
+ { itype = ARC600F_INSN_MULULW_CC__RA__RC; goto extract_sfmt_mullw_cc__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x28f00020)
+ { itype = ARC600F_INSN_MULULW_CCU6__RA_; goto extract_sfmt_mullw_ccu6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 497 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC600F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC600F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC600F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC600F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8ff0020) == 0x28f10000)
+ { itype = ARC600F_INSN_MULLW_CC__RA__RC; goto extract_sfmt_mullw_cc__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0020) == 0x28f10020)
+ { itype = ARC600F_INSN_MULLW_CCU6__RA_; goto extract_sfmt_mullw_ccu6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 499 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC600F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC600F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC600F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC600F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8ff0020) == 0x28f30000)
+ { itype = ARC600F_INSN_MACLW_CC__RA__RC; goto extract_sfmt_maclw_cc__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0020) == 0x28f30020)
+ { itype = ARC600F_INSN_MACLW_CCU6__RA_; goto extract_sfmt_maclw_ccu6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 501 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC600F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC600F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC600F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC600F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8ff0020) == 0x28f50000)
+ { itype = ARC600F_INSN_MACHULW_CC__RA__RC; goto extract_sfmt_machulw_cc__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0020) == 0x28f50020)
+ { itype = ARC600F_INSN_MACHULW_CCU6__RA_; goto extract_sfmt_machulw_ccu6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 502 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = ARC600F_INSN_BL; goto extract_sfmt_bl; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = ARC600F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x28f60000)
+ { itype = ARC600F_INSN_MACHLW_CC__RA__RC; goto extract_sfmt_maclw_cc__RA__RC; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x28f60020)
+ { itype = ARC600F_INSN_MACHLW_CCU6__RA_; goto extract_sfmt_maclw_ccu6__RA_; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC600F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC600F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 512 : /* fall through */
+ case 513 : /* fall through */
+ case 514 : /* fall through */
+ case 515 : /* fall through */
+ case 516 : /* fall through */
+ case 517 : /* fall through */
+ case 518 : /* fall through */
+ case 519 : /* fall through */
+ case 520 : /* fall through */
+ case 521 : /* fall through */
+ case 522 : /* fall through */
+ case 523 : /* fall through */
+ case 524 : /* fall through */
+ case 525 : /* fall through */
+ case 526 : /* fall through */
+ case 527 : /* fall through */
+ case 528 : /* fall through */
+ case 529 : /* fall through */
+ case 530 : /* fall through */
+ case 531 : /* fall through */
+ case 532 : /* fall through */
+ case 533 : /* fall through */
+ case 534 : /* fall through */
+ case 535 : /* fall through */
+ case 536 : /* fall through */
+ case 537 : /* fall through */
+ case 538 : /* fall through */
+ case 539 : /* fall through */
+ case 540 : /* fall through */
+ case 541 : /* fall through */
+ case 542 : /* fall through */
+ case 543 : /* fall through */
+ case 544 : /* fall through */
+ case 545 : /* fall through */
+ case 546 : /* fall through */
+ case 547 : /* fall through */
+ case 548 : /* fall through */
+ case 549 : /* fall through */
+ case 550 : /* fall through */
+ case 551 : /* fall through */
+ case 552 : /* fall through */
+ case 553 : /* fall through */
+ case 554 : /* fall through */
+ case 555 : /* fall through */
+ case 556 : /* fall through */
+ case 557 : /* fall through */
+ case 558 : /* fall through */
+ case 559 : /* fall through */
+ case 560 : /* fall through */
+ case 561 : /* fall through */
+ case 562 : /* fall through */
+ case 563 : /* fall through */
+ case 564 : /* fall through */
+ case 565 : /* fall through */
+ case 566 : /* fall through */
+ case 567 : /* fall through */
+ case 568 : /* fall through */
+ case 569 : /* fall through */
+ case 570 : /* fall through */
+ case 571 : /* fall through */
+ case 572 : /* fall through */
+ case 573 : /* fall through */
+ case 574 : /* fall through */
+ case 575 : /* fall through */
+ case 576 : /* fall through */
+ case 577 : /* fall through */
+ case 578 : /* fall through */
+ case 579 : /* fall through */
+ case 580 : /* fall through */
+ case 581 : /* fall through */
+ case 582 : /* fall through */
+ case 583 : /* fall through */
+ case 584 : /* fall through */
+ case 585 : /* fall through */
+ case 586 : /* fall through */
+ case 587 : /* fall through */
+ case 588 : /* fall through */
+ case 589 : /* fall through */
+ case 590 : /* fall through */
+ case 591 : /* fall through */
+ case 592 : /* fall through */
+ case 593 : /* fall through */
+ case 594 : /* fall through */
+ case 595 : /* fall through */
+ case 596 : /* fall through */
+ case 597 : /* fall through */
+ case 598 : /* fall through */
+ case 599 : /* fall through */
+ case 600 : /* fall through */
+ case 601 : /* fall through */
+ case 602 : /* fall through */
+ case 603 : /* fall through */
+ case 604 : /* fall through */
+ case 605 : /* fall through */
+ case 606 : /* fall through */
+ case 607 : /* fall through */
+ case 608 : /* fall through */
+ case 609 : /* fall through */
+ case 610 : /* fall through */
+ case 611 : /* fall through */
+ case 612 : /* fall through */
+ case 613 : /* fall through */
+ case 614 : /* fall through */
+ case 615 : /* fall through */
+ case 616 : /* fall through */
+ case 617 : /* fall through */
+ case 618 : /* fall through */
+ case 619 : /* fall through */
+ case 620 : /* fall through */
+ case 621 : /* fall through */
+ case 622 : /* fall through */
+ case 623 : /* fall through */
+ case 624 : /* fall through */
+ case 625 : /* fall through */
+ case 626 : /* fall through */
+ case 627 : /* fall through */
+ case 628 : /* fall through */
+ case 629 : /* fall through */
+ case 630 : /* fall through */
+ case 631 : /* fall through */
+ case 632 : /* fall through */
+ case 633 : /* fall through */
+ case 634 : /* fall through */
+ case 635 : /* fall through */
+ case 636 : /* fall through */
+ case 637 : /* fall through */
+ case 638 : /* fall through */
+ case 639 : /* fall through */
+ case 640 : /* fall through */
+ case 641 : /* fall through */
+ case 642 : /* fall through */
+ case 643 : /* fall through */
+ case 644 : /* fall through */
+ case 645 : /* fall through */
+ case 646 : /* fall through */
+ case 647 : /* fall through */
+ case 648 : /* fall through */
+ case 649 : /* fall through */
+ case 650 : /* fall through */
+ case 651 : /* fall through */
+ case 652 : /* fall through */
+ case 653 : /* fall through */
+ case 654 : /* fall through */
+ case 655 : /* fall through */
+ case 656 : /* fall through */
+ case 657 : /* fall through */
+ case 658 : /* fall through */
+ case 659 : /* fall through */
+ case 660 : /* fall through */
+ case 661 : /* fall through */
+ case 662 : /* fall through */
+ case 663 : /* fall through */
+ case 664 : /* fall through */
+ case 665 : /* fall through */
+ case 666 : /* fall through */
+ case 667 : /* fall through */
+ case 668 : /* fall through */
+ case 669 : /* fall through */
+ case 670 : /* fall through */
+ case 671 : /* fall through */
+ case 672 : /* fall through */
+ case 673 : /* fall through */
+ case 674 : /* fall through */
+ case 675 : /* fall through */
+ case 676 : /* fall through */
+ case 677 : /* fall through */
+ case 678 : /* fall through */
+ case 679 : /* fall through */
+ case 680 : /* fall through */
+ case 681 : /* fall through */
+ case 682 : /* fall through */
+ case 683 : /* fall through */
+ case 684 : /* fall through */
+ case 685 : /* fall through */
+ case 686 : /* fall through */
+ case 687 : /* fall through */
+ case 688 : /* fall through */
+ case 689 : /* fall through */
+ case 690 : /* fall through */
+ case 691 : /* fall through */
+ case 692 : /* fall through */
+ case 693 : /* fall through */
+ case 694 : /* fall through */
+ case 695 : /* fall through */
+ case 696 : /* fall through */
+ case 697 : /* fall through */
+ case 698 : /* fall through */
+ case 699 : /* fall through */
+ case 700 : /* fall through */
+ case 701 : /* fall through */
+ case 702 : /* fall through */
+ case 703 : /* fall through */
+ case 704 : /* fall through */
+ case 705 : /* fall through */
+ case 706 : /* fall through */
+ case 707 : /* fall through */
+ case 708 : /* fall through */
+ case 709 : /* fall through */
+ case 710 : /* fall through */
+ case 711 : /* fall through */
+ case 712 : /* fall through */
+ case 713 : /* fall through */
+ case 714 : /* fall through */
+ case 715 : /* fall through */
+ case 716 : /* fall through */
+ case 717 : /* fall through */
+ case 718 : /* fall through */
+ case 719 : /* fall through */
+ case 720 : /* fall through */
+ case 721 : /* fall through */
+ case 722 : /* fall through */
+ case 723 : /* fall through */
+ case 724 : /* fall through */
+ case 725 : /* fall through */
+ case 726 : /* fall through */
+ case 727 : /* fall through */
+ case 728 : /* fall through */
+ case 729 : /* fall through */
+ case 730 : /* fall through */
+ case 731 : /* fall through */
+ case 732 : /* fall through */
+ case 733 : /* fall through */
+ case 734 : /* fall through */
+ case 735 : /* fall through */
+ case 736 : /* fall through */
+ case 737 : /* fall through */
+ case 738 : /* fall through */
+ case 739 : /* fall through */
+ case 740 : /* fall through */
+ case 741 : /* fall through */
+ case 742 : /* fall through */
+ case 743 : /* fall through */
+ case 744 : /* fall through */
+ case 745 : /* fall through */
+ case 746 : /* fall through */
+ case 747 : /* fall through */
+ case 748 : /* fall through */
+ case 749 : /* fall through */
+ case 750 : /* fall through */
+ case 751 : /* fall through */
+ case 752 : /* fall through */
+ case 753 : /* fall through */
+ case 754 : /* fall through */
+ case 755 : /* fall through */
+ case 756 : /* fall through */
+ case 757 : /* fall through */
+ case 758 : /* fall through */
+ case 759 : /* fall through */
+ case 760 : /* fall through */
+ case 761 : /* fall through */
+ case 762 : /* fall through */
+ case 763 : /* fall through */
+ case 764 : /* fall through */
+ case 765 : /* fall through */
+ case 766 : /* fall through */
+ case 767 :
+ {
+ unsigned int val = (((insn >> 25) & (1 << 6)) | ((insn >> 24) & (1 << 5)) | ((insn >> 6) & (31 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf80007c0) == 0x10000000)
+ { itype = ARC600F_INSN_LD_ABS; goto extract_sfmt_ld_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf80007c0) == 0x10000080)
+ { itype = ARC600F_INSN_LDB_ABS; goto extract_sfmt_ldb_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf80007c0) == 0x100000c0)
+ { itype = ARC600F_INSN_LDB_X_ABS; goto extract_sfmt_ldb_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xf80007c0) == 0x10000100)
+ { itype = ARC600F_INSN_LDW_ABS; goto extract_sfmt_ldw_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xf80007c0) == 0x10000140)
+ { itype = ARC600F_INSN_LDW_X_ABS; goto extract_sfmt_ldw_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 :
+ if ((entire_insn & 0xf80007c0) == 0x10000200)
+ { itype = ARC600F_INSN_LD__AW_ABS; goto extract_sfmt_ld__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 10 :
+ if ((entire_insn & 0xf80007c0) == 0x10000280)
+ { itype = ARC600F_INSN_LDB__AW_ABS; goto extract_sfmt_ldb__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 11 :
+ if ((entire_insn & 0xf80007c0) == 0x100002c0)
+ { itype = ARC600F_INSN_LDB__AW_X_ABS; goto extract_sfmt_ldb__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 :
+ if ((entire_insn & 0xf80007c0) == 0x10000300)
+ { itype = ARC600F_INSN_LDW__AW_ABS; goto extract_sfmt_ldw__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 13 :
+ if ((entire_insn & 0xf80007c0) == 0x10000340)
+ { itype = ARC600F_INSN_LDW__AW_X_ABS; goto extract_sfmt_ldw__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 16 :
+ if ((entire_insn & 0xf80007c0) == 0x10000400)
+ { itype = ARC600F_INSN_LD_AB_ABS; goto extract_sfmt_ld__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 18 :
+ if ((entire_insn & 0xf80007c0) == 0x10000480)
+ { itype = ARC600F_INSN_LDB_AB_ABS; goto extract_sfmt_ldb__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 19 :
+ if ((entire_insn & 0xf80007c0) == 0x100004c0)
+ { itype = ARC600F_INSN_LDB_AB_X_ABS; goto extract_sfmt_ldb__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 20 :
+ if ((entire_insn & 0xf80007c0) == 0x10000500)
+ { itype = ARC600F_INSN_LDW_AB_ABS; goto extract_sfmt_ldw__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 21 :
+ if ((entire_insn & 0xf80007c0) == 0x10000540)
+ { itype = ARC600F_INSN_LDW_AB_X_ABS; goto extract_sfmt_ldw__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 24 :
+ if ((entire_insn & 0xf80007c0) == 0x10000600)
+ { itype = ARC600F_INSN_LD_AS_ABS; goto extract_sfmt_ld_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 26 :
+ if ((entire_insn & 0xf80007c0) == 0x10000680)
+ { itype = ARC600F_INSN_LDB_AS_ABS; goto extract_sfmt_ldb_as_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 27 :
+ if ((entire_insn & 0xf80007c0) == 0x100006c0)
+ { itype = ARC600F_INSN_LDB_AS_X_ABS; goto extract_sfmt_ldb_as_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 28 :
+ if ((entire_insn & 0xf80007c0) == 0x10000700)
+ { itype = ARC600F_INSN_LDW_AS_ABS; goto extract_sfmt_ldw_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 29 :
+ if ((entire_insn & 0xf80007c0) == 0x10000740)
+ { itype = ARC600F_INSN_LDW_AS_X_ABS; goto extract_sfmt_ldw_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 64 : /* fall through */
+ case 65 : /* fall through */
+ case 66 : /* fall through */
+ case 67 : /* fall through */
+ case 68 : /* fall through */
+ case 69 : /* fall through */
+ case 70 : /* fall through */
+ case 71 : /* fall through */
+ case 72 : /* fall through */
+ case 73 : /* fall through */
+ case 74 : /* fall through */
+ case 75 : /* fall through */
+ case 76 : /* fall through */
+ case 77 : /* fall through */
+ case 78 : /* fall through */
+ case 79 : /* fall through */
+ case 80 : /* fall through */
+ case 81 : /* fall through */
+ case 82 : /* fall through */
+ case 83 : /* fall through */
+ case 84 : /* fall through */
+ case 85 : /* fall through */
+ case 86 : /* fall through */
+ case 87 : /* fall through */
+ case 88 : /* fall through */
+ case 89 : /* fall through */
+ case 90 : /* fall through */
+ case 91 : /* fall through */
+ case 92 : /* fall through */
+ case 93 : /* fall through */
+ case 94 : /* fall through */
+ case 95 :
+ if ((entire_insn & 0xf8000000) == 0x90000000)
+ { itype = ARC600F_INSN_LDW_S_ABU; goto extract_sfmt_ldw_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 96 : /* fall through */
+ case 97 : /* fall through */
+ case 98 : /* fall through */
+ case 99 : /* fall through */
+ case 100 : /* fall through */
+ case 101 : /* fall through */
+ case 102 : /* fall through */
+ case 103 : /* fall through */
+ case 104 : /* fall through */
+ case 105 : /* fall through */
+ case 106 : /* fall through */
+ case 107 : /* fall through */
+ case 108 : /* fall through */
+ case 109 : /* fall through */
+ case 110 : /* fall through */
+ case 111 : /* fall through */
+ case 112 : /* fall through */
+ case 113 : /* fall through */
+ case 114 : /* fall through */
+ case 115 : /* fall through */
+ case 116 : /* fall through */
+ case 117 : /* fall through */
+ case 118 : /* fall through */
+ case 119 : /* fall through */
+ case 120 : /* fall through */
+ case 121 : /* fall through */
+ case 122 : /* fall through */
+ case 123 : /* fall through */
+ case 124 : /* fall through */
+ case 125 : /* fall through */
+ case 126 : /* fall through */
+ case 127 :
+ if ((entire_insn & 0xf8000000) == 0xb0000000)
+ { itype = ARC600F_INSN_STW_S_ABU; goto extract_sfmt_stw_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 768 : /* fall through */
+ case 769 : /* fall through */
+ case 770 : /* fall through */
+ case 771 : /* fall through */
+ case 772 : /* fall through */
+ case 773 : /* fall through */
+ case 774 : /* fall through */
+ case 775 : /* fall through */
+ case 776 : /* fall through */
+ case 777 : /* fall through */
+ case 778 : /* fall through */
+ case 779 : /* fall through */
+ case 780 : /* fall through */
+ case 781 : /* fall through */
+ case 782 : /* fall through */
+ case 783 : /* fall through */
+ case 784 : /* fall through */
+ case 785 : /* fall through */
+ case 786 : /* fall through */
+ case 787 : /* fall through */
+ case 788 : /* fall through */
+ case 789 : /* fall through */
+ case 790 : /* fall through */
+ case 791 : /* fall through */
+ case 792 : /* fall through */
+ case 793 : /* fall through */
+ case 794 : /* fall through */
+ case 795 : /* fall through */
+ case 796 : /* fall through */
+ case 797 : /* fall through */
+ case 798 : /* fall through */
+ case 799 :
+ {
+ unsigned int val = (((insn >> 26) & (1 << 5)) | ((insn >> 25) & (1 << 4)) | ((insn >> 1) & (15 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf800001f) == 0x18000000)
+ { itype = ARC600F_INSN_ST_ABS; goto extract_sfmt_st_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf800001f) == 0x18000002)
+ { itype = ARC600F_INSN_STB_ABS; goto extract_sfmt_stb_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf800001f) == 0x18000004)
+ { itype = ARC600F_INSN_STW_ABS; goto extract_sfmt_stw_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xf800001f) == 0x18000008)
+ { itype = ARC600F_INSN_ST__AW_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xf800001f) == 0x1800000a)
+ { itype = ARC600F_INSN_STB__AW_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 :
+ if ((entire_insn & 0xf800001f) == 0x1800000c)
+ { itype = ARC600F_INSN_STW__AW_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 :
+ if ((entire_insn & 0xf800001f) == 0x18000010)
+ { itype = ARC600F_INSN_ST_AB_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 9 :
+ if ((entire_insn & 0xf800001f) == 0x18000012)
+ { itype = ARC600F_INSN_STB_AB_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 10 :
+ if ((entire_insn & 0xf800001f) == 0x18000014)
+ { itype = ARC600F_INSN_STW_AB_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 :
+ if ((entire_insn & 0xf800001f) == 0x18000018)
+ { itype = ARC600F_INSN_ST_AS_ABS; goto extract_sfmt_st_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 13 :
+ if ((entire_insn & 0xf800001f) == 0x1800001a)
+ { itype = ARC600F_INSN_STB_AS_ABS; goto extract_sfmt_stb_as_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 14 :
+ if ((entire_insn & 0xf800001f) == 0x1800001c)
+ { itype = ARC600F_INSN_STW_AS_ABS; goto extract_sfmt_stw_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 32 : /* fall through */
+ case 33 : /* fall through */
+ case 34 : /* fall through */
+ case 35 : /* fall through */
+ case 36 : /* fall through */
+ case 37 : /* fall through */
+ case 38 : /* fall through */
+ case 39 : /* fall through */
+ case 40 : /* fall through */
+ case 41 : /* fall through */
+ case 42 : /* fall through */
+ case 43 : /* fall through */
+ case 44 : /* fall through */
+ case 45 : /* fall through */
+ case 46 : /* fall through */
+ case 47 :
+ if ((entire_insn & 0xf8000000) == 0x98000000)
+ { itype = ARC600F_INSN_LDW_S_X_ABU; goto extract_sfmt_ldw_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 48 : /* fall through */
+ case 49 : /* fall through */
+ case 50 : /* fall through */
+ case 51 : /* fall through */
+ case 52 : /* fall through */
+ case 53 : /* fall through */
+ case 54 : /* fall through */
+ case 55 : /* fall through */
+ case 56 : /* fall through */
+ case 57 : /* fall through */
+ case 58 : /* fall through */
+ case 59 : /* fall through */
+ case 60 : /* fall through */
+ case 61 : /* fall through */
+ case 62 : /* fall through */
+ case 63 :
+ if ((entire_insn & 0xf8e00000) == 0xb8000000)
+ { itype = ARC600F_INSN_ASL_S_SSB; goto extract_sfmt_sub_s_ssb; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 800 : /* fall through */
+ case 801 : /* fall through */
+ case 802 : /* fall through */
+ case 803 : /* fall through */
+ case 804 : /* fall through */
+ case 805 : /* fall through */
+ case 806 : /* fall through */
+ case 807 : /* fall through */
+ case 808 : /* fall through */
+ case 809 : /* fall through */
+ case 810 : /* fall through */
+ case 811 : /* fall through */
+ case 812 : /* fall through */
+ case 813 : /* fall through */
+ case 814 : /* fall through */
+ case 815 : /* fall through */
+ case 816 : /* fall through */
+ case 817 : /* fall through */
+ case 818 : /* fall through */
+ case 819 : /* fall through */
+ case 820 : /* fall through */
+ case 821 : /* fall through */
+ case 822 : /* fall through */
+ case 823 : /* fall through */
+ case 824 : /* fall through */
+ case 825 : /* fall through */
+ case 826 : /* fall through */
+ case 827 : /* fall through */
+ case 828 : /* fall through */
+ case 829 : /* fall through */
+ case 830 : /* fall through */
+ case 831 :
+ {
+ unsigned int val = (((insn >> 26) & (1 << 5)) | ((insn >> 25) & (1 << 4)) | ((insn >> 1) & (15 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf800001f) == 0x18000000)
+ { itype = ARC600F_INSN_ST_ABS; goto extract_sfmt_st_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf800001f) == 0x18000002)
+ { itype = ARC600F_INSN_STB_ABS; goto extract_sfmt_stb_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf800001f) == 0x18000004)
+ { itype = ARC600F_INSN_STW_ABS; goto extract_sfmt_stw_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xf800001f) == 0x18000008)
+ { itype = ARC600F_INSN_ST__AW_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xf800001f) == 0x1800000a)
+ { itype = ARC600F_INSN_STB__AW_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 :
+ if ((entire_insn & 0xf800001f) == 0x1800000c)
+ { itype = ARC600F_INSN_STW__AW_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 :
+ if ((entire_insn & 0xf800001f) == 0x18000010)
+ { itype = ARC600F_INSN_ST_AB_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 9 :
+ if ((entire_insn & 0xf800001f) == 0x18000012)
+ { itype = ARC600F_INSN_STB_AB_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 10 :
+ if ((entire_insn & 0xf800001f) == 0x18000014)
+ { itype = ARC600F_INSN_STW_AB_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 :
+ if ((entire_insn & 0xf800001f) == 0x18000018)
+ { itype = ARC600F_INSN_ST_AS_ABS; goto extract_sfmt_st_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 13 :
+ if ((entire_insn & 0xf800001f) == 0x1800001a)
+ { itype = ARC600F_INSN_STB_AS_ABS; goto extract_sfmt_stb_as_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 14 :
+ if ((entire_insn & 0xf800001f) == 0x1800001c)
+ { itype = ARC600F_INSN_STW_AS_ABS; goto extract_sfmt_stw_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 32 : /* fall through */
+ case 33 : /* fall through */
+ case 34 : /* fall through */
+ case 35 : /* fall through */
+ case 36 : /* fall through */
+ case 37 : /* fall through */
+ case 38 : /* fall through */
+ case 39 : /* fall through */
+ case 40 : /* fall through */
+ case 41 : /* fall through */
+ case 42 : /* fall through */
+ case 43 : /* fall through */
+ case 44 : /* fall through */
+ case 45 : /* fall through */
+ case 46 : /* fall through */
+ case 47 :
+ if ((entire_insn & 0xf8000000) == 0x98000000)
+ { itype = ARC600F_INSN_LDW_S_X_ABU; goto extract_sfmt_ldw_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 48 : /* fall through */
+ case 49 : /* fall through */
+ case 50 : /* fall through */
+ case 51 : /* fall through */
+ case 52 : /* fall through */
+ case 53 : /* fall through */
+ case 54 : /* fall through */
+ case 55 : /* fall through */
+ case 56 : /* fall through */
+ case 57 : /* fall through */
+ case 58 : /* fall through */
+ case 59 : /* fall through */
+ case 60 : /* fall through */
+ case 61 : /* fall through */
+ case 62 : /* fall through */
+ case 63 :
+ if ((entire_insn & 0xf8e00000) == 0xb8200000)
+ { itype = ARC600F_INSN_LSR_S_SSB; goto extract_sfmt_sub_s_ssb; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 832 : /* fall through */
+ case 833 : /* fall through */
+ case 834 : /* fall through */
+ case 835 : /* fall through */
+ case 836 : /* fall through */
+ case 837 : /* fall through */
+ case 838 : /* fall through */
+ case 839 : /* fall through */
+ case 840 : /* fall through */
+ case 841 : /* fall through */
+ case 842 : /* fall through */
+ case 843 : /* fall through */
+ case 844 : /* fall through */
+ case 845 : /* fall through */
+ case 846 : /* fall through */
+ case 847 : /* fall through */
+ case 848 : /* fall through */
+ case 849 : /* fall through */
+ case 850 : /* fall through */
+ case 851 : /* fall through */
+ case 852 : /* fall through */
+ case 853 : /* fall through */
+ case 854 : /* fall through */
+ case 855 : /* fall through */
+ case 856 : /* fall through */
+ case 857 : /* fall through */
+ case 858 : /* fall through */
+ case 859 : /* fall through */
+ case 860 : /* fall through */
+ case 861 : /* fall through */
+ case 862 : /* fall through */
+ case 863 :
+ {
+ unsigned int val = (((insn >> 26) & (1 << 5)) | ((insn >> 25) & (1 << 4)) | ((insn >> 1) & (15 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf800001f) == 0x18000000)
+ { itype = ARC600F_INSN_ST_ABS; goto extract_sfmt_st_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf800001f) == 0x18000002)
+ { itype = ARC600F_INSN_STB_ABS; goto extract_sfmt_stb_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf800001f) == 0x18000004)
+ { itype = ARC600F_INSN_STW_ABS; goto extract_sfmt_stw_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xf800001f) == 0x18000008)
+ { itype = ARC600F_INSN_ST__AW_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xf800001f) == 0x1800000a)
+ { itype = ARC600F_INSN_STB__AW_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 :
+ if ((entire_insn & 0xf800001f) == 0x1800000c)
+ { itype = ARC600F_INSN_STW__AW_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 :
+ if ((entire_insn & 0xf800001f) == 0x18000010)
+ { itype = ARC600F_INSN_ST_AB_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 9 :
+ if ((entire_insn & 0xf800001f) == 0x18000012)
+ { itype = ARC600F_INSN_STB_AB_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 10 :
+ if ((entire_insn & 0xf800001f) == 0x18000014)
+ { itype = ARC600F_INSN_STW_AB_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 :
+ if ((entire_insn & 0xf800001f) == 0x18000018)
+ { itype = ARC600F_INSN_ST_AS_ABS; goto extract_sfmt_st_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 13 :
+ if ((entire_insn & 0xf800001f) == 0x1800001a)
+ { itype = ARC600F_INSN_STB_AS_ABS; goto extract_sfmt_stb_as_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 14 :
+ if ((entire_insn & 0xf800001f) == 0x1800001c)
+ { itype = ARC600F_INSN_STW_AS_ABS; goto extract_sfmt_stw_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 32 : /* fall through */
+ case 33 : /* fall through */
+ case 34 : /* fall through */
+ case 35 : /* fall through */
+ case 36 : /* fall through */
+ case 37 : /* fall through */
+ case 38 : /* fall through */
+ case 39 : /* fall through */
+ case 40 : /* fall through */
+ case 41 : /* fall through */
+ case 42 : /* fall through */
+ case 43 : /* fall through */
+ case 44 : /* fall through */
+ case 45 : /* fall through */
+ case 46 : /* fall through */
+ case 47 :
+ if ((entire_insn & 0xf8000000) == 0x98000000)
+ { itype = ARC600F_INSN_LDW_S_X_ABU; goto extract_sfmt_ldw_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 48 : /* fall through */
+ case 49 : /* fall through */
+ case 50 : /* fall through */
+ case 51 : /* fall through */
+ case 52 : /* fall through */
+ case 53 : /* fall through */
+ case 54 : /* fall through */
+ case 55 : /* fall through */
+ case 56 : /* fall through */
+ case 57 : /* fall through */
+ case 58 : /* fall through */
+ case 59 : /* fall through */
+ case 60 : /* fall through */
+ case 61 : /* fall through */
+ case 62 : /* fall through */
+ case 63 :
+ if ((entire_insn & 0xf8e00000) == 0xb8400000)
+ { itype = ARC600F_INSN_ASR_S_SSB; goto extract_sfmt_sub_s_ssb; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 864 : /* fall through */
+ case 865 : /* fall through */
+ case 866 : /* fall through */
+ case 867 : /* fall through */
+ case 868 : /* fall through */
+ case 869 : /* fall through */
+ case 870 : /* fall through */
+ case 871 : /* fall through */
+ case 872 : /* fall through */
+ case 873 : /* fall through */
+ case 874 : /* fall through */
+ case 875 : /* fall through */
+ case 876 : /* fall through */
+ case 877 : /* fall through */
+ case 878 : /* fall through */
+ case 879 : /* fall through */
+ case 880 : /* fall through */
+ case 881 : /* fall through */
+ case 882 : /* fall through */
+ case 883 : /* fall through */
+ case 884 : /* fall through */
+ case 885 : /* fall through */
+ case 886 : /* fall through */
+ case 887 : /* fall through */
+ case 888 : /* fall through */
+ case 889 : /* fall through */
+ case 890 : /* fall through */
+ case 891 : /* fall through */
+ case 892 : /* fall through */
+ case 893 : /* fall through */
+ case 894 : /* fall through */
+ case 895 :
+ {
+ unsigned int val = (((insn >> 26) & (1 << 5)) | ((insn >> 25) & (1 << 4)) | ((insn >> 1) & (15 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf800001f) == 0x18000000)
+ { itype = ARC600F_INSN_ST_ABS; goto extract_sfmt_st_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf800001f) == 0x18000002)
+ { itype = ARC600F_INSN_STB_ABS; goto extract_sfmt_stb_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf800001f) == 0x18000004)
+ { itype = ARC600F_INSN_STW_ABS; goto extract_sfmt_stw_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xf800001f) == 0x18000008)
+ { itype = ARC600F_INSN_ST__AW_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xf800001f) == 0x1800000a)
+ { itype = ARC600F_INSN_STB__AW_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 :
+ if ((entire_insn & 0xf800001f) == 0x1800000c)
+ { itype = ARC600F_INSN_STW__AW_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 :
+ if ((entire_insn & 0xf800001f) == 0x18000010)
+ { itype = ARC600F_INSN_ST_AB_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 9 :
+ if ((entire_insn & 0xf800001f) == 0x18000012)
+ { itype = ARC600F_INSN_STB_AB_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 10 :
+ if ((entire_insn & 0xf800001f) == 0x18000014)
+ { itype = ARC600F_INSN_STW_AB_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 :
+ if ((entire_insn & 0xf800001f) == 0x18000018)
+ { itype = ARC600F_INSN_ST_AS_ABS; goto extract_sfmt_st_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 13 :
+ if ((entire_insn & 0xf800001f) == 0x1800001a)
+ { itype = ARC600F_INSN_STB_AS_ABS; goto extract_sfmt_stb_as_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 14 :
+ if ((entire_insn & 0xf800001f) == 0x1800001c)
+ { itype = ARC600F_INSN_STW_AS_ABS; goto extract_sfmt_stw_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 32 : /* fall through */
+ case 33 : /* fall through */
+ case 34 : /* fall through */
+ case 35 : /* fall through */
+ case 36 : /* fall through */
+ case 37 : /* fall through */
+ case 38 : /* fall through */
+ case 39 : /* fall through */
+ case 40 : /* fall through */
+ case 41 : /* fall through */
+ case 42 : /* fall through */
+ case 43 : /* fall through */
+ case 44 : /* fall through */
+ case 45 : /* fall through */
+ case 46 : /* fall through */
+ case 47 :
+ if ((entire_insn & 0xf8000000) == 0x98000000)
+ { itype = ARC600F_INSN_LDW_S_X_ABU; goto extract_sfmt_ldw_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 48 : /* fall through */
+ case 49 : /* fall through */
+ case 50 : /* fall through */
+ case 51 : /* fall through */
+ case 52 : /* fall through */
+ case 53 : /* fall through */
+ case 54 : /* fall through */
+ case 55 : /* fall through */
+ case 56 : /* fall through */
+ case 57 : /* fall through */
+ case 58 : /* fall through */
+ case 59 : /* fall through */
+ case 60 : /* fall through */
+ case 61 : /* fall through */
+ case 62 : /* fall through */
+ case 63 :
+ if ((entire_insn & 0xf8e00000) == 0xb8600000)
+ { itype = ARC600F_INSN_SUB_S_SSB; goto extract_sfmt_sub_s_ssb; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 896 : /* fall through */
+ case 897 : /* fall through */
+ case 898 : /* fall through */
+ case 899 : /* fall through */
+ case 900 : /* fall through */
+ case 901 : /* fall through */
+ case 902 : /* fall through */
+ case 903 : /* fall through */
+ case 904 : /* fall through */
+ case 905 : /* fall through */
+ case 906 : /* fall through */
+ case 907 : /* fall through */
+ case 908 : /* fall through */
+ case 909 : /* fall through */
+ case 910 : /* fall through */
+ case 911 : /* fall through */
+ case 912 : /* fall through */
+ case 913 : /* fall through */
+ case 914 : /* fall through */
+ case 915 : /* fall through */
+ case 916 : /* fall through */
+ case 917 : /* fall through */
+ case 918 : /* fall through */
+ case 919 : /* fall through */
+ case 920 : /* fall through */
+ case 921 : /* fall through */
+ case 922 : /* fall through */
+ case 923 : /* fall through */
+ case 924 : /* fall through */
+ case 925 : /* fall through */
+ case 926 : /* fall through */
+ case 927 :
+ {
+ unsigned int val = (((insn >> 26) & (1 << 5)) | ((insn >> 25) & (1 << 4)) | ((insn >> 1) & (15 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf800001f) == 0x18000000)
+ { itype = ARC600F_INSN_ST_ABS; goto extract_sfmt_st_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf800001f) == 0x18000002)
+ { itype = ARC600F_INSN_STB_ABS; goto extract_sfmt_stb_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf800001f) == 0x18000004)
+ { itype = ARC600F_INSN_STW_ABS; goto extract_sfmt_stw_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xf800001f) == 0x18000008)
+ { itype = ARC600F_INSN_ST__AW_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xf800001f) == 0x1800000a)
+ { itype = ARC600F_INSN_STB__AW_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 :
+ if ((entire_insn & 0xf800001f) == 0x1800000c)
+ { itype = ARC600F_INSN_STW__AW_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 :
+ if ((entire_insn & 0xf800001f) == 0x18000010)
+ { itype = ARC600F_INSN_ST_AB_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 9 :
+ if ((entire_insn & 0xf800001f) == 0x18000012)
+ { itype = ARC600F_INSN_STB_AB_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 10 :
+ if ((entire_insn & 0xf800001f) == 0x18000014)
+ { itype = ARC600F_INSN_STW_AB_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 :
+ if ((entire_insn & 0xf800001f) == 0x18000018)
+ { itype = ARC600F_INSN_ST_AS_ABS; goto extract_sfmt_st_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 13 :
+ if ((entire_insn & 0xf800001f) == 0x1800001a)
+ { itype = ARC600F_INSN_STB_AS_ABS; goto extract_sfmt_stb_as_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 14 :
+ if ((entire_insn & 0xf800001f) == 0x1800001c)
+ { itype = ARC600F_INSN_STW_AS_ABS; goto extract_sfmt_stw_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 32 : /* fall through */
+ case 33 : /* fall through */
+ case 34 : /* fall through */
+ case 35 : /* fall through */
+ case 36 : /* fall through */
+ case 37 : /* fall through */
+ case 38 : /* fall through */
+ case 39 : /* fall through */
+ case 40 : /* fall through */
+ case 41 : /* fall through */
+ case 42 : /* fall through */
+ case 43 : /* fall through */
+ case 44 : /* fall through */
+ case 45 : /* fall through */
+ case 46 : /* fall through */
+ case 47 :
+ if ((entire_insn & 0xf8000000) == 0x98000000)
+ { itype = ARC600F_INSN_LDW_S_X_ABU; goto extract_sfmt_ldw_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 48 : /* fall through */
+ case 49 : /* fall through */
+ case 50 : /* fall through */
+ case 51 : /* fall through */
+ case 52 : /* fall through */
+ case 53 : /* fall through */
+ case 54 : /* fall through */
+ case 55 : /* fall through */
+ case 56 : /* fall through */
+ case 57 : /* fall through */
+ case 58 : /* fall through */
+ case 59 : /* fall through */
+ case 60 : /* fall through */
+ case 61 : /* fall through */
+ case 62 : /* fall through */
+ case 63 :
+ if ((entire_insn & 0xf8e00000) == 0xb8800000)
+ { itype = ARC600F_INSN_BSET_S_SSB; goto extract_sfmt_sub_s_ssb; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 928 : /* fall through */
+ case 929 : /* fall through */
+ case 930 : /* fall through */
+ case 931 : /* fall through */
+ case 932 : /* fall through */
+ case 933 : /* fall through */
+ case 934 : /* fall through */
+ case 935 : /* fall through */
+ case 936 : /* fall through */
+ case 937 : /* fall through */
+ case 938 : /* fall through */
+ case 939 : /* fall through */
+ case 940 : /* fall through */
+ case 941 : /* fall through */
+ case 942 : /* fall through */
+ case 943 : /* fall through */
+ case 944 : /* fall through */
+ case 945 : /* fall through */
+ case 946 : /* fall through */
+ case 947 : /* fall through */
+ case 948 : /* fall through */
+ case 949 : /* fall through */
+ case 950 : /* fall through */
+ case 951 : /* fall through */
+ case 952 : /* fall through */
+ case 953 : /* fall through */
+ case 954 : /* fall through */
+ case 955 : /* fall through */
+ case 956 : /* fall through */
+ case 957 : /* fall through */
+ case 958 : /* fall through */
+ case 959 :
+ {
+ unsigned int val = (((insn >> 26) & (1 << 5)) | ((insn >> 25) & (1 << 4)) | ((insn >> 1) & (15 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf800001f) == 0x18000000)
+ { itype = ARC600F_INSN_ST_ABS; goto extract_sfmt_st_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf800001f) == 0x18000002)
+ { itype = ARC600F_INSN_STB_ABS; goto extract_sfmt_stb_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf800001f) == 0x18000004)
+ { itype = ARC600F_INSN_STW_ABS; goto extract_sfmt_stw_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xf800001f) == 0x18000008)
+ { itype = ARC600F_INSN_ST__AW_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xf800001f) == 0x1800000a)
+ { itype = ARC600F_INSN_STB__AW_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 :
+ if ((entire_insn & 0xf800001f) == 0x1800000c)
+ { itype = ARC600F_INSN_STW__AW_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 :
+ if ((entire_insn & 0xf800001f) == 0x18000010)
+ { itype = ARC600F_INSN_ST_AB_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 9 :
+ if ((entire_insn & 0xf800001f) == 0x18000012)
+ { itype = ARC600F_INSN_STB_AB_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 10 :
+ if ((entire_insn & 0xf800001f) == 0x18000014)
+ { itype = ARC600F_INSN_STW_AB_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 :
+ if ((entire_insn & 0xf800001f) == 0x18000018)
+ { itype = ARC600F_INSN_ST_AS_ABS; goto extract_sfmt_st_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 13 :
+ if ((entire_insn & 0xf800001f) == 0x1800001a)
+ { itype = ARC600F_INSN_STB_AS_ABS; goto extract_sfmt_stb_as_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 14 :
+ if ((entire_insn & 0xf800001f) == 0x1800001c)
+ { itype = ARC600F_INSN_STW_AS_ABS; goto extract_sfmt_stw_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 32 : /* fall through */
+ case 33 : /* fall through */
+ case 34 : /* fall through */
+ case 35 : /* fall through */
+ case 36 : /* fall through */
+ case 37 : /* fall through */
+ case 38 : /* fall through */
+ case 39 : /* fall through */
+ case 40 : /* fall through */
+ case 41 : /* fall through */
+ case 42 : /* fall through */
+ case 43 : /* fall through */
+ case 44 : /* fall through */
+ case 45 : /* fall through */
+ case 46 : /* fall through */
+ case 47 :
+ if ((entire_insn & 0xf8000000) == 0x98000000)
+ { itype = ARC600F_INSN_LDW_S_X_ABU; goto extract_sfmt_ldw_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 48 : /* fall through */
+ case 49 : /* fall through */
+ case 50 : /* fall through */
+ case 51 : /* fall through */
+ case 52 : /* fall through */
+ case 53 : /* fall through */
+ case 54 : /* fall through */
+ case 55 : /* fall through */
+ case 56 : /* fall through */
+ case 57 : /* fall through */
+ case 58 : /* fall through */
+ case 59 : /* fall through */
+ case 60 : /* fall through */
+ case 61 : /* fall through */
+ case 62 : /* fall through */
+ case 63 :
+ if ((entire_insn & 0xf8e00000) == 0xb8a00000)
+ { itype = ARC600F_INSN_BCLR_S_SSB; goto extract_sfmt_sub_s_ssb; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 960 : /* fall through */
+ case 961 : /* fall through */
+ case 962 : /* fall through */
+ case 963 : /* fall through */
+ case 964 : /* fall through */
+ case 965 : /* fall through */
+ case 966 : /* fall through */
+ case 967 : /* fall through */
+ case 968 : /* fall through */
+ case 969 : /* fall through */
+ case 970 : /* fall through */
+ case 971 : /* fall through */
+ case 972 : /* fall through */
+ case 973 : /* fall through */
+ case 974 : /* fall through */
+ case 975 : /* fall through */
+ case 976 : /* fall through */
+ case 977 : /* fall through */
+ case 978 : /* fall through */
+ case 979 : /* fall through */
+ case 980 : /* fall through */
+ case 981 : /* fall through */
+ case 982 : /* fall through */
+ case 983 : /* fall through */
+ case 984 : /* fall through */
+ case 985 : /* fall through */
+ case 986 : /* fall through */
+ case 987 : /* fall through */
+ case 988 : /* fall through */
+ case 989 : /* fall through */
+ case 990 : /* fall through */
+ case 991 :
+ {
+ unsigned int val = (((insn >> 26) & (1 << 5)) | ((insn >> 25) & (1 << 4)) | ((insn >> 1) & (15 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf800001f) == 0x18000000)
+ { itype = ARC600F_INSN_ST_ABS; goto extract_sfmt_st_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf800001f) == 0x18000002)
+ { itype = ARC600F_INSN_STB_ABS; goto extract_sfmt_stb_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf800001f) == 0x18000004)
+ { itype = ARC600F_INSN_STW_ABS; goto extract_sfmt_stw_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xf800001f) == 0x18000008)
+ { itype = ARC600F_INSN_ST__AW_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xf800001f) == 0x1800000a)
+ { itype = ARC600F_INSN_STB__AW_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 :
+ if ((entire_insn & 0xf800001f) == 0x1800000c)
+ { itype = ARC600F_INSN_STW__AW_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 :
+ if ((entire_insn & 0xf800001f) == 0x18000010)
+ { itype = ARC600F_INSN_ST_AB_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 9 :
+ if ((entire_insn & 0xf800001f) == 0x18000012)
+ { itype = ARC600F_INSN_STB_AB_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 10 :
+ if ((entire_insn & 0xf800001f) == 0x18000014)
+ { itype = ARC600F_INSN_STW_AB_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 :
+ if ((entire_insn & 0xf800001f) == 0x18000018)
+ { itype = ARC600F_INSN_ST_AS_ABS; goto extract_sfmt_st_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 13 :
+ if ((entire_insn & 0xf800001f) == 0x1800001a)
+ { itype = ARC600F_INSN_STB_AS_ABS; goto extract_sfmt_stb_as_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 14 :
+ if ((entire_insn & 0xf800001f) == 0x1800001c)
+ { itype = ARC600F_INSN_STW_AS_ABS; goto extract_sfmt_stw_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 32 : /* fall through */
+ case 33 : /* fall through */
+ case 34 : /* fall through */
+ case 35 : /* fall through */
+ case 36 : /* fall through */
+ case 37 : /* fall through */
+ case 38 : /* fall through */
+ case 39 : /* fall through */
+ case 40 : /* fall through */
+ case 41 : /* fall through */
+ case 42 : /* fall through */
+ case 43 : /* fall through */
+ case 44 : /* fall through */
+ case 45 : /* fall through */
+ case 46 : /* fall through */
+ case 47 :
+ if ((entire_insn & 0xf8000000) == 0x98000000)
+ { itype = ARC600F_INSN_LDW_S_X_ABU; goto extract_sfmt_ldw_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 48 : /* fall through */
+ case 49 : /* fall through */
+ case 50 : /* fall through */
+ case 51 : /* fall through */
+ case 52 : /* fall through */
+ case 53 : /* fall through */
+ case 54 : /* fall through */
+ case 55 : /* fall through */
+ case 56 : /* fall through */
+ case 57 : /* fall through */
+ case 58 : /* fall through */
+ case 59 : /* fall through */
+ case 60 : /* fall through */
+ case 61 : /* fall through */
+ case 62 : /* fall through */
+ case 63 :
+ if ((entire_insn & 0xf8e00000) == 0xb8c00000)
+ { itype = ARC600F_INSN_BMSK_S_SSB; goto extract_sfmt_sub_s_ssb; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 992 : /* fall through */
+ case 993 : /* fall through */
+ case 994 : /* fall through */
+ case 995 : /* fall through */
+ case 996 : /* fall through */
+ case 997 : /* fall through */
+ case 998 : /* fall through */
+ case 999 : /* fall through */
+ case 1000 : /* fall through */
+ case 1001 : /* fall through */
+ case 1002 : /* fall through */
+ case 1003 : /* fall through */
+ case 1004 : /* fall through */
+ case 1005 : /* fall through */
+ case 1006 : /* fall through */
+ case 1007 : /* fall through */
+ case 1008 : /* fall through */
+ case 1009 : /* fall through */
+ case 1010 : /* fall through */
+ case 1011 : /* fall through */
+ case 1012 : /* fall through */
+ case 1013 : /* fall through */
+ case 1014 : /* fall through */
+ case 1015 : /* fall through */
+ case 1016 : /* fall through */
+ case 1017 : /* fall through */
+ case 1018 : /* fall through */
+ case 1019 : /* fall through */
+ case 1020 : /* fall through */
+ case 1021 : /* fall through */
+ case 1022 : /* fall through */
+ case 1023 :
+ {
+ unsigned int val = (((insn >> 26) & (1 << 5)) | ((insn >> 25) & (1 << 4)) | ((insn >> 1) & (15 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf800001f) == 0x18000000)
+ { itype = ARC600F_INSN_ST_ABS; goto extract_sfmt_st_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf800001f) == 0x18000002)
+ { itype = ARC600F_INSN_STB_ABS; goto extract_sfmt_stb_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf800001f) == 0x18000004)
+ { itype = ARC600F_INSN_STW_ABS; goto extract_sfmt_stw_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xf800001f) == 0x18000008)
+ { itype = ARC600F_INSN_ST__AW_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xf800001f) == 0x1800000a)
+ { itype = ARC600F_INSN_STB__AW_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 :
+ if ((entire_insn & 0xf800001f) == 0x1800000c)
+ { itype = ARC600F_INSN_STW__AW_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 :
+ if ((entire_insn & 0xf800001f) == 0x18000010)
+ { itype = ARC600F_INSN_ST_AB_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 9 :
+ if ((entire_insn & 0xf800001f) == 0x18000012)
+ { itype = ARC600F_INSN_STB_AB_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 10 :
+ if ((entire_insn & 0xf800001f) == 0x18000014)
+ { itype = ARC600F_INSN_STW_AB_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 :
+ if ((entire_insn & 0xf800001f) == 0x18000018)
+ { itype = ARC600F_INSN_ST_AS_ABS; goto extract_sfmt_st_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 13 :
+ if ((entire_insn & 0xf800001f) == 0x1800001a)
+ { itype = ARC600F_INSN_STB_AS_ABS; goto extract_sfmt_stb_as_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 14 :
+ if ((entire_insn & 0xf800001f) == 0x1800001c)
+ { itype = ARC600F_INSN_STW_AS_ABS; goto extract_sfmt_stw_abs; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 32 : /* fall through */
+ case 33 : /* fall through */
+ case 34 : /* fall through */
+ case 35 : /* fall through */
+ case 36 : /* fall through */
+ case 37 : /* fall through */
+ case 38 : /* fall through */
+ case 39 : /* fall through */
+ case 40 : /* fall through */
+ case 41 : /* fall through */
+ case 42 : /* fall through */
+ case 43 : /* fall through */
+ case 44 : /* fall through */
+ case 45 : /* fall through */
+ case 46 : /* fall through */
+ case 47 :
+ if ((entire_insn & 0xf8000000) == 0x98000000)
+ { itype = ARC600F_INSN_LDW_S_X_ABU; goto extract_sfmt_ldw_s_abu; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 48 : /* fall through */
+ case 49 : /* fall through */
+ case 50 : /* fall through */
+ case 51 : /* fall through */
+ case 52 : /* fall through */
+ case 53 : /* fall through */
+ case 54 : /* fall through */
+ case 55 : /* fall through */
+ case 56 : /* fall through */
+ case 57 : /* fall through */
+ case 58 : /* fall through */
+ case 59 : /* fall through */
+ case 60 : /* fall through */
+ case 61 : /* fall through */
+ case 62 : /* fall through */
+ case 63 :
+ if ((entire_insn & 0xf8e00000) == 0xb8e00000)
+ { itype = ARC600F_INSN_BTST_S_SSB; goto extract_sfmt_btst_s_ssb; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1024 : /* fall through */
+ case 1025 : /* fall through */
+ case 1026 : /* fall through */
+ case 1027 : /* fall through */
+ case 1028 : /* fall through */
+ case 1029 : /* fall through */
+ case 1030 : /* fall through */
+ case 1031 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60000000)
+ { itype = ARC600F_INSN_LD_S_ABC; goto extract_sfmt_ld_s_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0000000)
+ { itype = ARC600F_INSN_LD_S_ABSP; goto extract_sfmt_ld_s_absp; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = ARC600F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1032 : /* fall through */
+ case 1033 : /* fall through */
+ case 1034 : /* fall through */
+ case 1035 : /* fall through */
+ case 1036 : /* fall through */
+ case 1037 : /* fall through */
+ case 1038 : /* fall through */
+ case 1039 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60080000)
+ { itype = ARC600F_INSN_LDB_S_ABC; goto extract_sfmt_ldb_s_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0000000)
+ { itype = ARC600F_INSN_LD_S_ABSP; goto extract_sfmt_ld_s_absp; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = ARC600F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1040 : /* fall through */
+ case 1041 : /* fall through */
+ case 1042 : /* fall through */
+ case 1043 : /* fall through */
+ case 1044 : /* fall through */
+ case 1045 : /* fall through */
+ case 1046 : /* fall through */
+ case 1047 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60100000)
+ { itype = ARC600F_INSN_LDW_S_ABC; goto extract_sfmt_ldw_s_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0000000)
+ { itype = ARC600F_INSN_LD_S_ABSP; goto extract_sfmt_ld_s_absp; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = ARC600F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1048 : /* fall through */
+ case 1049 : /* fall through */
+ case 1050 : /* fall through */
+ case 1051 : /* fall through */
+ case 1052 : /* fall through */
+ case 1053 : /* fall through */
+ case 1054 : /* fall through */
+ case 1055 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60180000)
+ { itype = ARC600F_INSN_ADD_S_ABC; goto extract_sfmt_add_s_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0000000)
+ { itype = ARC600F_INSN_LD_S_ABSP; goto extract_sfmt_ld_s_absp; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = ARC600F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1056 : /* fall through */
+ case 1057 : /* fall through */
+ case 1058 : /* fall through */
+ case 1059 : /* fall through */
+ case 1060 : /* fall through */
+ case 1061 : /* fall through */
+ case 1062 : /* fall through */
+ case 1063 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60000000)
+ { itype = ARC600F_INSN_LD_S_ABC; goto extract_sfmt_ld_s_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0200000)
+ { itype = ARC600F_INSN_LDB_S_ABSP; goto extract_sfmt_ldb_s_absp; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = ARC600F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1064 : /* fall through */
+ case 1065 : /* fall through */
+ case 1066 : /* fall through */
+ case 1067 : /* fall through */
+ case 1068 : /* fall through */
+ case 1069 : /* fall through */
+ case 1070 : /* fall through */
+ case 1071 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60080000)
+ { itype = ARC600F_INSN_LDB_S_ABC; goto extract_sfmt_ldb_s_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0200000)
+ { itype = ARC600F_INSN_LDB_S_ABSP; goto extract_sfmt_ldb_s_absp; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = ARC600F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1072 : /* fall through */
+ case 1073 : /* fall through */
+ case 1074 : /* fall through */
+ case 1075 : /* fall through */
+ case 1076 : /* fall through */
+ case 1077 : /* fall through */
+ case 1078 : /* fall through */
+ case 1079 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60100000)
+ { itype = ARC600F_INSN_LDW_S_ABC; goto extract_sfmt_ldw_s_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0200000)
+ { itype = ARC600F_INSN_LDB_S_ABSP; goto extract_sfmt_ldb_s_absp; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = ARC600F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1080 : /* fall through */
+ case 1081 : /* fall through */
+ case 1082 : /* fall through */
+ case 1083 : /* fall through */
+ case 1084 : /* fall through */
+ case 1085 : /* fall through */
+ case 1086 : /* fall through */
+ case 1087 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60180000)
+ { itype = ARC600F_INSN_ADD_S_ABC; goto extract_sfmt_add_s_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0200000)
+ { itype = ARC600F_INSN_LDB_S_ABSP; goto extract_sfmt_ldb_s_absp; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = ARC600F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1088 : /* fall through */
+ case 1089 : /* fall through */
+ case 1090 : /* fall through */
+ case 1091 : /* fall through */
+ case 1092 : /* fall through */
+ case 1093 : /* fall through */
+ case 1094 : /* fall through */
+ case 1095 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60000000)
+ { itype = ARC600F_INSN_LD_S_ABC; goto extract_sfmt_ld_s_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0400000)
+ { itype = ARC600F_INSN_ST_S_ABSP; goto extract_sfmt_st_s_absp; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = ARC600F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1096 : /* fall through */
+ case 1097 : /* fall through */
+ case 1098 : /* fall through */
+ case 1099 : /* fall through */
+ case 1100 : /* fall through */
+ case 1101 : /* fall through */
+ case 1102 : /* fall through */
+ case 1103 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60080000)
+ { itype = ARC600F_INSN_LDB_S_ABC; goto extract_sfmt_ldb_s_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0400000)
+ { itype = ARC600F_INSN_ST_S_ABSP; goto extract_sfmt_st_s_absp; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = ARC600F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1104 : /* fall through */
+ case 1105 : /* fall through */
+ case 1106 : /* fall through */
+ case 1107 : /* fall through */
+ case 1108 : /* fall through */
+ case 1109 : /* fall through */
+ case 1110 : /* fall through */
+ case 1111 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60100000)
+ { itype = ARC600F_INSN_LDW_S_ABC; goto extract_sfmt_ldw_s_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0400000)
+ { itype = ARC600F_INSN_ST_S_ABSP; goto extract_sfmt_st_s_absp; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = ARC600F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1112 : /* fall through */
+ case 1113 : /* fall through */
+ case 1114 : /* fall through */
+ case 1115 : /* fall through */
+ case 1116 : /* fall through */
+ case 1117 : /* fall through */
+ case 1118 : /* fall through */
+ case 1119 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60180000)
+ { itype = ARC600F_INSN_ADD_S_ABC; goto extract_sfmt_add_s_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0400000)
+ { itype = ARC600F_INSN_ST_S_ABSP; goto extract_sfmt_st_s_absp; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = ARC600F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1120 : /* fall through */
+ case 1121 : /* fall through */
+ case 1122 : /* fall through */
+ case 1123 : /* fall through */
+ case 1124 : /* fall through */
+ case 1125 : /* fall through */
+ case 1126 : /* fall through */
+ case 1127 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60000000)
+ { itype = ARC600F_INSN_LD_S_ABC; goto extract_sfmt_ld_s_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0600000)
+ { itype = ARC600F_INSN_STB_S_ABSP; goto extract_sfmt_stb_s_absp; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = ARC600F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1128 : /* fall through */
+ case 1129 : /* fall through */
+ case 1130 : /* fall through */
+ case 1131 : /* fall through */
+ case 1132 : /* fall through */
+ case 1133 : /* fall through */
+ case 1134 : /* fall through */
+ case 1135 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60080000)
+ { itype = ARC600F_INSN_LDB_S_ABC; goto extract_sfmt_ldb_s_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0600000)
+ { itype = ARC600F_INSN_STB_S_ABSP; goto extract_sfmt_stb_s_absp; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = ARC600F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1136 : /* fall through */
+ case 1137 : /* fall through */
+ case 1138 : /* fall through */
+ case 1139 : /* fall through */
+ case 1140 : /* fall through */
+ case 1141 : /* fall through */
+ case 1142 : /* fall through */
+ case 1143 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60100000)
+ { itype = ARC600F_INSN_LDW_S_ABC; goto extract_sfmt_ldw_s_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0600000)
+ { itype = ARC600F_INSN_STB_S_ABSP; goto extract_sfmt_stb_s_absp; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = ARC600F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1144 : /* fall through */
+ case 1145 : /* fall through */
+ case 1146 : /* fall through */
+ case 1147 : /* fall through */
+ case 1148 : /* fall through */
+ case 1149 : /* fall through */
+ case 1150 : /* fall through */
+ case 1151 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60180000)
+ { itype = ARC600F_INSN_ADD_S_ABC; goto extract_sfmt_add_s_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0600000)
+ { itype = ARC600F_INSN_STB_S_ABSP; goto extract_sfmt_stb_s_absp; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = ARC600F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1152 : /* fall through */
+ case 1153 : /* fall through */
+ case 1154 : /* fall through */
+ case 1155 : /* fall through */
+ case 1156 : /* fall through */
+ case 1157 : /* fall through */
+ case 1158 : /* fall through */
+ case 1159 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60000000)
+ { itype = ARC600F_INSN_LD_S_ABC; goto extract_sfmt_ld_s_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0800000)
+ { itype = ARC600F_INSN_ADD_S_ABSP; goto extract_sfmt_add_s_absp; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = ARC600F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1160 : /* fall through */
+ case 1161 : /* fall through */
+ case 1162 : /* fall through */
+ case 1163 : /* fall through */
+ case 1164 : /* fall through */
+ case 1165 : /* fall through */
+ case 1166 : /* fall through */
+ case 1167 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60080000)
+ { itype = ARC600F_INSN_LDB_S_ABC; goto extract_sfmt_ldb_s_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0800000)
+ { itype = ARC600F_INSN_ADD_S_ABSP; goto extract_sfmt_add_s_absp; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = ARC600F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1168 : /* fall through */
+ case 1169 : /* fall through */
+ case 1170 : /* fall through */
+ case 1171 : /* fall through */
+ case 1172 : /* fall through */
+ case 1173 : /* fall through */
+ case 1174 : /* fall through */
+ case 1175 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60100000)
+ { itype = ARC600F_INSN_LDW_S_ABC; goto extract_sfmt_ldw_s_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0800000)
+ { itype = ARC600F_INSN_ADD_S_ABSP; goto extract_sfmt_add_s_absp; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = ARC600F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1176 : /* fall through */
+ case 1177 : /* fall through */
+ case 1178 : /* fall through */
+ case 1179 : /* fall through */
+ case 1180 : /* fall through */
+ case 1181 : /* fall through */
+ case 1182 : /* fall through */
+ case 1183 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60180000)
+ { itype = ARC600F_INSN_ADD_S_ABC; goto extract_sfmt_add_s_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0800000)
+ { itype = ARC600F_INSN_ADD_S_ABSP; goto extract_sfmt_add_s_absp; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = ARC600F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1184 : /* fall through */
+ case 1185 : /* fall through */
+ case 1186 : /* fall through */
+ case 1187 : /* fall through */
+ case 1188 : /* fall through */
+ case 1189 : /* fall through */
+ case 1190 : /* fall through */
+ case 1191 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 24) & (1 << 0)));
+ switch (val)
+ {
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8180000) == 0x60000000)
+ { itype = ARC600F_INSN_LD_S_ABC; goto extract_sfmt_ld_s_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xffe00000) == 0xc0a00000)
+ { itype = ARC600F_INSN_ADD_S_ASSPSP; goto extract_sfmt_add_s_asspsp; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xffe00000) == 0xc1a00000)
+ { itype = ARC600F_INSN_SUB_S_ASSPSP; goto extract_sfmt_add_s_asspsp; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = ARC600F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1192 : /* fall through */
+ case 1193 : /* fall through */
+ case 1194 : /* fall through */
+ case 1195 : /* fall through */
+ case 1196 : /* fall through */
+ case 1197 : /* fall through */
+ case 1198 : /* fall through */
+ case 1199 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 24) & (1 << 0)));
+ switch (val)
+ {
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8180000) == 0x60080000)
+ { itype = ARC600F_INSN_LDB_S_ABC; goto extract_sfmt_ldb_s_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xffe00000) == 0xc0a00000)
+ { itype = ARC600F_INSN_ADD_S_ASSPSP; goto extract_sfmt_add_s_asspsp; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xffe00000) == 0xc1a00000)
+ { itype = ARC600F_INSN_SUB_S_ASSPSP; goto extract_sfmt_add_s_asspsp; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = ARC600F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1200 : /* fall through */
+ case 1201 : /* fall through */
+ case 1202 : /* fall through */
+ case 1203 : /* fall through */
+ case 1204 : /* fall through */
+ case 1205 : /* fall through */
+ case 1206 : /* fall through */
+ case 1207 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 24) & (1 << 0)));
+ switch (val)
+ {
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8180000) == 0x60100000)
+ { itype = ARC600F_INSN_LDW_S_ABC; goto extract_sfmt_ldw_s_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xffe00000) == 0xc0a00000)
+ { itype = ARC600F_INSN_ADD_S_ASSPSP; goto extract_sfmt_add_s_asspsp; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xffe00000) == 0xc1a00000)
+ { itype = ARC600F_INSN_SUB_S_ASSPSP; goto extract_sfmt_add_s_asspsp; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = ARC600F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1208 : /* fall through */
+ case 1209 : /* fall through */
+ case 1210 : /* fall through */
+ case 1211 : /* fall through */
+ case 1212 : /* fall through */
+ case 1213 : /* fall through */
+ case 1214 : /* fall through */
+ case 1215 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 24) & (1 << 0)));
+ switch (val)
+ {
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8180000) == 0x60180000)
+ { itype = ARC600F_INSN_ADD_S_ABC; goto extract_sfmt_add_s_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xffe00000) == 0xc0a00000)
+ { itype = ARC600F_INSN_ADD_S_ASSPSP; goto extract_sfmt_add_s_asspsp; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xffe00000) == 0xc1a00000)
+ { itype = ARC600F_INSN_SUB_S_ASSPSP; goto extract_sfmt_add_s_asspsp; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = ARC600F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1216 : /* fall through */
+ case 1218 : /* fall through */
+ case 1219 : /* fall through */
+ case 1220 : /* fall through */
+ case 1221 : /* fall through */
+ case 1222 : /* fall through */
+ case 1223 : /* fall through */
+ case 1248 : /* fall through */
+ case 1250 : /* fall through */
+ case 1251 : /* fall through */
+ case 1252 : /* fall through */
+ case 1253 : /* fall through */
+ case 1254 : /* fall through */
+ case 1255 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8180000) == 0x60000000)
+ { itype = ARC600F_INSN_LD_S_ABC; goto extract_sfmt_ld_s_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = ARC600F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1217 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60000000)
+ { itype = ARC600F_INSN_LD_S_ABC; goto extract_sfmt_ld_s_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0000) == 0xc0c10000)
+ { itype = ARC600F_INSN_POP_S_B; goto extract_sfmt_pop_s_b; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = ARC600F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1224 : /* fall through */
+ case 1225 : /* fall through */
+ case 1226 : /* fall through */
+ case 1227 : /* fall through */
+ case 1228 : /* fall through */
+ case 1229 : /* fall through */
+ case 1230 : /* fall through */
+ case 1231 : /* fall through */
+ case 1256 : /* fall through */
+ case 1257 : /* fall through */
+ case 1258 : /* fall through */
+ case 1259 : /* fall through */
+ case 1260 : /* fall through */
+ case 1261 : /* fall through */
+ case 1262 : /* fall through */
+ case 1263 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8180000) == 0x60080000)
+ { itype = ARC600F_INSN_LDB_S_ABC; goto extract_sfmt_ldb_s_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = ARC600F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1232 : /* fall through */
+ case 1234 : /* fall through */
+ case 1235 : /* fall through */
+ case 1236 : /* fall through */
+ case 1237 : /* fall through */
+ case 1238 : /* fall through */
+ case 1239 : /* fall through */
+ case 1264 : /* fall through */
+ case 1266 : /* fall through */
+ case 1267 : /* fall through */
+ case 1268 : /* fall through */
+ case 1269 : /* fall through */
+ case 1270 : /* fall through */
+ case 1271 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8180000) == 0x60100000)
+ { itype = ARC600F_INSN_LDW_S_ABC; goto extract_sfmt_ldw_s_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = ARC600F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1233 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60100000)
+ { itype = ARC600F_INSN_LDW_S_ABC; goto extract_sfmt_ldw_s_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xffff0000) == 0xc0d10000)
+ { itype = ARC600F_INSN_POP_S_BLINK; goto extract_sfmt_pop_s_blink; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = ARC600F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1240 : /* fall through */
+ case 1241 : /* fall through */
+ case 1242 : /* fall through */
+ case 1243 : /* fall through */
+ case 1244 : /* fall through */
+ case 1245 : /* fall through */
+ case 1246 : /* fall through */
+ case 1247 : /* fall through */
+ case 1272 : /* fall through */
+ case 1273 : /* fall through */
+ case 1274 : /* fall through */
+ case 1275 : /* fall through */
+ case 1276 : /* fall through */
+ case 1277 : /* fall through */
+ case 1278 : /* fall through */
+ case 1279 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8180000) == 0x60180000)
+ { itype = ARC600F_INSN_ADD_S_ABC; goto extract_sfmt_add_s_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = ARC600F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1249 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60000000)
+ { itype = ARC600F_INSN_LD_S_ABC; goto extract_sfmt_ld_s_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0000) == 0xc0e10000)
+ { itype = ARC600F_INSN_PUSH_S_B; goto extract_sfmt_push_s_b; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = ARC600F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1265 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60100000)
+ { itype = ARC600F_INSN_LDW_S_ABC; goto extract_sfmt_ldw_s_abc; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xffff0000) == 0xc0f10000)
+ { itype = ARC600F_INSN_PUSH_S_BLINK; goto extract_sfmt_push_s_blink; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = ARC600F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1280 : /* fall through */
+ case 1281 : /* fall through */
+ case 1282 : /* fall through */
+ case 1283 : /* fall through */
+ case 1284 : /* fall through */
+ case 1285 : /* fall through */
+ case 1286 : /* fall through */
+ case 1287 : /* fall through */
+ case 1312 : /* fall through */
+ case 1313 : /* fall through */
+ case 1314 : /* fall through */
+ case 1315 : /* fall through */
+ case 1316 : /* fall through */
+ case 1317 : /* fall through */
+ case 1318 : /* fall through */
+ case 1319 : /* fall through */
+ case 1344 : /* fall through */
+ case 1345 : /* fall through */
+ case 1346 : /* fall through */
+ case 1347 : /* fall through */
+ case 1348 : /* fall through */
+ case 1349 : /* fall through */
+ case 1350 : /* fall through */
+ case 1351 : /* fall through */
+ case 1376 : /* fall through */
+ case 1377 : /* fall through */
+ case 1378 : /* fall through */
+ case 1379 : /* fall through */
+ case 1380 : /* fall through */
+ case 1381 : /* fall through */
+ case 1382 : /* fall through */
+ case 1383 : /* fall through */
+ case 1408 : /* fall through */
+ case 1409 : /* fall through */
+ case 1410 : /* fall through */
+ case 1411 : /* fall through */
+ case 1412 : /* fall through */
+ case 1413 : /* fall through */
+ case 1414 : /* fall through */
+ case 1415 : /* fall through */
+ case 1440 : /* fall through */
+ case 1441 : /* fall through */
+ case 1442 : /* fall through */
+ case 1443 : /* fall through */
+ case 1444 : /* fall through */
+ case 1445 : /* fall through */
+ case 1446 : /* fall through */
+ case 1447 : /* fall through */
+ case 1472 : /* fall through */
+ case 1473 : /* fall through */
+ case 1474 : /* fall through */
+ case 1475 : /* fall through */
+ case 1476 : /* fall through */
+ case 1477 : /* fall through */
+ case 1478 : /* fall through */
+ case 1479 : /* fall through */
+ case 1504 : /* fall through */
+ case 1505 : /* fall through */
+ case 1506 : /* fall through */
+ case 1507 : /* fall through */
+ case 1508 : /* fall through */
+ case 1509 : /* fall through */
+ case 1510 : /* fall through */
+ case 1511 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 25) & (3 << 0)));
+ switch (val)
+ {
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8180000) == 0x68000000)
+ { itype = ARC600F_INSN_ADD_S_CBU3; goto extract_sfmt_add_s_cbu3; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 :
+ if ((entire_insn & 0xfe000000) == 0xc8000000)
+ { itype = ARC600F_INSN_LD_S_GPREL; goto extract_sfmt_ld_s_gprel; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 9 :
+ if ((entire_insn & 0xfe000000) == 0xca000000)
+ { itype = ARC600F_INSN_LDB_S_GPREL; goto extract_sfmt_ldb_s_gprel; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 10 :
+ if ((entire_insn & 0xfe000000) == 0xcc000000)
+ { itype = ARC600F_INSN_LDW_S_GPREL; goto extract_sfmt_ldw_s_gprel; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 11 :
+ if ((entire_insn & 0xfe000000) == 0xce000000)
+ { itype = ARC600F_INSN_ADD_S_GP; goto extract_sfmt_add_s_gp; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xe8000000)
+ { itype = ARC600F_INSN_BRCC_S; goto extract_sfmt_brcc_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1288 : /* fall through */
+ case 1289 : /* fall through */
+ case 1290 : /* fall through */
+ case 1291 : /* fall through */
+ case 1292 : /* fall through */
+ case 1293 : /* fall through */
+ case 1294 : /* fall through */
+ case 1295 : /* fall through */
+ case 1320 : /* fall through */
+ case 1321 : /* fall through */
+ case 1322 : /* fall through */
+ case 1323 : /* fall through */
+ case 1324 : /* fall through */
+ case 1325 : /* fall through */
+ case 1326 : /* fall through */
+ case 1327 : /* fall through */
+ case 1352 : /* fall through */
+ case 1353 : /* fall through */
+ case 1354 : /* fall through */
+ case 1355 : /* fall through */
+ case 1356 : /* fall through */
+ case 1357 : /* fall through */
+ case 1358 : /* fall through */
+ case 1359 : /* fall through */
+ case 1384 : /* fall through */
+ case 1385 : /* fall through */
+ case 1386 : /* fall through */
+ case 1387 : /* fall through */
+ case 1388 : /* fall through */
+ case 1389 : /* fall through */
+ case 1390 : /* fall through */
+ case 1391 : /* fall through */
+ case 1416 : /* fall through */
+ case 1417 : /* fall through */
+ case 1418 : /* fall through */
+ case 1419 : /* fall through */
+ case 1420 : /* fall through */
+ case 1421 : /* fall through */
+ case 1422 : /* fall through */
+ case 1423 : /* fall through */
+ case 1448 : /* fall through */
+ case 1449 : /* fall through */
+ case 1450 : /* fall through */
+ case 1451 : /* fall through */
+ case 1452 : /* fall through */
+ case 1453 : /* fall through */
+ case 1454 : /* fall through */
+ case 1455 : /* fall through */
+ case 1480 : /* fall through */
+ case 1481 : /* fall through */
+ case 1482 : /* fall through */
+ case 1483 : /* fall through */
+ case 1484 : /* fall through */
+ case 1485 : /* fall through */
+ case 1486 : /* fall through */
+ case 1487 : /* fall through */
+ case 1512 : /* fall through */
+ case 1513 : /* fall through */
+ case 1514 : /* fall through */
+ case 1515 : /* fall through */
+ case 1516 : /* fall through */
+ case 1517 : /* fall through */
+ case 1518 : /* fall through */
+ case 1519 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 25) & (3 << 0)));
+ switch (val)
+ {
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8180000) == 0x68080000)
+ { itype = ARC600F_INSN_SUB_S_CBU3; goto extract_sfmt_add_s_cbu3; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 :
+ if ((entire_insn & 0xfe000000) == 0xc8000000)
+ { itype = ARC600F_INSN_LD_S_GPREL; goto extract_sfmt_ld_s_gprel; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 9 :
+ if ((entire_insn & 0xfe000000) == 0xca000000)
+ { itype = ARC600F_INSN_LDB_S_GPREL; goto extract_sfmt_ldb_s_gprel; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 10 :
+ if ((entire_insn & 0xfe000000) == 0xcc000000)
+ { itype = ARC600F_INSN_LDW_S_GPREL; goto extract_sfmt_ldw_s_gprel; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 11 :
+ if ((entire_insn & 0xfe000000) == 0xce000000)
+ { itype = ARC600F_INSN_ADD_S_GP; goto extract_sfmt_add_s_gp; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xe8000000)
+ { itype = ARC600F_INSN_BRCC_S; goto extract_sfmt_brcc_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1296 : /* fall through */
+ case 1297 : /* fall through */
+ case 1298 : /* fall through */
+ case 1299 : /* fall through */
+ case 1300 : /* fall through */
+ case 1301 : /* fall through */
+ case 1302 : /* fall through */
+ case 1303 : /* fall through */
+ case 1328 : /* fall through */
+ case 1329 : /* fall through */
+ case 1330 : /* fall through */
+ case 1331 : /* fall through */
+ case 1332 : /* fall through */
+ case 1333 : /* fall through */
+ case 1334 : /* fall through */
+ case 1335 : /* fall through */
+ case 1360 : /* fall through */
+ case 1361 : /* fall through */
+ case 1362 : /* fall through */
+ case 1363 : /* fall through */
+ case 1364 : /* fall through */
+ case 1365 : /* fall through */
+ case 1366 : /* fall through */
+ case 1367 : /* fall through */
+ case 1392 : /* fall through */
+ case 1393 : /* fall through */
+ case 1394 : /* fall through */
+ case 1395 : /* fall through */
+ case 1396 : /* fall through */
+ case 1397 : /* fall through */
+ case 1398 : /* fall through */
+ case 1399 : /* fall through */
+ case 1424 : /* fall through */
+ case 1425 : /* fall through */
+ case 1426 : /* fall through */
+ case 1427 : /* fall through */
+ case 1428 : /* fall through */
+ case 1429 : /* fall through */
+ case 1430 : /* fall through */
+ case 1431 : /* fall through */
+ case 1456 : /* fall through */
+ case 1457 : /* fall through */
+ case 1458 : /* fall through */
+ case 1459 : /* fall through */
+ case 1460 : /* fall through */
+ case 1461 : /* fall through */
+ case 1462 : /* fall through */
+ case 1463 : /* fall through */
+ case 1488 : /* fall through */
+ case 1489 : /* fall through */
+ case 1490 : /* fall through */
+ case 1491 : /* fall through */
+ case 1492 : /* fall through */
+ case 1493 : /* fall through */
+ case 1494 : /* fall through */
+ case 1495 : /* fall through */
+ case 1520 : /* fall through */
+ case 1521 : /* fall through */
+ case 1522 : /* fall through */
+ case 1523 : /* fall through */
+ case 1524 : /* fall through */
+ case 1525 : /* fall through */
+ case 1526 : /* fall through */
+ case 1527 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 25) & (3 << 0)));
+ switch (val)
+ {
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8180000) == 0x68100000)
+ { itype = ARC600F_INSN_ASL_S_CBU3; goto extract_sfmt_add_s_cbu3; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 :
+ if ((entire_insn & 0xfe000000) == 0xc8000000)
+ { itype = ARC600F_INSN_LD_S_GPREL; goto extract_sfmt_ld_s_gprel; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 9 :
+ if ((entire_insn & 0xfe000000) == 0xca000000)
+ { itype = ARC600F_INSN_LDB_S_GPREL; goto extract_sfmt_ldb_s_gprel; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 10 :
+ if ((entire_insn & 0xfe000000) == 0xcc000000)
+ { itype = ARC600F_INSN_LDW_S_GPREL; goto extract_sfmt_ldw_s_gprel; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 11 :
+ if ((entire_insn & 0xfe000000) == 0xce000000)
+ { itype = ARC600F_INSN_ADD_S_GP; goto extract_sfmt_add_s_gp; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xe8000000)
+ { itype = ARC600F_INSN_BRCC_S; goto extract_sfmt_brcc_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1304 : /* fall through */
+ case 1305 : /* fall through */
+ case 1306 : /* fall through */
+ case 1307 : /* fall through */
+ case 1308 : /* fall through */
+ case 1309 : /* fall through */
+ case 1310 : /* fall through */
+ case 1311 : /* fall through */
+ case 1336 : /* fall through */
+ case 1337 : /* fall through */
+ case 1338 : /* fall through */
+ case 1339 : /* fall through */
+ case 1340 : /* fall through */
+ case 1341 : /* fall through */
+ case 1342 : /* fall through */
+ case 1343 : /* fall through */
+ case 1368 : /* fall through */
+ case 1369 : /* fall through */
+ case 1370 : /* fall through */
+ case 1371 : /* fall through */
+ case 1372 : /* fall through */
+ case 1373 : /* fall through */
+ case 1374 : /* fall through */
+ case 1375 : /* fall through */
+ case 1400 : /* fall through */
+ case 1401 : /* fall through */
+ case 1402 : /* fall through */
+ case 1403 : /* fall through */
+ case 1404 : /* fall through */
+ case 1405 : /* fall through */
+ case 1406 : /* fall through */
+ case 1407 : /* fall through */
+ case 1432 : /* fall through */
+ case 1433 : /* fall through */
+ case 1434 : /* fall through */
+ case 1435 : /* fall through */
+ case 1436 : /* fall through */
+ case 1437 : /* fall through */
+ case 1438 : /* fall through */
+ case 1439 : /* fall through */
+ case 1464 : /* fall through */
+ case 1465 : /* fall through */
+ case 1466 : /* fall through */
+ case 1467 : /* fall through */
+ case 1468 : /* fall through */
+ case 1469 : /* fall through */
+ case 1470 : /* fall through */
+ case 1471 : /* fall through */
+ case 1496 : /* fall through */
+ case 1497 : /* fall through */
+ case 1498 : /* fall through */
+ case 1499 : /* fall through */
+ case 1500 : /* fall through */
+ case 1501 : /* fall through */
+ case 1502 : /* fall through */
+ case 1503 : /* fall through */
+ case 1528 : /* fall through */
+ case 1529 : /* fall through */
+ case 1530 : /* fall through */
+ case 1531 : /* fall through */
+ case 1532 : /* fall through */
+ case 1533 : /* fall through */
+ case 1534 : /* fall through */
+ case 1535 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 25) & (3 << 0)));
+ switch (val)
+ {
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8180000) == 0x68180000)
+ { itype = ARC600F_INSN_ASR_S_CBU3; goto extract_sfmt_add_s_cbu3; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 :
+ if ((entire_insn & 0xfe000000) == 0xc8000000)
+ { itype = ARC600F_INSN_LD_S_GPREL; goto extract_sfmt_ld_s_gprel; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 9 :
+ if ((entire_insn & 0xfe000000) == 0xca000000)
+ { itype = ARC600F_INSN_LDB_S_GPREL; goto extract_sfmt_ldb_s_gprel; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 10 :
+ if ((entire_insn & 0xfe000000) == 0xcc000000)
+ { itype = ARC600F_INSN_LDW_S_GPREL; goto extract_sfmt_ldw_s_gprel; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 11 :
+ if ((entire_insn & 0xfe000000) == 0xce000000)
+ { itype = ARC600F_INSN_ADD_S_GP; goto extract_sfmt_add_s_gp; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xe8000000)
+ { itype = ARC600F_INSN_BRCC_S; goto extract_sfmt_brcc_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1536 : /* fall through */
+ case 1537 : /* fall through */
+ case 1538 : /* fall through */
+ case 1539 : /* fall through */
+ case 1540 : /* fall through */
+ case 1541 : /* fall through */
+ case 1542 : /* fall through */
+ case 1543 : /* fall through */
+ case 1568 : /* fall through */
+ case 1569 : /* fall through */
+ case 1570 : /* fall through */
+ case 1571 : /* fall through */
+ case 1572 : /* fall through */
+ case 1573 : /* fall through */
+ case 1574 : /* fall through */
+ case 1575 : /* fall through */
+ case 1600 : /* fall through */
+ case 1601 : /* fall through */
+ case 1602 : /* fall through */
+ case 1603 : /* fall through */
+ case 1604 : /* fall through */
+ case 1605 : /* fall through */
+ case 1606 : /* fall through */
+ case 1607 : /* fall through */
+ case 1632 : /* fall through */
+ case 1633 : /* fall through */
+ case 1634 : /* fall through */
+ case 1635 : /* fall through */
+ case 1636 : /* fall through */
+ case 1637 : /* fall through */
+ case 1638 : /* fall through */
+ case 1639 : /* fall through */
+ case 1664 : /* fall through */
+ case 1665 : /* fall through */
+ case 1666 : /* fall through */
+ case 1667 : /* fall through */
+ case 1668 : /* fall through */
+ case 1669 : /* fall through */
+ case 1670 : /* fall through */
+ case 1671 : /* fall through */
+ case 1696 : /* fall through */
+ case 1697 : /* fall through */
+ case 1698 : /* fall through */
+ case 1699 : /* fall through */
+ case 1700 : /* fall through */
+ case 1701 : /* fall through */
+ case 1702 : /* fall through */
+ case 1703 : /* fall through */
+ case 1728 : /* fall through */
+ case 1729 : /* fall through */
+ case 1730 : /* fall through */
+ case 1731 : /* fall through */
+ case 1732 : /* fall through */
+ case 1733 : /* fall through */
+ case 1734 : /* fall through */
+ case 1735 : /* fall through */
+ case 1760 : /* fall through */
+ case 1761 : /* fall through */
+ case 1762 : /* fall through */
+ case 1763 : /* fall through */
+ case 1764 : /* fall through */
+ case 1765 : /* fall through */
+ case 1766 : /* fall through */
+ case 1767 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x70000000)
+ { itype = ARC600F_INSN_ADD_S_MCAH; goto extract_sfmt_add_s_mcah; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd0000000)
+ { itype = ARC600F_INSN_LD_S_PCREL; goto extract_sfmt_ld_s_pcrel; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ {
+ unsigned int val = (((insn >> 25) & (3 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xf0000000)
+ { itype = ARC600F_INSN_B_S; goto extract_sfmt_b_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xfe000000) == 0xf6000000)
+ { itype = ARC600F_INSN_BCC_S; goto extract_sfmt_bcc_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1544 : /* fall through */
+ case 1545 : /* fall through */
+ case 1546 : /* fall through */
+ case 1547 : /* fall through */
+ case 1548 : /* fall through */
+ case 1549 : /* fall through */
+ case 1550 : /* fall through */
+ case 1551 : /* fall through */
+ case 1576 : /* fall through */
+ case 1577 : /* fall through */
+ case 1578 : /* fall through */
+ case 1579 : /* fall through */
+ case 1580 : /* fall through */
+ case 1581 : /* fall through */
+ case 1582 : /* fall through */
+ case 1583 : /* fall through */
+ case 1608 : /* fall through */
+ case 1609 : /* fall through */
+ case 1610 : /* fall through */
+ case 1611 : /* fall through */
+ case 1612 : /* fall through */
+ case 1613 : /* fall through */
+ case 1614 : /* fall through */
+ case 1615 : /* fall through */
+ case 1640 : /* fall through */
+ case 1641 : /* fall through */
+ case 1642 : /* fall through */
+ case 1643 : /* fall through */
+ case 1644 : /* fall through */
+ case 1645 : /* fall through */
+ case 1646 : /* fall through */
+ case 1647 : /* fall through */
+ case 1672 : /* fall through */
+ case 1673 : /* fall through */
+ case 1674 : /* fall through */
+ case 1675 : /* fall through */
+ case 1676 : /* fall through */
+ case 1677 : /* fall through */
+ case 1678 : /* fall through */
+ case 1679 : /* fall through */
+ case 1704 : /* fall through */
+ case 1705 : /* fall through */
+ case 1706 : /* fall through */
+ case 1707 : /* fall through */
+ case 1708 : /* fall through */
+ case 1709 : /* fall through */
+ case 1710 : /* fall through */
+ case 1711 : /* fall through */
+ case 1736 : /* fall through */
+ case 1737 : /* fall through */
+ case 1738 : /* fall through */
+ case 1739 : /* fall through */
+ case 1740 : /* fall through */
+ case 1741 : /* fall through */
+ case 1742 : /* fall through */
+ case 1743 : /* fall through */
+ case 1768 : /* fall through */
+ case 1769 : /* fall through */
+ case 1770 : /* fall through */
+ case 1771 : /* fall through */
+ case 1772 : /* fall through */
+ case 1773 : /* fall through */
+ case 1774 : /* fall through */
+ case 1775 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x70080000)
+ { itype = ARC600F_INSN_MOV_S_MCAH; goto extract_sfmt_mov_s_mcah; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd0000000)
+ { itype = ARC600F_INSN_LD_S_PCREL; goto extract_sfmt_ld_s_pcrel; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ {
+ unsigned int val = (((insn >> 25) & (3 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xf0000000)
+ { itype = ARC600F_INSN_B_S; goto extract_sfmt_b_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xfe000000) == 0xf6000000)
+ { itype = ARC600F_INSN_BCC_S; goto extract_sfmt_bcc_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1552 : /* fall through */
+ case 1553 : /* fall through */
+ case 1554 : /* fall through */
+ case 1555 : /* fall through */
+ case 1556 : /* fall through */
+ case 1557 : /* fall through */
+ case 1558 : /* fall through */
+ case 1559 : /* fall through */
+ case 1584 : /* fall through */
+ case 1585 : /* fall through */
+ case 1586 : /* fall through */
+ case 1587 : /* fall through */
+ case 1588 : /* fall through */
+ case 1589 : /* fall through */
+ case 1590 : /* fall through */
+ case 1591 : /* fall through */
+ case 1616 : /* fall through */
+ case 1617 : /* fall through */
+ case 1618 : /* fall through */
+ case 1619 : /* fall through */
+ case 1620 : /* fall through */
+ case 1621 : /* fall through */
+ case 1622 : /* fall through */
+ case 1623 : /* fall through */
+ case 1648 : /* fall through */
+ case 1649 : /* fall through */
+ case 1650 : /* fall through */
+ case 1651 : /* fall through */
+ case 1652 : /* fall through */
+ case 1653 : /* fall through */
+ case 1654 : /* fall through */
+ case 1655 : /* fall through */
+ case 1680 : /* fall through */
+ case 1681 : /* fall through */
+ case 1682 : /* fall through */
+ case 1683 : /* fall through */
+ case 1684 : /* fall through */
+ case 1685 : /* fall through */
+ case 1686 : /* fall through */
+ case 1687 : /* fall through */
+ case 1712 : /* fall through */
+ case 1713 : /* fall through */
+ case 1714 : /* fall through */
+ case 1715 : /* fall through */
+ case 1716 : /* fall through */
+ case 1717 : /* fall through */
+ case 1718 : /* fall through */
+ case 1719 : /* fall through */
+ case 1744 : /* fall through */
+ case 1745 : /* fall through */
+ case 1746 : /* fall through */
+ case 1747 : /* fall through */
+ case 1748 : /* fall through */
+ case 1749 : /* fall through */
+ case 1750 : /* fall through */
+ case 1751 : /* fall through */
+ case 1776 : /* fall through */
+ case 1777 : /* fall through */
+ case 1778 : /* fall through */
+ case 1779 : /* fall through */
+ case 1780 : /* fall through */
+ case 1781 : /* fall through */
+ case 1782 : /* fall through */
+ case 1783 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x70100000)
+ { itype = ARC600F_INSN_CMP_S_MCAH; goto extract_sfmt_cmp_s_mcah; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd0000000)
+ { itype = ARC600F_INSN_LD_S_PCREL; goto extract_sfmt_ld_s_pcrel; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ {
+ unsigned int val = (((insn >> 25) & (3 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xf0000000)
+ { itype = ARC600F_INSN_B_S; goto extract_sfmt_b_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xfe000000) == 0xf6000000)
+ { itype = ARC600F_INSN_BCC_S; goto extract_sfmt_bcc_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1560 : /* fall through */
+ case 1561 : /* fall through */
+ case 1562 : /* fall through */
+ case 1563 : /* fall through */
+ case 1564 : /* fall through */
+ case 1565 : /* fall through */
+ case 1566 : /* fall through */
+ case 1567 : /* fall through */
+ case 1592 : /* fall through */
+ case 1593 : /* fall through */
+ case 1594 : /* fall through */
+ case 1595 : /* fall through */
+ case 1596 : /* fall through */
+ case 1597 : /* fall through */
+ case 1598 : /* fall through */
+ case 1599 : /* fall through */
+ case 1624 : /* fall through */
+ case 1625 : /* fall through */
+ case 1626 : /* fall through */
+ case 1627 : /* fall through */
+ case 1628 : /* fall through */
+ case 1629 : /* fall through */
+ case 1630 : /* fall through */
+ case 1631 : /* fall through */
+ case 1656 : /* fall through */
+ case 1657 : /* fall through */
+ case 1658 : /* fall through */
+ case 1659 : /* fall through */
+ case 1660 : /* fall through */
+ case 1661 : /* fall through */
+ case 1662 : /* fall through */
+ case 1663 : /* fall through */
+ case 1688 : /* fall through */
+ case 1689 : /* fall through */
+ case 1690 : /* fall through */
+ case 1691 : /* fall through */
+ case 1692 : /* fall through */
+ case 1693 : /* fall through */
+ case 1694 : /* fall through */
+ case 1695 : /* fall through */
+ case 1720 : /* fall through */
+ case 1721 : /* fall through */
+ case 1722 : /* fall through */
+ case 1723 : /* fall through */
+ case 1724 : /* fall through */
+ case 1725 : /* fall through */
+ case 1726 : /* fall through */
+ case 1727 : /* fall through */
+ case 1752 : /* fall through */
+ case 1753 : /* fall through */
+ case 1754 : /* fall through */
+ case 1755 : /* fall through */
+ case 1756 : /* fall through */
+ case 1757 : /* fall through */
+ case 1758 : /* fall through */
+ case 1759 : /* fall through */
+ case 1784 : /* fall through */
+ case 1785 : /* fall through */
+ case 1786 : /* fall through */
+ case 1787 : /* fall through */
+ case 1788 : /* fall through */
+ case 1789 : /* fall through */
+ case 1790 : /* fall through */
+ case 1791 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x70180000)
+ { itype = ARC600F_INSN_MOV_S_MCAHB; goto extract_sfmt_mov_s_mcahb; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd0000000)
+ { itype = ARC600F_INSN_LD_S_PCREL; goto extract_sfmt_ld_s_pcrel; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ {
+ unsigned int val = (((insn >> 25) & (3 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xf0000000)
+ { itype = ARC600F_INSN_B_S; goto extract_sfmt_b_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xfe000000) == 0xf6000000)
+ { itype = ARC600F_INSN_BCC_S; goto extract_sfmt_bcc_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1792 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8ff0000) == 0x78000000)
+ { itype = ARC600F_INSN_J_S; goto extract_sfmt_j_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC600F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC600F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1793 : /* fall through */
+ case 1795 : /* fall through */
+ case 1800 : /* fall through */
+ case 1801 : /* fall through */
+ case 1802 : /* fall through */
+ case 1815 : /* fall through */
+ case 1823 : /* fall through */
+ case 1825 : /* fall through */
+ case 1827 : /* fall through */
+ case 1832 : /* fall through */
+ case 1833 : /* fall through */
+ case 1834 : /* fall through */
+ case 1847 : /* fall through */
+ case 1855 : /* fall through */
+ case 1857 : /* fall through */
+ case 1859 : /* fall through */
+ case 1864 : /* fall through */
+ case 1865 : /* fall through */
+ case 1866 : /* fall through */
+ case 1879 : /* fall through */
+ case 1887 : /* fall through */
+ case 1889 : /* fall through */
+ case 1891 : /* fall through */
+ case 1896 : /* fall through */
+ case 1897 : /* fall through */
+ case 1898 : /* fall through */
+ case 1911 : /* fall through */
+ case 1919 : /* fall through */
+ case 1920 : /* fall through */
+ case 1921 : /* fall through */
+ case 1923 : /* fall through */
+ case 1928 : /* fall through */
+ case 1929 : /* fall through */
+ case 1930 : /* fall through */
+ case 1943 : /* fall through */
+ case 1951 : /* fall through */
+ case 1952 : /* fall through */
+ case 1953 : /* fall through */
+ case 1955 : /* fall through */
+ case 1960 : /* fall through */
+ case 1961 : /* fall through */
+ case 1962 : /* fall through */
+ case 1975 : /* fall through */
+ case 1983 : /* fall through */
+ case 1985 : /* fall through */
+ case 1987 : /* fall through */
+ case 1992 : /* fall through */
+ case 1993 : /* fall through */
+ case 1994 : /* fall through */
+ case 2007 : /* fall through */
+ case 2015 : /* fall through */
+ case 2017 : /* fall through */
+ case 2019 : /* fall through */
+ case 2024 : /* fall through */
+ case 2025 : /* fall through */
+ case 2026 : /* fall through */
+ case 2039 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC600F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC600F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1794 : /* fall through */
+ case 1826 : /* fall through */
+ case 1858 : /* fall through */
+ case 1890 : /* fall through */
+ case 1922 : /* fall through */
+ case 1954 : /* fall through */
+ case 1986 : /* fall through */
+ case 2018 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x78020000)
+ { itype = ARC600F_INSN_I16_GO_SUB_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC600F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC600F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1796 : /* fall through */
+ case 1828 : /* fall through */
+ case 1860 : /* fall through */
+ case 1892 : /* fall through */
+ case 1924 : /* fall through */
+ case 1956 : /* fall through */
+ case 1988 : /* fall through */
+ case 2020 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x78040000)
+ { itype = ARC600F_INSN_I16_GO_AND_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC600F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC600F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1797 : /* fall through */
+ case 1829 : /* fall through */
+ case 1861 : /* fall through */
+ case 1893 : /* fall through */
+ case 1925 : /* fall through */
+ case 1957 : /* fall through */
+ case 1989 : /* fall through */
+ case 2021 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x78050000)
+ { itype = ARC600F_INSN_I16_GO_OR_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC600F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC600F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1798 : /* fall through */
+ case 1830 : /* fall through */
+ case 1862 : /* fall through */
+ case 1894 : /* fall through */
+ case 1926 : /* fall through */
+ case 1958 : /* fall through */
+ case 1990 : /* fall through */
+ case 2022 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x78060000)
+ { itype = ARC600F_INSN_I16_GO_BIC_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC600F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC600F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1799 : /* fall through */
+ case 1831 : /* fall through */
+ case 1863 : /* fall through */
+ case 1895 : /* fall through */
+ case 1927 : /* fall through */
+ case 1959 : /* fall through */
+ case 1991 : /* fall through */
+ case 2023 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x78070000)
+ { itype = ARC600F_INSN_I16_GO_XOR_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC600F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC600F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1803 : /* fall through */
+ case 1835 : /* fall through */
+ case 1867 : /* fall through */
+ case 1899 : /* fall through */
+ case 1931 : /* fall through */
+ case 1963 : /* fall through */
+ case 1995 : /* fall through */
+ case 2027 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x780b0000)
+ { itype = ARC600F_INSN_TST_S_GO; goto extract_sfmt_tst_s_go; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC600F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC600F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1804 : /* fall through */
+ case 1836 : /* fall through */
+ case 1868 : /* fall through */
+ case 1900 : /* fall through */
+ case 1932 : /* fall through */
+ case 1964 : /* fall through */
+ case 1996 : /* fall through */
+ case 2028 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x780c0000)
+ { itype = ARC600F_INSN_MUL64_S_GO; goto extract_sfmt_mul64_s_go; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC600F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC600F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1805 : /* fall through */
+ case 1837 : /* fall through */
+ case 1869 : /* fall through */
+ case 1901 : /* fall through */
+ case 1933 : /* fall through */
+ case 1965 : /* fall through */
+ case 1997 : /* fall through */
+ case 2029 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x780d0000)
+ { itype = ARC600F_INSN_I16_GO_SEXB_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC600F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC600F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1806 : /* fall through */
+ case 1838 : /* fall through */
+ case 1870 : /* fall through */
+ case 1902 : /* fall through */
+ case 1934 : /* fall through */
+ case 1966 : /* fall through */
+ case 1998 : /* fall through */
+ case 2030 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x780e0000)
+ { itype = ARC600F_INSN_I16_GO_SEXW_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC600F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC600F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1807 : /* fall through */
+ case 1839 : /* fall through */
+ case 1871 : /* fall through */
+ case 1903 : /* fall through */
+ case 1935 : /* fall through */
+ case 1967 : /* fall through */
+ case 1999 : /* fall through */
+ case 2031 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x780f0000)
+ { itype = ARC600F_INSN_I16_GO_EXTB_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC600F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC600F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1808 : /* fall through */
+ case 1840 : /* fall through */
+ case 1872 : /* fall through */
+ case 1904 : /* fall through */
+ case 1936 : /* fall through */
+ case 1968 : /* fall through */
+ case 2000 : /* fall through */
+ case 2032 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x78100000)
+ { itype = ARC600F_INSN_I16_GO_EXTW_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC600F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC600F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1809 : /* fall through */
+ case 1841 : /* fall through */
+ case 1873 : /* fall through */
+ case 1905 : /* fall through */
+ case 1937 : /* fall through */
+ case 1969 : /* fall through */
+ case 2001 : /* fall through */
+ case 2033 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x78110000)
+ { itype = ARC600F_INSN_I16_GO_ABS_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC600F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC600F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1810 : /* fall through */
+ case 1842 : /* fall through */
+ case 1874 : /* fall through */
+ case 1906 : /* fall through */
+ case 1938 : /* fall through */
+ case 1970 : /* fall through */
+ case 2002 : /* fall through */
+ case 2034 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x78120000)
+ { itype = ARC600F_INSN_I16_GO_NOT_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC600F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC600F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1811 : /* fall through */
+ case 1843 : /* fall through */
+ case 1875 : /* fall through */
+ case 1907 : /* fall through */
+ case 1939 : /* fall through */
+ case 1971 : /* fall through */
+ case 2003 : /* fall through */
+ case 2035 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x78130000)
+ { itype = ARC600F_INSN_I16_GO_NEG_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC600F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC600F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1812 : /* fall through */
+ case 1844 : /* fall through */
+ case 1876 : /* fall through */
+ case 1908 : /* fall through */
+ case 1940 : /* fall through */
+ case 1972 : /* fall through */
+ case 2004 : /* fall through */
+ case 2036 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x78140000)
+ { itype = ARC600F_INSN_I16_GO_ADD1_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC600F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC600F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1813 : /* fall through */
+ case 1845 : /* fall through */
+ case 1877 : /* fall through */
+ case 1909 : /* fall through */
+ case 1941 : /* fall through */
+ case 1973 : /* fall through */
+ case 2005 : /* fall through */
+ case 2037 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x78150000)
+ { itype = ARC600F_INSN_I16_GO_ADD2_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC600F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC600F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1814 : /* fall through */
+ case 1846 : /* fall through */
+ case 1878 : /* fall through */
+ case 1910 : /* fall through */
+ case 1942 : /* fall through */
+ case 1974 : /* fall through */
+ case 2006 : /* fall through */
+ case 2038 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x78160000)
+ { itype = ARC600F_INSN_I16_GO_ADD3_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC600F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC600F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1816 : /* fall through */
+ case 1848 : /* fall through */
+ case 1880 : /* fall through */
+ case 1912 : /* fall through */
+ case 1944 : /* fall through */
+ case 1976 : /* fall through */
+ case 2008 : /* fall through */
+ case 2040 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x78180000)
+ { itype = ARC600F_INSN_I16_GO_ASLM_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC600F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC600F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1817 : /* fall through */
+ case 1849 : /* fall through */
+ case 1881 : /* fall through */
+ case 1913 : /* fall through */
+ case 1945 : /* fall through */
+ case 1977 : /* fall through */
+ case 2009 : /* fall through */
+ case 2041 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x78190000)
+ { itype = ARC600F_INSN_I16_GO_LSRM_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC600F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC600F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1818 : /* fall through */
+ case 1850 : /* fall through */
+ case 1882 : /* fall through */
+ case 1914 : /* fall through */
+ case 1946 : /* fall through */
+ case 1978 : /* fall through */
+ case 2010 : /* fall through */
+ case 2042 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x781a0000)
+ { itype = ARC600F_INSN_I16_GO_ASRM_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC600F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC600F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1819 : /* fall through */
+ case 1851 : /* fall through */
+ case 1883 : /* fall through */
+ case 1915 : /* fall through */
+ case 1947 : /* fall through */
+ case 1979 : /* fall through */
+ case 2011 : /* fall through */
+ case 2043 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x781b0000)
+ { itype = ARC600F_INSN_I16_GO_ASL_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC600F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC600F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1820 : /* fall through */
+ case 1852 : /* fall through */
+ case 1884 : /* fall through */
+ case 1916 : /* fall through */
+ case 1948 : /* fall through */
+ case 1980 : /* fall through */
+ case 2012 : /* fall through */
+ case 2044 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x781c0000)
+ { itype = ARC600F_INSN_I16_GO_ASR_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC600F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC600F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1821 : /* fall through */
+ case 1853 : /* fall through */
+ case 1885 : /* fall through */
+ case 1917 : /* fall through */
+ case 1949 : /* fall through */
+ case 1981 : /* fall through */
+ case 2013 : /* fall through */
+ case 2045 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x781d0000)
+ { itype = ARC600F_INSN_I16_GO_LSR_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC600F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC600F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1822 : /* fall through */
+ case 1854 : /* fall through */
+ case 1886 : /* fall through */
+ case 1918 : /* fall through */
+ case 1950 : /* fall through */
+ case 1982 : /* fall through */
+ case 2014 : /* fall through */
+ case 2046 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x781e0000)
+ { itype = ARC600F_INSN_TRAP_S; goto extract_sfmt_trap_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC600F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC600F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1824 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8ff0000) == 0x78200000)
+ { itype = ARC600F_INSN_J_S_D; goto extract_sfmt_j_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC600F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC600F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1856 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8ff0000) == 0x78400000)
+ { itype = ARC600F_INSN_JL_S; goto extract_sfmt_jl_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC600F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC600F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1888 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8ff0000) == 0x78600000)
+ { itype = ARC600F_INSN_JL_S_D; goto extract_sfmt_jl_s_d; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC600F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC600F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1984 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8ff0000) == 0x78c00000)
+ { itype = ARC600F_INSN_SUB_S_GO_SUB_NE; goto extract_sfmt_sub_s_go_sub_ne; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC600F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC600F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 2016 :
+ {
+ unsigned int val = (((insn >> 27) & (1 << 4)) | ((insn >> 26) & (1 << 3)) | ((insn >> 24) & (7 << 0)));
+ switch (val)
+ {
+ case 8 :
+ if ((entire_insn & 0xffff0000) == 0x78e00000)
+ { itype = ARC600F_INSN_NOP_S; goto extract_sfmt_nop_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 9 :
+ if ((entire_insn & 0xffff0000) == 0x79e00000)
+ { itype = ARC600F_INSN_UNIMP_S; goto extract_sfmt_nop_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 :
+ if ((entire_insn & 0xffff0000) == 0x7ce00000)
+ { itype = ARC600F_INSN_J_SEQ__S; goto extract_sfmt_j_seq__S; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 13 :
+ if ((entire_insn & 0xffff0000) == 0x7de00000)
+ { itype = ARC600F_INSN_J_SNE__S; goto extract_sfmt_j_seq__S; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 14 :
+ if ((entire_insn & 0xffff0000) == 0x7ee00000)
+ { itype = ARC600F_INSN_J_S__S; goto extract_sfmt_j_s__S; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 15 :
+ if ((entire_insn & 0xffff0000) == 0x7fe00000)
+ { itype = ARC600F_INSN_J_S__S_D; goto extract_sfmt_j_s__S; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 16 : /* fall through */
+ case 17 : /* fall through */
+ case 18 : /* fall through */
+ case 19 : /* fall through */
+ case 20 : /* fall through */
+ case 21 : /* fall through */
+ case 22 : /* fall through */
+ case 23 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC600F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 24 : /* fall through */
+ case 25 : /* fall through */
+ case 26 : /* fall through */
+ case 27 : /* fall through */
+ case 28 : /* fall through */
+ case 29 : /* fall through */
+ case 30 : /* fall through */
+ case 31 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC600F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 2047 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xffff0000) == 0x7fff0000)
+ { itype = ARC600F_INSN_BRK_S; goto extract_sfmt_brk; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC600F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC600F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ default : itype = ARC600F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ }
+
+ /* The instruction has been decoded, now extract the fields. */
+
+ extract_sfmt_empty:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_b_s:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_b_s.f
+ UINT f_cond_i2;
+ SI f_rel10;
+
+ f_cond_i2 = EXTRACT_MSB0_UINT (insn, 32, 5, 2);
+ f_rel10 = ((((EXTRACT_MSB0_INT (insn, 32, 7, 9)) << (1))) + (((pc) & (-4))));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_i2) = f_cond_i2;
+ FLD (i_label10) = f_rel10;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_b_s", "f_cond_i2 0x%x", 'x', f_cond_i2, "label10 0x%x", 'x', f_rel10, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_bcc_s:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_bcc_s.f
+ UINT f_cond_i3;
+ SI f_rel7;
+
+ f_cond_i3 = EXTRACT_MSB0_UINT (insn, 32, 7, 3);
+ f_rel7 = ((((EXTRACT_MSB0_INT (insn, 32, 10, 6)) << (1))) + (((pc) & (-4))));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_i3) = f_cond_i3;
+ FLD (i_label7) = f_rel7;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcc_s", "f_cond_i3 0x%x", 'x', f_cond_i3, "label7 0x%x", 'x', f_rel7, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_brcc_s:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_brcc_s.f
+ UINT f_op__b;
+ UINT f_brscond;
+ SI f_rel8;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_brscond = EXTRACT_MSB0_UINT (insn, 32, 8, 1);
+ f_rel8 = ((((EXTRACT_MSB0_INT (insn, 32, 9, 7)) << (1))) + (((pc) & (-4))));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_brscond) = f_brscond;
+ FLD (i_label8) = f_rel8;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_brcc_s", "f_op__b 0x%x", 'x', f_op__b, "f_brscond 0x%x", 'x', f_brscond, "label8 0x%x", 'x', f_rel8, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_bcc_l:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_bcc_l.f
+ UINT f_d21l;
+ INT f_d21h;
+ UINT f_cond_Q;
+ INT f_rel21;
+
+ f_d21l = EXTRACT_MSB0_UINT (insn, 32, 5, 10);
+ f_d21h = EXTRACT_MSB0_INT (insn, 32, 16, 10);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_rel21 = ((((((f_d21l) << (1))) | (((f_d21h) << (11))))) + (((pc) & (-4))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (i_label21) = f_rel21;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcc_l", "f_cond_Q 0x%x", 'x', f_cond_Q, "label21 0x%x", 'x', f_rel21, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_b_l:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_b_l.f
+ UINT f_d21l;
+ UINT f_d25m;
+ INT f_d25h;
+ INT f_rel25;
+
+ f_d21l = EXTRACT_MSB0_UINT (insn, 32, 5, 10);
+ f_d25m = EXTRACT_MSB0_UINT (insn, 32, 16, 10);
+ f_d25h = EXTRACT_MSB0_INT (insn, 32, 28, 4);
+{
+ f_rel25 = ((((((((f_d21l) << (1))) | (((f_d25m) << (11))))) | (((f_d25h) << (21))))) + (((pc) & (-4))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_label25) = f_rel25;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_b_l", "label25 0x%x", 'x', f_rel25, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_brcc_RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_brcc_RC.f
+ UINT f_op__b;
+ UINT f_d9l;
+ INT f_d9h;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_brcond;
+ UINT f_op_B;
+ INT f_rel9;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_d9l = EXTRACT_MSB0_UINT (insn, 32, 8, 7);
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_brcond = EXTRACT_MSB0_UINT (insn, 32, 28, 4);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_rel9 = ((((((f_d9l) << (1))) | (((f_d9h) << (8))))) + (((pc) & (-4))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_brcond) = f_brcond;
+ FLD (i_label9) = f_rel9;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_brcc_RC", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_brcond 0x%x", 'x', f_brcond, "label9 0x%x", 'x', f_rel9, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_brcc_U6:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_brcc_U6.f
+ UINT f_op__b;
+ UINT f_d9l;
+ INT f_d9h;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_brcond;
+ UINT f_op_B;
+ INT f_rel9;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_d9l = EXTRACT_MSB0_UINT (insn, 32, 8, 7);
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_brcond = EXTRACT_MSB0_UINT (insn, 32, 28, 4);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_rel9 = ((((((f_d9l) << (1))) | (((f_d9h) << (8))))) + (((pc) & (-4))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_brcond) = f_brcond;
+ FLD (f_u6) = f_u6;
+ FLD (i_label9) = f_rel9;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_brcc_U6", "f_op_B 0x%x", 'x', f_op_B, "f_brcond 0x%x", 'x', f_brcond, "f_u6 0x%x", 'x', f_u6, "label9 0x%x", 'x', f_rel9, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_bl_s:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_bl_s.f
+ SI f_rel13bl;
+
+ f_rel13bl = ((((EXTRACT_MSB0_INT (insn, 32, 5, 11)) << (2))) + (((pc) & (-4))));
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_label13a) = f_rel13bl;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl_s", "label13a 0x%x", 'x', f_rel13bl, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_blcc:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_blcc.f
+ UINT f_d21bl;
+ INT f_d21h;
+ UINT f_cond_Q;
+ INT f_rel21bl;
+
+ f_d21bl = EXTRACT_MSB0_UINT (insn, 32, 5, 9);
+ f_d21h = EXTRACT_MSB0_INT (insn, 32, 16, 10);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_rel21bl = ((((((f_d21bl) << (2))) | (((f_d21h) << (11))))) + (((pc) & (-4))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (i_label21a) = f_rel21bl;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_blcc", "f_cond_Q 0x%x", 'x', f_cond_Q, "label21a 0x%x", 'x', f_rel21bl, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_bl:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_bl.f
+ UINT f_d21bl;
+ UINT f_d25m;
+ INT f_d25h;
+ INT f_rel25bl;
+
+ f_d21bl = EXTRACT_MSB0_UINT (insn, 32, 5, 9);
+ f_d25m = EXTRACT_MSB0_UINT (insn, 32, 16, 10);
+ f_d25h = EXTRACT_MSB0_INT (insn, 32, 28, 4);
+{
+ f_rel25bl = ((((((((f_d21bl) << (2))) | (((f_d25m) << (11))))) | (((f_d25h) << (21))))) + (((pc) & (-4))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_label25a) = f_rel25bl;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl", "label25a 0x%x", 'x', f_rel25bl, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_bl_d:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_bl.f
+ UINT f_d21bl;
+ UINT f_d25m;
+ INT f_d25h;
+ INT f_rel25bl;
+
+ f_d21bl = EXTRACT_MSB0_UINT (insn, 32, 5, 9);
+ f_d25m = EXTRACT_MSB0_UINT (insn, 32, 16, 10);
+ f_d25h = EXTRACT_MSB0_INT (insn, 32, 28, 4);
+{
+ f_rel25bl = ((((((((f_d21bl) << (2))) | (((f_d25m) << (11))))) | (((f_d25h) << (21))))) + (((pc) & (-4))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_label25a) = f_rel25bl;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl_d", "label25a 0x%x", 'x', f_rel25bl, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ld_abs:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ UINT f_op__b;
+ UINT f_u8;
+ INT f_d9h;
+ UINT f_B_5_3;
+ UINT f_op_A;
+ UINT f_op_B;
+ INT f_s9;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8);
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s9 = ((f_u8) | (((f_d9h) << (8))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s9) = f_s9;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_abs", "f_op_B 0x%x", 'x', f_op_B, "f_s9 0x%x", 'x', f_s9, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ld__AW_abs:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ UINT f_op__b;
+ UINT f_u8;
+ INT f_d9h;
+ UINT f_B_5_3;
+ UINT f_op_A;
+ UINT f_op_B;
+ INT f_s9;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8);
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s9 = ((f_u8) | (((f_d9h) << (8))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s9) = f_s9;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld__AW_abs", "f_op_B 0x%x", 'x', f_op_B, "f_s9 0x%x", 'x', f_s9, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ld_abc:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_abc", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ld__AW_abc:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld__AW_abc", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ld_s_abc:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ UINT f_op__b;
+ UINT f_op__c;
+ UINT f_op__a;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_op__a = EXTRACT_MSB0_UINT (insn, 32, 13, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_op__c) = f_op__c;
+ FLD (f_op__a) = f_op__a;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_s_abc", "f_op__b 0x%x", 'x', f_op__b, "f_op__c 0x%x", 'x', f_op__c, "f_op__a 0x%x", 'x', f_op__a, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ld_s_abu:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ UINT f_op__b;
+ UINT f_op__c;
+ SI f_u5x4;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_u5x4 = ((EXTRACT_MSB0_UINT (insn, 32, 11, 5)) << (2));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_u5x4) = f_u5x4;
+ FLD (f_op__c) = f_op__c;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_s_abu", "f_op__b 0x%x", 'x', f_op__b, "f_u5x4 0x%x", 'x', f_u5x4, "f_op__c 0x%x", 'x', f_op__c, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ld_s_absp:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ UINT f_op__b;
+ SI f_u5x4;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u5x4 = ((EXTRACT_MSB0_UINT (insn, 32, 11, 5)) << (2));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_u5x4) = f_u5x4;
+ FLD (f_op__b) = f_op__b;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_s_absp", "f_u5x4 0x%x", 'x', f_u5x4, "f_op__b 0x%x", 'x', f_op__b, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ld_s_gprel:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_gprel.f
+ SI f_s9x4;
+
+ f_s9x4 = ((EXTRACT_MSB0_INT (insn, 32, 7, 9)) << (2));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_s9x4) = f_s9x4;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_s_gprel", "f_s9x4 0x%x", 'x', f_s9x4, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ld_s_pcrel:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_pcrel.f
+ UINT f_op__b;
+ SI f_u8x4;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u8x4 = ((EXTRACT_MSB0_UINT (insn, 32, 8, 8)) << (2));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_u8x4) = f_u8x4;
+ FLD (f_op__b) = f_op__b;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_s_pcrel", "f_u8x4 0x%x", 'x', f_u8x4, "f_op__b 0x%x", 'x', f_op__b, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldb_abs:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ UINT f_op__b;
+ UINT f_u8;
+ INT f_d9h;
+ UINT f_B_5_3;
+ UINT f_op_A;
+ UINT f_op_B;
+ INT f_s9;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8);
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s9 = ((f_u8) | (((f_d9h) << (8))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s9) = f_s9;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_abs", "f_op_B 0x%x", 'x', f_op_B, "f_s9 0x%x", 'x', f_s9, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldb__AW_abs:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ UINT f_op__b;
+ UINT f_u8;
+ INT f_d9h;
+ UINT f_B_5_3;
+ UINT f_op_A;
+ UINT f_op_B;
+ INT f_s9;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8);
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s9 = ((f_u8) | (((f_d9h) << (8))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s9) = f_s9;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb__AW_abs", "f_op_B 0x%x", 'x', f_op_B, "f_s9 0x%x", 'x', f_s9, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldb_as_abs:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_as_abs", "f_op_B 0x%x", 'x', f_op_B, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldb_abc:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_abc", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldb__AW_abc:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb__AW_abc", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldb_as_abc:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_as_abc", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldb_s_abc:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ UINT f_op__b;
+ UINT f_op__c;
+ UINT f_op__a;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_op__a = EXTRACT_MSB0_UINT (insn, 32, 13, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_op__c) = f_op__c;
+ FLD (f_op__a) = f_op__a;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_s_abc", "f_op__b 0x%x", 'x', f_op__b, "f_op__c 0x%x", 'x', f_op__c, "f_op__a 0x%x", 'x', f_op__a, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldb_s_abu:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ UINT f_op__b;
+ UINT f_op__c;
+ UINT f_u5;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_u5 = EXTRACT_MSB0_UINT (insn, 32, 11, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_u5) = f_u5;
+ FLD (f_op__c) = f_op__c;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_s_abu", "f_op__b 0x%x", 'x', f_op__b, "f_u5 0x%x", 'x', f_u5, "f_op__c 0x%x", 'x', f_op__c, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldb_s_absp:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ UINT f_op__b;
+ SI f_u5x4;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u5x4 = ((EXTRACT_MSB0_UINT (insn, 32, 11, 5)) << (2));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_u5x4) = f_u5x4;
+ FLD (f_op__b) = f_op__b;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_s_absp", "f_u5x4 0x%x", 'x', f_u5x4, "f_op__b 0x%x", 'x', f_op__b, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldb_s_gprel:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ldb_s_gprel.f
+ INT f_s9x1;
+
+ f_s9x1 = EXTRACT_MSB0_INT (insn, 32, 7, 9);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_s9x1) = f_s9x1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_s_gprel", "f_s9x1 0x%x", 'x', f_s9x1, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldw_abs:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ UINT f_op__b;
+ UINT f_u8;
+ INT f_d9h;
+ UINT f_B_5_3;
+ UINT f_op_A;
+ UINT f_op_B;
+ INT f_s9;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8);
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s9 = ((f_u8) | (((f_d9h) << (8))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s9) = f_s9;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldw_abs", "f_op_B 0x%x", 'x', f_op_B, "f_s9 0x%x", 'x', f_s9, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldw__AW_abs:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ UINT f_op__b;
+ UINT f_u8;
+ INT f_d9h;
+ UINT f_B_5_3;
+ UINT f_op_A;
+ UINT f_op_B;
+ INT f_s9;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8);
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s9 = ((f_u8) | (((f_d9h) << (8))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s9) = f_s9;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldw__AW_abs", "f_op_B 0x%x", 'x', f_op_B, "f_s9 0x%x", 'x', f_s9, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldw_abc:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldw_abc", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldw__AW_abc:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldw__AW_abc", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldw_s_abc:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ UINT f_op__b;
+ UINT f_op__c;
+ UINT f_op__a;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_op__a = EXTRACT_MSB0_UINT (insn, 32, 13, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_op__c) = f_op__c;
+ FLD (f_op__a) = f_op__a;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldw_s_abc", "f_op__b 0x%x", 'x', f_op__b, "f_op__c 0x%x", 'x', f_op__c, "f_op__a 0x%x", 'x', f_op__a, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldw_s_abu:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ldw_s_abu.f
+ UINT f_op__b;
+ UINT f_op__c;
+ SI f_u5x2;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_u5x2 = ((EXTRACT_MSB0_UINT (insn, 32, 11, 5)) << (1));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_u5x2) = f_u5x2;
+ FLD (f_op__c) = f_op__c;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldw_s_abu", "f_op__b 0x%x", 'x', f_op__b, "f_u5x2 0x%x", 'x', f_u5x2, "f_op__c 0x%x", 'x', f_op__c, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldw_s_gprel:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ldw_s_gprel.f
+ SI f_s9x2;
+
+ f_s9x2 = ((EXTRACT_MSB0_INT (insn, 32, 7, 9)) << (1));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_s9x2) = f_s9x2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldw_s_gprel", "f_s9x2 0x%x", 'x', f_s9x2, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_st_abs:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_u8;
+ INT f_d9h;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+ INT f_s9;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8);
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s9 = ((f_u8) | (((f_d9h) << (8))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_s9) = f_s9;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_abs", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_s9 0x%x", 'x', f_s9, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_st__AW_abs:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_u8;
+ INT f_d9h;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+ INT f_s9;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8);
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s9 = ((f_u8) | (((f_d9h) << (8))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_s9) = f_s9;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st__AW_abs", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_s9 0x%x", 'x', f_s9, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_st_s_abu:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ UINT f_op__b;
+ UINT f_op__c;
+ SI f_u5x4;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_u5x4 = ((EXTRACT_MSB0_UINT (insn, 32, 11, 5)) << (2));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_op__c) = f_op__c;
+ FLD (f_u5x4) = f_u5x4;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_s_abu", "f_op__b 0x%x", 'x', f_op__b, "f_op__c 0x%x", 'x', f_op__c, "f_u5x4 0x%x", 'x', f_u5x4, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_st_s_absp:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ UINT f_op__b;
+ SI f_u5x4;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u5x4 = ((EXTRACT_MSB0_UINT (insn, 32, 11, 5)) << (2));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_u5x4) = f_u5x4;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_s_absp", "f_op__b 0x%x", 'x', f_op__b, "f_u5x4 0x%x", 'x', f_u5x4, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stb_abs:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_u8;
+ INT f_d9h;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+ INT f_s9;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8);
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s9 = ((f_u8) | (((f_d9h) << (8))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_s9) = f_s9;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_abs", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_s9 0x%x", 'x', f_s9, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stb__AW_abs:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_u8;
+ INT f_d9h;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+ INT f_s9;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8);
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s9 = ((f_u8) | (((f_d9h) << (8))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_s9) = f_s9;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb__AW_abs", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_s9 0x%x", 'x', f_s9, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stb_as_abs:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_as_abs", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stb_s_abu:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ UINT f_op__b;
+ UINT f_op__c;
+ UINT f_u5;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_u5 = EXTRACT_MSB0_UINT (insn, 32, 11, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_op__c) = f_op__c;
+ FLD (f_u5) = f_u5;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_s_abu", "f_op__b 0x%x", 'x', f_op__b, "f_op__c 0x%x", 'x', f_op__c, "f_u5 0x%x", 'x', f_u5, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stb_s_absp:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ UINT f_op__b;
+ SI f_u5x4;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u5x4 = ((EXTRACT_MSB0_UINT (insn, 32, 11, 5)) << (2));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_u5x4) = f_u5x4;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_s_absp", "f_op__b 0x%x", 'x', f_op__b, "f_u5x4 0x%x", 'x', f_u5x4, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stw_abs:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_u8;
+ INT f_d9h;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+ INT f_s9;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8);
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s9 = ((f_u8) | (((f_d9h) << (8))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_s9) = f_s9;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stw_abs", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_s9 0x%x", 'x', f_s9, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stw__AW_abs:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_u8;
+ INT f_d9h;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+ INT f_s9;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8);
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s9 = ((f_u8) | (((f_d9h) << (8))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_s9) = f_s9;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stw__AW_abs", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_s9 0x%x", 'x', f_s9, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stw_s_abu:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ldw_s_abu.f
+ UINT f_op__b;
+ UINT f_op__c;
+ SI f_u5x2;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_u5x2 = ((EXTRACT_MSB0_UINT (insn, 32, 11, 5)) << (1));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_op__c) = f_op__c;
+ FLD (f_u5x2) = f_u5x2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stw_s_abu", "f_op__b 0x%x", 'x', f_op__b, "f_op__c 0x%x", 'x', f_op__c, "f_u5x2 0x%x", 'x', f_u5x2, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_L_s12__RA_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_L_s12__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_ccu6__RA_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_ccu6__RA_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_L_u6__RA_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_L_u6__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_L_r_r__RA__RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_L_r_r__RA__RC", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_cc__RA__RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_cc__RA__RC", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_s_abc:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ UINT f_op__b;
+ UINT f_op__c;
+ UINT f_op__a;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_op__a = EXTRACT_MSB0_UINT (insn, 32, 13, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_op__c) = f_op__c;
+ FLD (f_op__a) = f_op__a;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_s_abc", "f_op__b 0x%x", 'x', f_op__b, "f_op__c 0x%x", 'x', f_op__c, "f_op__a 0x%x", 'x', f_op__a, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_s_cbu3:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ UINT f_op__b;
+ UINT f_op__c;
+ UINT f_u3;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_u3 = EXTRACT_MSB0_UINT (insn, 32, 13, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_u3) = f_u3;
+ FLD (f_op__c) = f_op__c;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_s_cbu3", "f_op__b 0x%x", 'x', f_op__b, "f_u3 0x%x", 'x', f_u3, "f_op__c 0x%x", 'x', f_op__c, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_s_mcah:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ UINT f_op__b;
+ UINT f_h_2_0;
+ UINT f_h_5_3;
+ UINT f_op_h;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_h_2_0 = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_h_5_3 = EXTRACT_MSB0_UINT (insn, 32, 13, 3);
+{
+ f_op_h = ((f_h_2_0) | (((f_h_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_op_h) = f_op_h;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_s_mcah", "f_op__b 0x%x", 'x', f_op__b, "f_op_h 0x%x", 'x', f_op_h, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_s_absp:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ UINT f_op__b;
+ SI f_u5x4;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u5x4 = ((EXTRACT_MSB0_UINT (insn, 32, 11, 5)) << (2));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_u5x4) = f_u5x4;
+ FLD (f_op__b) = f_op__b;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_s_absp", "f_u5x4 0x%x", 'x', f_u5x4, "f_op__b 0x%x", 'x', f_op__b, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_s_asspsp:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ SI f_u5x4;
+
+ f_u5x4 = ((EXTRACT_MSB0_UINT (insn, 32, 11, 5)) << (2));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_u5x4) = f_u5x4;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_s_asspsp", "f_u5x4 0x%x", 'x', f_u5x4, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_s_gp:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_gprel.f
+ SI f_s9x4;
+
+ f_s9x4 = ((EXTRACT_MSB0_INT (insn, 32, 7, 9)) << (2));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_s9x4) = f_s9x4;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_s_gp", "f_s9x4 0x%x", 'x', f_s9x4, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_s_r_u7:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_s_r_u7.f
+ UINT f_op__b;
+ UINT f_u7;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u7 = EXTRACT_MSB0_UINT (insn, 32, 9, 7);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_u7) = f_u7;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_s_r_u7", "f_op__b 0x%x", 'x', f_op__b, "f_u7 0x%x", 'x', f_u7, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_adc_L_s12__RA_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_adc_L_s12__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_adc_ccu6__RA_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_adc_ccu6__RA_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_adc_L_u6__RA_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_adc_L_u6__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_adc_L_r_r__RA__RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_adc_L_r_r__RA__RC", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_adc_cc__RA__RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_adc_cc__RA__RC", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_I16_GO_SUB_s_go:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ UINT f_op__b;
+ UINT f_op__c;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_op__c) = f_op__c;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_I16_GO_SUB_s_go", "f_op__b 0x%x", 'x', f_op__b, "f_op__c 0x%x", 'x', f_op__c, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sub_s_go_sub_ne:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ UINT f_op__b;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sub_s_go_sub_ne", "f_op__b 0x%x", 'x', f_op__b, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sub_s_ssb:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ UINT f_op__b;
+ UINT f_u5;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u5 = EXTRACT_MSB0_UINT (insn, 32, 11, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_u5) = f_u5;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sub_s_ssb", "f_op__b 0x%x", 'x', f_op__b, "f_u5 0x%x", 'x', f_u5, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_and_L_s12__RA_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and_L_s12__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_and_ccu6__RA_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and_ccu6__RA_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_and_L_u6__RA_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and_L_u6__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_and_L_r_r__RA__RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and_L_r_r__RA__RC", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_and_cc__RA__RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and_cc__RA__RC", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mov_L_s12_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_s12) = f_s12;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mov_L_s12_", "f_F 0x%x", 'x', f_F, "f_s12 0x%x", 'x', f_s12, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mov_ccu6_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mov_ccu6_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mov_L_u6_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mov_L_u6_", "f_F 0x%x", 'x', f_F, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mov_L_r_r__RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mov_L_r_r__RC", "f_F 0x%x", 'x', f_F, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mov_cc__RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mov_cc__RC", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mov_s_mcah:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ UINT f_op__b;
+ UINT f_h_2_0;
+ UINT f_h_5_3;
+ UINT f_op_h;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_h_2_0 = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_h_5_3 = EXTRACT_MSB0_UINT (insn, 32, 13, 3);
+{
+ f_op_h = ((f_h_2_0) | (((f_h_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_h) = f_op_h;
+ FLD (f_op__b) = f_op__b;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mov_s_mcah", "f_op_h 0x%x", 'x', f_op_h, "f_op__b 0x%x", 'x', f_op__b, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mov_s_mcahb:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ UINT f_op__b;
+ UINT f_h_2_0;
+ UINT f_h_5_3;
+ UINT f_op_h;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_h_2_0 = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_h_5_3 = EXTRACT_MSB0_UINT (insn, 32, 13, 3);
+{
+ f_op_h = ((f_h_2_0) | (((f_h_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_op_h) = f_op_h;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mov_s_mcahb", "f_op__b 0x%x", 'x', f_op__b, "f_op_h 0x%x", 'x', f_op_h, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mov_s_r_u7:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ UINT f_op__b;
+ UINT f_u8;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_u8) = f_u8;
+ FLD (f_op__b) = f_op__b;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mov_s_r_u7", "f_u8 0x%x", 'x', f_u8, "f_op__b 0x%x", 'x', f_op__b, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_tst_L_s12_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_tst_L_s12_", "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_tst_ccu6_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_tst_ccu6_", "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_tst_L_u6_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_tst_L_u6_", "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_tst_L_r_r__RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_tst_L_r_r__RC", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_tst_cc__RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_tst_cc__RC", "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_tst_s_go:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ UINT f_op__b;
+ UINT f_op__c;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_op__c) = f_op__c;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_tst_s_go", "f_op__b 0x%x", 'x', f_op__b, "f_op__c 0x%x", 'x', f_op__c, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmp_L_s12_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp_L_s12_", "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmp_ccu6_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp_ccu6_", "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmp_L_u6_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp_L_u6_", "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmp_L_r_r__RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp_L_r_r__RC", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmp_cc__RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp_cc__RC", "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmp_s_mcah:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ UINT f_op__b;
+ UINT f_h_2_0;
+ UINT f_h_5_3;
+ UINT f_op_h;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_h_2_0 = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_h_5_3 = EXTRACT_MSB0_UINT (insn, 32, 13, 3);
+{
+ f_op_h = ((f_h_2_0) | (((f_h_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_op_h) = f_op_h;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp_s_mcah", "f_op__b 0x%x", 'x', f_op__b, "f_op_h 0x%x", 'x', f_op_h, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmp_s_r_u7:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_s_r_u7.f
+ UINT f_op__b;
+ UINT f_u7;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u7 = EXTRACT_MSB0_UINT (insn, 32, 9, 7);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_u7) = f_u7;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp_s_r_u7", "f_op__b 0x%x", 'x', f_op__b, "f_u7 0x%x", 'x', f_u7, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_btst_s_ssb:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ UINT f_op__b;
+ UINT f_u5;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u5 = EXTRACT_MSB0_UINT (insn, 32, 11, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_u5) = f_u5;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_btst_s_ssb", "f_op__b 0x%x", 'x', f_op__b, "f_u5 0x%x", 'x', f_u5, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mpy_L_s12__RA_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mpy_L_s12__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mpy_ccu6__RA_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mpy_ccu6__RA_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mpy_L_u6__RA_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mpy_L_u6__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mpy_L_r_r__RA__RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mpy_L_r_r__RA__RC", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mpy_cc__RA__RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mpy_cc__RA__RC", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_L_r_r___RC_noilink_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_Cj;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_Cj = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_Cj) = f_op_Cj;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_L_r_r___RC_noilink_", "f_F 0x%x", 'x', f_F, "f_op_Cj 0x%x", 'x', f_op_Cj, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_cc___RC_noilink_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_Cj;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_Cj = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_Cj) = f_op_Cj;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_cc___RC_noilink_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_Cj 0x%x", 'x', f_op_Cj, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_L_r_r___RC_ilink_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_Cj;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_Cj = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_Cj) = f_op_Cj;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_L_r_r___RC_ilink_", "f_F 0x%x", 'x', f_F, "f_op_Cj 0x%x", 'x', f_op_Cj, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_cc___RC_ilink_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_Cj;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_Cj = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_Cj) = f_op_Cj;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_cc___RC_ilink_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_Cj 0x%x", 'x', f_op_Cj, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_L_s12_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_L_s12_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_ccu6_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_ccu6_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_L_u6_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_L_u6_", "f_F 0x%x", 'x', f_F, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_s:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ UINT f_op__b;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_s", "f_op__b 0x%x", 'x', f_op__b, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_s__S:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_s__S", (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_seq__S:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_seq__S", (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_L_s12_d_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_L_s12_d_", "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_ccu6_d_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_ccu6_d_", "f_cond_Q 0x%x", 'x', f_cond_Q, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_L_u6_d_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_L_u6_d_", "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_L_r_r_d___RC_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_L_r_r_d___RC_", "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_cc_d___RC_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_cc_d___RC_", "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_jl_L_s12_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl_L_s12_", "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_jl_ccu6_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl_ccu6_", "f_cond_Q 0x%x", 'x', f_cond_Q, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_jl_L_u6_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl_L_u6_", "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_jl_s:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ UINT f_op__b;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl_s", "f_op__b 0x%x", 'x', f_op__b, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_jl_L_r_r___RC_noilink_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_Cj;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_Cj = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_Cj) = f_op_Cj;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl_L_r_r___RC_noilink_", "f_op_Cj 0x%x", 'x', f_op_Cj, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_jl_cc___RC_noilink_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_Cj;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_Cj = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_Cj) = f_op_Cj;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl_cc___RC_noilink_", "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_Cj 0x%x", 'x', f_op_Cj, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_jl_L_r_r_d___RC_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl_L_r_r_d___RC_", "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_jl_cc_d___RC_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl_cc_d___RC_", "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_jl_s_d:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ UINT f_op__b;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl_s_d", "f_op__b 0x%x", 'x', f_op__b, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lp_L_s12_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_lp_L_s12_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12x2;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12x2 = ((((f_u6) << (1))) | (((f_s12h) << (7))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12x2) = f_s12x2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lp_L_s12_", "f_op_B 0x%x", 'x', f_op_B, "f_s12x2 0x%x", 'x', f_s12x2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lpcc_ccu6:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_lpcc_ccu6.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ SI f_u6x2;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6x2 = ((EXTRACT_MSB0_UINT (insn, 32, 20, 6)) << (1));
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_u6x2) = f_u6x2;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lpcc_ccu6", "f_cond_Q 0x%x", 'x', f_cond_Q, "f_u6x2 0x%x", 'x', f_u6x2, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_flag_L_s12_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_flag_L_s12_", "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_flag_ccu6_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_flag_ccu6_", "f_cond_Q 0x%x", 'x', f_cond_Q, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_flag_L_u6_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_flag_L_u6_", "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_flag_L_r_r__RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_flag_L_r_r__RC", "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_flag_cc__RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_flag_cc__RC", "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lr_L_r_r___RC_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lr_L_r_r___RC_", "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lr_L_s12_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lr_L_s12_", "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lr_L_u6_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lr_L_u6_", "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sr_L_r_r___RC_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sr_L_r_r___RC_", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sr_L_s12_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sr_L_s12_", "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sr_L_u6_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sr_L_u6_", "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asl_L_r_r__RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asl_L_r_r__RC", "f_F 0x%x", 'x', f_F, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asl_L_u6_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asl_L_u6_", "f_F 0x%x", 'x', f_F, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asr_L_r_r__RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asr_L_r_r__RC", "f_F 0x%x", 'x', f_F, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asr_L_u6_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asr_L_u6_", "f_F 0x%x", 'x', f_F, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_rrc_L_r_r__RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rrc_L_r_r__RC", "f_F 0x%x", 'x', f_F, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_rrc_L_u6_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rrc_L_u6_", "f_F 0x%x", 'x', f_F, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sexb_L_r_r__RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sexb_L_r_r__RC", "f_F 0x%x", 'x', f_F, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sexb_L_u6_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sexb_L_u6_", "f_F 0x%x", 'x', f_F, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sexw_L_r_r__RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sexw_L_r_r__RC", "f_F 0x%x", 'x', f_F, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sexw_L_u6_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sexw_L_u6_", "f_F 0x%x", 'x', f_F, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_abs_L_r_r__RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_abs_L_r_r__RC", "f_F 0x%x", 'x', f_F, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_abs_L_u6_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_abs_L_u6_", "f_F 0x%x", 'x', f_F, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_not_L_r_r__RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_not_L_r_r__RC", "f_F 0x%x", 'x', f_F, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_not_L_u6_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_not_L_u6_", "f_F 0x%x", 'x', f_F, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_swi:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_swi", (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_trap_s:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_trap_s.f
+ UINT f_trapnum;
+
+ f_trapnum = EXTRACT_MSB0_UINT (insn, 32, 5, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_trapnum) = f_trapnum;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_trap_s", "f_trapnum 0x%x", 'x', f_trapnum, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_brk:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_brk", (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asl_L_s12__RA_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asl_L_s12__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asl_ccu6__RA_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asl_ccu6__RA_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asl_L_u6__RA_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asl_L_u6__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asl_L_r_r__RA__RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asl_L_r_r__RA__RC", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asl_cc__RA__RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asl_cc__RA__RC", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mul64_L_s12_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mul64_L_s12_", "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mul64_ccu6_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mul64_ccu6_", "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mul64_L_u6_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mul64_L_u6_", "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mul64_L_r_r__RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mul64_L_r_r__RC", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mul64_cc__RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mul64_cc__RC", "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mul64_s_go:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ UINT f_op__b;
+ UINT f_op__c;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_op__c) = f_op__c;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mul64_s_go", "f_op__b 0x%x", 'x', f_op__b, "f_op__c 0x%x", 'x', f_op__c, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_adds_L_s12__RA_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_adds_L_s12__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_adds_ccu6__RA_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_adds_ccu6__RA_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_adds_L_u6__RA_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_adds_L_u6__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_adds_L_r_r__RA__RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_adds_L_r_r__RA__RC", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_adds_cc__RA__RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_adds_cc__RA__RC", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_divaw_L_s12__RA_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_divaw_L_s12__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_divaw_ccu6__RA_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_divaw_ccu6__RA_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_divaw_L_u6__RA_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_divaw_L_u6__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_divaw_L_r_r__RA__RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_divaw_L_r_r__RA__RC", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_divaw_cc__RA__RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_divaw_cc__RA__RC", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asls_L_s12__RA_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asls_L_s12__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asls_ccu6__RA_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asls_ccu6__RA_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asls_L_u6__RA_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asls_L_u6__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asls_L_r_r__RA__RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asls_L_r_r__RA__RC", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asls_cc__RA__RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asls_cc__RA__RC", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_swap_L_r_r__RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_swap_L_r_r__RC", "f_F 0x%x", 'x', f_F, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_swap_L_u6_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_swap_L_u6_", "f_F 0x%x", 'x', f_F, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_norm_L_u6_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_norm_L_u6_", "f_F 0x%x", 'x', f_F, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_rnd16_L_r_r__RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rnd16_L_r_r__RC", "f_F 0x%x", 'x', f_F, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_rnd16_L_u6_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rnd16_L_u6_", "f_F 0x%x", 'x', f_F, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_abssw_L_r_r__RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_abssw_L_r_r__RC", "f_F 0x%x", 'x', f_F, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_abssw_L_u6_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_abssw_L_u6_", "f_F 0x%x", 'x', f_F, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_abss_L_u6_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_abss_L_u6_", "f_F 0x%x", 'x', f_F, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_nop_s:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nop_s", (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_pop_s_b:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ UINT f_op__b;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_pop_s_b", "f_op__b 0x%x", 'x', f_op__b, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_pop_s_blink:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_pop_s_blink", (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_push_s_b:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ UINT f_op__b;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_push_s_b", "f_op__b 0x%x", 'x', f_op__b, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_push_s_blink:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_push_s_blink", (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mullw_L_s12__RA_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mullw_L_s12__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mullw_ccu6__RA_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mullw_ccu6__RA_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mullw_L_u6__RA_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mullw_L_u6__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mullw_L_r_r__RA__RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mullw_L_r_r__RA__RC", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mullw_cc__RA__RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mullw_cc__RA__RC", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_maclw_L_s12__RA_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_maclw_L_s12__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_maclw_ccu6__RA_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_maclw_ccu6__RA_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_maclw_L_u6__RA_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_maclw_L_u6__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_maclw_L_r_r__RA__RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_maclw_L_r_r__RA__RC", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_maclw_cc__RA__RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_maclw_cc__RA__RC", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_machulw_L_s12__RA_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machulw_L_s12__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_machulw_ccu6__RA_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machulw_ccu6__RA_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_machulw_L_u6__RA_:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machulw_L_u6__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_machulw_L_r_r__RA__RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machulw_L_r_r__RA__RC", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_machulw_cc__RA__RC:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machulw_cc__RA__RC", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_current_loop_end:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_current_loop_end", (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_current_loop_end_after_branch:
+ {
+ const IDESC *idesc = &arc600f_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_current_loop_end_after_branch", (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+}
diff --git a/sim/arc/decode6.h b/sim/arc/decode6.h
new file mode 100644
index 0000000..465df40
--- /dev/null
+++ b/sim/arc/decode6.h
@@ -0,0 +1,225 @@
+/* Decode header for arc600f.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2007 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#ifndef ARC600F_DECODE_H
+#define ARC600F_DECODE_H
+
+extern const IDESC *arc600f_decode (SIM_CPU *, IADDR,
+ CGEN_INSN_INT, CGEN_INSN_INT,
+ ARGBUF *);
+extern void arc600f_init_idesc_table (SIM_CPU *);
+extern void arc600f_sem_init_idesc_table (SIM_CPU *);
+extern void arc600f_semf_init_idesc_table (SIM_CPU *);
+
+/* Enum declaration for instructions in cpu family arc600f. */
+typedef enum arc600f_insn_type {
+ ARC600F_INSN_X_INVALID, ARC600F_INSN_X_AFTER, ARC600F_INSN_X_BEFORE, ARC600F_INSN_X_CTI_CHAIN
+ , ARC600F_INSN_X_CHAIN, ARC600F_INSN_X_BEGIN, ARC600F_INSN_B_S, ARC600F_INSN_BCC_S
+ , ARC600F_INSN_BRCC_S, ARC600F_INSN_BCC_L, ARC600F_INSN_BCC_L_D, ARC600F_INSN_B_L
+ , ARC600F_INSN_B_L_D, ARC600F_INSN_BRCC_RC, ARC600F_INSN_BRCC_RC_D, ARC600F_INSN_BRCC_U6
+ , ARC600F_INSN_BRCC_U6_D, ARC600F_INSN_BL_S, ARC600F_INSN_BLCC, ARC600F_INSN_BLCC_D
+ , ARC600F_INSN_BL, ARC600F_INSN_BL_D, ARC600F_INSN_LD_ABS, ARC600F_INSN_LD__AW_ABS
+ , ARC600F_INSN_LD_AB_ABS, ARC600F_INSN_LD_AS_ABS, ARC600F_INSN_LD_ABC, ARC600F_INSN_LD__AW_ABC
+ , ARC600F_INSN_LD_AB_ABC, ARC600F_INSN_LD_AS_ABC, ARC600F_INSN_LD_S_ABC, ARC600F_INSN_LD_S_ABU
+ , ARC600F_INSN_LD_S_ABSP, ARC600F_INSN_LD_S_GPREL, ARC600F_INSN_LD_S_PCREL, ARC600F_INSN_LDB_ABS
+ , ARC600F_INSN_LDB__AW_ABS, ARC600F_INSN_LDB_AB_ABS, ARC600F_INSN_LDB_AS_ABS, ARC600F_INSN_LDB_ABC
+ , ARC600F_INSN_LDB__AW_ABC, ARC600F_INSN_LDB_AB_ABC, ARC600F_INSN_LDB_AS_ABC, ARC600F_INSN_LDB_S_ABC
+ , ARC600F_INSN_LDB_S_ABU, ARC600F_INSN_LDB_S_ABSP, ARC600F_INSN_LDB_S_GPREL, ARC600F_INSN_LDB_X_ABS
+ , ARC600F_INSN_LDB__AW_X_ABS, ARC600F_INSN_LDB_AB_X_ABS, ARC600F_INSN_LDB_AS_X_ABS, ARC600F_INSN_LDB_X_ABC
+ , ARC600F_INSN_LDB__AW_X_ABC, ARC600F_INSN_LDB_AB_X_ABC, ARC600F_INSN_LDB_AS_X_ABC, ARC600F_INSN_LDW_ABS
+ , ARC600F_INSN_LDW__AW_ABS, ARC600F_INSN_LDW_AB_ABS, ARC600F_INSN_LDW_AS_ABS, ARC600F_INSN_LDW_ABC
+ , ARC600F_INSN_LDW__AW_ABC, ARC600F_INSN_LDW_AB_ABC, ARC600F_INSN_LDW_AS_ABC, ARC600F_INSN_LDW_S_ABC
+ , ARC600F_INSN_LDW_S_ABU, ARC600F_INSN_LDW_S_GPREL, ARC600F_INSN_LDW_X_ABS, ARC600F_INSN_LDW__AW_X_ABS
+ , ARC600F_INSN_LDW_AB_X_ABS, ARC600F_INSN_LDW_AS_X_ABS, ARC600F_INSN_LDW_X_ABC, ARC600F_INSN_LDW__AW_X_ABC
+ , ARC600F_INSN_LDW_AB_X_ABC, ARC600F_INSN_LDW_AS_X_ABC, ARC600F_INSN_LDW_S_X_ABU, ARC600F_INSN_ST_ABS
+ , ARC600F_INSN_ST__AW_ABS, ARC600F_INSN_ST_AB_ABS, ARC600F_INSN_ST_AS_ABS, ARC600F_INSN_ST_S_ABU
+ , ARC600F_INSN_ST_S_ABSP, ARC600F_INSN_STB_ABS, ARC600F_INSN_STB__AW_ABS, ARC600F_INSN_STB_AB_ABS
+ , ARC600F_INSN_STB_AS_ABS, ARC600F_INSN_STB_S_ABU, ARC600F_INSN_STB_S_ABSP, ARC600F_INSN_STW_ABS
+ , ARC600F_INSN_STW__AW_ABS, ARC600F_INSN_STW_AB_ABS, ARC600F_INSN_STW_AS_ABS, ARC600F_INSN_STW_S_ABU
+ , ARC600F_INSN_ADD_L_S12__RA_, ARC600F_INSN_ADD_CCU6__RA_, ARC600F_INSN_ADD_L_U6__RA_, ARC600F_INSN_ADD_L_R_R__RA__RC
+ , ARC600F_INSN_ADD_CC__RA__RC, ARC600F_INSN_ADD_S_ABC, ARC600F_INSN_ADD_S_CBU3, ARC600F_INSN_ADD_S_MCAH
+ , ARC600F_INSN_ADD_S_ABSP, ARC600F_INSN_ADD_S_ASSPSP, ARC600F_INSN_ADD_S_GP, ARC600F_INSN_ADD_S_R_U7
+ , ARC600F_INSN_ADC_L_S12__RA_, ARC600F_INSN_ADC_CCU6__RA_, ARC600F_INSN_ADC_L_U6__RA_, ARC600F_INSN_ADC_L_R_R__RA__RC
+ , ARC600F_INSN_ADC_CC__RA__RC, ARC600F_INSN_SUB_L_S12__RA_, ARC600F_INSN_SUB_CCU6__RA_, ARC600F_INSN_SUB_L_U6__RA_
+ , ARC600F_INSN_SUB_L_R_R__RA__RC, ARC600F_INSN_SUB_CC__RA__RC, ARC600F_INSN_SUB_S_CBU3, ARC600F_INSN_I16_GO_SUB_S_GO
+ , ARC600F_INSN_SUB_S_GO_SUB_NE, ARC600F_INSN_SUB_S_SSB, ARC600F_INSN_SUB_S_ASSPSP, ARC600F_INSN_SBC_L_S12__RA_
+ , ARC600F_INSN_SBC_CCU6__RA_, ARC600F_INSN_SBC_L_U6__RA_, ARC600F_INSN_SBC_L_R_R__RA__RC, ARC600F_INSN_SBC_CC__RA__RC
+ , ARC600F_INSN_AND_L_S12__RA_, ARC600F_INSN_AND_CCU6__RA_, ARC600F_INSN_AND_L_U6__RA_, ARC600F_INSN_AND_L_R_R__RA__RC
+ , ARC600F_INSN_AND_CC__RA__RC, ARC600F_INSN_I16_GO_AND_S_GO, ARC600F_INSN_OR_L_S12__RA_, ARC600F_INSN_OR_CCU6__RA_
+ , ARC600F_INSN_OR_L_U6__RA_, ARC600F_INSN_OR_L_R_R__RA__RC, ARC600F_INSN_OR_CC__RA__RC, ARC600F_INSN_I16_GO_OR_S_GO
+ , ARC600F_INSN_BIC_L_S12__RA_, ARC600F_INSN_BIC_CCU6__RA_, ARC600F_INSN_BIC_L_U6__RA_, ARC600F_INSN_BIC_L_R_R__RA__RC
+ , ARC600F_INSN_BIC_CC__RA__RC, ARC600F_INSN_I16_GO_BIC_S_GO, ARC600F_INSN_XOR_L_S12__RA_, ARC600F_INSN_XOR_CCU6__RA_
+ , ARC600F_INSN_XOR_L_U6__RA_, ARC600F_INSN_XOR_L_R_R__RA__RC, ARC600F_INSN_XOR_CC__RA__RC, ARC600F_INSN_I16_GO_XOR_S_GO
+ , ARC600F_INSN_MAX_L_S12__RA_, ARC600F_INSN_MAX_CCU6__RA_, ARC600F_INSN_MAX_L_U6__RA_, ARC600F_INSN_MAX_L_R_R__RA__RC
+ , ARC600F_INSN_MAX_CC__RA__RC, ARC600F_INSN_MIN_L_S12__RA_, ARC600F_INSN_MIN_CCU6__RA_, ARC600F_INSN_MIN_L_U6__RA_
+ , ARC600F_INSN_MIN_L_R_R__RA__RC, ARC600F_INSN_MIN_CC__RA__RC, ARC600F_INSN_MOV_L_S12_, ARC600F_INSN_MOV_CCU6_
+ , ARC600F_INSN_MOV_L_U6_, ARC600F_INSN_MOV_L_R_R__RC, ARC600F_INSN_MOV_CC__RC, ARC600F_INSN_MOV_S_MCAH
+ , ARC600F_INSN_MOV_S_MCAHB, ARC600F_INSN_MOV_S_R_U7, ARC600F_INSN_TST_L_S12_, ARC600F_INSN_TST_CCU6_
+ , ARC600F_INSN_TST_L_U6_, ARC600F_INSN_TST_L_R_R__RC, ARC600F_INSN_TST_CC__RC, ARC600F_INSN_TST_S_GO
+ , ARC600F_INSN_CMP_L_S12_, ARC600F_INSN_CMP_CCU6_, ARC600F_INSN_CMP_L_U6_, ARC600F_INSN_CMP_L_R_R__RC
+ , ARC600F_INSN_CMP_CC__RC, ARC600F_INSN_CMP_S_MCAH, ARC600F_INSN_CMP_S_R_U7, ARC600F_INSN_RCMP_L_S12_
+ , ARC600F_INSN_RCMP_CCU6_, ARC600F_INSN_RCMP_L_U6_, ARC600F_INSN_RCMP_L_R_R__RC, ARC600F_INSN_RCMP_CC__RC
+ , ARC600F_INSN_RSUB_L_S12__RA_, ARC600F_INSN_RSUB_CCU6__RA_, ARC600F_INSN_RSUB_L_U6__RA_, ARC600F_INSN_RSUB_L_R_R__RA__RC
+ , ARC600F_INSN_RSUB_CC__RA__RC, ARC600F_INSN_BSET_L_S12__RA_, ARC600F_INSN_BSET_CCU6__RA_, ARC600F_INSN_BSET_L_U6__RA_
+ , ARC600F_INSN_BSET_L_R_R__RA__RC, ARC600F_INSN_BSET_CC__RA__RC, ARC600F_INSN_BSET_S_SSB, ARC600F_INSN_BCLR_L_S12__RA_
+ , ARC600F_INSN_BCLR_CCU6__RA_, ARC600F_INSN_BCLR_L_U6__RA_, ARC600F_INSN_BCLR_L_R_R__RA__RC, ARC600F_INSN_BCLR_CC__RA__RC
+ , ARC600F_INSN_BCLR_S_SSB, ARC600F_INSN_BTST_L_S12_, ARC600F_INSN_BTST_CCU6_, ARC600F_INSN_BTST_L_U6_
+ , ARC600F_INSN_BTST_L_R_R__RC, ARC600F_INSN_BTST_CC__RC, ARC600F_INSN_BTST_S_SSB, ARC600F_INSN_BXOR_L_S12__RA_
+ , ARC600F_INSN_BXOR_CCU6__RA_, ARC600F_INSN_BXOR_L_U6__RA_, ARC600F_INSN_BXOR_L_R_R__RA__RC, ARC600F_INSN_BXOR_CC__RA__RC
+ , ARC600F_INSN_BMSK_L_S12__RA_, ARC600F_INSN_BMSK_CCU6__RA_, ARC600F_INSN_BMSK_L_U6__RA_, ARC600F_INSN_BMSK_L_R_R__RA__RC
+ , ARC600F_INSN_BMSK_CC__RA__RC, ARC600F_INSN_BMSK_S_SSB, ARC600F_INSN_ADD1_L_S12__RA_, ARC600F_INSN_ADD1_CCU6__RA_
+ , ARC600F_INSN_ADD1_L_U6__RA_, ARC600F_INSN_ADD1_L_R_R__RA__RC, ARC600F_INSN_ADD1_CC__RA__RC, ARC600F_INSN_I16_GO_ADD1_S_GO
+ , ARC600F_INSN_ADD2_L_S12__RA_, ARC600F_INSN_ADD2_CCU6__RA_, ARC600F_INSN_ADD2_L_U6__RA_, ARC600F_INSN_ADD2_L_R_R__RA__RC
+ , ARC600F_INSN_ADD2_CC__RA__RC, ARC600F_INSN_I16_GO_ADD2_S_GO, ARC600F_INSN_ADD3_L_S12__RA_, ARC600F_INSN_ADD3_CCU6__RA_
+ , ARC600F_INSN_ADD3_L_U6__RA_, ARC600F_INSN_ADD3_L_R_R__RA__RC, ARC600F_INSN_ADD3_CC__RA__RC, ARC600F_INSN_I16_GO_ADD3_S_GO
+ , ARC600F_INSN_SUB1_L_S12__RA_, ARC600F_INSN_SUB1_CCU6__RA_, ARC600F_INSN_SUB1_L_U6__RA_, ARC600F_INSN_SUB1_L_R_R__RA__RC
+ , ARC600F_INSN_SUB1_CC__RA__RC, ARC600F_INSN_SUB2_L_S12__RA_, ARC600F_INSN_SUB2_CCU6__RA_, ARC600F_INSN_SUB2_L_U6__RA_
+ , ARC600F_INSN_SUB2_L_R_R__RA__RC, ARC600F_INSN_SUB2_CC__RA__RC, ARC600F_INSN_SUB3_L_S12__RA_, ARC600F_INSN_SUB3_CCU6__RA_
+ , ARC600F_INSN_SUB3_L_U6__RA_, ARC600F_INSN_SUB3_L_R_R__RA__RC, ARC600F_INSN_SUB3_CC__RA__RC, ARC600F_INSN_MPY_L_S12__RA_
+ , ARC600F_INSN_MPY_CCU6__RA_, ARC600F_INSN_MPY_L_U6__RA_, ARC600F_INSN_MPY_L_R_R__RA__RC, ARC600F_INSN_MPY_CC__RA__RC
+ , ARC600F_INSN_MPYH_L_S12__RA_, ARC600F_INSN_MPYH_CCU6__RA_, ARC600F_INSN_MPYH_L_U6__RA_, ARC600F_INSN_MPYH_L_R_R__RA__RC
+ , ARC600F_INSN_MPYH_CC__RA__RC, ARC600F_INSN_MPYHU_L_S12__RA_, ARC600F_INSN_MPYHU_CCU6__RA_, ARC600F_INSN_MPYHU_L_U6__RA_
+ , ARC600F_INSN_MPYHU_L_R_R__RA__RC, ARC600F_INSN_MPYHU_CC__RA__RC, ARC600F_INSN_MPYU_L_S12__RA_, ARC600F_INSN_MPYU_CCU6__RA_
+ , ARC600F_INSN_MPYU_L_U6__RA_, ARC600F_INSN_MPYU_L_R_R__RA__RC, ARC600F_INSN_MPYU_CC__RA__RC, ARC600F_INSN_J_L_R_R___RC_NOILINK_
+ , ARC600F_INSN_J_CC___RC_NOILINK_, ARC600F_INSN_J_L_R_R___RC_ILINK_, ARC600F_INSN_J_CC___RC_ILINK_, ARC600F_INSN_J_L_S12_
+ , ARC600F_INSN_J_CCU6_, ARC600F_INSN_J_L_U6_, ARC600F_INSN_J_S, ARC600F_INSN_J_S__S
+ , ARC600F_INSN_J_SEQ__S, ARC600F_INSN_J_SNE__S, ARC600F_INSN_J_L_S12_D_, ARC600F_INSN_J_CCU6_D_
+ , ARC600F_INSN_J_L_U6_D_, ARC600F_INSN_J_L_R_R_D___RC_, ARC600F_INSN_J_CC_D___RC_, ARC600F_INSN_J_S_D
+ , ARC600F_INSN_J_S__S_D, ARC600F_INSN_JL_L_S12_, ARC600F_INSN_JL_CCU6_, ARC600F_INSN_JL_L_U6_
+ , ARC600F_INSN_JL_S, ARC600F_INSN_JL_L_R_R___RC_NOILINK_, ARC600F_INSN_JL_CC___RC_NOILINK_, ARC600F_INSN_JL_L_S12_D_
+ , ARC600F_INSN_JL_CCU6_D_, ARC600F_INSN_JL_L_U6_D_, ARC600F_INSN_JL_L_R_R_D___RC_, ARC600F_INSN_JL_CC_D___RC_
+ , ARC600F_INSN_JL_S_D, ARC600F_INSN_LP_L_S12_, ARC600F_INSN_LPCC_CCU6, ARC600F_INSN_FLAG_L_S12_
+ , ARC600F_INSN_FLAG_CCU6_, ARC600F_INSN_FLAG_L_U6_, ARC600F_INSN_FLAG_L_R_R__RC, ARC600F_INSN_FLAG_CC__RC
+ , ARC600F_INSN_LR_L_R_R___RC_, ARC600F_INSN_LR_L_S12_, ARC600F_INSN_LR_L_U6_, ARC600F_INSN_SR_L_R_R___RC_
+ , ARC600F_INSN_SR_L_S12_, ARC600F_INSN_SR_L_U6_, ARC600F_INSN_ASL_L_R_R__RC, ARC600F_INSN_ASL_L_U6_
+ , ARC600F_INSN_I16_GO_ASL_S_GO, ARC600F_INSN_ASR_L_R_R__RC, ARC600F_INSN_ASR_L_U6_, ARC600F_INSN_I16_GO_ASR_S_GO
+ , ARC600F_INSN_LSR_L_R_R__RC, ARC600F_INSN_LSR_L_U6_, ARC600F_INSN_I16_GO_LSR_S_GO, ARC600F_INSN_ROR_L_R_R__RC
+ , ARC600F_INSN_ROR_L_U6_, ARC600F_INSN_RRC_L_R_R__RC, ARC600F_INSN_RRC_L_U6_, ARC600F_INSN_SEXB_L_R_R__RC
+ , ARC600F_INSN_SEXB_L_U6_, ARC600F_INSN_I16_GO_SEXB_S_GO, ARC600F_INSN_SEXW_L_R_R__RC, ARC600F_INSN_SEXW_L_U6_
+ , ARC600F_INSN_I16_GO_SEXW_S_GO, ARC600F_INSN_EXTB_L_R_R__RC, ARC600F_INSN_EXTB_L_U6_, ARC600F_INSN_I16_GO_EXTB_S_GO
+ , ARC600F_INSN_EXTW_L_R_R__RC, ARC600F_INSN_EXTW_L_U6_, ARC600F_INSN_I16_GO_EXTW_S_GO, ARC600F_INSN_ABS_L_R_R__RC
+ , ARC600F_INSN_ABS_L_U6_, ARC600F_INSN_I16_GO_ABS_S_GO, ARC600F_INSN_NOT_L_R_R__RC, ARC600F_INSN_NOT_L_U6_
+ , ARC600F_INSN_I16_GO_NOT_S_GO, ARC600F_INSN_RLC_L_R_R__RC, ARC600F_INSN_RLC_L_U6_, ARC600F_INSN_I16_GO_NEG_S_GO
+ , ARC600F_INSN_SWI, ARC600F_INSN_TRAP_S, ARC600F_INSN_BRK, ARC600F_INSN_BRK_S
+ , ARC600F_INSN_ASL_L_S12__RA_, ARC600F_INSN_ASL_CCU6__RA_, ARC600F_INSN_ASL_L_U6__RA_, ARC600F_INSN_ASL_L_R_R__RA__RC
+ , ARC600F_INSN_ASL_CC__RA__RC, ARC600F_INSN_ASL_S_CBU3, ARC600F_INSN_ASL_S_SSB, ARC600F_INSN_I16_GO_ASLM_S_GO
+ , ARC600F_INSN_LSR_L_S12__RA_, ARC600F_INSN_LSR_CCU6__RA_, ARC600F_INSN_LSR_L_U6__RA_, ARC600F_INSN_LSR_L_R_R__RA__RC
+ , ARC600F_INSN_LSR_CC__RA__RC, ARC600F_INSN_LSR_S_SSB, ARC600F_INSN_I16_GO_LSRM_S_GO, ARC600F_INSN_ASR_L_S12__RA_
+ , ARC600F_INSN_ASR_CCU6__RA_, ARC600F_INSN_ASR_L_U6__RA_, ARC600F_INSN_ASR_L_R_R__RA__RC, ARC600F_INSN_ASR_CC__RA__RC
+ , ARC600F_INSN_ASR_S_CBU3, ARC600F_INSN_ASR_S_SSB, ARC600F_INSN_I16_GO_ASRM_S_GO, ARC600F_INSN_ROR_L_S12__RA_
+ , ARC600F_INSN_ROR_CCU6__RA_, ARC600F_INSN_ROR_L_U6__RA_, ARC600F_INSN_ROR_L_R_R__RA__RC, ARC600F_INSN_ROR_CC__RA__RC
+ , ARC600F_INSN_MUL64_L_S12_, ARC600F_INSN_MUL64_CCU6_, ARC600F_INSN_MUL64_L_U6_, ARC600F_INSN_MUL64_L_R_R__RC
+ , ARC600F_INSN_MUL64_CC__RC, ARC600F_INSN_MUL64_S_GO, ARC600F_INSN_MULU64_L_S12_, ARC600F_INSN_MULU64_CCU6_
+ , ARC600F_INSN_MULU64_L_U6_, ARC600F_INSN_MULU64_L_R_R__RC, ARC600F_INSN_MULU64_CC__RC, ARC600F_INSN_ADDS_L_S12__RA_
+ , ARC600F_INSN_ADDS_CCU6__RA_, ARC600F_INSN_ADDS_L_U6__RA_, ARC600F_INSN_ADDS_L_R_R__RA__RC, ARC600F_INSN_ADDS_CC__RA__RC
+ , ARC600F_INSN_SUBS_L_S12__RA_, ARC600F_INSN_SUBS_CCU6__RA_, ARC600F_INSN_SUBS_L_U6__RA_, ARC600F_INSN_SUBS_L_R_R__RA__RC
+ , ARC600F_INSN_SUBS_CC__RA__RC, ARC600F_INSN_DIVAW_L_S12__RA_, ARC600F_INSN_DIVAW_CCU6__RA_, ARC600F_INSN_DIVAW_L_U6__RA_
+ , ARC600F_INSN_DIVAW_L_R_R__RA__RC, ARC600F_INSN_DIVAW_CC__RA__RC, ARC600F_INSN_ASLS_L_S12__RA_, ARC600F_INSN_ASLS_CCU6__RA_
+ , ARC600F_INSN_ASLS_L_U6__RA_, ARC600F_INSN_ASLS_L_R_R__RA__RC, ARC600F_INSN_ASLS_CC__RA__RC, ARC600F_INSN_ASRS_L_S12__RA_
+ , ARC600F_INSN_ASRS_CCU6__RA_, ARC600F_INSN_ASRS_L_U6__RA_, ARC600F_INSN_ASRS_L_R_R__RA__RC, ARC600F_INSN_ASRS_CC__RA__RC
+ , ARC600F_INSN_ADDSDW_L_S12__RA_, ARC600F_INSN_ADDSDW_CCU6__RA_, ARC600F_INSN_ADDSDW_L_U6__RA_, ARC600F_INSN_ADDSDW_L_R_R__RA__RC
+ , ARC600F_INSN_ADDSDW_CC__RA__RC, ARC600F_INSN_SUBSDW_L_S12__RA_, ARC600F_INSN_SUBSDW_CCU6__RA_, ARC600F_INSN_SUBSDW_L_U6__RA_
+ , ARC600F_INSN_SUBSDW_L_R_R__RA__RC, ARC600F_INSN_SUBSDW_CC__RA__RC, ARC600F_INSN_SWAP_L_R_R__RC, ARC600F_INSN_SWAP_L_U6_
+ , ARC600F_INSN_NORM_L_R_R__RC, ARC600F_INSN_NORM_L_U6_, ARC600F_INSN_RND16_L_R_R__RC, ARC600F_INSN_RND16_L_U6_
+ , ARC600F_INSN_ABSSW_L_R_R__RC, ARC600F_INSN_ABSSW_L_U6_, ARC600F_INSN_ABSS_L_R_R__RC, ARC600F_INSN_ABSS_L_U6_
+ , ARC600F_INSN_NEGSW_L_R_R__RC, ARC600F_INSN_NEGSW_L_U6_, ARC600F_INSN_NEGS_L_R_R__RC, ARC600F_INSN_NEGS_L_U6_
+ , ARC600F_INSN_NORMW_L_R_R__RC, ARC600F_INSN_NORMW_L_U6_, ARC600F_INSN_NOP_S, ARC600F_INSN_UNIMP_S
+ , ARC600F_INSN_POP_S_B, ARC600F_INSN_POP_S_BLINK, ARC600F_INSN_PUSH_S_B, ARC600F_INSN_PUSH_S_BLINK
+ , ARC600F_INSN_MULLW_L_S12__RA_, ARC600F_INSN_MULLW_CCU6__RA_, ARC600F_INSN_MULLW_L_U6__RA_, ARC600F_INSN_MULLW_L_R_R__RA__RC
+ , ARC600F_INSN_MULLW_CC__RA__RC, ARC600F_INSN_MACLW_L_S12__RA_, ARC600F_INSN_MACLW_CCU6__RA_, ARC600F_INSN_MACLW_L_U6__RA_
+ , ARC600F_INSN_MACLW_L_R_R__RA__RC, ARC600F_INSN_MACLW_CC__RA__RC, ARC600F_INSN_MACHLW_L_S12__RA_, ARC600F_INSN_MACHLW_CCU6__RA_
+ , ARC600F_INSN_MACHLW_L_U6__RA_, ARC600F_INSN_MACHLW_L_R_R__RA__RC, ARC600F_INSN_MACHLW_CC__RA__RC, ARC600F_INSN_MULULW_L_S12__RA_
+ , ARC600F_INSN_MULULW_CCU6__RA_, ARC600F_INSN_MULULW_L_U6__RA_, ARC600F_INSN_MULULW_L_R_R__RA__RC, ARC600F_INSN_MULULW_CC__RA__RC
+ , ARC600F_INSN_MACHULW_L_S12__RA_, ARC600F_INSN_MACHULW_CCU6__RA_, ARC600F_INSN_MACHULW_L_U6__RA_, ARC600F_INSN_MACHULW_L_R_R__RA__RC
+ , ARC600F_INSN_MACHULW_CC__RA__RC, ARC600F_INSN_CURRENT_LOOP_END, ARC600F_INSN_CURRENT_LOOP_END_AFTER_BRANCH, ARC600F_INSN_ARC600_CURRENT_LOOP_END_AFTER_BRANCH
+ , ARC600F_INSN__MAX
+} ARC600F_INSN_TYPE;
+
+/* Enum declaration for semantic formats in cpu family arc600f. */
+typedef enum arc600f_sfmt_type {
+ ARC600F_SFMT_EMPTY, ARC600F_SFMT_B_S, ARC600F_SFMT_BCC_S, ARC600F_SFMT_BRCC_S
+ , ARC600F_SFMT_BCC_L, ARC600F_SFMT_B_L, ARC600F_SFMT_BRCC_RC, ARC600F_SFMT_BRCC_U6
+ , ARC600F_SFMT_BL_S, ARC600F_SFMT_BLCC, ARC600F_SFMT_BL, ARC600F_SFMT_BL_D
+ , ARC600F_SFMT_LD_ABS, ARC600F_SFMT_LD__AW_ABS, ARC600F_SFMT_LD_ABC, ARC600F_SFMT_LD__AW_ABC
+ , ARC600F_SFMT_LD_S_ABC, ARC600F_SFMT_LD_S_ABU, ARC600F_SFMT_LD_S_ABSP, ARC600F_SFMT_LD_S_GPREL
+ , ARC600F_SFMT_LD_S_PCREL, ARC600F_SFMT_LDB_ABS, ARC600F_SFMT_LDB__AW_ABS, ARC600F_SFMT_LDB_AS_ABS
+ , ARC600F_SFMT_LDB_ABC, ARC600F_SFMT_LDB__AW_ABC, ARC600F_SFMT_LDB_AS_ABC, ARC600F_SFMT_LDB_S_ABC
+ , ARC600F_SFMT_LDB_S_ABU, ARC600F_SFMT_LDB_S_ABSP, ARC600F_SFMT_LDB_S_GPREL, ARC600F_SFMT_LDW_ABS
+ , ARC600F_SFMT_LDW__AW_ABS, ARC600F_SFMT_LDW_ABC, ARC600F_SFMT_LDW__AW_ABC, ARC600F_SFMT_LDW_S_ABC
+ , ARC600F_SFMT_LDW_S_ABU, ARC600F_SFMT_LDW_S_GPREL, ARC600F_SFMT_ST_ABS, ARC600F_SFMT_ST__AW_ABS
+ , ARC600F_SFMT_ST_S_ABU, ARC600F_SFMT_ST_S_ABSP, ARC600F_SFMT_STB_ABS, ARC600F_SFMT_STB__AW_ABS
+ , ARC600F_SFMT_STB_AS_ABS, ARC600F_SFMT_STB_S_ABU, ARC600F_SFMT_STB_S_ABSP, ARC600F_SFMT_STW_ABS
+ , ARC600F_SFMT_STW__AW_ABS, ARC600F_SFMT_STW_S_ABU, ARC600F_SFMT_ADD_L_S12__RA_, ARC600F_SFMT_ADD_CCU6__RA_
+ , ARC600F_SFMT_ADD_L_U6__RA_, ARC600F_SFMT_ADD_L_R_R__RA__RC, ARC600F_SFMT_ADD_CC__RA__RC, ARC600F_SFMT_ADD_S_ABC
+ , ARC600F_SFMT_ADD_S_CBU3, ARC600F_SFMT_ADD_S_MCAH, ARC600F_SFMT_ADD_S_ABSP, ARC600F_SFMT_ADD_S_ASSPSP
+ , ARC600F_SFMT_ADD_S_GP, ARC600F_SFMT_ADD_S_R_U7, ARC600F_SFMT_ADC_L_S12__RA_, ARC600F_SFMT_ADC_CCU6__RA_
+ , ARC600F_SFMT_ADC_L_U6__RA_, ARC600F_SFMT_ADC_L_R_R__RA__RC, ARC600F_SFMT_ADC_CC__RA__RC, ARC600F_SFMT_I16_GO_SUB_S_GO
+ , ARC600F_SFMT_SUB_S_GO_SUB_NE, ARC600F_SFMT_SUB_S_SSB, ARC600F_SFMT_AND_L_S12__RA_, ARC600F_SFMT_AND_CCU6__RA_
+ , ARC600F_SFMT_AND_L_U6__RA_, ARC600F_SFMT_AND_L_R_R__RA__RC, ARC600F_SFMT_AND_CC__RA__RC, ARC600F_SFMT_MOV_L_S12_
+ , ARC600F_SFMT_MOV_CCU6_, ARC600F_SFMT_MOV_L_U6_, ARC600F_SFMT_MOV_L_R_R__RC, ARC600F_SFMT_MOV_CC__RC
+ , ARC600F_SFMT_MOV_S_MCAH, ARC600F_SFMT_MOV_S_MCAHB, ARC600F_SFMT_MOV_S_R_U7, ARC600F_SFMT_TST_L_S12_
+ , ARC600F_SFMT_TST_CCU6_, ARC600F_SFMT_TST_L_U6_, ARC600F_SFMT_TST_L_R_R__RC, ARC600F_SFMT_TST_CC__RC
+ , ARC600F_SFMT_TST_S_GO, ARC600F_SFMT_CMP_L_S12_, ARC600F_SFMT_CMP_CCU6_, ARC600F_SFMT_CMP_L_U6_
+ , ARC600F_SFMT_CMP_L_R_R__RC, ARC600F_SFMT_CMP_CC__RC, ARC600F_SFMT_CMP_S_MCAH, ARC600F_SFMT_CMP_S_R_U7
+ , ARC600F_SFMT_BTST_S_SSB, ARC600F_SFMT_MPY_L_S12__RA_, ARC600F_SFMT_MPY_CCU6__RA_, ARC600F_SFMT_MPY_L_U6__RA_
+ , ARC600F_SFMT_MPY_L_R_R__RA__RC, ARC600F_SFMT_MPY_CC__RA__RC, ARC600F_SFMT_J_L_R_R___RC_NOILINK_, ARC600F_SFMT_J_CC___RC_NOILINK_
+ , ARC600F_SFMT_J_L_R_R___RC_ILINK_, ARC600F_SFMT_J_CC___RC_ILINK_, ARC600F_SFMT_J_L_S12_, ARC600F_SFMT_J_CCU6_
+ , ARC600F_SFMT_J_L_U6_, ARC600F_SFMT_J_S, ARC600F_SFMT_J_S__S, ARC600F_SFMT_J_SEQ__S
+ , ARC600F_SFMT_J_L_S12_D_, ARC600F_SFMT_J_CCU6_D_, ARC600F_SFMT_J_L_U6_D_, ARC600F_SFMT_J_L_R_R_D___RC_
+ , ARC600F_SFMT_J_CC_D___RC_, ARC600F_SFMT_JL_L_S12_, ARC600F_SFMT_JL_CCU6_, ARC600F_SFMT_JL_L_U6_
+ , ARC600F_SFMT_JL_S, ARC600F_SFMT_JL_L_R_R___RC_NOILINK_, ARC600F_SFMT_JL_CC___RC_NOILINK_, ARC600F_SFMT_JL_L_R_R_D___RC_
+ , ARC600F_SFMT_JL_CC_D___RC_, ARC600F_SFMT_JL_S_D, ARC600F_SFMT_LP_L_S12_, ARC600F_SFMT_LPCC_CCU6
+ , ARC600F_SFMT_FLAG_L_S12_, ARC600F_SFMT_FLAG_CCU6_, ARC600F_SFMT_FLAG_L_U6_, ARC600F_SFMT_FLAG_L_R_R__RC
+ , ARC600F_SFMT_FLAG_CC__RC, ARC600F_SFMT_LR_L_R_R___RC_, ARC600F_SFMT_LR_L_S12_, ARC600F_SFMT_LR_L_U6_
+ , ARC600F_SFMT_SR_L_R_R___RC_, ARC600F_SFMT_SR_L_S12_, ARC600F_SFMT_SR_L_U6_, ARC600F_SFMT_ASL_L_R_R__RC
+ , ARC600F_SFMT_ASL_L_U6_, ARC600F_SFMT_ASR_L_R_R__RC, ARC600F_SFMT_ASR_L_U6_, ARC600F_SFMT_RRC_L_R_R__RC
+ , ARC600F_SFMT_RRC_L_U6_, ARC600F_SFMT_SEXB_L_R_R__RC, ARC600F_SFMT_SEXB_L_U6_, ARC600F_SFMT_SEXW_L_R_R__RC
+ , ARC600F_SFMT_SEXW_L_U6_, ARC600F_SFMT_ABS_L_R_R__RC, ARC600F_SFMT_ABS_L_U6_, ARC600F_SFMT_NOT_L_R_R__RC
+ , ARC600F_SFMT_NOT_L_U6_, ARC600F_SFMT_SWI, ARC600F_SFMT_TRAP_S, ARC600F_SFMT_BRK
+ , ARC600F_SFMT_ASL_L_S12__RA_, ARC600F_SFMT_ASL_CCU6__RA_, ARC600F_SFMT_ASL_L_U6__RA_, ARC600F_SFMT_ASL_L_R_R__RA__RC
+ , ARC600F_SFMT_ASL_CC__RA__RC, ARC600F_SFMT_MUL64_L_S12_, ARC600F_SFMT_MUL64_CCU6_, ARC600F_SFMT_MUL64_L_U6_
+ , ARC600F_SFMT_MUL64_L_R_R__RC, ARC600F_SFMT_MUL64_CC__RC, ARC600F_SFMT_MUL64_S_GO, ARC600F_SFMT_ADDS_L_S12__RA_
+ , ARC600F_SFMT_ADDS_CCU6__RA_, ARC600F_SFMT_ADDS_L_U6__RA_, ARC600F_SFMT_ADDS_L_R_R__RA__RC, ARC600F_SFMT_ADDS_CC__RA__RC
+ , ARC600F_SFMT_DIVAW_L_S12__RA_, ARC600F_SFMT_DIVAW_CCU6__RA_, ARC600F_SFMT_DIVAW_L_U6__RA_, ARC600F_SFMT_DIVAW_L_R_R__RA__RC
+ , ARC600F_SFMT_DIVAW_CC__RA__RC, ARC600F_SFMT_ASLS_L_S12__RA_, ARC600F_SFMT_ASLS_CCU6__RA_, ARC600F_SFMT_ASLS_L_U6__RA_
+ , ARC600F_SFMT_ASLS_L_R_R__RA__RC, ARC600F_SFMT_ASLS_CC__RA__RC, ARC600F_SFMT_SWAP_L_R_R__RC, ARC600F_SFMT_SWAP_L_U6_
+ , ARC600F_SFMT_NORM_L_U6_, ARC600F_SFMT_RND16_L_R_R__RC, ARC600F_SFMT_RND16_L_U6_, ARC600F_SFMT_ABSSW_L_R_R__RC
+ , ARC600F_SFMT_ABSSW_L_U6_, ARC600F_SFMT_ABSS_L_U6_, ARC600F_SFMT_NOP_S, ARC600F_SFMT_POP_S_B
+ , ARC600F_SFMT_POP_S_BLINK, ARC600F_SFMT_PUSH_S_B, ARC600F_SFMT_PUSH_S_BLINK, ARC600F_SFMT_MULLW_L_S12__RA_
+ , ARC600F_SFMT_MULLW_CCU6__RA_, ARC600F_SFMT_MULLW_L_U6__RA_, ARC600F_SFMT_MULLW_L_R_R__RA__RC, ARC600F_SFMT_MULLW_CC__RA__RC
+ , ARC600F_SFMT_MACLW_L_S12__RA_, ARC600F_SFMT_MACLW_CCU6__RA_, ARC600F_SFMT_MACLW_L_U6__RA_, ARC600F_SFMT_MACLW_L_R_R__RA__RC
+ , ARC600F_SFMT_MACLW_CC__RA__RC, ARC600F_SFMT_MACHULW_L_S12__RA_, ARC600F_SFMT_MACHULW_CCU6__RA_, ARC600F_SFMT_MACHULW_L_U6__RA_
+ , ARC600F_SFMT_MACHULW_L_R_R__RA__RC, ARC600F_SFMT_MACHULW_CC__RA__RC, ARC600F_SFMT_CURRENT_LOOP_END, ARC600F_SFMT_CURRENT_LOOP_END_AFTER_BRANCH
+} ARC600F_SFMT_TYPE;
+
+/* Function unit handlers (user written). */
+
+extern int arc600f_model_ARC600_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*b*/, INT /*c*/, INT /*a*/);
+
+/* Profiling before/after handlers (user written) */
+
+extern void arc600f_model_insn_before (SIM_CPU *, int /*first_p*/);
+extern void arc600f_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
+
+#endif /* ARC600F_DECODE_H */
diff --git a/sim/arc/decode7.c b/sim/arc/decode7.c
new file mode 100644
index 0000000..2279453
--- /dev/null
+++ b/sim/arc/decode7.c
@@ -0,0 +1,21315 @@
+/* Simulator instruction decoder for arc700f.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2007 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#define WANT_CPU arc700f
+#define WANT_CPU_ARC700F
+
+#include "sim-main.h"
+#include "sim-assert.h"
+
+/* The instruction descriptor array.
+ This is computed at runtime. Space for it is not malloc'd to save a
+ teensy bit of cpu in the decoder. Moving it to malloc space is trivial
+ but won't be done until necessary (we don't currently support the runtime
+ addition of instructions nor an SMP machine with different cpus). */
+static IDESC arc700f_insn_data[ARC700F_INSN__MAX];
+
+/* Commas between elements are contained in the macros.
+ Some of these are conditionally compiled out. */
+
+static const struct insn_sem arc700f_insn_sem[] =
+{
+ { VIRTUAL_INSN_X_INVALID, ARC700F_INSN_X_INVALID, ARC700F_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_AFTER, ARC700F_INSN_X_AFTER, ARC700F_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_BEFORE, ARC700F_INSN_X_BEFORE, ARC700F_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_CTI_CHAIN, ARC700F_INSN_X_CTI_CHAIN, ARC700F_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_CHAIN, ARC700F_INSN_X_CHAIN, ARC700F_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_BEGIN, ARC700F_INSN_X_BEGIN, ARC700F_SFMT_EMPTY },
+ { ARC_INSN_B_S, ARC700F_INSN_B_S, ARC700F_SFMT_B_S },
+ { ARC_INSN_BCC_S, ARC700F_INSN_BCC_S, ARC700F_SFMT_BCC_S },
+ { ARC_INSN_BRCC_S, ARC700F_INSN_BRCC_S, ARC700F_SFMT_BRCC_S },
+ { ARC_INSN_BCC_L, ARC700F_INSN_BCC_L, ARC700F_SFMT_BCC_L },
+ { ARC_INSN_BCC_L_D, ARC700F_INSN_BCC_L_D, ARC700F_SFMT_BCC_L },
+ { ARC_INSN_B_L, ARC700F_INSN_B_L, ARC700F_SFMT_B_L },
+ { ARC_INSN_B_L_D, ARC700F_INSN_B_L_D, ARC700F_SFMT_B_L },
+ { ARC_INSN_BRCC_RC, ARC700F_INSN_BRCC_RC, ARC700F_SFMT_BRCC_RC },
+ { ARC_INSN_BRCC_RC_D, ARC700F_INSN_BRCC_RC_D, ARC700F_SFMT_BRCC_RC },
+ { ARC_INSN_BRCC_U6, ARC700F_INSN_BRCC_U6, ARC700F_SFMT_BRCC_U6 },
+ { ARC_INSN_BRCC_U6_D, ARC700F_INSN_BRCC_U6_D, ARC700F_SFMT_BRCC_U6 },
+ { ARC_INSN_BL_S, ARC700F_INSN_BL_S, ARC700F_SFMT_BL_S },
+ { ARC_INSN_BLCC, ARC700F_INSN_BLCC, ARC700F_SFMT_BLCC },
+ { ARC_INSN_BLCC_D, ARC700F_INSN_BLCC_D, ARC700F_SFMT_BLCC },
+ { ARC_INSN_BL, ARC700F_INSN_BL, ARC700F_SFMT_BL },
+ { ARC_INSN_BL_D, ARC700F_INSN_BL_D, ARC700F_SFMT_BL_D },
+ { ARC_INSN_LD_ABS, ARC700F_INSN_LD_ABS, ARC700F_SFMT_LD_ABS },
+ { ARC_INSN_LD__AW_ABS, ARC700F_INSN_LD__AW_ABS, ARC700F_SFMT_LD__AW_ABS },
+ { ARC_INSN_LD_AB_ABS, ARC700F_INSN_LD_AB_ABS, ARC700F_SFMT_LD__AW_ABS },
+ { ARC_INSN_LD_AS_ABS, ARC700F_INSN_LD_AS_ABS, ARC700F_SFMT_LD_ABS },
+ { ARC_INSN_LD_ABC, ARC700F_INSN_LD_ABC, ARC700F_SFMT_LD_ABC },
+ { ARC_INSN_LD__AW_ABC, ARC700F_INSN_LD__AW_ABC, ARC700F_SFMT_LD__AW_ABC },
+ { ARC_INSN_LD_AB_ABC, ARC700F_INSN_LD_AB_ABC, ARC700F_SFMT_LD__AW_ABC },
+ { ARC_INSN_LD_AS_ABC, ARC700F_INSN_LD_AS_ABC, ARC700F_SFMT_LD_ABC },
+ { ARC_INSN_LD_S_ABC, ARC700F_INSN_LD_S_ABC, ARC700F_SFMT_LD_S_ABC },
+ { ARC_INSN_LD_S_ABU, ARC700F_INSN_LD_S_ABU, ARC700F_SFMT_LD_S_ABU },
+ { ARC_INSN_LD_S_ABSP, ARC700F_INSN_LD_S_ABSP, ARC700F_SFMT_LD_S_ABSP },
+ { ARC_INSN_LD_S_GPREL, ARC700F_INSN_LD_S_GPREL, ARC700F_SFMT_LD_S_GPREL },
+ { ARC_INSN_LD_S_PCREL, ARC700F_INSN_LD_S_PCREL, ARC700F_SFMT_LD_S_PCREL },
+ { ARC_INSN_LDB_ABS, ARC700F_INSN_LDB_ABS, ARC700F_SFMT_LDB_ABS },
+ { ARC_INSN_LDB__AW_ABS, ARC700F_INSN_LDB__AW_ABS, ARC700F_SFMT_LDB__AW_ABS },
+ { ARC_INSN_LDB_AB_ABS, ARC700F_INSN_LDB_AB_ABS, ARC700F_SFMT_LDB__AW_ABS },
+ { ARC_INSN_LDB_AS_ABS, ARC700F_INSN_LDB_AS_ABS, ARC700F_SFMT_LDB_AS_ABS },
+ { ARC_INSN_LDB_ABC, ARC700F_INSN_LDB_ABC, ARC700F_SFMT_LDB_ABC },
+ { ARC_INSN_LDB__AW_ABC, ARC700F_INSN_LDB__AW_ABC, ARC700F_SFMT_LDB__AW_ABC },
+ { ARC_INSN_LDB_AB_ABC, ARC700F_INSN_LDB_AB_ABC, ARC700F_SFMT_LDB__AW_ABC },
+ { ARC_INSN_LDB_AS_ABC, ARC700F_INSN_LDB_AS_ABC, ARC700F_SFMT_LDB_AS_ABC },
+ { ARC_INSN_LDB_S_ABC, ARC700F_INSN_LDB_S_ABC, ARC700F_SFMT_LDB_S_ABC },
+ { ARC_INSN_LDB_S_ABU, ARC700F_INSN_LDB_S_ABU, ARC700F_SFMT_LDB_S_ABU },
+ { ARC_INSN_LDB_S_ABSP, ARC700F_INSN_LDB_S_ABSP, ARC700F_SFMT_LDB_S_ABSP },
+ { ARC_INSN_LDB_S_GPREL, ARC700F_INSN_LDB_S_GPREL, ARC700F_SFMT_LDB_S_GPREL },
+ { ARC_INSN_LDB_X_ABS, ARC700F_INSN_LDB_X_ABS, ARC700F_SFMT_LDB_ABS },
+ { ARC_INSN_LDB__AW_X_ABS, ARC700F_INSN_LDB__AW_X_ABS, ARC700F_SFMT_LDB__AW_ABS },
+ { ARC_INSN_LDB_AB_X_ABS, ARC700F_INSN_LDB_AB_X_ABS, ARC700F_SFMT_LDB__AW_ABS },
+ { ARC_INSN_LDB_AS_X_ABS, ARC700F_INSN_LDB_AS_X_ABS, ARC700F_SFMT_LDB_AS_ABS },
+ { ARC_INSN_LDB_X_ABC, ARC700F_INSN_LDB_X_ABC, ARC700F_SFMT_LDB_ABC },
+ { ARC_INSN_LDB__AW_X_ABC, ARC700F_INSN_LDB__AW_X_ABC, ARC700F_SFMT_LDB__AW_ABC },
+ { ARC_INSN_LDB_AB_X_ABC, ARC700F_INSN_LDB_AB_X_ABC, ARC700F_SFMT_LDB__AW_ABC },
+ { ARC_INSN_LDB_AS_X_ABC, ARC700F_INSN_LDB_AS_X_ABC, ARC700F_SFMT_LDB_AS_ABC },
+ { ARC_INSN_LDW_ABS, ARC700F_INSN_LDW_ABS, ARC700F_SFMT_LDW_ABS },
+ { ARC_INSN_LDW__AW_ABS, ARC700F_INSN_LDW__AW_ABS, ARC700F_SFMT_LDW__AW_ABS },
+ { ARC_INSN_LDW_AB_ABS, ARC700F_INSN_LDW_AB_ABS, ARC700F_SFMT_LDW__AW_ABS },
+ { ARC_INSN_LDW_AS_ABS, ARC700F_INSN_LDW_AS_ABS, ARC700F_SFMT_LDW_ABS },
+ { ARC_INSN_LDW_ABC, ARC700F_INSN_LDW_ABC, ARC700F_SFMT_LDW_ABC },
+ { ARC_INSN_LDW__AW_ABC, ARC700F_INSN_LDW__AW_ABC, ARC700F_SFMT_LDW__AW_ABC },
+ { ARC_INSN_LDW_AB_ABC, ARC700F_INSN_LDW_AB_ABC, ARC700F_SFMT_LDW__AW_ABC },
+ { ARC_INSN_LDW_AS_ABC, ARC700F_INSN_LDW_AS_ABC, ARC700F_SFMT_LDW_ABC },
+ { ARC_INSN_LDW_S_ABC, ARC700F_INSN_LDW_S_ABC, ARC700F_SFMT_LDW_S_ABC },
+ { ARC_INSN_LDW_S_ABU, ARC700F_INSN_LDW_S_ABU, ARC700F_SFMT_LDW_S_ABU },
+ { ARC_INSN_LDW_S_GPREL, ARC700F_INSN_LDW_S_GPREL, ARC700F_SFMT_LDW_S_GPREL },
+ { ARC_INSN_LDW_X_ABS, ARC700F_INSN_LDW_X_ABS, ARC700F_SFMT_LDW_ABS },
+ { ARC_INSN_LDW__AW_X_ABS, ARC700F_INSN_LDW__AW_X_ABS, ARC700F_SFMT_LDW__AW_ABS },
+ { ARC_INSN_LDW_AB_X_ABS, ARC700F_INSN_LDW_AB_X_ABS, ARC700F_SFMT_LDW__AW_ABS },
+ { ARC_INSN_LDW_AS_X_ABS, ARC700F_INSN_LDW_AS_X_ABS, ARC700F_SFMT_LDW_ABS },
+ { ARC_INSN_LDW_X_ABC, ARC700F_INSN_LDW_X_ABC, ARC700F_SFMT_LDW_ABC },
+ { ARC_INSN_LDW__AW_X_ABC, ARC700F_INSN_LDW__AW_X_ABC, ARC700F_SFMT_LDW__AW_ABC },
+ { ARC_INSN_LDW_AB_X_ABC, ARC700F_INSN_LDW_AB_X_ABC, ARC700F_SFMT_LDW__AW_ABC },
+ { ARC_INSN_LDW_AS_X_ABC, ARC700F_INSN_LDW_AS_X_ABC, ARC700F_SFMT_LDW_ABC },
+ { ARC_INSN_LDW_S_X_ABU, ARC700F_INSN_LDW_S_X_ABU, ARC700F_SFMT_LDW_S_ABU },
+ { ARC_INSN_ST_ABS, ARC700F_INSN_ST_ABS, ARC700F_SFMT_ST_ABS },
+ { ARC_INSN_ST__AW_ABS, ARC700F_INSN_ST__AW_ABS, ARC700F_SFMT_ST__AW_ABS },
+ { ARC_INSN_ST_AB_ABS, ARC700F_INSN_ST_AB_ABS, ARC700F_SFMT_ST__AW_ABS },
+ { ARC_INSN_ST_AS_ABS, ARC700F_INSN_ST_AS_ABS, ARC700F_SFMT_ST_ABS },
+ { ARC_INSN_ST_S_ABU, ARC700F_INSN_ST_S_ABU, ARC700F_SFMT_ST_S_ABU },
+ { ARC_INSN_ST_S_ABSP, ARC700F_INSN_ST_S_ABSP, ARC700F_SFMT_ST_S_ABSP },
+ { ARC_INSN_STB_ABS, ARC700F_INSN_STB_ABS, ARC700F_SFMT_STB_ABS },
+ { ARC_INSN_STB__AW_ABS, ARC700F_INSN_STB__AW_ABS, ARC700F_SFMT_STB__AW_ABS },
+ { ARC_INSN_STB_AB_ABS, ARC700F_INSN_STB_AB_ABS, ARC700F_SFMT_STB__AW_ABS },
+ { ARC_INSN_STB_AS_ABS, ARC700F_INSN_STB_AS_ABS, ARC700F_SFMT_STB_AS_ABS },
+ { ARC_INSN_STB_S_ABU, ARC700F_INSN_STB_S_ABU, ARC700F_SFMT_STB_S_ABU },
+ { ARC_INSN_STB_S_ABSP, ARC700F_INSN_STB_S_ABSP, ARC700F_SFMT_STB_S_ABSP },
+ { ARC_INSN_STW_ABS, ARC700F_INSN_STW_ABS, ARC700F_SFMT_STW_ABS },
+ { ARC_INSN_STW__AW_ABS, ARC700F_INSN_STW__AW_ABS, ARC700F_SFMT_STW__AW_ABS },
+ { ARC_INSN_STW_AB_ABS, ARC700F_INSN_STW_AB_ABS, ARC700F_SFMT_STW__AW_ABS },
+ { ARC_INSN_STW_AS_ABS, ARC700F_INSN_STW_AS_ABS, ARC700F_SFMT_STW_ABS },
+ { ARC_INSN_STW_S_ABU, ARC700F_INSN_STW_S_ABU, ARC700F_SFMT_STW_S_ABU },
+ { ARC_INSN_ADD_L_S12__RA_, ARC700F_INSN_ADD_L_S12__RA_, ARC700F_SFMT_ADD_L_S12__RA_ },
+ { ARC_INSN_ADD_CCU6__RA_, ARC700F_INSN_ADD_CCU6__RA_, ARC700F_SFMT_ADD_CCU6__RA_ },
+ { ARC_INSN_ADD_L_U6__RA_, ARC700F_INSN_ADD_L_U6__RA_, ARC700F_SFMT_ADD_L_U6__RA_ },
+ { ARC_INSN_ADD_L_R_R__RA__RC, ARC700F_INSN_ADD_L_R_R__RA__RC, ARC700F_SFMT_ADD_L_R_R__RA__RC },
+ { ARC_INSN_ADD_CC__RA__RC, ARC700F_INSN_ADD_CC__RA__RC, ARC700F_SFMT_ADD_CC__RA__RC },
+ { ARC_INSN_ADD_S_ABC, ARC700F_INSN_ADD_S_ABC, ARC700F_SFMT_ADD_S_ABC },
+ { ARC_INSN_ADD_S_CBU3, ARC700F_INSN_ADD_S_CBU3, ARC700F_SFMT_ADD_S_CBU3 },
+ { ARC_INSN_ADD_S_MCAH, ARC700F_INSN_ADD_S_MCAH, ARC700F_SFMT_ADD_S_MCAH },
+ { ARC_INSN_ADD_S_ABSP, ARC700F_INSN_ADD_S_ABSP, ARC700F_SFMT_ADD_S_ABSP },
+ { ARC_INSN_ADD_S_ASSPSP, ARC700F_INSN_ADD_S_ASSPSP, ARC700F_SFMT_ADD_S_ASSPSP },
+ { ARC_INSN_ADD_S_GP, ARC700F_INSN_ADD_S_GP, ARC700F_SFMT_ADD_S_GP },
+ { ARC_INSN_ADD_S_R_U7, ARC700F_INSN_ADD_S_R_U7, ARC700F_SFMT_ADD_S_R_U7 },
+ { ARC_INSN_ADC_L_S12__RA_, ARC700F_INSN_ADC_L_S12__RA_, ARC700F_SFMT_ADC_L_S12__RA_ },
+ { ARC_INSN_ADC_CCU6__RA_, ARC700F_INSN_ADC_CCU6__RA_, ARC700F_SFMT_ADC_CCU6__RA_ },
+ { ARC_INSN_ADC_L_U6__RA_, ARC700F_INSN_ADC_L_U6__RA_, ARC700F_SFMT_ADC_L_U6__RA_ },
+ { ARC_INSN_ADC_L_R_R__RA__RC, ARC700F_INSN_ADC_L_R_R__RA__RC, ARC700F_SFMT_ADC_L_R_R__RA__RC },
+ { ARC_INSN_ADC_CC__RA__RC, ARC700F_INSN_ADC_CC__RA__RC, ARC700F_SFMT_ADC_CC__RA__RC },
+ { ARC_INSN_SUB_L_S12__RA_, ARC700F_INSN_SUB_L_S12__RA_, ARC700F_SFMT_ADD_L_S12__RA_ },
+ { ARC_INSN_SUB_CCU6__RA_, ARC700F_INSN_SUB_CCU6__RA_, ARC700F_SFMT_ADD_CCU6__RA_ },
+ { ARC_INSN_SUB_L_U6__RA_, ARC700F_INSN_SUB_L_U6__RA_, ARC700F_SFMT_ADD_L_U6__RA_ },
+ { ARC_INSN_SUB_L_R_R__RA__RC, ARC700F_INSN_SUB_L_R_R__RA__RC, ARC700F_SFMT_ADD_L_R_R__RA__RC },
+ { ARC_INSN_SUB_CC__RA__RC, ARC700F_INSN_SUB_CC__RA__RC, ARC700F_SFMT_ADD_CC__RA__RC },
+ { ARC_INSN_SUB_S_CBU3, ARC700F_INSN_SUB_S_CBU3, ARC700F_SFMT_ADD_S_CBU3 },
+ { ARC_INSN_I16_GO_SUB_S_GO, ARC700F_INSN_I16_GO_SUB_S_GO, ARC700F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_SUB_S_GO_SUB_NE, ARC700F_INSN_SUB_S_GO_SUB_NE, ARC700F_SFMT_SUB_S_GO_SUB_NE },
+ { ARC_INSN_SUB_S_SSB, ARC700F_INSN_SUB_S_SSB, ARC700F_SFMT_SUB_S_SSB },
+ { ARC_INSN_SUB_S_ASSPSP, ARC700F_INSN_SUB_S_ASSPSP, ARC700F_SFMT_ADD_S_ASSPSP },
+ { ARC_INSN_SBC_L_S12__RA_, ARC700F_INSN_SBC_L_S12__RA_, ARC700F_SFMT_ADC_L_S12__RA_ },
+ { ARC_INSN_SBC_CCU6__RA_, ARC700F_INSN_SBC_CCU6__RA_, ARC700F_SFMT_ADC_CCU6__RA_ },
+ { ARC_INSN_SBC_L_U6__RA_, ARC700F_INSN_SBC_L_U6__RA_, ARC700F_SFMT_ADC_L_U6__RA_ },
+ { ARC_INSN_SBC_L_R_R__RA__RC, ARC700F_INSN_SBC_L_R_R__RA__RC, ARC700F_SFMT_ADC_L_R_R__RA__RC },
+ { ARC_INSN_SBC_CC__RA__RC, ARC700F_INSN_SBC_CC__RA__RC, ARC700F_SFMT_ADC_CC__RA__RC },
+ { ARC_INSN_AND_L_S12__RA_, ARC700F_INSN_AND_L_S12__RA_, ARC700F_SFMT_AND_L_S12__RA_ },
+ { ARC_INSN_AND_CCU6__RA_, ARC700F_INSN_AND_CCU6__RA_, ARC700F_SFMT_AND_CCU6__RA_ },
+ { ARC_INSN_AND_L_U6__RA_, ARC700F_INSN_AND_L_U6__RA_, ARC700F_SFMT_AND_L_U6__RA_ },
+ { ARC_INSN_AND_L_R_R__RA__RC, ARC700F_INSN_AND_L_R_R__RA__RC, ARC700F_SFMT_AND_L_R_R__RA__RC },
+ { ARC_INSN_AND_CC__RA__RC, ARC700F_INSN_AND_CC__RA__RC, ARC700F_SFMT_AND_CC__RA__RC },
+ { ARC_INSN_I16_GO_AND_S_GO, ARC700F_INSN_I16_GO_AND_S_GO, ARC700F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_OR_L_S12__RA_, ARC700F_INSN_OR_L_S12__RA_, ARC700F_SFMT_AND_L_S12__RA_ },
+ { ARC_INSN_OR_CCU6__RA_, ARC700F_INSN_OR_CCU6__RA_, ARC700F_SFMT_AND_CCU6__RA_ },
+ { ARC_INSN_OR_L_U6__RA_, ARC700F_INSN_OR_L_U6__RA_, ARC700F_SFMT_AND_L_U6__RA_ },
+ { ARC_INSN_OR_L_R_R__RA__RC, ARC700F_INSN_OR_L_R_R__RA__RC, ARC700F_SFMT_AND_L_R_R__RA__RC },
+ { ARC_INSN_OR_CC__RA__RC, ARC700F_INSN_OR_CC__RA__RC, ARC700F_SFMT_AND_CC__RA__RC },
+ { ARC_INSN_I16_GO_OR_S_GO, ARC700F_INSN_I16_GO_OR_S_GO, ARC700F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_BIC_L_S12__RA_, ARC700F_INSN_BIC_L_S12__RA_, ARC700F_SFMT_AND_L_S12__RA_ },
+ { ARC_INSN_BIC_CCU6__RA_, ARC700F_INSN_BIC_CCU6__RA_, ARC700F_SFMT_AND_CCU6__RA_ },
+ { ARC_INSN_BIC_L_U6__RA_, ARC700F_INSN_BIC_L_U6__RA_, ARC700F_SFMT_AND_L_U6__RA_ },
+ { ARC_INSN_BIC_L_R_R__RA__RC, ARC700F_INSN_BIC_L_R_R__RA__RC, ARC700F_SFMT_AND_L_R_R__RA__RC },
+ { ARC_INSN_BIC_CC__RA__RC, ARC700F_INSN_BIC_CC__RA__RC, ARC700F_SFMT_AND_CC__RA__RC },
+ { ARC_INSN_I16_GO_BIC_S_GO, ARC700F_INSN_I16_GO_BIC_S_GO, ARC700F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_XOR_L_S12__RA_, ARC700F_INSN_XOR_L_S12__RA_, ARC700F_SFMT_AND_L_S12__RA_ },
+ { ARC_INSN_XOR_CCU6__RA_, ARC700F_INSN_XOR_CCU6__RA_, ARC700F_SFMT_AND_CCU6__RA_ },
+ { ARC_INSN_XOR_L_U6__RA_, ARC700F_INSN_XOR_L_U6__RA_, ARC700F_SFMT_AND_L_U6__RA_ },
+ { ARC_INSN_XOR_L_R_R__RA__RC, ARC700F_INSN_XOR_L_R_R__RA__RC, ARC700F_SFMT_AND_L_R_R__RA__RC },
+ { ARC_INSN_XOR_CC__RA__RC, ARC700F_INSN_XOR_CC__RA__RC, ARC700F_SFMT_AND_CC__RA__RC },
+ { ARC_INSN_I16_GO_XOR_S_GO, ARC700F_INSN_I16_GO_XOR_S_GO, ARC700F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_MAX_L_S12__RA_, ARC700F_INSN_MAX_L_S12__RA_, ARC700F_SFMT_ADD_L_S12__RA_ },
+ { ARC_INSN_MAX_CCU6__RA_, ARC700F_INSN_MAX_CCU6__RA_, ARC700F_SFMT_ADD_CCU6__RA_ },
+ { ARC_INSN_MAX_L_U6__RA_, ARC700F_INSN_MAX_L_U6__RA_, ARC700F_SFMT_ADD_L_U6__RA_ },
+ { ARC_INSN_MAX_L_R_R__RA__RC, ARC700F_INSN_MAX_L_R_R__RA__RC, ARC700F_SFMT_ADD_L_R_R__RA__RC },
+ { ARC_INSN_MAX_CC__RA__RC, ARC700F_INSN_MAX_CC__RA__RC, ARC700F_SFMT_ADD_CC__RA__RC },
+ { ARC_INSN_MIN_L_S12__RA_, ARC700F_INSN_MIN_L_S12__RA_, ARC700F_SFMT_ADD_L_S12__RA_ },
+ { ARC_INSN_MIN_CCU6__RA_, ARC700F_INSN_MIN_CCU6__RA_, ARC700F_SFMT_ADD_CCU6__RA_ },
+ { ARC_INSN_MIN_L_U6__RA_, ARC700F_INSN_MIN_L_U6__RA_, ARC700F_SFMT_ADD_L_U6__RA_ },
+ { ARC_INSN_MIN_L_R_R__RA__RC, ARC700F_INSN_MIN_L_R_R__RA__RC, ARC700F_SFMT_ADD_L_R_R__RA__RC },
+ { ARC_INSN_MIN_CC__RA__RC, ARC700F_INSN_MIN_CC__RA__RC, ARC700F_SFMT_ADD_CC__RA__RC },
+ { ARC_INSN_MOV_L_S12_, ARC700F_INSN_MOV_L_S12_, ARC700F_SFMT_MOV_L_S12_ },
+ { ARC_INSN_MOV_CCU6_, ARC700F_INSN_MOV_CCU6_, ARC700F_SFMT_MOV_CCU6_ },
+ { ARC_INSN_MOV_L_U6_, ARC700F_INSN_MOV_L_U6_, ARC700F_SFMT_MOV_L_U6_ },
+ { ARC_INSN_MOV_L_R_R__RC, ARC700F_INSN_MOV_L_R_R__RC, ARC700F_SFMT_MOV_L_R_R__RC },
+ { ARC_INSN_MOV_CC__RC, ARC700F_INSN_MOV_CC__RC, ARC700F_SFMT_MOV_CC__RC },
+ { ARC_INSN_MOV_S_MCAH, ARC700F_INSN_MOV_S_MCAH, ARC700F_SFMT_MOV_S_MCAH },
+ { ARC_INSN_MOV_S_MCAHB, ARC700F_INSN_MOV_S_MCAHB, ARC700F_SFMT_MOV_S_MCAHB },
+ { ARC_INSN_MOV_S_R_U7, ARC700F_INSN_MOV_S_R_U7, ARC700F_SFMT_MOV_S_R_U7 },
+ { ARC_INSN_TST_L_S12_, ARC700F_INSN_TST_L_S12_, ARC700F_SFMT_TST_L_S12_ },
+ { ARC_INSN_TST_CCU6_, ARC700F_INSN_TST_CCU6_, ARC700F_SFMT_TST_CCU6_ },
+ { ARC_INSN_TST_L_U6_, ARC700F_INSN_TST_L_U6_, ARC700F_SFMT_TST_L_U6_ },
+ { ARC_INSN_TST_L_R_R__RC, ARC700F_INSN_TST_L_R_R__RC, ARC700F_SFMT_TST_L_R_R__RC },
+ { ARC_INSN_TST_CC__RC, ARC700F_INSN_TST_CC__RC, ARC700F_SFMT_TST_CC__RC },
+ { ARC_INSN_TST_S_GO, ARC700F_INSN_TST_S_GO, ARC700F_SFMT_TST_S_GO },
+ { ARC_INSN_CMP_L_S12_, ARC700F_INSN_CMP_L_S12_, ARC700F_SFMT_CMP_L_S12_ },
+ { ARC_INSN_CMP_CCU6_, ARC700F_INSN_CMP_CCU6_, ARC700F_SFMT_CMP_CCU6_ },
+ { ARC_INSN_CMP_L_U6_, ARC700F_INSN_CMP_L_U6_, ARC700F_SFMT_CMP_L_U6_ },
+ { ARC_INSN_CMP_L_R_R__RC, ARC700F_INSN_CMP_L_R_R__RC, ARC700F_SFMT_CMP_L_R_R__RC },
+ { ARC_INSN_CMP_CC__RC, ARC700F_INSN_CMP_CC__RC, ARC700F_SFMT_CMP_CC__RC },
+ { ARC_INSN_CMP_S_MCAH, ARC700F_INSN_CMP_S_MCAH, ARC700F_SFMT_CMP_S_MCAH },
+ { ARC_INSN_CMP_S_R_U7, ARC700F_INSN_CMP_S_R_U7, ARC700F_SFMT_CMP_S_R_U7 },
+ { ARC_INSN_RCMP_L_S12_, ARC700F_INSN_RCMP_L_S12_, ARC700F_SFMT_CMP_L_S12_ },
+ { ARC_INSN_RCMP_CCU6_, ARC700F_INSN_RCMP_CCU6_, ARC700F_SFMT_CMP_CCU6_ },
+ { ARC_INSN_RCMP_L_U6_, ARC700F_INSN_RCMP_L_U6_, ARC700F_SFMT_CMP_L_U6_ },
+ { ARC_INSN_RCMP_L_R_R__RC, ARC700F_INSN_RCMP_L_R_R__RC, ARC700F_SFMT_CMP_L_R_R__RC },
+ { ARC_INSN_RCMP_CC__RC, ARC700F_INSN_RCMP_CC__RC, ARC700F_SFMT_CMP_CC__RC },
+ { ARC_INSN_RSUB_L_S12__RA_, ARC700F_INSN_RSUB_L_S12__RA_, ARC700F_SFMT_ADD_L_S12__RA_ },
+ { ARC_INSN_RSUB_CCU6__RA_, ARC700F_INSN_RSUB_CCU6__RA_, ARC700F_SFMT_ADD_CCU6__RA_ },
+ { ARC_INSN_RSUB_L_U6__RA_, ARC700F_INSN_RSUB_L_U6__RA_, ARC700F_SFMT_ADD_L_U6__RA_ },
+ { ARC_INSN_RSUB_L_R_R__RA__RC, ARC700F_INSN_RSUB_L_R_R__RA__RC, ARC700F_SFMT_ADD_L_R_R__RA__RC },
+ { ARC_INSN_RSUB_CC__RA__RC, ARC700F_INSN_RSUB_CC__RA__RC, ARC700F_SFMT_ADD_CC__RA__RC },
+ { ARC_INSN_BSET_L_S12__RA_, ARC700F_INSN_BSET_L_S12__RA_, ARC700F_SFMT_AND_L_S12__RA_ },
+ { ARC_INSN_BSET_CCU6__RA_, ARC700F_INSN_BSET_CCU6__RA_, ARC700F_SFMT_AND_CCU6__RA_ },
+ { ARC_INSN_BSET_L_U6__RA_, ARC700F_INSN_BSET_L_U6__RA_, ARC700F_SFMT_AND_L_U6__RA_ },
+ { ARC_INSN_BSET_L_R_R__RA__RC, ARC700F_INSN_BSET_L_R_R__RA__RC, ARC700F_SFMT_AND_L_R_R__RA__RC },
+ { ARC_INSN_BSET_CC__RA__RC, ARC700F_INSN_BSET_CC__RA__RC, ARC700F_SFMT_AND_CC__RA__RC },
+ { ARC_INSN_BSET_S_SSB, ARC700F_INSN_BSET_S_SSB, ARC700F_SFMT_SUB_S_SSB },
+ { ARC_INSN_BCLR_L_S12__RA_, ARC700F_INSN_BCLR_L_S12__RA_, ARC700F_SFMT_AND_L_S12__RA_ },
+ { ARC_INSN_BCLR_CCU6__RA_, ARC700F_INSN_BCLR_CCU6__RA_, ARC700F_SFMT_AND_CCU6__RA_ },
+ { ARC_INSN_BCLR_L_U6__RA_, ARC700F_INSN_BCLR_L_U6__RA_, ARC700F_SFMT_AND_L_U6__RA_ },
+ { ARC_INSN_BCLR_L_R_R__RA__RC, ARC700F_INSN_BCLR_L_R_R__RA__RC, ARC700F_SFMT_AND_L_R_R__RA__RC },
+ { ARC_INSN_BCLR_CC__RA__RC, ARC700F_INSN_BCLR_CC__RA__RC, ARC700F_SFMT_AND_CC__RA__RC },
+ { ARC_INSN_BCLR_S_SSB, ARC700F_INSN_BCLR_S_SSB, ARC700F_SFMT_SUB_S_SSB },
+ { ARC_INSN_BTST_L_S12_, ARC700F_INSN_BTST_L_S12_, ARC700F_SFMT_TST_L_S12_ },
+ { ARC_INSN_BTST_CCU6_, ARC700F_INSN_BTST_CCU6_, ARC700F_SFMT_TST_CCU6_ },
+ { ARC_INSN_BTST_L_U6_, ARC700F_INSN_BTST_L_U6_, ARC700F_SFMT_TST_L_U6_ },
+ { ARC_INSN_BTST_L_R_R__RC, ARC700F_INSN_BTST_L_R_R__RC, ARC700F_SFMT_TST_L_R_R__RC },
+ { ARC_INSN_BTST_CC__RC, ARC700F_INSN_BTST_CC__RC, ARC700F_SFMT_TST_CC__RC },
+ { ARC_INSN_BTST_S_SSB, ARC700F_INSN_BTST_S_SSB, ARC700F_SFMT_BTST_S_SSB },
+ { ARC_INSN_BXOR_L_S12__RA_, ARC700F_INSN_BXOR_L_S12__RA_, ARC700F_SFMT_AND_L_S12__RA_ },
+ { ARC_INSN_BXOR_CCU6__RA_, ARC700F_INSN_BXOR_CCU6__RA_, ARC700F_SFMT_AND_CCU6__RA_ },
+ { ARC_INSN_BXOR_L_U6__RA_, ARC700F_INSN_BXOR_L_U6__RA_, ARC700F_SFMT_AND_L_U6__RA_ },
+ { ARC_INSN_BXOR_L_R_R__RA__RC, ARC700F_INSN_BXOR_L_R_R__RA__RC, ARC700F_SFMT_AND_L_R_R__RA__RC },
+ { ARC_INSN_BXOR_CC__RA__RC, ARC700F_INSN_BXOR_CC__RA__RC, ARC700F_SFMT_AND_CC__RA__RC },
+ { ARC_INSN_BMSK_L_S12__RA_, ARC700F_INSN_BMSK_L_S12__RA_, ARC700F_SFMT_AND_L_S12__RA_ },
+ { ARC_INSN_BMSK_CCU6__RA_, ARC700F_INSN_BMSK_CCU6__RA_, ARC700F_SFMT_AND_CCU6__RA_ },
+ { ARC_INSN_BMSK_L_U6__RA_, ARC700F_INSN_BMSK_L_U6__RA_, ARC700F_SFMT_AND_L_U6__RA_ },
+ { ARC_INSN_BMSK_L_R_R__RA__RC, ARC700F_INSN_BMSK_L_R_R__RA__RC, ARC700F_SFMT_AND_L_R_R__RA__RC },
+ { ARC_INSN_BMSK_CC__RA__RC, ARC700F_INSN_BMSK_CC__RA__RC, ARC700F_SFMT_AND_CC__RA__RC },
+ { ARC_INSN_BMSK_S_SSB, ARC700F_INSN_BMSK_S_SSB, ARC700F_SFMT_SUB_S_SSB },
+ { ARC_INSN_ADD1_L_S12__RA_, ARC700F_INSN_ADD1_L_S12__RA_, ARC700F_SFMT_ADD_L_S12__RA_ },
+ { ARC_INSN_ADD1_CCU6__RA_, ARC700F_INSN_ADD1_CCU6__RA_, ARC700F_SFMT_ADD_CCU6__RA_ },
+ { ARC_INSN_ADD1_L_U6__RA_, ARC700F_INSN_ADD1_L_U6__RA_, ARC700F_SFMT_ADD_L_U6__RA_ },
+ { ARC_INSN_ADD1_L_R_R__RA__RC, ARC700F_INSN_ADD1_L_R_R__RA__RC, ARC700F_SFMT_ADD_L_R_R__RA__RC },
+ { ARC_INSN_ADD1_CC__RA__RC, ARC700F_INSN_ADD1_CC__RA__RC, ARC700F_SFMT_ADD_CC__RA__RC },
+ { ARC_INSN_I16_GO_ADD1_S_GO, ARC700F_INSN_I16_GO_ADD1_S_GO, ARC700F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_ADD2_L_S12__RA_, ARC700F_INSN_ADD2_L_S12__RA_, ARC700F_SFMT_ADD_L_S12__RA_ },
+ { ARC_INSN_ADD2_CCU6__RA_, ARC700F_INSN_ADD2_CCU6__RA_, ARC700F_SFMT_ADD_CCU6__RA_ },
+ { ARC_INSN_ADD2_L_U6__RA_, ARC700F_INSN_ADD2_L_U6__RA_, ARC700F_SFMT_ADD_L_U6__RA_ },
+ { ARC_INSN_ADD2_L_R_R__RA__RC, ARC700F_INSN_ADD2_L_R_R__RA__RC, ARC700F_SFMT_ADD_L_R_R__RA__RC },
+ { ARC_INSN_ADD2_CC__RA__RC, ARC700F_INSN_ADD2_CC__RA__RC, ARC700F_SFMT_ADD_CC__RA__RC },
+ { ARC_INSN_I16_GO_ADD2_S_GO, ARC700F_INSN_I16_GO_ADD2_S_GO, ARC700F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_ADD3_L_S12__RA_, ARC700F_INSN_ADD3_L_S12__RA_, ARC700F_SFMT_ADD_L_S12__RA_ },
+ { ARC_INSN_ADD3_CCU6__RA_, ARC700F_INSN_ADD3_CCU6__RA_, ARC700F_SFMT_ADD_CCU6__RA_ },
+ { ARC_INSN_ADD3_L_U6__RA_, ARC700F_INSN_ADD3_L_U6__RA_, ARC700F_SFMT_ADD_L_U6__RA_ },
+ { ARC_INSN_ADD3_L_R_R__RA__RC, ARC700F_INSN_ADD3_L_R_R__RA__RC, ARC700F_SFMT_ADD_L_R_R__RA__RC },
+ { ARC_INSN_ADD3_CC__RA__RC, ARC700F_INSN_ADD3_CC__RA__RC, ARC700F_SFMT_ADD_CC__RA__RC },
+ { ARC_INSN_I16_GO_ADD3_S_GO, ARC700F_INSN_I16_GO_ADD3_S_GO, ARC700F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_SUB1_L_S12__RA_, ARC700F_INSN_SUB1_L_S12__RA_, ARC700F_SFMT_ADD_L_S12__RA_ },
+ { ARC_INSN_SUB1_CCU6__RA_, ARC700F_INSN_SUB1_CCU6__RA_, ARC700F_SFMT_ADD_CCU6__RA_ },
+ { ARC_INSN_SUB1_L_U6__RA_, ARC700F_INSN_SUB1_L_U6__RA_, ARC700F_SFMT_ADD_L_U6__RA_ },
+ { ARC_INSN_SUB1_L_R_R__RA__RC, ARC700F_INSN_SUB1_L_R_R__RA__RC, ARC700F_SFMT_ADD_L_R_R__RA__RC },
+ { ARC_INSN_SUB1_CC__RA__RC, ARC700F_INSN_SUB1_CC__RA__RC, ARC700F_SFMT_ADD_CC__RA__RC },
+ { ARC_INSN_SUB2_L_S12__RA_, ARC700F_INSN_SUB2_L_S12__RA_, ARC700F_SFMT_ADD_L_S12__RA_ },
+ { ARC_INSN_SUB2_CCU6__RA_, ARC700F_INSN_SUB2_CCU6__RA_, ARC700F_SFMT_ADD_CCU6__RA_ },
+ { ARC_INSN_SUB2_L_U6__RA_, ARC700F_INSN_SUB2_L_U6__RA_, ARC700F_SFMT_ADD_L_U6__RA_ },
+ { ARC_INSN_SUB2_L_R_R__RA__RC, ARC700F_INSN_SUB2_L_R_R__RA__RC, ARC700F_SFMT_ADD_L_R_R__RA__RC },
+ { ARC_INSN_SUB2_CC__RA__RC, ARC700F_INSN_SUB2_CC__RA__RC, ARC700F_SFMT_ADD_CC__RA__RC },
+ { ARC_INSN_SUB3_L_S12__RA_, ARC700F_INSN_SUB3_L_S12__RA_, ARC700F_SFMT_ADD_L_S12__RA_ },
+ { ARC_INSN_SUB3_CCU6__RA_, ARC700F_INSN_SUB3_CCU6__RA_, ARC700F_SFMT_ADD_CCU6__RA_ },
+ { ARC_INSN_SUB3_L_U6__RA_, ARC700F_INSN_SUB3_L_U6__RA_, ARC700F_SFMT_ADD_L_U6__RA_ },
+ { ARC_INSN_SUB3_L_R_R__RA__RC, ARC700F_INSN_SUB3_L_R_R__RA__RC, ARC700F_SFMT_ADD_L_R_R__RA__RC },
+ { ARC_INSN_SUB3_CC__RA__RC, ARC700F_INSN_SUB3_CC__RA__RC, ARC700F_SFMT_ADD_CC__RA__RC },
+ { ARC_INSN_MPY_L_S12__RA_, ARC700F_INSN_MPY_L_S12__RA_, ARC700F_SFMT_MPY_L_S12__RA_ },
+ { ARC_INSN_MPY_CCU6__RA_, ARC700F_INSN_MPY_CCU6__RA_, ARC700F_SFMT_MPY_CCU6__RA_ },
+ { ARC_INSN_MPY_L_U6__RA_, ARC700F_INSN_MPY_L_U6__RA_, ARC700F_SFMT_MPY_L_U6__RA_ },
+ { ARC_INSN_MPY_L_R_R__RA__RC, ARC700F_INSN_MPY_L_R_R__RA__RC, ARC700F_SFMT_MPY_L_R_R__RA__RC },
+ { ARC_INSN_MPY_CC__RA__RC, ARC700F_INSN_MPY_CC__RA__RC, ARC700F_SFMT_MPY_CC__RA__RC },
+ { ARC_INSN_MPYH_L_S12__RA_, ARC700F_INSN_MPYH_L_S12__RA_, ARC700F_SFMT_MPY_L_S12__RA_ },
+ { ARC_INSN_MPYH_CCU6__RA_, ARC700F_INSN_MPYH_CCU6__RA_, ARC700F_SFMT_MPY_CCU6__RA_ },
+ { ARC_INSN_MPYH_L_U6__RA_, ARC700F_INSN_MPYH_L_U6__RA_, ARC700F_SFMT_MPY_L_U6__RA_ },
+ { ARC_INSN_MPYH_L_R_R__RA__RC, ARC700F_INSN_MPYH_L_R_R__RA__RC, ARC700F_SFMT_MPY_L_R_R__RA__RC },
+ { ARC_INSN_MPYH_CC__RA__RC, ARC700F_INSN_MPYH_CC__RA__RC, ARC700F_SFMT_MPY_CC__RA__RC },
+ { ARC_INSN_MPYHU_L_S12__RA_, ARC700F_INSN_MPYHU_L_S12__RA_, ARC700F_SFMT_MPY_L_S12__RA_ },
+ { ARC_INSN_MPYHU_CCU6__RA_, ARC700F_INSN_MPYHU_CCU6__RA_, ARC700F_SFMT_MPY_CCU6__RA_ },
+ { ARC_INSN_MPYHU_L_U6__RA_, ARC700F_INSN_MPYHU_L_U6__RA_, ARC700F_SFMT_MPY_L_U6__RA_ },
+ { ARC_INSN_MPYHU_L_R_R__RA__RC, ARC700F_INSN_MPYHU_L_R_R__RA__RC, ARC700F_SFMT_MPY_L_R_R__RA__RC },
+ { ARC_INSN_MPYHU_CC__RA__RC, ARC700F_INSN_MPYHU_CC__RA__RC, ARC700F_SFMT_MPY_CC__RA__RC },
+ { ARC_INSN_MPYU_L_S12__RA_, ARC700F_INSN_MPYU_L_S12__RA_, ARC700F_SFMT_MPY_L_S12__RA_ },
+ { ARC_INSN_MPYU_CCU6__RA_, ARC700F_INSN_MPYU_CCU6__RA_, ARC700F_SFMT_MPY_CCU6__RA_ },
+ { ARC_INSN_MPYU_L_U6__RA_, ARC700F_INSN_MPYU_L_U6__RA_, ARC700F_SFMT_MPY_L_U6__RA_ },
+ { ARC_INSN_MPYU_L_R_R__RA__RC, ARC700F_INSN_MPYU_L_R_R__RA__RC, ARC700F_SFMT_MPY_L_R_R__RA__RC },
+ { ARC_INSN_MPYU_CC__RA__RC, ARC700F_INSN_MPYU_CC__RA__RC, ARC700F_SFMT_MPY_CC__RA__RC },
+ { ARC_INSN_J_L_R_R___RC_NOILINK_, ARC700F_INSN_J_L_R_R___RC_NOILINK_, ARC700F_SFMT_J_L_R_R___RC_NOILINK_ },
+ { ARC_INSN_J_CC___RC_NOILINK_, ARC700F_INSN_J_CC___RC_NOILINK_, ARC700F_SFMT_J_CC___RC_NOILINK_ },
+ { ARC_INSN_J_L_R_R___RC_ILINK_, ARC700F_INSN_J_L_R_R___RC_ILINK_, ARC700F_SFMT_J_L_R_R___RC_ILINK_ },
+ { ARC_INSN_J_CC___RC_ILINK_, ARC700F_INSN_J_CC___RC_ILINK_, ARC700F_SFMT_J_CC___RC_ILINK_ },
+ { ARC_INSN_J_L_S12_, ARC700F_INSN_J_L_S12_, ARC700F_SFMT_J_L_S12_ },
+ { ARC_INSN_J_CCU6_, ARC700F_INSN_J_CCU6_, ARC700F_SFMT_J_CCU6_ },
+ { ARC_INSN_J_L_U6_, ARC700F_INSN_J_L_U6_, ARC700F_SFMT_J_L_U6_ },
+ { ARC_INSN_J_S, ARC700F_INSN_J_S, ARC700F_SFMT_J_S },
+ { ARC_INSN_J_S__S, ARC700F_INSN_J_S__S, ARC700F_SFMT_J_S__S },
+ { ARC_INSN_J_SEQ__S, ARC700F_INSN_J_SEQ__S, ARC700F_SFMT_J_SEQ__S },
+ { ARC_INSN_J_SNE__S, ARC700F_INSN_J_SNE__S, ARC700F_SFMT_J_SEQ__S },
+ { ARC_INSN_J_L_S12_D_, ARC700F_INSN_J_L_S12_D_, ARC700F_SFMT_J_L_S12_D_ },
+ { ARC_INSN_J_CCU6_D_, ARC700F_INSN_J_CCU6_D_, ARC700F_SFMT_J_CCU6_D_ },
+ { ARC_INSN_J_L_U6_D_, ARC700F_INSN_J_L_U6_D_, ARC700F_SFMT_J_L_U6_D_ },
+ { ARC_INSN_J_L_R_R_D___RC_, ARC700F_INSN_J_L_R_R_D___RC_, ARC700F_SFMT_J_L_R_R_D___RC_ },
+ { ARC_INSN_J_CC_D___RC_, ARC700F_INSN_J_CC_D___RC_, ARC700F_SFMT_J_CC_D___RC_ },
+ { ARC_INSN_J_S_D, ARC700F_INSN_J_S_D, ARC700F_SFMT_J_S },
+ { ARC_INSN_J_S__S_D, ARC700F_INSN_J_S__S_D, ARC700F_SFMT_J_S__S },
+ { ARC_INSN_JL_L_S12_, ARC700F_INSN_JL_L_S12_, ARC700F_SFMT_JL_L_S12_ },
+ { ARC_INSN_JL_CCU6_, ARC700F_INSN_JL_CCU6_, ARC700F_SFMT_JL_CCU6_ },
+ { ARC_INSN_JL_L_U6_, ARC700F_INSN_JL_L_U6_, ARC700F_SFMT_JL_L_U6_ },
+ { ARC_INSN_JL_S, ARC700F_INSN_JL_S, ARC700F_SFMT_JL_S },
+ { ARC_INSN_JL_L_R_R___RC_NOILINK_, ARC700F_INSN_JL_L_R_R___RC_NOILINK_, ARC700F_SFMT_JL_L_R_R___RC_NOILINK_ },
+ { ARC_INSN_JL_CC___RC_NOILINK_, ARC700F_INSN_JL_CC___RC_NOILINK_, ARC700F_SFMT_JL_CC___RC_NOILINK_ },
+ { ARC_INSN_JL_L_S12_D_, ARC700F_INSN_JL_L_S12_D_, ARC700F_SFMT_JL_L_S12_ },
+ { ARC_INSN_JL_CCU6_D_, ARC700F_INSN_JL_CCU6_D_, ARC700F_SFMT_JL_CCU6_ },
+ { ARC_INSN_JL_L_U6_D_, ARC700F_INSN_JL_L_U6_D_, ARC700F_SFMT_JL_L_U6_ },
+ { ARC_INSN_JL_L_R_R_D___RC_, ARC700F_INSN_JL_L_R_R_D___RC_, ARC700F_SFMT_JL_L_R_R_D___RC_ },
+ { ARC_INSN_JL_CC_D___RC_, ARC700F_INSN_JL_CC_D___RC_, ARC700F_SFMT_JL_CC_D___RC_ },
+ { ARC_INSN_JL_S_D, ARC700F_INSN_JL_S_D, ARC700F_SFMT_JL_S_D },
+ { ARC_INSN_LP_L_S12_, ARC700F_INSN_LP_L_S12_, ARC700F_SFMT_LP_L_S12_ },
+ { ARC_INSN_LPCC_CCU6, ARC700F_INSN_LPCC_CCU6, ARC700F_SFMT_LPCC_CCU6 },
+ { ARC_INSN_FLAG_L_S12_, ARC700F_INSN_FLAG_L_S12_, ARC700F_SFMT_FLAG_L_S12_ },
+ { ARC_INSN_FLAG_CCU6_, ARC700F_INSN_FLAG_CCU6_, ARC700F_SFMT_FLAG_CCU6_ },
+ { ARC_INSN_FLAG_L_U6_, ARC700F_INSN_FLAG_L_U6_, ARC700F_SFMT_FLAG_L_U6_ },
+ { ARC_INSN_FLAG_L_R_R__RC, ARC700F_INSN_FLAG_L_R_R__RC, ARC700F_SFMT_FLAG_L_R_R__RC },
+ { ARC_INSN_FLAG_CC__RC, ARC700F_INSN_FLAG_CC__RC, ARC700F_SFMT_FLAG_CC__RC },
+ { ARC_INSN_LR_L_R_R___RC_, ARC700F_INSN_LR_L_R_R___RC_, ARC700F_SFMT_LR_L_R_R___RC_ },
+ { ARC_INSN_LR_L_S12_, ARC700F_INSN_LR_L_S12_, ARC700F_SFMT_LR_L_S12_ },
+ { ARC_INSN_LR_L_U6_, ARC700F_INSN_LR_L_U6_, ARC700F_SFMT_LR_L_U6_ },
+ { ARC_INSN_SR_L_R_R___RC_, ARC700F_INSN_SR_L_R_R___RC_, ARC700F_SFMT_SR_L_R_R___RC_ },
+ { ARC_INSN_SR_L_S12_, ARC700F_INSN_SR_L_S12_, ARC700F_SFMT_SR_L_S12_ },
+ { ARC_INSN_SR_L_U6_, ARC700F_INSN_SR_L_U6_, ARC700F_SFMT_SR_L_U6_ },
+ { ARC_INSN_ASL_L_R_R__RC, ARC700F_INSN_ASL_L_R_R__RC, ARC700F_SFMT_ASL_L_R_R__RC },
+ { ARC_INSN_ASL_L_U6_, ARC700F_INSN_ASL_L_U6_, ARC700F_SFMT_ASL_L_U6_ },
+ { ARC_INSN_I16_GO_ASL_S_GO, ARC700F_INSN_I16_GO_ASL_S_GO, ARC700F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_ASR_L_R_R__RC, ARC700F_INSN_ASR_L_R_R__RC, ARC700F_SFMT_ASR_L_R_R__RC },
+ { ARC_INSN_ASR_L_U6_, ARC700F_INSN_ASR_L_U6_, ARC700F_SFMT_ASR_L_U6_ },
+ { ARC_INSN_I16_GO_ASR_S_GO, ARC700F_INSN_I16_GO_ASR_S_GO, ARC700F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_LSR_L_R_R__RC, ARC700F_INSN_LSR_L_R_R__RC, ARC700F_SFMT_ASR_L_R_R__RC },
+ { ARC_INSN_LSR_L_U6_, ARC700F_INSN_LSR_L_U6_, ARC700F_SFMT_ASR_L_U6_ },
+ { ARC_INSN_I16_GO_LSR_S_GO, ARC700F_INSN_I16_GO_LSR_S_GO, ARC700F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_ROR_L_R_R__RC, ARC700F_INSN_ROR_L_R_R__RC, ARC700F_SFMT_ASR_L_R_R__RC },
+ { ARC_INSN_ROR_L_U6_, ARC700F_INSN_ROR_L_U6_, ARC700F_SFMT_ASR_L_U6_ },
+ { ARC_INSN_RRC_L_R_R__RC, ARC700F_INSN_RRC_L_R_R__RC, ARC700F_SFMT_RRC_L_R_R__RC },
+ { ARC_INSN_RRC_L_U6_, ARC700F_INSN_RRC_L_U6_, ARC700F_SFMT_RRC_L_U6_ },
+ { ARC_INSN_SEXB_L_R_R__RC, ARC700F_INSN_SEXB_L_R_R__RC, ARC700F_SFMT_SEXB_L_R_R__RC },
+ { ARC_INSN_SEXB_L_U6_, ARC700F_INSN_SEXB_L_U6_, ARC700F_SFMT_SEXB_L_U6_ },
+ { ARC_INSN_I16_GO_SEXB_S_GO, ARC700F_INSN_I16_GO_SEXB_S_GO, ARC700F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_SEXW_L_R_R__RC, ARC700F_INSN_SEXW_L_R_R__RC, ARC700F_SFMT_SEXW_L_R_R__RC },
+ { ARC_INSN_SEXW_L_U6_, ARC700F_INSN_SEXW_L_U6_, ARC700F_SFMT_SEXW_L_U6_ },
+ { ARC_INSN_I16_GO_SEXW_S_GO, ARC700F_INSN_I16_GO_SEXW_S_GO, ARC700F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_EXTB_L_R_R__RC, ARC700F_INSN_EXTB_L_R_R__RC, ARC700F_SFMT_SEXB_L_R_R__RC },
+ { ARC_INSN_EXTB_L_U6_, ARC700F_INSN_EXTB_L_U6_, ARC700F_SFMT_SEXB_L_U6_ },
+ { ARC_INSN_I16_GO_EXTB_S_GO, ARC700F_INSN_I16_GO_EXTB_S_GO, ARC700F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_EXTW_L_R_R__RC, ARC700F_INSN_EXTW_L_R_R__RC, ARC700F_SFMT_SEXW_L_R_R__RC },
+ { ARC_INSN_EXTW_L_U6_, ARC700F_INSN_EXTW_L_U6_, ARC700F_SFMT_SEXW_L_U6_ },
+ { ARC_INSN_I16_GO_EXTW_S_GO, ARC700F_INSN_I16_GO_EXTW_S_GO, ARC700F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_ABS_L_R_R__RC, ARC700F_INSN_ABS_L_R_R__RC, ARC700F_SFMT_ABS_L_R_R__RC },
+ { ARC_INSN_ABS_L_U6_, ARC700F_INSN_ABS_L_U6_, ARC700F_SFMT_ABS_L_U6_ },
+ { ARC_INSN_I16_GO_ABS_S_GO, ARC700F_INSN_I16_GO_ABS_S_GO, ARC700F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_NOT_L_R_R__RC, ARC700F_INSN_NOT_L_R_R__RC, ARC700F_SFMT_NOT_L_R_R__RC },
+ { ARC_INSN_NOT_L_U6_, ARC700F_INSN_NOT_L_U6_, ARC700F_SFMT_NOT_L_U6_ },
+ { ARC_INSN_I16_GO_NOT_S_GO, ARC700F_INSN_I16_GO_NOT_S_GO, ARC700F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_RLC_L_R_R__RC, ARC700F_INSN_RLC_L_R_R__RC, ARC700F_SFMT_RRC_L_R_R__RC },
+ { ARC_INSN_RLC_L_U6_, ARC700F_INSN_RLC_L_U6_, ARC700F_SFMT_RRC_L_U6_ },
+ { ARC_INSN_EX_L_R_R__RC, ARC700F_INSN_EX_L_R_R__RC, ARC700F_SFMT_EX_L_R_R__RC },
+ { ARC_INSN_EX_L_U6_, ARC700F_INSN_EX_L_U6_, ARC700F_SFMT_EX_L_U6_ },
+ { ARC_INSN_I16_GO_NEG_S_GO, ARC700F_INSN_I16_GO_NEG_S_GO, ARC700F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_SWI, ARC700F_INSN_SWI, ARC700F_SFMT_SWI },
+ { ARC_INSN_TRAP_S, ARC700F_INSN_TRAP_S, ARC700F_SFMT_TRAP_S },
+ { ARC_INSN_BRK, ARC700F_INSN_BRK, ARC700F_SFMT_BRK },
+ { ARC_INSN_BRK_S, ARC700F_INSN_BRK_S, ARC700F_SFMT_BRK },
+ { ARC_INSN_ASL_L_S12__RA_, ARC700F_INSN_ASL_L_S12__RA_, ARC700F_SFMT_ASL_L_S12__RA_ },
+ { ARC_INSN_ASL_CCU6__RA_, ARC700F_INSN_ASL_CCU6__RA_, ARC700F_SFMT_ASL_CCU6__RA_ },
+ { ARC_INSN_ASL_L_U6__RA_, ARC700F_INSN_ASL_L_U6__RA_, ARC700F_SFMT_ASL_L_U6__RA_ },
+ { ARC_INSN_ASL_L_R_R__RA__RC, ARC700F_INSN_ASL_L_R_R__RA__RC, ARC700F_SFMT_ASL_L_R_R__RA__RC },
+ { ARC_INSN_ASL_CC__RA__RC, ARC700F_INSN_ASL_CC__RA__RC, ARC700F_SFMT_ASL_CC__RA__RC },
+ { ARC_INSN_ASL_S_CBU3, ARC700F_INSN_ASL_S_CBU3, ARC700F_SFMT_ADD_S_CBU3 },
+ { ARC_INSN_ASL_S_SSB, ARC700F_INSN_ASL_S_SSB, ARC700F_SFMT_SUB_S_SSB },
+ { ARC_INSN_I16_GO_ASLM_S_GO, ARC700F_INSN_I16_GO_ASLM_S_GO, ARC700F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_LSR_L_S12__RA_, ARC700F_INSN_LSR_L_S12__RA_, ARC700F_SFMT_ASL_L_S12__RA_ },
+ { ARC_INSN_LSR_CCU6__RA_, ARC700F_INSN_LSR_CCU6__RA_, ARC700F_SFMT_ASL_CCU6__RA_ },
+ { ARC_INSN_LSR_L_U6__RA_, ARC700F_INSN_LSR_L_U6__RA_, ARC700F_SFMT_ASL_L_U6__RA_ },
+ { ARC_INSN_LSR_L_R_R__RA__RC, ARC700F_INSN_LSR_L_R_R__RA__RC, ARC700F_SFMT_ASL_L_R_R__RA__RC },
+ { ARC_INSN_LSR_CC__RA__RC, ARC700F_INSN_LSR_CC__RA__RC, ARC700F_SFMT_ASL_CC__RA__RC },
+ { ARC_INSN_LSR_S_SSB, ARC700F_INSN_LSR_S_SSB, ARC700F_SFMT_SUB_S_SSB },
+ { ARC_INSN_I16_GO_LSRM_S_GO, ARC700F_INSN_I16_GO_LSRM_S_GO, ARC700F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_ASR_L_S12__RA_, ARC700F_INSN_ASR_L_S12__RA_, ARC700F_SFMT_ASL_L_S12__RA_ },
+ { ARC_INSN_ASR_CCU6__RA_, ARC700F_INSN_ASR_CCU6__RA_, ARC700F_SFMT_ASL_CCU6__RA_ },
+ { ARC_INSN_ASR_L_U6__RA_, ARC700F_INSN_ASR_L_U6__RA_, ARC700F_SFMT_ASL_L_U6__RA_ },
+ { ARC_INSN_ASR_L_R_R__RA__RC, ARC700F_INSN_ASR_L_R_R__RA__RC, ARC700F_SFMT_ASL_L_R_R__RA__RC },
+ { ARC_INSN_ASR_CC__RA__RC, ARC700F_INSN_ASR_CC__RA__RC, ARC700F_SFMT_ASL_CC__RA__RC },
+ { ARC_INSN_ASR_S_CBU3, ARC700F_INSN_ASR_S_CBU3, ARC700F_SFMT_ADD_S_CBU3 },
+ { ARC_INSN_ASR_S_SSB, ARC700F_INSN_ASR_S_SSB, ARC700F_SFMT_SUB_S_SSB },
+ { ARC_INSN_I16_GO_ASRM_S_GO, ARC700F_INSN_I16_GO_ASRM_S_GO, ARC700F_SFMT_I16_GO_SUB_S_GO },
+ { ARC_INSN_ROR_L_S12__RA_, ARC700F_INSN_ROR_L_S12__RA_, ARC700F_SFMT_ASL_L_S12__RA_ },
+ { ARC_INSN_ROR_CCU6__RA_, ARC700F_INSN_ROR_CCU6__RA_, ARC700F_SFMT_ASL_CCU6__RA_ },
+ { ARC_INSN_ROR_L_U6__RA_, ARC700F_INSN_ROR_L_U6__RA_, ARC700F_SFMT_ASL_L_U6__RA_ },
+ { ARC_INSN_ROR_L_R_R__RA__RC, ARC700F_INSN_ROR_L_R_R__RA__RC, ARC700F_SFMT_ASL_L_R_R__RA__RC },
+ { ARC_INSN_ROR_CC__RA__RC, ARC700F_INSN_ROR_CC__RA__RC, ARC700F_SFMT_ASL_CC__RA__RC },
+ { ARC_INSN_MUL64_L_S12_, ARC700F_INSN_MUL64_L_S12_, ARC700F_SFMT_MUL64_L_S12_ },
+ { ARC_INSN_MUL64_CCU6_, ARC700F_INSN_MUL64_CCU6_, ARC700F_SFMT_MUL64_CCU6_ },
+ { ARC_INSN_MUL64_L_U6_, ARC700F_INSN_MUL64_L_U6_, ARC700F_SFMT_MUL64_L_U6_ },
+ { ARC_INSN_MUL64_L_R_R__RC, ARC700F_INSN_MUL64_L_R_R__RC, ARC700F_SFMT_MUL64_L_R_R__RC },
+ { ARC_INSN_MUL64_CC__RC, ARC700F_INSN_MUL64_CC__RC, ARC700F_SFMT_MUL64_CC__RC },
+ { ARC_INSN_MUL64_S_GO, ARC700F_INSN_MUL64_S_GO, ARC700F_SFMT_MUL64_S_GO },
+ { ARC_INSN_MULU64_L_S12_, ARC700F_INSN_MULU64_L_S12_, ARC700F_SFMT_MUL64_L_S12_ },
+ { ARC_INSN_MULU64_CCU6_, ARC700F_INSN_MULU64_CCU6_, ARC700F_SFMT_MUL64_CCU6_ },
+ { ARC_INSN_MULU64_L_U6_, ARC700F_INSN_MULU64_L_U6_, ARC700F_SFMT_MUL64_L_U6_ },
+ { ARC_INSN_MULU64_L_R_R__RC, ARC700F_INSN_MULU64_L_R_R__RC, ARC700F_SFMT_MUL64_L_R_R__RC },
+ { ARC_INSN_MULU64_CC__RC, ARC700F_INSN_MULU64_CC__RC, ARC700F_SFMT_MUL64_CC__RC },
+ { ARC_INSN_ADDS_L_S12__RA_, ARC700F_INSN_ADDS_L_S12__RA_, ARC700F_SFMT_ADDS_L_S12__RA_ },
+ { ARC_INSN_ADDS_CCU6__RA_, ARC700F_INSN_ADDS_CCU6__RA_, ARC700F_SFMT_ADDS_CCU6__RA_ },
+ { ARC_INSN_ADDS_L_U6__RA_, ARC700F_INSN_ADDS_L_U6__RA_, ARC700F_SFMT_ADDS_L_U6__RA_ },
+ { ARC_INSN_ADDS_L_R_R__RA__RC, ARC700F_INSN_ADDS_L_R_R__RA__RC, ARC700F_SFMT_ADDS_L_R_R__RA__RC },
+ { ARC_INSN_ADDS_CC__RA__RC, ARC700F_INSN_ADDS_CC__RA__RC, ARC700F_SFMT_ADDS_CC__RA__RC },
+ { ARC_INSN_SUBS_L_S12__RA_, ARC700F_INSN_SUBS_L_S12__RA_, ARC700F_SFMT_ADDS_L_S12__RA_ },
+ { ARC_INSN_SUBS_CCU6__RA_, ARC700F_INSN_SUBS_CCU6__RA_, ARC700F_SFMT_ADDS_CCU6__RA_ },
+ { ARC_INSN_SUBS_L_U6__RA_, ARC700F_INSN_SUBS_L_U6__RA_, ARC700F_SFMT_ADDS_L_U6__RA_ },
+ { ARC_INSN_SUBS_L_R_R__RA__RC, ARC700F_INSN_SUBS_L_R_R__RA__RC, ARC700F_SFMT_ADDS_L_R_R__RA__RC },
+ { ARC_INSN_SUBS_CC__RA__RC, ARC700F_INSN_SUBS_CC__RA__RC, ARC700F_SFMT_ADDS_CC__RA__RC },
+ { ARC_INSN_DIVAW_L_S12__RA_, ARC700F_INSN_DIVAW_L_S12__RA_, ARC700F_SFMT_DIVAW_L_S12__RA_ },
+ { ARC_INSN_DIVAW_CCU6__RA_, ARC700F_INSN_DIVAW_CCU6__RA_, ARC700F_SFMT_DIVAW_CCU6__RA_ },
+ { ARC_INSN_DIVAW_L_U6__RA_, ARC700F_INSN_DIVAW_L_U6__RA_, ARC700F_SFMT_DIVAW_L_U6__RA_ },
+ { ARC_INSN_DIVAW_L_R_R__RA__RC, ARC700F_INSN_DIVAW_L_R_R__RA__RC, ARC700F_SFMT_DIVAW_L_R_R__RA__RC },
+ { ARC_INSN_DIVAW_CC__RA__RC, ARC700F_INSN_DIVAW_CC__RA__RC, ARC700F_SFMT_DIVAW_CC__RA__RC },
+ { ARC_INSN_ASLS_L_S12__RA_, ARC700F_INSN_ASLS_L_S12__RA_, ARC700F_SFMT_ASLS_L_S12__RA_ },
+ { ARC_INSN_ASLS_CCU6__RA_, ARC700F_INSN_ASLS_CCU6__RA_, ARC700F_SFMT_ASLS_CCU6__RA_ },
+ { ARC_INSN_ASLS_L_U6__RA_, ARC700F_INSN_ASLS_L_U6__RA_, ARC700F_SFMT_ASLS_L_U6__RA_ },
+ { ARC_INSN_ASLS_L_R_R__RA__RC, ARC700F_INSN_ASLS_L_R_R__RA__RC, ARC700F_SFMT_ASLS_L_R_R__RA__RC },
+ { ARC_INSN_ASLS_CC__RA__RC, ARC700F_INSN_ASLS_CC__RA__RC, ARC700F_SFMT_ASLS_CC__RA__RC },
+ { ARC_INSN_ASRS_L_S12__RA_, ARC700F_INSN_ASRS_L_S12__RA_, ARC700F_SFMT_ASLS_L_S12__RA_ },
+ { ARC_INSN_ASRS_CCU6__RA_, ARC700F_INSN_ASRS_CCU6__RA_, ARC700F_SFMT_ASLS_CCU6__RA_ },
+ { ARC_INSN_ASRS_L_U6__RA_, ARC700F_INSN_ASRS_L_U6__RA_, ARC700F_SFMT_ASLS_L_U6__RA_ },
+ { ARC_INSN_ASRS_L_R_R__RA__RC, ARC700F_INSN_ASRS_L_R_R__RA__RC, ARC700F_SFMT_ASLS_L_R_R__RA__RC },
+ { ARC_INSN_ASRS_CC__RA__RC, ARC700F_INSN_ASRS_CC__RA__RC, ARC700F_SFMT_ASLS_CC__RA__RC },
+ { ARC_INSN_ADDSDW_L_S12__RA_, ARC700F_INSN_ADDSDW_L_S12__RA_, ARC700F_SFMT_ASLS_L_S12__RA_ },
+ { ARC_INSN_ADDSDW_CCU6__RA_, ARC700F_INSN_ADDSDW_CCU6__RA_, ARC700F_SFMT_ASLS_CCU6__RA_ },
+ { ARC_INSN_ADDSDW_L_U6__RA_, ARC700F_INSN_ADDSDW_L_U6__RA_, ARC700F_SFMT_ASLS_L_U6__RA_ },
+ { ARC_INSN_ADDSDW_L_R_R__RA__RC, ARC700F_INSN_ADDSDW_L_R_R__RA__RC, ARC700F_SFMT_ASLS_L_R_R__RA__RC },
+ { ARC_INSN_ADDSDW_CC__RA__RC, ARC700F_INSN_ADDSDW_CC__RA__RC, ARC700F_SFMT_ASLS_CC__RA__RC },
+ { ARC_INSN_SUBSDW_L_S12__RA_, ARC700F_INSN_SUBSDW_L_S12__RA_, ARC700F_SFMT_ASLS_L_S12__RA_ },
+ { ARC_INSN_SUBSDW_CCU6__RA_, ARC700F_INSN_SUBSDW_CCU6__RA_, ARC700F_SFMT_ASLS_CCU6__RA_ },
+ { ARC_INSN_SUBSDW_L_U6__RA_, ARC700F_INSN_SUBSDW_L_U6__RA_, ARC700F_SFMT_ASLS_L_U6__RA_ },
+ { ARC_INSN_SUBSDW_L_R_R__RA__RC, ARC700F_INSN_SUBSDW_L_R_R__RA__RC, ARC700F_SFMT_ASLS_L_R_R__RA__RC },
+ { ARC_INSN_SUBSDW_CC__RA__RC, ARC700F_INSN_SUBSDW_CC__RA__RC, ARC700F_SFMT_ASLS_CC__RA__RC },
+ { ARC_INSN_SWAP_L_R_R__RC, ARC700F_INSN_SWAP_L_R_R__RC, ARC700F_SFMT_SWAP_L_R_R__RC },
+ { ARC_INSN_SWAP_L_U6_, ARC700F_INSN_SWAP_L_U6_, ARC700F_SFMT_SWAP_L_U6_ },
+ { ARC_INSN_NORM_L_R_R__RC, ARC700F_INSN_NORM_L_R_R__RC, ARC700F_SFMT_SWAP_L_R_R__RC },
+ { ARC_INSN_NORM_L_U6_, ARC700F_INSN_NORM_L_U6_, ARC700F_SFMT_NORM_L_U6_ },
+ { ARC_INSN_RND16_L_R_R__RC, ARC700F_INSN_RND16_L_R_R__RC, ARC700F_SFMT_RND16_L_R_R__RC },
+ { ARC_INSN_RND16_L_U6_, ARC700F_INSN_RND16_L_U6_, ARC700F_SFMT_RND16_L_U6_ },
+ { ARC_INSN_ABSSW_L_R_R__RC, ARC700F_INSN_ABSSW_L_R_R__RC, ARC700F_SFMT_ABSSW_L_R_R__RC },
+ { ARC_INSN_ABSSW_L_U6_, ARC700F_INSN_ABSSW_L_U6_, ARC700F_SFMT_ABSSW_L_U6_ },
+ { ARC_INSN_ABSS_L_R_R__RC, ARC700F_INSN_ABSS_L_R_R__RC, ARC700F_SFMT_RND16_L_R_R__RC },
+ { ARC_INSN_ABSS_L_U6_, ARC700F_INSN_ABSS_L_U6_, ARC700F_SFMT_ABSS_L_U6_ },
+ { ARC_INSN_NEGSW_L_R_R__RC, ARC700F_INSN_NEGSW_L_R_R__RC, ARC700F_SFMT_ABSSW_L_R_R__RC },
+ { ARC_INSN_NEGSW_L_U6_, ARC700F_INSN_NEGSW_L_U6_, ARC700F_SFMT_ABSSW_L_U6_ },
+ { ARC_INSN_NEGS_L_R_R__RC, ARC700F_INSN_NEGS_L_R_R__RC, ARC700F_SFMT_RND16_L_R_R__RC },
+ { ARC_INSN_NEGS_L_U6_, ARC700F_INSN_NEGS_L_U6_, ARC700F_SFMT_RND16_L_U6_ },
+ { ARC_INSN_NORMW_L_R_R__RC, ARC700F_INSN_NORMW_L_R_R__RC, ARC700F_SFMT_SWAP_L_R_R__RC },
+ { ARC_INSN_NORMW_L_U6_, ARC700F_INSN_NORMW_L_U6_, ARC700F_SFMT_SWAP_L_U6_ },
+ { ARC_INSN_NOP_S, ARC700F_INSN_NOP_S, ARC700F_SFMT_NOP_S },
+ { ARC_INSN_UNIMP_S, ARC700F_INSN_UNIMP_S, ARC700F_SFMT_NOP_S },
+ { ARC_INSN_POP_S_B, ARC700F_INSN_POP_S_B, ARC700F_SFMT_POP_S_B },
+ { ARC_INSN_POP_S_BLINK, ARC700F_INSN_POP_S_BLINK, ARC700F_SFMT_POP_S_BLINK },
+ { ARC_INSN_PUSH_S_B, ARC700F_INSN_PUSH_S_B, ARC700F_SFMT_PUSH_S_B },
+ { ARC_INSN_PUSH_S_BLINK, ARC700F_INSN_PUSH_S_BLINK, ARC700F_SFMT_PUSH_S_BLINK },
+ { ARC_INSN_MULLW_L_S12__RA_, ARC700F_INSN_MULLW_L_S12__RA_, ARC700F_SFMT_MULLW_L_S12__RA_ },
+ { ARC_INSN_MULLW_CCU6__RA_, ARC700F_INSN_MULLW_CCU6__RA_, ARC700F_SFMT_MULLW_CCU6__RA_ },
+ { ARC_INSN_MULLW_L_U6__RA_, ARC700F_INSN_MULLW_L_U6__RA_, ARC700F_SFMT_MULLW_L_U6__RA_ },
+ { ARC_INSN_MULLW_L_R_R__RA__RC, ARC700F_INSN_MULLW_L_R_R__RA__RC, ARC700F_SFMT_MULLW_L_R_R__RA__RC },
+ { ARC_INSN_MULLW_CC__RA__RC, ARC700F_INSN_MULLW_CC__RA__RC, ARC700F_SFMT_MULLW_CC__RA__RC },
+ { ARC_INSN_MACLW_L_S12__RA_, ARC700F_INSN_MACLW_L_S12__RA_, ARC700F_SFMT_MACLW_L_S12__RA_ },
+ { ARC_INSN_MACLW_CCU6__RA_, ARC700F_INSN_MACLW_CCU6__RA_, ARC700F_SFMT_MACLW_CCU6__RA_ },
+ { ARC_INSN_MACLW_L_U6__RA_, ARC700F_INSN_MACLW_L_U6__RA_, ARC700F_SFMT_MACLW_L_U6__RA_ },
+ { ARC_INSN_MACLW_L_R_R__RA__RC, ARC700F_INSN_MACLW_L_R_R__RA__RC, ARC700F_SFMT_MACLW_L_R_R__RA__RC },
+ { ARC_INSN_MACLW_CC__RA__RC, ARC700F_INSN_MACLW_CC__RA__RC, ARC700F_SFMT_MACLW_CC__RA__RC },
+ { ARC_INSN_MACHLW_L_S12__RA_, ARC700F_INSN_MACHLW_L_S12__RA_, ARC700F_SFMT_MACLW_L_S12__RA_ },
+ { ARC_INSN_MACHLW_CCU6__RA_, ARC700F_INSN_MACHLW_CCU6__RA_, ARC700F_SFMT_MACLW_CCU6__RA_ },
+ { ARC_INSN_MACHLW_L_U6__RA_, ARC700F_INSN_MACHLW_L_U6__RA_, ARC700F_SFMT_MACLW_L_U6__RA_ },
+ { ARC_INSN_MACHLW_L_R_R__RA__RC, ARC700F_INSN_MACHLW_L_R_R__RA__RC, ARC700F_SFMT_MACLW_L_R_R__RA__RC },
+ { ARC_INSN_MACHLW_CC__RA__RC, ARC700F_INSN_MACHLW_CC__RA__RC, ARC700F_SFMT_MACLW_CC__RA__RC },
+ { ARC_INSN_MULULW_L_S12__RA_, ARC700F_INSN_MULULW_L_S12__RA_, ARC700F_SFMT_MULLW_L_S12__RA_ },
+ { ARC_INSN_MULULW_CCU6__RA_, ARC700F_INSN_MULULW_CCU6__RA_, ARC700F_SFMT_MULLW_CCU6__RA_ },
+ { ARC_INSN_MULULW_L_U6__RA_, ARC700F_INSN_MULULW_L_U6__RA_, ARC700F_SFMT_MULLW_L_U6__RA_ },
+ { ARC_INSN_MULULW_L_R_R__RA__RC, ARC700F_INSN_MULULW_L_R_R__RA__RC, ARC700F_SFMT_MULLW_L_R_R__RA__RC },
+ { ARC_INSN_MULULW_CC__RA__RC, ARC700F_INSN_MULULW_CC__RA__RC, ARC700F_SFMT_MULLW_CC__RA__RC },
+ { ARC_INSN_MACHULW_L_S12__RA_, ARC700F_INSN_MACHULW_L_S12__RA_, ARC700F_SFMT_MACHULW_L_S12__RA_ },
+ { ARC_INSN_MACHULW_CCU6__RA_, ARC700F_INSN_MACHULW_CCU6__RA_, ARC700F_SFMT_MACHULW_CCU6__RA_ },
+ { ARC_INSN_MACHULW_L_U6__RA_, ARC700F_INSN_MACHULW_L_U6__RA_, ARC700F_SFMT_MACHULW_L_U6__RA_ },
+ { ARC_INSN_MACHULW_L_R_R__RA__RC, ARC700F_INSN_MACHULW_L_R_R__RA__RC, ARC700F_SFMT_MACHULW_L_R_R__RA__RC },
+ { ARC_INSN_MACHULW_CC__RA__RC, ARC700F_INSN_MACHULW_CC__RA__RC, ARC700F_SFMT_MACHULW_CC__RA__RC },
+ { ARC_INSN_CURRENT_LOOP_END, ARC700F_INSN_CURRENT_LOOP_END, ARC700F_SFMT_CURRENT_LOOP_END },
+ { ARC_INSN_CURRENT_LOOP_END_AFTER_BRANCH, ARC700F_INSN_CURRENT_LOOP_END_AFTER_BRANCH, ARC700F_SFMT_CURRENT_LOOP_END_AFTER_BRANCH },
+ { ARC_INSN_ARC600_CURRENT_LOOP_END_AFTER_BRANCH, ARC700F_INSN_ARC600_CURRENT_LOOP_END_AFTER_BRANCH, ARC700F_SFMT_CURRENT_LOOP_END_AFTER_BRANCH },
+};
+
+static const struct insn_sem arc700f_insn_sem_invalid = {
+ VIRTUAL_INSN_X_INVALID, ARC700F_INSN_X_INVALID, ARC700F_SFMT_EMPTY
+};
+
+/* Initialize an IDESC from the compile-time computable parts. */
+
+static INLINE void
+init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
+{
+ const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries;
+
+ id->num = t->index;
+ id->sfmt = t->sfmt;
+ if ((int) t->type <= 0)
+ id->idata = & cgen_virtual_insn_table[- (int) t->type];
+ else
+ id->idata = & insn_table[t->type];
+ id->attrs = CGEN_INSN_ATTRS (id->idata);
+ /* Oh my god, a magic number. */
+ id->length = CGEN_INSN_BITSIZE (id->idata) / 8;
+
+#if WITH_PROFILE_MODEL_P
+ id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index];
+ {
+ SIM_DESC sd = CPU_STATE (cpu);
+ SIM_ASSERT (t->index == id->timing->num);
+ }
+#endif
+
+ /* Semantic pointers are initialized elsewhere. */
+}
+
+/* Initialize the instruction descriptor table. */
+
+void
+arc700f_init_idesc_table (SIM_CPU *cpu)
+{
+ IDESC *id,*tabend;
+ const struct insn_sem *t,*tend;
+ int tabsize = ARC700F_INSN__MAX;
+ IDESC *table = arc700f_insn_data;
+
+ memset (table, 0, tabsize * sizeof (IDESC));
+
+ /* First set all entries to the `invalid insn'. */
+ t = & arc700f_insn_sem_invalid;
+ for (id = table, tabend = table + tabsize; id < tabend; ++id)
+ init_idesc (cpu, id, t);
+
+ /* Now fill in the values for the chosen cpu. */
+ for (t = arc700f_insn_sem, tend = t + sizeof (arc700f_insn_sem) / sizeof (*t);
+ t != tend; ++t)
+ {
+ init_idesc (cpu, & table[t->index], t);
+ }
+
+ /* Link the IDESC table into the cpu. */
+ CPU_IDESC (cpu) = table;
+}
+
+/* Given an instruction, return a pointer to its IDESC entry. */
+
+const IDESC *
+arc700f_decode (SIM_CPU *current_cpu, IADDR pc,
+ CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn,
+ ARGBUF *abuf)
+{
+ /* Result of decoder. */
+ ARC700F_INSN_TYPE itype;
+
+ {
+ CGEN_INSN_INT insn = base_insn;
+
+ {
+ unsigned int val = (((insn >> 20) & (1 << 10)) | ((insn >> 19) & (3 << 8)) | ((insn >> 16) & (255 << 0)));
+ switch (val)
+ {
+ case 0 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20000000)
+ { itype = ARC700F_INSN_ADD_L_R_R__RA__RC; goto extract_sfmt_add_L_r_r__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20010000)
+ { itype = ARC700F_INSN_ADC_L_R_R__RA__RC; goto extract_sfmt_adc_L_r_r__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 2 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20020000)
+ { itype = ARC700F_INSN_SUB_L_R_R__RA__RC; goto extract_sfmt_add_L_r_r__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 3 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20030000)
+ { itype = ARC700F_INSN_SBC_L_R_R__RA__RC; goto extract_sfmt_adc_L_r_r__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 4 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20040000)
+ { itype = ARC700F_INSN_AND_L_R_R__RA__RC; goto extract_sfmt_and_L_r_r__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 5 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20050000)
+ { itype = ARC700F_INSN_OR_L_R_R__RA__RC; goto extract_sfmt_and_L_r_r__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 6 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20060000)
+ { itype = ARC700F_INSN_BIC_L_R_R__RA__RC; goto extract_sfmt_and_L_r_r__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 7 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20070000)
+ { itype = ARC700F_INSN_XOR_L_R_R__RA__RC; goto extract_sfmt_and_L_r_r__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 8 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20080000)
+ { itype = ARC700F_INSN_MAX_L_R_R__RA__RC; goto extract_sfmt_add_L_r_r__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 9 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20090000)
+ { itype = ARC700F_INSN_MIN_L_R_R__RA__RC; goto extract_sfmt_add_L_r_r__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 10 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x200a0000)
+ { itype = ARC700F_INSN_MOV_L_R_R__RC; goto extract_sfmt_mov_L_r_r__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 11 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x200b0000)
+ { itype = ARC700F_INSN_TST_L_R_R__RC; goto extract_sfmt_tst_L_r_r__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 12 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x200c0000)
+ { itype = ARC700F_INSN_CMP_L_R_R__RC; goto extract_sfmt_cmp_L_r_r__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 13 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x200d0000)
+ { itype = ARC700F_INSN_RCMP_L_R_R__RC; goto extract_sfmt_cmp_L_r_r__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 14 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x200e0000)
+ { itype = ARC700F_INSN_RSUB_L_R_R__RA__RC; goto extract_sfmt_add_L_r_r__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 15 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x200f0000)
+ { itype = ARC700F_INSN_BSET_L_R_R__RA__RC; goto extract_sfmt_and_L_r_r__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 16 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20100000)
+ { itype = ARC700F_INSN_BCLR_L_R_R__RA__RC; goto extract_sfmt_and_L_r_r__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 17 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20110000)
+ { itype = ARC700F_INSN_BTST_L_R_R__RC; goto extract_sfmt_tst_L_r_r__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 18 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20120000)
+ { itype = ARC700F_INSN_BXOR_L_R_R__RA__RC; goto extract_sfmt_and_L_r_r__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 19 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20130000)
+ { itype = ARC700F_INSN_BMSK_L_R_R__RA__RC; goto extract_sfmt_and_L_r_r__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 20 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20140000)
+ { itype = ARC700F_INSN_ADD1_L_R_R__RA__RC; goto extract_sfmt_add_L_r_r__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 21 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20150000)
+ { itype = ARC700F_INSN_ADD2_L_R_R__RA__RC; goto extract_sfmt_add_L_r_r__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 22 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20160000)
+ { itype = ARC700F_INSN_ADD3_L_R_R__RA__RC; goto extract_sfmt_add_L_r_r__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 23 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20170000)
+ { itype = ARC700F_INSN_SUB1_L_R_R__RA__RC; goto extract_sfmt_add_L_r_r__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 24 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20180000)
+ { itype = ARC700F_INSN_SUB2_L_R_R__RA__RC; goto extract_sfmt_add_L_r_r__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 25 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20190000)
+ { itype = ARC700F_INSN_SUB3_L_R_R__RA__RC; goto extract_sfmt_add_L_r_r__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 26 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x201a0000)
+ { itype = ARC700F_INSN_MPY_L_R_R__RA__RC; goto extract_sfmt_mpy_L_r_r__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 27 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x201b0000)
+ { itype = ARC700F_INSN_MPYH_L_R_R__RA__RC; goto extract_sfmt_mpy_L_r_r__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 28 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x201c0000)
+ { itype = ARC700F_INSN_MPYHU_L_R_R__RA__RC; goto extract_sfmt_mpy_L_r_r__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 29 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x201d0000)
+ { itype = ARC700F_INSN_MPYU_L_R_R__RA__RC; goto extract_sfmt_mpy_L_r_r__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 30 : /* fall through */
+ case 36 : /* fall through */
+ case 38 : /* fall through */
+ case 40 : /* fall through */
+ case 44 : /* fall through */
+ case 46 : /* fall through */
+ case 54 : /* fall through */
+ case 56 : /* fall through */
+ case 58 : /* fall through */
+ case 60 : /* fall through */
+ case 62 : /* fall through */
+ case 94 : /* fall through */
+ case 100 : /* fall through */
+ case 102 : /* fall through */
+ case 104 : /* fall through */
+ case 108 : /* fall through */
+ case 110 : /* fall through */
+ case 118 : /* fall through */
+ case 120 : /* fall through */
+ case 122 : /* fall through */
+ case 124 : /* fall through */
+ case 126 : /* fall through */
+ case 158 : /* fall through */
+ case 164 : /* fall through */
+ case 166 : /* fall through */
+ case 172 : /* fall through */
+ case 174 : /* fall through */
+ case 182 : /* fall through */
+ case 184 : /* fall through */
+ case 186 : /* fall through */
+ case 188 : /* fall through */
+ case 190 : /* fall through */
+ case 222 : /* fall through */
+ case 228 : /* fall through */
+ case 230 : /* fall through */
+ case 234 : /* fall through */
+ case 236 : /* fall through */
+ case 238 : /* fall through */
+ case 246 : /* fall through */
+ case 248 : /* fall through */
+ case 250 : /* fall through */
+ case 252 : /* fall through */
+ case 254 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 31 : /* fall through */
+ case 37 : /* fall through */
+ case 39 : /* fall through */
+ case 45 : /* fall through */
+ case 49 : /* fall through */
+ case 55 : /* fall through */
+ case 57 : /* fall through */
+ case 59 : /* fall through */
+ case 61 : /* fall through */
+ case 63 : /* fall through */
+ case 95 : /* fall through */
+ case 101 : /* fall through */
+ case 103 : /* fall through */
+ case 109 : /* fall through */
+ case 113 : /* fall through */
+ case 119 : /* fall through */
+ case 121 : /* fall through */
+ case 123 : /* fall through */
+ case 125 : /* fall through */
+ case 127 : /* fall through */
+ case 159 : /* fall through */
+ case 165 : /* fall through */
+ case 167 : /* fall through */
+ case 173 : /* fall through */
+ case 175 : /* fall through */
+ case 177 : /* fall through */
+ case 183 : /* fall through */
+ case 185 : /* fall through */
+ case 187 : /* fall through */
+ case 189 : /* fall through */
+ case 191 : /* fall through */
+ case 223 : /* fall through */
+ case 229 : /* fall through */
+ case 231 : /* fall through */
+ case 235 : /* fall through */
+ case 237 : /* fall through */
+ case 239 : /* fall through */
+ case 241 : /* fall through */
+ case 247 : /* fall through */
+ case 249 : /* fall through */
+ case 251 : /* fall through */
+ case 253 : /* fall through */
+ case 255 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 32 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20200000)
+ { itype = ARC700F_INSN_J_L_R_R___RC_ILINK_; goto extract_sfmt_j_L_r_r___RC_ilink_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 33 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20210000)
+ { itype = ARC700F_INSN_J_L_R_R_D___RC_; goto extract_sfmt_j_L_r_r_d___RC_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 34 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20220000)
+ { itype = ARC700F_INSN_JL_L_R_R___RC_NOILINK_; goto extract_sfmt_jl_L_r_r___RC_noilink_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 35 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20230000)
+ { itype = ARC700F_INSN_JL_L_R_R_D___RC_; goto extract_sfmt_jl_L_r_r_d___RC_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 41 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20290000)
+ { itype = ARC700F_INSN_FLAG_L_R_R__RC; goto extract_sfmt_flag_L_r_r__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 42 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x202a0000)
+ { itype = ARC700F_INSN_LR_L_R_R___RC_; goto extract_sfmt_lr_L_r_r___RC_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 43 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x202b0000)
+ { itype = ARC700F_INSN_SR_L_R_R___RC_; goto extract_sfmt_sr_L_r_r___RC_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 47 :
+ {
+ unsigned int val = (((insn >> 23) & (1 << 6)) | ((insn >> 0) & (63 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 16 : /* fall through */
+ case 17 : /* fall through */
+ case 18 : /* fall through */
+ case 19 : /* fall through */
+ case 20 : /* fall through */
+ case 21 : /* fall through */
+ case 22 : /* fall through */
+ case 23 : /* fall through */
+ case 24 : /* fall through */
+ case 25 : /* fall through */
+ case 26 : /* fall through */
+ case 27 : /* fall through */
+ case 28 : /* fall through */
+ case 29 : /* fall through */
+ case 30 : /* fall through */
+ case 31 : /* fall through */
+ case 48 : /* fall through */
+ case 49 : /* fall through */
+ case 50 : /* fall through */
+ case 51 : /* fall through */
+ case 52 : /* fall through */
+ case 53 : /* fall through */
+ case 54 : /* fall through */
+ case 55 : /* fall through */
+ case 56 : /* fall through */
+ case 57 : /* fall through */
+ case 58 : /* fall through */
+ case 59 : /* fall through */
+ case 60 : /* fall through */
+ case 61 : /* fall through */
+ case 62 : /* fall through */
+ case 63 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 32 : /* fall through */
+ case 33 : /* fall through */
+ case 34 : /* fall through */
+ case 35 : /* fall through */
+ case 36 : /* fall through */
+ case 37 : /* fall through */
+ case 38 : /* fall through */
+ case 39 : /* fall through */
+ case 40 : /* fall through */
+ case 41 : /* fall through */
+ case 42 : /* fall through */
+ case 43 : /* fall through */
+ case 44 : /* fall through */
+ case 45 : /* fall through */
+ case 46 : /* fall through */
+ case 47 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 64 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x202f0000)
+ { itype = ARC700F_INSN_ASL_L_R_R__RC; goto extract_sfmt_asl_L_r_r__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 65 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x202f0001)
+ { itype = ARC700F_INSN_ASR_L_R_R__RC; goto extract_sfmt_asr_L_r_r__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 66 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x202f0002)
+ { itype = ARC700F_INSN_LSR_L_R_R__RC; goto extract_sfmt_asr_L_r_r__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 67 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x202f0003)
+ { itype = ARC700F_INSN_ROR_L_R_R__RC; goto extract_sfmt_asr_L_r_r__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 68 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x202f0004)
+ { itype = ARC700F_INSN_RRC_L_R_R__RC; goto extract_sfmt_rrc_L_r_r__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 69 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x202f0005)
+ { itype = ARC700F_INSN_SEXB_L_R_R__RC; goto extract_sfmt_sexb_L_r_r__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 70 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x202f0006)
+ { itype = ARC700F_INSN_SEXW_L_R_R__RC; goto extract_sfmt_sexw_L_r_r__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 71 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x202f0007)
+ { itype = ARC700F_INSN_EXTB_L_R_R__RC; goto extract_sfmt_sexb_L_r_r__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 72 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x202f0008)
+ { itype = ARC700F_INSN_EXTW_L_R_R__RC; goto extract_sfmt_sexw_L_r_r__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 73 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x202f0009)
+ { itype = ARC700F_INSN_ABS_L_R_R__RC; goto extract_sfmt_abs_L_r_r__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 74 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x202f000a)
+ { itype = ARC700F_INSN_NOT_L_R_R__RC; goto extract_sfmt_not_L_r_r__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 75 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x202f000b)
+ { itype = ARC700F_INSN_RLC_L_R_R__RC; goto extract_sfmt_rrc_L_r_r__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 76 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x202f000c)
+ { itype = ARC700F_INSN_EX_L_R_R__RC; goto extract_sfmt_ex_L_r_r__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 77 : /* fall through */
+ case 78 : /* fall through */
+ case 79 : /* fall through */
+ case 80 : /* fall through */
+ case 81 : /* fall through */
+ case 82 : /* fall through */
+ case 83 : /* fall through */
+ case 84 : /* fall through */
+ case 85 : /* fall through */
+ case 86 : /* fall through */
+ case 87 : /* fall through */
+ case 88 : /* fall through */
+ case 89 : /* fall through */
+ case 90 : /* fall through */
+ case 91 : /* fall through */
+ case 92 : /* fall through */
+ case 93 : /* fall through */
+ case 94 : /* fall through */
+ case 95 : /* fall through */
+ case 96 : /* fall through */
+ case 97 : /* fall through */
+ case 98 : /* fall through */
+ case 99 : /* fall through */
+ case 100 : /* fall through */
+ case 101 : /* fall through */
+ case 102 : /* fall through */
+ case 103 : /* fall through */
+ case 104 : /* fall through */
+ case 105 : /* fall through */
+ case 106 : /* fall through */
+ case 107 : /* fall through */
+ case 108 : /* fall through */
+ case 109 : /* fall through */
+ case 110 : /* fall through */
+ case 111 : /* fall through */
+ case 112 : /* fall through */
+ case 113 : /* fall through */
+ case 114 : /* fall through */
+ case 115 : /* fall through */
+ case 116 : /* fall through */
+ case 117 : /* fall through */
+ case 118 : /* fall through */
+ case 119 : /* fall through */
+ case 120 : /* fall through */
+ case 121 : /* fall through */
+ case 122 : /* fall through */
+ case 123 : /* fall through */
+ case 124 : /* fall through */
+ case 125 : /* fall through */
+ case 127 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 126 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x202f003e)
+ { itype = ARC700F_INSN_CURRENT_LOOP_END; goto extract_sfmt_current_loop_end; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 48 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20300000)
+ { itype = ARC700F_INSN_LD_ABC; goto extract_sfmt_ld_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 50 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20320000)
+ { itype = ARC700F_INSN_LDB_ABC; goto extract_sfmt_ldb_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 51 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20330000)
+ { itype = ARC700F_INSN_LDB_X_ABC; goto extract_sfmt_ldb_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 52 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20340000)
+ { itype = ARC700F_INSN_LDW_ABC; goto extract_sfmt_ldw_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 53 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20350000)
+ { itype = ARC700F_INSN_LDW_X_ABC; goto extract_sfmt_ldw_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 64 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20400000)
+ { itype = ARC700F_INSN_ADD_L_U6__RA_; goto extract_sfmt_add_L_u6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 65 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20410000)
+ { itype = ARC700F_INSN_ADC_L_U6__RA_; goto extract_sfmt_adc_L_u6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 66 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20420000)
+ { itype = ARC700F_INSN_SUB_L_U6__RA_; goto extract_sfmt_add_L_u6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 67 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20430000)
+ { itype = ARC700F_INSN_SBC_L_U6__RA_; goto extract_sfmt_adc_L_u6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 68 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20440000)
+ { itype = ARC700F_INSN_AND_L_U6__RA_; goto extract_sfmt_and_L_u6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 69 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20450000)
+ { itype = ARC700F_INSN_OR_L_U6__RA_; goto extract_sfmt_and_L_u6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 70 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20460000)
+ { itype = ARC700F_INSN_BIC_L_U6__RA_; goto extract_sfmt_and_L_u6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 71 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20470000)
+ { itype = ARC700F_INSN_XOR_L_U6__RA_; goto extract_sfmt_and_L_u6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 72 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20480000)
+ { itype = ARC700F_INSN_MAX_L_U6__RA_; goto extract_sfmt_add_L_u6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 73 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20490000)
+ { itype = ARC700F_INSN_MIN_L_U6__RA_; goto extract_sfmt_add_L_u6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 74 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x204a0000)
+ { itype = ARC700F_INSN_MOV_L_U6_; goto extract_sfmt_mov_L_u6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 75 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x204b0000)
+ { itype = ARC700F_INSN_TST_L_U6_; goto extract_sfmt_tst_L_u6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 76 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x204c0000)
+ { itype = ARC700F_INSN_CMP_L_U6_; goto extract_sfmt_cmp_L_u6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 77 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x204d0000)
+ { itype = ARC700F_INSN_RCMP_L_U6_; goto extract_sfmt_cmp_L_u6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 78 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x204e0000)
+ { itype = ARC700F_INSN_RSUB_L_U6__RA_; goto extract_sfmt_add_L_u6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 79 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x204f0000)
+ { itype = ARC700F_INSN_BSET_L_U6__RA_; goto extract_sfmt_and_L_u6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 80 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20500000)
+ { itype = ARC700F_INSN_BCLR_L_U6__RA_; goto extract_sfmt_and_L_u6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 81 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20510000)
+ { itype = ARC700F_INSN_BTST_L_U6_; goto extract_sfmt_tst_L_u6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 82 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20520000)
+ { itype = ARC700F_INSN_BXOR_L_U6__RA_; goto extract_sfmt_and_L_u6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 83 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20530000)
+ { itype = ARC700F_INSN_BMSK_L_U6__RA_; goto extract_sfmt_and_L_u6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 84 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20540000)
+ { itype = ARC700F_INSN_ADD1_L_U6__RA_; goto extract_sfmt_add_L_u6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 85 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20550000)
+ { itype = ARC700F_INSN_ADD2_L_U6__RA_; goto extract_sfmt_add_L_u6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 86 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20560000)
+ { itype = ARC700F_INSN_ADD3_L_U6__RA_; goto extract_sfmt_add_L_u6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 87 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20570000)
+ { itype = ARC700F_INSN_SUB1_L_U6__RA_; goto extract_sfmt_add_L_u6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 88 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20580000)
+ { itype = ARC700F_INSN_SUB2_L_U6__RA_; goto extract_sfmt_add_L_u6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 89 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20590000)
+ { itype = ARC700F_INSN_SUB3_L_U6__RA_; goto extract_sfmt_add_L_u6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 90 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x205a0000)
+ { itype = ARC700F_INSN_MPY_L_U6__RA_; goto extract_sfmt_mpy_L_u6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 91 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x205b0000)
+ { itype = ARC700F_INSN_MPYH_L_U6__RA_; goto extract_sfmt_mpy_L_u6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 92 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x205c0000)
+ { itype = ARC700F_INSN_MPYHU_L_U6__RA_; goto extract_sfmt_mpy_L_u6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 93 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x205d0000)
+ { itype = ARC700F_INSN_MPYU_L_U6__RA_; goto extract_sfmt_mpy_L_u6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 96 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20600000)
+ { itype = ARC700F_INSN_J_L_U6_; goto extract_sfmt_j_L_u6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 97 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20610000)
+ { itype = ARC700F_INSN_J_L_U6_D_; goto extract_sfmt_j_L_u6_d_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 98 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20620000)
+ { itype = ARC700F_INSN_JL_L_U6_; goto extract_sfmt_jl_L_u6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 99 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20630000)
+ { itype = ARC700F_INSN_JL_L_U6_D_; goto extract_sfmt_jl_L_u6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 105 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20690000)
+ { itype = ARC700F_INSN_FLAG_L_U6_; goto extract_sfmt_flag_L_u6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 106 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x206a0000)
+ { itype = ARC700F_INSN_LR_L_U6_; goto extract_sfmt_lr_L_u6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 107 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x206b0000)
+ { itype = ARC700F_INSN_SR_L_U6_; goto extract_sfmt_sr_L_u6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 111 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff003f) == 0x206f0000)
+ { itype = ARC700F_INSN_ASL_L_U6_; goto extract_sfmt_asl_L_u6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff003f) == 0x206f0001)
+ { itype = ARC700F_INSN_ASR_L_U6_; goto extract_sfmt_asr_L_u6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 2 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff003f) == 0x206f0002)
+ { itype = ARC700F_INSN_LSR_L_U6_; goto extract_sfmt_asr_L_u6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 3 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff003f) == 0x206f0003)
+ { itype = ARC700F_INSN_ROR_L_U6_; goto extract_sfmt_asr_L_u6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 4 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff003f) == 0x206f0004)
+ { itype = ARC700F_INSN_RRC_L_U6_; goto extract_sfmt_rrc_L_u6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 5 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff003f) == 0x206f0005)
+ { itype = ARC700F_INSN_SEXB_L_U6_; goto extract_sfmt_sexb_L_u6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 6 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff003f) == 0x206f0006)
+ { itype = ARC700F_INSN_SEXW_L_U6_; goto extract_sfmt_sexw_L_u6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 7 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff003f) == 0x206f0007)
+ { itype = ARC700F_INSN_EXTB_L_U6_; goto extract_sfmt_sexb_L_u6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 8 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff003f) == 0x206f0008)
+ { itype = ARC700F_INSN_EXTW_L_U6_; goto extract_sfmt_sexw_L_u6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 9 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff003f) == 0x206f0009)
+ { itype = ARC700F_INSN_ABS_L_U6_; goto extract_sfmt_abs_L_u6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 10 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff003f) == 0x206f000a)
+ { itype = ARC700F_INSN_NOT_L_U6_; goto extract_sfmt_not_L_u6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 11 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff003f) == 0x206f000b)
+ { itype = ARC700F_INSN_RLC_L_U6_; goto extract_sfmt_rrc_L_u6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 12 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff003f) == 0x206f000c)
+ { itype = ARC700F_INSN_EX_L_U6_; goto extract_sfmt_ex_L_u6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 13 : /* fall through */
+ case 14 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 15 :
+ {
+ unsigned int val = (((insn >> 25) & (1 << 6)) | ((insn >> 24) & (1 << 5)) | ((insn >> 22) & (7 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 4 : /* fall through */
+ case 8 : /* fall through */
+ case 12 : /* fall through */
+ case 16 : /* fall through */
+ case 20 : /* fall through */
+ case 24 : /* fall through */
+ case 28 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 6 : /* fall through */
+ case 10 : /* fall through */
+ case 14 : /* fall through */
+ case 18 : /* fall through */
+ case 22 : /* fall through */
+ case 26 : /* fall through */
+ case 30 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 43 :
+ if ((entire_insn & 0xffff7fff) == 0x226f003f)
+ { itype = ARC700F_INSN_SWI; goto extract_sfmt_swi; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 55 :
+ if ((entire_insn & 0xffff7fff) == 0x256f003f)
+ { itype = ARC700F_INSN_BRK; goto extract_sfmt_brk; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 64 : /* fall through */
+ case 65 : /* fall through */
+ case 66 : /* fall through */
+ case 67 : /* fall through */
+ case 68 : /* fall through */
+ case 69 : /* fall through */
+ case 70 : /* fall through */
+ case 71 : /* fall through */
+ case 72 : /* fall through */
+ case 73 : /* fall through */
+ case 74 : /* fall through */
+ case 75 : /* fall through */
+ case 76 : /* fall through */
+ case 77 : /* fall through */
+ case 78 : /* fall through */
+ case 79 : /* fall through */
+ case 80 : /* fall through */
+ case 81 : /* fall through */
+ case 82 : /* fall through */
+ case 83 : /* fall through */
+ case 84 : /* fall through */
+ case 85 : /* fall through */
+ case 86 : /* fall through */
+ case 87 : /* fall through */
+ case 88 : /* fall through */
+ case 89 : /* fall through */
+ case 90 : /* fall through */
+ case 91 : /* fall through */
+ case 92 : /* fall through */
+ case 93 : /* fall through */
+ case 94 : /* fall through */
+ case 95 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 96 : /* fall through */
+ case 97 : /* fall through */
+ case 98 : /* fall through */
+ case 99 : /* fall through */
+ case 100 : /* fall through */
+ case 101 : /* fall through */
+ case 102 : /* fall through */
+ case 103 : /* fall through */
+ case 104 : /* fall through */
+ case 105 : /* fall through */
+ case 106 : /* fall through */
+ case 107 : /* fall through */
+ case 108 : /* fall through */
+ case 109 : /* fall through */
+ case 110 : /* fall through */
+ case 111 : /* fall through */
+ case 112 : /* fall through */
+ case 113 : /* fall through */
+ case 114 : /* fall through */
+ case 115 : /* fall through */
+ case 116 : /* fall through */
+ case 117 : /* fall through */
+ case 118 : /* fall through */
+ case 119 : /* fall through */
+ case 120 : /* fall through */
+ case 121 : /* fall through */
+ case 122 : /* fall through */
+ case 123 : /* fall through */
+ case 124 : /* fall through */
+ case 125 : /* fall through */
+ case 126 : /* fall through */
+ case 127 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 112 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20700000)
+ { itype = ARC700F_INSN_LD__AW_ABC; goto extract_sfmt_ld__AW_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 114 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20720000)
+ { itype = ARC700F_INSN_LDB__AW_ABC; goto extract_sfmt_ldb__AW_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 115 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20730000)
+ { itype = ARC700F_INSN_LDB__AW_X_ABC; goto extract_sfmt_ldb__AW_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 116 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20740000)
+ { itype = ARC700F_INSN_LDW__AW_ABC; goto extract_sfmt_ldw__AW_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 117 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20750000)
+ { itype = ARC700F_INSN_LDW__AW_X_ABC; goto extract_sfmt_ldw__AW_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 128 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20800000)
+ { itype = ARC700F_INSN_ADD_L_S12__RA_; goto extract_sfmt_add_L_s12__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 129 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20810000)
+ { itype = ARC700F_INSN_ADC_L_S12__RA_; goto extract_sfmt_adc_L_s12__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 130 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20820000)
+ { itype = ARC700F_INSN_SUB_L_S12__RA_; goto extract_sfmt_add_L_s12__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 131 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20830000)
+ { itype = ARC700F_INSN_SBC_L_S12__RA_; goto extract_sfmt_adc_L_s12__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 132 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20840000)
+ { itype = ARC700F_INSN_AND_L_S12__RA_; goto extract_sfmt_and_L_s12__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 133 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20850000)
+ { itype = ARC700F_INSN_OR_L_S12__RA_; goto extract_sfmt_and_L_s12__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 134 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20860000)
+ { itype = ARC700F_INSN_BIC_L_S12__RA_; goto extract_sfmt_and_L_s12__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 135 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20870000)
+ { itype = ARC700F_INSN_XOR_L_S12__RA_; goto extract_sfmt_and_L_s12__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 136 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20880000)
+ { itype = ARC700F_INSN_MAX_L_S12__RA_; goto extract_sfmt_add_L_s12__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 137 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20890000)
+ { itype = ARC700F_INSN_MIN_L_S12__RA_; goto extract_sfmt_add_L_s12__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 138 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x208a0000)
+ { itype = ARC700F_INSN_MOV_L_S12_; goto extract_sfmt_mov_L_s12_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 139 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x208b0000)
+ { itype = ARC700F_INSN_TST_L_S12_; goto extract_sfmt_tst_L_s12_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 140 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x208c0000)
+ { itype = ARC700F_INSN_CMP_L_S12_; goto extract_sfmt_cmp_L_s12_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 141 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x208d0000)
+ { itype = ARC700F_INSN_RCMP_L_S12_; goto extract_sfmt_cmp_L_s12_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 142 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x208e0000)
+ { itype = ARC700F_INSN_RSUB_L_S12__RA_; goto extract_sfmt_add_L_s12__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 143 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x208f0000)
+ { itype = ARC700F_INSN_BSET_L_S12__RA_; goto extract_sfmt_and_L_s12__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 144 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20900000)
+ { itype = ARC700F_INSN_BCLR_L_S12__RA_; goto extract_sfmt_and_L_s12__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 145 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20910000)
+ { itype = ARC700F_INSN_BTST_L_S12_; goto extract_sfmt_tst_L_s12_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 146 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20920000)
+ { itype = ARC700F_INSN_BXOR_L_S12__RA_; goto extract_sfmt_and_L_s12__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 147 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20930000)
+ { itype = ARC700F_INSN_BMSK_L_S12__RA_; goto extract_sfmt_and_L_s12__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 148 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20940000)
+ { itype = ARC700F_INSN_ADD1_L_S12__RA_; goto extract_sfmt_add_L_s12__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 149 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20950000)
+ { itype = ARC700F_INSN_ADD2_L_S12__RA_; goto extract_sfmt_add_L_s12__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 150 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20960000)
+ { itype = ARC700F_INSN_ADD3_L_S12__RA_; goto extract_sfmt_add_L_s12__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 151 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20970000)
+ { itype = ARC700F_INSN_SUB1_L_S12__RA_; goto extract_sfmt_add_L_s12__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 152 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20980000)
+ { itype = ARC700F_INSN_SUB2_L_S12__RA_; goto extract_sfmt_add_L_s12__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 153 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20990000)
+ { itype = ARC700F_INSN_SUB3_L_S12__RA_; goto extract_sfmt_add_L_s12__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 154 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x209a0000)
+ { itype = ARC700F_INSN_MPY_L_S12__RA_; goto extract_sfmt_mpy_L_s12__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 155 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x209b0000)
+ { itype = ARC700F_INSN_MPYH_L_S12__RA_; goto extract_sfmt_mpy_L_s12__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 156 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x209c0000)
+ { itype = ARC700F_INSN_MPYHU_L_S12__RA_; goto extract_sfmt_mpy_L_s12__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 157 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x209d0000)
+ { itype = ARC700F_INSN_MPYU_L_S12__RA_; goto extract_sfmt_mpy_L_s12__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 160 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20a00000)
+ { itype = ARC700F_INSN_J_L_S12_; goto extract_sfmt_j_L_s12_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 161 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20a10000)
+ { itype = ARC700F_INSN_J_L_S12_D_; goto extract_sfmt_j_L_s12_d_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 162 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20a20000)
+ { itype = ARC700F_INSN_JL_L_S12_; goto extract_sfmt_jl_L_s12_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 163 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20a30000)
+ { itype = ARC700F_INSN_JL_L_S12_D_; goto extract_sfmt_jl_L_s12_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 168 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20a80000)
+ { itype = ARC700F_INSN_LP_L_S12_; goto extract_sfmt_lp_L_s12_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 169 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20a90000)
+ { itype = ARC700F_INSN_FLAG_L_S12_; goto extract_sfmt_flag_L_s12_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 170 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20aa0000)
+ { itype = ARC700F_INSN_LR_L_S12_; goto extract_sfmt_lr_L_s12_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 171 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20ab0000)
+ { itype = ARC700F_INSN_SR_L_S12_; goto extract_sfmt_sr_L_s12_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 176 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20b00000)
+ { itype = ARC700F_INSN_LD_AB_ABC; goto extract_sfmt_ld__AW_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 178 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20b20000)
+ { itype = ARC700F_INSN_LDB_AB_ABC; goto extract_sfmt_ldb__AW_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 179 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20b30000)
+ { itype = ARC700F_INSN_LDB_AB_X_ABC; goto extract_sfmt_ldb__AW_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 180 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20b40000)
+ { itype = ARC700F_INSN_LDW_AB_ABC; goto extract_sfmt_ldw__AW_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 181 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20b50000)
+ { itype = ARC700F_INSN_LDW_AB_X_ABC; goto extract_sfmt_ldw__AW_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 192 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c00000)
+ { itype = ARC700F_INSN_ADD_CC__RA__RC; goto extract_sfmt_add_cc__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c00020)
+ { itype = ARC700F_INSN_ADD_CCU6__RA_; goto extract_sfmt_add_ccu6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 193 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c10000)
+ { itype = ARC700F_INSN_ADC_CC__RA__RC; goto extract_sfmt_adc_cc__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c10020)
+ { itype = ARC700F_INSN_ADC_CCU6__RA_; goto extract_sfmt_adc_ccu6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 194 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c20000)
+ { itype = ARC700F_INSN_SUB_CC__RA__RC; goto extract_sfmt_add_cc__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c20020)
+ { itype = ARC700F_INSN_SUB_CCU6__RA_; goto extract_sfmt_add_ccu6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 195 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c30000)
+ { itype = ARC700F_INSN_SBC_CC__RA__RC; goto extract_sfmt_adc_cc__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c30020)
+ { itype = ARC700F_INSN_SBC_CCU6__RA_; goto extract_sfmt_adc_ccu6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 196 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c40000)
+ { itype = ARC700F_INSN_AND_CC__RA__RC; goto extract_sfmt_and_cc__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c40020)
+ { itype = ARC700F_INSN_AND_CCU6__RA_; goto extract_sfmt_and_ccu6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 197 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c50000)
+ { itype = ARC700F_INSN_OR_CC__RA__RC; goto extract_sfmt_and_cc__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c50020)
+ { itype = ARC700F_INSN_OR_CCU6__RA_; goto extract_sfmt_and_ccu6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 198 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c60000)
+ { itype = ARC700F_INSN_BIC_CC__RA__RC; goto extract_sfmt_and_cc__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c60020)
+ { itype = ARC700F_INSN_BIC_CCU6__RA_; goto extract_sfmt_and_ccu6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 199 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c70000)
+ { itype = ARC700F_INSN_XOR_CC__RA__RC; goto extract_sfmt_and_cc__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c70020)
+ { itype = ARC700F_INSN_XOR_CCU6__RA_; goto extract_sfmt_and_ccu6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 200 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c80000)
+ { itype = ARC700F_INSN_MAX_CC__RA__RC; goto extract_sfmt_add_cc__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c80020)
+ { itype = ARC700F_INSN_MAX_CCU6__RA_; goto extract_sfmt_add_ccu6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 201 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c90000)
+ { itype = ARC700F_INSN_MIN_CC__RA__RC; goto extract_sfmt_add_cc__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20c90020)
+ { itype = ARC700F_INSN_MIN_CCU6__RA_; goto extract_sfmt_add_ccu6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 202 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20ca0000)
+ { itype = ARC700F_INSN_MOV_CC__RC; goto extract_sfmt_mov_cc__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20ca0020)
+ { itype = ARC700F_INSN_MOV_CCU6_; goto extract_sfmt_mov_ccu6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 203 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20cb0000)
+ { itype = ARC700F_INSN_TST_CC__RC; goto extract_sfmt_tst_cc__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20cb0020)
+ { itype = ARC700F_INSN_TST_CCU6_; goto extract_sfmt_tst_ccu6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 204 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20cc0000)
+ { itype = ARC700F_INSN_CMP_CC__RC; goto extract_sfmt_cmp_cc__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20cc0020)
+ { itype = ARC700F_INSN_CMP_CCU6_; goto extract_sfmt_cmp_ccu6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 205 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20cd0000)
+ { itype = ARC700F_INSN_RCMP_CC__RC; goto extract_sfmt_cmp_cc__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20cd0020)
+ { itype = ARC700F_INSN_RCMP_CCU6_; goto extract_sfmt_cmp_ccu6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 206 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20ce0000)
+ { itype = ARC700F_INSN_RSUB_CC__RA__RC; goto extract_sfmt_add_cc__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20ce0020)
+ { itype = ARC700F_INSN_RSUB_CCU6__RA_; goto extract_sfmt_add_ccu6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 207 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20cf0000)
+ { itype = ARC700F_INSN_BSET_CC__RA__RC; goto extract_sfmt_and_cc__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20cf0020)
+ { itype = ARC700F_INSN_BSET_CCU6__RA_; goto extract_sfmt_and_ccu6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 208 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d00000)
+ { itype = ARC700F_INSN_BCLR_CC__RA__RC; goto extract_sfmt_and_cc__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d00020)
+ { itype = ARC700F_INSN_BCLR_CCU6__RA_; goto extract_sfmt_and_ccu6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 209 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d10000)
+ { itype = ARC700F_INSN_BTST_CC__RC; goto extract_sfmt_tst_cc__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d10020)
+ { itype = ARC700F_INSN_BTST_CCU6_; goto extract_sfmt_tst_ccu6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 210 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d20000)
+ { itype = ARC700F_INSN_BXOR_CC__RA__RC; goto extract_sfmt_and_cc__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d20020)
+ { itype = ARC700F_INSN_BXOR_CCU6__RA_; goto extract_sfmt_and_ccu6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 211 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d30000)
+ { itype = ARC700F_INSN_BMSK_CC__RA__RC; goto extract_sfmt_and_cc__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d30020)
+ { itype = ARC700F_INSN_BMSK_CCU6__RA_; goto extract_sfmt_and_ccu6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 212 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d40000)
+ { itype = ARC700F_INSN_ADD1_CC__RA__RC; goto extract_sfmt_add_cc__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d40020)
+ { itype = ARC700F_INSN_ADD1_CCU6__RA_; goto extract_sfmt_add_ccu6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 213 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d50000)
+ { itype = ARC700F_INSN_ADD2_CC__RA__RC; goto extract_sfmt_add_cc__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d50020)
+ { itype = ARC700F_INSN_ADD2_CCU6__RA_; goto extract_sfmt_add_ccu6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 214 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d60000)
+ { itype = ARC700F_INSN_ADD3_CC__RA__RC; goto extract_sfmt_add_cc__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d60020)
+ { itype = ARC700F_INSN_ADD3_CCU6__RA_; goto extract_sfmt_add_ccu6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 215 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d70000)
+ { itype = ARC700F_INSN_SUB1_CC__RA__RC; goto extract_sfmt_add_cc__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d70020)
+ { itype = ARC700F_INSN_SUB1_CCU6__RA_; goto extract_sfmt_add_ccu6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 216 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d80000)
+ { itype = ARC700F_INSN_SUB2_CC__RA__RC; goto extract_sfmt_add_cc__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d80020)
+ { itype = ARC700F_INSN_SUB2_CCU6__RA_; goto extract_sfmt_add_ccu6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 217 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d90000)
+ { itype = ARC700F_INSN_SUB3_CC__RA__RC; goto extract_sfmt_add_cc__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20d90020)
+ { itype = ARC700F_INSN_SUB3_CCU6__RA_; goto extract_sfmt_add_ccu6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 218 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20da0000)
+ { itype = ARC700F_INSN_MPY_CC__RA__RC; goto extract_sfmt_mpy_cc__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20da0020)
+ { itype = ARC700F_INSN_MPY_CCU6__RA_; goto extract_sfmt_mpy_ccu6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 219 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20db0000)
+ { itype = ARC700F_INSN_MPYH_CC__RA__RC; goto extract_sfmt_mpy_cc__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20db0020)
+ { itype = ARC700F_INSN_MPYH_CCU6__RA_; goto extract_sfmt_mpy_ccu6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 220 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20dc0000)
+ { itype = ARC700F_INSN_MPYHU_CC__RA__RC; goto extract_sfmt_mpy_cc__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20dc0020)
+ { itype = ARC700F_INSN_MPYHU_CCU6__RA_; goto extract_sfmt_mpy_ccu6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 221 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20dd0000)
+ { itype = ARC700F_INSN_MPYU_CC__RA__RC; goto extract_sfmt_mpy_cc__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20dd0020)
+ { itype = ARC700F_INSN_MPYU_CCU6__RA_; goto extract_sfmt_mpy_ccu6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 224 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20e00000)
+ { itype = ARC700F_INSN_J_CC___RC_ILINK_; goto extract_sfmt_j_cc___RC_ilink_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20e00020)
+ { itype = ARC700F_INSN_J_CCU6_; goto extract_sfmt_j_ccu6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 225 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20e10000)
+ { itype = ARC700F_INSN_J_CC_D___RC_; goto extract_sfmt_j_cc_d___RC_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20e10020)
+ { itype = ARC700F_INSN_J_CCU6_D_; goto extract_sfmt_j_ccu6_d_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 226 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20e20000)
+ { itype = ARC700F_INSN_JL_CC___RC_NOILINK_; goto extract_sfmt_jl_cc___RC_noilink_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20e20020)
+ { itype = ARC700F_INSN_JL_CCU6_; goto extract_sfmt_jl_ccu6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 227 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20e30000)
+ { itype = ARC700F_INSN_JL_CC_D___RC_; goto extract_sfmt_jl_cc_d___RC_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20e30020)
+ { itype = ARC700F_INSN_JL_CCU6_D_; goto extract_sfmt_jl_ccu6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 232 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20e80020)
+ { itype = ARC700F_INSN_LPCC_CCU6; goto extract_sfmt_lpcc_ccu6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 233 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x20e90000)
+ { itype = ARC700F_INSN_FLAG_CC__RC; goto extract_sfmt_flag_cc__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x20e90020)
+ { itype = ARC700F_INSN_FLAG_CCU6_; goto extract_sfmt_flag_ccu6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 240 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20f00000)
+ { itype = ARC700F_INSN_LD_AS_ABC; goto extract_sfmt_ld_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 242 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20f20000)
+ { itype = ARC700F_INSN_LDB_AS_ABC; goto extract_sfmt_ldb_as_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 243 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20f30000)
+ { itype = ARC700F_INSN_LDB_AS_X_ABC; goto extract_sfmt_ldb_as_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 244 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010020) == 0x0)
+ { itype = ARC700F_INSN_BCC_L; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010020) == 0x20)
+ { itype = ARC700F_INSN_BCC_L_D; goto extract_sfmt_bcc_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20f40000)
+ { itype = ARC700F_INSN_LDW_AS_ABC; goto extract_sfmt_ldw_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 245 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x10000)
+ { itype = ARC700F_INSN_B_L; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x10020)
+ { itype = ARC700F_INSN_B_L_D; goto extract_sfmt_b_l; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x20f50000)
+ { itype = ARC700F_INSN_LDW_AS_X_ABC; goto extract_sfmt_ldw_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x80000000)
+ { itype = ARC700F_INSN_LD_S_ABU; goto extract_sfmt_ld_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa0000000)
+ { itype = ARC700F_INSN_ST_S_ABU; goto extract_sfmt_st_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 256 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = ARC700F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = ARC700F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28000000)
+ { itype = ARC700F_INSN_ASL_L_R_R__RA__RC; goto extract_sfmt_asl_L_r_r__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 257 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC700F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC700F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC700F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC700F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28010000)
+ { itype = ARC700F_INSN_LSR_L_R_R__RA__RC; goto extract_sfmt_asl_L_r_r__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 258 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = ARC700F_INSN_BL; goto extract_sfmt_bl; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = ARC700F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28020000)
+ { itype = ARC700F_INSN_ASR_L_R_R__RA__RC; goto extract_sfmt_asl_L_r_r__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 259 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC700F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC700F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC700F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC700F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28030000)
+ { itype = ARC700F_INSN_ROR_L_R_R__RA__RC; goto extract_sfmt_asl_L_r_r__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 260 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = ARC700F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = ARC700F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28040000)
+ { itype = ARC700F_INSN_MUL64_L_R_R__RC; goto extract_sfmt_mul64_L_r_r__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 261 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC700F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC700F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC700F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC700F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28050000)
+ { itype = ARC700F_INSN_MULU64_L_R_R__RC; goto extract_sfmt_mul64_L_r_r__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 262 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = ARC700F_INSN_BL; goto extract_sfmt_bl; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = ARC700F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28060000)
+ { itype = ARC700F_INSN_ADDS_L_R_R__RA__RC; goto extract_sfmt_adds_L_r_r__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 263 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC700F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC700F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC700F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC700F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28070000)
+ { itype = ARC700F_INSN_SUBS_L_R_R__RA__RC; goto extract_sfmt_adds_L_r_r__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 264 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = ARC700F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = ARC700F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28080000)
+ { itype = ARC700F_INSN_DIVAW_L_R_R__RA__RC; goto extract_sfmt_divaw_L_r_r__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 265 : /* fall through */
+ case 269 : /* fall through */
+ case 271 : /* fall through */
+ case 273 : /* fall through */
+ case 275 : /* fall through */
+ case 277 : /* fall through */
+ case 279 : /* fall through */
+ case 281 : /* fall through */
+ case 283 : /* fall through */
+ case 285 : /* fall through */
+ case 287 : /* fall through */
+ case 289 : /* fall through */
+ case 291 : /* fall through */
+ case 293 : /* fall through */
+ case 295 : /* fall through */
+ case 299 : /* fall through */
+ case 301 : /* fall through */
+ case 311 : /* fall through */
+ case 313 : /* fall through */
+ case 315 : /* fall through */
+ case 317 : /* fall through */
+ case 319 : /* fall through */
+ case 329 : /* fall through */
+ case 333 : /* fall through */
+ case 335 : /* fall through */
+ case 337 : /* fall through */
+ case 339 : /* fall through */
+ case 341 : /* fall through */
+ case 343 : /* fall through */
+ case 345 : /* fall through */
+ case 347 : /* fall through */
+ case 349 : /* fall through */
+ case 351 : /* fall through */
+ case 353 : /* fall through */
+ case 355 : /* fall through */
+ case 357 : /* fall through */
+ case 359 : /* fall through */
+ case 363 : /* fall through */
+ case 365 : /* fall through */
+ case 375 : /* fall through */
+ case 377 : /* fall through */
+ case 379 : /* fall through */
+ case 381 : /* fall through */
+ case 383 : /* fall through */
+ case 393 : /* fall through */
+ case 397 : /* fall through */
+ case 399 : /* fall through */
+ case 401 : /* fall through */
+ case 403 : /* fall through */
+ case 405 : /* fall through */
+ case 407 : /* fall through */
+ case 409 : /* fall through */
+ case 411 : /* fall through */
+ case 413 : /* fall through */
+ case 415 : /* fall through */
+ case 417 : /* fall through */
+ case 419 : /* fall through */
+ case 421 : /* fall through */
+ case 423 : /* fall through */
+ case 427 : /* fall through */
+ case 429 : /* fall through */
+ case 431 : /* fall through */
+ case 439 : /* fall through */
+ case 441 : /* fall through */
+ case 443 : /* fall through */
+ case 445 : /* fall through */
+ case 447 : /* fall through */
+ case 457 : /* fall through */
+ case 461 : /* fall through */
+ case 463 : /* fall through */
+ case 465 : /* fall through */
+ case 467 : /* fall through */
+ case 469 : /* fall through */
+ case 471 : /* fall through */
+ case 473 : /* fall through */
+ case 475 : /* fall through */
+ case 477 : /* fall through */
+ case 479 : /* fall through */
+ case 481 : /* fall through */
+ case 483 : /* fall through */
+ case 485 : /* fall through */
+ case 487 : /* fall through */
+ case 491 : /* fall through */
+ case 493 : /* fall through */
+ case 495 : /* fall through */
+ case 503 : /* fall through */
+ case 505 : /* fall through */
+ case 507 : /* fall through */
+ case 509 : /* fall through */
+ case 511 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC700F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC700F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC700F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC700F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 266 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = ARC700F_INSN_BL; goto extract_sfmt_bl; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = ARC700F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x280a0000)
+ { itype = ARC700F_INSN_ASLS_L_R_R__RA__RC; goto extract_sfmt_asls_L_r_r__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 267 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC700F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC700F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC700F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC700F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x280b0000)
+ { itype = ARC700F_INSN_ASRS_L_R_R__RA__RC; goto extract_sfmt_asls_L_r_r__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 268 : /* fall through */
+ case 272 : /* fall through */
+ case 276 : /* fall through */
+ case 280 : /* fall through */
+ case 284 : /* fall through */
+ case 288 : /* fall through */
+ case 292 : /* fall through */
+ case 300 : /* fall through */
+ case 308 : /* fall through */
+ case 312 : /* fall through */
+ case 316 : /* fall through */
+ case 332 : /* fall through */
+ case 336 : /* fall through */
+ case 340 : /* fall through */
+ case 344 : /* fall through */
+ case 348 : /* fall through */
+ case 352 : /* fall through */
+ case 356 : /* fall through */
+ case 364 : /* fall through */
+ case 372 : /* fall through */
+ case 376 : /* fall through */
+ case 380 : /* fall through */
+ case 396 : /* fall through */
+ case 400 : /* fall through */
+ case 404 : /* fall through */
+ case 408 : /* fall through */
+ case 412 : /* fall through */
+ case 416 : /* fall through */
+ case 420 : /* fall through */
+ case 428 : /* fall through */
+ case 436 : /* fall through */
+ case 440 : /* fall through */
+ case 444 : /* fall through */
+ case 460 : /* fall through */
+ case 464 : /* fall through */
+ case 468 : /* fall through */
+ case 472 : /* fall through */
+ case 476 : /* fall through */
+ case 480 : /* fall through */
+ case 484 : /* fall through */
+ case 492 : /* fall through */
+ case 500 : /* fall through */
+ case 504 : /* fall through */
+ case 508 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = ARC700F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = ARC700F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 270 : /* fall through */
+ case 274 : /* fall through */
+ case 278 : /* fall through */
+ case 282 : /* fall through */
+ case 286 : /* fall through */
+ case 290 : /* fall through */
+ case 294 : /* fall through */
+ case 298 : /* fall through */
+ case 302 : /* fall through */
+ case 306 : /* fall through */
+ case 314 : /* fall through */
+ case 318 : /* fall through */
+ case 334 : /* fall through */
+ case 338 : /* fall through */
+ case 342 : /* fall through */
+ case 346 : /* fall through */
+ case 350 : /* fall through */
+ case 354 : /* fall through */
+ case 358 : /* fall through */
+ case 362 : /* fall through */
+ case 366 : /* fall through */
+ case 370 : /* fall through */
+ case 378 : /* fall through */
+ case 382 : /* fall through */
+ case 398 : /* fall through */
+ case 402 : /* fall through */
+ case 406 : /* fall through */
+ case 410 : /* fall through */
+ case 414 : /* fall through */
+ case 418 : /* fall through */
+ case 422 : /* fall through */
+ case 426 : /* fall through */
+ case 430 : /* fall through */
+ case 434 : /* fall through */
+ case 442 : /* fall through */
+ case 446 : /* fall through */
+ case 462 : /* fall through */
+ case 466 : /* fall through */
+ case 470 : /* fall through */
+ case 474 : /* fall through */
+ case 478 : /* fall through */
+ case 482 : /* fall through */
+ case 486 : /* fall through */
+ case 490 : /* fall through */
+ case 494 : /* fall through */
+ case 498 : /* fall through */
+ case 506 : /* fall through */
+ case 510 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = ARC700F_INSN_BL; goto extract_sfmt_bl; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = ARC700F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 296 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = ARC700F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = ARC700F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28280000)
+ { itype = ARC700F_INSN_ADDSDW_L_R_R__RA__RC; goto extract_sfmt_asls_L_r_r__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 297 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC700F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC700F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC700F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC700F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28290000)
+ { itype = ARC700F_INSN_SUBSDW_L_R_R__RA__RC; goto extract_sfmt_asls_L_r_r__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 303 :
+ {
+ unsigned int val = (((insn >> 25) & (1 << 6)) | ((insn >> 24) & (1 << 5)) | ((insn >> 1) & (3 << 3)) | ((insn >> 0) & (7 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC700F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC700F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 16 : /* fall through */
+ case 17 : /* fall through */
+ case 18 : /* fall through */
+ case 19 : /* fall through */
+ case 20 : /* fall through */
+ case 21 : /* fall through */
+ case 22 : /* fall through */
+ case 23 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC700F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 24 : /* fall through */
+ case 25 : /* fall through */
+ case 26 : /* fall through */
+ case 27 : /* fall through */
+ case 28 : /* fall through */
+ case 29 : /* fall through */
+ case 30 : /* fall through */
+ case 31 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC700F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 32 :
+ {
+ unsigned int val = (((insn >> 3) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x282f0000)
+ { itype = ARC700F_INSN_SWAP_L_R_R__RC; goto extract_sfmt_swap_L_r_r__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8ff003f) == 0x282f0008)
+ { itype = ARC700F_INSN_NORMW_L_R_R__RC; goto extract_sfmt_swap_L_r_r__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 33 :
+ if ((entire_insn & 0xf8ff003f) == 0x282f0001)
+ { itype = ARC700F_INSN_NORM_L_R_R__RC; goto extract_sfmt_swap_L_r_r__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 35 :
+ if ((entire_insn & 0xf8ff003f) == 0x282f0003)
+ { itype = ARC700F_INSN_RND16_L_R_R__RC; goto extract_sfmt_rnd16_L_r_r__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 36 :
+ if ((entire_insn & 0xf8ff003f) == 0x282f0004)
+ { itype = ARC700F_INSN_ABSSW_L_R_R__RC; goto extract_sfmt_abssw_L_r_r__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 37 :
+ if ((entire_insn & 0xf8ff003f) == 0x282f0005)
+ { itype = ARC700F_INSN_ABSS_L_R_R__RC; goto extract_sfmt_rnd16_L_r_r__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 38 :
+ if ((entire_insn & 0xf8ff003f) == 0x282f0006)
+ { itype = ARC700F_INSN_NEGSW_L_R_R__RC; goto extract_sfmt_abssw_L_r_r__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 39 :
+ if ((entire_insn & 0xf8ff003f) == 0x282f0007)
+ { itype = ARC700F_INSN_NEGS_L_R_R__RC; goto extract_sfmt_rnd16_L_r_r__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 64 : /* fall through */
+ case 65 : /* fall through */
+ case 66 : /* fall through */
+ case 67 : /* fall through */
+ case 68 : /* fall through */
+ case 69 : /* fall through */
+ case 70 : /* fall through */
+ case 71 : /* fall through */
+ case 72 : /* fall through */
+ case 73 : /* fall through */
+ case 74 : /* fall through */
+ case 75 : /* fall through */
+ case 76 : /* fall through */
+ case 77 : /* fall through */
+ case 78 : /* fall through */
+ case 79 : /* fall through */
+ case 80 : /* fall through */
+ case 81 : /* fall through */
+ case 82 : /* fall through */
+ case 83 : /* fall through */
+ case 84 : /* fall through */
+ case 85 : /* fall through */
+ case 86 : /* fall through */
+ case 87 : /* fall through */
+ case 88 : /* fall through */
+ case 89 : /* fall through */
+ case 90 : /* fall through */
+ case 91 : /* fall through */
+ case 92 : /* fall through */
+ case 93 : /* fall through */
+ case 94 : /* fall through */
+ case 95 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 96 : /* fall through */
+ case 97 : /* fall through */
+ case 98 : /* fall through */
+ case 99 : /* fall through */
+ case 100 : /* fall through */
+ case 101 : /* fall through */
+ case 102 : /* fall through */
+ case 103 : /* fall through */
+ case 104 : /* fall through */
+ case 105 : /* fall through */
+ case 106 : /* fall through */
+ case 107 : /* fall through */
+ case 108 : /* fall through */
+ case 109 : /* fall through */
+ case 110 : /* fall through */
+ case 111 : /* fall through */
+ case 112 : /* fall through */
+ case 113 : /* fall through */
+ case 114 : /* fall through */
+ case 115 : /* fall through */
+ case 116 : /* fall through */
+ case 117 : /* fall through */
+ case 118 : /* fall through */
+ case 119 : /* fall through */
+ case 120 : /* fall through */
+ case 121 : /* fall through */
+ case 122 : /* fall through */
+ case 123 : /* fall through */
+ case 124 : /* fall through */
+ case 125 : /* fall through */
+ case 126 : /* fall through */
+ case 127 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 304 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = ARC700F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = ARC700F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28300000)
+ { itype = ARC700F_INSN_MULULW_L_R_R__RA__RC; goto extract_sfmt_mullw_L_r_r__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 305 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC700F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC700F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC700F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC700F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28310000)
+ { itype = ARC700F_INSN_MULLW_L_R_R__RA__RC; goto extract_sfmt_mullw_L_r_r__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 307 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC700F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC700F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC700F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC700F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28330000)
+ { itype = ARC700F_INSN_MACLW_L_R_R__RA__RC; goto extract_sfmt_maclw_L_r_r__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 309 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC700F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC700F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC700F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC700F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28350000)
+ { itype = ARC700F_INSN_MACHULW_L_R_R__RA__RC; goto extract_sfmt_machulw_L_r_r__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 310 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = ARC700F_INSN_BL; goto extract_sfmt_bl; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = ARC700F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28360000)
+ { itype = ARC700F_INSN_MACHLW_L_R_R__RA__RC; goto extract_sfmt_maclw_L_r_r__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 320 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = ARC700F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = ARC700F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28400000)
+ { itype = ARC700F_INSN_ASL_L_U6__RA_; goto extract_sfmt_asl_L_u6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 321 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC700F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC700F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC700F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC700F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28410000)
+ { itype = ARC700F_INSN_LSR_L_U6__RA_; goto extract_sfmt_asl_L_u6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 322 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = ARC700F_INSN_BL; goto extract_sfmt_bl; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = ARC700F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28420000)
+ { itype = ARC700F_INSN_ASR_L_U6__RA_; goto extract_sfmt_asl_L_u6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 323 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC700F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC700F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC700F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC700F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28430000)
+ { itype = ARC700F_INSN_ROR_L_U6__RA_; goto extract_sfmt_asl_L_u6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 324 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = ARC700F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = ARC700F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28440000)
+ { itype = ARC700F_INSN_MUL64_L_U6_; goto extract_sfmt_mul64_L_u6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 325 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC700F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC700F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC700F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC700F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28450000)
+ { itype = ARC700F_INSN_MULU64_L_U6_; goto extract_sfmt_mul64_L_u6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 326 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = ARC700F_INSN_BL; goto extract_sfmt_bl; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = ARC700F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28460000)
+ { itype = ARC700F_INSN_ADDS_L_U6__RA_; goto extract_sfmt_adds_L_u6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 327 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC700F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC700F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC700F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC700F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28470000)
+ { itype = ARC700F_INSN_SUBS_L_U6__RA_; goto extract_sfmt_adds_L_u6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 328 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = ARC700F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = ARC700F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28480000)
+ { itype = ARC700F_INSN_DIVAW_L_U6__RA_; goto extract_sfmt_divaw_L_u6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 330 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = ARC700F_INSN_BL; goto extract_sfmt_bl; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = ARC700F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x284a0000)
+ { itype = ARC700F_INSN_ASLS_L_U6__RA_; goto extract_sfmt_asls_L_u6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 331 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC700F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC700F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC700F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC700F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x284b0000)
+ { itype = ARC700F_INSN_ASRS_L_U6__RA_; goto extract_sfmt_asls_L_u6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 360 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = ARC700F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = ARC700F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28680000)
+ { itype = ARC700F_INSN_ADDSDW_L_U6__RA_; goto extract_sfmt_asls_L_u6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 361 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC700F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC700F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC700F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC700F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28690000)
+ { itype = ARC700F_INSN_SUBSDW_L_U6__RA_; goto extract_sfmt_asls_L_u6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 367 :
+ {
+ unsigned int val = (((insn >> 25) & (1 << 6)) | ((insn >> 24) & (1 << 5)) | ((insn >> 1) & (3 << 3)) | ((insn >> 0) & (7 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC700F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC700F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 16 : /* fall through */
+ case 17 : /* fall through */
+ case 18 : /* fall through */
+ case 19 : /* fall through */
+ case 20 : /* fall through */
+ case 21 : /* fall through */
+ case 22 : /* fall through */
+ case 23 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC700F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 24 : /* fall through */
+ case 25 : /* fall through */
+ case 26 : /* fall through */
+ case 27 : /* fall through */
+ case 28 : /* fall through */
+ case 29 : /* fall through */
+ case 30 : /* fall through */
+ case 31 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC700F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 32 :
+ {
+ unsigned int val = (((insn >> 3) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8ff003f) == 0x286f0000)
+ { itype = ARC700F_INSN_SWAP_L_U6_; goto extract_sfmt_swap_L_u6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8ff003f) == 0x286f0008)
+ { itype = ARC700F_INSN_NORMW_L_U6_; goto extract_sfmt_swap_L_u6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 33 :
+ if ((entire_insn & 0xf8ff003f) == 0x286f0001)
+ { itype = ARC700F_INSN_NORM_L_U6_; goto extract_sfmt_norm_L_u6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 35 :
+ if ((entire_insn & 0xf8ff003f) == 0x286f0003)
+ { itype = ARC700F_INSN_RND16_L_U6_; goto extract_sfmt_rnd16_L_u6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 36 :
+ if ((entire_insn & 0xf8ff003f) == 0x286f0004)
+ { itype = ARC700F_INSN_ABSSW_L_U6_; goto extract_sfmt_abssw_L_u6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 37 :
+ if ((entire_insn & 0xf8ff003f) == 0x286f0005)
+ { itype = ARC700F_INSN_ABSS_L_U6_; goto extract_sfmt_abss_L_u6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 38 :
+ if ((entire_insn & 0xf8ff003f) == 0x286f0006)
+ { itype = ARC700F_INSN_NEGSW_L_U6_; goto extract_sfmt_abssw_L_u6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 39 :
+ if ((entire_insn & 0xf8ff003f) == 0x286f0007)
+ { itype = ARC700F_INSN_NEGS_L_U6_; goto extract_sfmt_rnd16_L_u6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 64 : /* fall through */
+ case 65 : /* fall through */
+ case 66 : /* fall through */
+ case 67 : /* fall through */
+ case 68 : /* fall through */
+ case 69 : /* fall through */
+ case 70 : /* fall through */
+ case 71 : /* fall through */
+ case 72 : /* fall through */
+ case 73 : /* fall through */
+ case 74 : /* fall through */
+ case 75 : /* fall through */
+ case 76 : /* fall through */
+ case 77 : /* fall through */
+ case 78 : /* fall through */
+ case 79 : /* fall through */
+ case 80 : /* fall through */
+ case 81 : /* fall through */
+ case 82 : /* fall through */
+ case 83 : /* fall through */
+ case 84 : /* fall through */
+ case 85 : /* fall through */
+ case 86 : /* fall through */
+ case 87 : /* fall through */
+ case 88 : /* fall through */
+ case 89 : /* fall through */
+ case 90 : /* fall through */
+ case 91 : /* fall through */
+ case 92 : /* fall through */
+ case 93 : /* fall through */
+ case 94 : /* fall through */
+ case 95 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 96 : /* fall through */
+ case 97 : /* fall through */
+ case 98 : /* fall through */
+ case 99 : /* fall through */
+ case 100 : /* fall through */
+ case 101 : /* fall through */
+ case 102 : /* fall through */
+ case 103 : /* fall through */
+ case 104 : /* fall through */
+ case 105 : /* fall through */
+ case 106 : /* fall through */
+ case 107 : /* fall through */
+ case 108 : /* fall through */
+ case 109 : /* fall through */
+ case 110 : /* fall through */
+ case 111 : /* fall through */
+ case 112 : /* fall through */
+ case 113 : /* fall through */
+ case 114 : /* fall through */
+ case 115 : /* fall through */
+ case 116 : /* fall through */
+ case 117 : /* fall through */
+ case 118 : /* fall through */
+ case 119 : /* fall through */
+ case 120 : /* fall through */
+ case 121 : /* fall through */
+ case 122 : /* fall through */
+ case 123 : /* fall through */
+ case 124 : /* fall through */
+ case 125 : /* fall through */
+ case 126 : /* fall through */
+ case 127 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 368 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = ARC700F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = ARC700F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28700000)
+ { itype = ARC700F_INSN_MULULW_L_U6__RA_; goto extract_sfmt_mullw_L_u6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 369 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC700F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC700F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC700F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC700F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28710000)
+ { itype = ARC700F_INSN_MULLW_L_U6__RA_; goto extract_sfmt_mullw_L_u6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 371 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC700F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC700F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC700F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC700F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28730000)
+ { itype = ARC700F_INSN_MACLW_L_U6__RA_; goto extract_sfmt_maclw_L_u6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 373 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC700F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC700F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC700F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC700F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28750000)
+ { itype = ARC700F_INSN_MACHULW_L_U6__RA_; goto extract_sfmt_machulw_L_u6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 374 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = ARC700F_INSN_BL; goto extract_sfmt_bl; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = ARC700F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28760000)
+ { itype = ARC700F_INSN_MACHLW_L_U6__RA_; goto extract_sfmt_maclw_L_u6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 384 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = ARC700F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = ARC700F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28800000)
+ { itype = ARC700F_INSN_ASL_L_S12__RA_; goto extract_sfmt_asl_L_s12__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 385 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC700F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC700F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC700F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC700F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28810000)
+ { itype = ARC700F_INSN_LSR_L_S12__RA_; goto extract_sfmt_asl_L_s12__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 386 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = ARC700F_INSN_BL; goto extract_sfmt_bl; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = ARC700F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28820000)
+ { itype = ARC700F_INSN_ASR_L_S12__RA_; goto extract_sfmt_asl_L_s12__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 387 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC700F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC700F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC700F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC700F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28830000)
+ { itype = ARC700F_INSN_ROR_L_S12__RA_; goto extract_sfmt_asl_L_s12__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 388 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = ARC700F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = ARC700F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28840000)
+ { itype = ARC700F_INSN_MUL64_L_S12_; goto extract_sfmt_mul64_L_s12_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 389 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC700F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC700F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC700F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC700F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28850000)
+ { itype = ARC700F_INSN_MULU64_L_S12_; goto extract_sfmt_mul64_L_s12_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 390 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = ARC700F_INSN_BL; goto extract_sfmt_bl; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = ARC700F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28860000)
+ { itype = ARC700F_INSN_ADDS_L_S12__RA_; goto extract_sfmt_adds_L_s12__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 391 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC700F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC700F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC700F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC700F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28870000)
+ { itype = ARC700F_INSN_SUBS_L_S12__RA_; goto extract_sfmt_adds_L_s12__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 392 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = ARC700F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = ARC700F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28880000)
+ { itype = ARC700F_INSN_DIVAW_L_S12__RA_; goto extract_sfmt_divaw_L_s12__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 394 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = ARC700F_INSN_BL; goto extract_sfmt_bl; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = ARC700F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x288a0000)
+ { itype = ARC700F_INSN_ASLS_L_S12__RA_; goto extract_sfmt_asls_L_s12__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 395 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC700F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC700F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC700F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC700F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x288b0000)
+ { itype = ARC700F_INSN_ASRS_L_S12__RA_; goto extract_sfmt_asls_L_s12__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 424 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = ARC700F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = ARC700F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28a80000)
+ { itype = ARC700F_INSN_ADDSDW_L_S12__RA_; goto extract_sfmt_asls_L_s12__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 425 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC700F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC700F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC700F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC700F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28a90000)
+ { itype = ARC700F_INSN_SUBSDW_L_S12__RA_; goto extract_sfmt_asls_L_s12__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 432 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = ARC700F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = ARC700F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28b00000)
+ { itype = ARC700F_INSN_MULULW_L_S12__RA_; goto extract_sfmt_mullw_L_s12__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 433 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC700F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC700F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC700F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC700F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28b10000)
+ { itype = ARC700F_INSN_MULLW_L_S12__RA_; goto extract_sfmt_mullw_L_s12__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 435 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC700F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC700F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC700F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC700F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28b30000)
+ { itype = ARC700F_INSN_MACLW_L_S12__RA_; goto extract_sfmt_maclw_L_s12__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 437 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC700F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC700F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC700F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC700F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0000) == 0x28b50000)
+ { itype = ARC700F_INSN_MACHULW_L_S12__RA_; goto extract_sfmt_machulw_L_s12__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 438 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = ARC700F_INSN_BL; goto extract_sfmt_bl; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = ARC700F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8ff0000) == 0x28b60000)
+ { itype = ARC700F_INSN_MACHLW_L_S12__RA_; goto extract_sfmt_maclw_L_s12__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 448 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = ARC700F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = ARC700F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c00000)
+ { itype = ARC700F_INSN_ASL_CC__RA__RC; goto extract_sfmt_asl_cc__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c00020)
+ { itype = ARC700F_INSN_ASL_CCU6__RA_; goto extract_sfmt_asl_ccu6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 449 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC700F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC700F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC700F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC700F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c10000)
+ { itype = ARC700F_INSN_LSR_CC__RA__RC; goto extract_sfmt_asl_cc__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c10020)
+ { itype = ARC700F_INSN_LSR_CCU6__RA_; goto extract_sfmt_asl_ccu6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 450 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = ARC700F_INSN_BL; goto extract_sfmt_bl; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = ARC700F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c20000)
+ { itype = ARC700F_INSN_ASR_CC__RA__RC; goto extract_sfmt_asl_cc__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c20020)
+ { itype = ARC700F_INSN_ASR_CCU6__RA_; goto extract_sfmt_asl_ccu6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 451 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC700F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC700F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC700F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC700F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c30000)
+ { itype = ARC700F_INSN_ROR_CC__RA__RC; goto extract_sfmt_asl_cc__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c30020)
+ { itype = ARC700F_INSN_ROR_CCU6__RA_; goto extract_sfmt_asl_ccu6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 452 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = ARC700F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = ARC700F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c40000)
+ { itype = ARC700F_INSN_MUL64_CC__RC; goto extract_sfmt_mul64_cc__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c40020)
+ { itype = ARC700F_INSN_MUL64_CCU6_; goto extract_sfmt_mul64_ccu6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 453 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC700F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC700F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC700F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC700F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c50000)
+ { itype = ARC700F_INSN_MULU64_CC__RC; goto extract_sfmt_mul64_cc__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c50020)
+ { itype = ARC700F_INSN_MULU64_CCU6_; goto extract_sfmt_mul64_ccu6_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 454 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = ARC700F_INSN_BL; goto extract_sfmt_bl; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = ARC700F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c60000)
+ { itype = ARC700F_INSN_ADDS_CC__RA__RC; goto extract_sfmt_adds_cc__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c60020)
+ { itype = ARC700F_INSN_ADDS_CCU6__RA_; goto extract_sfmt_adds_ccu6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 455 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC700F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC700F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC700F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC700F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c70000)
+ { itype = ARC700F_INSN_SUBS_CC__RA__RC; goto extract_sfmt_adds_cc__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c70020)
+ { itype = ARC700F_INSN_SUBS_CCU6__RA_; goto extract_sfmt_adds_ccu6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 456 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = ARC700F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = ARC700F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c80000)
+ { itype = ARC700F_INSN_DIVAW_CC__RA__RC; goto extract_sfmt_divaw_cc__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x28c80020)
+ { itype = ARC700F_INSN_DIVAW_CCU6__RA_; goto extract_sfmt_divaw_ccu6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 458 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = ARC700F_INSN_BL; goto extract_sfmt_bl; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = ARC700F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x28ca0000)
+ { itype = ARC700F_INSN_ASLS_CC__RA__RC; goto extract_sfmt_asls_cc__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x28ca0020)
+ { itype = ARC700F_INSN_ASLS_CCU6__RA_; goto extract_sfmt_asls_ccu6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 459 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC700F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC700F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC700F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC700F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8ff0020) == 0x28cb0000)
+ { itype = ARC700F_INSN_ASRS_CC__RA__RC; goto extract_sfmt_asls_cc__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0020) == 0x28cb0020)
+ { itype = ARC700F_INSN_ASRS_CCU6__RA_; goto extract_sfmt_asls_ccu6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 488 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = ARC700F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = ARC700F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x28e80000)
+ { itype = ARC700F_INSN_ADDSDW_CC__RA__RC; goto extract_sfmt_asls_cc__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x28e80020)
+ { itype = ARC700F_INSN_ADDSDW_CCU6__RA_; goto extract_sfmt_asls_ccu6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 489 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC700F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC700F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC700F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC700F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8ff0020) == 0x28e90000)
+ { itype = ARC700F_INSN_SUBSDW_CC__RA__RC; goto extract_sfmt_asls_cc__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0020) == 0x28e90020)
+ { itype = ARC700F_INSN_SUBSDW_CCU6__RA_; goto extract_sfmt_asls_ccu6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 496 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030020) == 0x8000000)
+ { itype = ARC700F_INSN_BLCC; goto extract_sfmt_blcc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030020) == 0x8000020)
+ { itype = ARC700F_INSN_BLCC_D; goto extract_sfmt_blcc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x28f00000)
+ { itype = ARC700F_INSN_MULULW_CC__RA__RC; goto extract_sfmt_mullw_cc__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x28f00020)
+ { itype = ARC700F_INSN_MULULW_CCU6__RA_; goto extract_sfmt_mullw_ccu6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 497 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC700F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC700F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC700F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC700F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8ff0020) == 0x28f10000)
+ { itype = ARC700F_INSN_MULLW_CC__RA__RC; goto extract_sfmt_mullw_cc__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0020) == 0x28f10020)
+ { itype = ARC700F_INSN_MULLW_CCU6__RA_; goto extract_sfmt_mullw_ccu6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 499 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC700F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC700F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC700F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC700F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8ff0020) == 0x28f30000)
+ { itype = ARC700F_INSN_MACLW_CC__RA__RC; goto extract_sfmt_maclw_cc__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0020) == 0x28f30020)
+ { itype = ARC700F_INSN_MACLW_CCU6__RA_; goto extract_sfmt_maclw_ccu6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 501 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8010030) == 0x8010000)
+ { itype = ARC700F_INSN_BRCC_RC; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8010030) == 0x8010010)
+ { itype = ARC700F_INSN_BRCC_U6; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8010030) == 0x8010020)
+ { itype = ARC700F_INSN_BRCC_RC_D; goto extract_sfmt_brcc_RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8010030) == 0x8010030)
+ { itype = ARC700F_INSN_BRCC_U6_D; goto extract_sfmt_brcc_U6; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8ff0020) == 0x28f50000)
+ { itype = ARC700F_INSN_MACHULW_CC__RA__RC; goto extract_sfmt_machulw_cc__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8ff0020) == 0x28f50020)
+ { itype = ARC700F_INSN_MACHULW_CCU6__RA_; goto extract_sfmt_machulw_ccu6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 502 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8030030) == 0x8020000)
+ { itype = ARC700F_INSN_BL; goto extract_sfmt_bl; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8030030) == 0x8020020)
+ { itype = ARC700F_INSN_BL_D; goto extract_sfmt_bl_d; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0020) == 0x28f60000)
+ { itype = ARC700F_INSN_MACHLW_CC__RA__RC; goto extract_sfmt_maclw_cc__RA__RC; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8ff0020) == 0x28f60020)
+ { itype = ARC700F_INSN_MACHLW_CCU6__RA_; goto extract_sfmt_maclw_ccu6__RA_; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 : /* fall through */
+ case 5 :
+ if ((entire_insn & 0xf8000000) == 0x88000000)
+ { itype = ARC700F_INSN_LDB_S_ABU; goto extract_sfmt_ldb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8000000) == 0xa8000000)
+ { itype = ARC700F_INSN_STB_S_ABU; goto extract_sfmt_stb_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 512 : /* fall through */
+ case 513 : /* fall through */
+ case 514 : /* fall through */
+ case 515 : /* fall through */
+ case 516 : /* fall through */
+ case 517 : /* fall through */
+ case 518 : /* fall through */
+ case 519 : /* fall through */
+ case 520 : /* fall through */
+ case 521 : /* fall through */
+ case 522 : /* fall through */
+ case 523 : /* fall through */
+ case 524 : /* fall through */
+ case 525 : /* fall through */
+ case 526 : /* fall through */
+ case 527 : /* fall through */
+ case 528 : /* fall through */
+ case 529 : /* fall through */
+ case 530 : /* fall through */
+ case 531 : /* fall through */
+ case 532 : /* fall through */
+ case 533 : /* fall through */
+ case 534 : /* fall through */
+ case 535 : /* fall through */
+ case 536 : /* fall through */
+ case 537 : /* fall through */
+ case 538 : /* fall through */
+ case 539 : /* fall through */
+ case 540 : /* fall through */
+ case 541 : /* fall through */
+ case 542 : /* fall through */
+ case 543 : /* fall through */
+ case 544 : /* fall through */
+ case 545 : /* fall through */
+ case 546 : /* fall through */
+ case 547 : /* fall through */
+ case 548 : /* fall through */
+ case 549 : /* fall through */
+ case 550 : /* fall through */
+ case 551 : /* fall through */
+ case 552 : /* fall through */
+ case 553 : /* fall through */
+ case 554 : /* fall through */
+ case 555 : /* fall through */
+ case 556 : /* fall through */
+ case 557 : /* fall through */
+ case 558 : /* fall through */
+ case 559 : /* fall through */
+ case 560 : /* fall through */
+ case 561 : /* fall through */
+ case 562 : /* fall through */
+ case 563 : /* fall through */
+ case 564 : /* fall through */
+ case 565 : /* fall through */
+ case 566 : /* fall through */
+ case 567 : /* fall through */
+ case 568 : /* fall through */
+ case 569 : /* fall through */
+ case 570 : /* fall through */
+ case 571 : /* fall through */
+ case 572 : /* fall through */
+ case 573 : /* fall through */
+ case 574 : /* fall through */
+ case 575 : /* fall through */
+ case 576 : /* fall through */
+ case 577 : /* fall through */
+ case 578 : /* fall through */
+ case 579 : /* fall through */
+ case 580 : /* fall through */
+ case 581 : /* fall through */
+ case 582 : /* fall through */
+ case 583 : /* fall through */
+ case 584 : /* fall through */
+ case 585 : /* fall through */
+ case 586 : /* fall through */
+ case 587 : /* fall through */
+ case 588 : /* fall through */
+ case 589 : /* fall through */
+ case 590 : /* fall through */
+ case 591 : /* fall through */
+ case 592 : /* fall through */
+ case 593 : /* fall through */
+ case 594 : /* fall through */
+ case 595 : /* fall through */
+ case 596 : /* fall through */
+ case 597 : /* fall through */
+ case 598 : /* fall through */
+ case 599 : /* fall through */
+ case 600 : /* fall through */
+ case 601 : /* fall through */
+ case 602 : /* fall through */
+ case 603 : /* fall through */
+ case 604 : /* fall through */
+ case 605 : /* fall through */
+ case 606 : /* fall through */
+ case 607 : /* fall through */
+ case 608 : /* fall through */
+ case 609 : /* fall through */
+ case 610 : /* fall through */
+ case 611 : /* fall through */
+ case 612 : /* fall through */
+ case 613 : /* fall through */
+ case 614 : /* fall through */
+ case 615 : /* fall through */
+ case 616 : /* fall through */
+ case 617 : /* fall through */
+ case 618 : /* fall through */
+ case 619 : /* fall through */
+ case 620 : /* fall through */
+ case 621 : /* fall through */
+ case 622 : /* fall through */
+ case 623 : /* fall through */
+ case 624 : /* fall through */
+ case 625 : /* fall through */
+ case 626 : /* fall through */
+ case 627 : /* fall through */
+ case 628 : /* fall through */
+ case 629 : /* fall through */
+ case 630 : /* fall through */
+ case 631 : /* fall through */
+ case 632 : /* fall through */
+ case 633 : /* fall through */
+ case 634 : /* fall through */
+ case 635 : /* fall through */
+ case 636 : /* fall through */
+ case 637 : /* fall through */
+ case 638 : /* fall through */
+ case 639 : /* fall through */
+ case 640 : /* fall through */
+ case 641 : /* fall through */
+ case 642 : /* fall through */
+ case 643 : /* fall through */
+ case 644 : /* fall through */
+ case 645 : /* fall through */
+ case 646 : /* fall through */
+ case 647 : /* fall through */
+ case 648 : /* fall through */
+ case 649 : /* fall through */
+ case 650 : /* fall through */
+ case 651 : /* fall through */
+ case 652 : /* fall through */
+ case 653 : /* fall through */
+ case 654 : /* fall through */
+ case 655 : /* fall through */
+ case 656 : /* fall through */
+ case 657 : /* fall through */
+ case 658 : /* fall through */
+ case 659 : /* fall through */
+ case 660 : /* fall through */
+ case 661 : /* fall through */
+ case 662 : /* fall through */
+ case 663 : /* fall through */
+ case 664 : /* fall through */
+ case 665 : /* fall through */
+ case 666 : /* fall through */
+ case 667 : /* fall through */
+ case 668 : /* fall through */
+ case 669 : /* fall through */
+ case 670 : /* fall through */
+ case 671 : /* fall through */
+ case 672 : /* fall through */
+ case 673 : /* fall through */
+ case 674 : /* fall through */
+ case 675 : /* fall through */
+ case 676 : /* fall through */
+ case 677 : /* fall through */
+ case 678 : /* fall through */
+ case 679 : /* fall through */
+ case 680 : /* fall through */
+ case 681 : /* fall through */
+ case 682 : /* fall through */
+ case 683 : /* fall through */
+ case 684 : /* fall through */
+ case 685 : /* fall through */
+ case 686 : /* fall through */
+ case 687 : /* fall through */
+ case 688 : /* fall through */
+ case 689 : /* fall through */
+ case 690 : /* fall through */
+ case 691 : /* fall through */
+ case 692 : /* fall through */
+ case 693 : /* fall through */
+ case 694 : /* fall through */
+ case 695 : /* fall through */
+ case 696 : /* fall through */
+ case 697 : /* fall through */
+ case 698 : /* fall through */
+ case 699 : /* fall through */
+ case 700 : /* fall through */
+ case 701 : /* fall through */
+ case 702 : /* fall through */
+ case 703 : /* fall through */
+ case 704 : /* fall through */
+ case 705 : /* fall through */
+ case 706 : /* fall through */
+ case 707 : /* fall through */
+ case 708 : /* fall through */
+ case 709 : /* fall through */
+ case 710 : /* fall through */
+ case 711 : /* fall through */
+ case 712 : /* fall through */
+ case 713 : /* fall through */
+ case 714 : /* fall through */
+ case 715 : /* fall through */
+ case 716 : /* fall through */
+ case 717 : /* fall through */
+ case 718 : /* fall through */
+ case 719 : /* fall through */
+ case 720 : /* fall through */
+ case 721 : /* fall through */
+ case 722 : /* fall through */
+ case 723 : /* fall through */
+ case 724 : /* fall through */
+ case 725 : /* fall through */
+ case 726 : /* fall through */
+ case 727 : /* fall through */
+ case 728 : /* fall through */
+ case 729 : /* fall through */
+ case 730 : /* fall through */
+ case 731 : /* fall through */
+ case 732 : /* fall through */
+ case 733 : /* fall through */
+ case 734 : /* fall through */
+ case 735 : /* fall through */
+ case 736 : /* fall through */
+ case 737 : /* fall through */
+ case 738 : /* fall through */
+ case 739 : /* fall through */
+ case 740 : /* fall through */
+ case 741 : /* fall through */
+ case 742 : /* fall through */
+ case 743 : /* fall through */
+ case 744 : /* fall through */
+ case 745 : /* fall through */
+ case 746 : /* fall through */
+ case 747 : /* fall through */
+ case 748 : /* fall through */
+ case 749 : /* fall through */
+ case 750 : /* fall through */
+ case 751 : /* fall through */
+ case 752 : /* fall through */
+ case 753 : /* fall through */
+ case 754 : /* fall through */
+ case 755 : /* fall through */
+ case 756 : /* fall through */
+ case 757 : /* fall through */
+ case 758 : /* fall through */
+ case 759 : /* fall through */
+ case 760 : /* fall through */
+ case 761 : /* fall through */
+ case 762 : /* fall through */
+ case 763 : /* fall through */
+ case 764 : /* fall through */
+ case 765 : /* fall through */
+ case 766 : /* fall through */
+ case 767 :
+ {
+ unsigned int val = (((insn >> 25) & (1 << 6)) | ((insn >> 24) & (1 << 5)) | ((insn >> 6) & (31 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf80007c0) == 0x10000000)
+ { itype = ARC700F_INSN_LD_ABS; goto extract_sfmt_ld_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf80007c0) == 0x10000080)
+ { itype = ARC700F_INSN_LDB_ABS; goto extract_sfmt_ldb_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf80007c0) == 0x100000c0)
+ { itype = ARC700F_INSN_LDB_X_ABS; goto extract_sfmt_ldb_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xf80007c0) == 0x10000100)
+ { itype = ARC700F_INSN_LDW_ABS; goto extract_sfmt_ldw_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xf80007c0) == 0x10000140)
+ { itype = ARC700F_INSN_LDW_X_ABS; goto extract_sfmt_ldw_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 :
+ if ((entire_insn & 0xf80007c0) == 0x10000200)
+ { itype = ARC700F_INSN_LD__AW_ABS; goto extract_sfmt_ld__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 10 :
+ if ((entire_insn & 0xf80007c0) == 0x10000280)
+ { itype = ARC700F_INSN_LDB__AW_ABS; goto extract_sfmt_ldb__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 11 :
+ if ((entire_insn & 0xf80007c0) == 0x100002c0)
+ { itype = ARC700F_INSN_LDB__AW_X_ABS; goto extract_sfmt_ldb__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 :
+ if ((entire_insn & 0xf80007c0) == 0x10000300)
+ { itype = ARC700F_INSN_LDW__AW_ABS; goto extract_sfmt_ldw__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 13 :
+ if ((entire_insn & 0xf80007c0) == 0x10000340)
+ { itype = ARC700F_INSN_LDW__AW_X_ABS; goto extract_sfmt_ldw__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 16 :
+ if ((entire_insn & 0xf80007c0) == 0x10000400)
+ { itype = ARC700F_INSN_LD_AB_ABS; goto extract_sfmt_ld__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 18 :
+ if ((entire_insn & 0xf80007c0) == 0x10000480)
+ { itype = ARC700F_INSN_LDB_AB_ABS; goto extract_sfmt_ldb__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 19 :
+ if ((entire_insn & 0xf80007c0) == 0x100004c0)
+ { itype = ARC700F_INSN_LDB_AB_X_ABS; goto extract_sfmt_ldb__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 20 :
+ if ((entire_insn & 0xf80007c0) == 0x10000500)
+ { itype = ARC700F_INSN_LDW_AB_ABS; goto extract_sfmt_ldw__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 21 :
+ if ((entire_insn & 0xf80007c0) == 0x10000540)
+ { itype = ARC700F_INSN_LDW_AB_X_ABS; goto extract_sfmt_ldw__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 24 :
+ if ((entire_insn & 0xf80007c0) == 0x10000600)
+ { itype = ARC700F_INSN_LD_AS_ABS; goto extract_sfmt_ld_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 26 :
+ if ((entire_insn & 0xf80007c0) == 0x10000680)
+ { itype = ARC700F_INSN_LDB_AS_ABS; goto extract_sfmt_ldb_as_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 27 :
+ if ((entire_insn & 0xf80007c0) == 0x100006c0)
+ { itype = ARC700F_INSN_LDB_AS_X_ABS; goto extract_sfmt_ldb_as_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 28 :
+ if ((entire_insn & 0xf80007c0) == 0x10000700)
+ { itype = ARC700F_INSN_LDW_AS_ABS; goto extract_sfmt_ldw_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 29 :
+ if ((entire_insn & 0xf80007c0) == 0x10000740)
+ { itype = ARC700F_INSN_LDW_AS_X_ABS; goto extract_sfmt_ldw_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 64 : /* fall through */
+ case 65 : /* fall through */
+ case 66 : /* fall through */
+ case 67 : /* fall through */
+ case 68 : /* fall through */
+ case 69 : /* fall through */
+ case 70 : /* fall through */
+ case 71 : /* fall through */
+ case 72 : /* fall through */
+ case 73 : /* fall through */
+ case 74 : /* fall through */
+ case 75 : /* fall through */
+ case 76 : /* fall through */
+ case 77 : /* fall through */
+ case 78 : /* fall through */
+ case 79 : /* fall through */
+ case 80 : /* fall through */
+ case 81 : /* fall through */
+ case 82 : /* fall through */
+ case 83 : /* fall through */
+ case 84 : /* fall through */
+ case 85 : /* fall through */
+ case 86 : /* fall through */
+ case 87 : /* fall through */
+ case 88 : /* fall through */
+ case 89 : /* fall through */
+ case 90 : /* fall through */
+ case 91 : /* fall through */
+ case 92 : /* fall through */
+ case 93 : /* fall through */
+ case 94 : /* fall through */
+ case 95 :
+ if ((entire_insn & 0xf8000000) == 0x90000000)
+ { itype = ARC700F_INSN_LDW_S_ABU; goto extract_sfmt_ldw_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 96 : /* fall through */
+ case 97 : /* fall through */
+ case 98 : /* fall through */
+ case 99 : /* fall through */
+ case 100 : /* fall through */
+ case 101 : /* fall through */
+ case 102 : /* fall through */
+ case 103 : /* fall through */
+ case 104 : /* fall through */
+ case 105 : /* fall through */
+ case 106 : /* fall through */
+ case 107 : /* fall through */
+ case 108 : /* fall through */
+ case 109 : /* fall through */
+ case 110 : /* fall through */
+ case 111 : /* fall through */
+ case 112 : /* fall through */
+ case 113 : /* fall through */
+ case 114 : /* fall through */
+ case 115 : /* fall through */
+ case 116 : /* fall through */
+ case 117 : /* fall through */
+ case 118 : /* fall through */
+ case 119 : /* fall through */
+ case 120 : /* fall through */
+ case 121 : /* fall through */
+ case 122 : /* fall through */
+ case 123 : /* fall through */
+ case 124 : /* fall through */
+ case 125 : /* fall through */
+ case 126 : /* fall through */
+ case 127 :
+ if ((entire_insn & 0xf8000000) == 0xb0000000)
+ { itype = ARC700F_INSN_STW_S_ABU; goto extract_sfmt_stw_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 768 : /* fall through */
+ case 769 : /* fall through */
+ case 770 : /* fall through */
+ case 771 : /* fall through */
+ case 772 : /* fall through */
+ case 773 : /* fall through */
+ case 774 : /* fall through */
+ case 775 : /* fall through */
+ case 776 : /* fall through */
+ case 777 : /* fall through */
+ case 778 : /* fall through */
+ case 779 : /* fall through */
+ case 780 : /* fall through */
+ case 781 : /* fall through */
+ case 782 : /* fall through */
+ case 783 : /* fall through */
+ case 784 : /* fall through */
+ case 785 : /* fall through */
+ case 786 : /* fall through */
+ case 787 : /* fall through */
+ case 788 : /* fall through */
+ case 789 : /* fall through */
+ case 790 : /* fall through */
+ case 791 : /* fall through */
+ case 792 : /* fall through */
+ case 793 : /* fall through */
+ case 794 : /* fall through */
+ case 795 : /* fall through */
+ case 796 : /* fall through */
+ case 797 : /* fall through */
+ case 798 : /* fall through */
+ case 799 :
+ {
+ unsigned int val = (((insn >> 26) & (1 << 5)) | ((insn >> 25) & (1 << 4)) | ((insn >> 1) & (15 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf800001f) == 0x18000000)
+ { itype = ARC700F_INSN_ST_ABS; goto extract_sfmt_st_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf800001f) == 0x18000002)
+ { itype = ARC700F_INSN_STB_ABS; goto extract_sfmt_stb_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf800001f) == 0x18000004)
+ { itype = ARC700F_INSN_STW_ABS; goto extract_sfmt_stw_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xf800001f) == 0x18000008)
+ { itype = ARC700F_INSN_ST__AW_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xf800001f) == 0x1800000a)
+ { itype = ARC700F_INSN_STB__AW_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 :
+ if ((entire_insn & 0xf800001f) == 0x1800000c)
+ { itype = ARC700F_INSN_STW__AW_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 :
+ if ((entire_insn & 0xf800001f) == 0x18000010)
+ { itype = ARC700F_INSN_ST_AB_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 9 :
+ if ((entire_insn & 0xf800001f) == 0x18000012)
+ { itype = ARC700F_INSN_STB_AB_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 10 :
+ if ((entire_insn & 0xf800001f) == 0x18000014)
+ { itype = ARC700F_INSN_STW_AB_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 :
+ if ((entire_insn & 0xf800001f) == 0x18000018)
+ { itype = ARC700F_INSN_ST_AS_ABS; goto extract_sfmt_st_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 13 :
+ if ((entire_insn & 0xf800001f) == 0x1800001a)
+ { itype = ARC700F_INSN_STB_AS_ABS; goto extract_sfmt_stb_as_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 14 :
+ if ((entire_insn & 0xf800001f) == 0x1800001c)
+ { itype = ARC700F_INSN_STW_AS_ABS; goto extract_sfmt_stw_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 32 : /* fall through */
+ case 33 : /* fall through */
+ case 34 : /* fall through */
+ case 35 : /* fall through */
+ case 36 : /* fall through */
+ case 37 : /* fall through */
+ case 38 : /* fall through */
+ case 39 : /* fall through */
+ case 40 : /* fall through */
+ case 41 : /* fall through */
+ case 42 : /* fall through */
+ case 43 : /* fall through */
+ case 44 : /* fall through */
+ case 45 : /* fall through */
+ case 46 : /* fall through */
+ case 47 :
+ if ((entire_insn & 0xf8000000) == 0x98000000)
+ { itype = ARC700F_INSN_LDW_S_X_ABU; goto extract_sfmt_ldw_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 48 : /* fall through */
+ case 49 : /* fall through */
+ case 50 : /* fall through */
+ case 51 : /* fall through */
+ case 52 : /* fall through */
+ case 53 : /* fall through */
+ case 54 : /* fall through */
+ case 55 : /* fall through */
+ case 56 : /* fall through */
+ case 57 : /* fall through */
+ case 58 : /* fall through */
+ case 59 : /* fall through */
+ case 60 : /* fall through */
+ case 61 : /* fall through */
+ case 62 : /* fall through */
+ case 63 :
+ if ((entire_insn & 0xf8e00000) == 0xb8000000)
+ { itype = ARC700F_INSN_ASL_S_SSB; goto extract_sfmt_sub_s_ssb; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 800 : /* fall through */
+ case 801 : /* fall through */
+ case 802 : /* fall through */
+ case 803 : /* fall through */
+ case 804 : /* fall through */
+ case 805 : /* fall through */
+ case 806 : /* fall through */
+ case 807 : /* fall through */
+ case 808 : /* fall through */
+ case 809 : /* fall through */
+ case 810 : /* fall through */
+ case 811 : /* fall through */
+ case 812 : /* fall through */
+ case 813 : /* fall through */
+ case 814 : /* fall through */
+ case 815 : /* fall through */
+ case 816 : /* fall through */
+ case 817 : /* fall through */
+ case 818 : /* fall through */
+ case 819 : /* fall through */
+ case 820 : /* fall through */
+ case 821 : /* fall through */
+ case 822 : /* fall through */
+ case 823 : /* fall through */
+ case 824 : /* fall through */
+ case 825 : /* fall through */
+ case 826 : /* fall through */
+ case 827 : /* fall through */
+ case 828 : /* fall through */
+ case 829 : /* fall through */
+ case 830 : /* fall through */
+ case 831 :
+ {
+ unsigned int val = (((insn >> 26) & (1 << 5)) | ((insn >> 25) & (1 << 4)) | ((insn >> 1) & (15 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf800001f) == 0x18000000)
+ { itype = ARC700F_INSN_ST_ABS; goto extract_sfmt_st_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf800001f) == 0x18000002)
+ { itype = ARC700F_INSN_STB_ABS; goto extract_sfmt_stb_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf800001f) == 0x18000004)
+ { itype = ARC700F_INSN_STW_ABS; goto extract_sfmt_stw_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xf800001f) == 0x18000008)
+ { itype = ARC700F_INSN_ST__AW_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xf800001f) == 0x1800000a)
+ { itype = ARC700F_INSN_STB__AW_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 :
+ if ((entire_insn & 0xf800001f) == 0x1800000c)
+ { itype = ARC700F_INSN_STW__AW_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 :
+ if ((entire_insn & 0xf800001f) == 0x18000010)
+ { itype = ARC700F_INSN_ST_AB_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 9 :
+ if ((entire_insn & 0xf800001f) == 0x18000012)
+ { itype = ARC700F_INSN_STB_AB_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 10 :
+ if ((entire_insn & 0xf800001f) == 0x18000014)
+ { itype = ARC700F_INSN_STW_AB_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 :
+ if ((entire_insn & 0xf800001f) == 0x18000018)
+ { itype = ARC700F_INSN_ST_AS_ABS; goto extract_sfmt_st_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 13 :
+ if ((entire_insn & 0xf800001f) == 0x1800001a)
+ { itype = ARC700F_INSN_STB_AS_ABS; goto extract_sfmt_stb_as_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 14 :
+ if ((entire_insn & 0xf800001f) == 0x1800001c)
+ { itype = ARC700F_INSN_STW_AS_ABS; goto extract_sfmt_stw_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 32 : /* fall through */
+ case 33 : /* fall through */
+ case 34 : /* fall through */
+ case 35 : /* fall through */
+ case 36 : /* fall through */
+ case 37 : /* fall through */
+ case 38 : /* fall through */
+ case 39 : /* fall through */
+ case 40 : /* fall through */
+ case 41 : /* fall through */
+ case 42 : /* fall through */
+ case 43 : /* fall through */
+ case 44 : /* fall through */
+ case 45 : /* fall through */
+ case 46 : /* fall through */
+ case 47 :
+ if ((entire_insn & 0xf8000000) == 0x98000000)
+ { itype = ARC700F_INSN_LDW_S_X_ABU; goto extract_sfmt_ldw_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 48 : /* fall through */
+ case 49 : /* fall through */
+ case 50 : /* fall through */
+ case 51 : /* fall through */
+ case 52 : /* fall through */
+ case 53 : /* fall through */
+ case 54 : /* fall through */
+ case 55 : /* fall through */
+ case 56 : /* fall through */
+ case 57 : /* fall through */
+ case 58 : /* fall through */
+ case 59 : /* fall through */
+ case 60 : /* fall through */
+ case 61 : /* fall through */
+ case 62 : /* fall through */
+ case 63 :
+ if ((entire_insn & 0xf8e00000) == 0xb8200000)
+ { itype = ARC700F_INSN_LSR_S_SSB; goto extract_sfmt_sub_s_ssb; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 832 : /* fall through */
+ case 833 : /* fall through */
+ case 834 : /* fall through */
+ case 835 : /* fall through */
+ case 836 : /* fall through */
+ case 837 : /* fall through */
+ case 838 : /* fall through */
+ case 839 : /* fall through */
+ case 840 : /* fall through */
+ case 841 : /* fall through */
+ case 842 : /* fall through */
+ case 843 : /* fall through */
+ case 844 : /* fall through */
+ case 845 : /* fall through */
+ case 846 : /* fall through */
+ case 847 : /* fall through */
+ case 848 : /* fall through */
+ case 849 : /* fall through */
+ case 850 : /* fall through */
+ case 851 : /* fall through */
+ case 852 : /* fall through */
+ case 853 : /* fall through */
+ case 854 : /* fall through */
+ case 855 : /* fall through */
+ case 856 : /* fall through */
+ case 857 : /* fall through */
+ case 858 : /* fall through */
+ case 859 : /* fall through */
+ case 860 : /* fall through */
+ case 861 : /* fall through */
+ case 862 : /* fall through */
+ case 863 :
+ {
+ unsigned int val = (((insn >> 26) & (1 << 5)) | ((insn >> 25) & (1 << 4)) | ((insn >> 1) & (15 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf800001f) == 0x18000000)
+ { itype = ARC700F_INSN_ST_ABS; goto extract_sfmt_st_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf800001f) == 0x18000002)
+ { itype = ARC700F_INSN_STB_ABS; goto extract_sfmt_stb_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf800001f) == 0x18000004)
+ { itype = ARC700F_INSN_STW_ABS; goto extract_sfmt_stw_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xf800001f) == 0x18000008)
+ { itype = ARC700F_INSN_ST__AW_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xf800001f) == 0x1800000a)
+ { itype = ARC700F_INSN_STB__AW_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 :
+ if ((entire_insn & 0xf800001f) == 0x1800000c)
+ { itype = ARC700F_INSN_STW__AW_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 :
+ if ((entire_insn & 0xf800001f) == 0x18000010)
+ { itype = ARC700F_INSN_ST_AB_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 9 :
+ if ((entire_insn & 0xf800001f) == 0x18000012)
+ { itype = ARC700F_INSN_STB_AB_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 10 :
+ if ((entire_insn & 0xf800001f) == 0x18000014)
+ { itype = ARC700F_INSN_STW_AB_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 :
+ if ((entire_insn & 0xf800001f) == 0x18000018)
+ { itype = ARC700F_INSN_ST_AS_ABS; goto extract_sfmt_st_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 13 :
+ if ((entire_insn & 0xf800001f) == 0x1800001a)
+ { itype = ARC700F_INSN_STB_AS_ABS; goto extract_sfmt_stb_as_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 14 :
+ if ((entire_insn & 0xf800001f) == 0x1800001c)
+ { itype = ARC700F_INSN_STW_AS_ABS; goto extract_sfmt_stw_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 32 : /* fall through */
+ case 33 : /* fall through */
+ case 34 : /* fall through */
+ case 35 : /* fall through */
+ case 36 : /* fall through */
+ case 37 : /* fall through */
+ case 38 : /* fall through */
+ case 39 : /* fall through */
+ case 40 : /* fall through */
+ case 41 : /* fall through */
+ case 42 : /* fall through */
+ case 43 : /* fall through */
+ case 44 : /* fall through */
+ case 45 : /* fall through */
+ case 46 : /* fall through */
+ case 47 :
+ if ((entire_insn & 0xf8000000) == 0x98000000)
+ { itype = ARC700F_INSN_LDW_S_X_ABU; goto extract_sfmt_ldw_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 48 : /* fall through */
+ case 49 : /* fall through */
+ case 50 : /* fall through */
+ case 51 : /* fall through */
+ case 52 : /* fall through */
+ case 53 : /* fall through */
+ case 54 : /* fall through */
+ case 55 : /* fall through */
+ case 56 : /* fall through */
+ case 57 : /* fall through */
+ case 58 : /* fall through */
+ case 59 : /* fall through */
+ case 60 : /* fall through */
+ case 61 : /* fall through */
+ case 62 : /* fall through */
+ case 63 :
+ if ((entire_insn & 0xf8e00000) == 0xb8400000)
+ { itype = ARC700F_INSN_ASR_S_SSB; goto extract_sfmt_sub_s_ssb; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 864 : /* fall through */
+ case 865 : /* fall through */
+ case 866 : /* fall through */
+ case 867 : /* fall through */
+ case 868 : /* fall through */
+ case 869 : /* fall through */
+ case 870 : /* fall through */
+ case 871 : /* fall through */
+ case 872 : /* fall through */
+ case 873 : /* fall through */
+ case 874 : /* fall through */
+ case 875 : /* fall through */
+ case 876 : /* fall through */
+ case 877 : /* fall through */
+ case 878 : /* fall through */
+ case 879 : /* fall through */
+ case 880 : /* fall through */
+ case 881 : /* fall through */
+ case 882 : /* fall through */
+ case 883 : /* fall through */
+ case 884 : /* fall through */
+ case 885 : /* fall through */
+ case 886 : /* fall through */
+ case 887 : /* fall through */
+ case 888 : /* fall through */
+ case 889 : /* fall through */
+ case 890 : /* fall through */
+ case 891 : /* fall through */
+ case 892 : /* fall through */
+ case 893 : /* fall through */
+ case 894 : /* fall through */
+ case 895 :
+ {
+ unsigned int val = (((insn >> 26) & (1 << 5)) | ((insn >> 25) & (1 << 4)) | ((insn >> 1) & (15 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf800001f) == 0x18000000)
+ { itype = ARC700F_INSN_ST_ABS; goto extract_sfmt_st_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf800001f) == 0x18000002)
+ { itype = ARC700F_INSN_STB_ABS; goto extract_sfmt_stb_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf800001f) == 0x18000004)
+ { itype = ARC700F_INSN_STW_ABS; goto extract_sfmt_stw_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xf800001f) == 0x18000008)
+ { itype = ARC700F_INSN_ST__AW_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xf800001f) == 0x1800000a)
+ { itype = ARC700F_INSN_STB__AW_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 :
+ if ((entire_insn & 0xf800001f) == 0x1800000c)
+ { itype = ARC700F_INSN_STW__AW_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 :
+ if ((entire_insn & 0xf800001f) == 0x18000010)
+ { itype = ARC700F_INSN_ST_AB_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 9 :
+ if ((entire_insn & 0xf800001f) == 0x18000012)
+ { itype = ARC700F_INSN_STB_AB_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 10 :
+ if ((entire_insn & 0xf800001f) == 0x18000014)
+ { itype = ARC700F_INSN_STW_AB_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 :
+ if ((entire_insn & 0xf800001f) == 0x18000018)
+ { itype = ARC700F_INSN_ST_AS_ABS; goto extract_sfmt_st_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 13 :
+ if ((entire_insn & 0xf800001f) == 0x1800001a)
+ { itype = ARC700F_INSN_STB_AS_ABS; goto extract_sfmt_stb_as_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 14 :
+ if ((entire_insn & 0xf800001f) == 0x1800001c)
+ { itype = ARC700F_INSN_STW_AS_ABS; goto extract_sfmt_stw_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 32 : /* fall through */
+ case 33 : /* fall through */
+ case 34 : /* fall through */
+ case 35 : /* fall through */
+ case 36 : /* fall through */
+ case 37 : /* fall through */
+ case 38 : /* fall through */
+ case 39 : /* fall through */
+ case 40 : /* fall through */
+ case 41 : /* fall through */
+ case 42 : /* fall through */
+ case 43 : /* fall through */
+ case 44 : /* fall through */
+ case 45 : /* fall through */
+ case 46 : /* fall through */
+ case 47 :
+ if ((entire_insn & 0xf8000000) == 0x98000000)
+ { itype = ARC700F_INSN_LDW_S_X_ABU; goto extract_sfmt_ldw_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 48 : /* fall through */
+ case 49 : /* fall through */
+ case 50 : /* fall through */
+ case 51 : /* fall through */
+ case 52 : /* fall through */
+ case 53 : /* fall through */
+ case 54 : /* fall through */
+ case 55 : /* fall through */
+ case 56 : /* fall through */
+ case 57 : /* fall through */
+ case 58 : /* fall through */
+ case 59 : /* fall through */
+ case 60 : /* fall through */
+ case 61 : /* fall through */
+ case 62 : /* fall through */
+ case 63 :
+ if ((entire_insn & 0xf8e00000) == 0xb8600000)
+ { itype = ARC700F_INSN_SUB_S_SSB; goto extract_sfmt_sub_s_ssb; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 896 : /* fall through */
+ case 897 : /* fall through */
+ case 898 : /* fall through */
+ case 899 : /* fall through */
+ case 900 : /* fall through */
+ case 901 : /* fall through */
+ case 902 : /* fall through */
+ case 903 : /* fall through */
+ case 904 : /* fall through */
+ case 905 : /* fall through */
+ case 906 : /* fall through */
+ case 907 : /* fall through */
+ case 908 : /* fall through */
+ case 909 : /* fall through */
+ case 910 : /* fall through */
+ case 911 : /* fall through */
+ case 912 : /* fall through */
+ case 913 : /* fall through */
+ case 914 : /* fall through */
+ case 915 : /* fall through */
+ case 916 : /* fall through */
+ case 917 : /* fall through */
+ case 918 : /* fall through */
+ case 919 : /* fall through */
+ case 920 : /* fall through */
+ case 921 : /* fall through */
+ case 922 : /* fall through */
+ case 923 : /* fall through */
+ case 924 : /* fall through */
+ case 925 : /* fall through */
+ case 926 : /* fall through */
+ case 927 :
+ {
+ unsigned int val = (((insn >> 26) & (1 << 5)) | ((insn >> 25) & (1 << 4)) | ((insn >> 1) & (15 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf800001f) == 0x18000000)
+ { itype = ARC700F_INSN_ST_ABS; goto extract_sfmt_st_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf800001f) == 0x18000002)
+ { itype = ARC700F_INSN_STB_ABS; goto extract_sfmt_stb_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf800001f) == 0x18000004)
+ { itype = ARC700F_INSN_STW_ABS; goto extract_sfmt_stw_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xf800001f) == 0x18000008)
+ { itype = ARC700F_INSN_ST__AW_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xf800001f) == 0x1800000a)
+ { itype = ARC700F_INSN_STB__AW_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 :
+ if ((entire_insn & 0xf800001f) == 0x1800000c)
+ { itype = ARC700F_INSN_STW__AW_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 :
+ if ((entire_insn & 0xf800001f) == 0x18000010)
+ { itype = ARC700F_INSN_ST_AB_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 9 :
+ if ((entire_insn & 0xf800001f) == 0x18000012)
+ { itype = ARC700F_INSN_STB_AB_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 10 :
+ if ((entire_insn & 0xf800001f) == 0x18000014)
+ { itype = ARC700F_INSN_STW_AB_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 :
+ if ((entire_insn & 0xf800001f) == 0x18000018)
+ { itype = ARC700F_INSN_ST_AS_ABS; goto extract_sfmt_st_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 13 :
+ if ((entire_insn & 0xf800001f) == 0x1800001a)
+ { itype = ARC700F_INSN_STB_AS_ABS; goto extract_sfmt_stb_as_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 14 :
+ if ((entire_insn & 0xf800001f) == 0x1800001c)
+ { itype = ARC700F_INSN_STW_AS_ABS; goto extract_sfmt_stw_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 32 : /* fall through */
+ case 33 : /* fall through */
+ case 34 : /* fall through */
+ case 35 : /* fall through */
+ case 36 : /* fall through */
+ case 37 : /* fall through */
+ case 38 : /* fall through */
+ case 39 : /* fall through */
+ case 40 : /* fall through */
+ case 41 : /* fall through */
+ case 42 : /* fall through */
+ case 43 : /* fall through */
+ case 44 : /* fall through */
+ case 45 : /* fall through */
+ case 46 : /* fall through */
+ case 47 :
+ if ((entire_insn & 0xf8000000) == 0x98000000)
+ { itype = ARC700F_INSN_LDW_S_X_ABU; goto extract_sfmt_ldw_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 48 : /* fall through */
+ case 49 : /* fall through */
+ case 50 : /* fall through */
+ case 51 : /* fall through */
+ case 52 : /* fall through */
+ case 53 : /* fall through */
+ case 54 : /* fall through */
+ case 55 : /* fall through */
+ case 56 : /* fall through */
+ case 57 : /* fall through */
+ case 58 : /* fall through */
+ case 59 : /* fall through */
+ case 60 : /* fall through */
+ case 61 : /* fall through */
+ case 62 : /* fall through */
+ case 63 :
+ if ((entire_insn & 0xf8e00000) == 0xb8800000)
+ { itype = ARC700F_INSN_BSET_S_SSB; goto extract_sfmt_sub_s_ssb; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 928 : /* fall through */
+ case 929 : /* fall through */
+ case 930 : /* fall through */
+ case 931 : /* fall through */
+ case 932 : /* fall through */
+ case 933 : /* fall through */
+ case 934 : /* fall through */
+ case 935 : /* fall through */
+ case 936 : /* fall through */
+ case 937 : /* fall through */
+ case 938 : /* fall through */
+ case 939 : /* fall through */
+ case 940 : /* fall through */
+ case 941 : /* fall through */
+ case 942 : /* fall through */
+ case 943 : /* fall through */
+ case 944 : /* fall through */
+ case 945 : /* fall through */
+ case 946 : /* fall through */
+ case 947 : /* fall through */
+ case 948 : /* fall through */
+ case 949 : /* fall through */
+ case 950 : /* fall through */
+ case 951 : /* fall through */
+ case 952 : /* fall through */
+ case 953 : /* fall through */
+ case 954 : /* fall through */
+ case 955 : /* fall through */
+ case 956 : /* fall through */
+ case 957 : /* fall through */
+ case 958 : /* fall through */
+ case 959 :
+ {
+ unsigned int val = (((insn >> 26) & (1 << 5)) | ((insn >> 25) & (1 << 4)) | ((insn >> 1) & (15 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf800001f) == 0x18000000)
+ { itype = ARC700F_INSN_ST_ABS; goto extract_sfmt_st_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf800001f) == 0x18000002)
+ { itype = ARC700F_INSN_STB_ABS; goto extract_sfmt_stb_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf800001f) == 0x18000004)
+ { itype = ARC700F_INSN_STW_ABS; goto extract_sfmt_stw_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xf800001f) == 0x18000008)
+ { itype = ARC700F_INSN_ST__AW_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xf800001f) == 0x1800000a)
+ { itype = ARC700F_INSN_STB__AW_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 :
+ if ((entire_insn & 0xf800001f) == 0x1800000c)
+ { itype = ARC700F_INSN_STW__AW_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 :
+ if ((entire_insn & 0xf800001f) == 0x18000010)
+ { itype = ARC700F_INSN_ST_AB_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 9 :
+ if ((entire_insn & 0xf800001f) == 0x18000012)
+ { itype = ARC700F_INSN_STB_AB_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 10 :
+ if ((entire_insn & 0xf800001f) == 0x18000014)
+ { itype = ARC700F_INSN_STW_AB_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 :
+ if ((entire_insn & 0xf800001f) == 0x18000018)
+ { itype = ARC700F_INSN_ST_AS_ABS; goto extract_sfmt_st_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 13 :
+ if ((entire_insn & 0xf800001f) == 0x1800001a)
+ { itype = ARC700F_INSN_STB_AS_ABS; goto extract_sfmt_stb_as_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 14 :
+ if ((entire_insn & 0xf800001f) == 0x1800001c)
+ { itype = ARC700F_INSN_STW_AS_ABS; goto extract_sfmt_stw_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 32 : /* fall through */
+ case 33 : /* fall through */
+ case 34 : /* fall through */
+ case 35 : /* fall through */
+ case 36 : /* fall through */
+ case 37 : /* fall through */
+ case 38 : /* fall through */
+ case 39 : /* fall through */
+ case 40 : /* fall through */
+ case 41 : /* fall through */
+ case 42 : /* fall through */
+ case 43 : /* fall through */
+ case 44 : /* fall through */
+ case 45 : /* fall through */
+ case 46 : /* fall through */
+ case 47 :
+ if ((entire_insn & 0xf8000000) == 0x98000000)
+ { itype = ARC700F_INSN_LDW_S_X_ABU; goto extract_sfmt_ldw_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 48 : /* fall through */
+ case 49 : /* fall through */
+ case 50 : /* fall through */
+ case 51 : /* fall through */
+ case 52 : /* fall through */
+ case 53 : /* fall through */
+ case 54 : /* fall through */
+ case 55 : /* fall through */
+ case 56 : /* fall through */
+ case 57 : /* fall through */
+ case 58 : /* fall through */
+ case 59 : /* fall through */
+ case 60 : /* fall through */
+ case 61 : /* fall through */
+ case 62 : /* fall through */
+ case 63 :
+ if ((entire_insn & 0xf8e00000) == 0xb8a00000)
+ { itype = ARC700F_INSN_BCLR_S_SSB; goto extract_sfmt_sub_s_ssb; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 960 : /* fall through */
+ case 961 : /* fall through */
+ case 962 : /* fall through */
+ case 963 : /* fall through */
+ case 964 : /* fall through */
+ case 965 : /* fall through */
+ case 966 : /* fall through */
+ case 967 : /* fall through */
+ case 968 : /* fall through */
+ case 969 : /* fall through */
+ case 970 : /* fall through */
+ case 971 : /* fall through */
+ case 972 : /* fall through */
+ case 973 : /* fall through */
+ case 974 : /* fall through */
+ case 975 : /* fall through */
+ case 976 : /* fall through */
+ case 977 : /* fall through */
+ case 978 : /* fall through */
+ case 979 : /* fall through */
+ case 980 : /* fall through */
+ case 981 : /* fall through */
+ case 982 : /* fall through */
+ case 983 : /* fall through */
+ case 984 : /* fall through */
+ case 985 : /* fall through */
+ case 986 : /* fall through */
+ case 987 : /* fall through */
+ case 988 : /* fall through */
+ case 989 : /* fall through */
+ case 990 : /* fall through */
+ case 991 :
+ {
+ unsigned int val = (((insn >> 26) & (1 << 5)) | ((insn >> 25) & (1 << 4)) | ((insn >> 1) & (15 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf800001f) == 0x18000000)
+ { itype = ARC700F_INSN_ST_ABS; goto extract_sfmt_st_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf800001f) == 0x18000002)
+ { itype = ARC700F_INSN_STB_ABS; goto extract_sfmt_stb_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf800001f) == 0x18000004)
+ { itype = ARC700F_INSN_STW_ABS; goto extract_sfmt_stw_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xf800001f) == 0x18000008)
+ { itype = ARC700F_INSN_ST__AW_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xf800001f) == 0x1800000a)
+ { itype = ARC700F_INSN_STB__AW_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 :
+ if ((entire_insn & 0xf800001f) == 0x1800000c)
+ { itype = ARC700F_INSN_STW__AW_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 :
+ if ((entire_insn & 0xf800001f) == 0x18000010)
+ { itype = ARC700F_INSN_ST_AB_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 9 :
+ if ((entire_insn & 0xf800001f) == 0x18000012)
+ { itype = ARC700F_INSN_STB_AB_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 10 :
+ if ((entire_insn & 0xf800001f) == 0x18000014)
+ { itype = ARC700F_INSN_STW_AB_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 :
+ if ((entire_insn & 0xf800001f) == 0x18000018)
+ { itype = ARC700F_INSN_ST_AS_ABS; goto extract_sfmt_st_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 13 :
+ if ((entire_insn & 0xf800001f) == 0x1800001a)
+ { itype = ARC700F_INSN_STB_AS_ABS; goto extract_sfmt_stb_as_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 14 :
+ if ((entire_insn & 0xf800001f) == 0x1800001c)
+ { itype = ARC700F_INSN_STW_AS_ABS; goto extract_sfmt_stw_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 32 : /* fall through */
+ case 33 : /* fall through */
+ case 34 : /* fall through */
+ case 35 : /* fall through */
+ case 36 : /* fall through */
+ case 37 : /* fall through */
+ case 38 : /* fall through */
+ case 39 : /* fall through */
+ case 40 : /* fall through */
+ case 41 : /* fall through */
+ case 42 : /* fall through */
+ case 43 : /* fall through */
+ case 44 : /* fall through */
+ case 45 : /* fall through */
+ case 46 : /* fall through */
+ case 47 :
+ if ((entire_insn & 0xf8000000) == 0x98000000)
+ { itype = ARC700F_INSN_LDW_S_X_ABU; goto extract_sfmt_ldw_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 48 : /* fall through */
+ case 49 : /* fall through */
+ case 50 : /* fall through */
+ case 51 : /* fall through */
+ case 52 : /* fall through */
+ case 53 : /* fall through */
+ case 54 : /* fall through */
+ case 55 : /* fall through */
+ case 56 : /* fall through */
+ case 57 : /* fall through */
+ case 58 : /* fall through */
+ case 59 : /* fall through */
+ case 60 : /* fall through */
+ case 61 : /* fall through */
+ case 62 : /* fall through */
+ case 63 :
+ if ((entire_insn & 0xf8e00000) == 0xb8c00000)
+ { itype = ARC700F_INSN_BMSK_S_SSB; goto extract_sfmt_sub_s_ssb; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 992 : /* fall through */
+ case 993 : /* fall through */
+ case 994 : /* fall through */
+ case 995 : /* fall through */
+ case 996 : /* fall through */
+ case 997 : /* fall through */
+ case 998 : /* fall through */
+ case 999 : /* fall through */
+ case 1000 : /* fall through */
+ case 1001 : /* fall through */
+ case 1002 : /* fall through */
+ case 1003 : /* fall through */
+ case 1004 : /* fall through */
+ case 1005 : /* fall through */
+ case 1006 : /* fall through */
+ case 1007 : /* fall through */
+ case 1008 : /* fall through */
+ case 1009 : /* fall through */
+ case 1010 : /* fall through */
+ case 1011 : /* fall through */
+ case 1012 : /* fall through */
+ case 1013 : /* fall through */
+ case 1014 : /* fall through */
+ case 1015 : /* fall through */
+ case 1016 : /* fall through */
+ case 1017 : /* fall through */
+ case 1018 : /* fall through */
+ case 1019 : /* fall through */
+ case 1020 : /* fall through */
+ case 1021 : /* fall through */
+ case 1022 : /* fall through */
+ case 1023 :
+ {
+ unsigned int val = (((insn >> 26) & (1 << 5)) | ((insn >> 25) & (1 << 4)) | ((insn >> 1) & (15 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf800001f) == 0x18000000)
+ { itype = ARC700F_INSN_ST_ABS; goto extract_sfmt_st_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf800001f) == 0x18000002)
+ { itype = ARC700F_INSN_STB_ABS; goto extract_sfmt_stb_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf800001f) == 0x18000004)
+ { itype = ARC700F_INSN_STW_ABS; goto extract_sfmt_stw_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xf800001f) == 0x18000008)
+ { itype = ARC700F_INSN_ST__AW_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xf800001f) == 0x1800000a)
+ { itype = ARC700F_INSN_STB__AW_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 :
+ if ((entire_insn & 0xf800001f) == 0x1800000c)
+ { itype = ARC700F_INSN_STW__AW_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 :
+ if ((entire_insn & 0xf800001f) == 0x18000010)
+ { itype = ARC700F_INSN_ST_AB_ABS; goto extract_sfmt_st__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 9 :
+ if ((entire_insn & 0xf800001f) == 0x18000012)
+ { itype = ARC700F_INSN_STB_AB_ABS; goto extract_sfmt_stb__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 10 :
+ if ((entire_insn & 0xf800001f) == 0x18000014)
+ { itype = ARC700F_INSN_STW_AB_ABS; goto extract_sfmt_stw__AW_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 :
+ if ((entire_insn & 0xf800001f) == 0x18000018)
+ { itype = ARC700F_INSN_ST_AS_ABS; goto extract_sfmt_st_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 13 :
+ if ((entire_insn & 0xf800001f) == 0x1800001a)
+ { itype = ARC700F_INSN_STB_AS_ABS; goto extract_sfmt_stb_as_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 14 :
+ if ((entire_insn & 0xf800001f) == 0x1800001c)
+ { itype = ARC700F_INSN_STW_AS_ABS; goto extract_sfmt_stw_abs; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 32 : /* fall through */
+ case 33 : /* fall through */
+ case 34 : /* fall through */
+ case 35 : /* fall through */
+ case 36 : /* fall through */
+ case 37 : /* fall through */
+ case 38 : /* fall through */
+ case 39 : /* fall through */
+ case 40 : /* fall through */
+ case 41 : /* fall through */
+ case 42 : /* fall through */
+ case 43 : /* fall through */
+ case 44 : /* fall through */
+ case 45 : /* fall through */
+ case 46 : /* fall through */
+ case 47 :
+ if ((entire_insn & 0xf8000000) == 0x98000000)
+ { itype = ARC700F_INSN_LDW_S_X_ABU; goto extract_sfmt_ldw_s_abu; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 48 : /* fall through */
+ case 49 : /* fall through */
+ case 50 : /* fall through */
+ case 51 : /* fall through */
+ case 52 : /* fall through */
+ case 53 : /* fall through */
+ case 54 : /* fall through */
+ case 55 : /* fall through */
+ case 56 : /* fall through */
+ case 57 : /* fall through */
+ case 58 : /* fall through */
+ case 59 : /* fall through */
+ case 60 : /* fall through */
+ case 61 : /* fall through */
+ case 62 : /* fall through */
+ case 63 :
+ if ((entire_insn & 0xf8e00000) == 0xb8e00000)
+ { itype = ARC700F_INSN_BTST_S_SSB; goto extract_sfmt_btst_s_ssb; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1024 : /* fall through */
+ case 1025 : /* fall through */
+ case 1026 : /* fall through */
+ case 1027 : /* fall through */
+ case 1028 : /* fall through */
+ case 1029 : /* fall through */
+ case 1030 : /* fall through */
+ case 1031 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60000000)
+ { itype = ARC700F_INSN_LD_S_ABC; goto extract_sfmt_ld_s_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0000000)
+ { itype = ARC700F_INSN_LD_S_ABSP; goto extract_sfmt_ld_s_absp; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = ARC700F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1032 : /* fall through */
+ case 1033 : /* fall through */
+ case 1034 : /* fall through */
+ case 1035 : /* fall through */
+ case 1036 : /* fall through */
+ case 1037 : /* fall through */
+ case 1038 : /* fall through */
+ case 1039 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60080000)
+ { itype = ARC700F_INSN_LDB_S_ABC; goto extract_sfmt_ldb_s_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0000000)
+ { itype = ARC700F_INSN_LD_S_ABSP; goto extract_sfmt_ld_s_absp; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = ARC700F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1040 : /* fall through */
+ case 1041 : /* fall through */
+ case 1042 : /* fall through */
+ case 1043 : /* fall through */
+ case 1044 : /* fall through */
+ case 1045 : /* fall through */
+ case 1046 : /* fall through */
+ case 1047 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60100000)
+ { itype = ARC700F_INSN_LDW_S_ABC; goto extract_sfmt_ldw_s_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0000000)
+ { itype = ARC700F_INSN_LD_S_ABSP; goto extract_sfmt_ld_s_absp; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = ARC700F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1048 : /* fall through */
+ case 1049 : /* fall through */
+ case 1050 : /* fall through */
+ case 1051 : /* fall through */
+ case 1052 : /* fall through */
+ case 1053 : /* fall through */
+ case 1054 : /* fall through */
+ case 1055 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60180000)
+ { itype = ARC700F_INSN_ADD_S_ABC; goto extract_sfmt_add_s_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0000000)
+ { itype = ARC700F_INSN_LD_S_ABSP; goto extract_sfmt_ld_s_absp; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = ARC700F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1056 : /* fall through */
+ case 1057 : /* fall through */
+ case 1058 : /* fall through */
+ case 1059 : /* fall through */
+ case 1060 : /* fall through */
+ case 1061 : /* fall through */
+ case 1062 : /* fall through */
+ case 1063 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60000000)
+ { itype = ARC700F_INSN_LD_S_ABC; goto extract_sfmt_ld_s_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0200000)
+ { itype = ARC700F_INSN_LDB_S_ABSP; goto extract_sfmt_ldb_s_absp; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = ARC700F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1064 : /* fall through */
+ case 1065 : /* fall through */
+ case 1066 : /* fall through */
+ case 1067 : /* fall through */
+ case 1068 : /* fall through */
+ case 1069 : /* fall through */
+ case 1070 : /* fall through */
+ case 1071 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60080000)
+ { itype = ARC700F_INSN_LDB_S_ABC; goto extract_sfmt_ldb_s_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0200000)
+ { itype = ARC700F_INSN_LDB_S_ABSP; goto extract_sfmt_ldb_s_absp; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = ARC700F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1072 : /* fall through */
+ case 1073 : /* fall through */
+ case 1074 : /* fall through */
+ case 1075 : /* fall through */
+ case 1076 : /* fall through */
+ case 1077 : /* fall through */
+ case 1078 : /* fall through */
+ case 1079 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60100000)
+ { itype = ARC700F_INSN_LDW_S_ABC; goto extract_sfmt_ldw_s_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0200000)
+ { itype = ARC700F_INSN_LDB_S_ABSP; goto extract_sfmt_ldb_s_absp; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = ARC700F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1080 : /* fall through */
+ case 1081 : /* fall through */
+ case 1082 : /* fall through */
+ case 1083 : /* fall through */
+ case 1084 : /* fall through */
+ case 1085 : /* fall through */
+ case 1086 : /* fall through */
+ case 1087 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60180000)
+ { itype = ARC700F_INSN_ADD_S_ABC; goto extract_sfmt_add_s_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0200000)
+ { itype = ARC700F_INSN_LDB_S_ABSP; goto extract_sfmt_ldb_s_absp; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = ARC700F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1088 : /* fall through */
+ case 1089 : /* fall through */
+ case 1090 : /* fall through */
+ case 1091 : /* fall through */
+ case 1092 : /* fall through */
+ case 1093 : /* fall through */
+ case 1094 : /* fall through */
+ case 1095 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60000000)
+ { itype = ARC700F_INSN_LD_S_ABC; goto extract_sfmt_ld_s_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0400000)
+ { itype = ARC700F_INSN_ST_S_ABSP; goto extract_sfmt_st_s_absp; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = ARC700F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1096 : /* fall through */
+ case 1097 : /* fall through */
+ case 1098 : /* fall through */
+ case 1099 : /* fall through */
+ case 1100 : /* fall through */
+ case 1101 : /* fall through */
+ case 1102 : /* fall through */
+ case 1103 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60080000)
+ { itype = ARC700F_INSN_LDB_S_ABC; goto extract_sfmt_ldb_s_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0400000)
+ { itype = ARC700F_INSN_ST_S_ABSP; goto extract_sfmt_st_s_absp; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = ARC700F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1104 : /* fall through */
+ case 1105 : /* fall through */
+ case 1106 : /* fall through */
+ case 1107 : /* fall through */
+ case 1108 : /* fall through */
+ case 1109 : /* fall through */
+ case 1110 : /* fall through */
+ case 1111 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60100000)
+ { itype = ARC700F_INSN_LDW_S_ABC; goto extract_sfmt_ldw_s_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0400000)
+ { itype = ARC700F_INSN_ST_S_ABSP; goto extract_sfmt_st_s_absp; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = ARC700F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1112 : /* fall through */
+ case 1113 : /* fall through */
+ case 1114 : /* fall through */
+ case 1115 : /* fall through */
+ case 1116 : /* fall through */
+ case 1117 : /* fall through */
+ case 1118 : /* fall through */
+ case 1119 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60180000)
+ { itype = ARC700F_INSN_ADD_S_ABC; goto extract_sfmt_add_s_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0400000)
+ { itype = ARC700F_INSN_ST_S_ABSP; goto extract_sfmt_st_s_absp; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = ARC700F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1120 : /* fall through */
+ case 1121 : /* fall through */
+ case 1122 : /* fall through */
+ case 1123 : /* fall through */
+ case 1124 : /* fall through */
+ case 1125 : /* fall through */
+ case 1126 : /* fall through */
+ case 1127 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60000000)
+ { itype = ARC700F_INSN_LD_S_ABC; goto extract_sfmt_ld_s_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0600000)
+ { itype = ARC700F_INSN_STB_S_ABSP; goto extract_sfmt_stb_s_absp; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = ARC700F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1128 : /* fall through */
+ case 1129 : /* fall through */
+ case 1130 : /* fall through */
+ case 1131 : /* fall through */
+ case 1132 : /* fall through */
+ case 1133 : /* fall through */
+ case 1134 : /* fall through */
+ case 1135 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60080000)
+ { itype = ARC700F_INSN_LDB_S_ABC; goto extract_sfmt_ldb_s_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0600000)
+ { itype = ARC700F_INSN_STB_S_ABSP; goto extract_sfmt_stb_s_absp; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = ARC700F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1136 : /* fall through */
+ case 1137 : /* fall through */
+ case 1138 : /* fall through */
+ case 1139 : /* fall through */
+ case 1140 : /* fall through */
+ case 1141 : /* fall through */
+ case 1142 : /* fall through */
+ case 1143 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60100000)
+ { itype = ARC700F_INSN_LDW_S_ABC; goto extract_sfmt_ldw_s_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0600000)
+ { itype = ARC700F_INSN_STB_S_ABSP; goto extract_sfmt_stb_s_absp; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = ARC700F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1144 : /* fall through */
+ case 1145 : /* fall through */
+ case 1146 : /* fall through */
+ case 1147 : /* fall through */
+ case 1148 : /* fall through */
+ case 1149 : /* fall through */
+ case 1150 : /* fall through */
+ case 1151 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60180000)
+ { itype = ARC700F_INSN_ADD_S_ABC; goto extract_sfmt_add_s_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0600000)
+ { itype = ARC700F_INSN_STB_S_ABSP; goto extract_sfmt_stb_s_absp; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0000000)
+ { itype = ARC700F_INSN_ADD_S_R_U7; goto extract_sfmt_add_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1152 : /* fall through */
+ case 1153 : /* fall through */
+ case 1154 : /* fall through */
+ case 1155 : /* fall through */
+ case 1156 : /* fall through */
+ case 1157 : /* fall through */
+ case 1158 : /* fall through */
+ case 1159 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60000000)
+ { itype = ARC700F_INSN_LD_S_ABC; goto extract_sfmt_ld_s_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0800000)
+ { itype = ARC700F_INSN_ADD_S_ABSP; goto extract_sfmt_add_s_absp; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = ARC700F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1160 : /* fall through */
+ case 1161 : /* fall through */
+ case 1162 : /* fall through */
+ case 1163 : /* fall through */
+ case 1164 : /* fall through */
+ case 1165 : /* fall through */
+ case 1166 : /* fall through */
+ case 1167 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60080000)
+ { itype = ARC700F_INSN_LDB_S_ABC; goto extract_sfmt_ldb_s_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0800000)
+ { itype = ARC700F_INSN_ADD_S_ABSP; goto extract_sfmt_add_s_absp; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = ARC700F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1168 : /* fall through */
+ case 1169 : /* fall through */
+ case 1170 : /* fall through */
+ case 1171 : /* fall through */
+ case 1172 : /* fall through */
+ case 1173 : /* fall through */
+ case 1174 : /* fall through */
+ case 1175 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60100000)
+ { itype = ARC700F_INSN_LDW_S_ABC; goto extract_sfmt_ldw_s_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0800000)
+ { itype = ARC700F_INSN_ADD_S_ABSP; goto extract_sfmt_add_s_absp; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = ARC700F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1176 : /* fall through */
+ case 1177 : /* fall through */
+ case 1178 : /* fall through */
+ case 1179 : /* fall through */
+ case 1180 : /* fall through */
+ case 1181 : /* fall through */
+ case 1182 : /* fall through */
+ case 1183 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60180000)
+ { itype = ARC700F_INSN_ADD_S_ABC; goto extract_sfmt_add_s_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8e00000) == 0xc0800000)
+ { itype = ARC700F_INSN_ADD_S_ABSP; goto extract_sfmt_add_s_absp; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = ARC700F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1184 : /* fall through */
+ case 1185 : /* fall through */
+ case 1186 : /* fall through */
+ case 1187 : /* fall through */
+ case 1188 : /* fall through */
+ case 1189 : /* fall through */
+ case 1190 : /* fall through */
+ case 1191 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 24) & (1 << 0)));
+ switch (val)
+ {
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8180000) == 0x60000000)
+ { itype = ARC700F_INSN_LD_S_ABC; goto extract_sfmt_ld_s_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xffe00000) == 0xc0a00000)
+ { itype = ARC700F_INSN_ADD_S_ASSPSP; goto extract_sfmt_add_s_asspsp; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xffe00000) == 0xc1a00000)
+ { itype = ARC700F_INSN_SUB_S_ASSPSP; goto extract_sfmt_add_s_asspsp; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = ARC700F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1192 : /* fall through */
+ case 1193 : /* fall through */
+ case 1194 : /* fall through */
+ case 1195 : /* fall through */
+ case 1196 : /* fall through */
+ case 1197 : /* fall through */
+ case 1198 : /* fall through */
+ case 1199 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 24) & (1 << 0)));
+ switch (val)
+ {
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8180000) == 0x60080000)
+ { itype = ARC700F_INSN_LDB_S_ABC; goto extract_sfmt_ldb_s_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xffe00000) == 0xc0a00000)
+ { itype = ARC700F_INSN_ADD_S_ASSPSP; goto extract_sfmt_add_s_asspsp; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xffe00000) == 0xc1a00000)
+ { itype = ARC700F_INSN_SUB_S_ASSPSP; goto extract_sfmt_add_s_asspsp; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = ARC700F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1200 : /* fall through */
+ case 1201 : /* fall through */
+ case 1202 : /* fall through */
+ case 1203 : /* fall through */
+ case 1204 : /* fall through */
+ case 1205 : /* fall through */
+ case 1206 : /* fall through */
+ case 1207 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 24) & (1 << 0)));
+ switch (val)
+ {
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8180000) == 0x60100000)
+ { itype = ARC700F_INSN_LDW_S_ABC; goto extract_sfmt_ldw_s_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xffe00000) == 0xc0a00000)
+ { itype = ARC700F_INSN_ADD_S_ASSPSP; goto extract_sfmt_add_s_asspsp; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xffe00000) == 0xc1a00000)
+ { itype = ARC700F_INSN_SUB_S_ASSPSP; goto extract_sfmt_add_s_asspsp; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = ARC700F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1208 : /* fall through */
+ case 1209 : /* fall through */
+ case 1210 : /* fall through */
+ case 1211 : /* fall through */
+ case 1212 : /* fall through */
+ case 1213 : /* fall through */
+ case 1214 : /* fall through */
+ case 1215 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 2)) | ((insn >> 28) & (1 << 1)) | ((insn >> 24) & (1 << 0)));
+ switch (val)
+ {
+ case 2 : /* fall through */
+ case 3 :
+ if ((entire_insn & 0xf8180000) == 0x60180000)
+ { itype = ARC700F_INSN_ADD_S_ABC; goto extract_sfmt_add_s_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xffe00000) == 0xc0a00000)
+ { itype = ARC700F_INSN_ADD_S_ASSPSP; goto extract_sfmt_add_s_asspsp; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xffe00000) == 0xc1a00000)
+ { itype = ARC700F_INSN_SUB_S_ASSPSP; goto extract_sfmt_add_s_asspsp; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = ARC700F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1216 : /* fall through */
+ case 1218 : /* fall through */
+ case 1219 : /* fall through */
+ case 1220 : /* fall through */
+ case 1221 : /* fall through */
+ case 1222 : /* fall through */
+ case 1223 : /* fall through */
+ case 1248 : /* fall through */
+ case 1250 : /* fall through */
+ case 1251 : /* fall through */
+ case 1252 : /* fall through */
+ case 1253 : /* fall through */
+ case 1254 : /* fall through */
+ case 1255 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8180000) == 0x60000000)
+ { itype = ARC700F_INSN_LD_S_ABC; goto extract_sfmt_ld_s_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = ARC700F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1217 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60000000)
+ { itype = ARC700F_INSN_LD_S_ABC; goto extract_sfmt_ld_s_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0000) == 0xc0c10000)
+ { itype = ARC700F_INSN_POP_S_B; goto extract_sfmt_pop_s_b; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = ARC700F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1224 : /* fall through */
+ case 1225 : /* fall through */
+ case 1226 : /* fall through */
+ case 1227 : /* fall through */
+ case 1228 : /* fall through */
+ case 1229 : /* fall through */
+ case 1230 : /* fall through */
+ case 1231 : /* fall through */
+ case 1256 : /* fall through */
+ case 1257 : /* fall through */
+ case 1258 : /* fall through */
+ case 1259 : /* fall through */
+ case 1260 : /* fall through */
+ case 1261 : /* fall through */
+ case 1262 : /* fall through */
+ case 1263 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8180000) == 0x60080000)
+ { itype = ARC700F_INSN_LDB_S_ABC; goto extract_sfmt_ldb_s_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = ARC700F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1232 : /* fall through */
+ case 1234 : /* fall through */
+ case 1235 : /* fall through */
+ case 1236 : /* fall through */
+ case 1237 : /* fall through */
+ case 1238 : /* fall through */
+ case 1239 : /* fall through */
+ case 1264 : /* fall through */
+ case 1266 : /* fall through */
+ case 1267 : /* fall through */
+ case 1268 : /* fall through */
+ case 1269 : /* fall through */
+ case 1270 : /* fall through */
+ case 1271 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8180000) == 0x60100000)
+ { itype = ARC700F_INSN_LDW_S_ABC; goto extract_sfmt_ldw_s_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = ARC700F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1233 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60100000)
+ { itype = ARC700F_INSN_LDW_S_ABC; goto extract_sfmt_ldw_s_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xffff0000) == 0xc0d10000)
+ { itype = ARC700F_INSN_POP_S_BLINK; goto extract_sfmt_pop_s_blink; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = ARC700F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1240 : /* fall through */
+ case 1241 : /* fall through */
+ case 1242 : /* fall through */
+ case 1243 : /* fall through */
+ case 1244 : /* fall through */
+ case 1245 : /* fall through */
+ case 1246 : /* fall through */
+ case 1247 : /* fall through */
+ case 1272 : /* fall through */
+ case 1273 : /* fall through */
+ case 1274 : /* fall through */
+ case 1275 : /* fall through */
+ case 1276 : /* fall through */
+ case 1277 : /* fall through */
+ case 1278 : /* fall through */
+ case 1279 :
+ {
+ unsigned int val = (((insn >> 31) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8180000) == 0x60180000)
+ { itype = ARC700F_INSN_ADD_S_ABC; goto extract_sfmt_add_s_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = ARC700F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1249 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60000000)
+ { itype = ARC700F_INSN_LD_S_ABC; goto extract_sfmt_ld_s_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8ff0000) == 0xc0e10000)
+ { itype = ARC700F_INSN_PUSH_S_B; goto extract_sfmt_push_s_b; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = ARC700F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1265 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x60100000)
+ { itype = ARC700F_INSN_LDW_S_ABC; goto extract_sfmt_ldw_s_abc; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xffff0000) == 0xc0f10000)
+ { itype = ARC700F_INSN_PUSH_S_BLINK; goto extract_sfmt_push_s_blink; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8800000) == 0xe0800000)
+ { itype = ARC700F_INSN_CMP_S_R_U7; goto extract_sfmt_cmp_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1280 : /* fall through */
+ case 1281 : /* fall through */
+ case 1282 : /* fall through */
+ case 1283 : /* fall through */
+ case 1284 : /* fall through */
+ case 1285 : /* fall through */
+ case 1286 : /* fall through */
+ case 1287 : /* fall through */
+ case 1312 : /* fall through */
+ case 1313 : /* fall through */
+ case 1314 : /* fall through */
+ case 1315 : /* fall through */
+ case 1316 : /* fall through */
+ case 1317 : /* fall through */
+ case 1318 : /* fall through */
+ case 1319 : /* fall through */
+ case 1344 : /* fall through */
+ case 1345 : /* fall through */
+ case 1346 : /* fall through */
+ case 1347 : /* fall through */
+ case 1348 : /* fall through */
+ case 1349 : /* fall through */
+ case 1350 : /* fall through */
+ case 1351 : /* fall through */
+ case 1376 : /* fall through */
+ case 1377 : /* fall through */
+ case 1378 : /* fall through */
+ case 1379 : /* fall through */
+ case 1380 : /* fall through */
+ case 1381 : /* fall through */
+ case 1382 : /* fall through */
+ case 1383 : /* fall through */
+ case 1408 : /* fall through */
+ case 1409 : /* fall through */
+ case 1410 : /* fall through */
+ case 1411 : /* fall through */
+ case 1412 : /* fall through */
+ case 1413 : /* fall through */
+ case 1414 : /* fall through */
+ case 1415 : /* fall through */
+ case 1440 : /* fall through */
+ case 1441 : /* fall through */
+ case 1442 : /* fall through */
+ case 1443 : /* fall through */
+ case 1444 : /* fall through */
+ case 1445 : /* fall through */
+ case 1446 : /* fall through */
+ case 1447 : /* fall through */
+ case 1472 : /* fall through */
+ case 1473 : /* fall through */
+ case 1474 : /* fall through */
+ case 1475 : /* fall through */
+ case 1476 : /* fall through */
+ case 1477 : /* fall through */
+ case 1478 : /* fall through */
+ case 1479 : /* fall through */
+ case 1504 : /* fall through */
+ case 1505 : /* fall through */
+ case 1506 : /* fall through */
+ case 1507 : /* fall through */
+ case 1508 : /* fall through */
+ case 1509 : /* fall through */
+ case 1510 : /* fall through */
+ case 1511 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 25) & (3 << 0)));
+ switch (val)
+ {
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8180000) == 0x68000000)
+ { itype = ARC700F_INSN_ADD_S_CBU3; goto extract_sfmt_add_s_cbu3; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 :
+ if ((entire_insn & 0xfe000000) == 0xc8000000)
+ { itype = ARC700F_INSN_LD_S_GPREL; goto extract_sfmt_ld_s_gprel; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 9 :
+ if ((entire_insn & 0xfe000000) == 0xca000000)
+ { itype = ARC700F_INSN_LDB_S_GPREL; goto extract_sfmt_ldb_s_gprel; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 10 :
+ if ((entire_insn & 0xfe000000) == 0xcc000000)
+ { itype = ARC700F_INSN_LDW_S_GPREL; goto extract_sfmt_ldw_s_gprel; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 11 :
+ if ((entire_insn & 0xfe000000) == 0xce000000)
+ { itype = ARC700F_INSN_ADD_S_GP; goto extract_sfmt_add_s_gp; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xe8000000)
+ { itype = ARC700F_INSN_BRCC_S; goto extract_sfmt_brcc_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1288 : /* fall through */
+ case 1289 : /* fall through */
+ case 1290 : /* fall through */
+ case 1291 : /* fall through */
+ case 1292 : /* fall through */
+ case 1293 : /* fall through */
+ case 1294 : /* fall through */
+ case 1295 : /* fall through */
+ case 1320 : /* fall through */
+ case 1321 : /* fall through */
+ case 1322 : /* fall through */
+ case 1323 : /* fall through */
+ case 1324 : /* fall through */
+ case 1325 : /* fall through */
+ case 1326 : /* fall through */
+ case 1327 : /* fall through */
+ case 1352 : /* fall through */
+ case 1353 : /* fall through */
+ case 1354 : /* fall through */
+ case 1355 : /* fall through */
+ case 1356 : /* fall through */
+ case 1357 : /* fall through */
+ case 1358 : /* fall through */
+ case 1359 : /* fall through */
+ case 1384 : /* fall through */
+ case 1385 : /* fall through */
+ case 1386 : /* fall through */
+ case 1387 : /* fall through */
+ case 1388 : /* fall through */
+ case 1389 : /* fall through */
+ case 1390 : /* fall through */
+ case 1391 : /* fall through */
+ case 1416 : /* fall through */
+ case 1417 : /* fall through */
+ case 1418 : /* fall through */
+ case 1419 : /* fall through */
+ case 1420 : /* fall through */
+ case 1421 : /* fall through */
+ case 1422 : /* fall through */
+ case 1423 : /* fall through */
+ case 1448 : /* fall through */
+ case 1449 : /* fall through */
+ case 1450 : /* fall through */
+ case 1451 : /* fall through */
+ case 1452 : /* fall through */
+ case 1453 : /* fall through */
+ case 1454 : /* fall through */
+ case 1455 : /* fall through */
+ case 1480 : /* fall through */
+ case 1481 : /* fall through */
+ case 1482 : /* fall through */
+ case 1483 : /* fall through */
+ case 1484 : /* fall through */
+ case 1485 : /* fall through */
+ case 1486 : /* fall through */
+ case 1487 : /* fall through */
+ case 1512 : /* fall through */
+ case 1513 : /* fall through */
+ case 1514 : /* fall through */
+ case 1515 : /* fall through */
+ case 1516 : /* fall through */
+ case 1517 : /* fall through */
+ case 1518 : /* fall through */
+ case 1519 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 25) & (3 << 0)));
+ switch (val)
+ {
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8180000) == 0x68080000)
+ { itype = ARC700F_INSN_SUB_S_CBU3; goto extract_sfmt_add_s_cbu3; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 :
+ if ((entire_insn & 0xfe000000) == 0xc8000000)
+ { itype = ARC700F_INSN_LD_S_GPREL; goto extract_sfmt_ld_s_gprel; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 9 :
+ if ((entire_insn & 0xfe000000) == 0xca000000)
+ { itype = ARC700F_INSN_LDB_S_GPREL; goto extract_sfmt_ldb_s_gprel; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 10 :
+ if ((entire_insn & 0xfe000000) == 0xcc000000)
+ { itype = ARC700F_INSN_LDW_S_GPREL; goto extract_sfmt_ldw_s_gprel; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 11 :
+ if ((entire_insn & 0xfe000000) == 0xce000000)
+ { itype = ARC700F_INSN_ADD_S_GP; goto extract_sfmt_add_s_gp; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xe8000000)
+ { itype = ARC700F_INSN_BRCC_S; goto extract_sfmt_brcc_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1296 : /* fall through */
+ case 1297 : /* fall through */
+ case 1298 : /* fall through */
+ case 1299 : /* fall through */
+ case 1300 : /* fall through */
+ case 1301 : /* fall through */
+ case 1302 : /* fall through */
+ case 1303 : /* fall through */
+ case 1328 : /* fall through */
+ case 1329 : /* fall through */
+ case 1330 : /* fall through */
+ case 1331 : /* fall through */
+ case 1332 : /* fall through */
+ case 1333 : /* fall through */
+ case 1334 : /* fall through */
+ case 1335 : /* fall through */
+ case 1360 : /* fall through */
+ case 1361 : /* fall through */
+ case 1362 : /* fall through */
+ case 1363 : /* fall through */
+ case 1364 : /* fall through */
+ case 1365 : /* fall through */
+ case 1366 : /* fall through */
+ case 1367 : /* fall through */
+ case 1392 : /* fall through */
+ case 1393 : /* fall through */
+ case 1394 : /* fall through */
+ case 1395 : /* fall through */
+ case 1396 : /* fall through */
+ case 1397 : /* fall through */
+ case 1398 : /* fall through */
+ case 1399 : /* fall through */
+ case 1424 : /* fall through */
+ case 1425 : /* fall through */
+ case 1426 : /* fall through */
+ case 1427 : /* fall through */
+ case 1428 : /* fall through */
+ case 1429 : /* fall through */
+ case 1430 : /* fall through */
+ case 1431 : /* fall through */
+ case 1456 : /* fall through */
+ case 1457 : /* fall through */
+ case 1458 : /* fall through */
+ case 1459 : /* fall through */
+ case 1460 : /* fall through */
+ case 1461 : /* fall through */
+ case 1462 : /* fall through */
+ case 1463 : /* fall through */
+ case 1488 : /* fall through */
+ case 1489 : /* fall through */
+ case 1490 : /* fall through */
+ case 1491 : /* fall through */
+ case 1492 : /* fall through */
+ case 1493 : /* fall through */
+ case 1494 : /* fall through */
+ case 1495 : /* fall through */
+ case 1520 : /* fall through */
+ case 1521 : /* fall through */
+ case 1522 : /* fall through */
+ case 1523 : /* fall through */
+ case 1524 : /* fall through */
+ case 1525 : /* fall through */
+ case 1526 : /* fall through */
+ case 1527 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 25) & (3 << 0)));
+ switch (val)
+ {
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8180000) == 0x68100000)
+ { itype = ARC700F_INSN_ASL_S_CBU3; goto extract_sfmt_add_s_cbu3; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 :
+ if ((entire_insn & 0xfe000000) == 0xc8000000)
+ { itype = ARC700F_INSN_LD_S_GPREL; goto extract_sfmt_ld_s_gprel; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 9 :
+ if ((entire_insn & 0xfe000000) == 0xca000000)
+ { itype = ARC700F_INSN_LDB_S_GPREL; goto extract_sfmt_ldb_s_gprel; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 10 :
+ if ((entire_insn & 0xfe000000) == 0xcc000000)
+ { itype = ARC700F_INSN_LDW_S_GPREL; goto extract_sfmt_ldw_s_gprel; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 11 :
+ if ((entire_insn & 0xfe000000) == 0xce000000)
+ { itype = ARC700F_INSN_ADD_S_GP; goto extract_sfmt_add_s_gp; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xe8000000)
+ { itype = ARC700F_INSN_BRCC_S; goto extract_sfmt_brcc_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1304 : /* fall through */
+ case 1305 : /* fall through */
+ case 1306 : /* fall through */
+ case 1307 : /* fall through */
+ case 1308 : /* fall through */
+ case 1309 : /* fall through */
+ case 1310 : /* fall through */
+ case 1311 : /* fall through */
+ case 1336 : /* fall through */
+ case 1337 : /* fall through */
+ case 1338 : /* fall through */
+ case 1339 : /* fall through */
+ case 1340 : /* fall through */
+ case 1341 : /* fall through */
+ case 1342 : /* fall through */
+ case 1343 : /* fall through */
+ case 1368 : /* fall through */
+ case 1369 : /* fall through */
+ case 1370 : /* fall through */
+ case 1371 : /* fall through */
+ case 1372 : /* fall through */
+ case 1373 : /* fall through */
+ case 1374 : /* fall through */
+ case 1375 : /* fall through */
+ case 1400 : /* fall through */
+ case 1401 : /* fall through */
+ case 1402 : /* fall through */
+ case 1403 : /* fall through */
+ case 1404 : /* fall through */
+ case 1405 : /* fall through */
+ case 1406 : /* fall through */
+ case 1407 : /* fall through */
+ case 1432 : /* fall through */
+ case 1433 : /* fall through */
+ case 1434 : /* fall through */
+ case 1435 : /* fall through */
+ case 1436 : /* fall through */
+ case 1437 : /* fall through */
+ case 1438 : /* fall through */
+ case 1439 : /* fall through */
+ case 1464 : /* fall through */
+ case 1465 : /* fall through */
+ case 1466 : /* fall through */
+ case 1467 : /* fall through */
+ case 1468 : /* fall through */
+ case 1469 : /* fall through */
+ case 1470 : /* fall through */
+ case 1471 : /* fall through */
+ case 1496 : /* fall through */
+ case 1497 : /* fall through */
+ case 1498 : /* fall through */
+ case 1499 : /* fall through */
+ case 1500 : /* fall through */
+ case 1501 : /* fall through */
+ case 1502 : /* fall through */
+ case 1503 : /* fall through */
+ case 1528 : /* fall through */
+ case 1529 : /* fall through */
+ case 1530 : /* fall through */
+ case 1531 : /* fall through */
+ case 1532 : /* fall through */
+ case 1533 : /* fall through */
+ case 1534 : /* fall through */
+ case 1535 :
+ {
+ unsigned int val = (((insn >> 28) & (1 << 3)) | ((insn >> 27) & (1 << 2)) | ((insn >> 25) & (3 << 0)));
+ switch (val)
+ {
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 :
+ if ((entire_insn & 0xf8180000) == 0x68180000)
+ { itype = ARC700F_INSN_ASR_S_CBU3; goto extract_sfmt_add_s_cbu3; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 8 :
+ if ((entire_insn & 0xfe000000) == 0xc8000000)
+ { itype = ARC700F_INSN_LD_S_GPREL; goto extract_sfmt_ld_s_gprel; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 9 :
+ if ((entire_insn & 0xfe000000) == 0xca000000)
+ { itype = ARC700F_INSN_LDB_S_GPREL; goto extract_sfmt_ldb_s_gprel; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 10 :
+ if ((entire_insn & 0xfe000000) == 0xcc000000)
+ { itype = ARC700F_INSN_LDW_S_GPREL; goto extract_sfmt_ldw_s_gprel; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 11 :
+ if ((entire_insn & 0xfe000000) == 0xce000000)
+ { itype = ARC700F_INSN_ADD_S_GP; goto extract_sfmt_add_s_gp; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ if ((entire_insn & 0xf8000000) == 0xe8000000)
+ { itype = ARC700F_INSN_BRCC_S; goto extract_sfmt_brcc_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1536 : /* fall through */
+ case 1537 : /* fall through */
+ case 1538 : /* fall through */
+ case 1539 : /* fall through */
+ case 1540 : /* fall through */
+ case 1541 : /* fall through */
+ case 1542 : /* fall through */
+ case 1543 : /* fall through */
+ case 1568 : /* fall through */
+ case 1569 : /* fall through */
+ case 1570 : /* fall through */
+ case 1571 : /* fall through */
+ case 1572 : /* fall through */
+ case 1573 : /* fall through */
+ case 1574 : /* fall through */
+ case 1575 : /* fall through */
+ case 1600 : /* fall through */
+ case 1601 : /* fall through */
+ case 1602 : /* fall through */
+ case 1603 : /* fall through */
+ case 1604 : /* fall through */
+ case 1605 : /* fall through */
+ case 1606 : /* fall through */
+ case 1607 : /* fall through */
+ case 1632 : /* fall through */
+ case 1633 : /* fall through */
+ case 1634 : /* fall through */
+ case 1635 : /* fall through */
+ case 1636 : /* fall through */
+ case 1637 : /* fall through */
+ case 1638 : /* fall through */
+ case 1639 : /* fall through */
+ case 1664 : /* fall through */
+ case 1665 : /* fall through */
+ case 1666 : /* fall through */
+ case 1667 : /* fall through */
+ case 1668 : /* fall through */
+ case 1669 : /* fall through */
+ case 1670 : /* fall through */
+ case 1671 : /* fall through */
+ case 1696 : /* fall through */
+ case 1697 : /* fall through */
+ case 1698 : /* fall through */
+ case 1699 : /* fall through */
+ case 1700 : /* fall through */
+ case 1701 : /* fall through */
+ case 1702 : /* fall through */
+ case 1703 : /* fall through */
+ case 1728 : /* fall through */
+ case 1729 : /* fall through */
+ case 1730 : /* fall through */
+ case 1731 : /* fall through */
+ case 1732 : /* fall through */
+ case 1733 : /* fall through */
+ case 1734 : /* fall through */
+ case 1735 : /* fall through */
+ case 1760 : /* fall through */
+ case 1761 : /* fall through */
+ case 1762 : /* fall through */
+ case 1763 : /* fall through */
+ case 1764 : /* fall through */
+ case 1765 : /* fall through */
+ case 1766 : /* fall through */
+ case 1767 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x70000000)
+ { itype = ARC700F_INSN_ADD_S_MCAH; goto extract_sfmt_add_s_mcah; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd0000000)
+ { itype = ARC700F_INSN_LD_S_PCREL; goto extract_sfmt_ld_s_pcrel; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ {
+ unsigned int val = (((insn >> 25) & (3 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xf0000000)
+ { itype = ARC700F_INSN_B_S; goto extract_sfmt_b_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xfe000000) == 0xf6000000)
+ { itype = ARC700F_INSN_BCC_S; goto extract_sfmt_bcc_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1544 : /* fall through */
+ case 1545 : /* fall through */
+ case 1546 : /* fall through */
+ case 1547 : /* fall through */
+ case 1548 : /* fall through */
+ case 1549 : /* fall through */
+ case 1550 : /* fall through */
+ case 1551 : /* fall through */
+ case 1576 : /* fall through */
+ case 1577 : /* fall through */
+ case 1578 : /* fall through */
+ case 1579 : /* fall through */
+ case 1580 : /* fall through */
+ case 1581 : /* fall through */
+ case 1582 : /* fall through */
+ case 1583 : /* fall through */
+ case 1608 : /* fall through */
+ case 1609 : /* fall through */
+ case 1610 : /* fall through */
+ case 1611 : /* fall through */
+ case 1612 : /* fall through */
+ case 1613 : /* fall through */
+ case 1614 : /* fall through */
+ case 1615 : /* fall through */
+ case 1640 : /* fall through */
+ case 1641 : /* fall through */
+ case 1642 : /* fall through */
+ case 1643 : /* fall through */
+ case 1644 : /* fall through */
+ case 1645 : /* fall through */
+ case 1646 : /* fall through */
+ case 1647 : /* fall through */
+ case 1672 : /* fall through */
+ case 1673 : /* fall through */
+ case 1674 : /* fall through */
+ case 1675 : /* fall through */
+ case 1676 : /* fall through */
+ case 1677 : /* fall through */
+ case 1678 : /* fall through */
+ case 1679 : /* fall through */
+ case 1704 : /* fall through */
+ case 1705 : /* fall through */
+ case 1706 : /* fall through */
+ case 1707 : /* fall through */
+ case 1708 : /* fall through */
+ case 1709 : /* fall through */
+ case 1710 : /* fall through */
+ case 1711 : /* fall through */
+ case 1736 : /* fall through */
+ case 1737 : /* fall through */
+ case 1738 : /* fall through */
+ case 1739 : /* fall through */
+ case 1740 : /* fall through */
+ case 1741 : /* fall through */
+ case 1742 : /* fall through */
+ case 1743 : /* fall through */
+ case 1768 : /* fall through */
+ case 1769 : /* fall through */
+ case 1770 : /* fall through */
+ case 1771 : /* fall through */
+ case 1772 : /* fall through */
+ case 1773 : /* fall through */
+ case 1774 : /* fall through */
+ case 1775 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x70080000)
+ { itype = ARC700F_INSN_MOV_S_MCAH; goto extract_sfmt_mov_s_mcah; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd0000000)
+ { itype = ARC700F_INSN_LD_S_PCREL; goto extract_sfmt_ld_s_pcrel; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ {
+ unsigned int val = (((insn >> 25) & (3 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xf0000000)
+ { itype = ARC700F_INSN_B_S; goto extract_sfmt_b_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xfe000000) == 0xf6000000)
+ { itype = ARC700F_INSN_BCC_S; goto extract_sfmt_bcc_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1552 : /* fall through */
+ case 1553 : /* fall through */
+ case 1554 : /* fall through */
+ case 1555 : /* fall through */
+ case 1556 : /* fall through */
+ case 1557 : /* fall through */
+ case 1558 : /* fall through */
+ case 1559 : /* fall through */
+ case 1584 : /* fall through */
+ case 1585 : /* fall through */
+ case 1586 : /* fall through */
+ case 1587 : /* fall through */
+ case 1588 : /* fall through */
+ case 1589 : /* fall through */
+ case 1590 : /* fall through */
+ case 1591 : /* fall through */
+ case 1616 : /* fall through */
+ case 1617 : /* fall through */
+ case 1618 : /* fall through */
+ case 1619 : /* fall through */
+ case 1620 : /* fall through */
+ case 1621 : /* fall through */
+ case 1622 : /* fall through */
+ case 1623 : /* fall through */
+ case 1648 : /* fall through */
+ case 1649 : /* fall through */
+ case 1650 : /* fall through */
+ case 1651 : /* fall through */
+ case 1652 : /* fall through */
+ case 1653 : /* fall through */
+ case 1654 : /* fall through */
+ case 1655 : /* fall through */
+ case 1680 : /* fall through */
+ case 1681 : /* fall through */
+ case 1682 : /* fall through */
+ case 1683 : /* fall through */
+ case 1684 : /* fall through */
+ case 1685 : /* fall through */
+ case 1686 : /* fall through */
+ case 1687 : /* fall through */
+ case 1712 : /* fall through */
+ case 1713 : /* fall through */
+ case 1714 : /* fall through */
+ case 1715 : /* fall through */
+ case 1716 : /* fall through */
+ case 1717 : /* fall through */
+ case 1718 : /* fall through */
+ case 1719 : /* fall through */
+ case 1744 : /* fall through */
+ case 1745 : /* fall through */
+ case 1746 : /* fall through */
+ case 1747 : /* fall through */
+ case 1748 : /* fall through */
+ case 1749 : /* fall through */
+ case 1750 : /* fall through */
+ case 1751 : /* fall through */
+ case 1776 : /* fall through */
+ case 1777 : /* fall through */
+ case 1778 : /* fall through */
+ case 1779 : /* fall through */
+ case 1780 : /* fall through */
+ case 1781 : /* fall through */
+ case 1782 : /* fall through */
+ case 1783 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x70100000)
+ { itype = ARC700F_INSN_CMP_S_MCAH; goto extract_sfmt_cmp_s_mcah; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd0000000)
+ { itype = ARC700F_INSN_LD_S_PCREL; goto extract_sfmt_ld_s_pcrel; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ {
+ unsigned int val = (((insn >> 25) & (3 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xf0000000)
+ { itype = ARC700F_INSN_B_S; goto extract_sfmt_b_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xfe000000) == 0xf6000000)
+ { itype = ARC700F_INSN_BCC_S; goto extract_sfmt_bcc_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1560 : /* fall through */
+ case 1561 : /* fall through */
+ case 1562 : /* fall through */
+ case 1563 : /* fall through */
+ case 1564 : /* fall through */
+ case 1565 : /* fall through */
+ case 1566 : /* fall through */
+ case 1567 : /* fall through */
+ case 1592 : /* fall through */
+ case 1593 : /* fall through */
+ case 1594 : /* fall through */
+ case 1595 : /* fall through */
+ case 1596 : /* fall through */
+ case 1597 : /* fall through */
+ case 1598 : /* fall through */
+ case 1599 : /* fall through */
+ case 1624 : /* fall through */
+ case 1625 : /* fall through */
+ case 1626 : /* fall through */
+ case 1627 : /* fall through */
+ case 1628 : /* fall through */
+ case 1629 : /* fall through */
+ case 1630 : /* fall through */
+ case 1631 : /* fall through */
+ case 1656 : /* fall through */
+ case 1657 : /* fall through */
+ case 1658 : /* fall through */
+ case 1659 : /* fall through */
+ case 1660 : /* fall through */
+ case 1661 : /* fall through */
+ case 1662 : /* fall through */
+ case 1663 : /* fall through */
+ case 1688 : /* fall through */
+ case 1689 : /* fall through */
+ case 1690 : /* fall through */
+ case 1691 : /* fall through */
+ case 1692 : /* fall through */
+ case 1693 : /* fall through */
+ case 1694 : /* fall through */
+ case 1695 : /* fall through */
+ case 1720 : /* fall through */
+ case 1721 : /* fall through */
+ case 1722 : /* fall through */
+ case 1723 : /* fall through */
+ case 1724 : /* fall through */
+ case 1725 : /* fall through */
+ case 1726 : /* fall through */
+ case 1727 : /* fall through */
+ case 1752 : /* fall through */
+ case 1753 : /* fall through */
+ case 1754 : /* fall through */
+ case 1755 : /* fall through */
+ case 1756 : /* fall through */
+ case 1757 : /* fall through */
+ case 1758 : /* fall through */
+ case 1759 : /* fall through */
+ case 1784 : /* fall through */
+ case 1785 : /* fall through */
+ case 1786 : /* fall through */
+ case 1787 : /* fall through */
+ case 1788 : /* fall through */
+ case 1789 : /* fall through */
+ case 1790 : /* fall through */
+ case 1791 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8180000) == 0x70180000)
+ { itype = ARC700F_INSN_MOV_S_MCAHB; goto extract_sfmt_mov_s_mcahb; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd0000000)
+ { itype = ARC700F_INSN_LD_S_PCREL; goto extract_sfmt_ld_s_pcrel; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ {
+ unsigned int val = (((insn >> 25) & (3 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xf0000000)
+ { itype = ARC700F_INSN_B_S; goto extract_sfmt_b_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xfe000000) == 0xf6000000)
+ { itype = ARC700F_INSN_BCC_S; goto extract_sfmt_bcc_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1792 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8ff0000) == 0x78000000)
+ { itype = ARC700F_INSN_J_S; goto extract_sfmt_j_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC700F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC700F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1793 : /* fall through */
+ case 1795 : /* fall through */
+ case 1800 : /* fall through */
+ case 1801 : /* fall through */
+ case 1802 : /* fall through */
+ case 1815 : /* fall through */
+ case 1823 : /* fall through */
+ case 1825 : /* fall through */
+ case 1827 : /* fall through */
+ case 1832 : /* fall through */
+ case 1833 : /* fall through */
+ case 1834 : /* fall through */
+ case 1847 : /* fall through */
+ case 1855 : /* fall through */
+ case 1857 : /* fall through */
+ case 1859 : /* fall through */
+ case 1864 : /* fall through */
+ case 1865 : /* fall through */
+ case 1866 : /* fall through */
+ case 1879 : /* fall through */
+ case 1887 : /* fall through */
+ case 1889 : /* fall through */
+ case 1891 : /* fall through */
+ case 1896 : /* fall through */
+ case 1897 : /* fall through */
+ case 1898 : /* fall through */
+ case 1911 : /* fall through */
+ case 1919 : /* fall through */
+ case 1920 : /* fall through */
+ case 1921 : /* fall through */
+ case 1923 : /* fall through */
+ case 1928 : /* fall through */
+ case 1929 : /* fall through */
+ case 1930 : /* fall through */
+ case 1943 : /* fall through */
+ case 1951 : /* fall through */
+ case 1952 : /* fall through */
+ case 1953 : /* fall through */
+ case 1955 : /* fall through */
+ case 1960 : /* fall through */
+ case 1961 : /* fall through */
+ case 1962 : /* fall through */
+ case 1975 : /* fall through */
+ case 1983 : /* fall through */
+ case 1985 : /* fall through */
+ case 1987 : /* fall through */
+ case 1992 : /* fall through */
+ case 1993 : /* fall through */
+ case 1994 : /* fall through */
+ case 2007 : /* fall through */
+ case 2015 : /* fall through */
+ case 2017 : /* fall through */
+ case 2019 : /* fall through */
+ case 2024 : /* fall through */
+ case 2025 : /* fall through */
+ case 2026 : /* fall through */
+ case 2039 :
+ {
+ unsigned int val = (((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC700F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC700F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1794 : /* fall through */
+ case 1826 : /* fall through */
+ case 1858 : /* fall through */
+ case 1890 : /* fall through */
+ case 1922 : /* fall through */
+ case 1954 : /* fall through */
+ case 1986 : /* fall through */
+ case 2018 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x78020000)
+ { itype = ARC700F_INSN_I16_GO_SUB_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC700F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC700F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1796 : /* fall through */
+ case 1828 : /* fall through */
+ case 1860 : /* fall through */
+ case 1892 : /* fall through */
+ case 1924 : /* fall through */
+ case 1956 : /* fall through */
+ case 1988 : /* fall through */
+ case 2020 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x78040000)
+ { itype = ARC700F_INSN_I16_GO_AND_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC700F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC700F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1797 : /* fall through */
+ case 1829 : /* fall through */
+ case 1861 : /* fall through */
+ case 1893 : /* fall through */
+ case 1925 : /* fall through */
+ case 1957 : /* fall through */
+ case 1989 : /* fall through */
+ case 2021 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x78050000)
+ { itype = ARC700F_INSN_I16_GO_OR_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC700F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC700F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1798 : /* fall through */
+ case 1830 : /* fall through */
+ case 1862 : /* fall through */
+ case 1894 : /* fall through */
+ case 1926 : /* fall through */
+ case 1958 : /* fall through */
+ case 1990 : /* fall through */
+ case 2022 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x78060000)
+ { itype = ARC700F_INSN_I16_GO_BIC_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC700F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC700F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1799 : /* fall through */
+ case 1831 : /* fall through */
+ case 1863 : /* fall through */
+ case 1895 : /* fall through */
+ case 1927 : /* fall through */
+ case 1959 : /* fall through */
+ case 1991 : /* fall through */
+ case 2023 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x78070000)
+ { itype = ARC700F_INSN_I16_GO_XOR_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC700F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC700F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1803 : /* fall through */
+ case 1835 : /* fall through */
+ case 1867 : /* fall through */
+ case 1899 : /* fall through */
+ case 1931 : /* fall through */
+ case 1963 : /* fall through */
+ case 1995 : /* fall through */
+ case 2027 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x780b0000)
+ { itype = ARC700F_INSN_TST_S_GO; goto extract_sfmt_tst_s_go; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC700F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC700F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1804 : /* fall through */
+ case 1836 : /* fall through */
+ case 1868 : /* fall through */
+ case 1900 : /* fall through */
+ case 1932 : /* fall through */
+ case 1964 : /* fall through */
+ case 1996 : /* fall through */
+ case 2028 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x780c0000)
+ { itype = ARC700F_INSN_MUL64_S_GO; goto extract_sfmt_mul64_s_go; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC700F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC700F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1805 : /* fall through */
+ case 1837 : /* fall through */
+ case 1869 : /* fall through */
+ case 1901 : /* fall through */
+ case 1933 : /* fall through */
+ case 1965 : /* fall through */
+ case 1997 : /* fall through */
+ case 2029 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x780d0000)
+ { itype = ARC700F_INSN_I16_GO_SEXB_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC700F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC700F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1806 : /* fall through */
+ case 1838 : /* fall through */
+ case 1870 : /* fall through */
+ case 1902 : /* fall through */
+ case 1934 : /* fall through */
+ case 1966 : /* fall through */
+ case 1998 : /* fall through */
+ case 2030 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x780e0000)
+ { itype = ARC700F_INSN_I16_GO_SEXW_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC700F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC700F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1807 : /* fall through */
+ case 1839 : /* fall through */
+ case 1871 : /* fall through */
+ case 1903 : /* fall through */
+ case 1935 : /* fall through */
+ case 1967 : /* fall through */
+ case 1999 : /* fall through */
+ case 2031 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x780f0000)
+ { itype = ARC700F_INSN_I16_GO_EXTB_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC700F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC700F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1808 : /* fall through */
+ case 1840 : /* fall through */
+ case 1872 : /* fall through */
+ case 1904 : /* fall through */
+ case 1936 : /* fall through */
+ case 1968 : /* fall through */
+ case 2000 : /* fall through */
+ case 2032 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x78100000)
+ { itype = ARC700F_INSN_I16_GO_EXTW_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC700F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC700F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1809 : /* fall through */
+ case 1841 : /* fall through */
+ case 1873 : /* fall through */
+ case 1905 : /* fall through */
+ case 1937 : /* fall through */
+ case 1969 : /* fall through */
+ case 2001 : /* fall through */
+ case 2033 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x78110000)
+ { itype = ARC700F_INSN_I16_GO_ABS_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC700F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC700F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1810 : /* fall through */
+ case 1842 : /* fall through */
+ case 1874 : /* fall through */
+ case 1906 : /* fall through */
+ case 1938 : /* fall through */
+ case 1970 : /* fall through */
+ case 2002 : /* fall through */
+ case 2034 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x78120000)
+ { itype = ARC700F_INSN_I16_GO_NOT_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC700F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC700F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1811 : /* fall through */
+ case 1843 : /* fall through */
+ case 1875 : /* fall through */
+ case 1907 : /* fall through */
+ case 1939 : /* fall through */
+ case 1971 : /* fall through */
+ case 2003 : /* fall through */
+ case 2035 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x78130000)
+ { itype = ARC700F_INSN_I16_GO_NEG_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC700F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC700F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1812 : /* fall through */
+ case 1844 : /* fall through */
+ case 1876 : /* fall through */
+ case 1908 : /* fall through */
+ case 1940 : /* fall through */
+ case 1972 : /* fall through */
+ case 2004 : /* fall through */
+ case 2036 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x78140000)
+ { itype = ARC700F_INSN_I16_GO_ADD1_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC700F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC700F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1813 : /* fall through */
+ case 1845 : /* fall through */
+ case 1877 : /* fall through */
+ case 1909 : /* fall through */
+ case 1941 : /* fall through */
+ case 1973 : /* fall through */
+ case 2005 : /* fall through */
+ case 2037 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x78150000)
+ { itype = ARC700F_INSN_I16_GO_ADD2_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC700F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC700F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1814 : /* fall through */
+ case 1846 : /* fall through */
+ case 1878 : /* fall through */
+ case 1910 : /* fall through */
+ case 1942 : /* fall through */
+ case 1974 : /* fall through */
+ case 2006 : /* fall through */
+ case 2038 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x78160000)
+ { itype = ARC700F_INSN_I16_GO_ADD3_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC700F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC700F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1816 : /* fall through */
+ case 1848 : /* fall through */
+ case 1880 : /* fall through */
+ case 1912 : /* fall through */
+ case 1944 : /* fall through */
+ case 1976 : /* fall through */
+ case 2008 : /* fall through */
+ case 2040 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x78180000)
+ { itype = ARC700F_INSN_I16_GO_ASLM_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC700F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC700F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1817 : /* fall through */
+ case 1849 : /* fall through */
+ case 1881 : /* fall through */
+ case 1913 : /* fall through */
+ case 1945 : /* fall through */
+ case 1977 : /* fall through */
+ case 2009 : /* fall through */
+ case 2041 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x78190000)
+ { itype = ARC700F_INSN_I16_GO_LSRM_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC700F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC700F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1818 : /* fall through */
+ case 1850 : /* fall through */
+ case 1882 : /* fall through */
+ case 1914 : /* fall through */
+ case 1946 : /* fall through */
+ case 1978 : /* fall through */
+ case 2010 : /* fall through */
+ case 2042 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x781a0000)
+ { itype = ARC700F_INSN_I16_GO_ASRM_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC700F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC700F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1819 : /* fall through */
+ case 1851 : /* fall through */
+ case 1883 : /* fall through */
+ case 1915 : /* fall through */
+ case 1947 : /* fall through */
+ case 1979 : /* fall through */
+ case 2011 : /* fall through */
+ case 2043 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x781b0000)
+ { itype = ARC700F_INSN_I16_GO_ASL_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC700F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC700F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1820 : /* fall through */
+ case 1852 : /* fall through */
+ case 1884 : /* fall through */
+ case 1916 : /* fall through */
+ case 1948 : /* fall through */
+ case 1980 : /* fall through */
+ case 2012 : /* fall through */
+ case 2044 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x781c0000)
+ { itype = ARC700F_INSN_I16_GO_ASR_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC700F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC700F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1821 : /* fall through */
+ case 1853 : /* fall through */
+ case 1885 : /* fall through */
+ case 1917 : /* fall through */
+ case 1949 : /* fall through */
+ case 1981 : /* fall through */
+ case 2013 : /* fall through */
+ case 2045 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x781d0000)
+ { itype = ARC700F_INSN_I16_GO_LSR_S_GO; goto extract_sfmt_I16_GO_SUB_s_go; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC700F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC700F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1822 : /* fall through */
+ case 1854 : /* fall through */
+ case 1886 : /* fall through */
+ case 1918 : /* fall through */
+ case 1950 : /* fall through */
+ case 1982 : /* fall through */
+ case 2014 : /* fall through */
+ case 2046 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf81f0000) == 0x781e0000)
+ { itype = ARC700F_INSN_TRAP_S; goto extract_sfmt_trap_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC700F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC700F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1824 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8ff0000) == 0x78200000)
+ { itype = ARC700F_INSN_J_S_D; goto extract_sfmt_j_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC700F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC700F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1856 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8ff0000) == 0x78400000)
+ { itype = ARC700F_INSN_JL_S; goto extract_sfmt_jl_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC700F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC700F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1888 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8ff0000) == 0x78600000)
+ { itype = ARC700F_INSN_JL_S_D; goto extract_sfmt_jl_s_d; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC700F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC700F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1984 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xf8ff0000) == 0x78c00000)
+ { itype = ARC700F_INSN_SUB_S_GO_SUB_NE; goto extract_sfmt_sub_s_go_sub_ne; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC700F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC700F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 2016 :
+ {
+ unsigned int val = (((insn >> 27) & (1 << 4)) | ((insn >> 26) & (1 << 3)) | ((insn >> 24) & (7 << 0)));
+ switch (val)
+ {
+ case 8 :
+ if ((entire_insn & 0xffff0000) == 0x78e00000)
+ { itype = ARC700F_INSN_NOP_S; goto extract_sfmt_nop_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 9 :
+ if ((entire_insn & 0xffff0000) == 0x79e00000)
+ { itype = ARC700F_INSN_UNIMP_S; goto extract_sfmt_nop_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 :
+ if ((entire_insn & 0xffff0000) == 0x7ce00000)
+ { itype = ARC700F_INSN_J_SEQ__S; goto extract_sfmt_j_seq__S; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 13 :
+ if ((entire_insn & 0xffff0000) == 0x7de00000)
+ { itype = ARC700F_INSN_J_SNE__S; goto extract_sfmt_j_seq__S; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 14 :
+ if ((entire_insn & 0xffff0000) == 0x7ee00000)
+ { itype = ARC700F_INSN_J_S__S; goto extract_sfmt_j_s__S; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 15 :
+ if ((entire_insn & 0xffff0000) == 0x7fe00000)
+ { itype = ARC700F_INSN_J_S__S_D; goto extract_sfmt_j_s__S; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 16 : /* fall through */
+ case 17 : /* fall through */
+ case 18 : /* fall through */
+ case 19 : /* fall through */
+ case 20 : /* fall through */
+ case 21 : /* fall through */
+ case 22 : /* fall through */
+ case 23 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC700F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 24 : /* fall through */
+ case 25 : /* fall through */
+ case 26 : /* fall through */
+ case 27 : /* fall through */
+ case 28 : /* fall through */
+ case 29 : /* fall through */
+ case 30 : /* fall through */
+ case 31 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC700F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 2047 :
+ {
+ unsigned int val = (((insn >> 30) & (1 << 1)) | ((insn >> 29) & (1 << 0)));
+ switch (val)
+ {
+ case 1 :
+ if ((entire_insn & 0xffff0000) == 0x7fff0000)
+ { itype = ARC700F_INSN_BRK_S; goto extract_sfmt_brk; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xf8000000) == 0xd8000000)
+ { itype = ARC700F_INSN_MOV_S_R_U7; goto extract_sfmt_mov_s_r_u7; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xf8000000) == 0xf8000000)
+ { itype = ARC700F_INSN_BL_S; goto extract_sfmt_bl_s; }
+ itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ default : itype = ARC700F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ }
+
+ /* The instruction has been decoded, now extract the fields. */
+
+ extract_sfmt_empty:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_b_s:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_b_s.f
+ UINT f_cond_i2;
+ SI f_rel10;
+
+ f_cond_i2 = EXTRACT_MSB0_UINT (insn, 32, 5, 2);
+ f_rel10 = ((((EXTRACT_MSB0_INT (insn, 32, 7, 9)) << (1))) + (((pc) & (-4))));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_i2) = f_cond_i2;
+ FLD (i_label10) = f_rel10;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_b_s", "f_cond_i2 0x%x", 'x', f_cond_i2, "label10 0x%x", 'x', f_rel10, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_bcc_s:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_bcc_s.f
+ UINT f_cond_i3;
+ SI f_rel7;
+
+ f_cond_i3 = EXTRACT_MSB0_UINT (insn, 32, 7, 3);
+ f_rel7 = ((((EXTRACT_MSB0_INT (insn, 32, 10, 6)) << (1))) + (((pc) & (-4))));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_i3) = f_cond_i3;
+ FLD (i_label7) = f_rel7;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcc_s", "f_cond_i3 0x%x", 'x', f_cond_i3, "label7 0x%x", 'x', f_rel7, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_brcc_s:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_brcc_s.f
+ UINT f_op__b;
+ UINT f_brscond;
+ SI f_rel8;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_brscond = EXTRACT_MSB0_UINT (insn, 32, 8, 1);
+ f_rel8 = ((((EXTRACT_MSB0_INT (insn, 32, 9, 7)) << (1))) + (((pc) & (-4))));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_brscond) = f_brscond;
+ FLD (i_label8) = f_rel8;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_brcc_s", "f_op__b 0x%x", 'x', f_op__b, "f_brscond 0x%x", 'x', f_brscond, "label8 0x%x", 'x', f_rel8, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_bcc_l:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_bcc_l.f
+ UINT f_d21l;
+ INT f_d21h;
+ UINT f_cond_Q;
+ INT f_rel21;
+
+ f_d21l = EXTRACT_MSB0_UINT (insn, 32, 5, 10);
+ f_d21h = EXTRACT_MSB0_INT (insn, 32, 16, 10);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_rel21 = ((((((f_d21l) << (1))) | (((f_d21h) << (11))))) + (((pc) & (-4))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (i_label21) = f_rel21;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcc_l", "f_cond_Q 0x%x", 'x', f_cond_Q, "label21 0x%x", 'x', f_rel21, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_b_l:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_b_l.f
+ UINT f_d21l;
+ UINT f_d25m;
+ INT f_d25h;
+ INT f_rel25;
+
+ f_d21l = EXTRACT_MSB0_UINT (insn, 32, 5, 10);
+ f_d25m = EXTRACT_MSB0_UINT (insn, 32, 16, 10);
+ f_d25h = EXTRACT_MSB0_INT (insn, 32, 28, 4);
+{
+ f_rel25 = ((((((((f_d21l) << (1))) | (((f_d25m) << (11))))) | (((f_d25h) << (21))))) + (((pc) & (-4))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_label25) = f_rel25;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_b_l", "label25 0x%x", 'x', f_rel25, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_brcc_RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_brcc_RC.f
+ UINT f_op__b;
+ UINT f_d9l;
+ INT f_d9h;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_brcond;
+ UINT f_op_B;
+ INT f_rel9;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_d9l = EXTRACT_MSB0_UINT (insn, 32, 8, 7);
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_brcond = EXTRACT_MSB0_UINT (insn, 32, 28, 4);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_rel9 = ((((((f_d9l) << (1))) | (((f_d9h) << (8))))) + (((pc) & (-4))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_brcond) = f_brcond;
+ FLD (i_label9) = f_rel9;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_brcc_RC", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_brcond 0x%x", 'x', f_brcond, "label9 0x%x", 'x', f_rel9, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_brcc_U6:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_brcc_U6.f
+ UINT f_op__b;
+ UINT f_d9l;
+ INT f_d9h;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_brcond;
+ UINT f_op_B;
+ INT f_rel9;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_d9l = EXTRACT_MSB0_UINT (insn, 32, 8, 7);
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_brcond = EXTRACT_MSB0_UINT (insn, 32, 28, 4);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_rel9 = ((((((f_d9l) << (1))) | (((f_d9h) << (8))))) + (((pc) & (-4))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_brcond) = f_brcond;
+ FLD (f_u6) = f_u6;
+ FLD (i_label9) = f_rel9;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_brcc_U6", "f_op_B 0x%x", 'x', f_op_B, "f_brcond 0x%x", 'x', f_brcond, "f_u6 0x%x", 'x', f_u6, "label9 0x%x", 'x', f_rel9, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_bl_s:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_bl_s.f
+ SI f_rel13bl;
+
+ f_rel13bl = ((((EXTRACT_MSB0_INT (insn, 32, 5, 11)) << (2))) + (((pc) & (-4))));
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_label13a) = f_rel13bl;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl_s", "label13a 0x%x", 'x', f_rel13bl, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_blcc:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_blcc.f
+ UINT f_d21bl;
+ INT f_d21h;
+ UINT f_cond_Q;
+ INT f_rel21bl;
+
+ f_d21bl = EXTRACT_MSB0_UINT (insn, 32, 5, 9);
+ f_d21h = EXTRACT_MSB0_INT (insn, 32, 16, 10);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_rel21bl = ((((((f_d21bl) << (2))) | (((f_d21h) << (11))))) + (((pc) & (-4))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (i_label21a) = f_rel21bl;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_blcc", "f_cond_Q 0x%x", 'x', f_cond_Q, "label21a 0x%x", 'x', f_rel21bl, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_bl:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_bl.f
+ UINT f_d21bl;
+ UINT f_d25m;
+ INT f_d25h;
+ INT f_rel25bl;
+
+ f_d21bl = EXTRACT_MSB0_UINT (insn, 32, 5, 9);
+ f_d25m = EXTRACT_MSB0_UINT (insn, 32, 16, 10);
+ f_d25h = EXTRACT_MSB0_INT (insn, 32, 28, 4);
+{
+ f_rel25bl = ((((((((f_d21bl) << (2))) | (((f_d25m) << (11))))) | (((f_d25h) << (21))))) + (((pc) & (-4))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_label25a) = f_rel25bl;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl", "label25a 0x%x", 'x', f_rel25bl, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_bl_d:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_bl.f
+ UINT f_d21bl;
+ UINT f_d25m;
+ INT f_d25h;
+ INT f_rel25bl;
+
+ f_d21bl = EXTRACT_MSB0_UINT (insn, 32, 5, 9);
+ f_d25m = EXTRACT_MSB0_UINT (insn, 32, 16, 10);
+ f_d25h = EXTRACT_MSB0_INT (insn, 32, 28, 4);
+{
+ f_rel25bl = ((((((((f_d21bl) << (2))) | (((f_d25m) << (11))))) | (((f_d25h) << (21))))) + (((pc) & (-4))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_label25a) = f_rel25bl;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl_d", "label25a 0x%x", 'x', f_rel25bl, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ld_abs:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ UINT f_op__b;
+ UINT f_u8;
+ INT f_d9h;
+ UINT f_B_5_3;
+ UINT f_op_A;
+ UINT f_op_B;
+ INT f_s9;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8);
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s9 = ((f_u8) | (((f_d9h) << (8))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s9) = f_s9;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_abs", "f_op_B 0x%x", 'x', f_op_B, "f_s9 0x%x", 'x', f_s9, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ld__AW_abs:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ UINT f_op__b;
+ UINT f_u8;
+ INT f_d9h;
+ UINT f_B_5_3;
+ UINT f_op_A;
+ UINT f_op_B;
+ INT f_s9;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8);
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s9 = ((f_u8) | (((f_d9h) << (8))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s9) = f_s9;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld__AW_abs", "f_op_B 0x%x", 'x', f_op_B, "f_s9 0x%x", 'x', f_s9, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ld_abc:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_abc", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ld__AW_abc:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld__AW_abc", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ld_s_abc:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ UINT f_op__b;
+ UINT f_op__c;
+ UINT f_op__a;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_op__a = EXTRACT_MSB0_UINT (insn, 32, 13, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_op__c) = f_op__c;
+ FLD (f_op__a) = f_op__a;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_s_abc", "f_op__b 0x%x", 'x', f_op__b, "f_op__c 0x%x", 'x', f_op__c, "f_op__a 0x%x", 'x', f_op__a, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ld_s_abu:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ UINT f_op__b;
+ UINT f_op__c;
+ SI f_u5x4;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_u5x4 = ((EXTRACT_MSB0_UINT (insn, 32, 11, 5)) << (2));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_u5x4) = f_u5x4;
+ FLD (f_op__c) = f_op__c;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_s_abu", "f_op__b 0x%x", 'x', f_op__b, "f_u5x4 0x%x", 'x', f_u5x4, "f_op__c 0x%x", 'x', f_op__c, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ld_s_absp:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ UINT f_op__b;
+ SI f_u5x4;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u5x4 = ((EXTRACT_MSB0_UINT (insn, 32, 11, 5)) << (2));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_u5x4) = f_u5x4;
+ FLD (f_op__b) = f_op__b;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_s_absp", "f_u5x4 0x%x", 'x', f_u5x4, "f_op__b 0x%x", 'x', f_op__b, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ld_s_gprel:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_gprel.f
+ SI f_s9x4;
+
+ f_s9x4 = ((EXTRACT_MSB0_INT (insn, 32, 7, 9)) << (2));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_s9x4) = f_s9x4;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_s_gprel", "f_s9x4 0x%x", 'x', f_s9x4, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ld_s_pcrel:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_pcrel.f
+ UINT f_op__b;
+ SI f_u8x4;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u8x4 = ((EXTRACT_MSB0_UINT (insn, 32, 8, 8)) << (2));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_u8x4) = f_u8x4;
+ FLD (f_op__b) = f_op__b;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_s_pcrel", "f_u8x4 0x%x", 'x', f_u8x4, "f_op__b 0x%x", 'x', f_op__b, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldb_abs:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ UINT f_op__b;
+ UINT f_u8;
+ INT f_d9h;
+ UINT f_B_5_3;
+ UINT f_op_A;
+ UINT f_op_B;
+ INT f_s9;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8);
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s9 = ((f_u8) | (((f_d9h) << (8))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s9) = f_s9;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_abs", "f_op_B 0x%x", 'x', f_op_B, "f_s9 0x%x", 'x', f_s9, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldb__AW_abs:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ UINT f_op__b;
+ UINT f_u8;
+ INT f_d9h;
+ UINT f_B_5_3;
+ UINT f_op_A;
+ UINT f_op_B;
+ INT f_s9;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8);
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s9 = ((f_u8) | (((f_d9h) << (8))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s9) = f_s9;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb__AW_abs", "f_op_B 0x%x", 'x', f_op_B, "f_s9 0x%x", 'x', f_s9, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldb_as_abs:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_as_abs", "f_op_B 0x%x", 'x', f_op_B, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldb_abc:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_abc", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldb__AW_abc:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb__AW_abc", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldb_as_abc:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_as_abc", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldb_s_abc:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ UINT f_op__b;
+ UINT f_op__c;
+ UINT f_op__a;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_op__a = EXTRACT_MSB0_UINT (insn, 32, 13, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_op__c) = f_op__c;
+ FLD (f_op__a) = f_op__a;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_s_abc", "f_op__b 0x%x", 'x', f_op__b, "f_op__c 0x%x", 'x', f_op__c, "f_op__a 0x%x", 'x', f_op__a, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldb_s_abu:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ UINT f_op__b;
+ UINT f_op__c;
+ UINT f_u5;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_u5 = EXTRACT_MSB0_UINT (insn, 32, 11, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_u5) = f_u5;
+ FLD (f_op__c) = f_op__c;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_s_abu", "f_op__b 0x%x", 'x', f_op__b, "f_u5 0x%x", 'x', f_u5, "f_op__c 0x%x", 'x', f_op__c, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldb_s_absp:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ UINT f_op__b;
+ SI f_u5x4;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u5x4 = ((EXTRACT_MSB0_UINT (insn, 32, 11, 5)) << (2));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_u5x4) = f_u5x4;
+ FLD (f_op__b) = f_op__b;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_s_absp", "f_u5x4 0x%x", 'x', f_u5x4, "f_op__b 0x%x", 'x', f_op__b, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldb_s_gprel:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ldb_s_gprel.f
+ INT f_s9x1;
+
+ f_s9x1 = EXTRACT_MSB0_INT (insn, 32, 7, 9);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_s9x1) = f_s9x1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_s_gprel", "f_s9x1 0x%x", 'x', f_s9x1, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldw_abs:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ UINT f_op__b;
+ UINT f_u8;
+ INT f_d9h;
+ UINT f_B_5_3;
+ UINT f_op_A;
+ UINT f_op_B;
+ INT f_s9;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8);
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s9 = ((f_u8) | (((f_d9h) << (8))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s9) = f_s9;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldw_abs", "f_op_B 0x%x", 'x', f_op_B, "f_s9 0x%x", 'x', f_s9, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldw__AW_abs:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ UINT f_op__b;
+ UINT f_u8;
+ INT f_d9h;
+ UINT f_B_5_3;
+ UINT f_op_A;
+ UINT f_op_B;
+ INT f_s9;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8);
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s9 = ((f_u8) | (((f_d9h) << (8))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s9) = f_s9;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldw__AW_abs", "f_op_B 0x%x", 'x', f_op_B, "f_s9 0x%x", 'x', f_s9, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldw_abc:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldw_abc", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldw__AW_abc:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldw__AW_abc", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldw_s_abc:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ UINT f_op__b;
+ UINT f_op__c;
+ UINT f_op__a;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_op__a = EXTRACT_MSB0_UINT (insn, 32, 13, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_op__c) = f_op__c;
+ FLD (f_op__a) = f_op__a;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldw_s_abc", "f_op__b 0x%x", 'x', f_op__b, "f_op__c 0x%x", 'x', f_op__c, "f_op__a 0x%x", 'x', f_op__a, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldw_s_abu:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ldw_s_abu.f
+ UINT f_op__b;
+ UINT f_op__c;
+ SI f_u5x2;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_u5x2 = ((EXTRACT_MSB0_UINT (insn, 32, 11, 5)) << (1));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_u5x2) = f_u5x2;
+ FLD (f_op__c) = f_op__c;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldw_s_abu", "f_op__b 0x%x", 'x', f_op__b, "f_u5x2 0x%x", 'x', f_u5x2, "f_op__c 0x%x", 'x', f_op__c, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldw_s_gprel:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ldw_s_gprel.f
+ SI f_s9x2;
+
+ f_s9x2 = ((EXTRACT_MSB0_INT (insn, 32, 7, 9)) << (1));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_s9x2) = f_s9x2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldw_s_gprel", "f_s9x2 0x%x", 'x', f_s9x2, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_st_abs:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_u8;
+ INT f_d9h;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+ INT f_s9;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8);
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s9 = ((f_u8) | (((f_d9h) << (8))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_s9) = f_s9;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_abs", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_s9 0x%x", 'x', f_s9, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_st__AW_abs:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_u8;
+ INT f_d9h;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+ INT f_s9;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8);
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s9 = ((f_u8) | (((f_d9h) << (8))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_s9) = f_s9;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st__AW_abs", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_s9 0x%x", 'x', f_s9, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_st_s_abu:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ UINT f_op__b;
+ UINT f_op__c;
+ SI f_u5x4;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_u5x4 = ((EXTRACT_MSB0_UINT (insn, 32, 11, 5)) << (2));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_op__c) = f_op__c;
+ FLD (f_u5x4) = f_u5x4;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_s_abu", "f_op__b 0x%x", 'x', f_op__b, "f_op__c 0x%x", 'x', f_op__c, "f_u5x4 0x%x", 'x', f_u5x4, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_st_s_absp:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ UINT f_op__b;
+ SI f_u5x4;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u5x4 = ((EXTRACT_MSB0_UINT (insn, 32, 11, 5)) << (2));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_u5x4) = f_u5x4;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_s_absp", "f_op__b 0x%x", 'x', f_op__b, "f_u5x4 0x%x", 'x', f_u5x4, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stb_abs:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_u8;
+ INT f_d9h;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+ INT f_s9;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8);
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s9 = ((f_u8) | (((f_d9h) << (8))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_s9) = f_s9;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_abs", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_s9 0x%x", 'x', f_s9, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stb__AW_abs:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_u8;
+ INT f_d9h;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+ INT f_s9;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8);
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s9 = ((f_u8) | (((f_d9h) << (8))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_s9) = f_s9;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb__AW_abs", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_s9 0x%x", 'x', f_s9, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stb_as_abs:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_as_abs", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stb_s_abu:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ UINT f_op__b;
+ UINT f_op__c;
+ UINT f_u5;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_u5 = EXTRACT_MSB0_UINT (insn, 32, 11, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_op__c) = f_op__c;
+ FLD (f_u5) = f_u5;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_s_abu", "f_op__b 0x%x", 'x', f_op__b, "f_op__c 0x%x", 'x', f_op__c, "f_u5 0x%x", 'x', f_u5, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stb_s_absp:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ UINT f_op__b;
+ SI f_u5x4;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u5x4 = ((EXTRACT_MSB0_UINT (insn, 32, 11, 5)) << (2));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_u5x4) = f_u5x4;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_s_absp", "f_op__b 0x%x", 'x', f_op__b, "f_u5x4 0x%x", 'x', f_u5x4, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stw_abs:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_u8;
+ INT f_d9h;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+ INT f_s9;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8);
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s9 = ((f_u8) | (((f_d9h) << (8))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_s9) = f_s9;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stw_abs", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_s9 0x%x", 'x', f_s9, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stw__AW_abs:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_u8;
+ INT f_d9h;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+ INT f_s9;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8);
+ f_d9h = EXTRACT_MSB0_INT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s9 = ((f_u8) | (((f_d9h) << (8))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_s9) = f_s9;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stw__AW_abs", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_s9 0x%x", 'x', f_s9, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stw_s_abu:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ldw_s_abu.f
+ UINT f_op__b;
+ UINT f_op__c;
+ SI f_u5x2;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_u5x2 = ((EXTRACT_MSB0_UINT (insn, 32, 11, 5)) << (1));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_op__c) = f_op__c;
+ FLD (f_u5x2) = f_u5x2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stw_s_abu", "f_op__b 0x%x", 'x', f_op__b, "f_op__c 0x%x", 'x', f_op__c, "f_u5x2 0x%x", 'x', f_u5x2, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_L_s12__RA_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_L_s12__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_ccu6__RA_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_ccu6__RA_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_L_u6__RA_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_L_u6__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_L_r_r__RA__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_L_r_r__RA__RC", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_cc__RA__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_cc__RA__RC", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_s_abc:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ UINT f_op__b;
+ UINT f_op__c;
+ UINT f_op__a;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_op__a = EXTRACT_MSB0_UINT (insn, 32, 13, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_op__c) = f_op__c;
+ FLD (f_op__a) = f_op__a;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_s_abc", "f_op__b 0x%x", 'x', f_op__b, "f_op__c 0x%x", 'x', f_op__c, "f_op__a 0x%x", 'x', f_op__a, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_s_cbu3:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ UINT f_op__b;
+ UINT f_op__c;
+ UINT f_u3;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_u3 = EXTRACT_MSB0_UINT (insn, 32, 13, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_u3) = f_u3;
+ FLD (f_op__c) = f_op__c;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_s_cbu3", "f_op__b 0x%x", 'x', f_op__b, "f_u3 0x%x", 'x', f_u3, "f_op__c 0x%x", 'x', f_op__c, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_s_mcah:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ UINT f_op__b;
+ UINT f_h_2_0;
+ UINT f_h_5_3;
+ UINT f_op_h;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_h_2_0 = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_h_5_3 = EXTRACT_MSB0_UINT (insn, 32, 13, 3);
+{
+ f_op_h = ((f_h_2_0) | (((f_h_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_op_h) = f_op_h;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_s_mcah", "f_op__b 0x%x", 'x', f_op__b, "f_op_h 0x%x", 'x', f_op_h, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_s_absp:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ UINT f_op__b;
+ SI f_u5x4;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u5x4 = ((EXTRACT_MSB0_UINT (insn, 32, 11, 5)) << (2));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_u5x4) = f_u5x4;
+ FLD (f_op__b) = f_op__b;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_s_absp", "f_u5x4 0x%x", 'x', f_u5x4, "f_op__b 0x%x", 'x', f_op__b, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_s_asspsp:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ SI f_u5x4;
+
+ f_u5x4 = ((EXTRACT_MSB0_UINT (insn, 32, 11, 5)) << (2));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_u5x4) = f_u5x4;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_s_asspsp", "f_u5x4 0x%x", 'x', f_u5x4, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_s_gp:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_s_gprel.f
+ SI f_s9x4;
+
+ f_s9x4 = ((EXTRACT_MSB0_INT (insn, 32, 7, 9)) << (2));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_s9x4) = f_s9x4;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_s_gp", "f_s9x4 0x%x", 'x', f_s9x4, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_s_r_u7:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_s_r_u7.f
+ UINT f_op__b;
+ UINT f_u7;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u7 = EXTRACT_MSB0_UINT (insn, 32, 9, 7);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_u7) = f_u7;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_s_r_u7", "f_op__b 0x%x", 'x', f_op__b, "f_u7 0x%x", 'x', f_u7, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_adc_L_s12__RA_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_adc_L_s12__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_adc_ccu6__RA_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_adc_ccu6__RA_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_adc_L_u6__RA_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_adc_L_u6__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_adc_L_r_r__RA__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_adc_L_r_r__RA__RC", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_adc_cc__RA__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_adc_cc__RA__RC", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_I16_GO_SUB_s_go:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ UINT f_op__b;
+ UINT f_op__c;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_op__c) = f_op__c;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_I16_GO_SUB_s_go", "f_op__b 0x%x", 'x', f_op__b, "f_op__c 0x%x", 'x', f_op__c, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sub_s_go_sub_ne:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ UINT f_op__b;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sub_s_go_sub_ne", "f_op__b 0x%x", 'x', f_op__b, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sub_s_ssb:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ UINT f_op__b;
+ UINT f_u5;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u5 = EXTRACT_MSB0_UINT (insn, 32, 11, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_u5) = f_u5;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sub_s_ssb", "f_op__b 0x%x", 'x', f_op__b, "f_u5 0x%x", 'x', f_u5, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_and_L_s12__RA_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and_L_s12__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_and_ccu6__RA_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and_ccu6__RA_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_and_L_u6__RA_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and_L_u6__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_and_L_r_r__RA__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and_L_r_r__RA__RC", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_and_cc__RA__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and_cc__RA__RC", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mov_L_s12_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_s12) = f_s12;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mov_L_s12_", "f_F 0x%x", 'x', f_F, "f_s12 0x%x", 'x', f_s12, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mov_ccu6_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mov_ccu6_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mov_L_u6_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mov_L_u6_", "f_F 0x%x", 'x', f_F, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mov_L_r_r__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mov_L_r_r__RC", "f_F 0x%x", 'x', f_F, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mov_cc__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mov_cc__RC", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mov_s_mcah:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ UINT f_op__b;
+ UINT f_h_2_0;
+ UINT f_h_5_3;
+ UINT f_op_h;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_h_2_0 = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_h_5_3 = EXTRACT_MSB0_UINT (insn, 32, 13, 3);
+{
+ f_op_h = ((f_h_2_0) | (((f_h_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_h) = f_op_h;
+ FLD (f_op__b) = f_op__b;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mov_s_mcah", "f_op_h 0x%x", 'x', f_op_h, "f_op__b 0x%x", 'x', f_op__b, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mov_s_mcahb:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ UINT f_op__b;
+ UINT f_h_2_0;
+ UINT f_h_5_3;
+ UINT f_op_h;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_h_2_0 = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_h_5_3 = EXTRACT_MSB0_UINT (insn, 32, 13, 3);
+{
+ f_op_h = ((f_h_2_0) | (((f_h_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_op_h) = f_op_h;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mov_s_mcahb", "f_op__b 0x%x", 'x', f_op__b, "f_op_h 0x%x", 'x', f_op_h, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mov_s_r_u7:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ UINT f_op__b;
+ UINT f_u8;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u8 = EXTRACT_MSB0_UINT (insn, 32, 8, 8);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_u8) = f_u8;
+ FLD (f_op__b) = f_op__b;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mov_s_r_u7", "f_u8 0x%x", 'x', f_u8, "f_op__b 0x%x", 'x', f_op__b, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_tst_L_s12_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_tst_L_s12_", "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_tst_ccu6_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_tst_ccu6_", "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_tst_L_u6_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_tst_L_u6_", "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_tst_L_r_r__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_tst_L_r_r__RC", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_tst_cc__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_tst_cc__RC", "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_tst_s_go:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ UINT f_op__b;
+ UINT f_op__c;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_op__c) = f_op__c;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_tst_s_go", "f_op__b 0x%x", 'x', f_op__b, "f_op__c 0x%x", 'x', f_op__c, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmp_L_s12_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp_L_s12_", "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmp_ccu6_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp_ccu6_", "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmp_L_u6_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp_L_u6_", "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmp_L_r_r__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp_L_r_r__RC", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmp_cc__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp_cc__RC", "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmp_s_mcah:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ UINT f_op__b;
+ UINT f_h_2_0;
+ UINT f_h_5_3;
+ UINT f_op_h;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_h_2_0 = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+ f_h_5_3 = EXTRACT_MSB0_UINT (insn, 32, 13, 3);
+{
+ f_op_h = ((f_h_2_0) | (((f_h_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_op_h) = f_op_h;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp_s_mcah", "f_op__b 0x%x", 'x', f_op__b, "f_op_h 0x%x", 'x', f_op_h, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmp_s_r_u7:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_s_r_u7.f
+ UINT f_op__b;
+ UINT f_u7;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u7 = EXTRACT_MSB0_UINT (insn, 32, 9, 7);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_u7) = f_u7;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp_s_r_u7", "f_op__b 0x%x", 'x', f_op__b, "f_u7 0x%x", 'x', f_u7, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_btst_s_ssb:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ UINT f_op__b;
+ UINT f_u5;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_u5 = EXTRACT_MSB0_UINT (insn, 32, 11, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_u5) = f_u5;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_btst_s_ssb", "f_op__b 0x%x", 'x', f_op__b, "f_u5 0x%x", 'x', f_u5, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mpy_L_s12__RA_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mpy_L_s12__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mpy_ccu6__RA_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mpy_ccu6__RA_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mpy_L_u6__RA_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mpy_L_u6__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mpy_L_r_r__RA__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mpy_L_r_r__RA__RC", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mpy_cc__RA__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mpy_cc__RA__RC", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_L_r_r___RC_noilink_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_Cj;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_Cj = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_Cj) = f_op_Cj;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_L_r_r___RC_noilink_", "f_F 0x%x", 'x', f_F, "f_op_Cj 0x%x", 'x', f_op_Cj, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_cc___RC_noilink_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_Cj;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_Cj = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_Cj) = f_op_Cj;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_cc___RC_noilink_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_Cj 0x%x", 'x', f_op_Cj, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_L_r_r___RC_ilink_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_Cj;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_Cj = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_Cj) = f_op_Cj;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_L_r_r___RC_ilink_", "f_F 0x%x", 'x', f_F, "f_op_Cj 0x%x", 'x', f_op_Cj, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_cc___RC_ilink_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_Cj;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_Cj = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_Cj) = f_op_Cj;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_cc___RC_ilink_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_Cj 0x%x", 'x', f_op_Cj, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_L_s12_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_L_s12_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_ccu6_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_ccu6_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_L_u6_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_L_u6_", "f_F 0x%x", 'x', f_F, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_s:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ UINT f_op__b;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_s", "f_op__b 0x%x", 'x', f_op__b, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_s__S:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_s__S", (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_seq__S:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_seq__S", (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_L_s12_d_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_L_s12_d_", "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_ccu6_d_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_ccu6_d_", "f_cond_Q 0x%x", 'x', f_cond_Q, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_L_u6_d_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_L_u6_d_", "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_L_r_r_d___RC_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_L_r_r_d___RC_", "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_j_cc_d___RC_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j_cc_d___RC_", "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_jl_L_s12_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl_L_s12_", "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_jl_ccu6_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl_ccu6_", "f_cond_Q 0x%x", 'x', f_cond_Q, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_jl_L_u6_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl_L_u6_", "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_jl_s:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ UINT f_op__b;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl_s", "f_op__b 0x%x", 'x', f_op__b, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_jl_L_r_r___RC_noilink_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_Cj;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_Cj = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_Cj) = f_op_Cj;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl_L_r_r___RC_noilink_", "f_op_Cj 0x%x", 'x', f_op_Cj, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_jl_cc___RC_noilink_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_Cj;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_Cj = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_Cj) = f_op_Cj;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl_cc___RC_noilink_", "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_Cj 0x%x", 'x', f_op_Cj, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_jl_L_r_r_d___RC_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl_L_r_r_d___RC_", "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_jl_cc_d___RC_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl_cc_d___RC_", "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_jl_s_d:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ UINT f_op__b;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl_s_d", "f_op__b 0x%x", 'x', f_op__b, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lp_L_s12_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_lp_L_s12_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12x2;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12x2 = ((((f_u6) << (1))) | (((f_s12h) << (7))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12x2) = f_s12x2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lp_L_s12_", "f_op_B 0x%x", 'x', f_op_B, "f_s12x2 0x%x", 'x', f_s12x2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lpcc_ccu6:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_lpcc_ccu6.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ SI f_u6x2;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6x2 = ((EXTRACT_MSB0_UINT (insn, 32, 20, 6)) << (1));
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_u6x2) = f_u6x2;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lpcc_ccu6", "f_cond_Q 0x%x", 'x', f_cond_Q, "f_u6x2 0x%x", 'x', f_u6x2, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_flag_L_s12_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_flag_L_s12_", "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_flag_ccu6_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_flag_ccu6_", "f_cond_Q 0x%x", 'x', f_cond_Q, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_flag_L_u6_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_flag_L_u6_", "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_flag_L_r_r__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_flag_L_r_r__RC", "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_flag_cc__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_flag_cc__RC", "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lr_L_r_r___RC_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lr_L_r_r___RC_", "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lr_L_s12_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lr_L_s12_", "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lr_L_u6_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lr_L_u6_", "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sr_L_r_r___RC_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sr_L_r_r___RC_", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sr_L_s12_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sr_L_s12_", "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sr_L_u6_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sr_L_u6_", "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asl_L_r_r__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asl_L_r_r__RC", "f_F 0x%x", 'x', f_F, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asl_L_u6_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asl_L_u6_", "f_F 0x%x", 'x', f_F, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asr_L_r_r__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asr_L_r_r__RC", "f_F 0x%x", 'x', f_F, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asr_L_u6_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asr_L_u6_", "f_F 0x%x", 'x', f_F, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_rrc_L_r_r__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rrc_L_r_r__RC", "f_F 0x%x", 'x', f_F, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_rrc_L_u6_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rrc_L_u6_", "f_F 0x%x", 'x', f_F, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sexb_L_r_r__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sexb_L_r_r__RC", "f_F 0x%x", 'x', f_F, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sexb_L_u6_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sexb_L_u6_", "f_F 0x%x", 'x', f_F, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sexw_L_r_r__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sexw_L_r_r__RC", "f_F 0x%x", 'x', f_F, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sexw_L_u6_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sexw_L_u6_", "f_F 0x%x", 'x', f_F, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_abs_L_r_r__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_abs_L_r_r__RC", "f_F 0x%x", 'x', f_F, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_abs_L_u6_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_abs_L_u6_", "f_F 0x%x", 'x', f_F, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_not_L_r_r__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_not_L_r_r__RC", "f_F 0x%x", 'x', f_F, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_not_L_u6_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_not_L_u6_", "f_F 0x%x", 'x', f_F, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ex_L_r_r__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ex_L_r_r__RC", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ex_L_u6_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ex_L_u6_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_swi:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_swi", (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_trap_s:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_trap_s.f
+ UINT f_trapnum;
+
+ f_trapnum = EXTRACT_MSB0_UINT (insn, 32, 5, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_trapnum) = f_trapnum;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_trap_s", "f_trapnum 0x%x", 'x', f_trapnum, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_brk:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_brk", (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asl_L_s12__RA_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asl_L_s12__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asl_ccu6__RA_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asl_ccu6__RA_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asl_L_u6__RA_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asl_L_u6__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asl_L_r_r__RA__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asl_L_r_r__RA__RC", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asl_cc__RA__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asl_cc__RA__RC", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mul64_L_s12_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mul64_L_s12_", "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mul64_ccu6_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mul64_ccu6_", "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mul64_L_u6_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mul64_L_u6_", "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mul64_L_r_r__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mul64_L_r_r__RC", "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mul64_cc__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mul64_cc__RC", "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mul64_s_go:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ UINT f_op__b;
+ UINT f_op__c;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_op__c = EXTRACT_MSB0_UINT (insn, 32, 8, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ FLD (f_op__c) = f_op__c;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mul64_s_go", "f_op__b 0x%x", 'x', f_op__b, "f_op__c 0x%x", 'x', f_op__c, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_adds_L_s12__RA_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_adds_L_s12__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_adds_ccu6__RA_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_adds_ccu6__RA_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_adds_L_u6__RA_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_adds_L_u6__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_adds_L_r_r__RA__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_adds_L_r_r__RA__RC", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_adds_cc__RA__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_adds_cc__RA__RC", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_divaw_L_s12__RA_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_divaw_L_s12__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_divaw_ccu6__RA_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_divaw_ccu6__RA_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_divaw_L_u6__RA_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_divaw_L_u6__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_divaw_L_r_r__RA__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_divaw_L_r_r__RA__RC", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_divaw_cc__RA__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_divaw_cc__RA__RC", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asls_L_s12__RA_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asls_L_s12__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asls_ccu6__RA_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asls_ccu6__RA_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asls_L_u6__RA_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asls_L_u6__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asls_L_r_r__RA__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asls_L_r_r__RA__RC", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asls_cc__RA__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asls_cc__RA__RC", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_swap_L_r_r__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_swap_L_r_r__RC", "f_F 0x%x", 'x', f_F, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_swap_L_u6_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_swap_L_u6_", "f_F 0x%x", 'x', f_F, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_norm_L_u6_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_norm_L_u6_", "f_F 0x%x", 'x', f_F, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_rnd16_L_r_r__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rnd16_L_r_r__RC", "f_F 0x%x", 'x', f_F, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_rnd16_L_u6_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rnd16_L_u6_", "f_F 0x%x", 'x', f_F, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_abssw_L_r_r__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_abssw_L_r_r__RC", "f_F 0x%x", 'x', f_F, "f_op_C 0x%x", 'x', f_op_C, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_abssw_L_u6_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_abssw_L_u6_", "f_F 0x%x", 'x', f_F, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_abss_L_u6_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_B) = f_op_B;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_abss_L_u6_", "f_F 0x%x", 'x', f_F, "f_u6 0x%x", 'x', f_u6, "f_op_B 0x%x", 'x', f_op_B, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_nop_s:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nop_s", (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_pop_s_b:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ UINT f_op__b;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_pop_s_b", "f_op__b 0x%x", 'x', f_op__b, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_pop_s_blink:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_pop_s_blink", (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_push_s_b:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ UINT f_op__b;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_op__b) = f_op__b;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_push_s_b", "f_op__b 0x%x", 'x', f_op__b, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_push_s_blink:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_push_s_blink", (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mullw_L_s12__RA_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mullw_L_s12__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mullw_ccu6__RA_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mullw_ccu6__RA_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mullw_L_u6__RA_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mullw_L_u6__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mullw_L_r_r__RA__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mullw_L_r_r__RA__RC", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mullw_cc__RA__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mullw_cc__RA__RC", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_maclw_L_s12__RA_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_maclw_L_s12__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_maclw_ccu6__RA_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_maclw_ccu6__RA_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_maclw_L_u6__RA_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_maclw_L_u6__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_maclw_L_r_r__RA__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_maclw_L_r_r__RA__RC", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_maclw_cc__RA__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_maclw_cc__RA__RC", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_machulw_L_s12__RA_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ INT f_s12h;
+ UINT f_op_B;
+ INT f_s12;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_s12h = EXTRACT_MSB0_INT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+{
+ f_s12 = ((f_u6) | (((f_s12h) << (6))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_s12) = f_s12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machulw_L_s12__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_s12 0x%x", 'x', f_s12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_machulw_ccu6__RA_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machulw_ccu6__RA_", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_machulw_L_u6__RA_:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_u6;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_u6 = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_u6) = f_u6;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machulw_L_u6__RA_", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_u6 0x%x", 'x', f_u6, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_machulw_L_r_r__RA__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_op_A;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_op_A = EXTRACT_MSB0_UINT (insn, 32, 26, 6);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ FLD (f_op_A) = f_op_A;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machulw_L_r_r__RA__RC", "f_F 0x%x", 'x', f_F, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, "f_op_A 0x%x", 'x', f_op_A, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_machulw_cc__RA__RC:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ UINT f_op__b;
+ UINT f_F;
+ UINT f_B_5_3;
+ UINT f_op_C;
+ UINT f_cond_Q;
+ UINT f_op_B;
+
+ f_op__b = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+ f_F = EXTRACT_MSB0_UINT (insn, 32, 16, 1);
+ f_B_5_3 = EXTRACT_MSB0_UINT (insn, 32, 17, 3);
+ f_op_C = EXTRACT_MSB0_UINT (insn, 32, 20, 6);
+ f_cond_Q = EXTRACT_MSB0_UINT (insn, 32, 27, 5);
+{
+ f_op_B = ((f_op__b) | (((f_B_5_3) << (3))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_F) = f_F;
+ FLD (f_cond_Q) = f_cond_Q;
+ FLD (f_op_B) = f_op_B;
+ FLD (f_op_C) = f_op_C;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machulw_cc__RA__RC", "f_F 0x%x", 'x', f_F, "f_cond_Q 0x%x", 'x', f_cond_Q, "f_op_B 0x%x", 'x', f_op_B, "f_op_C 0x%x", 'x', f_op_C, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_current_loop_end:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_current_loop_end", (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_current_loop_end_after_branch:
+ {
+ const IDESC *idesc = &arc700f_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_current_loop_end_after_branch", (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+}
diff --git a/sim/arc/decode7.h b/sim/arc/decode7.h
new file mode 100644
index 0000000..8930444
--- /dev/null
+++ b/sim/arc/decode7.h
@@ -0,0 +1,226 @@
+/* Decode header for arc700f.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2007 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#ifndef ARC700F_DECODE_H
+#define ARC700F_DECODE_H
+
+extern const IDESC *arc700f_decode (SIM_CPU *, IADDR,
+ CGEN_INSN_INT, CGEN_INSN_INT,
+ ARGBUF *);
+extern void arc700f_init_idesc_table (SIM_CPU *);
+extern void arc700f_sem_init_idesc_table (SIM_CPU *);
+extern void arc700f_semf_init_idesc_table (SIM_CPU *);
+
+/* Enum declaration for instructions in cpu family arc700f. */
+typedef enum arc700f_insn_type {
+ ARC700F_INSN_X_INVALID, ARC700F_INSN_X_AFTER, ARC700F_INSN_X_BEFORE, ARC700F_INSN_X_CTI_CHAIN
+ , ARC700F_INSN_X_CHAIN, ARC700F_INSN_X_BEGIN, ARC700F_INSN_B_S, ARC700F_INSN_BCC_S
+ , ARC700F_INSN_BRCC_S, ARC700F_INSN_BCC_L, ARC700F_INSN_BCC_L_D, ARC700F_INSN_B_L
+ , ARC700F_INSN_B_L_D, ARC700F_INSN_BRCC_RC, ARC700F_INSN_BRCC_RC_D, ARC700F_INSN_BRCC_U6
+ , ARC700F_INSN_BRCC_U6_D, ARC700F_INSN_BL_S, ARC700F_INSN_BLCC, ARC700F_INSN_BLCC_D
+ , ARC700F_INSN_BL, ARC700F_INSN_BL_D, ARC700F_INSN_LD_ABS, ARC700F_INSN_LD__AW_ABS
+ , ARC700F_INSN_LD_AB_ABS, ARC700F_INSN_LD_AS_ABS, ARC700F_INSN_LD_ABC, ARC700F_INSN_LD__AW_ABC
+ , ARC700F_INSN_LD_AB_ABC, ARC700F_INSN_LD_AS_ABC, ARC700F_INSN_LD_S_ABC, ARC700F_INSN_LD_S_ABU
+ , ARC700F_INSN_LD_S_ABSP, ARC700F_INSN_LD_S_GPREL, ARC700F_INSN_LD_S_PCREL, ARC700F_INSN_LDB_ABS
+ , ARC700F_INSN_LDB__AW_ABS, ARC700F_INSN_LDB_AB_ABS, ARC700F_INSN_LDB_AS_ABS, ARC700F_INSN_LDB_ABC
+ , ARC700F_INSN_LDB__AW_ABC, ARC700F_INSN_LDB_AB_ABC, ARC700F_INSN_LDB_AS_ABC, ARC700F_INSN_LDB_S_ABC
+ , ARC700F_INSN_LDB_S_ABU, ARC700F_INSN_LDB_S_ABSP, ARC700F_INSN_LDB_S_GPREL, ARC700F_INSN_LDB_X_ABS
+ , ARC700F_INSN_LDB__AW_X_ABS, ARC700F_INSN_LDB_AB_X_ABS, ARC700F_INSN_LDB_AS_X_ABS, ARC700F_INSN_LDB_X_ABC
+ , ARC700F_INSN_LDB__AW_X_ABC, ARC700F_INSN_LDB_AB_X_ABC, ARC700F_INSN_LDB_AS_X_ABC, ARC700F_INSN_LDW_ABS
+ , ARC700F_INSN_LDW__AW_ABS, ARC700F_INSN_LDW_AB_ABS, ARC700F_INSN_LDW_AS_ABS, ARC700F_INSN_LDW_ABC
+ , ARC700F_INSN_LDW__AW_ABC, ARC700F_INSN_LDW_AB_ABC, ARC700F_INSN_LDW_AS_ABC, ARC700F_INSN_LDW_S_ABC
+ , ARC700F_INSN_LDW_S_ABU, ARC700F_INSN_LDW_S_GPREL, ARC700F_INSN_LDW_X_ABS, ARC700F_INSN_LDW__AW_X_ABS
+ , ARC700F_INSN_LDW_AB_X_ABS, ARC700F_INSN_LDW_AS_X_ABS, ARC700F_INSN_LDW_X_ABC, ARC700F_INSN_LDW__AW_X_ABC
+ , ARC700F_INSN_LDW_AB_X_ABC, ARC700F_INSN_LDW_AS_X_ABC, ARC700F_INSN_LDW_S_X_ABU, ARC700F_INSN_ST_ABS
+ , ARC700F_INSN_ST__AW_ABS, ARC700F_INSN_ST_AB_ABS, ARC700F_INSN_ST_AS_ABS, ARC700F_INSN_ST_S_ABU
+ , ARC700F_INSN_ST_S_ABSP, ARC700F_INSN_STB_ABS, ARC700F_INSN_STB__AW_ABS, ARC700F_INSN_STB_AB_ABS
+ , ARC700F_INSN_STB_AS_ABS, ARC700F_INSN_STB_S_ABU, ARC700F_INSN_STB_S_ABSP, ARC700F_INSN_STW_ABS
+ , ARC700F_INSN_STW__AW_ABS, ARC700F_INSN_STW_AB_ABS, ARC700F_INSN_STW_AS_ABS, ARC700F_INSN_STW_S_ABU
+ , ARC700F_INSN_ADD_L_S12__RA_, ARC700F_INSN_ADD_CCU6__RA_, ARC700F_INSN_ADD_L_U6__RA_, ARC700F_INSN_ADD_L_R_R__RA__RC
+ , ARC700F_INSN_ADD_CC__RA__RC, ARC700F_INSN_ADD_S_ABC, ARC700F_INSN_ADD_S_CBU3, ARC700F_INSN_ADD_S_MCAH
+ , ARC700F_INSN_ADD_S_ABSP, ARC700F_INSN_ADD_S_ASSPSP, ARC700F_INSN_ADD_S_GP, ARC700F_INSN_ADD_S_R_U7
+ , ARC700F_INSN_ADC_L_S12__RA_, ARC700F_INSN_ADC_CCU6__RA_, ARC700F_INSN_ADC_L_U6__RA_, ARC700F_INSN_ADC_L_R_R__RA__RC
+ , ARC700F_INSN_ADC_CC__RA__RC, ARC700F_INSN_SUB_L_S12__RA_, ARC700F_INSN_SUB_CCU6__RA_, ARC700F_INSN_SUB_L_U6__RA_
+ , ARC700F_INSN_SUB_L_R_R__RA__RC, ARC700F_INSN_SUB_CC__RA__RC, ARC700F_INSN_SUB_S_CBU3, ARC700F_INSN_I16_GO_SUB_S_GO
+ , ARC700F_INSN_SUB_S_GO_SUB_NE, ARC700F_INSN_SUB_S_SSB, ARC700F_INSN_SUB_S_ASSPSP, ARC700F_INSN_SBC_L_S12__RA_
+ , ARC700F_INSN_SBC_CCU6__RA_, ARC700F_INSN_SBC_L_U6__RA_, ARC700F_INSN_SBC_L_R_R__RA__RC, ARC700F_INSN_SBC_CC__RA__RC
+ , ARC700F_INSN_AND_L_S12__RA_, ARC700F_INSN_AND_CCU6__RA_, ARC700F_INSN_AND_L_U6__RA_, ARC700F_INSN_AND_L_R_R__RA__RC
+ , ARC700F_INSN_AND_CC__RA__RC, ARC700F_INSN_I16_GO_AND_S_GO, ARC700F_INSN_OR_L_S12__RA_, ARC700F_INSN_OR_CCU6__RA_
+ , ARC700F_INSN_OR_L_U6__RA_, ARC700F_INSN_OR_L_R_R__RA__RC, ARC700F_INSN_OR_CC__RA__RC, ARC700F_INSN_I16_GO_OR_S_GO
+ , ARC700F_INSN_BIC_L_S12__RA_, ARC700F_INSN_BIC_CCU6__RA_, ARC700F_INSN_BIC_L_U6__RA_, ARC700F_INSN_BIC_L_R_R__RA__RC
+ , ARC700F_INSN_BIC_CC__RA__RC, ARC700F_INSN_I16_GO_BIC_S_GO, ARC700F_INSN_XOR_L_S12__RA_, ARC700F_INSN_XOR_CCU6__RA_
+ , ARC700F_INSN_XOR_L_U6__RA_, ARC700F_INSN_XOR_L_R_R__RA__RC, ARC700F_INSN_XOR_CC__RA__RC, ARC700F_INSN_I16_GO_XOR_S_GO
+ , ARC700F_INSN_MAX_L_S12__RA_, ARC700F_INSN_MAX_CCU6__RA_, ARC700F_INSN_MAX_L_U6__RA_, ARC700F_INSN_MAX_L_R_R__RA__RC
+ , ARC700F_INSN_MAX_CC__RA__RC, ARC700F_INSN_MIN_L_S12__RA_, ARC700F_INSN_MIN_CCU6__RA_, ARC700F_INSN_MIN_L_U6__RA_
+ , ARC700F_INSN_MIN_L_R_R__RA__RC, ARC700F_INSN_MIN_CC__RA__RC, ARC700F_INSN_MOV_L_S12_, ARC700F_INSN_MOV_CCU6_
+ , ARC700F_INSN_MOV_L_U6_, ARC700F_INSN_MOV_L_R_R__RC, ARC700F_INSN_MOV_CC__RC, ARC700F_INSN_MOV_S_MCAH
+ , ARC700F_INSN_MOV_S_MCAHB, ARC700F_INSN_MOV_S_R_U7, ARC700F_INSN_TST_L_S12_, ARC700F_INSN_TST_CCU6_
+ , ARC700F_INSN_TST_L_U6_, ARC700F_INSN_TST_L_R_R__RC, ARC700F_INSN_TST_CC__RC, ARC700F_INSN_TST_S_GO
+ , ARC700F_INSN_CMP_L_S12_, ARC700F_INSN_CMP_CCU6_, ARC700F_INSN_CMP_L_U6_, ARC700F_INSN_CMP_L_R_R__RC
+ , ARC700F_INSN_CMP_CC__RC, ARC700F_INSN_CMP_S_MCAH, ARC700F_INSN_CMP_S_R_U7, ARC700F_INSN_RCMP_L_S12_
+ , ARC700F_INSN_RCMP_CCU6_, ARC700F_INSN_RCMP_L_U6_, ARC700F_INSN_RCMP_L_R_R__RC, ARC700F_INSN_RCMP_CC__RC
+ , ARC700F_INSN_RSUB_L_S12__RA_, ARC700F_INSN_RSUB_CCU6__RA_, ARC700F_INSN_RSUB_L_U6__RA_, ARC700F_INSN_RSUB_L_R_R__RA__RC
+ , ARC700F_INSN_RSUB_CC__RA__RC, ARC700F_INSN_BSET_L_S12__RA_, ARC700F_INSN_BSET_CCU6__RA_, ARC700F_INSN_BSET_L_U6__RA_
+ , ARC700F_INSN_BSET_L_R_R__RA__RC, ARC700F_INSN_BSET_CC__RA__RC, ARC700F_INSN_BSET_S_SSB, ARC700F_INSN_BCLR_L_S12__RA_
+ , ARC700F_INSN_BCLR_CCU6__RA_, ARC700F_INSN_BCLR_L_U6__RA_, ARC700F_INSN_BCLR_L_R_R__RA__RC, ARC700F_INSN_BCLR_CC__RA__RC
+ , ARC700F_INSN_BCLR_S_SSB, ARC700F_INSN_BTST_L_S12_, ARC700F_INSN_BTST_CCU6_, ARC700F_INSN_BTST_L_U6_
+ , ARC700F_INSN_BTST_L_R_R__RC, ARC700F_INSN_BTST_CC__RC, ARC700F_INSN_BTST_S_SSB, ARC700F_INSN_BXOR_L_S12__RA_
+ , ARC700F_INSN_BXOR_CCU6__RA_, ARC700F_INSN_BXOR_L_U6__RA_, ARC700F_INSN_BXOR_L_R_R__RA__RC, ARC700F_INSN_BXOR_CC__RA__RC
+ , ARC700F_INSN_BMSK_L_S12__RA_, ARC700F_INSN_BMSK_CCU6__RA_, ARC700F_INSN_BMSK_L_U6__RA_, ARC700F_INSN_BMSK_L_R_R__RA__RC
+ , ARC700F_INSN_BMSK_CC__RA__RC, ARC700F_INSN_BMSK_S_SSB, ARC700F_INSN_ADD1_L_S12__RA_, ARC700F_INSN_ADD1_CCU6__RA_
+ , ARC700F_INSN_ADD1_L_U6__RA_, ARC700F_INSN_ADD1_L_R_R__RA__RC, ARC700F_INSN_ADD1_CC__RA__RC, ARC700F_INSN_I16_GO_ADD1_S_GO
+ , ARC700F_INSN_ADD2_L_S12__RA_, ARC700F_INSN_ADD2_CCU6__RA_, ARC700F_INSN_ADD2_L_U6__RA_, ARC700F_INSN_ADD2_L_R_R__RA__RC
+ , ARC700F_INSN_ADD2_CC__RA__RC, ARC700F_INSN_I16_GO_ADD2_S_GO, ARC700F_INSN_ADD3_L_S12__RA_, ARC700F_INSN_ADD3_CCU6__RA_
+ , ARC700F_INSN_ADD3_L_U6__RA_, ARC700F_INSN_ADD3_L_R_R__RA__RC, ARC700F_INSN_ADD3_CC__RA__RC, ARC700F_INSN_I16_GO_ADD3_S_GO
+ , ARC700F_INSN_SUB1_L_S12__RA_, ARC700F_INSN_SUB1_CCU6__RA_, ARC700F_INSN_SUB1_L_U6__RA_, ARC700F_INSN_SUB1_L_R_R__RA__RC
+ , ARC700F_INSN_SUB1_CC__RA__RC, ARC700F_INSN_SUB2_L_S12__RA_, ARC700F_INSN_SUB2_CCU6__RA_, ARC700F_INSN_SUB2_L_U6__RA_
+ , ARC700F_INSN_SUB2_L_R_R__RA__RC, ARC700F_INSN_SUB2_CC__RA__RC, ARC700F_INSN_SUB3_L_S12__RA_, ARC700F_INSN_SUB3_CCU6__RA_
+ , ARC700F_INSN_SUB3_L_U6__RA_, ARC700F_INSN_SUB3_L_R_R__RA__RC, ARC700F_INSN_SUB3_CC__RA__RC, ARC700F_INSN_MPY_L_S12__RA_
+ , ARC700F_INSN_MPY_CCU6__RA_, ARC700F_INSN_MPY_L_U6__RA_, ARC700F_INSN_MPY_L_R_R__RA__RC, ARC700F_INSN_MPY_CC__RA__RC
+ , ARC700F_INSN_MPYH_L_S12__RA_, ARC700F_INSN_MPYH_CCU6__RA_, ARC700F_INSN_MPYH_L_U6__RA_, ARC700F_INSN_MPYH_L_R_R__RA__RC
+ , ARC700F_INSN_MPYH_CC__RA__RC, ARC700F_INSN_MPYHU_L_S12__RA_, ARC700F_INSN_MPYHU_CCU6__RA_, ARC700F_INSN_MPYHU_L_U6__RA_
+ , ARC700F_INSN_MPYHU_L_R_R__RA__RC, ARC700F_INSN_MPYHU_CC__RA__RC, ARC700F_INSN_MPYU_L_S12__RA_, ARC700F_INSN_MPYU_CCU6__RA_
+ , ARC700F_INSN_MPYU_L_U6__RA_, ARC700F_INSN_MPYU_L_R_R__RA__RC, ARC700F_INSN_MPYU_CC__RA__RC, ARC700F_INSN_J_L_R_R___RC_NOILINK_
+ , ARC700F_INSN_J_CC___RC_NOILINK_, ARC700F_INSN_J_L_R_R___RC_ILINK_, ARC700F_INSN_J_CC___RC_ILINK_, ARC700F_INSN_J_L_S12_
+ , ARC700F_INSN_J_CCU6_, ARC700F_INSN_J_L_U6_, ARC700F_INSN_J_S, ARC700F_INSN_J_S__S
+ , ARC700F_INSN_J_SEQ__S, ARC700F_INSN_J_SNE__S, ARC700F_INSN_J_L_S12_D_, ARC700F_INSN_J_CCU6_D_
+ , ARC700F_INSN_J_L_U6_D_, ARC700F_INSN_J_L_R_R_D___RC_, ARC700F_INSN_J_CC_D___RC_, ARC700F_INSN_J_S_D
+ , ARC700F_INSN_J_S__S_D, ARC700F_INSN_JL_L_S12_, ARC700F_INSN_JL_CCU6_, ARC700F_INSN_JL_L_U6_
+ , ARC700F_INSN_JL_S, ARC700F_INSN_JL_L_R_R___RC_NOILINK_, ARC700F_INSN_JL_CC___RC_NOILINK_, ARC700F_INSN_JL_L_S12_D_
+ , ARC700F_INSN_JL_CCU6_D_, ARC700F_INSN_JL_L_U6_D_, ARC700F_INSN_JL_L_R_R_D___RC_, ARC700F_INSN_JL_CC_D___RC_
+ , ARC700F_INSN_JL_S_D, ARC700F_INSN_LP_L_S12_, ARC700F_INSN_LPCC_CCU6, ARC700F_INSN_FLAG_L_S12_
+ , ARC700F_INSN_FLAG_CCU6_, ARC700F_INSN_FLAG_L_U6_, ARC700F_INSN_FLAG_L_R_R__RC, ARC700F_INSN_FLAG_CC__RC
+ , ARC700F_INSN_LR_L_R_R___RC_, ARC700F_INSN_LR_L_S12_, ARC700F_INSN_LR_L_U6_, ARC700F_INSN_SR_L_R_R___RC_
+ , ARC700F_INSN_SR_L_S12_, ARC700F_INSN_SR_L_U6_, ARC700F_INSN_ASL_L_R_R__RC, ARC700F_INSN_ASL_L_U6_
+ , ARC700F_INSN_I16_GO_ASL_S_GO, ARC700F_INSN_ASR_L_R_R__RC, ARC700F_INSN_ASR_L_U6_, ARC700F_INSN_I16_GO_ASR_S_GO
+ , ARC700F_INSN_LSR_L_R_R__RC, ARC700F_INSN_LSR_L_U6_, ARC700F_INSN_I16_GO_LSR_S_GO, ARC700F_INSN_ROR_L_R_R__RC
+ , ARC700F_INSN_ROR_L_U6_, ARC700F_INSN_RRC_L_R_R__RC, ARC700F_INSN_RRC_L_U6_, ARC700F_INSN_SEXB_L_R_R__RC
+ , ARC700F_INSN_SEXB_L_U6_, ARC700F_INSN_I16_GO_SEXB_S_GO, ARC700F_INSN_SEXW_L_R_R__RC, ARC700F_INSN_SEXW_L_U6_
+ , ARC700F_INSN_I16_GO_SEXW_S_GO, ARC700F_INSN_EXTB_L_R_R__RC, ARC700F_INSN_EXTB_L_U6_, ARC700F_INSN_I16_GO_EXTB_S_GO
+ , ARC700F_INSN_EXTW_L_R_R__RC, ARC700F_INSN_EXTW_L_U6_, ARC700F_INSN_I16_GO_EXTW_S_GO, ARC700F_INSN_ABS_L_R_R__RC
+ , ARC700F_INSN_ABS_L_U6_, ARC700F_INSN_I16_GO_ABS_S_GO, ARC700F_INSN_NOT_L_R_R__RC, ARC700F_INSN_NOT_L_U6_
+ , ARC700F_INSN_I16_GO_NOT_S_GO, ARC700F_INSN_RLC_L_R_R__RC, ARC700F_INSN_RLC_L_U6_, ARC700F_INSN_EX_L_R_R__RC
+ , ARC700F_INSN_EX_L_U6_, ARC700F_INSN_I16_GO_NEG_S_GO, ARC700F_INSN_SWI, ARC700F_INSN_TRAP_S
+ , ARC700F_INSN_BRK, ARC700F_INSN_BRK_S, ARC700F_INSN_ASL_L_S12__RA_, ARC700F_INSN_ASL_CCU6__RA_
+ , ARC700F_INSN_ASL_L_U6__RA_, ARC700F_INSN_ASL_L_R_R__RA__RC, ARC700F_INSN_ASL_CC__RA__RC, ARC700F_INSN_ASL_S_CBU3
+ , ARC700F_INSN_ASL_S_SSB, ARC700F_INSN_I16_GO_ASLM_S_GO, ARC700F_INSN_LSR_L_S12__RA_, ARC700F_INSN_LSR_CCU6__RA_
+ , ARC700F_INSN_LSR_L_U6__RA_, ARC700F_INSN_LSR_L_R_R__RA__RC, ARC700F_INSN_LSR_CC__RA__RC, ARC700F_INSN_LSR_S_SSB
+ , ARC700F_INSN_I16_GO_LSRM_S_GO, ARC700F_INSN_ASR_L_S12__RA_, ARC700F_INSN_ASR_CCU6__RA_, ARC700F_INSN_ASR_L_U6__RA_
+ , ARC700F_INSN_ASR_L_R_R__RA__RC, ARC700F_INSN_ASR_CC__RA__RC, ARC700F_INSN_ASR_S_CBU3, ARC700F_INSN_ASR_S_SSB
+ , ARC700F_INSN_I16_GO_ASRM_S_GO, ARC700F_INSN_ROR_L_S12__RA_, ARC700F_INSN_ROR_CCU6__RA_, ARC700F_INSN_ROR_L_U6__RA_
+ , ARC700F_INSN_ROR_L_R_R__RA__RC, ARC700F_INSN_ROR_CC__RA__RC, ARC700F_INSN_MUL64_L_S12_, ARC700F_INSN_MUL64_CCU6_
+ , ARC700F_INSN_MUL64_L_U6_, ARC700F_INSN_MUL64_L_R_R__RC, ARC700F_INSN_MUL64_CC__RC, ARC700F_INSN_MUL64_S_GO
+ , ARC700F_INSN_MULU64_L_S12_, ARC700F_INSN_MULU64_CCU6_, ARC700F_INSN_MULU64_L_U6_, ARC700F_INSN_MULU64_L_R_R__RC
+ , ARC700F_INSN_MULU64_CC__RC, ARC700F_INSN_ADDS_L_S12__RA_, ARC700F_INSN_ADDS_CCU6__RA_, ARC700F_INSN_ADDS_L_U6__RA_
+ , ARC700F_INSN_ADDS_L_R_R__RA__RC, ARC700F_INSN_ADDS_CC__RA__RC, ARC700F_INSN_SUBS_L_S12__RA_, ARC700F_INSN_SUBS_CCU6__RA_
+ , ARC700F_INSN_SUBS_L_U6__RA_, ARC700F_INSN_SUBS_L_R_R__RA__RC, ARC700F_INSN_SUBS_CC__RA__RC, ARC700F_INSN_DIVAW_L_S12__RA_
+ , ARC700F_INSN_DIVAW_CCU6__RA_, ARC700F_INSN_DIVAW_L_U6__RA_, ARC700F_INSN_DIVAW_L_R_R__RA__RC, ARC700F_INSN_DIVAW_CC__RA__RC
+ , ARC700F_INSN_ASLS_L_S12__RA_, ARC700F_INSN_ASLS_CCU6__RA_, ARC700F_INSN_ASLS_L_U6__RA_, ARC700F_INSN_ASLS_L_R_R__RA__RC
+ , ARC700F_INSN_ASLS_CC__RA__RC, ARC700F_INSN_ASRS_L_S12__RA_, ARC700F_INSN_ASRS_CCU6__RA_, ARC700F_INSN_ASRS_L_U6__RA_
+ , ARC700F_INSN_ASRS_L_R_R__RA__RC, ARC700F_INSN_ASRS_CC__RA__RC, ARC700F_INSN_ADDSDW_L_S12__RA_, ARC700F_INSN_ADDSDW_CCU6__RA_
+ , ARC700F_INSN_ADDSDW_L_U6__RA_, ARC700F_INSN_ADDSDW_L_R_R__RA__RC, ARC700F_INSN_ADDSDW_CC__RA__RC, ARC700F_INSN_SUBSDW_L_S12__RA_
+ , ARC700F_INSN_SUBSDW_CCU6__RA_, ARC700F_INSN_SUBSDW_L_U6__RA_, ARC700F_INSN_SUBSDW_L_R_R__RA__RC, ARC700F_INSN_SUBSDW_CC__RA__RC
+ , ARC700F_INSN_SWAP_L_R_R__RC, ARC700F_INSN_SWAP_L_U6_, ARC700F_INSN_NORM_L_R_R__RC, ARC700F_INSN_NORM_L_U6_
+ , ARC700F_INSN_RND16_L_R_R__RC, ARC700F_INSN_RND16_L_U6_, ARC700F_INSN_ABSSW_L_R_R__RC, ARC700F_INSN_ABSSW_L_U6_
+ , ARC700F_INSN_ABSS_L_R_R__RC, ARC700F_INSN_ABSS_L_U6_, ARC700F_INSN_NEGSW_L_R_R__RC, ARC700F_INSN_NEGSW_L_U6_
+ , ARC700F_INSN_NEGS_L_R_R__RC, ARC700F_INSN_NEGS_L_U6_, ARC700F_INSN_NORMW_L_R_R__RC, ARC700F_INSN_NORMW_L_U6_
+ , ARC700F_INSN_NOP_S, ARC700F_INSN_UNIMP_S, ARC700F_INSN_POP_S_B, ARC700F_INSN_POP_S_BLINK
+ , ARC700F_INSN_PUSH_S_B, ARC700F_INSN_PUSH_S_BLINK, ARC700F_INSN_MULLW_L_S12__RA_, ARC700F_INSN_MULLW_CCU6__RA_
+ , ARC700F_INSN_MULLW_L_U6__RA_, ARC700F_INSN_MULLW_L_R_R__RA__RC, ARC700F_INSN_MULLW_CC__RA__RC, ARC700F_INSN_MACLW_L_S12__RA_
+ , ARC700F_INSN_MACLW_CCU6__RA_, ARC700F_INSN_MACLW_L_U6__RA_, ARC700F_INSN_MACLW_L_R_R__RA__RC, ARC700F_INSN_MACLW_CC__RA__RC
+ , ARC700F_INSN_MACHLW_L_S12__RA_, ARC700F_INSN_MACHLW_CCU6__RA_, ARC700F_INSN_MACHLW_L_U6__RA_, ARC700F_INSN_MACHLW_L_R_R__RA__RC
+ , ARC700F_INSN_MACHLW_CC__RA__RC, ARC700F_INSN_MULULW_L_S12__RA_, ARC700F_INSN_MULULW_CCU6__RA_, ARC700F_INSN_MULULW_L_U6__RA_
+ , ARC700F_INSN_MULULW_L_R_R__RA__RC, ARC700F_INSN_MULULW_CC__RA__RC, ARC700F_INSN_MACHULW_L_S12__RA_, ARC700F_INSN_MACHULW_CCU6__RA_
+ , ARC700F_INSN_MACHULW_L_U6__RA_, ARC700F_INSN_MACHULW_L_R_R__RA__RC, ARC700F_INSN_MACHULW_CC__RA__RC, ARC700F_INSN_CURRENT_LOOP_END
+ , ARC700F_INSN_CURRENT_LOOP_END_AFTER_BRANCH, ARC700F_INSN_ARC600_CURRENT_LOOP_END_AFTER_BRANCH, ARC700F_INSN__MAX
+} ARC700F_INSN_TYPE;
+
+/* Enum declaration for semantic formats in cpu family arc700f. */
+typedef enum arc700f_sfmt_type {
+ ARC700F_SFMT_EMPTY, ARC700F_SFMT_B_S, ARC700F_SFMT_BCC_S, ARC700F_SFMT_BRCC_S
+ , ARC700F_SFMT_BCC_L, ARC700F_SFMT_B_L, ARC700F_SFMT_BRCC_RC, ARC700F_SFMT_BRCC_U6
+ , ARC700F_SFMT_BL_S, ARC700F_SFMT_BLCC, ARC700F_SFMT_BL, ARC700F_SFMT_BL_D
+ , ARC700F_SFMT_LD_ABS, ARC700F_SFMT_LD__AW_ABS, ARC700F_SFMT_LD_ABC, ARC700F_SFMT_LD__AW_ABC
+ , ARC700F_SFMT_LD_S_ABC, ARC700F_SFMT_LD_S_ABU, ARC700F_SFMT_LD_S_ABSP, ARC700F_SFMT_LD_S_GPREL
+ , ARC700F_SFMT_LD_S_PCREL, ARC700F_SFMT_LDB_ABS, ARC700F_SFMT_LDB__AW_ABS, ARC700F_SFMT_LDB_AS_ABS
+ , ARC700F_SFMT_LDB_ABC, ARC700F_SFMT_LDB__AW_ABC, ARC700F_SFMT_LDB_AS_ABC, ARC700F_SFMT_LDB_S_ABC
+ , ARC700F_SFMT_LDB_S_ABU, ARC700F_SFMT_LDB_S_ABSP, ARC700F_SFMT_LDB_S_GPREL, ARC700F_SFMT_LDW_ABS
+ , ARC700F_SFMT_LDW__AW_ABS, ARC700F_SFMT_LDW_ABC, ARC700F_SFMT_LDW__AW_ABC, ARC700F_SFMT_LDW_S_ABC
+ , ARC700F_SFMT_LDW_S_ABU, ARC700F_SFMT_LDW_S_GPREL, ARC700F_SFMT_ST_ABS, ARC700F_SFMT_ST__AW_ABS
+ , ARC700F_SFMT_ST_S_ABU, ARC700F_SFMT_ST_S_ABSP, ARC700F_SFMT_STB_ABS, ARC700F_SFMT_STB__AW_ABS
+ , ARC700F_SFMT_STB_AS_ABS, ARC700F_SFMT_STB_S_ABU, ARC700F_SFMT_STB_S_ABSP, ARC700F_SFMT_STW_ABS
+ , ARC700F_SFMT_STW__AW_ABS, ARC700F_SFMT_STW_S_ABU, ARC700F_SFMT_ADD_L_S12__RA_, ARC700F_SFMT_ADD_CCU6__RA_
+ , ARC700F_SFMT_ADD_L_U6__RA_, ARC700F_SFMT_ADD_L_R_R__RA__RC, ARC700F_SFMT_ADD_CC__RA__RC, ARC700F_SFMT_ADD_S_ABC
+ , ARC700F_SFMT_ADD_S_CBU3, ARC700F_SFMT_ADD_S_MCAH, ARC700F_SFMT_ADD_S_ABSP, ARC700F_SFMT_ADD_S_ASSPSP
+ , ARC700F_SFMT_ADD_S_GP, ARC700F_SFMT_ADD_S_R_U7, ARC700F_SFMT_ADC_L_S12__RA_, ARC700F_SFMT_ADC_CCU6__RA_
+ , ARC700F_SFMT_ADC_L_U6__RA_, ARC700F_SFMT_ADC_L_R_R__RA__RC, ARC700F_SFMT_ADC_CC__RA__RC, ARC700F_SFMT_I16_GO_SUB_S_GO
+ , ARC700F_SFMT_SUB_S_GO_SUB_NE, ARC700F_SFMT_SUB_S_SSB, ARC700F_SFMT_AND_L_S12__RA_, ARC700F_SFMT_AND_CCU6__RA_
+ , ARC700F_SFMT_AND_L_U6__RA_, ARC700F_SFMT_AND_L_R_R__RA__RC, ARC700F_SFMT_AND_CC__RA__RC, ARC700F_SFMT_MOV_L_S12_
+ , ARC700F_SFMT_MOV_CCU6_, ARC700F_SFMT_MOV_L_U6_, ARC700F_SFMT_MOV_L_R_R__RC, ARC700F_SFMT_MOV_CC__RC
+ , ARC700F_SFMT_MOV_S_MCAH, ARC700F_SFMT_MOV_S_MCAHB, ARC700F_SFMT_MOV_S_R_U7, ARC700F_SFMT_TST_L_S12_
+ , ARC700F_SFMT_TST_CCU6_, ARC700F_SFMT_TST_L_U6_, ARC700F_SFMT_TST_L_R_R__RC, ARC700F_SFMT_TST_CC__RC
+ , ARC700F_SFMT_TST_S_GO, ARC700F_SFMT_CMP_L_S12_, ARC700F_SFMT_CMP_CCU6_, ARC700F_SFMT_CMP_L_U6_
+ , ARC700F_SFMT_CMP_L_R_R__RC, ARC700F_SFMT_CMP_CC__RC, ARC700F_SFMT_CMP_S_MCAH, ARC700F_SFMT_CMP_S_R_U7
+ , ARC700F_SFMT_BTST_S_SSB, ARC700F_SFMT_MPY_L_S12__RA_, ARC700F_SFMT_MPY_CCU6__RA_, ARC700F_SFMT_MPY_L_U6__RA_
+ , ARC700F_SFMT_MPY_L_R_R__RA__RC, ARC700F_SFMT_MPY_CC__RA__RC, ARC700F_SFMT_J_L_R_R___RC_NOILINK_, ARC700F_SFMT_J_CC___RC_NOILINK_
+ , ARC700F_SFMT_J_L_R_R___RC_ILINK_, ARC700F_SFMT_J_CC___RC_ILINK_, ARC700F_SFMT_J_L_S12_, ARC700F_SFMT_J_CCU6_
+ , ARC700F_SFMT_J_L_U6_, ARC700F_SFMT_J_S, ARC700F_SFMT_J_S__S, ARC700F_SFMT_J_SEQ__S
+ , ARC700F_SFMT_J_L_S12_D_, ARC700F_SFMT_J_CCU6_D_, ARC700F_SFMT_J_L_U6_D_, ARC700F_SFMT_J_L_R_R_D___RC_
+ , ARC700F_SFMT_J_CC_D___RC_, ARC700F_SFMT_JL_L_S12_, ARC700F_SFMT_JL_CCU6_, ARC700F_SFMT_JL_L_U6_
+ , ARC700F_SFMT_JL_S, ARC700F_SFMT_JL_L_R_R___RC_NOILINK_, ARC700F_SFMT_JL_CC___RC_NOILINK_, ARC700F_SFMT_JL_L_R_R_D___RC_
+ , ARC700F_SFMT_JL_CC_D___RC_, ARC700F_SFMT_JL_S_D, ARC700F_SFMT_LP_L_S12_, ARC700F_SFMT_LPCC_CCU6
+ , ARC700F_SFMT_FLAG_L_S12_, ARC700F_SFMT_FLAG_CCU6_, ARC700F_SFMT_FLAG_L_U6_, ARC700F_SFMT_FLAG_L_R_R__RC
+ , ARC700F_SFMT_FLAG_CC__RC, ARC700F_SFMT_LR_L_R_R___RC_, ARC700F_SFMT_LR_L_S12_, ARC700F_SFMT_LR_L_U6_
+ , ARC700F_SFMT_SR_L_R_R___RC_, ARC700F_SFMT_SR_L_S12_, ARC700F_SFMT_SR_L_U6_, ARC700F_SFMT_ASL_L_R_R__RC
+ , ARC700F_SFMT_ASL_L_U6_, ARC700F_SFMT_ASR_L_R_R__RC, ARC700F_SFMT_ASR_L_U6_, ARC700F_SFMT_RRC_L_R_R__RC
+ , ARC700F_SFMT_RRC_L_U6_, ARC700F_SFMT_SEXB_L_R_R__RC, ARC700F_SFMT_SEXB_L_U6_, ARC700F_SFMT_SEXW_L_R_R__RC
+ , ARC700F_SFMT_SEXW_L_U6_, ARC700F_SFMT_ABS_L_R_R__RC, ARC700F_SFMT_ABS_L_U6_, ARC700F_SFMT_NOT_L_R_R__RC
+ , ARC700F_SFMT_NOT_L_U6_, ARC700F_SFMT_EX_L_R_R__RC, ARC700F_SFMT_EX_L_U6_, ARC700F_SFMT_SWI
+ , ARC700F_SFMT_TRAP_S, ARC700F_SFMT_BRK, ARC700F_SFMT_ASL_L_S12__RA_, ARC700F_SFMT_ASL_CCU6__RA_
+ , ARC700F_SFMT_ASL_L_U6__RA_, ARC700F_SFMT_ASL_L_R_R__RA__RC, ARC700F_SFMT_ASL_CC__RA__RC, ARC700F_SFMT_MUL64_L_S12_
+ , ARC700F_SFMT_MUL64_CCU6_, ARC700F_SFMT_MUL64_L_U6_, ARC700F_SFMT_MUL64_L_R_R__RC, ARC700F_SFMT_MUL64_CC__RC
+ , ARC700F_SFMT_MUL64_S_GO, ARC700F_SFMT_ADDS_L_S12__RA_, ARC700F_SFMT_ADDS_CCU6__RA_, ARC700F_SFMT_ADDS_L_U6__RA_
+ , ARC700F_SFMT_ADDS_L_R_R__RA__RC, ARC700F_SFMT_ADDS_CC__RA__RC, ARC700F_SFMT_DIVAW_L_S12__RA_, ARC700F_SFMT_DIVAW_CCU6__RA_
+ , ARC700F_SFMT_DIVAW_L_U6__RA_, ARC700F_SFMT_DIVAW_L_R_R__RA__RC, ARC700F_SFMT_DIVAW_CC__RA__RC, ARC700F_SFMT_ASLS_L_S12__RA_
+ , ARC700F_SFMT_ASLS_CCU6__RA_, ARC700F_SFMT_ASLS_L_U6__RA_, ARC700F_SFMT_ASLS_L_R_R__RA__RC, ARC700F_SFMT_ASLS_CC__RA__RC
+ , ARC700F_SFMT_SWAP_L_R_R__RC, ARC700F_SFMT_SWAP_L_U6_, ARC700F_SFMT_NORM_L_U6_, ARC700F_SFMT_RND16_L_R_R__RC
+ , ARC700F_SFMT_RND16_L_U6_, ARC700F_SFMT_ABSSW_L_R_R__RC, ARC700F_SFMT_ABSSW_L_U6_, ARC700F_SFMT_ABSS_L_U6_
+ , ARC700F_SFMT_NOP_S, ARC700F_SFMT_POP_S_B, ARC700F_SFMT_POP_S_BLINK, ARC700F_SFMT_PUSH_S_B
+ , ARC700F_SFMT_PUSH_S_BLINK, ARC700F_SFMT_MULLW_L_S12__RA_, ARC700F_SFMT_MULLW_CCU6__RA_, ARC700F_SFMT_MULLW_L_U6__RA_
+ , ARC700F_SFMT_MULLW_L_R_R__RA__RC, ARC700F_SFMT_MULLW_CC__RA__RC, ARC700F_SFMT_MACLW_L_S12__RA_, ARC700F_SFMT_MACLW_CCU6__RA_
+ , ARC700F_SFMT_MACLW_L_U6__RA_, ARC700F_SFMT_MACLW_L_R_R__RA__RC, ARC700F_SFMT_MACLW_CC__RA__RC, ARC700F_SFMT_MACHULW_L_S12__RA_
+ , ARC700F_SFMT_MACHULW_CCU6__RA_, ARC700F_SFMT_MACHULW_L_U6__RA_, ARC700F_SFMT_MACHULW_L_R_R__RA__RC, ARC700F_SFMT_MACHULW_CC__RA__RC
+ , ARC700F_SFMT_CURRENT_LOOP_END, ARC700F_SFMT_CURRENT_LOOP_END_AFTER_BRANCH
+} ARC700F_SFMT_TYPE;
+
+/* Function unit handlers (user written). */
+
+extern int arc700f_model_ARC700_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*b*/, INT /*c*/, INT /*a*/);
+
+/* Profiling before/after handlers (user written) */
+
+extern void arc700f_model_insn_before (SIM_CPU *, int /*first_p*/);
+extern void arc700f_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
+
+#endif /* ARC700F_DECODE_H */
diff --git a/sim/arc/devices.c b/sim/arc/devices.c
new file mode 100644
index 0000000..bc5c58e
--- /dev/null
+++ b/sim/arc/devices.c
@@ -0,0 +1,45 @@
+/* arc device support
+ Copyright (C) 1997, 1998 Free Software Foundation, Inc.
+
+This file is part of GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+#include "sim-main.h"
+
+int
+device_io_read_buffer (device *me, void *source, int space,
+ address_word addr, unsigned nr_bytes,
+ SIM_DESC sd, SIM_CPU *cpu, sim_cia cia)
+{
+ if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
+ return nr_bytes;
+ abort ();
+}
+
+int
+device_io_write_buffer (device *me, const void *source, int space,
+ address_word addr, unsigned nr_bytes,
+ SIM_DESC sd, SIM_CPU *cpu, sim_cia cia)
+{
+ if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
+ return nr_bytes;
+ abort ();
+}
+
+void
+device_error (device *me, char *message, ...)
+{
+}
diff --git a/sim/arc/mloop5.in b/sim/arc/mloop5.in
new file mode 100644
index 0000000..d59a141
--- /dev/null
+++ b/sim/arc/mloop5.in
@@ -0,0 +1,292 @@
+# Simulator main loop for arc. -*- C -*-
+# Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Simulators.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2, or (at your option)
+# any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License along
+# with this program; if not, write to the Free Software Foundation, Inc.,
+# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+# Syntax:
+# /bin/sh mainloop.in command
+#
+# Command is one of:
+#
+# init
+# support
+# extract-{simple,scache,pbb}
+# {full,fast}-exec-{simple,scache,pbb}
+#
+# A target need only provide a "full" version of one of simple,scache,pbb.
+# If the target wants it can also provide a fast version of same, or if
+# the slow (full featured) version is `simple', then the fast version can be
+# one of scache/pbb.
+# A target can't provide more than this.
+# However for illustration's sake this file provides examples of all.
+
+# ??? After a few more ports are done, revisit.
+# Will eventually need to machine generate a lot of this.
+
+case "x$1" in
+
+xsupport)
+
+cat <<EOF
+
+static INLINE const IDESC *
+extract (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT base_insn,
+ CGEN_INSN_INT insn, ARGBUF *abuf,
+ int fast_p)
+{
+ const IDESC *id = @cpu@_decode (current_cpu, pc, /*base_*/insn, insn, abuf);
+
+ @cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
+ if (! fast_p)
+ {
+ int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
+ int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
+ @cpu@_fill_argbuf_tp (current_cpu, abuf, trace_p, profile_p);
+ }
+ return id;
+}
+
+static INLINE SEM_PC
+execute (SIM_CPU *current_cpu, SCACHE *sc, int fast_p)
+{
+ SEM_PC vpc;
+
+ if (fast_p)
+ {
+#if ! WITH_SEM_SWITCH_FAST
+#if WITH_SCACHE
+ vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, sc);
+#else
+ vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, &sc->argbuf);
+#endif
+#else
+ abort ();
+#endif /* WITH_SEM_SWITCH_FAST */
+ }
+ else
+ {
+#if ! WITH_SEM_SWITCH_FULL
+ ARGBUF *abuf = &sc->argbuf;
+ const IDESC *idesc = abuf->idesc;
+ const CGEN_INSN *idata = idesc->idata;
+#if WITH_SCACHE_PBB
+ int virtual_p = CGEN_INSN_ATTR_VALUE (idata, CGEN_INSN_VIRTUAL);
+#else
+ int virtual_p = 0;
+#endif
+
+ if (! virtual_p)
+ {
+ /* FIXME: call x-before */
+ if (ARGBUF_PROFILE_P (abuf))
+ PROFILE_COUNT_INSN (current_cpu, abuf->addr, idesc->num);
+ /* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}. */
+ if (PROFILE_MODEL_P (current_cpu)
+ && ARGBUF_PROFILE_P (abuf))
+ @cpu@_model_insn_before (current_cpu, 1 /*first_p*/);
+ TRACE_INSN_INIT (current_cpu, abuf, 1);
+ TRACE_INSN (current_cpu, idata,
+ (const struct argbuf *) abuf, abuf->addr);
+ }
+#if WITH_SCACHE
+ vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, sc);
+#else
+ vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, abuf);
+#endif
+ if (! virtual_p)
+ {
+ /* FIXME: call x-after */
+ if (PROFILE_MODEL_P (current_cpu)
+ && ARGBUF_PROFILE_P (abuf))
+ {
+ int cycles;
+
+ cycles = (*idesc->timing->model_fn) (current_cpu, sc);
+ @cpu@_model_insn_after (current_cpu, 1 /*last_p*/, cycles);
+ }
+ TRACE_INSN_FINI (current_cpu, abuf, 1);
+ }
+#else
+ abort ();
+#endif /* WITH_SEM_SWITCH_FULL */
+ }
+
+ return vpc;
+}
+
+EOF
+
+;;
+
+xinit)
+
+# Nothing needed.
+
+;;
+
+xextract-simple | xextract-scache)
+
+cat <<EOF
+{
+ /* ??? FIXME: doesn't handle zero overhead loops. */
+ UHI high = GETIMEMUHI (current_cpu, vpc);
+ UHI low = GETIMEMUHI (current_cpu, vpc + 2);
+ USI insn = (high << 16) + low;
+
+ extract (current_cpu, vpc, high, insn, SEM_ARGBUF (sc), FAST_P);
+}
+EOF
+
+;;
+
+xextract-pbb)
+
+# Inputs: current_cpu, pc, sc, max_insns, FAST_P
+# Outputs: sc, pc
+# sc must be left pointing past the last created entry.
+# pc must be left pointing past the last created entry.
+# If the pbb is terminated by a cti insn, SET_CTI_VPC(sc) must be called
+# to record the vpc of the cti insn.
+# SET_INSN_COUNT(n) must be called to record number of real insns.
+
+cat <<EOF
+{
+ const IDESC *idesc;
+ int icount = 0;
+ PCADDR loop_end = @cpu@_h_auxr_get (current_cpu, 3);
+
+ /* Reserve one slot for a delay slot insn or zero overhead loop. */
+ max_insns--;
+ if (max_insns < 1)
+ max_insns = 1;
+ while (max_insns > 0)
+ {
+ UHI high = GETIMEMUHI (current_cpu, pc);
+ UHI low;
+ USI insn = (high << 16);
+
+ if ((high & ((HI) high >> 1)) & 0xa000)
+ {
+ /* 16 bit opcode */
+ idesc = extract (current_cpu, pc, high, insn, SEM_ARGBUF (sc),
+ FAST_P);
+ pc += 2;
+ /* Check for mov/cmp/add with long immediate. */
+ if ((high & 0xf8e7) == 0x70c7 && (high & 24) < 24)
+ pc += 4;
+ }
+ else
+ {
+ /* 32 bit opcode */
+ low = GETIMEMUHI (current_cpu, pc + 2);
+ insn = insn + low;
+ idesc = extract (current_cpu, pc, high, insn, SEM_ARGBUF (sc),
+ FAST_P);
+ pc += 4;
+ /* Check for long immediate. */
+ switch (CGEN_ATTR_CGEN_INSN_LIMM_VALUE (&(idesc->idata->base->attrs)))
+ {
+ case LIMM_H: abort ();
+ case LIMM_C:
+ if ((insn & 0x00000fc0) == 0x00000f80)
+ pc += 4;
+ break;
+ case LIMM_BC:
+ if ((insn & 0x00000fc0) != 0x00000f80)
+ {
+ case LIMM_B:
+ if ((insn & 0x07007000) != 0x06007000)
+ break;
+ }
+ pc += 4;
+ break;
+ case LIMM_NONE: break; /* Nothing to do. */
+
+ }
+ }
+ ++sc;
+ --max_insns;
+ ++icount;
+
+ /* Handle zero overhead loops. For ARCtangent-A5, these take
+ precendence over branches. */
+ if (pc == loop_end && !_cti_sc)
+ {
+ const IDESC *id =
+ & CPU_IDESC (current_cpu) [@CPU@_INSN_CURRENT_LOOP_END];
+
+ SEM_SET_CODE (&sc->argbuf, id, FAST_P);
+ sc->argbuf.idesc = id;
+ sc->argbuf.addr = pc;
+ sc->argbuf.fields.chain.insn_count = _insn_count;
+ sc->argbuf.fields.chain.next = 0;
+ sc->argbuf.fields.chain.branch_target = 0;
+ ++sc;
+ SET_CTI_VPC (sc - 1);
+ break;
+ }
+ else if (IDESC_CTI_P (idesc))
+ {
+ /* Must not have a CTI in a delay slot. That is not only invalid
+ in a program, it also could potentially overfill the scache. */
+ if (_cti_sc)
+ {
+ const IDESC *id =
+ & CPU_IDESC (current_cpu) [@CPU@_INSN_X_INVALID];
+
+ SEM_SET_CODE (&sc->argbuf, id, FAST_P);
+ sc->argbuf.idesc = id;
+ break;
+ }
+ SET_CTI_VPC (sc - 1);
+ if (CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_DELAY_SLOT))
+ max_insns = 1;
+ else
+ break;
+ }
+ }
+
+ Finish:
+ SET_INSN_COUNT (icount);
+}
+EOF
+
+;;
+
+xfull-exec-* | xfast-exec-*)
+
+# Inputs: current_cpu, vpc, FAST_P
+# Outputs: vpc
+# vpc is the virtual program counter.
+
+cat <<EOF
+#if (! FAST_P && WITH_SEM_SWITCH_FULL) || (FAST_P && WITH_SEM_SWITCH_FAST)
+#define DEFINE_SWITCH
+#include "sem5-switch.c"
+#else
+ vpc = execute (current_cpu, vpc, FAST_P);
+#endif
+EOF
+
+;;
+
+*)
+ echo "Invalid argument to mainloop.in: $1" >&2
+ exit 1
+ ;;
+
+esac
diff --git a/sim/arc/mloop6.in b/sim/arc/mloop6.in
new file mode 100644
index 0000000..21b44c4
--- /dev/null
+++ b/sim/arc/mloop6.in
@@ -0,0 +1,294 @@
+# Simulator main loop for arc. -*- C -*-
+# Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Simulators.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2, or (at your option)
+# any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License along
+# with this program; if not, write to the Free Software Foundation, Inc.,
+# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+# Syntax:
+# /bin/sh mainloop.in command
+#
+# Command is one of:
+#
+# init
+# support
+# extract-{simple,scache,pbb}
+# {full,fast}-exec-{simple,scache,pbb}
+#
+# A target need only provide a "full" version of one of simple,scache,pbb.
+# If the target wants it can also provide a fast version of same, or if
+# the slow (full featured) version is `simple', then the fast version can be
+# one of scache/pbb.
+# A target can't provide more than this.
+# However for illustration's sake this file provides examples of all.
+
+# ??? After a few more ports are done, revisit.
+# Will eventually need to machine generate a lot of this.
+
+case "x$1" in
+
+xsupport)
+
+cat <<EOF
+
+static INLINE const IDESC *
+extract (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT base_insn,
+ CGEN_INSN_INT insn, ARGBUF *abuf,
+ int fast_p)
+{
+ const IDESC *id = @cpu@_decode (current_cpu, pc, /*base_*/insn, insn, abuf);
+
+ @cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
+ if (! fast_p)
+ {
+ int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
+ int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
+ @cpu@_fill_argbuf_tp (current_cpu, abuf, trace_p, profile_p);
+ }
+ return id;
+}
+
+static INLINE SEM_PC
+execute (SIM_CPU *current_cpu, SCACHE *sc, int fast_p)
+{
+ SEM_PC vpc;
+
+ if (fast_p)
+ {
+#if ! WITH_SEM_SWITCH_FAST
+#if WITH_SCACHE
+ vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, sc);
+#else
+ vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, &sc->argbuf);
+#endif
+#else
+ abort ();
+#endif /* WITH_SEM_SWITCH_FAST */
+ }
+ else
+ {
+#if ! WITH_SEM_SWITCH_FULL
+ ARGBUF *abuf = &sc->argbuf;
+ const IDESC *idesc = abuf->idesc;
+ const CGEN_INSN *idata = idesc->idata;
+#if WITH_SCACHE_PBB
+ int virtual_p = CGEN_INSN_ATTR_VALUE (idata, CGEN_INSN_VIRTUAL);
+#else
+ int virtual_p = 0;
+#endif
+
+ if (! virtual_p)
+ {
+ /* FIXME: call x-before */
+ if (ARGBUF_PROFILE_P (abuf))
+ PROFILE_COUNT_INSN (current_cpu, abuf->addr, idesc->num);
+ /* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}. */
+ if (PROFILE_MODEL_P (current_cpu)
+ && ARGBUF_PROFILE_P (abuf))
+ @cpu@_model_insn_before (current_cpu, 1 /*first_p*/);
+ TRACE_INSN_INIT (current_cpu, abuf, 1);
+ TRACE_INSN (current_cpu, idata,
+ (const struct argbuf *) abuf, abuf->addr);
+ }
+#if WITH_SCACHE
+ vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, sc);
+#else
+ vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, abuf);
+#endif
+ if (! virtual_p)
+ {
+ /* FIXME: call x-after */
+ if (PROFILE_MODEL_P (current_cpu)
+ && ARGBUF_PROFILE_P (abuf))
+ {
+ int cycles;
+
+ cycles = (*idesc->timing->model_fn) (current_cpu, sc);
+ @cpu@_model_insn_after (current_cpu, 1 /*last_p*/, cycles);
+ }
+ TRACE_INSN_FINI (current_cpu, abuf, 1);
+ }
+#else
+ abort ();
+#endif /* WITH_SEM_SWITCH_FULL */
+ }
+
+ return vpc;
+}
+
+EOF
+
+;;
+
+xinit)
+
+# Nothing needed.
+
+;;
+
+xextract-simple | xextract-scache)
+
+cat <<EOF
+{
+ /* ??? FIXME: doesn't handle zero overhead loops. */
+ UHI high = GETIMEMUHI (current_cpu, vpc);
+ UHI low = GETIMEMUHI (current_cpu, vpc + 2);
+ USI insn = (high << 16) + low;
+
+ extract (current_cpu, vpc, high, insn, SEM_ARGBUF (sc), FAST_P);
+}
+EOF
+
+;;
+
+xextract-pbb)
+
+# Inputs: current_cpu, pc, sc, max_insns, FAST_P
+# Outputs: sc, pc
+# sc must be left pointing past the last created entry.
+# pc must be left pointing past the last created entry.
+# If the pbb is terminated by a cti insn, SET_CTI_VPC(sc) must be called
+# to record the vpc of the cti insn.
+# SET_INSN_COUNT(n) must be called to record number of real insns.
+
+cat <<EOF
+{
+ const IDESC *idesc;
+ int icount = 0;
+ PCADDR loop_end = @cpu@_h_auxr_get (current_cpu, 3);
+
+ /* Reserve two slots for a delay slot insn and zero overhead loop. */
+ max_insns -= 2;
+ if (max_insns < 1)
+ max_insns = 1;
+ while (max_insns > 0)
+ {
+ UHI high = GETIMEMUHI (current_cpu, pc);
+ UHI low;
+ USI insn = (high << 16);
+
+ if ((high & ((HI) high >> 1)) & 0xa000)
+ {
+ /* 16 bit opcode */
+ idesc = extract (current_cpu, pc, high, insn, SEM_ARGBUF (sc),
+ FAST_P);
+ pc += 2;
+ /* Check for mov/cmp/add with long immediate. */
+ if ((high & 0xf8e7) == 0x70c7 && (high & 24) < 24)
+ pc += 4;
+ }
+ else
+ {
+ /* 32 bit opcode */
+ low = GETIMEMUHI (current_cpu, pc + 2);
+ insn = insn + low;
+ idesc = extract (current_cpu, pc, high, insn, SEM_ARGBUF (sc),
+ FAST_P);
+ pc += 4;
+ /* Check for long immediate. */
+ switch (CGEN_ATTR_CGEN_INSN_LIMM_VALUE (&(idesc->idata->base->attrs)))
+ {
+ case LIMM_H: abort ();
+ case LIMM_C:
+ if ((insn & 0x00000fc0) == 0x00000f80)
+ pc += 4;
+ break;
+ case LIMM_BC:
+ if ((insn & 0x00000fc0) != 0x00000f80)
+ {
+ case LIMM_B:
+ if ((insn & 0x07007000) != 0x06007000)
+ break;
+ }
+ pc += 4;
+ break;
+ case LIMM_NONE: break; /* Nothing to do. */
+
+ }
+ }
+ ++sc;
+ --max_insns;
+ ++icount;
+
+ if (IDESC_CTI_P (idesc))
+ {
+ /* Must not have a CTI in a delay slot. That is not only invalid
+ in a program, it also could potentially overfill the scache. */
+ if (_cti_sc)
+ {
+ const IDESC *id =
+ & CPU_IDESC (current_cpu) [@CPU@_INSN_X_INVALID];
+
+ SEM_SET_CODE (&sc->argbuf, id, FAST_P);
+ sc->argbuf.idesc = id;
+ break;
+ }
+ SET_CTI_VPC (sc - 1);
+ if (CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_DELAY_SLOT))
+ max_insns = 1;
+ else
+ max_insns = 0;
+ }
+ /* Handle zero overhead loops. ARC 600 and ARC 700 suppress
+ zero overhead loops if a branch is pending. */
+ if (pc == loop_end)
+ {
+ const IDESC *id =
+ & CPU_IDESC (current_cpu)
+ [_cti_sc ? @CPU@_INSN_ARC600_CURRENT_LOOP_END_AFTER_BRANCH
+ : @CPU@_INSN_CURRENT_LOOP_END];
+
+ SEM_SET_CODE (&sc->argbuf, id, FAST_P);
+ sc->argbuf.idesc = id;
+ sc->argbuf.addr = pc;
+ sc->argbuf.fields.chain.insn_count = _insn_count;
+ sc->argbuf.fields.chain.next = 0;
+ sc->argbuf.fields.chain.branch_target = 0;
+ ++sc;
+ SET_CTI_VPC (sc - 1);
+ break;
+ }
+ }
+
+ Finish:
+ SET_INSN_COUNT (icount);
+}
+EOF
+
+;;
+
+xfull-exec-* | xfast-exec-*)
+
+# Inputs: current_cpu, vpc, FAST_P
+# Outputs: vpc
+# vpc is the virtual program counter.
+
+cat <<EOF
+#if (! FAST_P && WITH_SEM_SWITCH_FULL) || (FAST_P && WITH_SEM_SWITCH_FAST)
+#define DEFINE_SWITCH
+#include "sem6-switch.c"
+#else
+ vpc = execute (current_cpu, vpc, FAST_P);
+#endif
+EOF
+
+;;
+
+*)
+ echo "Invalid argument to mainloop.in: $1" >&2
+ exit 1
+ ;;
+
+esac
diff --git a/sim/arc/mloop7.in b/sim/arc/mloop7.in
new file mode 100644
index 0000000..fc95572
--- /dev/null
+++ b/sim/arc/mloop7.in
@@ -0,0 +1,294 @@
+# Simulator main loop for arc. -*- C -*-
+# Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Simulators.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2, or (at your option)
+# any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License along
+# with this program; if not, write to the Free Software Foundation, Inc.,
+# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+# Syntax:
+# /bin/sh mainloop.in command
+#
+# Command is one of:
+#
+# init
+# support
+# extract-{simple,scache,pbb}
+# {full,fast}-exec-{simple,scache,pbb}
+#
+# A target need only provide a "full" version of one of simple,scache,pbb.
+# If the target wants it can also provide a fast version of same, or if
+# the slow (full featured) version is `simple', then the fast version can be
+# one of scache/pbb.
+# A target can't provide more than this.
+# However for illustration's sake this file provides examples of all.
+
+# ??? After a few more ports are done, revisit.
+# Will eventually need to machine generate a lot of this.
+
+case "x$1" in
+
+xsupport)
+
+cat <<EOF
+
+static INLINE const IDESC *
+extract (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT base_insn,
+ CGEN_INSN_INT insn, ARGBUF *abuf,
+ int fast_p)
+{
+ const IDESC *id = @cpu@_decode (current_cpu, pc, /*base_*/insn, insn, abuf);
+
+ @cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
+ if (! fast_p)
+ {
+ int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
+ int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
+ @cpu@_fill_argbuf_tp (current_cpu, abuf, trace_p, profile_p);
+ }
+ return id;
+}
+
+static INLINE SEM_PC
+execute (SIM_CPU *current_cpu, SCACHE *sc, int fast_p)
+{
+ SEM_PC vpc;
+
+ if (fast_p)
+ {
+#if ! WITH_SEM_SWITCH_FAST
+#if WITH_SCACHE
+ vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, sc);
+#else
+ vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, &sc->argbuf);
+#endif
+#else
+ abort ();
+#endif /* WITH_SEM_SWITCH_FAST */
+ }
+ else
+ {
+#if ! WITH_SEM_SWITCH_FULL
+ ARGBUF *abuf = &sc->argbuf;
+ const IDESC *idesc = abuf->idesc;
+ const CGEN_INSN *idata = idesc->idata;
+#if WITH_SCACHE_PBB
+ int virtual_p = CGEN_INSN_ATTR_VALUE (idata, CGEN_INSN_VIRTUAL);
+#else
+ int virtual_p = 0;
+#endif
+
+ if (! virtual_p)
+ {
+ /* FIXME: call x-before */
+ if (ARGBUF_PROFILE_P (abuf))
+ PROFILE_COUNT_INSN (current_cpu, abuf->addr, idesc->num);
+ /* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}. */
+ if (PROFILE_MODEL_P (current_cpu)
+ && ARGBUF_PROFILE_P (abuf))
+ @cpu@_model_insn_before (current_cpu, 1 /*first_p*/);
+ TRACE_INSN_INIT (current_cpu, abuf, 1);
+ TRACE_INSN (current_cpu, idata,
+ (const struct argbuf *) abuf, abuf->addr);
+ }
+#if WITH_SCACHE
+ vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, sc);
+#else
+ vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, abuf);
+#endif
+ if (! virtual_p)
+ {
+ /* FIXME: call x-after */
+ if (PROFILE_MODEL_P (current_cpu)
+ && ARGBUF_PROFILE_P (abuf))
+ {
+ int cycles;
+
+ cycles = (*idesc->timing->model_fn) (current_cpu, sc);
+ @cpu@_model_insn_after (current_cpu, 1 /*last_p*/, cycles);
+ }
+ TRACE_INSN_FINI (current_cpu, abuf, 1);
+ }
+#else
+ abort ();
+#endif /* WITH_SEM_SWITCH_FULL */
+ }
+
+ return vpc;
+}
+
+EOF
+
+;;
+
+xinit)
+
+# Nothing needed.
+
+;;
+
+xextract-simple | xextract-scache)
+
+cat <<EOF
+{
+ /* ??? FIXME: doesn't handle zero overhead loops. */
+ UHI high = GETIMEMUHI (current_cpu, vpc);
+ UHI low = GETIMEMUHI (current_cpu, vpc + 2);
+ USI insn = (high << 16) + low;
+
+ extract (current_cpu, vpc, high, insn, SEM_ARGBUF (sc), FAST_P);
+}
+EOF
+
+;;
+
+xextract-pbb)
+
+# Inputs: current_cpu, pc, sc, max_insns, FAST_P
+# Outputs: sc, pc
+# sc must be left pointing past the last created entry.
+# pc must be left pointing past the last created entry.
+# If the pbb is terminated by a cti insn, SET_CTI_VPC(sc) must be called
+# to record the vpc of the cti insn.
+# SET_INSN_COUNT(n) must be called to record number of real insns.
+
+cat <<EOF
+{
+ const IDESC *idesc;
+ int icount = 0;
+ PCADDR loop_end = @cpu@_h_auxr_get (current_cpu, 3);
+
+ /* Reserve two slots for a delay slot insn and zero overhead loop. */
+ max_insns -= 2;
+ if (max_insns < 1)
+ max_insns = 1;
+ while (max_insns > 0)
+ {
+ UHI high = GETIMEMUHI (current_cpu, pc);
+ UHI low;
+ USI insn = (high << 16);
+
+ if ((high & ((HI) high >> 1)) & 0xa000)
+ {
+ /* 16 bit opcode */
+ idesc = extract (current_cpu, pc, high, insn, SEM_ARGBUF (sc),
+ FAST_P);
+ pc += 2;
+ /* Check for mov/cmp/add with long immediate. */
+ if ((high & 0xf8e7) == 0x70c7 && (high & 24) < 24)
+ pc += 4;
+ }
+ else
+ {
+ /* 32 bit opcode */
+ low = GETIMEMUHI (current_cpu, pc + 2);
+ insn = insn + low;
+ idesc = extract (current_cpu, pc, high, insn, SEM_ARGBUF (sc),
+ FAST_P);
+ pc += 4;
+ /* Check for long immediate. */
+ switch (CGEN_ATTR_CGEN_INSN_LIMM_VALUE (&(idesc->idata->base->attrs)))
+ {
+ case LIMM_H: abort ();
+ case LIMM_C:
+ if ((insn & 0x00000fc0) == 0x00000f80)
+ pc += 4;
+ break;
+ case LIMM_BC:
+ if ((insn & 0x00000fc0) != 0x00000f80)
+ {
+ case LIMM_B:
+ if ((insn & 0x07007000) != 0x06007000)
+ break;
+ }
+ pc += 4;
+ break;
+ case LIMM_NONE: break; /* Nothing to do. */
+
+ }
+ }
+ ++sc;
+ --max_insns;
+ ++icount;
+
+ if (IDESC_CTI_P (idesc))
+ {
+ /* Must not have a CTI in a delay slot. That is not only invalid
+ in a program, it also could potentially overfill the scache. */
+ if (_cti_sc)
+ {
+ const IDESC *id =
+ & CPU_IDESC (current_cpu) [@CPU@_INSN_X_INVALID];
+
+ SEM_SET_CODE (&sc->argbuf, id, FAST_P);
+ sc->argbuf.idesc = id;
+ break;
+ }
+ SET_CTI_VPC (sc - 1);
+ if (CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_DELAY_SLOT))
+ max_insns = 1;
+ else
+ max_insns = 0;
+ }
+ /* Handle zero overhead loops. ARC 600 and ARC 700 suppress
+ zero overhead loops if a branch is pending. */
+ if (pc == loop_end)
+ {
+ const IDESC *id =
+ & CPU_IDESC (current_cpu)
+ [_cti_sc ? @CPU@_INSN_CURRENT_LOOP_END_AFTER_BRANCH
+ : @CPU@_INSN_CURRENT_LOOP_END];
+
+ SEM_SET_CODE (&sc->argbuf, id, FAST_P);
+ sc->argbuf.idesc = id;
+ sc->argbuf.addr = pc;
+ sc->argbuf.fields.chain.insn_count = _insn_count;
+ sc->argbuf.fields.chain.next = 0;
+ sc->argbuf.fields.chain.branch_target = 0;
+ ++sc;
+ SET_CTI_VPC (sc - 1);
+ break;
+ }
+ }
+
+ Finish:
+ SET_INSN_COUNT (icount);
+}
+EOF
+
+;;
+
+xfull-exec-* | xfast-exec-*)
+
+# Inputs: current_cpu, vpc, FAST_P
+# Outputs: vpc
+# vpc is the virtual program counter.
+
+cat <<EOF
+#if (! FAST_P && WITH_SEM_SWITCH_FULL) || (FAST_P && WITH_SEM_SWITCH_FAST)
+#define DEFINE_SWITCH
+#include "sem7-switch.c"
+#else
+ vpc = execute (current_cpu, vpc, FAST_P);
+#endif
+EOF
+
+;;
+
+*)
+ echo "Invalid argument to mainloop.in: $1" >&2
+ exit 1
+ ;;
+
+esac
diff --git a/sim/arc/model5.c b/sim/arc/model5.c
new file mode 100644
index 0000000..82087ef
--- /dev/null
+++ b/sim/arc/model5.c
@@ -0,0 +1,9522 @@
+/* Simulator model support for a5f.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2007 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#define WANT_CPU a5f
+#define WANT_CPU_A5F
+
+#include "sim-main.h"
+
+/* The profiling data is recorded here, but is accessed via the profiling
+ mechanism. After all, this is information for profiling. */
+
+#if WITH_PROFILE_MODEL_P
+
+/* Model handlers for each insn. */
+
+static int
+model_A5_b_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_b_s.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_bcc_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bcc_s.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_brcc_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_brcc_s.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_bcc_l (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bcc_l.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_bcc_l_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bcc_l.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_b_l (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_b_l.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_b_l_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_b_l.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_brcc_RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_brcc_RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_brcc_RC_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_brcc_RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_brcc_U6 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_brcc_U6.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_brcc_U6_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_brcc_U6.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_bl_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bl_s.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_blcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_blcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_blcc_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_blcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_bl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bl.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_bl_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bl.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ld_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ld__AW_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ld_ab_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ld_as_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ld_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ld__AW_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ld_ab_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ld_as_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ld_s_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ld_s_abu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ld_s_absp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ld_s_gprel (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_gprel.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ld_s_pcrel (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_pcrel.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ldb_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ldb__AW_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ldb_ab_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ldb_as_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ldb_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ldb__AW_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ldb_ab_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ldb_as_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ldb_s_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ldb_s_abu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ldb_s_absp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ldb_s_gprel (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_gprel.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ldb_x_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ldb__AW_x_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ldb_ab_x_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ldb_as_x_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ldb_x_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ldb__AW_x_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ldb_ab_x_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ldb_as_x_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ldw_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ldw__AW_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ldw_ab_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ldw_as_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ldw_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ldw__AW_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ldw_ab_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ldw_as_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ldw_s_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ldw_s_abu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldw_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ldw_s_gprel (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldw_s_gprel.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ldw_x_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ldw__AW_x_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ldw_ab_x_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ldw_as_x_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ldw_x_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ldw__AW_x_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ldw_ab_x_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ldw_as_x_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ldw_s_x_abu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldw_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_st_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_st__AW_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_st_ab_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_st_as_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_st_s_abu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_st_s_absp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_stb_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_stb__AW_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_stb_ab_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_stb_as_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_stb_s_abu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_stb_s_absp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_stw_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_stw__AW_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_stw_ab_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_stw_as_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_stw_s_abu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldw_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_add_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_add_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_add_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_add_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_add_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_add_s_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_add_s_cbu3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_add_s_mcah (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_add_s_absp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_add_s_asspsp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_add_s_gp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_gprel.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_add_s_r_u7 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_r_u7.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_adc_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_adc_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_adc_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_adc_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_adc_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_sub_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_sub_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_sub_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_sub_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_sub_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_sub_s_cbu3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_I16_GO_SUB_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_sub_s_go_sub_ne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_sub_s_ssb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_sub_s_asspsp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_sbc_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_sbc_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_sbc_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_sbc_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_sbc_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_and_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_and_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_and_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_and_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_and_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_I16_GO_AND_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_or_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_or_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_or_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_or_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_or_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_I16_GO_OR_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_bic_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_bic_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_bic_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_bic_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_bic_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_I16_GO_BIC_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_xor_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_xor_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_xor_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_xor_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_xor_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_I16_GO_XOR_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_max_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_max_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_max_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_max_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_max_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_min_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_min_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_min_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_min_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_min_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mov_L_s12_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mov_ccu6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mov_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mov_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mov_cc__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mov_s_mcah (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mov_s_mcahb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mov_s_r_u7 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_tst_L_s12_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_tst_ccu6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_tst_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_tst_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_tst_cc__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_tst_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_cmp_L_s12_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_cmp_ccu6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_cmp_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_cmp_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_cmp_cc__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_cmp_s_mcah (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_cmp_s_r_u7 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_r_u7.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_rcmp_L_s12_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_rcmp_ccu6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_rcmp_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_rcmp_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_rcmp_cc__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_rsub_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_rsub_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_rsub_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_rsub_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_rsub_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_bset_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_bset_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_bset_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_bset_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_bset_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_bset_s_ssb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_bclr_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_bclr_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_bclr_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_bclr_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_bclr_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_bclr_s_ssb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_btst_L_s12_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_btst_ccu6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_btst_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_btst_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_btst_cc__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_btst_s_ssb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_bxor_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_bxor_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_bxor_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_bxor_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_bxor_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_bmsk_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_bmsk_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_bmsk_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_bmsk_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_bmsk_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_bmsk_s_ssb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_add1_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_add1_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_add1_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_add1_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_add1_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_I16_GO_ADD1_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_add2_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_add2_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_add2_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_add2_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_add2_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_I16_GO_ADD2_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_add3_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_add3_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_add3_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_add3_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_add3_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_I16_GO_ADD3_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_sub1_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_sub1_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_sub1_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_sub1_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_sub1_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_sub2_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_sub2_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_sub2_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_sub2_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_sub2_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_sub3_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_sub3_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_sub3_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_sub3_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_sub3_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mpy_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mpy_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mpy_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mpy_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mpy_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mpyh_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mpyh_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mpyh_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mpyh_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mpyh_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mpyhu_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mpyhu_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mpyhu_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mpyhu_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mpyhu_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mpyu_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mpyu_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mpyu_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mpyu_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mpyu_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_j_L_r_r___RC_noilink_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_j_cc___RC_noilink_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_j_L_r_r___RC_ilink_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_j_cc___RC_ilink_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_j_L_s12_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_j_ccu6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_j_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_j_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_j_s__S (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_j_seq__S (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_j_sne__S (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_j_L_s12_d_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_j_ccu6_d_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_j_L_u6_d_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_j_L_r_r_d___RC_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_j_cc_d___RC_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_j_s_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_j_s__S_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_jl_L_s12_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_jl_ccu6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_jl_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_jl_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_jl_L_r_r___RC_noilink_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_jl_cc___RC_noilink_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_jl_L_s12_d_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_jl_ccu6_d_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_jl_L_u6_d_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_jl_L_r_r_d___RC_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_jl_cc_d___RC_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_jl_s_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_lp_L_s12_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lp_L_s12_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_lpcc_ccu6 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lpcc_ccu6.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_flag_L_s12_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_flag_ccu6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_flag_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_flag_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_flag_cc__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_lr_L_r_r___RC_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_lr_L_s12_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_lr_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_sr_L_r_r___RC_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_sr_L_s12_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_sr_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_asl_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_asl_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_I16_GO_ASL_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_asr_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_asr_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_I16_GO_ASR_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_lsr_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_lsr_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_I16_GO_LSR_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ror_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ror_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_rrc_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_rrc_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_sexb_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_sexb_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_I16_GO_SEXB_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_sexw_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_sexw_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_I16_GO_SEXW_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_extb_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_extb_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_I16_GO_EXTB_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_extw_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_extw_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_I16_GO_EXTW_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_abs_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_abs_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_I16_GO_ABS_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_not_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_not_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_I16_GO_NOT_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_rlc_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_rlc_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_I16_GO_NEG_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_swi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_trap_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_trap_s.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_brk (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_brk_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_asl_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_asl_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_asl_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_asl_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_asl_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_asl_s_cbu3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_asl_s_ssb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_I16_GO_ASLM_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_lsr_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_lsr_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_lsr_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_lsr_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_lsr_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_lsr_s_ssb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_I16_GO_LSRM_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_asr_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_asr_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_asr_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_asr_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_asr_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_asr_s_cbu3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_asr_s_ssb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_I16_GO_ASRM_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ror_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ror_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ror_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ror_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_ror_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mul64_L_s12_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mul64_ccu6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mul64_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mul64_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mul64_cc__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mul64_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mulu64_L_s12_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mulu64_ccu6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mulu64_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mulu64_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mulu64_cc__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_adds_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_adds_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_adds_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_adds_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_adds_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_subs_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_subs_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_subs_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_subs_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_subs_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_divaw_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_divaw_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_divaw_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_divaw_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_divaw_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_asls_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_asls_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_asls_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_asls_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_asls_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_asrs_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_asrs_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_asrs_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_asrs_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_asrs_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_addsdw_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_addsdw_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_addsdw_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_addsdw_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_addsdw_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_subsdw_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_subsdw_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_subsdw_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_subsdw_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_subsdw_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_swap_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_swap_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_norm_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_norm_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_rnd16_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_rnd16_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_abssw_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_abssw_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_abss_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_abss_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_negsw_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_negsw_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_negs_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_negs_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_normw_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_normw_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_nop_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_unimp_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_pop_s_b (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_pop_s_blink (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_push_s_b (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_push_s_blink (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mullw_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mullw_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mullw_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mullw_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mullw_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_maclw_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_maclw_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_maclw_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_maclw_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_maclw_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_machlw_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_machlw_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_machlw_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_machlw_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_machlw_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mululw_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mululw_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mululw_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mululw_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_mululw_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_machulw_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_machulw_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_machulw_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_machulw_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_machulw_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_current_loop_end (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_current_loop_end_after_branch (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_A5_arc600_current_loop_end_after_branch (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += a5f_model_A5_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+/* We assume UNIT_NONE == 0 because the tables don't always terminate
+ entries with it. */
+
+/* Model timing data for `A5'. */
+
+static const INSN_TIMING A5_timing[] = {
+ { A5F_INSN_X_INVALID, 0, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_X_AFTER, 0, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_X_BEFORE, 0, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_X_CHAIN, 0, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_X_BEGIN, 0, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_B_S, model_A5_b_s, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BCC_S, model_A5_bcc_s, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BRCC_S, model_A5_brcc_s, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BCC_L, model_A5_bcc_l, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BCC_L_D, model_A5_bcc_l_d, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_B_L, model_A5_b_l, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_B_L_D, model_A5_b_l_d, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BRCC_RC, model_A5_brcc_RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BRCC_RC_D, model_A5_brcc_RC_d, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BRCC_U6, model_A5_brcc_U6, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BRCC_U6_D, model_A5_brcc_U6_d, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BL_S, model_A5_bl_s, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BLCC, model_A5_blcc, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BLCC_D, model_A5_blcc_d, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BL, model_A5_bl, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BL_D, model_A5_bl_d, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LD_ABS, model_A5_ld_abs, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LD__AW_ABS, model_A5_ld__AW_abs, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LD_AB_ABS, model_A5_ld_ab_abs, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LD_AS_ABS, model_A5_ld_as_abs, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LD_ABC, model_A5_ld_abc, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LD__AW_ABC, model_A5_ld__AW_abc, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LD_AB_ABC, model_A5_ld_ab_abc, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LD_AS_ABC, model_A5_ld_as_abc, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LD_S_ABC, model_A5_ld_s_abc, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LD_S_ABU, model_A5_ld_s_abu, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LD_S_ABSP, model_A5_ld_s_absp, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LD_S_GPREL, model_A5_ld_s_gprel, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LD_S_PCREL, model_A5_ld_s_pcrel, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LDB_ABS, model_A5_ldb_abs, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LDB__AW_ABS, model_A5_ldb__AW_abs, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LDB_AB_ABS, model_A5_ldb_ab_abs, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LDB_AS_ABS, model_A5_ldb_as_abs, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LDB_ABC, model_A5_ldb_abc, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LDB__AW_ABC, model_A5_ldb__AW_abc, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LDB_AB_ABC, model_A5_ldb_ab_abc, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LDB_AS_ABC, model_A5_ldb_as_abc, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LDB_S_ABC, model_A5_ldb_s_abc, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LDB_S_ABU, model_A5_ldb_s_abu, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LDB_S_ABSP, model_A5_ldb_s_absp, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LDB_S_GPREL, model_A5_ldb_s_gprel, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LDB_X_ABS, model_A5_ldb_x_abs, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LDB__AW_X_ABS, model_A5_ldb__AW_x_abs, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LDB_AB_X_ABS, model_A5_ldb_ab_x_abs, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LDB_AS_X_ABS, model_A5_ldb_as_x_abs, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LDB_X_ABC, model_A5_ldb_x_abc, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LDB__AW_X_ABC, model_A5_ldb__AW_x_abc, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LDB_AB_X_ABC, model_A5_ldb_ab_x_abc, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LDB_AS_X_ABC, model_A5_ldb_as_x_abc, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LDW_ABS, model_A5_ldw_abs, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LDW__AW_ABS, model_A5_ldw__AW_abs, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LDW_AB_ABS, model_A5_ldw_ab_abs, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LDW_AS_ABS, model_A5_ldw_as_abs, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LDW_ABC, model_A5_ldw_abc, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LDW__AW_ABC, model_A5_ldw__AW_abc, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LDW_AB_ABC, model_A5_ldw_ab_abc, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LDW_AS_ABC, model_A5_ldw_as_abc, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LDW_S_ABC, model_A5_ldw_s_abc, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LDW_S_ABU, model_A5_ldw_s_abu, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LDW_S_GPREL, model_A5_ldw_s_gprel, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LDW_X_ABS, model_A5_ldw_x_abs, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LDW__AW_X_ABS, model_A5_ldw__AW_x_abs, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LDW_AB_X_ABS, model_A5_ldw_ab_x_abs, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LDW_AS_X_ABS, model_A5_ldw_as_x_abs, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LDW_X_ABC, model_A5_ldw_x_abc, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LDW__AW_X_ABC, model_A5_ldw__AW_x_abc, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LDW_AB_X_ABC, model_A5_ldw_ab_x_abc, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LDW_AS_X_ABC, model_A5_ldw_as_x_abc, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LDW_S_X_ABU, model_A5_ldw_s_x_abu, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ST_ABS, model_A5_st_abs, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ST__AW_ABS, model_A5_st__AW_abs, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ST_AB_ABS, model_A5_st_ab_abs, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ST_AS_ABS, model_A5_st_as_abs, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ST_S_ABU, model_A5_st_s_abu, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ST_S_ABSP, model_A5_st_s_absp, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_STB_ABS, model_A5_stb_abs, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_STB__AW_ABS, model_A5_stb__AW_abs, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_STB_AB_ABS, model_A5_stb_ab_abs, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_STB_AS_ABS, model_A5_stb_as_abs, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_STB_S_ABU, model_A5_stb_s_abu, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_STB_S_ABSP, model_A5_stb_s_absp, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_STW_ABS, model_A5_stw_abs, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_STW__AW_ABS, model_A5_stw__AW_abs, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_STW_AB_ABS, model_A5_stw_ab_abs, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_STW_AS_ABS, model_A5_stw_as_abs, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_STW_S_ABU, model_A5_stw_s_abu, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ADD_L_S12__RA_, model_A5_add_L_s12__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ADD_CCU6__RA_, model_A5_add_ccu6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ADD_L_U6__RA_, model_A5_add_L_u6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ADD_L_R_R__RA__RC, model_A5_add_L_r_r__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ADD_CC__RA__RC, model_A5_add_cc__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ADD_S_ABC, model_A5_add_s_abc, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ADD_S_CBU3, model_A5_add_s_cbu3, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ADD_S_MCAH, model_A5_add_s_mcah, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ADD_S_ABSP, model_A5_add_s_absp, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ADD_S_ASSPSP, model_A5_add_s_asspsp, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ADD_S_GP, model_A5_add_s_gp, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ADD_S_R_U7, model_A5_add_s_r_u7, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ADC_L_S12__RA_, model_A5_adc_L_s12__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ADC_CCU6__RA_, model_A5_adc_ccu6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ADC_L_U6__RA_, model_A5_adc_L_u6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ADC_L_R_R__RA__RC, model_A5_adc_L_r_r__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ADC_CC__RA__RC, model_A5_adc_cc__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SUB_L_S12__RA_, model_A5_sub_L_s12__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SUB_CCU6__RA_, model_A5_sub_ccu6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SUB_L_U6__RA_, model_A5_sub_L_u6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SUB_L_R_R__RA__RC, model_A5_sub_L_r_r__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SUB_CC__RA__RC, model_A5_sub_cc__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SUB_S_CBU3, model_A5_sub_s_cbu3, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_I16_GO_SUB_S_GO, model_A5_I16_GO_SUB_s_go, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SUB_S_GO_SUB_NE, model_A5_sub_s_go_sub_ne, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SUB_S_SSB, model_A5_sub_s_ssb, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SUB_S_ASSPSP, model_A5_sub_s_asspsp, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SBC_L_S12__RA_, model_A5_sbc_L_s12__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SBC_CCU6__RA_, model_A5_sbc_ccu6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SBC_L_U6__RA_, model_A5_sbc_L_u6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SBC_L_R_R__RA__RC, model_A5_sbc_L_r_r__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SBC_CC__RA__RC, model_A5_sbc_cc__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_AND_L_S12__RA_, model_A5_and_L_s12__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_AND_CCU6__RA_, model_A5_and_ccu6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_AND_L_U6__RA_, model_A5_and_L_u6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_AND_L_R_R__RA__RC, model_A5_and_L_r_r__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_AND_CC__RA__RC, model_A5_and_cc__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_I16_GO_AND_S_GO, model_A5_I16_GO_AND_s_go, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_OR_L_S12__RA_, model_A5_or_L_s12__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_OR_CCU6__RA_, model_A5_or_ccu6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_OR_L_U6__RA_, model_A5_or_L_u6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_OR_L_R_R__RA__RC, model_A5_or_L_r_r__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_OR_CC__RA__RC, model_A5_or_cc__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_I16_GO_OR_S_GO, model_A5_I16_GO_OR_s_go, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BIC_L_S12__RA_, model_A5_bic_L_s12__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BIC_CCU6__RA_, model_A5_bic_ccu6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BIC_L_U6__RA_, model_A5_bic_L_u6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BIC_L_R_R__RA__RC, model_A5_bic_L_r_r__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BIC_CC__RA__RC, model_A5_bic_cc__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_I16_GO_BIC_S_GO, model_A5_I16_GO_BIC_s_go, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_XOR_L_S12__RA_, model_A5_xor_L_s12__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_XOR_CCU6__RA_, model_A5_xor_ccu6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_XOR_L_U6__RA_, model_A5_xor_L_u6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_XOR_L_R_R__RA__RC, model_A5_xor_L_r_r__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_XOR_CC__RA__RC, model_A5_xor_cc__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_I16_GO_XOR_S_GO, model_A5_I16_GO_XOR_s_go, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MAX_L_S12__RA_, model_A5_max_L_s12__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MAX_CCU6__RA_, model_A5_max_ccu6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MAX_L_U6__RA_, model_A5_max_L_u6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MAX_L_R_R__RA__RC, model_A5_max_L_r_r__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MAX_CC__RA__RC, model_A5_max_cc__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MIN_L_S12__RA_, model_A5_min_L_s12__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MIN_CCU6__RA_, model_A5_min_ccu6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MIN_L_U6__RA_, model_A5_min_L_u6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MIN_L_R_R__RA__RC, model_A5_min_L_r_r__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MIN_CC__RA__RC, model_A5_min_cc__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MOV_L_S12_, model_A5_mov_L_s12_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MOV_CCU6_, model_A5_mov_ccu6_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MOV_L_U6_, model_A5_mov_L_u6_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MOV_L_R_R__RC, model_A5_mov_L_r_r__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MOV_CC__RC, model_A5_mov_cc__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MOV_S_MCAH, model_A5_mov_s_mcah, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MOV_S_MCAHB, model_A5_mov_s_mcahb, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MOV_S_R_U7, model_A5_mov_s_r_u7, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_TST_L_S12_, model_A5_tst_L_s12_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_TST_CCU6_, model_A5_tst_ccu6_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_TST_L_U6_, model_A5_tst_L_u6_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_TST_L_R_R__RC, model_A5_tst_L_r_r__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_TST_CC__RC, model_A5_tst_cc__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_TST_S_GO, model_A5_tst_s_go, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_CMP_L_S12_, model_A5_cmp_L_s12_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_CMP_CCU6_, model_A5_cmp_ccu6_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_CMP_L_U6_, model_A5_cmp_L_u6_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_CMP_L_R_R__RC, model_A5_cmp_L_r_r__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_CMP_CC__RC, model_A5_cmp_cc__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_CMP_S_MCAH, model_A5_cmp_s_mcah, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_CMP_S_R_U7, model_A5_cmp_s_r_u7, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_RCMP_L_S12_, model_A5_rcmp_L_s12_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_RCMP_CCU6_, model_A5_rcmp_ccu6_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_RCMP_L_U6_, model_A5_rcmp_L_u6_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_RCMP_L_R_R__RC, model_A5_rcmp_L_r_r__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_RCMP_CC__RC, model_A5_rcmp_cc__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_RSUB_L_S12__RA_, model_A5_rsub_L_s12__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_RSUB_CCU6__RA_, model_A5_rsub_ccu6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_RSUB_L_U6__RA_, model_A5_rsub_L_u6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_RSUB_L_R_R__RA__RC, model_A5_rsub_L_r_r__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_RSUB_CC__RA__RC, model_A5_rsub_cc__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BSET_L_S12__RA_, model_A5_bset_L_s12__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BSET_CCU6__RA_, model_A5_bset_ccu6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BSET_L_U6__RA_, model_A5_bset_L_u6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BSET_L_R_R__RA__RC, model_A5_bset_L_r_r__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BSET_CC__RA__RC, model_A5_bset_cc__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BSET_S_SSB, model_A5_bset_s_ssb, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BCLR_L_S12__RA_, model_A5_bclr_L_s12__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BCLR_CCU6__RA_, model_A5_bclr_ccu6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BCLR_L_U6__RA_, model_A5_bclr_L_u6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BCLR_L_R_R__RA__RC, model_A5_bclr_L_r_r__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BCLR_CC__RA__RC, model_A5_bclr_cc__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BCLR_S_SSB, model_A5_bclr_s_ssb, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BTST_L_S12_, model_A5_btst_L_s12_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BTST_CCU6_, model_A5_btst_ccu6_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BTST_L_U6_, model_A5_btst_L_u6_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BTST_L_R_R__RC, model_A5_btst_L_r_r__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BTST_CC__RC, model_A5_btst_cc__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BTST_S_SSB, model_A5_btst_s_ssb, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BXOR_L_S12__RA_, model_A5_bxor_L_s12__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BXOR_CCU6__RA_, model_A5_bxor_ccu6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BXOR_L_U6__RA_, model_A5_bxor_L_u6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BXOR_L_R_R__RA__RC, model_A5_bxor_L_r_r__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BXOR_CC__RA__RC, model_A5_bxor_cc__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BMSK_L_S12__RA_, model_A5_bmsk_L_s12__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BMSK_CCU6__RA_, model_A5_bmsk_ccu6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BMSK_L_U6__RA_, model_A5_bmsk_L_u6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BMSK_L_R_R__RA__RC, model_A5_bmsk_L_r_r__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BMSK_CC__RA__RC, model_A5_bmsk_cc__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BMSK_S_SSB, model_A5_bmsk_s_ssb, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ADD1_L_S12__RA_, model_A5_add1_L_s12__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ADD1_CCU6__RA_, model_A5_add1_ccu6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ADD1_L_U6__RA_, model_A5_add1_L_u6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ADD1_L_R_R__RA__RC, model_A5_add1_L_r_r__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ADD1_CC__RA__RC, model_A5_add1_cc__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_I16_GO_ADD1_S_GO, model_A5_I16_GO_ADD1_s_go, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ADD2_L_S12__RA_, model_A5_add2_L_s12__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ADD2_CCU6__RA_, model_A5_add2_ccu6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ADD2_L_U6__RA_, model_A5_add2_L_u6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ADD2_L_R_R__RA__RC, model_A5_add2_L_r_r__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ADD2_CC__RA__RC, model_A5_add2_cc__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_I16_GO_ADD2_S_GO, model_A5_I16_GO_ADD2_s_go, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ADD3_L_S12__RA_, model_A5_add3_L_s12__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ADD3_CCU6__RA_, model_A5_add3_ccu6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ADD3_L_U6__RA_, model_A5_add3_L_u6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ADD3_L_R_R__RA__RC, model_A5_add3_L_r_r__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ADD3_CC__RA__RC, model_A5_add3_cc__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_I16_GO_ADD3_S_GO, model_A5_I16_GO_ADD3_s_go, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SUB1_L_S12__RA_, model_A5_sub1_L_s12__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SUB1_CCU6__RA_, model_A5_sub1_ccu6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SUB1_L_U6__RA_, model_A5_sub1_L_u6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SUB1_L_R_R__RA__RC, model_A5_sub1_L_r_r__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SUB1_CC__RA__RC, model_A5_sub1_cc__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SUB2_L_S12__RA_, model_A5_sub2_L_s12__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SUB2_CCU6__RA_, model_A5_sub2_ccu6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SUB2_L_U6__RA_, model_A5_sub2_L_u6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SUB2_L_R_R__RA__RC, model_A5_sub2_L_r_r__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SUB2_CC__RA__RC, model_A5_sub2_cc__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SUB3_L_S12__RA_, model_A5_sub3_L_s12__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SUB3_CCU6__RA_, model_A5_sub3_ccu6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SUB3_L_U6__RA_, model_A5_sub3_L_u6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SUB3_L_R_R__RA__RC, model_A5_sub3_L_r_r__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SUB3_CC__RA__RC, model_A5_sub3_cc__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MPY_L_S12__RA_, model_A5_mpy_L_s12__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MPY_CCU6__RA_, model_A5_mpy_ccu6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MPY_L_U6__RA_, model_A5_mpy_L_u6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MPY_L_R_R__RA__RC, model_A5_mpy_L_r_r__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MPY_CC__RA__RC, model_A5_mpy_cc__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MPYH_L_S12__RA_, model_A5_mpyh_L_s12__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MPYH_CCU6__RA_, model_A5_mpyh_ccu6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MPYH_L_U6__RA_, model_A5_mpyh_L_u6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MPYH_L_R_R__RA__RC, model_A5_mpyh_L_r_r__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MPYH_CC__RA__RC, model_A5_mpyh_cc__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MPYHU_L_S12__RA_, model_A5_mpyhu_L_s12__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MPYHU_CCU6__RA_, model_A5_mpyhu_ccu6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MPYHU_L_U6__RA_, model_A5_mpyhu_L_u6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MPYHU_L_R_R__RA__RC, model_A5_mpyhu_L_r_r__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MPYHU_CC__RA__RC, model_A5_mpyhu_cc__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MPYU_L_S12__RA_, model_A5_mpyu_L_s12__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MPYU_CCU6__RA_, model_A5_mpyu_ccu6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MPYU_L_U6__RA_, model_A5_mpyu_L_u6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MPYU_L_R_R__RA__RC, model_A5_mpyu_L_r_r__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MPYU_CC__RA__RC, model_A5_mpyu_cc__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_J_L_R_R___RC_NOILINK_, model_A5_j_L_r_r___RC_noilink_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_J_CC___RC_NOILINK_, model_A5_j_cc___RC_noilink_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_J_L_R_R___RC_ILINK_, model_A5_j_L_r_r___RC_ilink_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_J_CC___RC_ILINK_, model_A5_j_cc___RC_ilink_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_J_L_S12_, model_A5_j_L_s12_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_J_CCU6_, model_A5_j_ccu6_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_J_L_U6_, model_A5_j_L_u6_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_J_S, model_A5_j_s, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_J_S__S, model_A5_j_s__S, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_J_SEQ__S, model_A5_j_seq__S, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_J_SNE__S, model_A5_j_sne__S, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_J_L_S12_D_, model_A5_j_L_s12_d_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_J_CCU6_D_, model_A5_j_ccu6_d_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_J_L_U6_D_, model_A5_j_L_u6_d_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_J_L_R_R_D___RC_, model_A5_j_L_r_r_d___RC_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_J_CC_D___RC_, model_A5_j_cc_d___RC_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_J_S_D, model_A5_j_s_d, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_J_S__S_D, model_A5_j_s__S_d, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_JL_L_S12_, model_A5_jl_L_s12_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_JL_CCU6_, model_A5_jl_ccu6_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_JL_L_U6_, model_A5_jl_L_u6_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_JL_S, model_A5_jl_s, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_JL_L_R_R___RC_NOILINK_, model_A5_jl_L_r_r___RC_noilink_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_JL_CC___RC_NOILINK_, model_A5_jl_cc___RC_noilink_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_JL_L_S12_D_, model_A5_jl_L_s12_d_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_JL_CCU6_D_, model_A5_jl_ccu6_d_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_JL_L_U6_D_, model_A5_jl_L_u6_d_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_JL_L_R_R_D___RC_, model_A5_jl_L_r_r_d___RC_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_JL_CC_D___RC_, model_A5_jl_cc_d___RC_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_JL_S_D, model_A5_jl_s_d, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LP_L_S12_, model_A5_lp_L_s12_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LPCC_CCU6, model_A5_lpcc_ccu6, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_FLAG_L_S12_, model_A5_flag_L_s12_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_FLAG_CCU6_, model_A5_flag_ccu6_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_FLAG_L_U6_, model_A5_flag_L_u6_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_FLAG_L_R_R__RC, model_A5_flag_L_r_r__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_FLAG_CC__RC, model_A5_flag_cc__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LR_L_R_R___RC_, model_A5_lr_L_r_r___RC_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LR_L_S12_, model_A5_lr_L_s12_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LR_L_U6_, model_A5_lr_L_u6_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SR_L_R_R___RC_, model_A5_sr_L_r_r___RC_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SR_L_S12_, model_A5_sr_L_s12_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SR_L_U6_, model_A5_sr_L_u6_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ASL_L_R_R__RC, model_A5_asl_L_r_r__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ASL_L_U6_, model_A5_asl_L_u6_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_I16_GO_ASL_S_GO, model_A5_I16_GO_ASL_s_go, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ASR_L_R_R__RC, model_A5_asr_L_r_r__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ASR_L_U6_, model_A5_asr_L_u6_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_I16_GO_ASR_S_GO, model_A5_I16_GO_ASR_s_go, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LSR_L_R_R__RC, model_A5_lsr_L_r_r__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LSR_L_U6_, model_A5_lsr_L_u6_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_I16_GO_LSR_S_GO, model_A5_I16_GO_LSR_s_go, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ROR_L_R_R__RC, model_A5_ror_L_r_r__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ROR_L_U6_, model_A5_ror_L_u6_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_RRC_L_R_R__RC, model_A5_rrc_L_r_r__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_RRC_L_U6_, model_A5_rrc_L_u6_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SEXB_L_R_R__RC, model_A5_sexb_L_r_r__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SEXB_L_U6_, model_A5_sexb_L_u6_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_I16_GO_SEXB_S_GO, model_A5_I16_GO_SEXB_s_go, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SEXW_L_R_R__RC, model_A5_sexw_L_r_r__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SEXW_L_U6_, model_A5_sexw_L_u6_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_I16_GO_SEXW_S_GO, model_A5_I16_GO_SEXW_s_go, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_EXTB_L_R_R__RC, model_A5_extb_L_r_r__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_EXTB_L_U6_, model_A5_extb_L_u6_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_I16_GO_EXTB_S_GO, model_A5_I16_GO_EXTB_s_go, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_EXTW_L_R_R__RC, model_A5_extw_L_r_r__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_EXTW_L_U6_, model_A5_extw_L_u6_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_I16_GO_EXTW_S_GO, model_A5_I16_GO_EXTW_s_go, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ABS_L_R_R__RC, model_A5_abs_L_r_r__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ABS_L_U6_, model_A5_abs_L_u6_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_I16_GO_ABS_S_GO, model_A5_I16_GO_ABS_s_go, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_NOT_L_R_R__RC, model_A5_not_L_r_r__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_NOT_L_U6_, model_A5_not_L_u6_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_I16_GO_NOT_S_GO, model_A5_I16_GO_NOT_s_go, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_RLC_L_R_R__RC, model_A5_rlc_L_r_r__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_RLC_L_U6_, model_A5_rlc_L_u6_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_I16_GO_NEG_S_GO, model_A5_I16_GO_NEG_s_go, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SWI, model_A5_swi, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_TRAP_S, model_A5_trap_s, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BRK, model_A5_brk, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_BRK_S, model_A5_brk_s, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ASL_L_S12__RA_, model_A5_asl_L_s12__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ASL_CCU6__RA_, model_A5_asl_ccu6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ASL_L_U6__RA_, model_A5_asl_L_u6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ASL_L_R_R__RA__RC, model_A5_asl_L_r_r__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ASL_CC__RA__RC, model_A5_asl_cc__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ASL_S_CBU3, model_A5_asl_s_cbu3, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ASL_S_SSB, model_A5_asl_s_ssb, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_I16_GO_ASLM_S_GO, model_A5_I16_GO_ASLM_s_go, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LSR_L_S12__RA_, model_A5_lsr_L_s12__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LSR_CCU6__RA_, model_A5_lsr_ccu6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LSR_L_U6__RA_, model_A5_lsr_L_u6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LSR_L_R_R__RA__RC, model_A5_lsr_L_r_r__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LSR_CC__RA__RC, model_A5_lsr_cc__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_LSR_S_SSB, model_A5_lsr_s_ssb, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_I16_GO_LSRM_S_GO, model_A5_I16_GO_LSRM_s_go, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ASR_L_S12__RA_, model_A5_asr_L_s12__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ASR_CCU6__RA_, model_A5_asr_ccu6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ASR_L_U6__RA_, model_A5_asr_L_u6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ASR_L_R_R__RA__RC, model_A5_asr_L_r_r__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ASR_CC__RA__RC, model_A5_asr_cc__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ASR_S_CBU3, model_A5_asr_s_cbu3, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ASR_S_SSB, model_A5_asr_s_ssb, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_I16_GO_ASRM_S_GO, model_A5_I16_GO_ASRM_s_go, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ROR_L_S12__RA_, model_A5_ror_L_s12__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ROR_CCU6__RA_, model_A5_ror_ccu6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ROR_L_U6__RA_, model_A5_ror_L_u6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ROR_L_R_R__RA__RC, model_A5_ror_L_r_r__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ROR_CC__RA__RC, model_A5_ror_cc__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MUL64_L_S12_, model_A5_mul64_L_s12_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MUL64_CCU6_, model_A5_mul64_ccu6_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MUL64_L_U6_, model_A5_mul64_L_u6_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MUL64_L_R_R__RC, model_A5_mul64_L_r_r__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MUL64_CC__RC, model_A5_mul64_cc__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MUL64_S_GO, model_A5_mul64_s_go, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MULU64_L_S12_, model_A5_mulu64_L_s12_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MULU64_CCU6_, model_A5_mulu64_ccu6_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MULU64_L_U6_, model_A5_mulu64_L_u6_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MULU64_L_R_R__RC, model_A5_mulu64_L_r_r__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MULU64_CC__RC, model_A5_mulu64_cc__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ADDS_L_S12__RA_, model_A5_adds_L_s12__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ADDS_CCU6__RA_, model_A5_adds_ccu6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ADDS_L_U6__RA_, model_A5_adds_L_u6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ADDS_L_R_R__RA__RC, model_A5_adds_L_r_r__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ADDS_CC__RA__RC, model_A5_adds_cc__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SUBS_L_S12__RA_, model_A5_subs_L_s12__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SUBS_CCU6__RA_, model_A5_subs_ccu6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SUBS_L_U6__RA_, model_A5_subs_L_u6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SUBS_L_R_R__RA__RC, model_A5_subs_L_r_r__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SUBS_CC__RA__RC, model_A5_subs_cc__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_DIVAW_L_S12__RA_, model_A5_divaw_L_s12__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_DIVAW_CCU6__RA_, model_A5_divaw_ccu6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_DIVAW_L_U6__RA_, model_A5_divaw_L_u6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_DIVAW_L_R_R__RA__RC, model_A5_divaw_L_r_r__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_DIVAW_CC__RA__RC, model_A5_divaw_cc__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ASLS_L_S12__RA_, model_A5_asls_L_s12__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ASLS_CCU6__RA_, model_A5_asls_ccu6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ASLS_L_U6__RA_, model_A5_asls_L_u6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ASLS_L_R_R__RA__RC, model_A5_asls_L_r_r__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ASLS_CC__RA__RC, model_A5_asls_cc__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ASRS_L_S12__RA_, model_A5_asrs_L_s12__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ASRS_CCU6__RA_, model_A5_asrs_ccu6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ASRS_L_U6__RA_, model_A5_asrs_L_u6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ASRS_L_R_R__RA__RC, model_A5_asrs_L_r_r__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ASRS_CC__RA__RC, model_A5_asrs_cc__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ADDSDW_L_S12__RA_, model_A5_addsdw_L_s12__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ADDSDW_CCU6__RA_, model_A5_addsdw_ccu6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ADDSDW_L_U6__RA_, model_A5_addsdw_L_u6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ADDSDW_L_R_R__RA__RC, model_A5_addsdw_L_r_r__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ADDSDW_CC__RA__RC, model_A5_addsdw_cc__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SUBSDW_L_S12__RA_, model_A5_subsdw_L_s12__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SUBSDW_CCU6__RA_, model_A5_subsdw_ccu6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SUBSDW_L_U6__RA_, model_A5_subsdw_L_u6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SUBSDW_L_R_R__RA__RC, model_A5_subsdw_L_r_r__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SUBSDW_CC__RA__RC, model_A5_subsdw_cc__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SWAP_L_R_R__RC, model_A5_swap_L_r_r__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_SWAP_L_U6_, model_A5_swap_L_u6_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_NORM_L_R_R__RC, model_A5_norm_L_r_r__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_NORM_L_U6_, model_A5_norm_L_u6_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_RND16_L_R_R__RC, model_A5_rnd16_L_r_r__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_RND16_L_U6_, model_A5_rnd16_L_u6_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ABSSW_L_R_R__RC, model_A5_abssw_L_r_r__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ABSSW_L_U6_, model_A5_abssw_L_u6_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ABSS_L_R_R__RC, model_A5_abss_L_r_r__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ABSS_L_U6_, model_A5_abss_L_u6_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_NEGSW_L_R_R__RC, model_A5_negsw_L_r_r__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_NEGSW_L_U6_, model_A5_negsw_L_u6_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_NEGS_L_R_R__RC, model_A5_negs_L_r_r__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_NEGS_L_U6_, model_A5_negs_L_u6_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_NORMW_L_R_R__RC, model_A5_normw_L_r_r__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_NORMW_L_U6_, model_A5_normw_L_u6_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_NOP_S, model_A5_nop_s, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_UNIMP_S, model_A5_unimp_s, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_POP_S_B, model_A5_pop_s_b, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_POP_S_BLINK, model_A5_pop_s_blink, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_PUSH_S_B, model_A5_push_s_b, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_PUSH_S_BLINK, model_A5_push_s_blink, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MULLW_L_S12__RA_, model_A5_mullw_L_s12__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MULLW_CCU6__RA_, model_A5_mullw_ccu6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MULLW_L_U6__RA_, model_A5_mullw_L_u6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MULLW_L_R_R__RA__RC, model_A5_mullw_L_r_r__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MULLW_CC__RA__RC, model_A5_mullw_cc__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MACLW_L_S12__RA_, model_A5_maclw_L_s12__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MACLW_CCU6__RA_, model_A5_maclw_ccu6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MACLW_L_U6__RA_, model_A5_maclw_L_u6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MACLW_L_R_R__RA__RC, model_A5_maclw_L_r_r__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MACLW_CC__RA__RC, model_A5_maclw_cc__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MACHLW_L_S12__RA_, model_A5_machlw_L_s12__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MACHLW_CCU6__RA_, model_A5_machlw_ccu6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MACHLW_L_U6__RA_, model_A5_machlw_L_u6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MACHLW_L_R_R__RA__RC, model_A5_machlw_L_r_r__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MACHLW_CC__RA__RC, model_A5_machlw_cc__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MULULW_L_S12__RA_, model_A5_mululw_L_s12__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MULULW_CCU6__RA_, model_A5_mululw_ccu6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MULULW_L_U6__RA_, model_A5_mululw_L_u6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MULULW_L_R_R__RA__RC, model_A5_mululw_L_r_r__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MULULW_CC__RA__RC, model_A5_mululw_cc__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MACHULW_L_S12__RA_, model_A5_machulw_L_s12__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MACHULW_CCU6__RA_, model_A5_machulw_ccu6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MACHULW_L_U6__RA_, model_A5_machulw_L_u6__RA_, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MACHULW_L_R_R__RA__RC, model_A5_machulw_L_r_r__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_MACHULW_CC__RA__RC, model_A5_machulw_cc__RA__RC, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_CURRENT_LOOP_END, model_A5_current_loop_end, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_CURRENT_LOOP_END_AFTER_BRANCH, model_A5_current_loop_end_after_branch, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+ { A5F_INSN_ARC600_CURRENT_LOOP_END_AFTER_BRANCH, model_A5_arc600_current_loop_end_after_branch, { { (int) UNIT_A5_U_EXEC, 1, 1 } } },
+};
+
+#endif /* WITH_PROFILE_MODEL_P */
+
+static void
+A5_model_init (SIM_CPU *cpu)
+{
+ CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_A5_DATA));
+}
+
+#if WITH_PROFILE_MODEL_P
+#define TIMING_DATA(td) td
+#else
+#define TIMING_DATA(td) 0
+#endif
+
+static const MODEL a5_models[] =
+{
+ { "A5", & a5_mach, MODEL_A5, TIMING_DATA (& A5_timing[0]), A5_model_init },
+ { 0 }
+};
+
+/* The properties of this cpu's implementation. */
+
+static const MACH_IMP_PROPERTIES a5f_imp_properties =
+{
+ sizeof (SIM_CPU),
+#if WITH_SCACHE
+ sizeof (SCACHE)
+#else
+ 0
+#endif
+};
+
+
+static void
+a5f_prepare_run (SIM_CPU *cpu)
+{
+ if (CPU_IDESC (cpu) == NULL)
+ a5f_init_idesc_table (cpu);
+}
+
+static const CGEN_INSN *
+a5f_get_idata (SIM_CPU *cpu, int inum)
+{
+ return CPU_IDESC (cpu) [inum].idata;
+}
+
+static void
+a5_init_cpu (SIM_CPU *cpu)
+{
+ CPU_REG_FETCH (cpu) = a5f_fetch_register;
+ CPU_REG_STORE (cpu) = a5f_store_register;
+ CPU_PC_FETCH (cpu) = a5f_h_pc_get;
+ CPU_PC_STORE (cpu) = a5f_h_pc_set;
+ CPU_GET_IDATA (cpu) = a5f_get_idata;
+ CPU_MAX_INSNS (cpu) = A5F_INSN__MAX;
+ CPU_INSN_NAME (cpu) = cgen_insn_name;
+ CPU_FULL_ENGINE_FN (cpu) = a5f_engine_run_full;
+#if WITH_FAST
+ CPU_FAST_ENGINE_FN (cpu) = a5f_engine_run_fast;
+#else
+ CPU_FAST_ENGINE_FN (cpu) = a5f_engine_run_full;
+#endif
+}
+
+const MACH a5_mach =
+{
+ "a5", "A5", MACH_A5,
+ 32, 32, & a5_models[0], & a5f_imp_properties,
+ a5_init_cpu,
+ a5f_prepare_run
+};
+
diff --git a/sim/arc/model6.c b/sim/arc/model6.c
new file mode 100644
index 0000000..c4fbf7d
--- /dev/null
+++ b/sim/arc/model6.c
@@ -0,0 +1,9522 @@
+/* Simulator model support for arc600f.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2007 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#define WANT_CPU arc600f
+#define WANT_CPU_ARC600F
+
+#include "sim-main.h"
+
+/* The profiling data is recorded here, but is accessed via the profiling
+ mechanism. After all, this is information for profiling. */
+
+#if WITH_PROFILE_MODEL_P
+
+/* Model handlers for each insn. */
+
+static int
+model_ARC600_b_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_b_s.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_bcc_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bcc_s.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_brcc_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_brcc_s.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_bcc_l (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bcc_l.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_bcc_l_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bcc_l.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_b_l (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_b_l.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_b_l_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_b_l.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_brcc_RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_brcc_RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_brcc_RC_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_brcc_RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_brcc_U6 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_brcc_U6.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_brcc_U6_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_brcc_U6.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_bl_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bl_s.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_blcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_blcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_blcc_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_blcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_bl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bl.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_bl_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bl.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ld_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ld__AW_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ld_ab_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ld_as_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ld_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ld__AW_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ld_ab_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ld_as_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ld_s_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ld_s_abu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ld_s_absp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ld_s_gprel (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_gprel.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ld_s_pcrel (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_pcrel.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ldb_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ldb__AW_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ldb_ab_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ldb_as_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ldb_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ldb__AW_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ldb_ab_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ldb_as_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ldb_s_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ldb_s_abu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ldb_s_absp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ldb_s_gprel (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_gprel.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ldb_x_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ldb__AW_x_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ldb_ab_x_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ldb_as_x_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ldb_x_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ldb__AW_x_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ldb_ab_x_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ldb_as_x_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ldw_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ldw__AW_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ldw_ab_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ldw_as_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ldw_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ldw__AW_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ldw_ab_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ldw_as_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ldw_s_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ldw_s_abu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldw_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ldw_s_gprel (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldw_s_gprel.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ldw_x_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ldw__AW_x_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ldw_ab_x_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ldw_as_x_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ldw_x_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ldw__AW_x_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ldw_ab_x_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ldw_as_x_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ldw_s_x_abu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldw_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_st_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_st__AW_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_st_ab_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_st_as_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_st_s_abu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_st_s_absp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_stb_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_stb__AW_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_stb_ab_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_stb_as_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_stb_s_abu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_stb_s_absp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_stw_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_stw__AW_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_stw_ab_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_stw_as_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_stw_s_abu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldw_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_add_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_add_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_add_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_add_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_add_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_add_s_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_add_s_cbu3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_add_s_mcah (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_add_s_absp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_add_s_asspsp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_add_s_gp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_gprel.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_add_s_r_u7 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_r_u7.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_adc_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_adc_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_adc_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_adc_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_adc_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_sub_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_sub_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_sub_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_sub_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_sub_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_sub_s_cbu3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_I16_GO_SUB_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_sub_s_go_sub_ne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_sub_s_ssb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_sub_s_asspsp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_sbc_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_sbc_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_sbc_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_sbc_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_sbc_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_and_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_and_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_and_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_and_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_and_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_I16_GO_AND_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_or_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_or_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_or_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_or_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_or_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_I16_GO_OR_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_bic_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_bic_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_bic_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_bic_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_bic_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_I16_GO_BIC_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_xor_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_xor_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_xor_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_xor_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_xor_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_I16_GO_XOR_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_max_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_max_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_max_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_max_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_max_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_min_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_min_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_min_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_min_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_min_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mov_L_s12_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mov_ccu6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mov_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mov_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mov_cc__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mov_s_mcah (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mov_s_mcahb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mov_s_r_u7 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_tst_L_s12_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_tst_ccu6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_tst_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_tst_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_tst_cc__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_tst_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_cmp_L_s12_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_cmp_ccu6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_cmp_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_cmp_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_cmp_cc__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_cmp_s_mcah (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_cmp_s_r_u7 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_r_u7.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_rcmp_L_s12_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_rcmp_ccu6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_rcmp_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_rcmp_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_rcmp_cc__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_rsub_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_rsub_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_rsub_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_rsub_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_rsub_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_bset_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_bset_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_bset_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_bset_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_bset_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_bset_s_ssb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_bclr_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_bclr_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_bclr_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_bclr_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_bclr_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_bclr_s_ssb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_btst_L_s12_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_btst_ccu6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_btst_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_btst_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_btst_cc__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_btst_s_ssb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_bxor_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_bxor_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_bxor_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_bxor_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_bxor_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_bmsk_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_bmsk_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_bmsk_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_bmsk_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_bmsk_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_bmsk_s_ssb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_add1_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_add1_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_add1_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_add1_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_add1_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_I16_GO_ADD1_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_add2_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_add2_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_add2_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_add2_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_add2_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_I16_GO_ADD2_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_add3_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_add3_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_add3_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_add3_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_add3_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_I16_GO_ADD3_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_sub1_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_sub1_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_sub1_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_sub1_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_sub1_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_sub2_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_sub2_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_sub2_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_sub2_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_sub2_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_sub3_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_sub3_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_sub3_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_sub3_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_sub3_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mpy_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mpy_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mpy_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mpy_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mpy_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mpyh_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mpyh_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mpyh_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mpyh_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mpyh_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mpyhu_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mpyhu_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mpyhu_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mpyhu_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mpyhu_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mpyu_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mpyu_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mpyu_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mpyu_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mpyu_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_j_L_r_r___RC_noilink_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_j_cc___RC_noilink_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_j_L_r_r___RC_ilink_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_j_cc___RC_ilink_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_j_L_s12_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_j_ccu6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_j_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_j_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_j_s__S (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_j_seq__S (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_j_sne__S (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_j_L_s12_d_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_j_ccu6_d_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_j_L_u6_d_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_j_L_r_r_d___RC_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_j_cc_d___RC_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_j_s_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_j_s__S_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_jl_L_s12_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_jl_ccu6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_jl_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_jl_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_jl_L_r_r___RC_noilink_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_jl_cc___RC_noilink_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_jl_L_s12_d_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_jl_ccu6_d_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_jl_L_u6_d_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_jl_L_r_r_d___RC_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_jl_cc_d___RC_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_jl_s_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_lp_L_s12_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lp_L_s12_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_lpcc_ccu6 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lpcc_ccu6.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_flag_L_s12_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_flag_ccu6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_flag_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_flag_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_flag_cc__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_lr_L_r_r___RC_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_lr_L_s12_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_lr_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_sr_L_r_r___RC_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_sr_L_s12_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_sr_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_asl_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_asl_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_I16_GO_ASL_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_asr_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_asr_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_I16_GO_ASR_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_lsr_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_lsr_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_I16_GO_LSR_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ror_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ror_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_rrc_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_rrc_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_sexb_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_sexb_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_I16_GO_SEXB_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_sexw_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_sexw_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_I16_GO_SEXW_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_extb_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_extb_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_I16_GO_EXTB_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_extw_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_extw_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_I16_GO_EXTW_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_abs_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_abs_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_I16_GO_ABS_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_not_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_not_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_I16_GO_NOT_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_rlc_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_rlc_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_I16_GO_NEG_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_swi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_trap_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_trap_s.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_brk (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_brk_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_asl_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_asl_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_asl_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_asl_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_asl_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_asl_s_cbu3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_asl_s_ssb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_I16_GO_ASLM_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_lsr_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_lsr_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_lsr_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_lsr_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_lsr_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_lsr_s_ssb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_I16_GO_LSRM_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_asr_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_asr_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_asr_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_asr_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_asr_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_asr_s_cbu3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_asr_s_ssb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_I16_GO_ASRM_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ror_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ror_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ror_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ror_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_ror_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mul64_L_s12_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mul64_ccu6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mul64_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mul64_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mul64_cc__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mul64_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mulu64_L_s12_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mulu64_ccu6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mulu64_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mulu64_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mulu64_cc__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_adds_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_adds_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_adds_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_adds_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_adds_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_subs_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_subs_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_subs_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_subs_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_subs_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_divaw_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_divaw_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_divaw_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_divaw_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_divaw_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_asls_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_asls_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_asls_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_asls_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_asls_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_asrs_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_asrs_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_asrs_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_asrs_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_asrs_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_addsdw_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_addsdw_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_addsdw_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_addsdw_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_addsdw_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_subsdw_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_subsdw_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_subsdw_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_subsdw_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_subsdw_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_swap_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_swap_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_norm_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_norm_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_rnd16_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_rnd16_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_abssw_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_abssw_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_abss_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_abss_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_negsw_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_negsw_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_negs_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_negs_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_normw_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_normw_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_nop_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_unimp_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_pop_s_b (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_pop_s_blink (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_push_s_b (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_push_s_blink (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mullw_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mullw_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mullw_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mullw_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mullw_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_maclw_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_maclw_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_maclw_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_maclw_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_maclw_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_machlw_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_machlw_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_machlw_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_machlw_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_machlw_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mululw_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mululw_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mululw_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mululw_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_mululw_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_machulw_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_machulw_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_machulw_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_machulw_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_machulw_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_current_loop_end (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_current_loop_end_after_branch (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC600_arc600_current_loop_end_after_branch (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc600f_model_ARC600_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+/* We assume UNIT_NONE == 0 because the tables don't always terminate
+ entries with it. */
+
+/* Model timing data for `ARC600'. */
+
+static const INSN_TIMING ARC600_timing[] = {
+ { ARC600F_INSN_X_INVALID, 0, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_X_AFTER, 0, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_X_BEFORE, 0, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_X_CHAIN, 0, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_X_BEGIN, 0, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_B_S, model_ARC600_b_s, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BCC_S, model_ARC600_bcc_s, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BRCC_S, model_ARC600_brcc_s, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BCC_L, model_ARC600_bcc_l, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BCC_L_D, model_ARC600_bcc_l_d, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_B_L, model_ARC600_b_l, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_B_L_D, model_ARC600_b_l_d, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BRCC_RC, model_ARC600_brcc_RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BRCC_RC_D, model_ARC600_brcc_RC_d, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BRCC_U6, model_ARC600_brcc_U6, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BRCC_U6_D, model_ARC600_brcc_U6_d, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BL_S, model_ARC600_bl_s, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BLCC, model_ARC600_blcc, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BLCC_D, model_ARC600_blcc_d, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BL, model_ARC600_bl, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BL_D, model_ARC600_bl_d, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LD_ABS, model_ARC600_ld_abs, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LD__AW_ABS, model_ARC600_ld__AW_abs, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LD_AB_ABS, model_ARC600_ld_ab_abs, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LD_AS_ABS, model_ARC600_ld_as_abs, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LD_ABC, model_ARC600_ld_abc, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LD__AW_ABC, model_ARC600_ld__AW_abc, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LD_AB_ABC, model_ARC600_ld_ab_abc, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LD_AS_ABC, model_ARC600_ld_as_abc, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LD_S_ABC, model_ARC600_ld_s_abc, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LD_S_ABU, model_ARC600_ld_s_abu, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LD_S_ABSP, model_ARC600_ld_s_absp, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LD_S_GPREL, model_ARC600_ld_s_gprel, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LD_S_PCREL, model_ARC600_ld_s_pcrel, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LDB_ABS, model_ARC600_ldb_abs, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LDB__AW_ABS, model_ARC600_ldb__AW_abs, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LDB_AB_ABS, model_ARC600_ldb_ab_abs, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LDB_AS_ABS, model_ARC600_ldb_as_abs, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LDB_ABC, model_ARC600_ldb_abc, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LDB__AW_ABC, model_ARC600_ldb__AW_abc, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LDB_AB_ABC, model_ARC600_ldb_ab_abc, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LDB_AS_ABC, model_ARC600_ldb_as_abc, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LDB_S_ABC, model_ARC600_ldb_s_abc, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LDB_S_ABU, model_ARC600_ldb_s_abu, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LDB_S_ABSP, model_ARC600_ldb_s_absp, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LDB_S_GPREL, model_ARC600_ldb_s_gprel, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LDB_X_ABS, model_ARC600_ldb_x_abs, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LDB__AW_X_ABS, model_ARC600_ldb__AW_x_abs, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LDB_AB_X_ABS, model_ARC600_ldb_ab_x_abs, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LDB_AS_X_ABS, model_ARC600_ldb_as_x_abs, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LDB_X_ABC, model_ARC600_ldb_x_abc, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LDB__AW_X_ABC, model_ARC600_ldb__AW_x_abc, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LDB_AB_X_ABC, model_ARC600_ldb_ab_x_abc, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LDB_AS_X_ABC, model_ARC600_ldb_as_x_abc, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LDW_ABS, model_ARC600_ldw_abs, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LDW__AW_ABS, model_ARC600_ldw__AW_abs, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LDW_AB_ABS, model_ARC600_ldw_ab_abs, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LDW_AS_ABS, model_ARC600_ldw_as_abs, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LDW_ABC, model_ARC600_ldw_abc, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LDW__AW_ABC, model_ARC600_ldw__AW_abc, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LDW_AB_ABC, model_ARC600_ldw_ab_abc, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LDW_AS_ABC, model_ARC600_ldw_as_abc, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LDW_S_ABC, model_ARC600_ldw_s_abc, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LDW_S_ABU, model_ARC600_ldw_s_abu, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LDW_S_GPREL, model_ARC600_ldw_s_gprel, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LDW_X_ABS, model_ARC600_ldw_x_abs, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LDW__AW_X_ABS, model_ARC600_ldw__AW_x_abs, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LDW_AB_X_ABS, model_ARC600_ldw_ab_x_abs, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LDW_AS_X_ABS, model_ARC600_ldw_as_x_abs, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LDW_X_ABC, model_ARC600_ldw_x_abc, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LDW__AW_X_ABC, model_ARC600_ldw__AW_x_abc, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LDW_AB_X_ABC, model_ARC600_ldw_ab_x_abc, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LDW_AS_X_ABC, model_ARC600_ldw_as_x_abc, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LDW_S_X_ABU, model_ARC600_ldw_s_x_abu, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ST_ABS, model_ARC600_st_abs, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ST__AW_ABS, model_ARC600_st__AW_abs, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ST_AB_ABS, model_ARC600_st_ab_abs, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ST_AS_ABS, model_ARC600_st_as_abs, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ST_S_ABU, model_ARC600_st_s_abu, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ST_S_ABSP, model_ARC600_st_s_absp, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_STB_ABS, model_ARC600_stb_abs, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_STB__AW_ABS, model_ARC600_stb__AW_abs, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_STB_AB_ABS, model_ARC600_stb_ab_abs, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_STB_AS_ABS, model_ARC600_stb_as_abs, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_STB_S_ABU, model_ARC600_stb_s_abu, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_STB_S_ABSP, model_ARC600_stb_s_absp, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_STW_ABS, model_ARC600_stw_abs, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_STW__AW_ABS, model_ARC600_stw__AW_abs, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_STW_AB_ABS, model_ARC600_stw_ab_abs, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_STW_AS_ABS, model_ARC600_stw_as_abs, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_STW_S_ABU, model_ARC600_stw_s_abu, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ADD_L_S12__RA_, model_ARC600_add_L_s12__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ADD_CCU6__RA_, model_ARC600_add_ccu6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ADD_L_U6__RA_, model_ARC600_add_L_u6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ADD_L_R_R__RA__RC, model_ARC600_add_L_r_r__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ADD_CC__RA__RC, model_ARC600_add_cc__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ADD_S_ABC, model_ARC600_add_s_abc, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ADD_S_CBU3, model_ARC600_add_s_cbu3, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ADD_S_MCAH, model_ARC600_add_s_mcah, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ADD_S_ABSP, model_ARC600_add_s_absp, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ADD_S_ASSPSP, model_ARC600_add_s_asspsp, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ADD_S_GP, model_ARC600_add_s_gp, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ADD_S_R_U7, model_ARC600_add_s_r_u7, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ADC_L_S12__RA_, model_ARC600_adc_L_s12__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ADC_CCU6__RA_, model_ARC600_adc_ccu6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ADC_L_U6__RA_, model_ARC600_adc_L_u6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ADC_L_R_R__RA__RC, model_ARC600_adc_L_r_r__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ADC_CC__RA__RC, model_ARC600_adc_cc__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SUB_L_S12__RA_, model_ARC600_sub_L_s12__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SUB_CCU6__RA_, model_ARC600_sub_ccu6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SUB_L_U6__RA_, model_ARC600_sub_L_u6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SUB_L_R_R__RA__RC, model_ARC600_sub_L_r_r__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SUB_CC__RA__RC, model_ARC600_sub_cc__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SUB_S_CBU3, model_ARC600_sub_s_cbu3, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_I16_GO_SUB_S_GO, model_ARC600_I16_GO_SUB_s_go, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SUB_S_GO_SUB_NE, model_ARC600_sub_s_go_sub_ne, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SUB_S_SSB, model_ARC600_sub_s_ssb, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SUB_S_ASSPSP, model_ARC600_sub_s_asspsp, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SBC_L_S12__RA_, model_ARC600_sbc_L_s12__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SBC_CCU6__RA_, model_ARC600_sbc_ccu6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SBC_L_U6__RA_, model_ARC600_sbc_L_u6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SBC_L_R_R__RA__RC, model_ARC600_sbc_L_r_r__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SBC_CC__RA__RC, model_ARC600_sbc_cc__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_AND_L_S12__RA_, model_ARC600_and_L_s12__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_AND_CCU6__RA_, model_ARC600_and_ccu6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_AND_L_U6__RA_, model_ARC600_and_L_u6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_AND_L_R_R__RA__RC, model_ARC600_and_L_r_r__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_AND_CC__RA__RC, model_ARC600_and_cc__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_I16_GO_AND_S_GO, model_ARC600_I16_GO_AND_s_go, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_OR_L_S12__RA_, model_ARC600_or_L_s12__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_OR_CCU6__RA_, model_ARC600_or_ccu6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_OR_L_U6__RA_, model_ARC600_or_L_u6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_OR_L_R_R__RA__RC, model_ARC600_or_L_r_r__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_OR_CC__RA__RC, model_ARC600_or_cc__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_I16_GO_OR_S_GO, model_ARC600_I16_GO_OR_s_go, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BIC_L_S12__RA_, model_ARC600_bic_L_s12__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BIC_CCU6__RA_, model_ARC600_bic_ccu6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BIC_L_U6__RA_, model_ARC600_bic_L_u6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BIC_L_R_R__RA__RC, model_ARC600_bic_L_r_r__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BIC_CC__RA__RC, model_ARC600_bic_cc__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_I16_GO_BIC_S_GO, model_ARC600_I16_GO_BIC_s_go, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_XOR_L_S12__RA_, model_ARC600_xor_L_s12__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_XOR_CCU6__RA_, model_ARC600_xor_ccu6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_XOR_L_U6__RA_, model_ARC600_xor_L_u6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_XOR_L_R_R__RA__RC, model_ARC600_xor_L_r_r__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_XOR_CC__RA__RC, model_ARC600_xor_cc__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_I16_GO_XOR_S_GO, model_ARC600_I16_GO_XOR_s_go, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MAX_L_S12__RA_, model_ARC600_max_L_s12__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MAX_CCU6__RA_, model_ARC600_max_ccu6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MAX_L_U6__RA_, model_ARC600_max_L_u6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MAX_L_R_R__RA__RC, model_ARC600_max_L_r_r__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MAX_CC__RA__RC, model_ARC600_max_cc__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MIN_L_S12__RA_, model_ARC600_min_L_s12__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MIN_CCU6__RA_, model_ARC600_min_ccu6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MIN_L_U6__RA_, model_ARC600_min_L_u6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MIN_L_R_R__RA__RC, model_ARC600_min_L_r_r__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MIN_CC__RA__RC, model_ARC600_min_cc__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MOV_L_S12_, model_ARC600_mov_L_s12_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MOV_CCU6_, model_ARC600_mov_ccu6_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MOV_L_U6_, model_ARC600_mov_L_u6_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MOV_L_R_R__RC, model_ARC600_mov_L_r_r__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MOV_CC__RC, model_ARC600_mov_cc__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MOV_S_MCAH, model_ARC600_mov_s_mcah, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MOV_S_MCAHB, model_ARC600_mov_s_mcahb, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MOV_S_R_U7, model_ARC600_mov_s_r_u7, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_TST_L_S12_, model_ARC600_tst_L_s12_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_TST_CCU6_, model_ARC600_tst_ccu6_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_TST_L_U6_, model_ARC600_tst_L_u6_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_TST_L_R_R__RC, model_ARC600_tst_L_r_r__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_TST_CC__RC, model_ARC600_tst_cc__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_TST_S_GO, model_ARC600_tst_s_go, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_CMP_L_S12_, model_ARC600_cmp_L_s12_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_CMP_CCU6_, model_ARC600_cmp_ccu6_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_CMP_L_U6_, model_ARC600_cmp_L_u6_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_CMP_L_R_R__RC, model_ARC600_cmp_L_r_r__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_CMP_CC__RC, model_ARC600_cmp_cc__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_CMP_S_MCAH, model_ARC600_cmp_s_mcah, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_CMP_S_R_U7, model_ARC600_cmp_s_r_u7, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_RCMP_L_S12_, model_ARC600_rcmp_L_s12_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_RCMP_CCU6_, model_ARC600_rcmp_ccu6_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_RCMP_L_U6_, model_ARC600_rcmp_L_u6_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_RCMP_L_R_R__RC, model_ARC600_rcmp_L_r_r__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_RCMP_CC__RC, model_ARC600_rcmp_cc__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_RSUB_L_S12__RA_, model_ARC600_rsub_L_s12__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_RSUB_CCU6__RA_, model_ARC600_rsub_ccu6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_RSUB_L_U6__RA_, model_ARC600_rsub_L_u6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_RSUB_L_R_R__RA__RC, model_ARC600_rsub_L_r_r__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_RSUB_CC__RA__RC, model_ARC600_rsub_cc__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BSET_L_S12__RA_, model_ARC600_bset_L_s12__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BSET_CCU6__RA_, model_ARC600_bset_ccu6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BSET_L_U6__RA_, model_ARC600_bset_L_u6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BSET_L_R_R__RA__RC, model_ARC600_bset_L_r_r__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BSET_CC__RA__RC, model_ARC600_bset_cc__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BSET_S_SSB, model_ARC600_bset_s_ssb, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BCLR_L_S12__RA_, model_ARC600_bclr_L_s12__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BCLR_CCU6__RA_, model_ARC600_bclr_ccu6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BCLR_L_U6__RA_, model_ARC600_bclr_L_u6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BCLR_L_R_R__RA__RC, model_ARC600_bclr_L_r_r__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BCLR_CC__RA__RC, model_ARC600_bclr_cc__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BCLR_S_SSB, model_ARC600_bclr_s_ssb, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BTST_L_S12_, model_ARC600_btst_L_s12_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BTST_CCU6_, model_ARC600_btst_ccu6_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BTST_L_U6_, model_ARC600_btst_L_u6_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BTST_L_R_R__RC, model_ARC600_btst_L_r_r__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BTST_CC__RC, model_ARC600_btst_cc__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BTST_S_SSB, model_ARC600_btst_s_ssb, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BXOR_L_S12__RA_, model_ARC600_bxor_L_s12__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BXOR_CCU6__RA_, model_ARC600_bxor_ccu6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BXOR_L_U6__RA_, model_ARC600_bxor_L_u6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BXOR_L_R_R__RA__RC, model_ARC600_bxor_L_r_r__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BXOR_CC__RA__RC, model_ARC600_bxor_cc__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BMSK_L_S12__RA_, model_ARC600_bmsk_L_s12__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BMSK_CCU6__RA_, model_ARC600_bmsk_ccu6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BMSK_L_U6__RA_, model_ARC600_bmsk_L_u6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BMSK_L_R_R__RA__RC, model_ARC600_bmsk_L_r_r__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BMSK_CC__RA__RC, model_ARC600_bmsk_cc__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BMSK_S_SSB, model_ARC600_bmsk_s_ssb, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ADD1_L_S12__RA_, model_ARC600_add1_L_s12__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ADD1_CCU6__RA_, model_ARC600_add1_ccu6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ADD1_L_U6__RA_, model_ARC600_add1_L_u6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ADD1_L_R_R__RA__RC, model_ARC600_add1_L_r_r__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ADD1_CC__RA__RC, model_ARC600_add1_cc__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_I16_GO_ADD1_S_GO, model_ARC600_I16_GO_ADD1_s_go, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ADD2_L_S12__RA_, model_ARC600_add2_L_s12__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ADD2_CCU6__RA_, model_ARC600_add2_ccu6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ADD2_L_U6__RA_, model_ARC600_add2_L_u6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ADD2_L_R_R__RA__RC, model_ARC600_add2_L_r_r__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ADD2_CC__RA__RC, model_ARC600_add2_cc__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_I16_GO_ADD2_S_GO, model_ARC600_I16_GO_ADD2_s_go, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ADD3_L_S12__RA_, model_ARC600_add3_L_s12__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ADD3_CCU6__RA_, model_ARC600_add3_ccu6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ADD3_L_U6__RA_, model_ARC600_add3_L_u6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ADD3_L_R_R__RA__RC, model_ARC600_add3_L_r_r__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ADD3_CC__RA__RC, model_ARC600_add3_cc__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_I16_GO_ADD3_S_GO, model_ARC600_I16_GO_ADD3_s_go, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SUB1_L_S12__RA_, model_ARC600_sub1_L_s12__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SUB1_CCU6__RA_, model_ARC600_sub1_ccu6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SUB1_L_U6__RA_, model_ARC600_sub1_L_u6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SUB1_L_R_R__RA__RC, model_ARC600_sub1_L_r_r__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SUB1_CC__RA__RC, model_ARC600_sub1_cc__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SUB2_L_S12__RA_, model_ARC600_sub2_L_s12__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SUB2_CCU6__RA_, model_ARC600_sub2_ccu6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SUB2_L_U6__RA_, model_ARC600_sub2_L_u6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SUB2_L_R_R__RA__RC, model_ARC600_sub2_L_r_r__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SUB2_CC__RA__RC, model_ARC600_sub2_cc__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SUB3_L_S12__RA_, model_ARC600_sub3_L_s12__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SUB3_CCU6__RA_, model_ARC600_sub3_ccu6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SUB3_L_U6__RA_, model_ARC600_sub3_L_u6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SUB3_L_R_R__RA__RC, model_ARC600_sub3_L_r_r__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SUB3_CC__RA__RC, model_ARC600_sub3_cc__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MPY_L_S12__RA_, model_ARC600_mpy_L_s12__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MPY_CCU6__RA_, model_ARC600_mpy_ccu6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MPY_L_U6__RA_, model_ARC600_mpy_L_u6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MPY_L_R_R__RA__RC, model_ARC600_mpy_L_r_r__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MPY_CC__RA__RC, model_ARC600_mpy_cc__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MPYH_L_S12__RA_, model_ARC600_mpyh_L_s12__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MPYH_CCU6__RA_, model_ARC600_mpyh_ccu6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MPYH_L_U6__RA_, model_ARC600_mpyh_L_u6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MPYH_L_R_R__RA__RC, model_ARC600_mpyh_L_r_r__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MPYH_CC__RA__RC, model_ARC600_mpyh_cc__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MPYHU_L_S12__RA_, model_ARC600_mpyhu_L_s12__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MPYHU_CCU6__RA_, model_ARC600_mpyhu_ccu6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MPYHU_L_U6__RA_, model_ARC600_mpyhu_L_u6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MPYHU_L_R_R__RA__RC, model_ARC600_mpyhu_L_r_r__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MPYHU_CC__RA__RC, model_ARC600_mpyhu_cc__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MPYU_L_S12__RA_, model_ARC600_mpyu_L_s12__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MPYU_CCU6__RA_, model_ARC600_mpyu_ccu6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MPYU_L_U6__RA_, model_ARC600_mpyu_L_u6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MPYU_L_R_R__RA__RC, model_ARC600_mpyu_L_r_r__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MPYU_CC__RA__RC, model_ARC600_mpyu_cc__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_J_L_R_R___RC_NOILINK_, model_ARC600_j_L_r_r___RC_noilink_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_J_CC___RC_NOILINK_, model_ARC600_j_cc___RC_noilink_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_J_L_R_R___RC_ILINK_, model_ARC600_j_L_r_r___RC_ilink_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_J_CC___RC_ILINK_, model_ARC600_j_cc___RC_ilink_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_J_L_S12_, model_ARC600_j_L_s12_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_J_CCU6_, model_ARC600_j_ccu6_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_J_L_U6_, model_ARC600_j_L_u6_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_J_S, model_ARC600_j_s, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_J_S__S, model_ARC600_j_s__S, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_J_SEQ__S, model_ARC600_j_seq__S, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_J_SNE__S, model_ARC600_j_sne__S, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_J_L_S12_D_, model_ARC600_j_L_s12_d_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_J_CCU6_D_, model_ARC600_j_ccu6_d_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_J_L_U6_D_, model_ARC600_j_L_u6_d_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_J_L_R_R_D___RC_, model_ARC600_j_L_r_r_d___RC_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_J_CC_D___RC_, model_ARC600_j_cc_d___RC_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_J_S_D, model_ARC600_j_s_d, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_J_S__S_D, model_ARC600_j_s__S_d, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_JL_L_S12_, model_ARC600_jl_L_s12_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_JL_CCU6_, model_ARC600_jl_ccu6_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_JL_L_U6_, model_ARC600_jl_L_u6_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_JL_S, model_ARC600_jl_s, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_JL_L_R_R___RC_NOILINK_, model_ARC600_jl_L_r_r___RC_noilink_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_JL_CC___RC_NOILINK_, model_ARC600_jl_cc___RC_noilink_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_JL_L_S12_D_, model_ARC600_jl_L_s12_d_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_JL_CCU6_D_, model_ARC600_jl_ccu6_d_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_JL_L_U6_D_, model_ARC600_jl_L_u6_d_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_JL_L_R_R_D___RC_, model_ARC600_jl_L_r_r_d___RC_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_JL_CC_D___RC_, model_ARC600_jl_cc_d___RC_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_JL_S_D, model_ARC600_jl_s_d, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LP_L_S12_, model_ARC600_lp_L_s12_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LPCC_CCU6, model_ARC600_lpcc_ccu6, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_FLAG_L_S12_, model_ARC600_flag_L_s12_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_FLAG_CCU6_, model_ARC600_flag_ccu6_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_FLAG_L_U6_, model_ARC600_flag_L_u6_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_FLAG_L_R_R__RC, model_ARC600_flag_L_r_r__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_FLAG_CC__RC, model_ARC600_flag_cc__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LR_L_R_R___RC_, model_ARC600_lr_L_r_r___RC_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LR_L_S12_, model_ARC600_lr_L_s12_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LR_L_U6_, model_ARC600_lr_L_u6_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SR_L_R_R___RC_, model_ARC600_sr_L_r_r___RC_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SR_L_S12_, model_ARC600_sr_L_s12_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SR_L_U6_, model_ARC600_sr_L_u6_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ASL_L_R_R__RC, model_ARC600_asl_L_r_r__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ASL_L_U6_, model_ARC600_asl_L_u6_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_I16_GO_ASL_S_GO, model_ARC600_I16_GO_ASL_s_go, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ASR_L_R_R__RC, model_ARC600_asr_L_r_r__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ASR_L_U6_, model_ARC600_asr_L_u6_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_I16_GO_ASR_S_GO, model_ARC600_I16_GO_ASR_s_go, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LSR_L_R_R__RC, model_ARC600_lsr_L_r_r__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LSR_L_U6_, model_ARC600_lsr_L_u6_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_I16_GO_LSR_S_GO, model_ARC600_I16_GO_LSR_s_go, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ROR_L_R_R__RC, model_ARC600_ror_L_r_r__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ROR_L_U6_, model_ARC600_ror_L_u6_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_RRC_L_R_R__RC, model_ARC600_rrc_L_r_r__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_RRC_L_U6_, model_ARC600_rrc_L_u6_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SEXB_L_R_R__RC, model_ARC600_sexb_L_r_r__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SEXB_L_U6_, model_ARC600_sexb_L_u6_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_I16_GO_SEXB_S_GO, model_ARC600_I16_GO_SEXB_s_go, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SEXW_L_R_R__RC, model_ARC600_sexw_L_r_r__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SEXW_L_U6_, model_ARC600_sexw_L_u6_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_I16_GO_SEXW_S_GO, model_ARC600_I16_GO_SEXW_s_go, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_EXTB_L_R_R__RC, model_ARC600_extb_L_r_r__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_EXTB_L_U6_, model_ARC600_extb_L_u6_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_I16_GO_EXTB_S_GO, model_ARC600_I16_GO_EXTB_s_go, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_EXTW_L_R_R__RC, model_ARC600_extw_L_r_r__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_EXTW_L_U6_, model_ARC600_extw_L_u6_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_I16_GO_EXTW_S_GO, model_ARC600_I16_GO_EXTW_s_go, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ABS_L_R_R__RC, model_ARC600_abs_L_r_r__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ABS_L_U6_, model_ARC600_abs_L_u6_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_I16_GO_ABS_S_GO, model_ARC600_I16_GO_ABS_s_go, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_NOT_L_R_R__RC, model_ARC600_not_L_r_r__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_NOT_L_U6_, model_ARC600_not_L_u6_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_I16_GO_NOT_S_GO, model_ARC600_I16_GO_NOT_s_go, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_RLC_L_R_R__RC, model_ARC600_rlc_L_r_r__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_RLC_L_U6_, model_ARC600_rlc_L_u6_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_I16_GO_NEG_S_GO, model_ARC600_I16_GO_NEG_s_go, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SWI, model_ARC600_swi, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_TRAP_S, model_ARC600_trap_s, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BRK, model_ARC600_brk, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_BRK_S, model_ARC600_brk_s, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ASL_L_S12__RA_, model_ARC600_asl_L_s12__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ASL_CCU6__RA_, model_ARC600_asl_ccu6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ASL_L_U6__RA_, model_ARC600_asl_L_u6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ASL_L_R_R__RA__RC, model_ARC600_asl_L_r_r__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ASL_CC__RA__RC, model_ARC600_asl_cc__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ASL_S_CBU3, model_ARC600_asl_s_cbu3, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ASL_S_SSB, model_ARC600_asl_s_ssb, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_I16_GO_ASLM_S_GO, model_ARC600_I16_GO_ASLM_s_go, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LSR_L_S12__RA_, model_ARC600_lsr_L_s12__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LSR_CCU6__RA_, model_ARC600_lsr_ccu6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LSR_L_U6__RA_, model_ARC600_lsr_L_u6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LSR_L_R_R__RA__RC, model_ARC600_lsr_L_r_r__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LSR_CC__RA__RC, model_ARC600_lsr_cc__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_LSR_S_SSB, model_ARC600_lsr_s_ssb, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_I16_GO_LSRM_S_GO, model_ARC600_I16_GO_LSRM_s_go, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ASR_L_S12__RA_, model_ARC600_asr_L_s12__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ASR_CCU6__RA_, model_ARC600_asr_ccu6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ASR_L_U6__RA_, model_ARC600_asr_L_u6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ASR_L_R_R__RA__RC, model_ARC600_asr_L_r_r__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ASR_CC__RA__RC, model_ARC600_asr_cc__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ASR_S_CBU3, model_ARC600_asr_s_cbu3, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ASR_S_SSB, model_ARC600_asr_s_ssb, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_I16_GO_ASRM_S_GO, model_ARC600_I16_GO_ASRM_s_go, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ROR_L_S12__RA_, model_ARC600_ror_L_s12__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ROR_CCU6__RA_, model_ARC600_ror_ccu6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ROR_L_U6__RA_, model_ARC600_ror_L_u6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ROR_L_R_R__RA__RC, model_ARC600_ror_L_r_r__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ROR_CC__RA__RC, model_ARC600_ror_cc__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MUL64_L_S12_, model_ARC600_mul64_L_s12_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MUL64_CCU6_, model_ARC600_mul64_ccu6_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MUL64_L_U6_, model_ARC600_mul64_L_u6_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MUL64_L_R_R__RC, model_ARC600_mul64_L_r_r__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MUL64_CC__RC, model_ARC600_mul64_cc__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MUL64_S_GO, model_ARC600_mul64_s_go, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MULU64_L_S12_, model_ARC600_mulu64_L_s12_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MULU64_CCU6_, model_ARC600_mulu64_ccu6_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MULU64_L_U6_, model_ARC600_mulu64_L_u6_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MULU64_L_R_R__RC, model_ARC600_mulu64_L_r_r__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MULU64_CC__RC, model_ARC600_mulu64_cc__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ADDS_L_S12__RA_, model_ARC600_adds_L_s12__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ADDS_CCU6__RA_, model_ARC600_adds_ccu6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ADDS_L_U6__RA_, model_ARC600_adds_L_u6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ADDS_L_R_R__RA__RC, model_ARC600_adds_L_r_r__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ADDS_CC__RA__RC, model_ARC600_adds_cc__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SUBS_L_S12__RA_, model_ARC600_subs_L_s12__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SUBS_CCU6__RA_, model_ARC600_subs_ccu6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SUBS_L_U6__RA_, model_ARC600_subs_L_u6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SUBS_L_R_R__RA__RC, model_ARC600_subs_L_r_r__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SUBS_CC__RA__RC, model_ARC600_subs_cc__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_DIVAW_L_S12__RA_, model_ARC600_divaw_L_s12__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_DIVAW_CCU6__RA_, model_ARC600_divaw_ccu6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_DIVAW_L_U6__RA_, model_ARC600_divaw_L_u6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_DIVAW_L_R_R__RA__RC, model_ARC600_divaw_L_r_r__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_DIVAW_CC__RA__RC, model_ARC600_divaw_cc__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ASLS_L_S12__RA_, model_ARC600_asls_L_s12__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ASLS_CCU6__RA_, model_ARC600_asls_ccu6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ASLS_L_U6__RA_, model_ARC600_asls_L_u6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ASLS_L_R_R__RA__RC, model_ARC600_asls_L_r_r__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ASLS_CC__RA__RC, model_ARC600_asls_cc__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ASRS_L_S12__RA_, model_ARC600_asrs_L_s12__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ASRS_CCU6__RA_, model_ARC600_asrs_ccu6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ASRS_L_U6__RA_, model_ARC600_asrs_L_u6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ASRS_L_R_R__RA__RC, model_ARC600_asrs_L_r_r__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ASRS_CC__RA__RC, model_ARC600_asrs_cc__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ADDSDW_L_S12__RA_, model_ARC600_addsdw_L_s12__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ADDSDW_CCU6__RA_, model_ARC600_addsdw_ccu6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ADDSDW_L_U6__RA_, model_ARC600_addsdw_L_u6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ADDSDW_L_R_R__RA__RC, model_ARC600_addsdw_L_r_r__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ADDSDW_CC__RA__RC, model_ARC600_addsdw_cc__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SUBSDW_L_S12__RA_, model_ARC600_subsdw_L_s12__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SUBSDW_CCU6__RA_, model_ARC600_subsdw_ccu6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SUBSDW_L_U6__RA_, model_ARC600_subsdw_L_u6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SUBSDW_L_R_R__RA__RC, model_ARC600_subsdw_L_r_r__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SUBSDW_CC__RA__RC, model_ARC600_subsdw_cc__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SWAP_L_R_R__RC, model_ARC600_swap_L_r_r__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_SWAP_L_U6_, model_ARC600_swap_L_u6_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_NORM_L_R_R__RC, model_ARC600_norm_L_r_r__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_NORM_L_U6_, model_ARC600_norm_L_u6_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_RND16_L_R_R__RC, model_ARC600_rnd16_L_r_r__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_RND16_L_U6_, model_ARC600_rnd16_L_u6_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ABSSW_L_R_R__RC, model_ARC600_abssw_L_r_r__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ABSSW_L_U6_, model_ARC600_abssw_L_u6_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ABSS_L_R_R__RC, model_ARC600_abss_L_r_r__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ABSS_L_U6_, model_ARC600_abss_L_u6_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_NEGSW_L_R_R__RC, model_ARC600_negsw_L_r_r__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_NEGSW_L_U6_, model_ARC600_negsw_L_u6_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_NEGS_L_R_R__RC, model_ARC600_negs_L_r_r__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_NEGS_L_U6_, model_ARC600_negs_L_u6_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_NORMW_L_R_R__RC, model_ARC600_normw_L_r_r__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_NORMW_L_U6_, model_ARC600_normw_L_u6_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_NOP_S, model_ARC600_nop_s, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_UNIMP_S, model_ARC600_unimp_s, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_POP_S_B, model_ARC600_pop_s_b, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_POP_S_BLINK, model_ARC600_pop_s_blink, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_PUSH_S_B, model_ARC600_push_s_b, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_PUSH_S_BLINK, model_ARC600_push_s_blink, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MULLW_L_S12__RA_, model_ARC600_mullw_L_s12__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MULLW_CCU6__RA_, model_ARC600_mullw_ccu6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MULLW_L_U6__RA_, model_ARC600_mullw_L_u6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MULLW_L_R_R__RA__RC, model_ARC600_mullw_L_r_r__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MULLW_CC__RA__RC, model_ARC600_mullw_cc__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MACLW_L_S12__RA_, model_ARC600_maclw_L_s12__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MACLW_CCU6__RA_, model_ARC600_maclw_ccu6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MACLW_L_U6__RA_, model_ARC600_maclw_L_u6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MACLW_L_R_R__RA__RC, model_ARC600_maclw_L_r_r__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MACLW_CC__RA__RC, model_ARC600_maclw_cc__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MACHLW_L_S12__RA_, model_ARC600_machlw_L_s12__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MACHLW_CCU6__RA_, model_ARC600_machlw_ccu6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MACHLW_L_U6__RA_, model_ARC600_machlw_L_u6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MACHLW_L_R_R__RA__RC, model_ARC600_machlw_L_r_r__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MACHLW_CC__RA__RC, model_ARC600_machlw_cc__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MULULW_L_S12__RA_, model_ARC600_mululw_L_s12__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MULULW_CCU6__RA_, model_ARC600_mululw_ccu6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MULULW_L_U6__RA_, model_ARC600_mululw_L_u6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MULULW_L_R_R__RA__RC, model_ARC600_mululw_L_r_r__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MULULW_CC__RA__RC, model_ARC600_mululw_cc__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MACHULW_L_S12__RA_, model_ARC600_machulw_L_s12__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MACHULW_CCU6__RA_, model_ARC600_machulw_ccu6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MACHULW_L_U6__RA_, model_ARC600_machulw_L_u6__RA_, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MACHULW_L_R_R__RA__RC, model_ARC600_machulw_L_r_r__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_MACHULW_CC__RA__RC, model_ARC600_machulw_cc__RA__RC, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_CURRENT_LOOP_END, model_ARC600_current_loop_end, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_CURRENT_LOOP_END_AFTER_BRANCH, model_ARC600_current_loop_end_after_branch, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+ { ARC600F_INSN_ARC600_CURRENT_LOOP_END_AFTER_BRANCH, model_ARC600_arc600_current_loop_end_after_branch, { { (int) UNIT_ARC600_U_EXEC, 1, 1 } } },
+};
+
+#endif /* WITH_PROFILE_MODEL_P */
+
+static void
+ARC600_model_init (SIM_CPU *cpu)
+{
+ CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_ARC600_DATA));
+}
+
+#if WITH_PROFILE_MODEL_P
+#define TIMING_DATA(td) td
+#else
+#define TIMING_DATA(td) 0
+#endif
+
+static const MODEL arc600_models[] =
+{
+ { "ARC600", & arc600_mach, MODEL_ARC600, TIMING_DATA (& ARC600_timing[0]), ARC600_model_init },
+ { 0 }
+};
+
+/* The properties of this cpu's implementation. */
+
+static const MACH_IMP_PROPERTIES arc600f_imp_properties =
+{
+ sizeof (SIM_CPU),
+#if WITH_SCACHE
+ sizeof (SCACHE)
+#else
+ 0
+#endif
+};
+
+
+static void
+arc600f_prepare_run (SIM_CPU *cpu)
+{
+ if (CPU_IDESC (cpu) == NULL)
+ arc600f_init_idesc_table (cpu);
+}
+
+static const CGEN_INSN *
+arc600f_get_idata (SIM_CPU *cpu, int inum)
+{
+ return CPU_IDESC (cpu) [inum].idata;
+}
+
+static void
+arc600_init_cpu (SIM_CPU *cpu)
+{
+ CPU_REG_FETCH (cpu) = arc600f_fetch_register;
+ CPU_REG_STORE (cpu) = arc600f_store_register;
+ CPU_PC_FETCH (cpu) = arc600f_h_pc_get;
+ CPU_PC_STORE (cpu) = arc600f_h_pc_set;
+ CPU_GET_IDATA (cpu) = arc600f_get_idata;
+ CPU_MAX_INSNS (cpu) = ARC600F_INSN__MAX;
+ CPU_INSN_NAME (cpu) = cgen_insn_name;
+ CPU_FULL_ENGINE_FN (cpu) = arc600f_engine_run_full;
+#if WITH_FAST
+ CPU_FAST_ENGINE_FN (cpu) = arc600f_engine_run_fast;
+#else
+ CPU_FAST_ENGINE_FN (cpu) = arc600f_engine_run_full;
+#endif
+}
+
+const MACH arc600_mach =
+{
+ "arc600", "ARC600", MACH_ARC600,
+ 32, 32, & arc600_models[0], & arc600f_imp_properties,
+ arc600_init_cpu,
+ arc600f_prepare_run
+};
+
diff --git a/sim/arc/model7.c b/sim/arc/model7.c
new file mode 100644
index 0000000..27f97e6
--- /dev/null
+++ b/sim/arc/model7.c
@@ -0,0 +1,9562 @@
+/* Simulator model support for arc700f.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2007 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#define WANT_CPU arc700f
+#define WANT_CPU_ARC700F
+
+#include "sim-main.h"
+
+/* The profiling data is recorded here, but is accessed via the profiling
+ mechanism. After all, this is information for profiling. */
+
+#if WITH_PROFILE_MODEL_P
+
+/* Model handlers for each insn. */
+
+static int
+model_ARC700_b_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_b_s.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_bcc_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bcc_s.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_brcc_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_brcc_s.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_bcc_l (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bcc_l.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_bcc_l_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bcc_l.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_b_l (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_b_l.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_b_l_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_b_l.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_brcc_RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_brcc_RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_brcc_RC_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_brcc_RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_brcc_U6 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_brcc_U6.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_brcc_U6_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_brcc_U6.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_bl_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bl_s.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_blcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_blcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_blcc_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_blcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_bl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bl.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_bl_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bl.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ld_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ld__AW_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ld_ab_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ld_as_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ld_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ld__AW_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ld_ab_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ld_as_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ld_s_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ld_s_abu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ld_s_absp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ld_s_gprel (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_gprel.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ld_s_pcrel (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_pcrel.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ldb_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ldb__AW_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ldb_ab_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ldb_as_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ldb_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ldb__AW_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ldb_ab_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ldb_as_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ldb_s_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ldb_s_abu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ldb_s_absp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ldb_s_gprel (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_gprel.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ldb_x_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ldb__AW_x_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ldb_ab_x_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ldb_as_x_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ldb_x_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ldb__AW_x_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ldb_ab_x_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ldb_as_x_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ldw_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ldw__AW_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ldw_ab_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ldw_as_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ldw_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ldw__AW_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ldw_ab_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ldw_as_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ldw_s_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ldw_s_abu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldw_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ldw_s_gprel (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldw_s_gprel.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ldw_x_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ldw__AW_x_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ldw_ab_x_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ldw_as_x_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ldw_x_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ldw__AW_x_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ldw_ab_x_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ldw_as_x_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ldw_s_x_abu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldw_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_st_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_st__AW_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_st_ab_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_st_as_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_st_s_abu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_st_s_absp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_stb_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_stb__AW_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_stb_ab_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_stb_as_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_stb_s_abu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_stb_s_absp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_stw_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_stw__AW_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_stw_ab_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_stw_as_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_stw_s_abu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldw_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_add_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_add_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_add_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_add_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_add_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_add_s_abc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_add_s_cbu3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_add_s_mcah (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_add_s_absp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_add_s_asspsp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_add_s_gp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_gprel.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_add_s_r_u7 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_r_u7.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_adc_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_adc_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_adc_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_adc_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_adc_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_sub_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_sub_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_sub_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_sub_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_sub_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_sub_s_cbu3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_I16_GO_SUB_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_sub_s_go_sub_ne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_sub_s_ssb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_sub_s_asspsp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_sbc_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_sbc_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_sbc_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_sbc_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_sbc_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_and_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_and_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_and_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_and_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_and_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_I16_GO_AND_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_or_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_or_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_or_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_or_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_or_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_I16_GO_OR_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_bic_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_bic_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_bic_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_bic_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_bic_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_I16_GO_BIC_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_xor_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_xor_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_xor_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_xor_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_xor_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_I16_GO_XOR_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_max_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_max_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_max_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_max_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_max_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_min_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_min_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_min_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_min_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_min_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mov_L_s12_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mov_ccu6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mov_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mov_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mov_cc__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mov_s_mcah (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mov_s_mcahb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mov_s_r_u7 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_tst_L_s12_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_tst_ccu6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_tst_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_tst_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_tst_cc__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_tst_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_cmp_L_s12_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_cmp_ccu6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_cmp_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_cmp_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_cmp_cc__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_cmp_s_mcah (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_cmp_s_r_u7 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_r_u7.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_rcmp_L_s12_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_rcmp_ccu6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_rcmp_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_rcmp_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_rcmp_cc__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_rsub_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_rsub_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_rsub_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_rsub_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_rsub_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_bset_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_bset_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_bset_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_bset_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_bset_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_bset_s_ssb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_bclr_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_bclr_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_bclr_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_bclr_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_bclr_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_bclr_s_ssb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_btst_L_s12_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_btst_ccu6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_btst_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_btst_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_btst_cc__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_btst_s_ssb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_bxor_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_bxor_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_bxor_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_bxor_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_bxor_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_bmsk_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_bmsk_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_bmsk_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_bmsk_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_bmsk_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_bmsk_s_ssb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_add1_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_add1_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_add1_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_add1_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_add1_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_I16_GO_ADD1_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_add2_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_add2_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_add2_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_add2_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_add2_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_I16_GO_ADD2_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_add3_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_add3_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_add3_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_add3_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_add3_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_I16_GO_ADD3_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_sub1_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_sub1_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_sub1_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_sub1_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_sub1_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_sub2_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_sub2_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_sub2_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_sub2_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_sub2_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_sub3_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_sub3_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_sub3_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_sub3_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_sub3_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mpy_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mpy_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mpy_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mpy_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mpy_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mpyh_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mpyh_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mpyh_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mpyh_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mpyh_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mpyhu_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mpyhu_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mpyhu_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mpyhu_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mpyhu_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mpyu_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mpyu_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mpyu_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mpyu_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mpyu_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_j_L_r_r___RC_noilink_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_j_cc___RC_noilink_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_j_L_r_r___RC_ilink_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_j_cc___RC_ilink_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_j_L_s12_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_j_ccu6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_j_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_j_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_j_s__S (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_j_seq__S (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_j_sne__S (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_j_L_s12_d_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_j_ccu6_d_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_j_L_u6_d_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_j_L_r_r_d___RC_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_j_cc_d___RC_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_j_s_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_j_s__S_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_jl_L_s12_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_jl_ccu6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_jl_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_jl_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_jl_L_r_r___RC_noilink_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_jl_cc___RC_noilink_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_jl_L_s12_d_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_jl_ccu6_d_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_jl_L_u6_d_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_jl_L_r_r_d___RC_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_jl_cc_d___RC_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_jl_s_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_lp_L_s12_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lp_L_s12_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_lpcc_ccu6 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lpcc_ccu6.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_flag_L_s12_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_flag_ccu6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_flag_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_flag_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_flag_cc__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_lr_L_r_r___RC_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_lr_L_s12_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_lr_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_sr_L_r_r___RC_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_sr_L_s12_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_sr_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_asl_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_asl_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_I16_GO_ASL_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_asr_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_asr_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_I16_GO_ASR_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_lsr_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_lsr_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_I16_GO_LSR_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ror_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ror_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_rrc_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_rrc_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_sexb_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_sexb_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_I16_GO_SEXB_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_sexw_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_sexw_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_I16_GO_SEXW_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_extb_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_extb_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_I16_GO_EXTB_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_extw_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_extw_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_I16_GO_EXTW_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_abs_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_abs_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_I16_GO_ABS_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_not_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_not_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_I16_GO_NOT_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_rlc_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_rlc_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ex_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ex_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_I16_GO_NEG_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_swi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_trap_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_trap_s.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_brk (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_brk_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_asl_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_asl_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_asl_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_asl_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_asl_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_asl_s_cbu3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_asl_s_ssb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_I16_GO_ASLM_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_lsr_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_lsr_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_lsr_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_lsr_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_lsr_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_lsr_s_ssb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_I16_GO_LSRM_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_asr_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_asr_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_asr_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_asr_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_asr_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_asr_s_cbu3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_asr_s_ssb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_I16_GO_ASRM_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ror_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ror_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ror_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ror_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_ror_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mul64_L_s12_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mul64_ccu6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mul64_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mul64_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mul64_cc__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mul64_s_go (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mulu64_L_s12_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mulu64_ccu6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mulu64_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mulu64_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mulu64_cc__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_adds_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_adds_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_adds_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_adds_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_adds_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_subs_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_subs_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_subs_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_subs_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_subs_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_divaw_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_divaw_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_divaw_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_divaw_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_divaw_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_asls_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_asls_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_asls_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_asls_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_asls_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_asrs_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_asrs_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_asrs_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_asrs_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_asrs_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_addsdw_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_addsdw_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_addsdw_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_addsdw_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_addsdw_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_subsdw_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_subsdw_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_subsdw_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_subsdw_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_subsdw_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_swap_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_swap_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_norm_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_norm_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_rnd16_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_rnd16_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_abssw_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_abssw_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_abss_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_abss_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_negsw_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_negsw_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_negs_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_negs_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_normw_L_r_r__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_normw_L_u6_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_nop_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_unimp_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_pop_s_b (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_pop_s_blink (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_push_s_b (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_push_s_blink (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mullw_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mullw_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mullw_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mullw_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mullw_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_maclw_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_maclw_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_maclw_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_maclw_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_maclw_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_machlw_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_machlw_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_machlw_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_machlw_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_machlw_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mululw_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mululw_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mululw_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mululw_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_mululw_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_machulw_L_s12__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_machulw_ccu6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_machulw_L_u6__RA_ (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_machulw_L_r_r__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_machulw_cc__RA__RC (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_current_loop_end (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_current_loop_end_after_branch (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_ARC700_arc600_current_loop_end_after_branch (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_b = -1;
+ INT in_c = -1;
+ INT out_a = -1;
+ cycles += arc700f_model_ARC700_u_exec (current_cpu, idesc, 0, referenced, in_b, in_c, out_a);
+ }
+ return cycles;
+#undef FLD
+}
+
+/* We assume UNIT_NONE == 0 because the tables don't always terminate
+ entries with it. */
+
+/* Model timing data for `ARC700'. */
+
+static const INSN_TIMING ARC700_timing[] = {
+ { ARC700F_INSN_X_INVALID, 0, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_X_AFTER, 0, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_X_BEFORE, 0, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_X_CHAIN, 0, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_X_BEGIN, 0, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_B_S, model_ARC700_b_s, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BCC_S, model_ARC700_bcc_s, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BRCC_S, model_ARC700_brcc_s, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BCC_L, model_ARC700_bcc_l, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BCC_L_D, model_ARC700_bcc_l_d, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_B_L, model_ARC700_b_l, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_B_L_D, model_ARC700_b_l_d, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BRCC_RC, model_ARC700_brcc_RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BRCC_RC_D, model_ARC700_brcc_RC_d, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BRCC_U6, model_ARC700_brcc_U6, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BRCC_U6_D, model_ARC700_brcc_U6_d, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BL_S, model_ARC700_bl_s, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BLCC, model_ARC700_blcc, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BLCC_D, model_ARC700_blcc_d, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BL, model_ARC700_bl, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BL_D, model_ARC700_bl_d, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LD_ABS, model_ARC700_ld_abs, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LD__AW_ABS, model_ARC700_ld__AW_abs, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LD_AB_ABS, model_ARC700_ld_ab_abs, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LD_AS_ABS, model_ARC700_ld_as_abs, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LD_ABC, model_ARC700_ld_abc, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LD__AW_ABC, model_ARC700_ld__AW_abc, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LD_AB_ABC, model_ARC700_ld_ab_abc, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LD_AS_ABC, model_ARC700_ld_as_abc, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LD_S_ABC, model_ARC700_ld_s_abc, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LD_S_ABU, model_ARC700_ld_s_abu, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LD_S_ABSP, model_ARC700_ld_s_absp, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LD_S_GPREL, model_ARC700_ld_s_gprel, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LD_S_PCREL, model_ARC700_ld_s_pcrel, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LDB_ABS, model_ARC700_ldb_abs, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LDB__AW_ABS, model_ARC700_ldb__AW_abs, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LDB_AB_ABS, model_ARC700_ldb_ab_abs, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LDB_AS_ABS, model_ARC700_ldb_as_abs, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LDB_ABC, model_ARC700_ldb_abc, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LDB__AW_ABC, model_ARC700_ldb__AW_abc, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LDB_AB_ABC, model_ARC700_ldb_ab_abc, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LDB_AS_ABC, model_ARC700_ldb_as_abc, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LDB_S_ABC, model_ARC700_ldb_s_abc, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LDB_S_ABU, model_ARC700_ldb_s_abu, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LDB_S_ABSP, model_ARC700_ldb_s_absp, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LDB_S_GPREL, model_ARC700_ldb_s_gprel, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LDB_X_ABS, model_ARC700_ldb_x_abs, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LDB__AW_X_ABS, model_ARC700_ldb__AW_x_abs, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LDB_AB_X_ABS, model_ARC700_ldb_ab_x_abs, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LDB_AS_X_ABS, model_ARC700_ldb_as_x_abs, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LDB_X_ABC, model_ARC700_ldb_x_abc, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LDB__AW_X_ABC, model_ARC700_ldb__AW_x_abc, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LDB_AB_X_ABC, model_ARC700_ldb_ab_x_abc, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LDB_AS_X_ABC, model_ARC700_ldb_as_x_abc, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LDW_ABS, model_ARC700_ldw_abs, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LDW__AW_ABS, model_ARC700_ldw__AW_abs, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LDW_AB_ABS, model_ARC700_ldw_ab_abs, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LDW_AS_ABS, model_ARC700_ldw_as_abs, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LDW_ABC, model_ARC700_ldw_abc, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LDW__AW_ABC, model_ARC700_ldw__AW_abc, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LDW_AB_ABC, model_ARC700_ldw_ab_abc, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LDW_AS_ABC, model_ARC700_ldw_as_abc, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LDW_S_ABC, model_ARC700_ldw_s_abc, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LDW_S_ABU, model_ARC700_ldw_s_abu, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LDW_S_GPREL, model_ARC700_ldw_s_gprel, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LDW_X_ABS, model_ARC700_ldw_x_abs, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LDW__AW_X_ABS, model_ARC700_ldw__AW_x_abs, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LDW_AB_X_ABS, model_ARC700_ldw_ab_x_abs, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LDW_AS_X_ABS, model_ARC700_ldw_as_x_abs, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LDW_X_ABC, model_ARC700_ldw_x_abc, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LDW__AW_X_ABC, model_ARC700_ldw__AW_x_abc, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LDW_AB_X_ABC, model_ARC700_ldw_ab_x_abc, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LDW_AS_X_ABC, model_ARC700_ldw_as_x_abc, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LDW_S_X_ABU, model_ARC700_ldw_s_x_abu, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ST_ABS, model_ARC700_st_abs, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ST__AW_ABS, model_ARC700_st__AW_abs, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ST_AB_ABS, model_ARC700_st_ab_abs, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ST_AS_ABS, model_ARC700_st_as_abs, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ST_S_ABU, model_ARC700_st_s_abu, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ST_S_ABSP, model_ARC700_st_s_absp, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_STB_ABS, model_ARC700_stb_abs, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_STB__AW_ABS, model_ARC700_stb__AW_abs, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_STB_AB_ABS, model_ARC700_stb_ab_abs, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_STB_AS_ABS, model_ARC700_stb_as_abs, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_STB_S_ABU, model_ARC700_stb_s_abu, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_STB_S_ABSP, model_ARC700_stb_s_absp, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_STW_ABS, model_ARC700_stw_abs, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_STW__AW_ABS, model_ARC700_stw__AW_abs, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_STW_AB_ABS, model_ARC700_stw_ab_abs, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_STW_AS_ABS, model_ARC700_stw_as_abs, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_STW_S_ABU, model_ARC700_stw_s_abu, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ADD_L_S12__RA_, model_ARC700_add_L_s12__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ADD_CCU6__RA_, model_ARC700_add_ccu6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ADD_L_U6__RA_, model_ARC700_add_L_u6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ADD_L_R_R__RA__RC, model_ARC700_add_L_r_r__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ADD_CC__RA__RC, model_ARC700_add_cc__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ADD_S_ABC, model_ARC700_add_s_abc, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ADD_S_CBU3, model_ARC700_add_s_cbu3, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ADD_S_MCAH, model_ARC700_add_s_mcah, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ADD_S_ABSP, model_ARC700_add_s_absp, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ADD_S_ASSPSP, model_ARC700_add_s_asspsp, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ADD_S_GP, model_ARC700_add_s_gp, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ADD_S_R_U7, model_ARC700_add_s_r_u7, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ADC_L_S12__RA_, model_ARC700_adc_L_s12__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ADC_CCU6__RA_, model_ARC700_adc_ccu6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ADC_L_U6__RA_, model_ARC700_adc_L_u6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ADC_L_R_R__RA__RC, model_ARC700_adc_L_r_r__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ADC_CC__RA__RC, model_ARC700_adc_cc__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SUB_L_S12__RA_, model_ARC700_sub_L_s12__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SUB_CCU6__RA_, model_ARC700_sub_ccu6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SUB_L_U6__RA_, model_ARC700_sub_L_u6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SUB_L_R_R__RA__RC, model_ARC700_sub_L_r_r__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SUB_CC__RA__RC, model_ARC700_sub_cc__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SUB_S_CBU3, model_ARC700_sub_s_cbu3, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_I16_GO_SUB_S_GO, model_ARC700_I16_GO_SUB_s_go, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SUB_S_GO_SUB_NE, model_ARC700_sub_s_go_sub_ne, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SUB_S_SSB, model_ARC700_sub_s_ssb, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SUB_S_ASSPSP, model_ARC700_sub_s_asspsp, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SBC_L_S12__RA_, model_ARC700_sbc_L_s12__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SBC_CCU6__RA_, model_ARC700_sbc_ccu6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SBC_L_U6__RA_, model_ARC700_sbc_L_u6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SBC_L_R_R__RA__RC, model_ARC700_sbc_L_r_r__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SBC_CC__RA__RC, model_ARC700_sbc_cc__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_AND_L_S12__RA_, model_ARC700_and_L_s12__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_AND_CCU6__RA_, model_ARC700_and_ccu6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_AND_L_U6__RA_, model_ARC700_and_L_u6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_AND_L_R_R__RA__RC, model_ARC700_and_L_r_r__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_AND_CC__RA__RC, model_ARC700_and_cc__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_I16_GO_AND_S_GO, model_ARC700_I16_GO_AND_s_go, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_OR_L_S12__RA_, model_ARC700_or_L_s12__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_OR_CCU6__RA_, model_ARC700_or_ccu6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_OR_L_U6__RA_, model_ARC700_or_L_u6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_OR_L_R_R__RA__RC, model_ARC700_or_L_r_r__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_OR_CC__RA__RC, model_ARC700_or_cc__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_I16_GO_OR_S_GO, model_ARC700_I16_GO_OR_s_go, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BIC_L_S12__RA_, model_ARC700_bic_L_s12__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BIC_CCU6__RA_, model_ARC700_bic_ccu6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BIC_L_U6__RA_, model_ARC700_bic_L_u6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BIC_L_R_R__RA__RC, model_ARC700_bic_L_r_r__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BIC_CC__RA__RC, model_ARC700_bic_cc__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_I16_GO_BIC_S_GO, model_ARC700_I16_GO_BIC_s_go, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_XOR_L_S12__RA_, model_ARC700_xor_L_s12__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_XOR_CCU6__RA_, model_ARC700_xor_ccu6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_XOR_L_U6__RA_, model_ARC700_xor_L_u6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_XOR_L_R_R__RA__RC, model_ARC700_xor_L_r_r__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_XOR_CC__RA__RC, model_ARC700_xor_cc__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_I16_GO_XOR_S_GO, model_ARC700_I16_GO_XOR_s_go, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MAX_L_S12__RA_, model_ARC700_max_L_s12__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MAX_CCU6__RA_, model_ARC700_max_ccu6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MAX_L_U6__RA_, model_ARC700_max_L_u6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MAX_L_R_R__RA__RC, model_ARC700_max_L_r_r__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MAX_CC__RA__RC, model_ARC700_max_cc__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MIN_L_S12__RA_, model_ARC700_min_L_s12__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MIN_CCU6__RA_, model_ARC700_min_ccu6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MIN_L_U6__RA_, model_ARC700_min_L_u6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MIN_L_R_R__RA__RC, model_ARC700_min_L_r_r__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MIN_CC__RA__RC, model_ARC700_min_cc__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MOV_L_S12_, model_ARC700_mov_L_s12_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MOV_CCU6_, model_ARC700_mov_ccu6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MOV_L_U6_, model_ARC700_mov_L_u6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MOV_L_R_R__RC, model_ARC700_mov_L_r_r__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MOV_CC__RC, model_ARC700_mov_cc__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MOV_S_MCAH, model_ARC700_mov_s_mcah, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MOV_S_MCAHB, model_ARC700_mov_s_mcahb, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MOV_S_R_U7, model_ARC700_mov_s_r_u7, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_TST_L_S12_, model_ARC700_tst_L_s12_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_TST_CCU6_, model_ARC700_tst_ccu6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_TST_L_U6_, model_ARC700_tst_L_u6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_TST_L_R_R__RC, model_ARC700_tst_L_r_r__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_TST_CC__RC, model_ARC700_tst_cc__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_TST_S_GO, model_ARC700_tst_s_go, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_CMP_L_S12_, model_ARC700_cmp_L_s12_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_CMP_CCU6_, model_ARC700_cmp_ccu6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_CMP_L_U6_, model_ARC700_cmp_L_u6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_CMP_L_R_R__RC, model_ARC700_cmp_L_r_r__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_CMP_CC__RC, model_ARC700_cmp_cc__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_CMP_S_MCAH, model_ARC700_cmp_s_mcah, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_CMP_S_R_U7, model_ARC700_cmp_s_r_u7, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_RCMP_L_S12_, model_ARC700_rcmp_L_s12_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_RCMP_CCU6_, model_ARC700_rcmp_ccu6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_RCMP_L_U6_, model_ARC700_rcmp_L_u6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_RCMP_L_R_R__RC, model_ARC700_rcmp_L_r_r__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_RCMP_CC__RC, model_ARC700_rcmp_cc__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_RSUB_L_S12__RA_, model_ARC700_rsub_L_s12__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_RSUB_CCU6__RA_, model_ARC700_rsub_ccu6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_RSUB_L_U6__RA_, model_ARC700_rsub_L_u6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_RSUB_L_R_R__RA__RC, model_ARC700_rsub_L_r_r__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_RSUB_CC__RA__RC, model_ARC700_rsub_cc__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BSET_L_S12__RA_, model_ARC700_bset_L_s12__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BSET_CCU6__RA_, model_ARC700_bset_ccu6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BSET_L_U6__RA_, model_ARC700_bset_L_u6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BSET_L_R_R__RA__RC, model_ARC700_bset_L_r_r__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BSET_CC__RA__RC, model_ARC700_bset_cc__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BSET_S_SSB, model_ARC700_bset_s_ssb, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BCLR_L_S12__RA_, model_ARC700_bclr_L_s12__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BCLR_CCU6__RA_, model_ARC700_bclr_ccu6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BCLR_L_U6__RA_, model_ARC700_bclr_L_u6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BCLR_L_R_R__RA__RC, model_ARC700_bclr_L_r_r__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BCLR_CC__RA__RC, model_ARC700_bclr_cc__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BCLR_S_SSB, model_ARC700_bclr_s_ssb, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BTST_L_S12_, model_ARC700_btst_L_s12_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BTST_CCU6_, model_ARC700_btst_ccu6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BTST_L_U6_, model_ARC700_btst_L_u6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BTST_L_R_R__RC, model_ARC700_btst_L_r_r__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BTST_CC__RC, model_ARC700_btst_cc__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BTST_S_SSB, model_ARC700_btst_s_ssb, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BXOR_L_S12__RA_, model_ARC700_bxor_L_s12__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BXOR_CCU6__RA_, model_ARC700_bxor_ccu6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BXOR_L_U6__RA_, model_ARC700_bxor_L_u6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BXOR_L_R_R__RA__RC, model_ARC700_bxor_L_r_r__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BXOR_CC__RA__RC, model_ARC700_bxor_cc__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BMSK_L_S12__RA_, model_ARC700_bmsk_L_s12__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BMSK_CCU6__RA_, model_ARC700_bmsk_ccu6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BMSK_L_U6__RA_, model_ARC700_bmsk_L_u6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BMSK_L_R_R__RA__RC, model_ARC700_bmsk_L_r_r__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BMSK_CC__RA__RC, model_ARC700_bmsk_cc__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BMSK_S_SSB, model_ARC700_bmsk_s_ssb, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ADD1_L_S12__RA_, model_ARC700_add1_L_s12__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ADD1_CCU6__RA_, model_ARC700_add1_ccu6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ADD1_L_U6__RA_, model_ARC700_add1_L_u6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ADD1_L_R_R__RA__RC, model_ARC700_add1_L_r_r__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ADD1_CC__RA__RC, model_ARC700_add1_cc__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_I16_GO_ADD1_S_GO, model_ARC700_I16_GO_ADD1_s_go, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ADD2_L_S12__RA_, model_ARC700_add2_L_s12__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ADD2_CCU6__RA_, model_ARC700_add2_ccu6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ADD2_L_U6__RA_, model_ARC700_add2_L_u6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ADD2_L_R_R__RA__RC, model_ARC700_add2_L_r_r__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ADD2_CC__RA__RC, model_ARC700_add2_cc__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_I16_GO_ADD2_S_GO, model_ARC700_I16_GO_ADD2_s_go, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ADD3_L_S12__RA_, model_ARC700_add3_L_s12__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ADD3_CCU6__RA_, model_ARC700_add3_ccu6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ADD3_L_U6__RA_, model_ARC700_add3_L_u6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ADD3_L_R_R__RA__RC, model_ARC700_add3_L_r_r__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ADD3_CC__RA__RC, model_ARC700_add3_cc__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_I16_GO_ADD3_S_GO, model_ARC700_I16_GO_ADD3_s_go, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SUB1_L_S12__RA_, model_ARC700_sub1_L_s12__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SUB1_CCU6__RA_, model_ARC700_sub1_ccu6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SUB1_L_U6__RA_, model_ARC700_sub1_L_u6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SUB1_L_R_R__RA__RC, model_ARC700_sub1_L_r_r__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SUB1_CC__RA__RC, model_ARC700_sub1_cc__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SUB2_L_S12__RA_, model_ARC700_sub2_L_s12__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SUB2_CCU6__RA_, model_ARC700_sub2_ccu6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SUB2_L_U6__RA_, model_ARC700_sub2_L_u6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SUB2_L_R_R__RA__RC, model_ARC700_sub2_L_r_r__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SUB2_CC__RA__RC, model_ARC700_sub2_cc__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SUB3_L_S12__RA_, model_ARC700_sub3_L_s12__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SUB3_CCU6__RA_, model_ARC700_sub3_ccu6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SUB3_L_U6__RA_, model_ARC700_sub3_L_u6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SUB3_L_R_R__RA__RC, model_ARC700_sub3_L_r_r__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SUB3_CC__RA__RC, model_ARC700_sub3_cc__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MPY_L_S12__RA_, model_ARC700_mpy_L_s12__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MPY_CCU6__RA_, model_ARC700_mpy_ccu6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MPY_L_U6__RA_, model_ARC700_mpy_L_u6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MPY_L_R_R__RA__RC, model_ARC700_mpy_L_r_r__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MPY_CC__RA__RC, model_ARC700_mpy_cc__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MPYH_L_S12__RA_, model_ARC700_mpyh_L_s12__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MPYH_CCU6__RA_, model_ARC700_mpyh_ccu6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MPYH_L_U6__RA_, model_ARC700_mpyh_L_u6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MPYH_L_R_R__RA__RC, model_ARC700_mpyh_L_r_r__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MPYH_CC__RA__RC, model_ARC700_mpyh_cc__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MPYHU_L_S12__RA_, model_ARC700_mpyhu_L_s12__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MPYHU_CCU6__RA_, model_ARC700_mpyhu_ccu6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MPYHU_L_U6__RA_, model_ARC700_mpyhu_L_u6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MPYHU_L_R_R__RA__RC, model_ARC700_mpyhu_L_r_r__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MPYHU_CC__RA__RC, model_ARC700_mpyhu_cc__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MPYU_L_S12__RA_, model_ARC700_mpyu_L_s12__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MPYU_CCU6__RA_, model_ARC700_mpyu_ccu6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MPYU_L_U6__RA_, model_ARC700_mpyu_L_u6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MPYU_L_R_R__RA__RC, model_ARC700_mpyu_L_r_r__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MPYU_CC__RA__RC, model_ARC700_mpyu_cc__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_J_L_R_R___RC_NOILINK_, model_ARC700_j_L_r_r___RC_noilink_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_J_CC___RC_NOILINK_, model_ARC700_j_cc___RC_noilink_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_J_L_R_R___RC_ILINK_, model_ARC700_j_L_r_r___RC_ilink_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_J_CC___RC_ILINK_, model_ARC700_j_cc___RC_ilink_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_J_L_S12_, model_ARC700_j_L_s12_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_J_CCU6_, model_ARC700_j_ccu6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_J_L_U6_, model_ARC700_j_L_u6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_J_S, model_ARC700_j_s, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_J_S__S, model_ARC700_j_s__S, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_J_SEQ__S, model_ARC700_j_seq__S, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_J_SNE__S, model_ARC700_j_sne__S, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_J_L_S12_D_, model_ARC700_j_L_s12_d_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_J_CCU6_D_, model_ARC700_j_ccu6_d_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_J_L_U6_D_, model_ARC700_j_L_u6_d_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_J_L_R_R_D___RC_, model_ARC700_j_L_r_r_d___RC_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_J_CC_D___RC_, model_ARC700_j_cc_d___RC_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_J_S_D, model_ARC700_j_s_d, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_J_S__S_D, model_ARC700_j_s__S_d, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_JL_L_S12_, model_ARC700_jl_L_s12_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_JL_CCU6_, model_ARC700_jl_ccu6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_JL_L_U6_, model_ARC700_jl_L_u6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_JL_S, model_ARC700_jl_s, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_JL_L_R_R___RC_NOILINK_, model_ARC700_jl_L_r_r___RC_noilink_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_JL_CC___RC_NOILINK_, model_ARC700_jl_cc___RC_noilink_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_JL_L_S12_D_, model_ARC700_jl_L_s12_d_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_JL_CCU6_D_, model_ARC700_jl_ccu6_d_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_JL_L_U6_D_, model_ARC700_jl_L_u6_d_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_JL_L_R_R_D___RC_, model_ARC700_jl_L_r_r_d___RC_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_JL_CC_D___RC_, model_ARC700_jl_cc_d___RC_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_JL_S_D, model_ARC700_jl_s_d, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LP_L_S12_, model_ARC700_lp_L_s12_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LPCC_CCU6, model_ARC700_lpcc_ccu6, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_FLAG_L_S12_, model_ARC700_flag_L_s12_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_FLAG_CCU6_, model_ARC700_flag_ccu6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_FLAG_L_U6_, model_ARC700_flag_L_u6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_FLAG_L_R_R__RC, model_ARC700_flag_L_r_r__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_FLAG_CC__RC, model_ARC700_flag_cc__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LR_L_R_R___RC_, model_ARC700_lr_L_r_r___RC_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LR_L_S12_, model_ARC700_lr_L_s12_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LR_L_U6_, model_ARC700_lr_L_u6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SR_L_R_R___RC_, model_ARC700_sr_L_r_r___RC_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SR_L_S12_, model_ARC700_sr_L_s12_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SR_L_U6_, model_ARC700_sr_L_u6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ASL_L_R_R__RC, model_ARC700_asl_L_r_r__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ASL_L_U6_, model_ARC700_asl_L_u6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_I16_GO_ASL_S_GO, model_ARC700_I16_GO_ASL_s_go, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ASR_L_R_R__RC, model_ARC700_asr_L_r_r__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ASR_L_U6_, model_ARC700_asr_L_u6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_I16_GO_ASR_S_GO, model_ARC700_I16_GO_ASR_s_go, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LSR_L_R_R__RC, model_ARC700_lsr_L_r_r__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LSR_L_U6_, model_ARC700_lsr_L_u6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_I16_GO_LSR_S_GO, model_ARC700_I16_GO_LSR_s_go, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ROR_L_R_R__RC, model_ARC700_ror_L_r_r__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ROR_L_U6_, model_ARC700_ror_L_u6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_RRC_L_R_R__RC, model_ARC700_rrc_L_r_r__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_RRC_L_U6_, model_ARC700_rrc_L_u6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SEXB_L_R_R__RC, model_ARC700_sexb_L_r_r__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SEXB_L_U6_, model_ARC700_sexb_L_u6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_I16_GO_SEXB_S_GO, model_ARC700_I16_GO_SEXB_s_go, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SEXW_L_R_R__RC, model_ARC700_sexw_L_r_r__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SEXW_L_U6_, model_ARC700_sexw_L_u6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_I16_GO_SEXW_S_GO, model_ARC700_I16_GO_SEXW_s_go, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_EXTB_L_R_R__RC, model_ARC700_extb_L_r_r__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_EXTB_L_U6_, model_ARC700_extb_L_u6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_I16_GO_EXTB_S_GO, model_ARC700_I16_GO_EXTB_s_go, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_EXTW_L_R_R__RC, model_ARC700_extw_L_r_r__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_EXTW_L_U6_, model_ARC700_extw_L_u6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_I16_GO_EXTW_S_GO, model_ARC700_I16_GO_EXTW_s_go, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ABS_L_R_R__RC, model_ARC700_abs_L_r_r__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ABS_L_U6_, model_ARC700_abs_L_u6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_I16_GO_ABS_S_GO, model_ARC700_I16_GO_ABS_s_go, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_NOT_L_R_R__RC, model_ARC700_not_L_r_r__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_NOT_L_U6_, model_ARC700_not_L_u6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_I16_GO_NOT_S_GO, model_ARC700_I16_GO_NOT_s_go, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_RLC_L_R_R__RC, model_ARC700_rlc_L_r_r__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_RLC_L_U6_, model_ARC700_rlc_L_u6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_EX_L_R_R__RC, model_ARC700_ex_L_r_r__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_EX_L_U6_, model_ARC700_ex_L_u6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_I16_GO_NEG_S_GO, model_ARC700_I16_GO_NEG_s_go, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SWI, model_ARC700_swi, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_TRAP_S, model_ARC700_trap_s, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BRK, model_ARC700_brk, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_BRK_S, model_ARC700_brk_s, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ASL_L_S12__RA_, model_ARC700_asl_L_s12__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ASL_CCU6__RA_, model_ARC700_asl_ccu6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ASL_L_U6__RA_, model_ARC700_asl_L_u6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ASL_L_R_R__RA__RC, model_ARC700_asl_L_r_r__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ASL_CC__RA__RC, model_ARC700_asl_cc__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ASL_S_CBU3, model_ARC700_asl_s_cbu3, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ASL_S_SSB, model_ARC700_asl_s_ssb, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_I16_GO_ASLM_S_GO, model_ARC700_I16_GO_ASLM_s_go, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LSR_L_S12__RA_, model_ARC700_lsr_L_s12__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LSR_CCU6__RA_, model_ARC700_lsr_ccu6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LSR_L_U6__RA_, model_ARC700_lsr_L_u6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LSR_L_R_R__RA__RC, model_ARC700_lsr_L_r_r__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LSR_CC__RA__RC, model_ARC700_lsr_cc__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_LSR_S_SSB, model_ARC700_lsr_s_ssb, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_I16_GO_LSRM_S_GO, model_ARC700_I16_GO_LSRM_s_go, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ASR_L_S12__RA_, model_ARC700_asr_L_s12__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ASR_CCU6__RA_, model_ARC700_asr_ccu6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ASR_L_U6__RA_, model_ARC700_asr_L_u6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ASR_L_R_R__RA__RC, model_ARC700_asr_L_r_r__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ASR_CC__RA__RC, model_ARC700_asr_cc__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ASR_S_CBU3, model_ARC700_asr_s_cbu3, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ASR_S_SSB, model_ARC700_asr_s_ssb, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_I16_GO_ASRM_S_GO, model_ARC700_I16_GO_ASRM_s_go, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ROR_L_S12__RA_, model_ARC700_ror_L_s12__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ROR_CCU6__RA_, model_ARC700_ror_ccu6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ROR_L_U6__RA_, model_ARC700_ror_L_u6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ROR_L_R_R__RA__RC, model_ARC700_ror_L_r_r__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ROR_CC__RA__RC, model_ARC700_ror_cc__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MUL64_L_S12_, model_ARC700_mul64_L_s12_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MUL64_CCU6_, model_ARC700_mul64_ccu6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MUL64_L_U6_, model_ARC700_mul64_L_u6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MUL64_L_R_R__RC, model_ARC700_mul64_L_r_r__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MUL64_CC__RC, model_ARC700_mul64_cc__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MUL64_S_GO, model_ARC700_mul64_s_go, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MULU64_L_S12_, model_ARC700_mulu64_L_s12_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MULU64_CCU6_, model_ARC700_mulu64_ccu6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MULU64_L_U6_, model_ARC700_mulu64_L_u6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MULU64_L_R_R__RC, model_ARC700_mulu64_L_r_r__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MULU64_CC__RC, model_ARC700_mulu64_cc__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ADDS_L_S12__RA_, model_ARC700_adds_L_s12__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ADDS_CCU6__RA_, model_ARC700_adds_ccu6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ADDS_L_U6__RA_, model_ARC700_adds_L_u6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ADDS_L_R_R__RA__RC, model_ARC700_adds_L_r_r__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ADDS_CC__RA__RC, model_ARC700_adds_cc__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SUBS_L_S12__RA_, model_ARC700_subs_L_s12__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SUBS_CCU6__RA_, model_ARC700_subs_ccu6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SUBS_L_U6__RA_, model_ARC700_subs_L_u6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SUBS_L_R_R__RA__RC, model_ARC700_subs_L_r_r__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SUBS_CC__RA__RC, model_ARC700_subs_cc__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_DIVAW_L_S12__RA_, model_ARC700_divaw_L_s12__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_DIVAW_CCU6__RA_, model_ARC700_divaw_ccu6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_DIVAW_L_U6__RA_, model_ARC700_divaw_L_u6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_DIVAW_L_R_R__RA__RC, model_ARC700_divaw_L_r_r__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_DIVAW_CC__RA__RC, model_ARC700_divaw_cc__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ASLS_L_S12__RA_, model_ARC700_asls_L_s12__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ASLS_CCU6__RA_, model_ARC700_asls_ccu6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ASLS_L_U6__RA_, model_ARC700_asls_L_u6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ASLS_L_R_R__RA__RC, model_ARC700_asls_L_r_r__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ASLS_CC__RA__RC, model_ARC700_asls_cc__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ASRS_L_S12__RA_, model_ARC700_asrs_L_s12__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ASRS_CCU6__RA_, model_ARC700_asrs_ccu6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ASRS_L_U6__RA_, model_ARC700_asrs_L_u6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ASRS_L_R_R__RA__RC, model_ARC700_asrs_L_r_r__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ASRS_CC__RA__RC, model_ARC700_asrs_cc__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ADDSDW_L_S12__RA_, model_ARC700_addsdw_L_s12__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ADDSDW_CCU6__RA_, model_ARC700_addsdw_ccu6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ADDSDW_L_U6__RA_, model_ARC700_addsdw_L_u6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ADDSDW_L_R_R__RA__RC, model_ARC700_addsdw_L_r_r__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ADDSDW_CC__RA__RC, model_ARC700_addsdw_cc__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SUBSDW_L_S12__RA_, model_ARC700_subsdw_L_s12__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SUBSDW_CCU6__RA_, model_ARC700_subsdw_ccu6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SUBSDW_L_U6__RA_, model_ARC700_subsdw_L_u6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SUBSDW_L_R_R__RA__RC, model_ARC700_subsdw_L_r_r__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SUBSDW_CC__RA__RC, model_ARC700_subsdw_cc__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SWAP_L_R_R__RC, model_ARC700_swap_L_r_r__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_SWAP_L_U6_, model_ARC700_swap_L_u6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_NORM_L_R_R__RC, model_ARC700_norm_L_r_r__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_NORM_L_U6_, model_ARC700_norm_L_u6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_RND16_L_R_R__RC, model_ARC700_rnd16_L_r_r__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_RND16_L_U6_, model_ARC700_rnd16_L_u6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ABSSW_L_R_R__RC, model_ARC700_abssw_L_r_r__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ABSSW_L_U6_, model_ARC700_abssw_L_u6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ABSS_L_R_R__RC, model_ARC700_abss_L_r_r__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ABSS_L_U6_, model_ARC700_abss_L_u6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_NEGSW_L_R_R__RC, model_ARC700_negsw_L_r_r__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_NEGSW_L_U6_, model_ARC700_negsw_L_u6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_NEGS_L_R_R__RC, model_ARC700_negs_L_r_r__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_NEGS_L_U6_, model_ARC700_negs_L_u6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_NORMW_L_R_R__RC, model_ARC700_normw_L_r_r__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_NORMW_L_U6_, model_ARC700_normw_L_u6_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_NOP_S, model_ARC700_nop_s, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_UNIMP_S, model_ARC700_unimp_s, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_POP_S_B, model_ARC700_pop_s_b, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_POP_S_BLINK, model_ARC700_pop_s_blink, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_PUSH_S_B, model_ARC700_push_s_b, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_PUSH_S_BLINK, model_ARC700_push_s_blink, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MULLW_L_S12__RA_, model_ARC700_mullw_L_s12__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MULLW_CCU6__RA_, model_ARC700_mullw_ccu6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MULLW_L_U6__RA_, model_ARC700_mullw_L_u6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MULLW_L_R_R__RA__RC, model_ARC700_mullw_L_r_r__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MULLW_CC__RA__RC, model_ARC700_mullw_cc__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MACLW_L_S12__RA_, model_ARC700_maclw_L_s12__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MACLW_CCU6__RA_, model_ARC700_maclw_ccu6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MACLW_L_U6__RA_, model_ARC700_maclw_L_u6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MACLW_L_R_R__RA__RC, model_ARC700_maclw_L_r_r__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MACLW_CC__RA__RC, model_ARC700_maclw_cc__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MACHLW_L_S12__RA_, model_ARC700_machlw_L_s12__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MACHLW_CCU6__RA_, model_ARC700_machlw_ccu6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MACHLW_L_U6__RA_, model_ARC700_machlw_L_u6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MACHLW_L_R_R__RA__RC, model_ARC700_machlw_L_r_r__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MACHLW_CC__RA__RC, model_ARC700_machlw_cc__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MULULW_L_S12__RA_, model_ARC700_mululw_L_s12__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MULULW_CCU6__RA_, model_ARC700_mululw_ccu6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MULULW_L_U6__RA_, model_ARC700_mululw_L_u6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MULULW_L_R_R__RA__RC, model_ARC700_mululw_L_r_r__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MULULW_CC__RA__RC, model_ARC700_mululw_cc__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MACHULW_L_S12__RA_, model_ARC700_machulw_L_s12__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MACHULW_CCU6__RA_, model_ARC700_machulw_ccu6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MACHULW_L_U6__RA_, model_ARC700_machulw_L_u6__RA_, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MACHULW_L_R_R__RA__RC, model_ARC700_machulw_L_r_r__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_MACHULW_CC__RA__RC, model_ARC700_machulw_cc__RA__RC, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_CURRENT_LOOP_END, model_ARC700_current_loop_end, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_CURRENT_LOOP_END_AFTER_BRANCH, model_ARC700_current_loop_end_after_branch, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+ { ARC700F_INSN_ARC600_CURRENT_LOOP_END_AFTER_BRANCH, model_ARC700_arc600_current_loop_end_after_branch, { { (int) UNIT_ARC700_U_EXEC, 1, 1 } } },
+};
+
+#endif /* WITH_PROFILE_MODEL_P */
+
+static void
+ARC700_model_init (SIM_CPU *cpu)
+{
+ CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_ARC700_DATA));
+}
+
+#if WITH_PROFILE_MODEL_P
+#define TIMING_DATA(td) td
+#else
+#define TIMING_DATA(td) 0
+#endif
+
+static const MODEL arc700_models[] =
+{
+ { "ARC700", & arc700_mach, MODEL_ARC700, TIMING_DATA (& ARC700_timing[0]), ARC700_model_init },
+ { 0 }
+};
+
+/* The properties of this cpu's implementation. */
+
+static const MACH_IMP_PROPERTIES arc700f_imp_properties =
+{
+ sizeof (SIM_CPU),
+#if WITH_SCACHE
+ sizeof (SCACHE)
+#else
+ 0
+#endif
+};
+
+
+static void
+arc700f_prepare_run (SIM_CPU *cpu)
+{
+ if (CPU_IDESC (cpu) == NULL)
+ arc700f_init_idesc_table (cpu);
+}
+
+static const CGEN_INSN *
+arc700f_get_idata (SIM_CPU *cpu, int inum)
+{
+ return CPU_IDESC (cpu) [inum].idata;
+}
+
+static void
+arc700_init_cpu (SIM_CPU *cpu)
+{
+ CPU_REG_FETCH (cpu) = arc700f_fetch_register;
+ CPU_REG_STORE (cpu) = arc700f_store_register;
+ CPU_PC_FETCH (cpu) = arc700f_h_pc_get;
+ CPU_PC_STORE (cpu) = arc700f_h_pc_set;
+ CPU_GET_IDATA (cpu) = arc700f_get_idata;
+ CPU_MAX_INSNS (cpu) = ARC700F_INSN__MAX;
+ CPU_INSN_NAME (cpu) = cgen_insn_name;
+ CPU_FULL_ENGINE_FN (cpu) = arc700f_engine_run_full;
+#if WITH_FAST
+ CPU_FAST_ENGINE_FN (cpu) = arc700f_engine_run_fast;
+#else
+ CPU_FAST_ENGINE_FN (cpu) = arc700f_engine_run_full;
+#endif
+}
+
+const MACH arc700_mach =
+{
+ "arc700", "ARC700", MACH_ARC700,
+ 32, 32, & arc700_models[0], & arc700f_imp_properties,
+ arc700_init_cpu,
+ arc700f_prepare_run
+};
+
diff --git a/sim/arc/sem5-switch.c b/sim/arc/sem5-switch.c
new file mode 100644
index 0000000..f5b8f5f
--- /dev/null
+++ b/sim/arc/sem5-switch.c
@@ -0,0 +1,32975 @@
+/* Simulator instruction semantics for a5f.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2007 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#ifdef DEFINE_LABELS
+
+ /* The labels have the case they have because the enum of insn types
+ is all uppercase and in the non-stdc case the insn symbol is built
+ into the enum name. */
+
+ static struct {
+ int index;
+ void *label;
+ } labels[] = {
+ { A5F_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
+ { A5F_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
+ { A5F_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
+ { A5F_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
+ { A5F_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
+ { A5F_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
+ { A5F_INSN_B_S, && case_sem_INSN_B_S },
+ { A5F_INSN_BCC_S, && case_sem_INSN_BCC_S },
+ { A5F_INSN_BRCC_S, && case_sem_INSN_BRCC_S },
+ { A5F_INSN_BCC_L, && case_sem_INSN_BCC_L },
+ { A5F_INSN_BCC_L_D, && case_sem_INSN_BCC_L_D },
+ { A5F_INSN_B_L, && case_sem_INSN_B_L },
+ { A5F_INSN_B_L_D, && case_sem_INSN_B_L_D },
+ { A5F_INSN_BRCC_RC, && case_sem_INSN_BRCC_RC },
+ { A5F_INSN_BRCC_RC_D, && case_sem_INSN_BRCC_RC_D },
+ { A5F_INSN_BRCC_U6, && case_sem_INSN_BRCC_U6 },
+ { A5F_INSN_BRCC_U6_D, && case_sem_INSN_BRCC_U6_D },
+ { A5F_INSN_BL_S, && case_sem_INSN_BL_S },
+ { A5F_INSN_BLCC, && case_sem_INSN_BLCC },
+ { A5F_INSN_BLCC_D, && case_sem_INSN_BLCC_D },
+ { A5F_INSN_BL, && case_sem_INSN_BL },
+ { A5F_INSN_BL_D, && case_sem_INSN_BL_D },
+ { A5F_INSN_LD_ABS, && case_sem_INSN_LD_ABS },
+ { A5F_INSN_LD__AW_ABS, && case_sem_INSN_LD__AW_ABS },
+ { A5F_INSN_LD_AB_ABS, && case_sem_INSN_LD_AB_ABS },
+ { A5F_INSN_LD_AS_ABS, && case_sem_INSN_LD_AS_ABS },
+ { A5F_INSN_LD_ABC, && case_sem_INSN_LD_ABC },
+ { A5F_INSN_LD__AW_ABC, && case_sem_INSN_LD__AW_ABC },
+ { A5F_INSN_LD_AB_ABC, && case_sem_INSN_LD_AB_ABC },
+ { A5F_INSN_LD_AS_ABC, && case_sem_INSN_LD_AS_ABC },
+ { A5F_INSN_LD_S_ABC, && case_sem_INSN_LD_S_ABC },
+ { A5F_INSN_LD_S_ABU, && case_sem_INSN_LD_S_ABU },
+ { A5F_INSN_LD_S_ABSP, && case_sem_INSN_LD_S_ABSP },
+ { A5F_INSN_LD_S_GPREL, && case_sem_INSN_LD_S_GPREL },
+ { A5F_INSN_LD_S_PCREL, && case_sem_INSN_LD_S_PCREL },
+ { A5F_INSN_LDB_ABS, && case_sem_INSN_LDB_ABS },
+ { A5F_INSN_LDB__AW_ABS, && case_sem_INSN_LDB__AW_ABS },
+ { A5F_INSN_LDB_AB_ABS, && case_sem_INSN_LDB_AB_ABS },
+ { A5F_INSN_LDB_AS_ABS, && case_sem_INSN_LDB_AS_ABS },
+ { A5F_INSN_LDB_ABC, && case_sem_INSN_LDB_ABC },
+ { A5F_INSN_LDB__AW_ABC, && case_sem_INSN_LDB__AW_ABC },
+ { A5F_INSN_LDB_AB_ABC, && case_sem_INSN_LDB_AB_ABC },
+ { A5F_INSN_LDB_AS_ABC, && case_sem_INSN_LDB_AS_ABC },
+ { A5F_INSN_LDB_S_ABC, && case_sem_INSN_LDB_S_ABC },
+ { A5F_INSN_LDB_S_ABU, && case_sem_INSN_LDB_S_ABU },
+ { A5F_INSN_LDB_S_ABSP, && case_sem_INSN_LDB_S_ABSP },
+ { A5F_INSN_LDB_S_GPREL, && case_sem_INSN_LDB_S_GPREL },
+ { A5F_INSN_LDB_X_ABS, && case_sem_INSN_LDB_X_ABS },
+ { A5F_INSN_LDB__AW_X_ABS, && case_sem_INSN_LDB__AW_X_ABS },
+ { A5F_INSN_LDB_AB_X_ABS, && case_sem_INSN_LDB_AB_X_ABS },
+ { A5F_INSN_LDB_AS_X_ABS, && case_sem_INSN_LDB_AS_X_ABS },
+ { A5F_INSN_LDB_X_ABC, && case_sem_INSN_LDB_X_ABC },
+ { A5F_INSN_LDB__AW_X_ABC, && case_sem_INSN_LDB__AW_X_ABC },
+ { A5F_INSN_LDB_AB_X_ABC, && case_sem_INSN_LDB_AB_X_ABC },
+ { A5F_INSN_LDB_AS_X_ABC, && case_sem_INSN_LDB_AS_X_ABC },
+ { A5F_INSN_LDW_ABS, && case_sem_INSN_LDW_ABS },
+ { A5F_INSN_LDW__AW_ABS, && case_sem_INSN_LDW__AW_ABS },
+ { A5F_INSN_LDW_AB_ABS, && case_sem_INSN_LDW_AB_ABS },
+ { A5F_INSN_LDW_AS_ABS, && case_sem_INSN_LDW_AS_ABS },
+ { A5F_INSN_LDW_ABC, && case_sem_INSN_LDW_ABC },
+ { A5F_INSN_LDW__AW_ABC, && case_sem_INSN_LDW__AW_ABC },
+ { A5F_INSN_LDW_AB_ABC, && case_sem_INSN_LDW_AB_ABC },
+ { A5F_INSN_LDW_AS_ABC, && case_sem_INSN_LDW_AS_ABC },
+ { A5F_INSN_LDW_S_ABC, && case_sem_INSN_LDW_S_ABC },
+ { A5F_INSN_LDW_S_ABU, && case_sem_INSN_LDW_S_ABU },
+ { A5F_INSN_LDW_S_GPREL, && case_sem_INSN_LDW_S_GPREL },
+ { A5F_INSN_LDW_X_ABS, && case_sem_INSN_LDW_X_ABS },
+ { A5F_INSN_LDW__AW_X_ABS, && case_sem_INSN_LDW__AW_X_ABS },
+ { A5F_INSN_LDW_AB_X_ABS, && case_sem_INSN_LDW_AB_X_ABS },
+ { A5F_INSN_LDW_AS_X_ABS, && case_sem_INSN_LDW_AS_X_ABS },
+ { A5F_INSN_LDW_X_ABC, && case_sem_INSN_LDW_X_ABC },
+ { A5F_INSN_LDW__AW_X_ABC, && case_sem_INSN_LDW__AW_X_ABC },
+ { A5F_INSN_LDW_AB_X_ABC, && case_sem_INSN_LDW_AB_X_ABC },
+ { A5F_INSN_LDW_AS_X_ABC, && case_sem_INSN_LDW_AS_X_ABC },
+ { A5F_INSN_LDW_S_X_ABU, && case_sem_INSN_LDW_S_X_ABU },
+ { A5F_INSN_ST_ABS, && case_sem_INSN_ST_ABS },
+ { A5F_INSN_ST__AW_ABS, && case_sem_INSN_ST__AW_ABS },
+ { A5F_INSN_ST_AB_ABS, && case_sem_INSN_ST_AB_ABS },
+ { A5F_INSN_ST_AS_ABS, && case_sem_INSN_ST_AS_ABS },
+ { A5F_INSN_ST_S_ABU, && case_sem_INSN_ST_S_ABU },
+ { A5F_INSN_ST_S_ABSP, && case_sem_INSN_ST_S_ABSP },
+ { A5F_INSN_STB_ABS, && case_sem_INSN_STB_ABS },
+ { A5F_INSN_STB__AW_ABS, && case_sem_INSN_STB__AW_ABS },
+ { A5F_INSN_STB_AB_ABS, && case_sem_INSN_STB_AB_ABS },
+ { A5F_INSN_STB_AS_ABS, && case_sem_INSN_STB_AS_ABS },
+ { A5F_INSN_STB_S_ABU, && case_sem_INSN_STB_S_ABU },
+ { A5F_INSN_STB_S_ABSP, && case_sem_INSN_STB_S_ABSP },
+ { A5F_INSN_STW_ABS, && case_sem_INSN_STW_ABS },
+ { A5F_INSN_STW__AW_ABS, && case_sem_INSN_STW__AW_ABS },
+ { A5F_INSN_STW_AB_ABS, && case_sem_INSN_STW_AB_ABS },
+ { A5F_INSN_STW_AS_ABS, && case_sem_INSN_STW_AS_ABS },
+ { A5F_INSN_STW_S_ABU, && case_sem_INSN_STW_S_ABU },
+ { A5F_INSN_ADD_L_S12__RA_, && case_sem_INSN_ADD_L_S12__RA_ },
+ { A5F_INSN_ADD_CCU6__RA_, && case_sem_INSN_ADD_CCU6__RA_ },
+ { A5F_INSN_ADD_L_U6__RA_, && case_sem_INSN_ADD_L_U6__RA_ },
+ { A5F_INSN_ADD_L_R_R__RA__RC, && case_sem_INSN_ADD_L_R_R__RA__RC },
+ { A5F_INSN_ADD_CC__RA__RC, && case_sem_INSN_ADD_CC__RA__RC },
+ { A5F_INSN_ADD_S_ABC, && case_sem_INSN_ADD_S_ABC },
+ { A5F_INSN_ADD_S_CBU3, && case_sem_INSN_ADD_S_CBU3 },
+ { A5F_INSN_ADD_S_MCAH, && case_sem_INSN_ADD_S_MCAH },
+ { A5F_INSN_ADD_S_ABSP, && case_sem_INSN_ADD_S_ABSP },
+ { A5F_INSN_ADD_S_ASSPSP, && case_sem_INSN_ADD_S_ASSPSP },
+ { A5F_INSN_ADD_S_GP, && case_sem_INSN_ADD_S_GP },
+ { A5F_INSN_ADD_S_R_U7, && case_sem_INSN_ADD_S_R_U7 },
+ { A5F_INSN_ADC_L_S12__RA_, && case_sem_INSN_ADC_L_S12__RA_ },
+ { A5F_INSN_ADC_CCU6__RA_, && case_sem_INSN_ADC_CCU6__RA_ },
+ { A5F_INSN_ADC_L_U6__RA_, && case_sem_INSN_ADC_L_U6__RA_ },
+ { A5F_INSN_ADC_L_R_R__RA__RC, && case_sem_INSN_ADC_L_R_R__RA__RC },
+ { A5F_INSN_ADC_CC__RA__RC, && case_sem_INSN_ADC_CC__RA__RC },
+ { A5F_INSN_SUB_L_S12__RA_, && case_sem_INSN_SUB_L_S12__RA_ },
+ { A5F_INSN_SUB_CCU6__RA_, && case_sem_INSN_SUB_CCU6__RA_ },
+ { A5F_INSN_SUB_L_U6__RA_, && case_sem_INSN_SUB_L_U6__RA_ },
+ { A5F_INSN_SUB_L_R_R__RA__RC, && case_sem_INSN_SUB_L_R_R__RA__RC },
+ { A5F_INSN_SUB_CC__RA__RC, && case_sem_INSN_SUB_CC__RA__RC },
+ { A5F_INSN_SUB_S_CBU3, && case_sem_INSN_SUB_S_CBU3 },
+ { A5F_INSN_I16_GO_SUB_S_GO, && case_sem_INSN_I16_GO_SUB_S_GO },
+ { A5F_INSN_SUB_S_GO_SUB_NE, && case_sem_INSN_SUB_S_GO_SUB_NE },
+ { A5F_INSN_SUB_S_SSB, && case_sem_INSN_SUB_S_SSB },
+ { A5F_INSN_SUB_S_ASSPSP, && case_sem_INSN_SUB_S_ASSPSP },
+ { A5F_INSN_SBC_L_S12__RA_, && case_sem_INSN_SBC_L_S12__RA_ },
+ { A5F_INSN_SBC_CCU6__RA_, && case_sem_INSN_SBC_CCU6__RA_ },
+ { A5F_INSN_SBC_L_U6__RA_, && case_sem_INSN_SBC_L_U6__RA_ },
+ { A5F_INSN_SBC_L_R_R__RA__RC, && case_sem_INSN_SBC_L_R_R__RA__RC },
+ { A5F_INSN_SBC_CC__RA__RC, && case_sem_INSN_SBC_CC__RA__RC },
+ { A5F_INSN_AND_L_S12__RA_, && case_sem_INSN_AND_L_S12__RA_ },
+ { A5F_INSN_AND_CCU6__RA_, && case_sem_INSN_AND_CCU6__RA_ },
+ { A5F_INSN_AND_L_U6__RA_, && case_sem_INSN_AND_L_U6__RA_ },
+ { A5F_INSN_AND_L_R_R__RA__RC, && case_sem_INSN_AND_L_R_R__RA__RC },
+ { A5F_INSN_AND_CC__RA__RC, && case_sem_INSN_AND_CC__RA__RC },
+ { A5F_INSN_I16_GO_AND_S_GO, && case_sem_INSN_I16_GO_AND_S_GO },
+ { A5F_INSN_OR_L_S12__RA_, && case_sem_INSN_OR_L_S12__RA_ },
+ { A5F_INSN_OR_CCU6__RA_, && case_sem_INSN_OR_CCU6__RA_ },
+ { A5F_INSN_OR_L_U6__RA_, && case_sem_INSN_OR_L_U6__RA_ },
+ { A5F_INSN_OR_L_R_R__RA__RC, && case_sem_INSN_OR_L_R_R__RA__RC },
+ { A5F_INSN_OR_CC__RA__RC, && case_sem_INSN_OR_CC__RA__RC },
+ { A5F_INSN_I16_GO_OR_S_GO, && case_sem_INSN_I16_GO_OR_S_GO },
+ { A5F_INSN_BIC_L_S12__RA_, && case_sem_INSN_BIC_L_S12__RA_ },
+ { A5F_INSN_BIC_CCU6__RA_, && case_sem_INSN_BIC_CCU6__RA_ },
+ { A5F_INSN_BIC_L_U6__RA_, && case_sem_INSN_BIC_L_U6__RA_ },
+ { A5F_INSN_BIC_L_R_R__RA__RC, && case_sem_INSN_BIC_L_R_R__RA__RC },
+ { A5F_INSN_BIC_CC__RA__RC, && case_sem_INSN_BIC_CC__RA__RC },
+ { A5F_INSN_I16_GO_BIC_S_GO, && case_sem_INSN_I16_GO_BIC_S_GO },
+ { A5F_INSN_XOR_L_S12__RA_, && case_sem_INSN_XOR_L_S12__RA_ },
+ { A5F_INSN_XOR_CCU6__RA_, && case_sem_INSN_XOR_CCU6__RA_ },
+ { A5F_INSN_XOR_L_U6__RA_, && case_sem_INSN_XOR_L_U6__RA_ },
+ { A5F_INSN_XOR_L_R_R__RA__RC, && case_sem_INSN_XOR_L_R_R__RA__RC },
+ { A5F_INSN_XOR_CC__RA__RC, && case_sem_INSN_XOR_CC__RA__RC },
+ { A5F_INSN_I16_GO_XOR_S_GO, && case_sem_INSN_I16_GO_XOR_S_GO },
+ { A5F_INSN_MAX_L_S12__RA_, && case_sem_INSN_MAX_L_S12__RA_ },
+ { A5F_INSN_MAX_CCU6__RA_, && case_sem_INSN_MAX_CCU6__RA_ },
+ { A5F_INSN_MAX_L_U6__RA_, && case_sem_INSN_MAX_L_U6__RA_ },
+ { A5F_INSN_MAX_L_R_R__RA__RC, && case_sem_INSN_MAX_L_R_R__RA__RC },
+ { A5F_INSN_MAX_CC__RA__RC, && case_sem_INSN_MAX_CC__RA__RC },
+ { A5F_INSN_MIN_L_S12__RA_, && case_sem_INSN_MIN_L_S12__RA_ },
+ { A5F_INSN_MIN_CCU6__RA_, && case_sem_INSN_MIN_CCU6__RA_ },
+ { A5F_INSN_MIN_L_U6__RA_, && case_sem_INSN_MIN_L_U6__RA_ },
+ { A5F_INSN_MIN_L_R_R__RA__RC, && case_sem_INSN_MIN_L_R_R__RA__RC },
+ { A5F_INSN_MIN_CC__RA__RC, && case_sem_INSN_MIN_CC__RA__RC },
+ { A5F_INSN_MOV_L_S12_, && case_sem_INSN_MOV_L_S12_ },
+ { A5F_INSN_MOV_CCU6_, && case_sem_INSN_MOV_CCU6_ },
+ { A5F_INSN_MOV_L_U6_, && case_sem_INSN_MOV_L_U6_ },
+ { A5F_INSN_MOV_L_R_R__RC, && case_sem_INSN_MOV_L_R_R__RC },
+ { A5F_INSN_MOV_CC__RC, && case_sem_INSN_MOV_CC__RC },
+ { A5F_INSN_MOV_S_MCAH, && case_sem_INSN_MOV_S_MCAH },
+ { A5F_INSN_MOV_S_MCAHB, && case_sem_INSN_MOV_S_MCAHB },
+ { A5F_INSN_MOV_S_R_U7, && case_sem_INSN_MOV_S_R_U7 },
+ { A5F_INSN_TST_L_S12_, && case_sem_INSN_TST_L_S12_ },
+ { A5F_INSN_TST_CCU6_, && case_sem_INSN_TST_CCU6_ },
+ { A5F_INSN_TST_L_U6_, && case_sem_INSN_TST_L_U6_ },
+ { A5F_INSN_TST_L_R_R__RC, && case_sem_INSN_TST_L_R_R__RC },
+ { A5F_INSN_TST_CC__RC, && case_sem_INSN_TST_CC__RC },
+ { A5F_INSN_TST_S_GO, && case_sem_INSN_TST_S_GO },
+ { A5F_INSN_CMP_L_S12_, && case_sem_INSN_CMP_L_S12_ },
+ { A5F_INSN_CMP_CCU6_, && case_sem_INSN_CMP_CCU6_ },
+ { A5F_INSN_CMP_L_U6_, && case_sem_INSN_CMP_L_U6_ },
+ { A5F_INSN_CMP_L_R_R__RC, && case_sem_INSN_CMP_L_R_R__RC },
+ { A5F_INSN_CMP_CC__RC, && case_sem_INSN_CMP_CC__RC },
+ { A5F_INSN_CMP_S_MCAH, && case_sem_INSN_CMP_S_MCAH },
+ { A5F_INSN_CMP_S_R_U7, && case_sem_INSN_CMP_S_R_U7 },
+ { A5F_INSN_RCMP_L_S12_, && case_sem_INSN_RCMP_L_S12_ },
+ { A5F_INSN_RCMP_CCU6_, && case_sem_INSN_RCMP_CCU6_ },
+ { A5F_INSN_RCMP_L_U6_, && case_sem_INSN_RCMP_L_U6_ },
+ { A5F_INSN_RCMP_L_R_R__RC, && case_sem_INSN_RCMP_L_R_R__RC },
+ { A5F_INSN_RCMP_CC__RC, && case_sem_INSN_RCMP_CC__RC },
+ { A5F_INSN_RSUB_L_S12__RA_, && case_sem_INSN_RSUB_L_S12__RA_ },
+ { A5F_INSN_RSUB_CCU6__RA_, && case_sem_INSN_RSUB_CCU6__RA_ },
+ { A5F_INSN_RSUB_L_U6__RA_, && case_sem_INSN_RSUB_L_U6__RA_ },
+ { A5F_INSN_RSUB_L_R_R__RA__RC, && case_sem_INSN_RSUB_L_R_R__RA__RC },
+ { A5F_INSN_RSUB_CC__RA__RC, && case_sem_INSN_RSUB_CC__RA__RC },
+ { A5F_INSN_BSET_L_S12__RA_, && case_sem_INSN_BSET_L_S12__RA_ },
+ { A5F_INSN_BSET_CCU6__RA_, && case_sem_INSN_BSET_CCU6__RA_ },
+ { A5F_INSN_BSET_L_U6__RA_, && case_sem_INSN_BSET_L_U6__RA_ },
+ { A5F_INSN_BSET_L_R_R__RA__RC, && case_sem_INSN_BSET_L_R_R__RA__RC },
+ { A5F_INSN_BSET_CC__RA__RC, && case_sem_INSN_BSET_CC__RA__RC },
+ { A5F_INSN_BSET_S_SSB, && case_sem_INSN_BSET_S_SSB },
+ { A5F_INSN_BCLR_L_S12__RA_, && case_sem_INSN_BCLR_L_S12__RA_ },
+ { A5F_INSN_BCLR_CCU6__RA_, && case_sem_INSN_BCLR_CCU6__RA_ },
+ { A5F_INSN_BCLR_L_U6__RA_, && case_sem_INSN_BCLR_L_U6__RA_ },
+ { A5F_INSN_BCLR_L_R_R__RA__RC, && case_sem_INSN_BCLR_L_R_R__RA__RC },
+ { A5F_INSN_BCLR_CC__RA__RC, && case_sem_INSN_BCLR_CC__RA__RC },
+ { A5F_INSN_BCLR_S_SSB, && case_sem_INSN_BCLR_S_SSB },
+ { A5F_INSN_BTST_L_S12_, && case_sem_INSN_BTST_L_S12_ },
+ { A5F_INSN_BTST_CCU6_, && case_sem_INSN_BTST_CCU6_ },
+ { A5F_INSN_BTST_L_U6_, && case_sem_INSN_BTST_L_U6_ },
+ { A5F_INSN_BTST_L_R_R__RC, && case_sem_INSN_BTST_L_R_R__RC },
+ { A5F_INSN_BTST_CC__RC, && case_sem_INSN_BTST_CC__RC },
+ { A5F_INSN_BTST_S_SSB, && case_sem_INSN_BTST_S_SSB },
+ { A5F_INSN_BXOR_L_S12__RA_, && case_sem_INSN_BXOR_L_S12__RA_ },
+ { A5F_INSN_BXOR_CCU6__RA_, && case_sem_INSN_BXOR_CCU6__RA_ },
+ { A5F_INSN_BXOR_L_U6__RA_, && case_sem_INSN_BXOR_L_U6__RA_ },
+ { A5F_INSN_BXOR_L_R_R__RA__RC, && case_sem_INSN_BXOR_L_R_R__RA__RC },
+ { A5F_INSN_BXOR_CC__RA__RC, && case_sem_INSN_BXOR_CC__RA__RC },
+ { A5F_INSN_BMSK_L_S12__RA_, && case_sem_INSN_BMSK_L_S12__RA_ },
+ { A5F_INSN_BMSK_CCU6__RA_, && case_sem_INSN_BMSK_CCU6__RA_ },
+ { A5F_INSN_BMSK_L_U6__RA_, && case_sem_INSN_BMSK_L_U6__RA_ },
+ { A5F_INSN_BMSK_L_R_R__RA__RC, && case_sem_INSN_BMSK_L_R_R__RA__RC },
+ { A5F_INSN_BMSK_CC__RA__RC, && case_sem_INSN_BMSK_CC__RA__RC },
+ { A5F_INSN_BMSK_S_SSB, && case_sem_INSN_BMSK_S_SSB },
+ { A5F_INSN_ADD1_L_S12__RA_, && case_sem_INSN_ADD1_L_S12__RA_ },
+ { A5F_INSN_ADD1_CCU6__RA_, && case_sem_INSN_ADD1_CCU6__RA_ },
+ { A5F_INSN_ADD1_L_U6__RA_, && case_sem_INSN_ADD1_L_U6__RA_ },
+ { A5F_INSN_ADD1_L_R_R__RA__RC, && case_sem_INSN_ADD1_L_R_R__RA__RC },
+ { A5F_INSN_ADD1_CC__RA__RC, && case_sem_INSN_ADD1_CC__RA__RC },
+ { A5F_INSN_I16_GO_ADD1_S_GO, && case_sem_INSN_I16_GO_ADD1_S_GO },
+ { A5F_INSN_ADD2_L_S12__RA_, && case_sem_INSN_ADD2_L_S12__RA_ },
+ { A5F_INSN_ADD2_CCU6__RA_, && case_sem_INSN_ADD2_CCU6__RA_ },
+ { A5F_INSN_ADD2_L_U6__RA_, && case_sem_INSN_ADD2_L_U6__RA_ },
+ { A5F_INSN_ADD2_L_R_R__RA__RC, && case_sem_INSN_ADD2_L_R_R__RA__RC },
+ { A5F_INSN_ADD2_CC__RA__RC, && case_sem_INSN_ADD2_CC__RA__RC },
+ { A5F_INSN_I16_GO_ADD2_S_GO, && case_sem_INSN_I16_GO_ADD2_S_GO },
+ { A5F_INSN_ADD3_L_S12__RA_, && case_sem_INSN_ADD3_L_S12__RA_ },
+ { A5F_INSN_ADD3_CCU6__RA_, && case_sem_INSN_ADD3_CCU6__RA_ },
+ { A5F_INSN_ADD3_L_U6__RA_, && case_sem_INSN_ADD3_L_U6__RA_ },
+ { A5F_INSN_ADD3_L_R_R__RA__RC, && case_sem_INSN_ADD3_L_R_R__RA__RC },
+ { A5F_INSN_ADD3_CC__RA__RC, && case_sem_INSN_ADD3_CC__RA__RC },
+ { A5F_INSN_I16_GO_ADD3_S_GO, && case_sem_INSN_I16_GO_ADD3_S_GO },
+ { A5F_INSN_SUB1_L_S12__RA_, && case_sem_INSN_SUB1_L_S12__RA_ },
+ { A5F_INSN_SUB1_CCU6__RA_, && case_sem_INSN_SUB1_CCU6__RA_ },
+ { A5F_INSN_SUB1_L_U6__RA_, && case_sem_INSN_SUB1_L_U6__RA_ },
+ { A5F_INSN_SUB1_L_R_R__RA__RC, && case_sem_INSN_SUB1_L_R_R__RA__RC },
+ { A5F_INSN_SUB1_CC__RA__RC, && case_sem_INSN_SUB1_CC__RA__RC },
+ { A5F_INSN_SUB2_L_S12__RA_, && case_sem_INSN_SUB2_L_S12__RA_ },
+ { A5F_INSN_SUB2_CCU6__RA_, && case_sem_INSN_SUB2_CCU6__RA_ },
+ { A5F_INSN_SUB2_L_U6__RA_, && case_sem_INSN_SUB2_L_U6__RA_ },
+ { A5F_INSN_SUB2_L_R_R__RA__RC, && case_sem_INSN_SUB2_L_R_R__RA__RC },
+ { A5F_INSN_SUB2_CC__RA__RC, && case_sem_INSN_SUB2_CC__RA__RC },
+ { A5F_INSN_SUB3_L_S12__RA_, && case_sem_INSN_SUB3_L_S12__RA_ },
+ { A5F_INSN_SUB3_CCU6__RA_, && case_sem_INSN_SUB3_CCU6__RA_ },
+ { A5F_INSN_SUB3_L_U6__RA_, && case_sem_INSN_SUB3_L_U6__RA_ },
+ { A5F_INSN_SUB3_L_R_R__RA__RC, && case_sem_INSN_SUB3_L_R_R__RA__RC },
+ { A5F_INSN_SUB3_CC__RA__RC, && case_sem_INSN_SUB3_CC__RA__RC },
+ { A5F_INSN_MPY_L_S12__RA_, && case_sem_INSN_MPY_L_S12__RA_ },
+ { A5F_INSN_MPY_CCU6__RA_, && case_sem_INSN_MPY_CCU6__RA_ },
+ { A5F_INSN_MPY_L_U6__RA_, && case_sem_INSN_MPY_L_U6__RA_ },
+ { A5F_INSN_MPY_L_R_R__RA__RC, && case_sem_INSN_MPY_L_R_R__RA__RC },
+ { A5F_INSN_MPY_CC__RA__RC, && case_sem_INSN_MPY_CC__RA__RC },
+ { A5F_INSN_MPYH_L_S12__RA_, && case_sem_INSN_MPYH_L_S12__RA_ },
+ { A5F_INSN_MPYH_CCU6__RA_, && case_sem_INSN_MPYH_CCU6__RA_ },
+ { A5F_INSN_MPYH_L_U6__RA_, && case_sem_INSN_MPYH_L_U6__RA_ },
+ { A5F_INSN_MPYH_L_R_R__RA__RC, && case_sem_INSN_MPYH_L_R_R__RA__RC },
+ { A5F_INSN_MPYH_CC__RA__RC, && case_sem_INSN_MPYH_CC__RA__RC },
+ { A5F_INSN_MPYHU_L_S12__RA_, && case_sem_INSN_MPYHU_L_S12__RA_ },
+ { A5F_INSN_MPYHU_CCU6__RA_, && case_sem_INSN_MPYHU_CCU6__RA_ },
+ { A5F_INSN_MPYHU_L_U6__RA_, && case_sem_INSN_MPYHU_L_U6__RA_ },
+ { A5F_INSN_MPYHU_L_R_R__RA__RC, && case_sem_INSN_MPYHU_L_R_R__RA__RC },
+ { A5F_INSN_MPYHU_CC__RA__RC, && case_sem_INSN_MPYHU_CC__RA__RC },
+ { A5F_INSN_MPYU_L_S12__RA_, && case_sem_INSN_MPYU_L_S12__RA_ },
+ { A5F_INSN_MPYU_CCU6__RA_, && case_sem_INSN_MPYU_CCU6__RA_ },
+ { A5F_INSN_MPYU_L_U6__RA_, && case_sem_INSN_MPYU_L_U6__RA_ },
+ { A5F_INSN_MPYU_L_R_R__RA__RC, && case_sem_INSN_MPYU_L_R_R__RA__RC },
+ { A5F_INSN_MPYU_CC__RA__RC, && case_sem_INSN_MPYU_CC__RA__RC },
+ { A5F_INSN_J_L_R_R___RC_NOILINK_, && case_sem_INSN_J_L_R_R___RC_NOILINK_ },
+ { A5F_INSN_J_CC___RC_NOILINK_, && case_sem_INSN_J_CC___RC_NOILINK_ },
+ { A5F_INSN_J_L_R_R___RC_ILINK_, && case_sem_INSN_J_L_R_R___RC_ILINK_ },
+ { A5F_INSN_J_CC___RC_ILINK_, && case_sem_INSN_J_CC___RC_ILINK_ },
+ { A5F_INSN_J_L_S12_, && case_sem_INSN_J_L_S12_ },
+ { A5F_INSN_J_CCU6_, && case_sem_INSN_J_CCU6_ },
+ { A5F_INSN_J_L_U6_, && case_sem_INSN_J_L_U6_ },
+ { A5F_INSN_J_S, && case_sem_INSN_J_S },
+ { A5F_INSN_J_S__S, && case_sem_INSN_J_S__S },
+ { A5F_INSN_J_SEQ__S, && case_sem_INSN_J_SEQ__S },
+ { A5F_INSN_J_SNE__S, && case_sem_INSN_J_SNE__S },
+ { A5F_INSN_J_L_S12_D_, && case_sem_INSN_J_L_S12_D_ },
+ { A5F_INSN_J_CCU6_D_, && case_sem_INSN_J_CCU6_D_ },
+ { A5F_INSN_J_L_U6_D_, && case_sem_INSN_J_L_U6_D_ },
+ { A5F_INSN_J_L_R_R_D___RC_, && case_sem_INSN_J_L_R_R_D___RC_ },
+ { A5F_INSN_J_CC_D___RC_, && case_sem_INSN_J_CC_D___RC_ },
+ { A5F_INSN_J_S_D, && case_sem_INSN_J_S_D },
+ { A5F_INSN_J_S__S_D, && case_sem_INSN_J_S__S_D },
+ { A5F_INSN_JL_L_S12_, && case_sem_INSN_JL_L_S12_ },
+ { A5F_INSN_JL_CCU6_, && case_sem_INSN_JL_CCU6_ },
+ { A5F_INSN_JL_L_U6_, && case_sem_INSN_JL_L_U6_ },
+ { A5F_INSN_JL_S, && case_sem_INSN_JL_S },
+ { A5F_INSN_JL_L_R_R___RC_NOILINK_, && case_sem_INSN_JL_L_R_R___RC_NOILINK_ },
+ { A5F_INSN_JL_CC___RC_NOILINK_, && case_sem_INSN_JL_CC___RC_NOILINK_ },
+ { A5F_INSN_JL_L_S12_D_, && case_sem_INSN_JL_L_S12_D_ },
+ { A5F_INSN_JL_CCU6_D_, && case_sem_INSN_JL_CCU6_D_ },
+ { A5F_INSN_JL_L_U6_D_, && case_sem_INSN_JL_L_U6_D_ },
+ { A5F_INSN_JL_L_R_R_D___RC_, && case_sem_INSN_JL_L_R_R_D___RC_ },
+ { A5F_INSN_JL_CC_D___RC_, && case_sem_INSN_JL_CC_D___RC_ },
+ { A5F_INSN_JL_S_D, && case_sem_INSN_JL_S_D },
+ { A5F_INSN_LP_L_S12_, && case_sem_INSN_LP_L_S12_ },
+ { A5F_INSN_LPCC_CCU6, && case_sem_INSN_LPCC_CCU6 },
+ { A5F_INSN_FLAG_L_S12_, && case_sem_INSN_FLAG_L_S12_ },
+ { A5F_INSN_FLAG_CCU6_, && case_sem_INSN_FLAG_CCU6_ },
+ { A5F_INSN_FLAG_L_U6_, && case_sem_INSN_FLAG_L_U6_ },
+ { A5F_INSN_FLAG_L_R_R__RC, && case_sem_INSN_FLAG_L_R_R__RC },
+ { A5F_INSN_FLAG_CC__RC, && case_sem_INSN_FLAG_CC__RC },
+ { A5F_INSN_LR_L_R_R___RC_, && case_sem_INSN_LR_L_R_R___RC_ },
+ { A5F_INSN_LR_L_S12_, && case_sem_INSN_LR_L_S12_ },
+ { A5F_INSN_LR_L_U6_, && case_sem_INSN_LR_L_U6_ },
+ { A5F_INSN_SR_L_R_R___RC_, && case_sem_INSN_SR_L_R_R___RC_ },
+ { A5F_INSN_SR_L_S12_, && case_sem_INSN_SR_L_S12_ },
+ { A5F_INSN_SR_L_U6_, && case_sem_INSN_SR_L_U6_ },
+ { A5F_INSN_ASL_L_R_R__RC, && case_sem_INSN_ASL_L_R_R__RC },
+ { A5F_INSN_ASL_L_U6_, && case_sem_INSN_ASL_L_U6_ },
+ { A5F_INSN_I16_GO_ASL_S_GO, && case_sem_INSN_I16_GO_ASL_S_GO },
+ { A5F_INSN_ASR_L_R_R__RC, && case_sem_INSN_ASR_L_R_R__RC },
+ { A5F_INSN_ASR_L_U6_, && case_sem_INSN_ASR_L_U6_ },
+ { A5F_INSN_I16_GO_ASR_S_GO, && case_sem_INSN_I16_GO_ASR_S_GO },
+ { A5F_INSN_LSR_L_R_R__RC, && case_sem_INSN_LSR_L_R_R__RC },
+ { A5F_INSN_LSR_L_U6_, && case_sem_INSN_LSR_L_U6_ },
+ { A5F_INSN_I16_GO_LSR_S_GO, && case_sem_INSN_I16_GO_LSR_S_GO },
+ { A5F_INSN_ROR_L_R_R__RC, && case_sem_INSN_ROR_L_R_R__RC },
+ { A5F_INSN_ROR_L_U6_, && case_sem_INSN_ROR_L_U6_ },
+ { A5F_INSN_RRC_L_R_R__RC, && case_sem_INSN_RRC_L_R_R__RC },
+ { A5F_INSN_RRC_L_U6_, && case_sem_INSN_RRC_L_U6_ },
+ { A5F_INSN_SEXB_L_R_R__RC, && case_sem_INSN_SEXB_L_R_R__RC },
+ { A5F_INSN_SEXB_L_U6_, && case_sem_INSN_SEXB_L_U6_ },
+ { A5F_INSN_I16_GO_SEXB_S_GO, && case_sem_INSN_I16_GO_SEXB_S_GO },
+ { A5F_INSN_SEXW_L_R_R__RC, && case_sem_INSN_SEXW_L_R_R__RC },
+ { A5F_INSN_SEXW_L_U6_, && case_sem_INSN_SEXW_L_U6_ },
+ { A5F_INSN_I16_GO_SEXW_S_GO, && case_sem_INSN_I16_GO_SEXW_S_GO },
+ { A5F_INSN_EXTB_L_R_R__RC, && case_sem_INSN_EXTB_L_R_R__RC },
+ { A5F_INSN_EXTB_L_U6_, && case_sem_INSN_EXTB_L_U6_ },
+ { A5F_INSN_I16_GO_EXTB_S_GO, && case_sem_INSN_I16_GO_EXTB_S_GO },
+ { A5F_INSN_EXTW_L_R_R__RC, && case_sem_INSN_EXTW_L_R_R__RC },
+ { A5F_INSN_EXTW_L_U6_, && case_sem_INSN_EXTW_L_U6_ },
+ { A5F_INSN_I16_GO_EXTW_S_GO, && case_sem_INSN_I16_GO_EXTW_S_GO },
+ { A5F_INSN_ABS_L_R_R__RC, && case_sem_INSN_ABS_L_R_R__RC },
+ { A5F_INSN_ABS_L_U6_, && case_sem_INSN_ABS_L_U6_ },
+ { A5F_INSN_I16_GO_ABS_S_GO, && case_sem_INSN_I16_GO_ABS_S_GO },
+ { A5F_INSN_NOT_L_R_R__RC, && case_sem_INSN_NOT_L_R_R__RC },
+ { A5F_INSN_NOT_L_U6_, && case_sem_INSN_NOT_L_U6_ },
+ { A5F_INSN_I16_GO_NOT_S_GO, && case_sem_INSN_I16_GO_NOT_S_GO },
+ { A5F_INSN_RLC_L_R_R__RC, && case_sem_INSN_RLC_L_R_R__RC },
+ { A5F_INSN_RLC_L_U6_, && case_sem_INSN_RLC_L_U6_ },
+ { A5F_INSN_I16_GO_NEG_S_GO, && case_sem_INSN_I16_GO_NEG_S_GO },
+ { A5F_INSN_SWI, && case_sem_INSN_SWI },
+ { A5F_INSN_TRAP_S, && case_sem_INSN_TRAP_S },
+ { A5F_INSN_BRK, && case_sem_INSN_BRK },
+ { A5F_INSN_BRK_S, && case_sem_INSN_BRK_S },
+ { A5F_INSN_ASL_L_S12__RA_, && case_sem_INSN_ASL_L_S12__RA_ },
+ { A5F_INSN_ASL_CCU6__RA_, && case_sem_INSN_ASL_CCU6__RA_ },
+ { A5F_INSN_ASL_L_U6__RA_, && case_sem_INSN_ASL_L_U6__RA_ },
+ { A5F_INSN_ASL_L_R_R__RA__RC, && case_sem_INSN_ASL_L_R_R__RA__RC },
+ { A5F_INSN_ASL_CC__RA__RC, && case_sem_INSN_ASL_CC__RA__RC },
+ { A5F_INSN_ASL_S_CBU3, && case_sem_INSN_ASL_S_CBU3 },
+ { A5F_INSN_ASL_S_SSB, && case_sem_INSN_ASL_S_SSB },
+ { A5F_INSN_I16_GO_ASLM_S_GO, && case_sem_INSN_I16_GO_ASLM_S_GO },
+ { A5F_INSN_LSR_L_S12__RA_, && case_sem_INSN_LSR_L_S12__RA_ },
+ { A5F_INSN_LSR_CCU6__RA_, && case_sem_INSN_LSR_CCU6__RA_ },
+ { A5F_INSN_LSR_L_U6__RA_, && case_sem_INSN_LSR_L_U6__RA_ },
+ { A5F_INSN_LSR_L_R_R__RA__RC, && case_sem_INSN_LSR_L_R_R__RA__RC },
+ { A5F_INSN_LSR_CC__RA__RC, && case_sem_INSN_LSR_CC__RA__RC },
+ { A5F_INSN_LSR_S_SSB, && case_sem_INSN_LSR_S_SSB },
+ { A5F_INSN_I16_GO_LSRM_S_GO, && case_sem_INSN_I16_GO_LSRM_S_GO },
+ { A5F_INSN_ASR_L_S12__RA_, && case_sem_INSN_ASR_L_S12__RA_ },
+ { A5F_INSN_ASR_CCU6__RA_, && case_sem_INSN_ASR_CCU6__RA_ },
+ { A5F_INSN_ASR_L_U6__RA_, && case_sem_INSN_ASR_L_U6__RA_ },
+ { A5F_INSN_ASR_L_R_R__RA__RC, && case_sem_INSN_ASR_L_R_R__RA__RC },
+ { A5F_INSN_ASR_CC__RA__RC, && case_sem_INSN_ASR_CC__RA__RC },
+ { A5F_INSN_ASR_S_CBU3, && case_sem_INSN_ASR_S_CBU3 },
+ { A5F_INSN_ASR_S_SSB, && case_sem_INSN_ASR_S_SSB },
+ { A5F_INSN_I16_GO_ASRM_S_GO, && case_sem_INSN_I16_GO_ASRM_S_GO },
+ { A5F_INSN_ROR_L_S12__RA_, && case_sem_INSN_ROR_L_S12__RA_ },
+ { A5F_INSN_ROR_CCU6__RA_, && case_sem_INSN_ROR_CCU6__RA_ },
+ { A5F_INSN_ROR_L_U6__RA_, && case_sem_INSN_ROR_L_U6__RA_ },
+ { A5F_INSN_ROR_L_R_R__RA__RC, && case_sem_INSN_ROR_L_R_R__RA__RC },
+ { A5F_INSN_ROR_CC__RA__RC, && case_sem_INSN_ROR_CC__RA__RC },
+ { A5F_INSN_MUL64_L_S12_, && case_sem_INSN_MUL64_L_S12_ },
+ { A5F_INSN_MUL64_CCU6_, && case_sem_INSN_MUL64_CCU6_ },
+ { A5F_INSN_MUL64_L_U6_, && case_sem_INSN_MUL64_L_U6_ },
+ { A5F_INSN_MUL64_L_R_R__RC, && case_sem_INSN_MUL64_L_R_R__RC },
+ { A5F_INSN_MUL64_CC__RC, && case_sem_INSN_MUL64_CC__RC },
+ { A5F_INSN_MUL64_S_GO, && case_sem_INSN_MUL64_S_GO },
+ { A5F_INSN_MULU64_L_S12_, && case_sem_INSN_MULU64_L_S12_ },
+ { A5F_INSN_MULU64_CCU6_, && case_sem_INSN_MULU64_CCU6_ },
+ { A5F_INSN_MULU64_L_U6_, && case_sem_INSN_MULU64_L_U6_ },
+ { A5F_INSN_MULU64_L_R_R__RC, && case_sem_INSN_MULU64_L_R_R__RC },
+ { A5F_INSN_MULU64_CC__RC, && case_sem_INSN_MULU64_CC__RC },
+ { A5F_INSN_ADDS_L_S12__RA_, && case_sem_INSN_ADDS_L_S12__RA_ },
+ { A5F_INSN_ADDS_CCU6__RA_, && case_sem_INSN_ADDS_CCU6__RA_ },
+ { A5F_INSN_ADDS_L_U6__RA_, && case_sem_INSN_ADDS_L_U6__RA_ },
+ { A5F_INSN_ADDS_L_R_R__RA__RC, && case_sem_INSN_ADDS_L_R_R__RA__RC },
+ { A5F_INSN_ADDS_CC__RA__RC, && case_sem_INSN_ADDS_CC__RA__RC },
+ { A5F_INSN_SUBS_L_S12__RA_, && case_sem_INSN_SUBS_L_S12__RA_ },
+ { A5F_INSN_SUBS_CCU6__RA_, && case_sem_INSN_SUBS_CCU6__RA_ },
+ { A5F_INSN_SUBS_L_U6__RA_, && case_sem_INSN_SUBS_L_U6__RA_ },
+ { A5F_INSN_SUBS_L_R_R__RA__RC, && case_sem_INSN_SUBS_L_R_R__RA__RC },
+ { A5F_INSN_SUBS_CC__RA__RC, && case_sem_INSN_SUBS_CC__RA__RC },
+ { A5F_INSN_DIVAW_L_S12__RA_, && case_sem_INSN_DIVAW_L_S12__RA_ },
+ { A5F_INSN_DIVAW_CCU6__RA_, && case_sem_INSN_DIVAW_CCU6__RA_ },
+ { A5F_INSN_DIVAW_L_U6__RA_, && case_sem_INSN_DIVAW_L_U6__RA_ },
+ { A5F_INSN_DIVAW_L_R_R__RA__RC, && case_sem_INSN_DIVAW_L_R_R__RA__RC },
+ { A5F_INSN_DIVAW_CC__RA__RC, && case_sem_INSN_DIVAW_CC__RA__RC },
+ { A5F_INSN_ASLS_L_S12__RA_, && case_sem_INSN_ASLS_L_S12__RA_ },
+ { A5F_INSN_ASLS_CCU6__RA_, && case_sem_INSN_ASLS_CCU6__RA_ },
+ { A5F_INSN_ASLS_L_U6__RA_, && case_sem_INSN_ASLS_L_U6__RA_ },
+ { A5F_INSN_ASLS_L_R_R__RA__RC, && case_sem_INSN_ASLS_L_R_R__RA__RC },
+ { A5F_INSN_ASLS_CC__RA__RC, && case_sem_INSN_ASLS_CC__RA__RC },
+ { A5F_INSN_ASRS_L_S12__RA_, && case_sem_INSN_ASRS_L_S12__RA_ },
+ { A5F_INSN_ASRS_CCU6__RA_, && case_sem_INSN_ASRS_CCU6__RA_ },
+ { A5F_INSN_ASRS_L_U6__RA_, && case_sem_INSN_ASRS_L_U6__RA_ },
+ { A5F_INSN_ASRS_L_R_R__RA__RC, && case_sem_INSN_ASRS_L_R_R__RA__RC },
+ { A5F_INSN_ASRS_CC__RA__RC, && case_sem_INSN_ASRS_CC__RA__RC },
+ { A5F_INSN_ADDSDW_L_S12__RA_, && case_sem_INSN_ADDSDW_L_S12__RA_ },
+ { A5F_INSN_ADDSDW_CCU6__RA_, && case_sem_INSN_ADDSDW_CCU6__RA_ },
+ { A5F_INSN_ADDSDW_L_U6__RA_, && case_sem_INSN_ADDSDW_L_U6__RA_ },
+ { A5F_INSN_ADDSDW_L_R_R__RA__RC, && case_sem_INSN_ADDSDW_L_R_R__RA__RC },
+ { A5F_INSN_ADDSDW_CC__RA__RC, && case_sem_INSN_ADDSDW_CC__RA__RC },
+ { A5F_INSN_SUBSDW_L_S12__RA_, && case_sem_INSN_SUBSDW_L_S12__RA_ },
+ { A5F_INSN_SUBSDW_CCU6__RA_, && case_sem_INSN_SUBSDW_CCU6__RA_ },
+ { A5F_INSN_SUBSDW_L_U6__RA_, && case_sem_INSN_SUBSDW_L_U6__RA_ },
+ { A5F_INSN_SUBSDW_L_R_R__RA__RC, && case_sem_INSN_SUBSDW_L_R_R__RA__RC },
+ { A5F_INSN_SUBSDW_CC__RA__RC, && case_sem_INSN_SUBSDW_CC__RA__RC },
+ { A5F_INSN_SWAP_L_R_R__RC, && case_sem_INSN_SWAP_L_R_R__RC },
+ { A5F_INSN_SWAP_L_U6_, && case_sem_INSN_SWAP_L_U6_ },
+ { A5F_INSN_NORM_L_R_R__RC, && case_sem_INSN_NORM_L_R_R__RC },
+ { A5F_INSN_NORM_L_U6_, && case_sem_INSN_NORM_L_U6_ },
+ { A5F_INSN_RND16_L_R_R__RC, && case_sem_INSN_RND16_L_R_R__RC },
+ { A5F_INSN_RND16_L_U6_, && case_sem_INSN_RND16_L_U6_ },
+ { A5F_INSN_ABSSW_L_R_R__RC, && case_sem_INSN_ABSSW_L_R_R__RC },
+ { A5F_INSN_ABSSW_L_U6_, && case_sem_INSN_ABSSW_L_U6_ },
+ { A5F_INSN_ABSS_L_R_R__RC, && case_sem_INSN_ABSS_L_R_R__RC },
+ { A5F_INSN_ABSS_L_U6_, && case_sem_INSN_ABSS_L_U6_ },
+ { A5F_INSN_NEGSW_L_R_R__RC, && case_sem_INSN_NEGSW_L_R_R__RC },
+ { A5F_INSN_NEGSW_L_U6_, && case_sem_INSN_NEGSW_L_U6_ },
+ { A5F_INSN_NEGS_L_R_R__RC, && case_sem_INSN_NEGS_L_R_R__RC },
+ { A5F_INSN_NEGS_L_U6_, && case_sem_INSN_NEGS_L_U6_ },
+ { A5F_INSN_NORMW_L_R_R__RC, && case_sem_INSN_NORMW_L_R_R__RC },
+ { A5F_INSN_NORMW_L_U6_, && case_sem_INSN_NORMW_L_U6_ },
+ { A5F_INSN_NOP_S, && case_sem_INSN_NOP_S },
+ { A5F_INSN_UNIMP_S, && case_sem_INSN_UNIMP_S },
+ { A5F_INSN_POP_S_B, && case_sem_INSN_POP_S_B },
+ { A5F_INSN_POP_S_BLINK, && case_sem_INSN_POP_S_BLINK },
+ { A5F_INSN_PUSH_S_B, && case_sem_INSN_PUSH_S_B },
+ { A5F_INSN_PUSH_S_BLINK, && case_sem_INSN_PUSH_S_BLINK },
+ { A5F_INSN_MULLW_L_S12__RA_, && case_sem_INSN_MULLW_L_S12__RA_ },
+ { A5F_INSN_MULLW_CCU6__RA_, && case_sem_INSN_MULLW_CCU6__RA_ },
+ { A5F_INSN_MULLW_L_U6__RA_, && case_sem_INSN_MULLW_L_U6__RA_ },
+ { A5F_INSN_MULLW_L_R_R__RA__RC, && case_sem_INSN_MULLW_L_R_R__RA__RC },
+ { A5F_INSN_MULLW_CC__RA__RC, && case_sem_INSN_MULLW_CC__RA__RC },
+ { A5F_INSN_MACLW_L_S12__RA_, && case_sem_INSN_MACLW_L_S12__RA_ },
+ { A5F_INSN_MACLW_CCU6__RA_, && case_sem_INSN_MACLW_CCU6__RA_ },
+ { A5F_INSN_MACLW_L_U6__RA_, && case_sem_INSN_MACLW_L_U6__RA_ },
+ { A5F_INSN_MACLW_L_R_R__RA__RC, && case_sem_INSN_MACLW_L_R_R__RA__RC },
+ { A5F_INSN_MACLW_CC__RA__RC, && case_sem_INSN_MACLW_CC__RA__RC },
+ { A5F_INSN_MACHLW_L_S12__RA_, && case_sem_INSN_MACHLW_L_S12__RA_ },
+ { A5F_INSN_MACHLW_CCU6__RA_, && case_sem_INSN_MACHLW_CCU6__RA_ },
+ { A5F_INSN_MACHLW_L_U6__RA_, && case_sem_INSN_MACHLW_L_U6__RA_ },
+ { A5F_INSN_MACHLW_L_R_R__RA__RC, && case_sem_INSN_MACHLW_L_R_R__RA__RC },
+ { A5F_INSN_MACHLW_CC__RA__RC, && case_sem_INSN_MACHLW_CC__RA__RC },
+ { A5F_INSN_MULULW_L_S12__RA_, && case_sem_INSN_MULULW_L_S12__RA_ },
+ { A5F_INSN_MULULW_CCU6__RA_, && case_sem_INSN_MULULW_CCU6__RA_ },
+ { A5F_INSN_MULULW_L_U6__RA_, && case_sem_INSN_MULULW_L_U6__RA_ },
+ { A5F_INSN_MULULW_L_R_R__RA__RC, && case_sem_INSN_MULULW_L_R_R__RA__RC },
+ { A5F_INSN_MULULW_CC__RA__RC, && case_sem_INSN_MULULW_CC__RA__RC },
+ { A5F_INSN_MACHULW_L_S12__RA_, && case_sem_INSN_MACHULW_L_S12__RA_ },
+ { A5F_INSN_MACHULW_CCU6__RA_, && case_sem_INSN_MACHULW_CCU6__RA_ },
+ { A5F_INSN_MACHULW_L_U6__RA_, && case_sem_INSN_MACHULW_L_U6__RA_ },
+ { A5F_INSN_MACHULW_L_R_R__RA__RC, && case_sem_INSN_MACHULW_L_R_R__RA__RC },
+ { A5F_INSN_MACHULW_CC__RA__RC, && case_sem_INSN_MACHULW_CC__RA__RC },
+ { A5F_INSN_CURRENT_LOOP_END, && case_sem_INSN_CURRENT_LOOP_END },
+ { A5F_INSN_CURRENT_LOOP_END_AFTER_BRANCH, && case_sem_INSN_CURRENT_LOOP_END_AFTER_BRANCH },
+ { A5F_INSN_ARC600_CURRENT_LOOP_END_AFTER_BRANCH, && case_sem_INSN_ARC600_CURRENT_LOOP_END_AFTER_BRANCH },
+ { 0, 0 }
+ };
+ int i;
+
+ for (i = 0; labels[i].label != 0; ++i)
+ {
+#if FAST_P
+ CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
+#else
+ CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
+#endif
+ }
+
+#undef DEFINE_LABELS
+#endif /* DEFINE_LABELS */
+
+#ifdef DEFINE_SWITCH
+
+/* If hyper-fast [well not unnecessarily slow] execution is selected, turn
+ off frills like tracing and profiling. */
+/* FIXME: A better way would be to have TRACE_RESULT check for something
+ that can cause it to be optimized out. Another way would be to emit
+ special handlers into the instruction "stream". */
+
+#if FAST_P
+#undef TRACE_RESULT
+#define TRACE_RESULT(cpu, abuf, name, type, val)
+#endif
+
+#undef GET_ATTR
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
+#else
+#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr)
+#endif
+
+{
+
+#if WITH_SCACHE_PBB
+
+/* Branch to next handler without going around main loop. */
+#define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
+SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
+
+#else /* ! WITH_SCACHE_PBB */
+
+#define NEXT(vpc) BREAK (sem)
+#ifdef __GNUC__
+#if FAST_P
+ SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
+#else
+ SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
+#endif
+#else
+ SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
+#endif
+
+#endif /* ! WITH_SCACHE_PBB */
+
+ {
+
+ CASE (sem, INSN_X_INVALID) : /* --invalid-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+ /* Update the recorded pc in the cpu state struct.
+ Only necessary for WITH_SCACHE case, but to avoid the
+ conditional compilation .... */
+ SET_H_PC (pc);
+ /* Virtual insns have zero size. Overwrite vpc with address of next insn
+ using the default-insn-bitsize spec. When executing insns in parallel
+ we may want to queue the fault and continue execution. */
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+ vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_AFTER) : /* --after-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_A5F
+ a5f_pbb_after (current_cpu, sem_arg);
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_BEFORE) : /* --before-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_A5F
+ a5f_pbb_before (current_cpu, sem_arg);
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_A5F
+#ifdef DEFINE_SWITCH
+ vpc = a5f_pbb_cti_chain (current_cpu, sem_arg,
+ pbb_br_type, pbb_br_npc);
+ BREAK (sem);
+#else
+ /* FIXME: Allow provision of explicit ifmt spec in insn spec. */
+ vpc = a5f_pbb_cti_chain (current_cpu, sem_arg,
+ CPU_PBB_BR_TYPE (current_cpu),
+ CPU_PBB_BR_NPC (current_cpu));
+#endif
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_CHAIN) : /* --chain-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_A5F
+ vpc = a5f_pbb_chain (current_cpu, sem_arg);
+#ifdef DEFINE_SWITCH
+ BREAK (sem);
+#endif
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_BEGIN) : /* --begin-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_A5F
+#if defined DEFINE_SWITCH || defined FAST_P
+ /* In the switch case FAST_P is a constant, allowing several optimizations
+ in any called inline functions. */
+ vpc = a5f_pbb_begin (current_cpu, FAST_P);
+#else
+#if 0 /* cgen engine can't handle dynamic fast/full switching yet. */
+ vpc = a5f_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
+#else
+ vpc = a5f_pbb_begin (current_cpu, 0);
+#endif
+#endif
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_B_S) : /* b$i2cond $label10 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_b_s.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GET_H_I2COND (FLD (f_cond_i2))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = FLD (i_label10);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = FLD (i_label10);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = FLD (i_label10);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BCC_S) : /* b$i3cond$_S $label7 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bcc_s.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GET_H_I3COND (FLD (f_cond_i3))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = FLD (i_label7);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = FLD (i_label7);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = FLD (i_label7);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BRCC_S) : /* br$RccS$_S $R_b,0,$label8 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_brcc_s.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if ((FLD (f_brscond) == 0) ? (EQSI (GET_H_CR16 (FLD (f_op__b)), 0)) : (FLD (f_brscond) == 1) ? (NESI (GET_H_CR16 (FLD (f_op__b)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = FLD (i_label8);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = FLD (i_label8);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = FLD (i_label8);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BCC_L) : /* b$Qcondb$_L $label21 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bcc_l.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+((void) 0); /*nop*/
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = FLD (i_label21);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = FLD (i_label21);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = FLD (i_label21);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BCC_L_D) : /* b$Qcondb$_L.d $label21 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bcc_l.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+((void) 0); /*nop*/
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (i_label21);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else if (1) {
+{
+ {
+ USI opval = FLD (i_label21);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ {
+ USI opval = FLD (i_label21);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_B_L) : /* b$uncondb$_L $label25 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_b_l.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = FLD (i_label25);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = FLD (i_label25);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = FLD (i_label25);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_B_L_D) : /* b$uncondb$_L.d $label25 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_b_l.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (i_label25);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else if (1) {
+{
+ {
+ USI opval = FLD (i_label25);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ {
+ USI opval = FLD (i_label25);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BRCC_RC) : /* b$Rcc $RB,$RC,$label9 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_brcc_RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BRCC_RC_D) : /* b$Rcc.d $RB,$RC,$label9 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_brcc_RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+{
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+{
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+{
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BRCC_U6) : /* b$Rcc $RB,$U6,$label9 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_brcc_U6.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BRCC_U6_D) : /* b$Rcc.d $RB,$U6,$label9 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_brcc_U6.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+{
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+{
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+{
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BL_S) : /* bl$uncondj$_S $label13a */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl_s.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ {
+ SI opval = ADDSI (pc, 2);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label13a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else if (0) {
+{
+ {
+ SI opval = ADDSI (pc, 2);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label13a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ {
+ SI opval = ADDSI (pc, 2);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label13a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BLCC) : /* bl$Qcondj$_L $label21 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_blcc.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+((void) 0); /*nop*/
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label21a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else if (0) {
+{
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label21a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label21a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BLCC_D) : /* bl$Qcondj$_L.d $label21 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_blcc.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+((void) 0); /*nop*/
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+{
+ {
+ USI opval = FLD (i_label21a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+{
+ {
+ USI opval = FLD (i_label21a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+{
+ {
+ USI opval = FLD (i_label21a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BL) : /* bl$uncondj$_L $label25a */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label25a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else if (0) {
+{
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label25a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label25a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BL_D) : /* bl$uncondj$_L.d $label25a */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (i_label25a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (i_label25a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (i_label25a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD_ABS) : /* ld$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD__AW_ABS) : /* ld$_AW$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD_AB_ABS) : /* ld.ab$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD_AS_ABS) : /* ld.as$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s9), 2));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD_ABC) : /* ld$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD__AW_ABC) : /* ld$_AW$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD_AB_ABC) : /* ld.ab$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD_AS_ABC) : /* ld.as$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 2));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD_S_ABC) : /* ld$_S $R_a,[$R_b,$R_c] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), GET_H_CR16 (FLD (f_op__c)));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR16 (FLD (f_op__a), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD_S_ABU) : /* ld$_S $R_c,[$R_b,$sc_u5_] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), FLD (f_u5x4));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD_S_ABSP) : /* ld$_S $R_b,[$SP,$u5x4] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_SP (), FLD (f_u5x4));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD_S_GPREL) : /* ld$_S $R_b,[$GP,$sc_s9_] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_gprel.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_GP (), FLD (f_s9x4));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_R0 (, opval);
+ TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD_S_PCREL) : /* ld$_S $R_b,[$PCL,$u8x4] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_pcrel.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (ANDSI (pc, -4), FLD (f_u8x4));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_ABS) : /* ldb$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB__AW_ABS) : /* ldb$_AW$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_AB_ABS) : /* ldb.ab$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_AS_ABS) : /* ldb.as$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), (cgen_rtx_error (current_cpu, "invalid insn"), 0));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_ABC) : /* ldb$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB__AW_ABC) : /* ldb$_AW$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_AB_ABC) : /* ldb.ab$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_AS_ABC) : /* ldb.as$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), (cgen_rtx_error (current_cpu, "invalid insn"), 0));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_S_ABC) : /* ldb$_S $R_a,[$R_b,$R_c] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), GET_H_CR16 (FLD (f_op__c)));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR16 (FLD (f_op__a), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_S_ABU) : /* ldb$_S $R_c,[$R_b,$sc_u5b] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), FLD (f_u5));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_S_ABSP) : /* ldb$_S $R_b,[$SP,$u5x4] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_SP (), FLD (f_u5x4));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_S_GPREL) : /* ldb$_S $R_b,[$GP,$sc_s9b] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldb_s_gprel.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_GP (), FLD (f_s9x1));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_R0 (, opval);
+ TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_X_ABS) : /* ldb.x$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB__AW_X_ABS) : /* ldb$_AW.x$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_AB_X_ABS) : /* ldb.ab.x$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_AS_X_ABS) : /* ldb.as.x$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), (cgen_rtx_error (current_cpu, "invalid insn"), 0));
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_X_ABC) : /* ldb.x$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB__AW_X_ABC) : /* ldb$_AW.x$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_AB_X_ABC) : /* ldb.ab.x$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_AS_X_ABC) : /* ldb.as.x$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), (cgen_rtx_error (current_cpu, "invalid insn"), 0));
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_ABS) : /* ldw$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW__AW_ABS) : /* ldw$_AW$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_AB_ABS) : /* ldw.ab$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_AS_ABS) : /* ldw.as$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s9), 1));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_ABC) : /* ldw$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW__AW_ABC) : /* ldw$_AW$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_AB_ABC) : /* ldw.ab$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_AS_ABC) : /* ldw.as$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 1));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_S_ABC) : /* ldw$_S $R_a,[$R_b,$R_c] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), GET_H_CR16 (FLD (f_op__c)));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR16 (FLD (f_op__a), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_S_ABU) : /* ldw$_S $R_c,[$R_b,$sc_u5w] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldw_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), FLD (f_u5x2));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_S_GPREL) : /* ldw$_S $R_b,[$GP,$sc_s9w] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldw_s_gprel.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_GP (), FLD (f_s9x2));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_R0 (, opval);
+ TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_X_ABS) : /* ldw.x$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW__AW_X_ABS) : /* ldw$_AW.x$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_AB_X_ABS) : /* ldw.ab.x$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_AS_X_ABS) : /* ldw.as.x$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s9), 1));
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_X_ABC) : /* ldw.x$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW__AW_X_ABC) : /* ldw$_AW.x$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_AB_X_ABC) : /* ldw.ab.x$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_AS_X_ABC) : /* ldw.as.x$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 1));
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_S_X_ABU) : /* ldw$_S.x $R_c,[$R_b,$sc_u5w] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldw_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), FLD (f_u5x2));
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ST_ABS) : /* st$STODi $RC,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMSI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ST__AW_ABS) : /* st$_AW$STODi $RC,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMSI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ST_AB_ABS) : /* st.ab$STODi $RC,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMSI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ST_AS_ABS) : /* st.as$STODi $RC,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s9), 2));
+ {
+ SI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMSI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ST_S_ABU) : /* st$_S $R_c,[$R_b,$sc_u5_] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), FLD (f_u5x4));
+ {
+ SI opval = GET_H_CR16 (FLD (f_op__c));
+ SETMEMSI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ST_S_ABSP) : /* st$_S $R_b,[$SP,$u5x4] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_SP (), FLD (f_u5x4));
+ {
+ SI opval = GET_H_CR16 (FLD (f_op__b));
+ SETMEMSI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STB_ABS) : /* stb$STODi $RC,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ QI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMQI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STB__AW_ABS) : /* stb$_AW$STODi $RC,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ QI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMQI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STB_AB_ABS) : /* stb.ab$STODi $RC,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ QI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMQI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STB_AS_ABS) : /* stb.as$STODi $RC,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), (cgen_rtx_error (current_cpu, "invalid insn"), 0));
+ {
+ QI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMQI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STB_S_ABU) : /* stb$_S $R_c,[$R_b,$sc_u5b] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), FLD (f_u5));
+ {
+ QI opval = GET_H_CR16 (FLD (f_op__c));
+ SETMEMQI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STB_S_ABSP) : /* stb$_S $R_b,[$SP,$u5x4] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_SP (), FLD (f_u5x4));
+ {
+ QI opval = GET_H_CR16 (FLD (f_op__b));
+ SETMEMQI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STW_ABS) : /* stw$STODi $RC,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ HI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMHI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STW__AW_ABS) : /* stw$_AW$STODi $RC,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ HI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMHI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STW_AB_ABS) : /* stw.ab$STODi $RC,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ HI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMHI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STW_AS_ABS) : /* stw.as$STODi $RC,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s9), 1));
+ {
+ HI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMHI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STW_S_ABU) : /* stw$_S $R_c,[$R_b,$sc_u5w] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldw_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), FLD (f_u5x2));
+ {
+ HI opval = GET_H_CR16 (FLD (f_op__c));
+ SETMEMHI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_L_S12__RA_) : /* add$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_CCU6__RA_) : /* add$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_L_U6__RA_) : /* add$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_L_R_R__RA__RC) : /* add$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_CC__RA__RC) : /* add$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_S_ABC) : /* add$_S $R_a,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ADDSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__a), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_S_CBU3) : /* add$_S $R_c,$R_b,$u3 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u3);
+ {
+ SI opval = ADDSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_S_MCAH) : /* add$_S $R_b,$R_b,$Rh */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+{
+if (EQSI (FLD (f_op_h), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 2));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (2, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_h), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR (FLD (f_op_h));
+ {
+ SI opval = ADDSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_S_ABSP) : /* add$_S $R_b,$SP,$u5x4 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_SP ();
+ tmp_C = FLD (f_u5x4);
+ {
+ SI opval = ADDSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_S_ASSPSP) : /* add$_S $SP,$SP,$u5x4 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_SP ();
+ tmp_C = FLD (f_u5x4);
+ {
+ SI opval = ADDSI (tmp_B, tmp_C);
+ SET_H_SP (, opval);
+ TRACE_RESULT (current_cpu, abuf, "sp", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_S_GP) : /* add$_S $R0,$GP,$s9x4 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_gprel.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_GP ();
+ tmp_C = FLD (f_s9x4);
+ {
+ SI opval = ADDSI (tmp_B, tmp_C);
+ SET_H_R0 (, opval);
+ TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_S_R_U7) : /* add$_S $R_b,$R_b,$u7 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_r_u7.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u7);
+ {
+ SI opval = ADDSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADC_L_S12__RA_) : /* adc$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDCSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADC_CCU6__RA_) : /* adc$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDCSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADC_L_U6__RA_) : /* adc$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDCSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADC_L_R_R__RA__RC) : /* adc$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDCSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADC_CC__RA__RC) : /* adc$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDCSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_L_S12__RA_) : /* sub$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_CCU6__RA_) : /* sub$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_L_U6__RA_) : /* sub$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_L_R_R__RA__RC) : /* sub$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_CC__RA__RC) : /* sub$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_S_CBU3) : /* sub$_S $R_c,$R_b,$u3 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u3);
+ {
+ SI opval = SUBSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_SUB_S_GO) : /* sub$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = SUBSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_S_GO_SUB_NE) : /* sub$_S $NE$R_b,$R_b,$R_b */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQBI (CPU (h_zbit), 0)) {
+ {
+ SI opval = 0;
+ SET_H_CR16 (FLD (f_op__b), opval);
+ written |= (1 << 1);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_S_SSB) : /* sub$_S $R_b,$R_b,$u5 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ {
+ SI opval = SUBSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_S_ASSPSP) : /* sub$_S $SP,$SP,$u5x4 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_SP ();
+ tmp_C = FLD (f_u5x4);
+ {
+ SI opval = SUBSI (tmp_B, tmp_C);
+ SET_H_SP (, opval);
+ TRACE_RESULT (current_cpu, abuf, "sp", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SBC_L_S12__RA_) : /* sbc$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBCSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SBC_CCU6__RA_) : /* sbc$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBCSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SBC_L_U6__RA_) : /* sbc$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBCSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SBC_L_R_R__RA__RC) : /* sbc$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBCSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SBC_CC__RA__RC) : /* sbc$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBCSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_AND_L_S12__RA_) : /* and$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_AND_CCU6__RA_) : /* and$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_AND_L_U6__RA_) : /* and$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_AND_L_R_R__RA__RC) : /* and$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_AND_CC__RA__RC) : /* and$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_AND_S_GO) : /* and$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ANDSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_OR_L_S12__RA_) : /* or$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_OR_CCU6__RA_) : /* or$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_OR_L_U6__RA_) : /* or$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_OR_L_R_R__RA__RC) : /* or$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_OR_CC__RA__RC) : /* or$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_OR_S_GO) : /* or$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ORSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BIC_L_S12__RA_) : /* bic$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (FLD (f_s12)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BIC_CCU6__RA_) : /* bic$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (FLD (f_u6)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BIC_L_U6__RA_) : /* bic$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (FLD (f_u6)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BIC_L_R_R__RA__RC) : /* bic$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BIC_CC__RA__RC) : /* bic$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_BIC_S_GO) : /* bic$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ANDSI (tmp_B, INVSI (tmp_C));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_XOR_L_S12__RA_) : /* xor$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_XOR_CCU6__RA_) : /* xor$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_XOR_L_U6__RA_) : /* xor$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_XOR_L_R_R__RA__RC) : /* xor$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_XOR_CC__RA__RC) : /* xor$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_XOR_S_GO) : /* xor$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = XORSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MAX_L_S12__RA_) : /* max$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (GTSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12))) ? (GET_H_CR (FLD (f_op_B))) : (FLD (f_s12));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = GESI (FLD (f_s12), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MAX_CCU6__RA_) : /* max$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (GTSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6))) ? (GET_H_CR (FLD (f_op_B))) : (FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = GESI (FLD (f_u6), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MAX_L_U6__RA_) : /* max$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (GTSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6))) ? (GET_H_CR (FLD (f_op_B))) : (FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = GESI (FLD (f_u6), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MAX_L_R_R__RA__RC) : /* max$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (GTSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)))) ? (GET_H_CR (FLD (f_op_B))) : (GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = GESI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MAX_CC__RA__RC) : /* max$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (GTSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)))) ? (GET_H_CR (FLD (f_op_B))) : (GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = GESI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MIN_L_S12__RA_) : /* min$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (LTSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12))) ? (GET_H_CR (FLD (f_op_B))) : (FLD (f_s12));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = LESI (FLD (f_s12), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MIN_CCU6__RA_) : /* min$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (LTSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6))) ? (GET_H_CR (FLD (f_op_B))) : (FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = LESI (FLD (f_u6), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MIN_L_U6__RA_) : /* min$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (LTSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6))) ? (GET_H_CR (FLD (f_op_B))) : (FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = LESI (FLD (f_u6), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MIN_L_R_R__RA__RC) : /* min$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (LTSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)))) ? (GET_H_CR (FLD (f_op_B))) : (GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = LESI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MIN_CC__RA__RC) : /* min$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (LTSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)))) ? (GET_H_CR (FLD (f_op_B))) : (GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = LESI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOV_L_S12_) : /* mov$_L$F $RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+ tmp_result = FLD (f_s12);
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GTSI (FLD (f_F), 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOV_CCU6_) : /* mov$Qcondi$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+((void) 0); /*nop*/
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+ tmp_result = FLD (f_u6);
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GTSI (FLD (f_F), 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 5);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOV_L_U6_) : /* mov$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+ tmp_result = FLD (f_u6);
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GTSI (FLD (f_F), 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOV_L_R_R__RC) : /* mov$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = GET_H_CR (FLD (f_op_C));
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GTSI (FLD (f_F), 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOV_CC__RC) : /* mov$Qcondi$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+ tmp_result = GET_H_CR (FLD (f_op_C));
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GTSI (FLD (f_F), 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOV_S_MCAH) : /* mov$_S $R_b,$Rh */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_h), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 2));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (2, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_h), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = GET_H_CR (FLD (f_op_h));
+ {
+ SI opval = tmp_result;
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+if (GTSI (-1, 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOV_S_MCAHB) : /* mov$_S $Rh,$R_b */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+ tmp_result = GET_H_CR16 (FLD (f_op__b));
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_h), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GTSI (-1, 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOV_S_R_U7) : /* mov$_S $R_b,$u7 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+ tmp_result = FLD (f_u8);
+ {
+ SI opval = tmp_result;
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+if (GTSI (-1, 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_TST_L_S12_) : /* tst$_L$F1 $RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_s12);
+ tmp_result = ANDSI (tmp_B, tmp_C);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_TST_CCU6_) : /* tst$Qcondi$F1 $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+ tmp_result = ANDSI (tmp_B, tmp_C);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_TST_L_U6_) : /* tst$_L$F1 $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+ tmp_result = ANDSI (tmp_B, tmp_C);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_TST_L_R_R__RC) : /* tst$_L$F1 $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+ tmp_result = ANDSI (tmp_B, tmp_C);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_TST_CC__RC) : /* tst$Qcondi$F1 $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+ tmp_result = ANDSI (tmp_B, tmp_C);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_TST_S_GO) : /* tst$_S $R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ tmp_result = ANDSI (tmp_B, tmp_C);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMP_L_S12_) : /* cmp$_L$F1 $RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (FLD (f_s12));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (FLD (f_s12));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMP_CCU6_) : /* cmp$Qcondi$F1 $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMP_L_U6_) : /* cmp$_L$F1 $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMP_L_R_R__RC) : /* cmp$_L$F1 $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMP_CC__RC) : /* cmp$Qcondi$F1 $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMP_S_MCAH) : /* cmp$_S $R_b,$Rh */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+{
+if (EQSI (FLD (f_op_h), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 2));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (2, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_h), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = EXTSIDI (GET_H_CR16 (FLD (f_op__b)));
+ tmp_C = EXTSIDI (GET_H_CR (FLD (f_op_h)));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR16 (FLD (f_op__b)));
+ tmp_C = ZEXTSIDI (GET_H_CR (FLD (f_op_h)));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMP_S_R_U7) : /* cmp$_S $R_b,$u7 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_r_u7.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = EXTSIDI (GET_H_CR16 (FLD (f_op__b)));
+ tmp_C = EXTSIDI (FLD (f_u7));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR16 (FLD (f_op__b)));
+ tmp_C = ZEXTSIDI (FLD (f_u7));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RCMP_L_S12_) : /* rcmp$_L$F1 $RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (FLD (f_s12));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (FLD (f_s12));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RCMP_CCU6_) : /* rcmp$Qcondi$F1 $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RCMP_L_U6_) : /* rcmp$_L$F1 $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RCMP_L_R_R__RC) : /* rcmp$_L$F1 $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RCMP_CC__RC) : /* rcmp$Qcondi$F1 $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RSUB_L_S12__RA_) : /* rsub$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (FLD (f_s12), GET_H_CR (FLD (f_op_B)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (FLD (f_s12), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (FLD (f_s12), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RSUB_CCU6__RA_) : /* rsub$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (FLD (f_u6), GET_H_CR (FLD (f_op_B)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (FLD (f_u6), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (FLD (f_u6), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RSUB_L_U6__RA_) : /* rsub$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (FLD (f_u6), GET_H_CR (FLD (f_op_B)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (FLD (f_u6), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (FLD (f_u6), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RSUB_L_R_R__RA__RC) : /* rsub$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RSUB_CC__RA__RC) : /* rsub$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BSET_L_S12__RA_) : /* bset$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (FLD (f_s12), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BSET_CCU6__RA_) : /* bset$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BSET_L_U6__RA_) : /* bset$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BSET_L_R_R__RA__RC) : /* bset$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BSET_CC__RA__RC) : /* bset$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BSET_S_SSB) : /* bset$_S $R_b,$R_b,$u5 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ {
+ SI opval = ORSI (tmp_B, SLLSI (1, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BCLR_L_S12__RA_) : /* bclr$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (SLLSI (1, ANDSI (FLD (f_s12), 31))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BCLR_CCU6__RA_) : /* bclr$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (SLLSI (1, ANDSI (FLD (f_u6), 31))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BCLR_L_U6__RA_) : /* bclr$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (SLLSI (1, ANDSI (FLD (f_u6), 31))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BCLR_L_R_R__RA__RC) : /* bclr$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BCLR_CC__RA__RC) : /* bclr$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BCLR_S_SSB) : /* bclr$_S $R_b,$R_b,$u5 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ {
+ SI opval = ANDSI (tmp_B, INVSI (SLLSI (1, ANDSI (tmp_C, 31))));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BTST_L_S12_) : /* btst$_L$F1 $RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_s12);
+ tmp_result = ANDSI (tmp_B, SLLSI (1, ANDSI (tmp_C, 31)));
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BTST_CCU6_) : /* btst$Qcondi$F1 $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+ tmp_result = ANDSI (tmp_B, SLLSI (1, ANDSI (tmp_C, 31)));
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BTST_L_U6_) : /* btst$_L$F1 $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+ tmp_result = ANDSI (tmp_B, SLLSI (1, ANDSI (tmp_C, 31)));
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BTST_L_R_R__RC) : /* btst$_L$F1 $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+ tmp_result = ANDSI (tmp_B, SLLSI (1, ANDSI (tmp_C, 31)));
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BTST_CC__RC) : /* btst$Qcondi$F1 $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+ tmp_result = ANDSI (tmp_B, SLLSI (1, ANDSI (tmp_C, 31)));
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BTST_S_SSB) : /* btst$_S $R_b,$u5 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ tmp_result = ANDSI (tmp_B, SLLSI (1, ANDSI (tmp_C, 31)));
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BXOR_L_S12__RA_) : /* bxor$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (FLD (f_s12), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BXOR_CCU6__RA_) : /* bxor$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BXOR_L_U6__RA_) : /* bxor$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BXOR_L_R_R__RA__RC) : /* bxor$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BXOR_CC__RA__RC) : /* bxor$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BMSK_L_S12__RA_) : /* bmsk$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), SUBSI (SLLSI (SLLSI (1, ANDSI (FLD (f_s12), 31)), 1), 1));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BMSK_CCU6__RA_) : /* bmsk$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), SUBSI (SLLSI (SLLSI (1, ANDSI (FLD (f_u6), 31)), 1), 1));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BMSK_L_U6__RA_) : /* bmsk$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), SUBSI (SLLSI (SLLSI (1, ANDSI (FLD (f_u6), 31)), 1), 1));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BMSK_L_R_R__RA__RC) : /* bmsk$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), SUBSI (SLLSI (SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31)), 1), 1));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BMSK_CC__RA__RC) : /* bmsk$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), SUBSI (SLLSI (SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31)), 1), 1));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BMSK_S_SSB) : /* bmsk$_S $R_b,$R_b,$u5 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ {
+ SI opval = ANDSI (tmp_B, SUBSI (SLLSI (SLLSI (1, ANDSI (tmp_C, 31)), 1), 1));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD1_L_S12__RA_) : /* add1$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s12), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_s12), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD1_CCU6__RA_) : /* add1$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD1_L_U6__RA_) : /* add1$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD1_L_R_R__RA__RC) : /* add1$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD1_CC__RA__RC) : /* add1$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_ADD1_S_GO) : /* add1$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ADDSI (tmp_B, SLLSI (tmp_C, 1));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD2_L_S12__RA_) : /* add2$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s12), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_s12), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD2_CCU6__RA_) : /* add2$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD2_L_U6__RA_) : /* add2$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD2_L_R_R__RA__RC) : /* add2$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD2_CC__RA__RC) : /* add2$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_ADD2_S_GO) : /* add2$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ADDSI (tmp_B, SLLSI (tmp_C, 2));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD3_L_S12__RA_) : /* add3$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s12), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_s12), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD3_CCU6__RA_) : /* add3$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD3_L_U6__RA_) : /* add3$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD3_L_R_R__RA__RC) : /* add3$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD3_CC__RA__RC) : /* add3$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_ADD3_S_GO) : /* add3$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ADDSI (tmp_B, SLLSI (tmp_C, 3));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB1_L_S12__RA_) : /* sub1$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s12), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_s12), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB1_CCU6__RA_) : /* sub1$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB1_L_U6__RA_) : /* sub1$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB1_L_R_R__RA__RC) : /* sub1$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB1_CC__RA__RC) : /* sub1$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB2_L_S12__RA_) : /* sub2$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s12), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_s12), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB2_CCU6__RA_) : /* sub2$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB2_L_U6__RA_) : /* sub2$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB2_L_R_R__RA__RC) : /* sub2$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB2_CC__RA__RC) : /* sub2$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB3_L_S12__RA_) : /* sub3$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s12), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_s12), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB3_CCU6__RA_) : /* sub3$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB3_L_U6__RA_) : /* sub3$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB3_L_R_R__RA__RC) : /* sub3$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB3_CC__RA__RC) : /* sub3$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPY_L_S12__RA_) : /* mpy$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (EXTSIDI (tmp_result), MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_s12))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPY_CCU6__RA_) : /* mpy$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (EXTSIDI (tmp_result), MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPY_L_U6__RA_) : /* mpy$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (EXTSIDI (tmp_result), MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPY_L_R_R__RA__RC) : /* mpy$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (EXTSIDI (tmp_result), MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C)))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPY_CC__RA__RC) : /* mpy$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (EXTSIDI (tmp_result), MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C)))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYH_L_S12__RA_) : /* mpyh$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_s12))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYH_CCU6__RA_) : /* mpyh$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYH_L_U6__RA_) : /* mpyh$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYH_L_R_R__RA__RC) : /* mpyh$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C)))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYH_CC__RA__RC) : /* mpyh$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C)))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYHU_L_S12__RA_) : /* mpyhu$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_s12))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYHU_CCU6__RA_) : /* mpyhu$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_u6))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYHU_L_U6__RA_) : /* mpyhu$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_u6))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYHU_L_R_R__RA__RC) : /* mpyhu$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (GET_H_CR (FLD (f_op_C)))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYHU_CC__RA__RC) : /* mpyhu$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (GET_H_CR (FLD (f_op_C)))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYU_L_S12__RA_) : /* mpyu$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (ZEXTSIDI (tmp_result), MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_s12))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYU_CCU6__RA_) : /* mpyu$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (ZEXTSIDI (tmp_result), MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_u6))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYU_L_U6__RA_) : /* mpyu$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (ZEXTSIDI (tmp_result), MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_u6))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYU_L_R_R__RA__RC) : /* mpyu$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (ZEXTSIDI (tmp_result), MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (GET_H_CR (FLD (f_op_C)))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYU_CC__RA__RC) : /* mpyu$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (ZEXTSIDI (tmp_result), MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (GET_H_CR (FLD (f_op_C)))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_L_R_R___RC_NOILINK_) : /* j$_L$F0 [$RC_noilink] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_CC___RC_NOILINK_) : /* j$Qcondi$F0 [$RC_noilink] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_L_R_R___RC_ILINK_) : /* j$_L$F1F [$RC_ilink] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_ILINKX (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_ILINKX (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_ILINKX (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_CC___RC_ILINK_) : /* j$Qcondi$F1F [$RC_ilink] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_ILINKX (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_ILINKX (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_ILINKX (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_L_S12_) : /* j$_L$F0 $s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_CCU6_) : /* j$Qcondi$F0 $U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_L_U6_) : /* j$_L$F0 $U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_S) : /* j$_S [$R_b] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_S__S) : /* j$_S [$R31] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_SEQ__S) : /* jeq$_S [$R31] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if (NEBI (CPU (h_zbit), 0)) {
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if (NEBI (CPU (h_zbit), 0)) {
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if (NEBI (CPU (h_zbit), 0)) {
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_SNE__S) : /* jne$_S [$R31] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if (EQBI (CPU (h_zbit), 0)) {
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if (EQBI (CPU (h_zbit), 0)) {
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if (EQBI (CPU (h_zbit), 0)) {
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_L_S12_D_) : /* j$_L$F0.d $s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_CCU6_D_) : /* j$Qcondi$F0.d $U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_L_U6_D_) : /* j$_L$F0.d $U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_L_R_R_D___RC_) : /* j$_L$F0.d [$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_CC_D___RC_) : /* j$Qcondi$F0.d [$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_S_D) : /* j$_S.d [$R_b] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_S__S_D) : /* j$_S.d [$R31] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JL_L_S12_) : /* jl$_L$F0 $s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JL_CCU6_) : /* jl$Qcondi$F0 $U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JL_L_U6_) : /* jl$_L$F0 $U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JL_S) : /* jl$_S [$R_b] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 2);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 2);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 2);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JL_L_R_R___RC_NOILINK_) : /* jl$_L$F0 [$RC_noilink] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, ((EQSI (FLD (f_op_C), 62)) ? (8) : (4)));
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, ((EQSI (FLD (f_op_C), 62)) ? (8) : (4)));
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, ((EQSI (FLD (f_op_C), 62)) ? (8) : (4)));
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JL_CC___RC_NOILINK_) : /* jl$Qcondi$F0 [$RC_noilink] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, ((EQSI (FLD (f_op_C), 62)) ? (8) : (4)));
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, ((EQSI (FLD (f_op_C), 62)) ? (8) : (4)));
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, ((EQSI (FLD (f_op_C), 62)) ? (8) : (4)));
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JL_L_S12_D_) : /* jl$_L$F0.d $s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JL_CCU6_D_) : /* jl$Qcondi$F0.d $U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JL_L_U6_D_) : /* jl$_L$F0.d $U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JL_L_R_R_D___RC_) : /* jl$_L$F0.d [$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JL_CC_D___RC_) : /* jl$Qcondi$F0.d [$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JL_S_D) : /* jl$_S.d [$R_b] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 2));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 2));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 2));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LP_L_S12_) : /* lp$_L$F0 $s12x2 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_lp_L_s12_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ SI opval = ADDSI (ANDSI (pc, -4), FLD (f_s12x2));
+ SET_H_AUXR (((UINT) 3), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_AUXR (((UINT) 2), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ SI opval = ADDSI (ANDSI (pc, -4), FLD (f_s12x2));
+ SET_H_AUXR (((UINT) 3), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_AUXR (((UINT) 2), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ SI opval = ADDSI (ANDSI (pc, -4), FLD (f_s12x2));
+ SET_H_AUXR (((UINT) 3), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_AUXR (((UINT) 2), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LPCC_CCU6) : /* lp$Qcondi$F0 $U6x2 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_lpcc_ccu6.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ SI opval = ADDSI (ANDSI (pc, -4), FLD (f_u6x2));
+ SET_H_AUXR (((UINT) 3), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_AUXR (((UINT) 2), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ SI opval = ADDSI (ANDSI (pc, -4), FLD (f_u6x2));
+ SET_H_AUXR (((UINT) 3), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_AUXR (((UINT) 2), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ SI opval = ADDSI (ANDSI (pc, -4), FLD (f_u6x2));
+ SET_H_AUXR (((UINT) 3), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_AUXR (((UINT) 2), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+}
+}
+} else {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = ADDSI (ANDSI (pc, -4), FLD (f_u6x2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = ADDSI (ANDSI (pc, -4), FLD (f_u6x2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = ADDSI (ANDSI (pc, -4), FLD (f_u6x2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FLAG_L_S12_) : /* flag$_L$F0 $s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (ANDSI (FLD (f_s12), 1)) {
+sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc, sim_exited, a5f_h_cr_get (current_cpu, 0));}
+ {
+ SI opval = FLD (f_s12);
+ SET_H_STATUS32 (((UINT) 0), opval);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FLAG_CCU6_) : /* flag$Qcondi$F0 $U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+if (ANDSI (FLD (f_u6), 1)) {
+sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc, sim_exited, a5f_h_cr_get (current_cpu, 0));}
+ {
+ SI opval = FLD (f_u6);
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FLAG_L_U6_) : /* flag$_L$F0 $U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (ANDSI (FLD (f_u6), 1)) {
+sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc, sim_exited, a5f_h_cr_get (current_cpu, 0));}
+ {
+ SI opval = FLD (f_u6);
+ SET_H_STATUS32 (((UINT) 0), opval);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FLAG_L_R_R__RC) : /* flag$_L$F0 $RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (ANDSI (GET_H_CR (FLD (f_op_C)), 1)) {
+sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc, sim_exited, a5f_h_cr_get (current_cpu, 0));}
+ {
+ SI opval = GET_H_CR (FLD (f_op_C));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FLAG_CC__RC) : /* flag$Qcondi$F0 $RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+if (ANDSI (GET_H_CR (FLD (f_op_C)), 1)) {
+sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc, sim_exited, a5f_h_cr_get (current_cpu, 0));}
+ {
+ SI opval = GET_H_CR (FLD (f_op_C));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LR_L_R_R___RC_) : /* lr$_L$F0 $RB,[$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ {
+ SI opval = GET_H_AUXR (GET_H_CR (FLD (f_op_C)));
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LR_L_S12_) : /* lr$_L$F0 $RB,[$s12] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ {
+ SI opval = GET_H_AUXR (FLD (f_s12));
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LR_L_U6_) : /* lr$_L$F0 $RB,[$U6] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ {
+ SI opval = GET_H_AUXR (FLD (f_u6));
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SR_L_R_R___RC_) : /* sr$_L$F0 $RB,[$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ {
+ SI opval = GET_H_CR (FLD (f_op_B));
+ SET_H_AUXR (GET_H_CR (FLD (f_op_C)), opval);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SR_L_S12_) : /* sr$_L$F0 $RB,[$s12] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ {
+ SI opval = GET_H_CR (FLD (f_op_B));
+ SET_H_AUXR (FLD (f_s12), opval);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SR_L_U6_) : /* sr$_L$F0 $RB,[$U6] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ {
+ SI opval = GET_H_CR (FLD (f_op_B));
+ SET_H_AUXR (FLD (f_u6), opval);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASL_L_R_R__RC) : /* asl$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASL_L_U6_) : /* asl$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (FLD (f_u6), FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (FLD (f_u6), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (FLD (f_u6), FLD (f_u6), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_ASL_S_GO) : /* asl$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ADDSI (tmp_C, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASR_L_R_R__RC) : /* asr$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SRASI (GET_H_CR (FLD (f_op_C)), 1);
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (GET_H_CR (FLD (f_op_C)), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASR_L_U6_) : /* asr$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SRASI (FLD (f_u6), 1);
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (FLD (f_u6), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_ASR_S_GO) : /* asr$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = SRASI (tmp_C, 1);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSR_L_R_R__RC) : /* lsr$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SRLSI (GET_H_CR (FLD (f_op_C)), 1);
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (GET_H_CR (FLD (f_op_C)), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSR_L_U6_) : /* lsr$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SRLSI (FLD (f_u6), 1);
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (FLD (f_u6), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_LSR_S_GO) : /* lsr$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = SRLSI (tmp_C, 1);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ROR_L_R_R__RC) : /* ror$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (SRLSI (GET_H_CR (FLD (f_op_C)), 1), SLLSI (GET_H_CR (FLD (f_op_C)), 31));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (GET_H_CR (FLD (f_op_C)), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ROR_L_U6_) : /* ror$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (SRLSI (FLD (f_u6), 1), SLLSI (FLD (f_u6), 31));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (FLD (f_u6), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RRC_L_R_R__RC) : /* rrc$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (SRLSI (GET_H_CR (FLD (f_op_C)), 1), SLLSI (ZEXTBISI (CPU (h_cbit)), 31));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (GET_H_CR (FLD (f_op_C)), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RRC_L_U6_) : /* rrc$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (SRLSI (FLD (f_u6), 1), SLLSI (ZEXTBISI (CPU (h_cbit)), 31));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (FLD (f_u6), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SEXB_L_R_R__RC) : /* sexb$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = EXTQISI ((GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SEXB_L_U6_) : /* sexb$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = EXTQISI ((FLD (f_u6)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_SEXB_S_GO) : /* sexb$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = EXTQISI ((tmp_C));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SEXW_L_R_R__RC) : /* sexw$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = EXTHISI ((GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SEXW_L_U6_) : /* sexw$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = EXTHISI ((FLD (f_u6)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_SEXW_S_GO) : /* sexw$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = EXTHISI ((tmp_C));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_EXTB_L_R_R__RC) : /* extb$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ZEXTQISI ((GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_EXTB_L_U6_) : /* extb$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ZEXTQISI ((FLD (f_u6)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_EXTB_S_GO) : /* extb$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ZEXTQISI ((tmp_C));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_EXTW_L_R_R__RC) : /* extw$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ZEXTHISI ((GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_EXTW_L_U6_) : /* extw$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ZEXTHISI ((FLD (f_u6)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_EXTW_S_GO) : /* extw$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ZEXTHISI ((tmp_C));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ABS_L_R_R__RC) : /* abs$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ABSSI (({ SI tmp_res;
+ tmp_res = GET_H_CR (FLD (f_op_C));
+; tmp_res; }));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI ((GET_H_CR (FLD (f_op_C))), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (GET_H_CR (FLD (f_op_C)), 0x80000000);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_vbit);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ABS_L_U6_) : /* abs$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ABSSI (({ SI tmp_res;
+ tmp_res = FLD (f_u6);
+; tmp_res; }));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI ((FLD (f_u6)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (FLD (f_u6), 0x80000000);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_vbit);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_ABS_S_GO) : /* abs$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ABSSI (({ SI tmp_res;
+ tmp_res = tmp_C;
+; tmp_res; }));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NOT_L_R_R__RC) : /* not$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = INVSI (GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NOT_L_U6_) : /* not$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = INVSI (FLD (f_u6));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_NOT_S_GO) : /* not$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = INVSI (tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RLC_L_R_R__RC) : /* rlc$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (SLLSI (GET_H_CR (FLD (f_op_C)), 1), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SRLSI (GET_H_CR (FLD (f_op_C)), 31);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RLC_L_U6_) : /* rlc$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (SLLSI (FLD (f_u6), 1), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SRLSI (FLD (f_u6), 31);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_NEG_S_GO) : /* neg$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = NEGSI (tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SWI) : /* swi */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+; /*clobber*/
+ {
+ USI opval = arc_trap (current_cpu, pc, 4, 0);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else if (0) {
+{
+; /*clobber*/
+ {
+ USI opval = arc_trap (current_cpu, pc, 4, 0);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+; /*clobber*/
+ {
+ USI opval = arc_trap (current_cpu, pc, 4, 0);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_TRAP_S) : /* trap$_S $trapnum */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_trap_s.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = arc_trap (current_cpu, pc, 2, FLD (f_trapnum));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+; /*clobber*/
+}
+}
+}
+ else if (0) {
+{
+ {
+ USI opval = arc_trap (current_cpu, pc, 2, FLD (f_trapnum));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+; /*clobber*/
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ {
+ USI opval = arc_trap (current_cpu, pc, 2, FLD (f_trapnum));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+; /*clobber*/
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BRK) : /* brk */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+arc_breakpoint (current_cpu, pc, 4);
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BRK_S) : /* brk_s */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+arc_breakpoint (current_cpu, pc, 2);
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASL_L_S12__RA_) : /* asl$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_s12), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_s12), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (32, ANDSI (FLD (f_s12), 31))), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASL_CCU6__RA_) : /* asl$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (32, ANDSI (FLD (f_u6), 31))), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASL_L_U6__RA_) : /* asl$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (32, ANDSI (FLD (f_u6), 31))), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASL_L_R_R__RA__RC) : /* asl$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (32, ANDSI (GET_H_CR (FLD (f_op_C)), 31))), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASL_CC__RA__RC) : /* asl$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (32, ANDSI (GET_H_CR (FLD (f_op_C)), 31))), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASL_S_CBU3) : /* asl$_S $R_c,$R_b,$u3 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u3);
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASL_S_SSB) : /* asl$_S $R_b,$R_b,$u5 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_ASLM_S_GO) : /* asl$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSR_L_S12__RA_) : /* lsr$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_s12), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_s12), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_s12), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSR_CCU6__RA_) : /* lsr$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_u6), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSR_L_U6__RA_) : /* lsr$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_u6), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSR_L_R_R__RA__RC) : /* lsr$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSR_CC__RA__RC) : /* lsr$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSR_S_SSB) : /* lsr$_S $R_b,$R_b,$u5 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_LSRM_S_GO) : /* lsr$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASR_L_S12__RA_) : /* asr$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_s12), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_s12), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_s12), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASR_CCU6__RA_) : /* asr$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_u6), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASR_L_U6__RA_) : /* asr$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_u6), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASR_L_R_R__RA__RC) : /* asr$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASR_CC__RA__RC) : /* asr$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASR_S_CBU3) : /* asr$_S $R_c,$R_b,$u3 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u3);
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASR_S_SSB) : /* asr$_S $R_b,$R_b,$u5 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_ASRM_S_GO) : /* asr$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ROR_L_S12__RA_) : /* ror$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (RORSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_s12), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_s12), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_s12), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ROR_CCU6__RA_) : /* ror$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (RORSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_u6), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ROR_L_U6__RA_) : /* ror$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (RORSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_u6), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ROR_L_R_R__RA__RC) : /* ror$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (RORSI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ROR_CC__RA__RC) : /* ror$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (RORSI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MUL64_L_S12_) : /* mul64$_L$F1 $RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_s12)));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MUL64_CCU6_) : /* mul64$Qcondi$F1 $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6)));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MUL64_L_U6_) : /* mul64$_L$F1 $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6)));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MUL64_L_R_R__RC) : /* mul64$_L$F1 $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MUL64_CC__RC) : /* mul64$Qcondi$F1 $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MUL64_S_GO) : /* mul64$_S $R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (EXTSIDI (GET_H_CR16 (FLD (f_op__b))), EXTSIDI (GET_H_CR16 (FLD (f_op__c))));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULU64_L_S12_) : /* mulu64$_L$F1 $RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_s12)));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULU64_CCU6_) : /* mulu64$Qcondi$F1 $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_u6)));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULU64_L_U6_) : /* mulu64$_L$F1 $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_u6)));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULU64_L_R_R__RC) : /* mulu64$_L$F1 $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (GET_H_CR (FLD (f_op_C))));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULU64_CC__RC) : /* mulu64$Qcondi$F1 $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (GET_H_CR (FLD (f_op_C))));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDS_L_S12__RA_) : /* adds$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = ADDDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_s12)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDS_CCU6__RA_) : /* adds$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = ADDDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDS_L_U6__RA_) : /* adds$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = ADDDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDS_L_R_R__RA__RC) : /* adds$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = ADDDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDS_CC__RA__RC) : /* adds$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = ADDDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBS_L_S12__RA_) : /* subs$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_s12)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBS_CCU6__RA_) : /* subs$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBS_L_U6__RA_) : /* subs$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBS_L_R_R__RA__RC) : /* subs$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBS_CC__RA__RC) : /* subs$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_DIVAW_L_S12__RA_) : /* divaw$_L$F0 $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ USI tmp_tmp;
+ tmp_tmp = SLLSI (GET_H_CR (FLD (f_op_B)), 1);
+; ((EQSI (ANDSI (SUBSI (tmp_tmp, FLD (f_s12)), 0x80000000), 0)) ? (ADDSI (SUBSI (tmp_tmp, FLD (f_s12)), 1)) : (tmp_tmp)); }));
+if (FLD (f_F)) {
+((void) 0); /*nop*/
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_DIVAW_CCU6__RA_) : /* divaw$Qcondi$F0 $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ USI tmp_tmp;
+ tmp_tmp = SLLSI (GET_H_CR (FLD (f_op_B)), 1);
+; ((EQSI (ANDSI (SUBSI (tmp_tmp, FLD (f_u6)), 0x80000000), 0)) ? (ADDSI (SUBSI (tmp_tmp, FLD (f_u6)), 1)) : (tmp_tmp)); }));
+if (FLD (f_F)) {
+((void) 0); /*nop*/
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_DIVAW_L_U6__RA_) : /* divaw$_L$F0 $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ USI tmp_tmp;
+ tmp_tmp = SLLSI (GET_H_CR (FLD (f_op_B)), 1);
+; ((EQSI (ANDSI (SUBSI (tmp_tmp, FLD (f_u6)), 0x80000000), 0)) ? (ADDSI (SUBSI (tmp_tmp, FLD (f_u6)), 1)) : (tmp_tmp)); }));
+if (FLD (f_F)) {
+((void) 0); /*nop*/
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_DIVAW_L_R_R__RA__RC) : /* divaw$_L$F0 $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ USI tmp_tmp;
+ tmp_tmp = SLLSI (GET_H_CR (FLD (f_op_B)), 1);
+; ((EQSI (ANDSI (SUBSI (tmp_tmp, GET_H_CR (FLD (f_op_C))), 0x80000000), 0)) ? (ADDSI (SUBSI (tmp_tmp, GET_H_CR (FLD (f_op_C))), 1)) : (tmp_tmp)); }));
+if (FLD (f_F)) {
+((void) 0); /*nop*/
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_DIVAW_CC__RA__RC) : /* divaw$Qcondi$F0 $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ USI tmp_tmp;
+ tmp_tmp = SLLSI (GET_H_CR (FLD (f_op_B)), 1);
+; ((EQSI (ANDSI (SUBSI (tmp_tmp, GET_H_CR (FLD (f_op_C))), 0x80000000), 0)) ? (ADDSI (SUBSI (tmp_tmp, GET_H_CR (FLD (f_op_C))), 1)) : (tmp_tmp)); }));
+if (FLD (f_F)) {
+((void) 0); /*nop*/
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASLS_L_S12__RA_) : /* asls$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((FLD (f_s12)), 31)) ? (SLLDI (tmp_b, 31)) : (LTSI ((FLD (f_s12)), -31)) ? (SRADI (tmp_b, 31)) : (GESI ((FLD (f_s12)), 0)) ? (SLLDI (tmp_b, (FLD (f_s12)))) : (SRASI (GET_H_CR (FLD (f_op_B)), NEGSI ((FLD (f_s12)))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASLS_CCU6__RA_) : /* asls$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((FLD (f_u6)), 31)) ? (SLLDI (tmp_b, 31)) : (LTSI ((FLD (f_u6)), -31)) ? (SRADI (tmp_b, 31)) : (GESI ((FLD (f_u6)), 0)) ? (SLLDI (tmp_b, (FLD (f_u6)))) : (SRASI (GET_H_CR (FLD (f_op_B)), NEGSI ((FLD (f_u6)))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASLS_L_U6__RA_) : /* asls$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((FLD (f_u6)), 31)) ? (SLLDI (tmp_b, 31)) : (LTSI ((FLD (f_u6)), -31)) ? (SRADI (tmp_b, 31)) : (GESI ((FLD (f_u6)), 0)) ? (SLLDI (tmp_b, (FLD (f_u6)))) : (SRASI (GET_H_CR (FLD (f_op_B)), NEGSI ((FLD (f_u6)))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASLS_L_R_R__RA__RC) : /* asls$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((GET_H_CR (FLD (f_op_C))), 31)) ? (SLLDI (tmp_b, 31)) : (LTSI ((GET_H_CR (FLD (f_op_C))), -31)) ? (SRADI (tmp_b, 31)) : (GESI ((GET_H_CR (FLD (f_op_C))), 0)) ? (SLLDI (tmp_b, (GET_H_CR (FLD (f_op_C))))) : (SRASI (GET_H_CR (FLD (f_op_B)), NEGSI ((GET_H_CR (FLD (f_op_C))))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASLS_CC__RA__RC) : /* asls$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((GET_H_CR (FLD (f_op_C))), 31)) ? (SLLDI (tmp_b, 31)) : (LTSI ((GET_H_CR (FLD (f_op_C))), -31)) ? (SRADI (tmp_b, 31)) : (GESI ((GET_H_CR (FLD (f_op_C))), 0)) ? (SLLDI (tmp_b, (GET_H_CR (FLD (f_op_C))))) : (SRASI (GET_H_CR (FLD (f_op_B)), NEGSI ((GET_H_CR (FLD (f_op_C))))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASRS_L_S12__RA_) : /* asrs$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((FLD (f_s12)), 31)) ? (SRADI (tmp_b, 31)) : (LTSI ((FLD (f_s12)), -31)) ? (SLLDI (tmp_b, 31)) : (GESI ((FLD (f_s12)), 0)) ? (SRADI (tmp_b, (FLD (f_s12)))) : (SLLSI (GET_H_CR (FLD (f_op_B)), NEGSI ((FLD (f_s12)))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASRS_CCU6__RA_) : /* asrs$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((FLD (f_u6)), 31)) ? (SRADI (tmp_b, 31)) : (LTSI ((FLD (f_u6)), -31)) ? (SLLDI (tmp_b, 31)) : (GESI ((FLD (f_u6)), 0)) ? (SRADI (tmp_b, (FLD (f_u6)))) : (SLLSI (GET_H_CR (FLD (f_op_B)), NEGSI ((FLD (f_u6)))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASRS_L_U6__RA_) : /* asrs$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((FLD (f_u6)), 31)) ? (SRADI (tmp_b, 31)) : (LTSI ((FLD (f_u6)), -31)) ? (SLLDI (tmp_b, 31)) : (GESI ((FLD (f_u6)), 0)) ? (SRADI (tmp_b, (FLD (f_u6)))) : (SLLSI (GET_H_CR (FLD (f_op_B)), NEGSI ((FLD (f_u6)))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASRS_L_R_R__RA__RC) : /* asrs$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((GET_H_CR (FLD (f_op_C))), 31)) ? (SRADI (tmp_b, 31)) : (LTSI ((GET_H_CR (FLD (f_op_C))), -31)) ? (SLLDI (tmp_b, 31)) : (GESI ((GET_H_CR (FLD (f_op_C))), 0)) ? (SRADI (tmp_b, (GET_H_CR (FLD (f_op_C))))) : (SLLSI (GET_H_CR (FLD (f_op_B)), NEGSI ((GET_H_CR (FLD (f_op_C))))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASRS_CC__RA__RC) : /* asrs$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((GET_H_CR (FLD (f_op_C))), 31)) ? (SRADI (tmp_b, 31)) : (LTSI ((GET_H_CR (FLD (f_op_C))), -31)) ? (SLLDI (tmp_b, 31)) : (GESI ((GET_H_CR (FLD (f_op_C))), 0)) ? (SRADI (tmp_b, (GET_H_CR (FLD (f_op_C))))) : (SLLSI (GET_H_CR (FLD (f_op_B)), NEGSI ((GET_H_CR (FLD (f_op_C))))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDSDW_L_S12__RA_) : /* addsdw$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((FLD (f_s12)), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((FLD (f_s12)), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDSDW_CCU6__RA_) : /* addsdw$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((FLD (f_u6)), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((FLD (f_u6)), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDSDW_L_U6__RA_) : /* addsdw$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((FLD (f_u6)), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((FLD (f_u6)), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDSDW_L_R_R__RA__RC) : /* addsdw$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDSDW_CC__RA__RC) : /* addsdw$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBSDW_L_S12__RA_) : /* subsdw$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((FLD (f_s12)), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((FLD (f_s12)), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBSDW_CCU6__RA_) : /* subsdw$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((FLD (f_u6)), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((FLD (f_u6)), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBSDW_L_U6__RA_) : /* subsdw$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((FLD (f_u6)), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((FLD (f_u6)), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBSDW_L_R_R__RA__RC) : /* subsdw$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBSDW_CC__RA__RC) : /* subsdw$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SWAP_L_R_R__RC) : /* swap$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (RORSI (GET_H_CR (FLD (f_op_C)), 16));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SWAP_L_U6_) : /* swap$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (RORSI (FLD (f_u6), 16));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NORM_L_R_R__RC) : /* norm$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_val;
+ SI tmp_bits;
+ tmp_val = ((GESI ((GET_H_CR (FLD (f_op_C))), 0)) ? ((GET_H_CR (FLD (f_op_C)))) : (INVSI ((GET_H_CR (FLD (f_op_C))))));
+; tmp_bits = 31;
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 4), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 4));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 4));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 3), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 3));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 3));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 2), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 2));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 2));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 1), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 1));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 1));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 0), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 0));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 0));
+}
+; tmp_bits; }));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NORM_L_U6_) : /* norm$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_val;
+ SI tmp_bits;
+ tmp_val = ((GESI ((FLD (f_u6)), 0)) ? ((FLD (f_u6))) : (INVSI ((FLD (f_u6)))));
+; tmp_bits = 31;
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 4), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 4));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 4));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 3), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 3));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 3));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 2), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 2));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 2));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 1), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 1));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 1));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 0), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 0));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 0));
+}
+; tmp_bits; }));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (FLD (f_u6), 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (FLD (f_u6), 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RND16_L_R_R__RC) : /* rnd16$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (({ DI tmp_tmp;
+ tmp_tmp = ADDDI (EXTSIDI (32768), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }), 16));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RND16_L_U6_) : /* rnd16$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (({ DI tmp_tmp;
+ tmp_tmp = ADDDI (EXTSIDI (32768), EXTSIDI (FLD (f_u6)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }), 16));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ABSSW_L_R_R__RC) : /* abssw$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_tmp;
+ tmp_tmp = ABSSI (EXTHISI ((GET_H_CR (FLD (f_op_C)))));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ABSSW_L_U6_) : /* abssw$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_tmp;
+ tmp_tmp = ABSSI (EXTHISI ((FLD (f_u6))));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ABSS_L_R_R__RC) : /* abss$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (((GESI ((GET_H_CR (FLD (f_op_C))), 0)) ? (GET_H_CR (FLD (f_op_C))) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (0), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }))));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ABSS_L_U6_) : /* abss$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (((GESI ((FLD (f_u6)), 0)) ? (FLD (f_u6)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (0), EXTSIDI (FLD (f_u6)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }))));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NEGSW_L_R_R__RC) : /* negsw$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_tmp;
+ tmp_tmp = EXTHISI ((GET_H_CR (FLD (f_op_C))));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NEGSW_L_U6_) : /* negsw$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_tmp;
+ tmp_tmp = EXTHISI ((FLD (f_u6)));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NEGS_L_R_R__RC) : /* negs$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (0), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NEGS_L_U6_) : /* negs$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (0), EXTSIDI (FLD (f_u6)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NORMW_L_R_R__RC) : /* normw$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_val;
+ SI tmp_bits;
+ tmp_val = ((GESI (ORSI (SLLSI (GET_H_CR (FLD (f_op_C)), 16), ANDSI (GET_H_CR (FLD (f_op_C)), 65535)), 0)) ? (ORSI (SLLSI (GET_H_CR (FLD (f_op_C)), 16), ANDSI (GET_H_CR (FLD (f_op_C)), 65535))) : (INVSI (ORSI (SLLSI (GET_H_CR (FLD (f_op_C)), 16), ANDSI (GET_H_CR (FLD (f_op_C)), 65535)))));
+; tmp_bits = 31;
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 4), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 4));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 4));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 3), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 3));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 3));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 2), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 2));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 2));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 1), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 1));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 1));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 0), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 0));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 0));
+}
+; tmp_bits; }));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NORMW_L_U6_) : /* normw$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_val;
+ SI tmp_bits;
+ tmp_val = ((GESI (ORSI (SLLSI (FLD (f_u6), 16), ANDSI (FLD (f_u6), 65535)), 0)) ? (ORSI (SLLSI (FLD (f_u6), 16), ANDSI (FLD (f_u6), 65535))) : (INVSI (ORSI (SLLSI (FLD (f_u6), 16), ANDSI (FLD (f_u6), 65535)))));
+; tmp_bits = 31;
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 4), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 4));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 4));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 3), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 3));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 3));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 2), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 2));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 2));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 1), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 1));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 1));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 0), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 0));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 0));
+}
+; tmp_bits; }));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NOP_S) : /* nop_s */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_UNIMP_S) : /* unimp_s */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+cgen_rtx_error (current_cpu, "invalid insn");
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_POP_S_B) : /* pop$_S $R_b */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ SI opval = GETMEMSI (current_cpu, pc, GET_H_SP ());
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (GET_H_SP (), 4);
+ SET_H_SP (, opval);
+ TRACE_RESULT (current_cpu, abuf, "sp", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_POP_S_BLINK) : /* pop$_S $R31 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ SI opval = GETMEMSI (current_cpu, pc, GET_H_SP ());
+ SET_H_R31 (, opval);
+ TRACE_RESULT (current_cpu, abuf, "r31", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (GET_H_SP (), 4);
+ SET_H_SP (, opval);
+ TRACE_RESULT (current_cpu, abuf, "sp", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_PUSH_S_B) : /* push$_S $R_b */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ SI opval = ADDSI (GET_H_SP (), -4);
+ SET_H_SP (, opval);
+ TRACE_RESULT (current_cpu, abuf, "sp", 'x', opval);
+ }
+ {
+ SI opval = GET_H_CR16 (FLD (f_op__b));
+ SETMEMSI (current_cpu, pc, GET_H_SP (), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_PUSH_S_BLINK) : /* push$_S $R31 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ SI opval = ADDSI (GET_H_SP (), -4);
+ SET_H_SP (, opval);
+ TRACE_RESULT (current_cpu, abuf, "sp", 'x', opval);
+ }
+ {
+ SI opval = GET_H_R31 ();
+ SETMEMSI (current_cpu, pc, GET_H_SP (), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULLW_L_S12__RA_) : /* mullw$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_s12), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULLW_CCU6__RA_) : /* mullw$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_u6), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULLW_L_U6__RA_) : /* mullw$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_u6), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULLW_L_R_R__RA__RC) : /* mullw$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULLW_CC__RA__RC) : /* mullw$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACLW_L_S12__RA_) : /* maclw$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ SI tmp_SItmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_s12), 65535))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; {
+ BI opval = ANDBI (CPU (h_vbit), SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; if (NEBI (CPU (h_vbit), 0)) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; tmp_SItmp = ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp));
+; tmp_cur_s1bit = ORBI (tmp_cur_s1bit, CPU (h_vbit));
+; tmp_SItmp; });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACLW_CCU6__RA_) : /* maclw$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ SI tmp_SItmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_u6), 65535))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; {
+ BI opval = ANDBI (CPU (h_vbit), SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; if (NEBI (CPU (h_vbit), 0)) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; tmp_SItmp = ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp));
+; tmp_cur_s1bit = ORBI (tmp_cur_s1bit, CPU (h_vbit));
+; tmp_SItmp; });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACLW_L_U6__RA_) : /* maclw$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ SI tmp_SItmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_u6), 65535))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; {
+ BI opval = ANDBI (CPU (h_vbit), SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; if (NEBI (CPU (h_vbit), 0)) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; tmp_SItmp = ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp));
+; tmp_cur_s1bit = ORBI (tmp_cur_s1bit, CPU (h_vbit));
+; tmp_SItmp; });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACLW_L_R_R__RA__RC) : /* maclw$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ SI tmp_SItmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), 65535))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; {
+ BI opval = ANDBI (CPU (h_vbit), SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; if (NEBI (CPU (h_vbit), 0)) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; tmp_SItmp = ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp));
+; tmp_cur_s1bit = ORBI (tmp_cur_s1bit, CPU (h_vbit));
+; tmp_SItmp; });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACLW_CC__RA__RC) : /* maclw$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ SI tmp_SItmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), 65535))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; {
+ BI opval = ANDBI (CPU (h_vbit), SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; if (NEBI (CPU (h_vbit), 0)) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; tmp_SItmp = ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp));
+; tmp_cur_s1bit = ORBI (tmp_cur_s1bit, CPU (h_vbit));
+; tmp_SItmp; });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACHLW_L_S12__RA_) : /* machlw$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_s12), -65536))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = ANDBI (CPU (h_vbit), XORDI (tmp_old, tmp_tmp));
+; if (tmp_cur_s1bit) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACHLW_CCU6__RA_) : /* machlw$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_u6), -65536))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = ANDBI (CPU (h_vbit), XORDI (tmp_old, tmp_tmp));
+; if (tmp_cur_s1bit) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACHLW_L_U6__RA_) : /* machlw$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_u6), -65536))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = ANDBI (CPU (h_vbit), XORDI (tmp_old, tmp_tmp));
+; if (tmp_cur_s1bit) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACHLW_L_R_R__RA__RC) : /* machlw$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), -65536))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = ANDBI (CPU (h_vbit), XORDI (tmp_old, tmp_tmp));
+; if (tmp_cur_s1bit) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACHLW_CC__RA__RC) : /* machlw$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), -65536))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = ANDBI (CPU (h_vbit), XORDI (tmp_old, tmp_tmp));
+; if (tmp_cur_s1bit) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULULW_L_S12__RA_) : /* mululw$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (FLD (f_s12), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULULW_CCU6__RA_) : /* mululw$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (FLD (f_u6), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULULW_L_U6__RA_) : /* mululw$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (FLD (f_u6), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULULW_L_R_R__RA__RC) : /* mululw$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULULW_CC__RA__RC) : /* mululw$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACHULW_L_S12__RA_) : /* machulw$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (FLD (f_s12), -65536))));
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = (GTUDI (tmp_old, tmp_tmp)) ? (( tmp_tmp = -1, 1)) : (0);
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACHULW_CCU6__RA_) : /* machulw$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (FLD (f_u6), -65536))));
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = (GTUDI (tmp_old, tmp_tmp)) ? (( tmp_tmp = -1, 1)) : (0);
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACHULW_L_U6__RA_) : /* machulw$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (FLD (f_u6), -65536))));
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = (GTUDI (tmp_old, tmp_tmp)) ? (( tmp_tmp = -1, 1)) : (0);
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACHULW_L_R_R__RA__RC) : /* machulw$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), -65536))));
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = (GTUDI (tmp_old, tmp_tmp)) ? (( tmp_tmp = -1, 1)) : (0);
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACHULW_CC__RA__RC) : /* machulw$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), -65536))));
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = (GTUDI (tmp_old, tmp_tmp)) ? (( tmp_tmp = -1, 1)) : (0);
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CURRENT_LOOP_END) : /* */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDBI (EQSI (pc, GET_H_AUXR (((UINT) 3))), NOTBI (CPU (h_lbit)))) {
+{
+ {
+ SI opval = ADDSI (GET_H_CR (((UINT) 60)), -1);
+ SET_H_CR (((UINT) 60), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GET_H_CR (((UINT) 60))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (GET_H_AUXR (((UINT) 2)), 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = GET_H_AUXR (((UINT) 2));
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CURRENT_LOOP_END_AFTER_BRANCH) : /* */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (
+#ifdef SEM_IN_SWITCH
+pbb_br_type != SEM_BRANCH_UNTAKEN
+#else
+CPU_PBB_BR_NPC (current_cpu) != SEM_BRANCH_UNTAKEN
+#endif
+) {
+
+#ifdef SEM_IN_SWITCH
+npc = pbb_br_npc; br_type = pbb_br_type;
+#else
+npc = CPU_PBB_BR_NPC (current_cpu); br_type = CPU_PBB_BR_TYPE (current_cpu);
+#endif
+}
+ else if (ANDBI (EQSI (pc, GET_H_AUXR (((UINT) 3))), NOTBI (CPU (h_lbit)))) {
+{
+ {
+ SI opval = ADDSI (GET_H_CR (((UINT) 60)), -1);
+ SET_H_CR (((UINT) 60), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GET_H_CR (((UINT) 60))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (GET_H_AUXR (((UINT) 2)), 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = GET_H_AUXR (((UINT) 2));
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ARC600_CURRENT_LOOP_END_AFTER_BRANCH) : /* */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (
+#ifdef SEM_IN_SWITCH
+pbb_br_type != SEM_BRANCH_UNTAKEN
+#else
+CPU_PBB_BR_NPC (current_cpu) != SEM_BRANCH_UNTAKEN
+#endif
+) {
+{
+
+#ifdef SEM_IN_SWITCH
+npc = pbb_br_npc; br_type = pbb_br_type;
+#else
+npc = CPU_PBB_BR_NPC (current_cpu); br_type = CPU_PBB_BR_TYPE (current_cpu);
+#endif
+ {
+ SI opval = ADDSI (GET_H_CR (((UINT) 60)), -1);
+ SET_H_CR (((UINT) 60), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+ else if (ANDBI (EQSI (pc, GET_H_AUXR (((UINT) 3))), NOTBI (CPU (h_lbit)))) {
+{
+ {
+ SI opval = ADDSI (GET_H_CR (((UINT) 60)), -1);
+ SET_H_CR (((UINT) 60), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GET_H_CR (((UINT) 60))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (GET_H_AUXR (((UINT) 2)), 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = GET_H_AUXR (((UINT) 2));
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+
+ }
+ ENDSWITCH (sem) /* End of semantic switch. */
+
+ /* At this point `vpc' contains the next insn to execute. */
+}
+
+#undef DEFINE_SWITCH
+#endif /* DEFINE_SWITCH */
diff --git a/sim/arc/sem5.c b/sim/arc/sem5.c
new file mode 100644
index 0000000..a03fedf
--- /dev/null
+++ b/sim/arc/sem5.c
@@ -0,0 +1,33906 @@
+/* Simulator instruction semantics for a5f.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2007 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#define WANT_CPU a5f
+#define WANT_CPU_A5F
+
+#include "sim-main.h"
+#include "cgen-mem.h"
+#include "cgen-ops.h"
+
+#undef GET_ATTR
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
+#else
+#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr)
+#endif
+
+/* This is used so that we can compile two copies of the semantic code,
+ one with full feature support and one without that runs fast(er).
+ FAST_P, when desired, is defined on the command line, -DFAST_P=1. */
+#if FAST_P
+#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_semf_,fn)
+#undef TRACE_RESULT
+#define TRACE_RESULT(cpu, abuf, name, type, val)
+#else
+#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_sem_,fn)
+#endif
+
+/* x-invalid: --invalid-- */
+
+static SEM_PC
+SEM_FN_NAME (a5f,x_invalid) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+ /* Update the recorded pc in the cpu state struct.
+ Only necessary for WITH_SCACHE case, but to avoid the
+ conditional compilation .... */
+ SET_H_PC (pc);
+ /* Virtual insns have zero size. Overwrite vpc with address of next insn
+ using the default-insn-bitsize spec. When executing insns in parallel
+ we may want to queue the fault and continue execution. */
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+ vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* x-after: --after-- */
+
+static SEM_PC
+SEM_FN_NAME (a5f,x_after) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_A5F
+ a5f_pbb_after (current_cpu, sem_arg);
+#endif
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* x-before: --before-- */
+
+static SEM_PC
+SEM_FN_NAME (a5f,x_before) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_A5F
+ a5f_pbb_before (current_cpu, sem_arg);
+#endif
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* x-cti-chain: --cti-chain-- */
+
+static SEM_PC
+SEM_FN_NAME (a5f,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_A5F
+#ifdef DEFINE_SWITCH
+ vpc = a5f_pbb_cti_chain (current_cpu, sem_arg,
+ pbb_br_type, pbb_br_npc);
+ BREAK (sem);
+#else
+ /* FIXME: Allow provision of explicit ifmt spec in insn spec. */
+ vpc = a5f_pbb_cti_chain (current_cpu, sem_arg,
+ CPU_PBB_BR_TYPE (current_cpu),
+ CPU_PBB_BR_NPC (current_cpu));
+#endif
+#endif
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* x-chain: --chain-- */
+
+static SEM_PC
+SEM_FN_NAME (a5f,x_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_A5F
+ vpc = a5f_pbb_chain (current_cpu, sem_arg);
+#ifdef DEFINE_SWITCH
+ BREAK (sem);
+#endif
+#endif
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* x-begin: --begin-- */
+
+static SEM_PC
+SEM_FN_NAME (a5f,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_A5F
+#if defined DEFINE_SWITCH || defined FAST_P
+ /* In the switch case FAST_P is a constant, allowing several optimizations
+ in any called inline functions. */
+ vpc = a5f_pbb_begin (current_cpu, FAST_P);
+#else
+#if 0 /* cgen engine can't handle dynamic fast/full switching yet. */
+ vpc = a5f_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
+#else
+ vpc = a5f_pbb_begin (current_cpu, 0);
+#endif
+#endif
+#endif
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* b_s: b$i2cond $label10 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,b_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_b_s.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GET_H_I2COND (FLD (f_cond_i2))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = FLD (i_label10);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = FLD (i_label10);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = FLD (i_label10);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* bcc_s: b$i3cond$_S $label7 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,bcc_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bcc_s.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GET_H_I3COND (FLD (f_cond_i3))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = FLD (i_label7);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = FLD (i_label7);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = FLD (i_label7);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* brcc_s: br$RccS$_S $R_b,0,$label8 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,brcc_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_brcc_s.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if ((FLD (f_brscond) == 0) ? (EQSI (GET_H_CR16 (FLD (f_op__b)), 0)) : (FLD (f_brscond) == 1) ? (NESI (GET_H_CR16 (FLD (f_op__b)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = FLD (i_label8);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = FLD (i_label8);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = FLD (i_label8);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* bcc_l: b$Qcondb$_L $label21 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,bcc_l) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bcc_l.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+((void) 0); /*nop*/
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = FLD (i_label21);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = FLD (i_label21);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = FLD (i_label21);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* bcc_l.d: b$Qcondb$_L.d $label21 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,bcc_l_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bcc_l.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+((void) 0); /*nop*/
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (i_label21);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else if (1) {
+{
+ {
+ USI opval = FLD (i_label21);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ {
+ USI opval = FLD (i_label21);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* b_l: b$uncondb$_L $label25 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,b_l) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_b_l.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = FLD (i_label25);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = FLD (i_label25);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = FLD (i_label25);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* b_l.d: b$uncondb$_L.d $label25 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,b_l_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_b_l.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (i_label25);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else if (1) {
+{
+ {
+ USI opval = FLD (i_label25);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ {
+ USI opval = FLD (i_label25);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* brcc_RC: b$Rcc $RB,$RC,$label9 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,brcc_RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_brcc_RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* brcc_RC.d: b$Rcc.d $RB,$RC,$label9 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,brcc_RC_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_brcc_RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+{
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+{
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+{
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* brcc_U6: b$Rcc $RB,$U6,$label9 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,brcc_U6) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_brcc_U6.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* brcc_U6.d: b$Rcc.d $RB,$U6,$label9 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,brcc_U6_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_brcc_U6.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+{
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+{
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+{
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* bl_s: bl$uncondj$_S $label13a */
+
+static SEM_PC
+SEM_FN_NAME (a5f,bl_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bl_s.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ {
+ SI opval = ADDSI (pc, 2);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label13a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else if (0) {
+{
+ {
+ SI opval = ADDSI (pc, 2);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label13a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ {
+ SI opval = ADDSI (pc, 2);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label13a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* blcc: bl$Qcondj$_L $label21 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,blcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_blcc.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+((void) 0); /*nop*/
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label21a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else if (0) {
+{
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label21a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label21a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* blcc.d: bl$Qcondj$_L.d $label21 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,blcc_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_blcc.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+((void) 0); /*nop*/
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+{
+ {
+ USI opval = FLD (i_label21a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+{
+ {
+ USI opval = FLD (i_label21a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+{
+ {
+ USI opval = FLD (i_label21a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* bl: bl$uncondj$_L $label25a */
+
+static SEM_PC
+SEM_FN_NAME (a5f,bl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bl.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label25a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else if (0) {
+{
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label25a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label25a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* bl.d: bl$uncondj$_L.d $label25a */
+
+static SEM_PC
+SEM_FN_NAME (a5f,bl_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bl.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (i_label25a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (i_label25a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (i_label25a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* ld_abs: ld$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ld_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ld$_AW_abs: ld$_AW$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ld__AW_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ld.ab_abs: ld.ab$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ld_ab_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ld.as_abs: ld.as$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ld_as_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s9), 2));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ld_abc: ld$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ld_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ld$_AW_abc: ld$_AW$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ld__AW_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ld.ab_abc: ld.ab$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ld_ab_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ld.as_abc: ld.as$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ld_as_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 2));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ld_s_abc: ld$_S $R_a,[$R_b,$R_c] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ld_s_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), GET_H_CR16 (FLD (f_op__c)));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR16 (FLD (f_op__a), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ld_s_abu: ld$_S $R_c,[$R_b,$sc_u5_] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ld_s_abu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), FLD (f_u5x4));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ld_s_absp: ld$_S $R_b,[$SP,$u5x4] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ld_s_absp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_SP (), FLD (f_u5x4));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ld_s_gprel: ld$_S $R_b,[$GP,$sc_s9_] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ld_s_gprel) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_gprel.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_GP (), FLD (f_s9x4));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_R0 (, opval);
+ TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ld_s_pcrel: ld$_S $R_b,[$PCL,$u8x4] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ld_s_pcrel) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_pcrel.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (ANDSI (pc, -4), FLD (f_u8x4));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb_abs: ldb$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ldb_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb$_AW_abs: ldb$_AW$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ldb__AW_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb.ab_abs: ldb.ab$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ldb_ab_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb.as_abs: ldb.as$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ldb_as_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), (cgen_rtx_error (current_cpu, "invalid insn"), 0));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb_abc: ldb$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ldb_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb$_AW_abc: ldb$_AW$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ldb__AW_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb.ab_abc: ldb.ab$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ldb_ab_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb.as_abc: ldb.as$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ldb_as_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), (cgen_rtx_error (current_cpu, "invalid insn"), 0));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb_s_abc: ldb$_S $R_a,[$R_b,$R_c] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ldb_s_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), GET_H_CR16 (FLD (f_op__c)));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR16 (FLD (f_op__a), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb_s_abu: ldb$_S $R_c,[$R_b,$sc_u5b] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ldb_s_abu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), FLD (f_u5));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb_s_absp: ldb$_S $R_b,[$SP,$u5x4] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ldb_s_absp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_SP (), FLD (f_u5x4));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb_s_gprel: ldb$_S $R_b,[$GP,$sc_s9b] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ldb_s_gprel) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_gprel.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_GP (), FLD (f_s9x1));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_R0 (, opval);
+ TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb.x_abs: ldb.x$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ldb_x_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb$_AW.x_abs: ldb$_AW.x$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ldb__AW_x_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb.ab.x_abs: ldb.ab.x$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ldb_ab_x_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb.as.x_abs: ldb.as.x$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ldb_as_x_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), (cgen_rtx_error (current_cpu, "invalid insn"), 0));
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb.x_abc: ldb.x$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ldb_x_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb$_AW.x_abc: ldb$_AW.x$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ldb__AW_x_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb.ab.x_abc: ldb.ab.x$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ldb_ab_x_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb.as.x_abc: ldb.as.x$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ldb_as_x_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), (cgen_rtx_error (current_cpu, "invalid insn"), 0));
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw_abs: ldw$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ldw_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw$_AW_abs: ldw$_AW$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ldw__AW_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw.ab_abs: ldw.ab$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ldw_ab_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw.as_abs: ldw.as$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ldw_as_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s9), 1));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw_abc: ldw$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ldw_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw$_AW_abc: ldw$_AW$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ldw__AW_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw.ab_abc: ldw.ab$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ldw_ab_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw.as_abc: ldw.as$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ldw_as_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 1));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw_s_abc: ldw$_S $R_a,[$R_b,$R_c] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ldw_s_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), GET_H_CR16 (FLD (f_op__c)));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR16 (FLD (f_op__a), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw_s_abu: ldw$_S $R_c,[$R_b,$sc_u5w] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ldw_s_abu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldw_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), FLD (f_u5x2));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw_s_gprel: ldw$_S $R_b,[$GP,$sc_s9w] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ldw_s_gprel) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldw_s_gprel.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_GP (), FLD (f_s9x2));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_R0 (, opval);
+ TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw.x_abs: ldw.x$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ldw_x_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw$_AW.x_abs: ldw$_AW.x$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ldw__AW_x_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw.ab.x_abs: ldw.ab.x$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ldw_ab_x_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw.as.x_abs: ldw.as.x$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ldw_as_x_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s9), 1));
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw.x_abc: ldw.x$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ldw_x_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw$_AW.x_abc: ldw$_AW.x$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ldw__AW_x_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw.ab.x_abc: ldw.ab.x$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ldw_ab_x_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw.as.x_abc: ldw.as.x$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ldw_as_x_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 1));
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw_s.x_abu: ldw$_S.x $R_c,[$R_b,$sc_u5w] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ldw_s_x_abu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldw_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), FLD (f_u5x2));
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* st_abs: st$STODi $RC,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,st_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMSI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* st$_AW_abs: st$_AW$STODi $RC,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,st__AW_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMSI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* st.ab_abs: st.ab$STODi $RC,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,st_ab_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMSI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* st.as_abs: st.as$STODi $RC,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,st_as_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s9), 2));
+ {
+ SI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMSI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* st_s_abu: st$_S $R_c,[$R_b,$sc_u5_] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,st_s_abu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), FLD (f_u5x4));
+ {
+ SI opval = GET_H_CR16 (FLD (f_op__c));
+ SETMEMSI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* st_s_absp: st$_S $R_b,[$SP,$u5x4] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,st_s_absp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_SP (), FLD (f_u5x4));
+ {
+ SI opval = GET_H_CR16 (FLD (f_op__b));
+ SETMEMSI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* stb_abs: stb$STODi $RC,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,stb_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ QI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMQI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* stb$_AW_abs: stb$_AW$STODi $RC,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,stb__AW_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ QI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMQI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* stb.ab_abs: stb.ab$STODi $RC,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,stb_ab_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ QI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMQI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* stb.as_abs: stb.as$STODi $RC,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,stb_as_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), (cgen_rtx_error (current_cpu, "invalid insn"), 0));
+ {
+ QI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMQI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* stb_s_abu: stb$_S $R_c,[$R_b,$sc_u5b] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,stb_s_abu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), FLD (f_u5));
+ {
+ QI opval = GET_H_CR16 (FLD (f_op__c));
+ SETMEMQI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* stb_s_absp: stb$_S $R_b,[$SP,$u5x4] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,stb_s_absp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_SP (), FLD (f_u5x4));
+ {
+ QI opval = GET_H_CR16 (FLD (f_op__b));
+ SETMEMQI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* stw_abs: stw$STODi $RC,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,stw_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ HI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMHI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* stw$_AW_abs: stw$_AW$STODi $RC,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,stw__AW_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ HI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMHI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* stw.ab_abs: stw.ab$STODi $RC,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,stw_ab_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ HI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMHI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* stw.as_abs: stw.as$STODi $RC,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,stw_as_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s9), 1));
+ {
+ HI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMHI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* stw_s_abu: stw$_S $R_c,[$R_b,$sc_u5w] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,stw_s_abu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldw_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), FLD (f_u5x2));
+ {
+ HI opval = GET_H_CR16 (FLD (f_op__c));
+ SETMEMHI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* add_L_s12 $RA,: add$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,add_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add_ccu6 $RA,: add$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,add_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add_L_u6 $RA,: add$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,add_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add_L_r_r $RA,$RC: add$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,add_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add_cc $RA,$RC: add$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,add_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add_s_abc: add$_S $R_a,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (a5f,add_s_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ADDSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__a), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* add_s_cbu3: add$_S $R_c,$R_b,$u3 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,add_s_cbu3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u3);
+ {
+ SI opval = ADDSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* add_s_mcah: add$_S $R_b,$R_b,$Rh */
+
+static SEM_PC
+SEM_FN_NAME (a5f,add_s_mcah) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+{
+if (EQSI (FLD (f_op_h), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 2));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (2, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_h), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR (FLD (f_op_h));
+ {
+ SI opval = ADDSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* add_s_absp: add$_S $R_b,$SP,$u5x4 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,add_s_absp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_SP ();
+ tmp_C = FLD (f_u5x4);
+ {
+ SI opval = ADDSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* add_s_asspsp: add$_S $SP,$SP,$u5x4 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,add_s_asspsp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_SP ();
+ tmp_C = FLD (f_u5x4);
+ {
+ SI opval = ADDSI (tmp_B, tmp_C);
+ SET_H_SP (, opval);
+ TRACE_RESULT (current_cpu, abuf, "sp", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* add_s_gp: add$_S $R0,$GP,$s9x4 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,add_s_gp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_gprel.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_GP ();
+ tmp_C = FLD (f_s9x4);
+ {
+ SI opval = ADDSI (tmp_B, tmp_C);
+ SET_H_R0 (, opval);
+ TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* add_s_r_u7: add$_S $R_b,$R_b,$u7 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,add_s_r_u7) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_r_u7.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u7);
+ {
+ SI opval = ADDSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* adc_L_s12 $RA,: adc$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,adc_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDCSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* adc_ccu6 $RA,: adc$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,adc_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDCSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* adc_L_u6 $RA,: adc$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,adc_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDCSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* adc_L_r_r $RA,$RC: adc$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,adc_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDCSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* adc_cc $RA,$RC: adc$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,adc_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDCSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub_L_s12 $RA,: sub$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,sub_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub_ccu6 $RA,: sub$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,sub_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub_L_u6 $RA,: sub$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,sub_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub_L_r_r $RA,$RC: sub$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,sub_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub_cc $RA,$RC: sub$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,sub_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub_s_cbu3: sub$_S $R_c,$R_b,$u3 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,sub_s_cbu3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u3);
+ {
+ SI opval = SUBSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_SUB_s_go: sub$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (a5f,I16_GO_SUB_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = SUBSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* sub_s_go_sub_ne: sub$_S $NE$R_b,$R_b,$R_b */
+
+static SEM_PC
+SEM_FN_NAME (a5f,sub_s_go_sub_ne) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQBI (CPU (h_zbit), 0)) {
+ {
+ SI opval = 0;
+ SET_H_CR16 (FLD (f_op__b), opval);
+ written |= (1 << 1);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub_s_ssb: sub$_S $R_b,$R_b,$u5 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,sub_s_ssb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ {
+ SI opval = SUBSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* sub_s_asspsp: sub$_S $SP,$SP,$u5x4 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,sub_s_asspsp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_SP ();
+ tmp_C = FLD (f_u5x4);
+ {
+ SI opval = SUBSI (tmp_B, tmp_C);
+ SET_H_SP (, opval);
+ TRACE_RESULT (current_cpu, abuf, "sp", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* sbc_L_s12 $RA,: sbc$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,sbc_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBCSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sbc_ccu6 $RA,: sbc$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,sbc_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBCSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sbc_L_u6 $RA,: sbc$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,sbc_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBCSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sbc_L_r_r $RA,$RC: sbc$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,sbc_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBCSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sbc_cc $RA,$RC: sbc$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,sbc_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBCSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* and_L_s12 $RA,: and$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,and_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* and_ccu6 $RA,: and$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,and_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* and_L_u6 $RA,: and$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,and_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* and_L_r_r $RA,$RC: and$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,and_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* and_cc $RA,$RC: and$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,and_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_AND_s_go: and$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (a5f,I16_GO_AND_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ANDSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* or_L_s12 $RA,: or$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,or_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* or_ccu6 $RA,: or$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,or_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* or_L_u6 $RA,: or$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,or_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* or_L_r_r $RA,$RC: or$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,or_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* or_cc $RA,$RC: or$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,or_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_OR_s_go: or$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (a5f,I16_GO_OR_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ORSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* bic_L_s12 $RA,: bic$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,bic_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (FLD (f_s12)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bic_ccu6 $RA,: bic$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,bic_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (FLD (f_u6)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bic_L_u6 $RA,: bic$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,bic_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (FLD (f_u6)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bic_L_r_r $RA,$RC: bic$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,bic_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bic_cc $RA,$RC: bic$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,bic_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_BIC_s_go: bic$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (a5f,I16_GO_BIC_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ANDSI (tmp_B, INVSI (tmp_C));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* xor_L_s12 $RA,: xor$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,xor_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* xor_ccu6 $RA,: xor$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,xor_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* xor_L_u6 $RA,: xor$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,xor_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* xor_L_r_r $RA,$RC: xor$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,xor_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* xor_cc $RA,$RC: xor$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,xor_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_XOR_s_go: xor$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (a5f,I16_GO_XOR_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = XORSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* max_L_s12 $RA,: max$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,max_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (GTSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12))) ? (GET_H_CR (FLD (f_op_B))) : (FLD (f_s12));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = GESI (FLD (f_s12), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* max_ccu6 $RA,: max$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,max_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (GTSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6))) ? (GET_H_CR (FLD (f_op_B))) : (FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = GESI (FLD (f_u6), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* max_L_u6 $RA,: max$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,max_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (GTSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6))) ? (GET_H_CR (FLD (f_op_B))) : (FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = GESI (FLD (f_u6), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* max_L_r_r $RA,$RC: max$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,max_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (GTSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)))) ? (GET_H_CR (FLD (f_op_B))) : (GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = GESI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* max_cc $RA,$RC: max$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,max_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (GTSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)))) ? (GET_H_CR (FLD (f_op_B))) : (GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = GESI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* min_L_s12 $RA,: min$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,min_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (LTSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12))) ? (GET_H_CR (FLD (f_op_B))) : (FLD (f_s12));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = LESI (FLD (f_s12), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* min_ccu6 $RA,: min$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,min_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (LTSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6))) ? (GET_H_CR (FLD (f_op_B))) : (FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = LESI (FLD (f_u6), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* min_L_u6 $RA,: min$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,min_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (LTSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6))) ? (GET_H_CR (FLD (f_op_B))) : (FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = LESI (FLD (f_u6), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* min_L_r_r $RA,$RC: min$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,min_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (LTSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)))) ? (GET_H_CR (FLD (f_op_B))) : (GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = LESI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* min_cc $RA,$RC: min$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,min_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (LTSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)))) ? (GET_H_CR (FLD (f_op_B))) : (GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = LESI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mov_L_s12 : mov$_L$F $RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mov_L_s12_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+ tmp_result = FLD (f_s12);
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GTSI (FLD (f_F), 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mov_ccu6 : mov$Qcondi$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mov_ccu6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+((void) 0); /*nop*/
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+ tmp_result = FLD (f_u6);
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GTSI (FLD (f_F), 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 5);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mov_L_u6 : mov$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mov_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+ tmp_result = FLD (f_u6);
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GTSI (FLD (f_F), 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mov_L_r_r $RC: mov$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mov_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = GET_H_CR (FLD (f_op_C));
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GTSI (FLD (f_F), 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mov_cc $RC: mov$Qcondi$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mov_cc__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+ tmp_result = GET_H_CR (FLD (f_op_C));
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GTSI (FLD (f_F), 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mov_s_mcah: mov$_S $R_b,$Rh */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mov_s_mcah) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_h), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 2));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (2, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_h), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = GET_H_CR (FLD (f_op_h));
+ {
+ SI opval = tmp_result;
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+if (GTSI (-1, 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mov_s_mcahb: mov$_S $Rh,$R_b */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mov_s_mcahb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+ tmp_result = GET_H_CR16 (FLD (f_op__b));
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_h), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GTSI (-1, 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mov_s_r_u7: mov$_S $R_b,$u7 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mov_s_r_u7) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+ tmp_result = FLD (f_u8);
+ {
+ SI opval = tmp_result;
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+if (GTSI (-1, 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* tst_L_s12 : tst$_L$F1 $RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,tst_L_s12_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_s12);
+ tmp_result = ANDSI (tmp_B, tmp_C);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* tst_ccu6 : tst$Qcondi$F1 $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,tst_ccu6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+ tmp_result = ANDSI (tmp_B, tmp_C);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* tst_L_u6 : tst$_L$F1 $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,tst_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+ tmp_result = ANDSI (tmp_B, tmp_C);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* tst_L_r_r $RC: tst$_L$F1 $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,tst_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+ tmp_result = ANDSI (tmp_B, tmp_C);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* tst_cc $RC: tst$Qcondi$F1 $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,tst_cc__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+ tmp_result = ANDSI (tmp_B, tmp_C);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* tst_s_go: tst$_S $R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (a5f,tst_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ tmp_result = ANDSI (tmp_B, tmp_C);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* cmp_L_s12 : cmp$_L$F1 $RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,cmp_L_s12_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (FLD (f_s12));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (FLD (f_s12));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* cmp_ccu6 : cmp$Qcondi$F1 $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,cmp_ccu6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* cmp_L_u6 : cmp$_L$F1 $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,cmp_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* cmp_L_r_r $RC: cmp$_L$F1 $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,cmp_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* cmp_cc $RC: cmp$Qcondi$F1 $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,cmp_cc__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* cmp_s_mcah: cmp$_S $R_b,$Rh */
+
+static SEM_PC
+SEM_FN_NAME (a5f,cmp_s_mcah) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+{
+if (EQSI (FLD (f_op_h), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 2));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (2, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_h), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = EXTSIDI (GET_H_CR16 (FLD (f_op__b)));
+ tmp_C = EXTSIDI (GET_H_CR (FLD (f_op_h)));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR16 (FLD (f_op__b)));
+ tmp_C = ZEXTSIDI (GET_H_CR (FLD (f_op_h)));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* cmp_s_r_u7: cmp$_S $R_b,$u7 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,cmp_s_r_u7) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_r_u7.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = EXTSIDI (GET_H_CR16 (FLD (f_op__b)));
+ tmp_C = EXTSIDI (FLD (f_u7));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR16 (FLD (f_op__b)));
+ tmp_C = ZEXTSIDI (FLD (f_u7));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* rcmp_L_s12 : rcmp$_L$F1 $RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,rcmp_L_s12_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (FLD (f_s12));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (FLD (f_s12));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* rcmp_ccu6 : rcmp$Qcondi$F1 $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,rcmp_ccu6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* rcmp_L_u6 : rcmp$_L$F1 $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,rcmp_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* rcmp_L_r_r $RC: rcmp$_L$F1 $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,rcmp_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* rcmp_cc $RC: rcmp$Qcondi$F1 $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,rcmp_cc__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* rsub_L_s12 $RA,: rsub$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,rsub_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (FLD (f_s12), GET_H_CR (FLD (f_op_B)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (FLD (f_s12), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (FLD (f_s12), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* rsub_ccu6 $RA,: rsub$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,rsub_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (FLD (f_u6), GET_H_CR (FLD (f_op_B)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (FLD (f_u6), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (FLD (f_u6), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* rsub_L_u6 $RA,: rsub$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,rsub_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (FLD (f_u6), GET_H_CR (FLD (f_op_B)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (FLD (f_u6), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (FLD (f_u6), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* rsub_L_r_r $RA,$RC: rsub$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,rsub_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* rsub_cc $RA,$RC: rsub$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,rsub_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bset_L_s12 $RA,: bset$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,bset_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (FLD (f_s12), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bset_ccu6 $RA,: bset$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,bset_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bset_L_u6 $RA,: bset$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,bset_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bset_L_r_r $RA,$RC: bset$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,bset_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bset_cc $RA,$RC: bset$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,bset_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bset_s_ssb: bset$_S $R_b,$R_b,$u5 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,bset_s_ssb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ {
+ SI opval = ORSI (tmp_B, SLLSI (1, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* bclr_L_s12 $RA,: bclr$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,bclr_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (SLLSI (1, ANDSI (FLD (f_s12), 31))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bclr_ccu6 $RA,: bclr$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,bclr_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (SLLSI (1, ANDSI (FLD (f_u6), 31))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bclr_L_u6 $RA,: bclr$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,bclr_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (SLLSI (1, ANDSI (FLD (f_u6), 31))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bclr_L_r_r $RA,$RC: bclr$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,bclr_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bclr_cc $RA,$RC: bclr$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,bclr_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bclr_s_ssb: bclr$_S $R_b,$R_b,$u5 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,bclr_s_ssb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ {
+ SI opval = ANDSI (tmp_B, INVSI (SLLSI (1, ANDSI (tmp_C, 31))));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* btst_L_s12 : btst$_L$F1 $RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,btst_L_s12_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_s12);
+ tmp_result = ANDSI (tmp_B, SLLSI (1, ANDSI (tmp_C, 31)));
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* btst_ccu6 : btst$Qcondi$F1 $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,btst_ccu6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+ tmp_result = ANDSI (tmp_B, SLLSI (1, ANDSI (tmp_C, 31)));
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* btst_L_u6 : btst$_L$F1 $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,btst_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+ tmp_result = ANDSI (tmp_B, SLLSI (1, ANDSI (tmp_C, 31)));
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* btst_L_r_r $RC: btst$_L$F1 $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,btst_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+ tmp_result = ANDSI (tmp_B, SLLSI (1, ANDSI (tmp_C, 31)));
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* btst_cc $RC: btst$Qcondi$F1 $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,btst_cc__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+ tmp_result = ANDSI (tmp_B, SLLSI (1, ANDSI (tmp_C, 31)));
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* btst_s_ssb: btst$_S $R_b,$u5 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,btst_s_ssb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ tmp_result = ANDSI (tmp_B, SLLSI (1, ANDSI (tmp_C, 31)));
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* bxor_L_s12 $RA,: bxor$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,bxor_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (FLD (f_s12), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bxor_ccu6 $RA,: bxor$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,bxor_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bxor_L_u6 $RA,: bxor$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,bxor_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bxor_L_r_r $RA,$RC: bxor$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,bxor_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bxor_cc $RA,$RC: bxor$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,bxor_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bmsk_L_s12 $RA,: bmsk$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,bmsk_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), SUBSI (SLLSI (SLLSI (1, ANDSI (FLD (f_s12), 31)), 1), 1));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bmsk_ccu6 $RA,: bmsk$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,bmsk_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), SUBSI (SLLSI (SLLSI (1, ANDSI (FLD (f_u6), 31)), 1), 1));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bmsk_L_u6 $RA,: bmsk$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,bmsk_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), SUBSI (SLLSI (SLLSI (1, ANDSI (FLD (f_u6), 31)), 1), 1));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bmsk_L_r_r $RA,$RC: bmsk$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,bmsk_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), SUBSI (SLLSI (SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31)), 1), 1));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bmsk_cc $RA,$RC: bmsk$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,bmsk_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), SUBSI (SLLSI (SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31)), 1), 1));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bmsk_s_ssb: bmsk$_S $R_b,$R_b,$u5 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,bmsk_s_ssb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ {
+ SI opval = ANDSI (tmp_B, SUBSI (SLLSI (SLLSI (1, ANDSI (tmp_C, 31)), 1), 1));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* add1_L_s12 $RA,: add1$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,add1_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s12), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_s12), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add1_ccu6 $RA,: add1$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,add1_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add1_L_u6 $RA,: add1$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,add1_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add1_L_r_r $RA,$RC: add1$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,add1_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add1_cc $RA,$RC: add1$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,add1_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_ADD1_s_go: add1$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (a5f,I16_GO_ADD1_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ADDSI (tmp_B, SLLSI (tmp_C, 1));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* add2_L_s12 $RA,: add2$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,add2_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s12), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_s12), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add2_ccu6 $RA,: add2$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,add2_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add2_L_u6 $RA,: add2$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,add2_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add2_L_r_r $RA,$RC: add2$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,add2_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add2_cc $RA,$RC: add2$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,add2_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_ADD2_s_go: add2$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (a5f,I16_GO_ADD2_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ADDSI (tmp_B, SLLSI (tmp_C, 2));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* add3_L_s12 $RA,: add3$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,add3_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s12), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_s12), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add3_ccu6 $RA,: add3$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,add3_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add3_L_u6 $RA,: add3$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,add3_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add3_L_r_r $RA,$RC: add3$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,add3_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add3_cc $RA,$RC: add3$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,add3_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_ADD3_s_go: add3$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (a5f,I16_GO_ADD3_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ADDSI (tmp_B, SLLSI (tmp_C, 3));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* sub1_L_s12 $RA,: sub1$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,sub1_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s12), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_s12), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub1_ccu6 $RA,: sub1$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,sub1_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub1_L_u6 $RA,: sub1$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,sub1_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub1_L_r_r $RA,$RC: sub1$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,sub1_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub1_cc $RA,$RC: sub1$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,sub1_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub2_L_s12 $RA,: sub2$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,sub2_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s12), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_s12), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub2_ccu6 $RA,: sub2$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,sub2_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub2_L_u6 $RA,: sub2$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,sub2_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub2_L_r_r $RA,$RC: sub2$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,sub2_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub2_cc $RA,$RC: sub2$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,sub2_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub3_L_s12 $RA,: sub3$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,sub3_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s12), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_s12), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub3_ccu6 $RA,: sub3$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,sub3_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub3_L_u6 $RA,: sub3$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,sub3_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub3_L_r_r $RA,$RC: sub3$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,sub3_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub3_cc $RA,$RC: sub3$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,sub3_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpy_L_s12 $RA,: mpy$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mpy_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (EXTSIDI (tmp_result), MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_s12))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpy_ccu6 $RA,: mpy$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mpy_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (EXTSIDI (tmp_result), MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpy_L_u6 $RA,: mpy$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mpy_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (EXTSIDI (tmp_result), MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpy_L_r_r $RA,$RC: mpy$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mpy_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (EXTSIDI (tmp_result), MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C)))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpy_cc $RA,$RC: mpy$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mpy_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (EXTSIDI (tmp_result), MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C)))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyh_L_s12 $RA,: mpyh$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mpyh_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_s12))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyh_ccu6 $RA,: mpyh$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mpyh_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyh_L_u6 $RA,: mpyh$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mpyh_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyh_L_r_r $RA,$RC: mpyh$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mpyh_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C)))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyh_cc $RA,$RC: mpyh$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mpyh_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C)))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyhu_L_s12 $RA,: mpyhu$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mpyhu_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_s12))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyhu_ccu6 $RA,: mpyhu$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mpyhu_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_u6))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyhu_L_u6 $RA,: mpyhu$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mpyhu_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_u6))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyhu_L_r_r $RA,$RC: mpyhu$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mpyhu_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (GET_H_CR (FLD (f_op_C)))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyhu_cc $RA,$RC: mpyhu$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mpyhu_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (GET_H_CR (FLD (f_op_C)))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyu_L_s12 $RA,: mpyu$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mpyu_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (ZEXTSIDI (tmp_result), MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_s12))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyu_ccu6 $RA,: mpyu$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mpyu_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (ZEXTSIDI (tmp_result), MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_u6))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyu_L_u6 $RA,: mpyu$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mpyu_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (ZEXTSIDI (tmp_result), MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_u6))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyu_L_r_r $RA,$RC: mpyu$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mpyu_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (ZEXTSIDI (tmp_result), MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (GET_H_CR (FLD (f_op_C)))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyu_cc $RA,$RC: mpyu$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mpyu_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (ZEXTSIDI (tmp_result), MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (GET_H_CR (FLD (f_op_C)))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* j_L_r_r [$RC_noilink]: j$_L$F0 [$RC_noilink] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,j_L_r_r___RC_noilink_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_cc [$RC_noilink]: j$Qcondi$F0 [$RC_noilink] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,j_cc___RC_noilink_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_L_r_r [$RC_ilink]: j$_L$F1F [$RC_ilink] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,j_L_r_r___RC_ilink_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_ILINKX (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_ILINKX (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_ILINKX (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_cc [$RC_ilink]: j$Qcondi$F1F [$RC_ilink] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,j_cc___RC_ilink_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_ILINKX (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_ILINKX (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_ILINKX (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_L_s12 : j$_L$F0 $s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,j_L_s12_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_ccu6 : j$Qcondi$F0 $U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,j_ccu6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_L_u6 : j$_L$F0 $U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,j_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_s: j$_S [$R_b] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,j_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_s$_S: j$_S [$R31] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,j_s__S) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_seq$_S: jeq$_S [$R31] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,j_seq__S) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if (NEBI (CPU (h_zbit), 0)) {
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if (NEBI (CPU (h_zbit), 0)) {
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if (NEBI (CPU (h_zbit), 0)) {
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_sne$_S: jne$_S [$R31] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,j_sne__S) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if (EQBI (CPU (h_zbit), 0)) {
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if (EQBI (CPU (h_zbit), 0)) {
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if (EQBI (CPU (h_zbit), 0)) {
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_L_s12.d : j$_L$F0.d $s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,j_L_s12_d_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_ccu6.d : j$Qcondi$F0.d $U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,j_ccu6_d_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_L_u6.d : j$_L$F0.d $U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,j_L_u6_d_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_L_r_r.d [$RC]: j$_L$F0.d [$RC] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,j_L_r_r_d___RC_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_cc.d [$RC]: j$Qcondi$F0.d [$RC] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,j_cc_d___RC_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_s.d: j$_S.d [$R_b] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,j_s_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_s$_S.d: j$_S.d [$R31] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,j_s__S_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jl_L_s12 : jl$_L$F0 $s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,jl_L_s12_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jl_ccu6 : jl$Qcondi$F0 $U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,jl_ccu6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jl_L_u6 : jl$_L$F0 $U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,jl_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jl_s: jl$_S [$R_b] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,jl_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 2);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 2);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 2);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jl_L_r_r [$RC_noilink]: jl$_L$F0 [$RC_noilink] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,jl_L_r_r___RC_noilink_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, ((EQSI (FLD (f_op_C), 62)) ? (8) : (4)));
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, ((EQSI (FLD (f_op_C), 62)) ? (8) : (4)));
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, ((EQSI (FLD (f_op_C), 62)) ? (8) : (4)));
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jl_cc [$RC_noilink]: jl$Qcondi$F0 [$RC_noilink] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,jl_cc___RC_noilink_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, ((EQSI (FLD (f_op_C), 62)) ? (8) : (4)));
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, ((EQSI (FLD (f_op_C), 62)) ? (8) : (4)));
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, ((EQSI (FLD (f_op_C), 62)) ? (8) : (4)));
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jl_L_s12.d : jl$_L$F0.d $s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,jl_L_s12_d_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jl_ccu6.d : jl$Qcondi$F0.d $U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,jl_ccu6_d_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jl_L_u6.d : jl$_L$F0.d $U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,jl_L_u6_d_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jl_L_r_r.d [$RC]: jl$_L$F0.d [$RC] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,jl_L_r_r_d___RC_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jl_cc.d [$RC]: jl$Qcondi$F0.d [$RC] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,jl_cc_d___RC_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jl_s.d: jl$_S.d [$R_b] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,jl_s_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 2));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 2));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 2));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* lp_L_s12 : lp$_L$F0 $s12x2 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,lp_L_s12_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lp_L_s12_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ SI opval = ADDSI (ANDSI (pc, -4), FLD (f_s12x2));
+ SET_H_AUXR (((UINT) 3), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_AUXR (((UINT) 2), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ SI opval = ADDSI (ANDSI (pc, -4), FLD (f_s12x2));
+ SET_H_AUXR (((UINT) 3), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_AUXR (((UINT) 2), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ SI opval = ADDSI (ANDSI (pc, -4), FLD (f_s12x2));
+ SET_H_AUXR (((UINT) 3), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_AUXR (((UINT) 2), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* lpcc_ccu6: lp$Qcondi$F0 $U6x2 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,lpcc_ccu6) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lpcc_ccu6.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ SI opval = ADDSI (ANDSI (pc, -4), FLD (f_u6x2));
+ SET_H_AUXR (((UINT) 3), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_AUXR (((UINT) 2), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ SI opval = ADDSI (ANDSI (pc, -4), FLD (f_u6x2));
+ SET_H_AUXR (((UINT) 3), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_AUXR (((UINT) 2), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ SI opval = ADDSI (ANDSI (pc, -4), FLD (f_u6x2));
+ SET_H_AUXR (((UINT) 3), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_AUXR (((UINT) 2), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+}
+}
+} else {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = ADDSI (ANDSI (pc, -4), FLD (f_u6x2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = ADDSI (ANDSI (pc, -4), FLD (f_u6x2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = ADDSI (ANDSI (pc, -4), FLD (f_u6x2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* flag_L_s12 : flag$_L$F0 $s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,flag_L_s12_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (ANDSI (FLD (f_s12), 1)) {
+sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc, sim_exited, a5f_h_cr_get (current_cpu, 0));}
+ {
+ SI opval = FLD (f_s12);
+ SET_H_STATUS32 (((UINT) 0), opval);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* flag_ccu6 : flag$Qcondi$F0 $U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,flag_ccu6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+if (ANDSI (FLD (f_u6), 1)) {
+sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc, sim_exited, a5f_h_cr_get (current_cpu, 0));}
+ {
+ SI opval = FLD (f_u6);
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* flag_L_u6 : flag$_L$F0 $U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,flag_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (ANDSI (FLD (f_u6), 1)) {
+sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc, sim_exited, a5f_h_cr_get (current_cpu, 0));}
+ {
+ SI opval = FLD (f_u6);
+ SET_H_STATUS32 (((UINT) 0), opval);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* flag_L_r_r $RC: flag$_L$F0 $RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,flag_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (ANDSI (GET_H_CR (FLD (f_op_C)), 1)) {
+sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc, sim_exited, a5f_h_cr_get (current_cpu, 0));}
+ {
+ SI opval = GET_H_CR (FLD (f_op_C));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* flag_cc $RC: flag$Qcondi$F0 $RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,flag_cc__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+if (ANDSI (GET_H_CR (FLD (f_op_C)), 1)) {
+sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc, sim_exited, a5f_h_cr_get (current_cpu, 0));}
+ {
+ SI opval = GET_H_CR (FLD (f_op_C));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* lr_L_r_r [$RC]: lr$_L$F0 $RB,[$RC] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,lr_L_r_r___RC_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ {
+ SI opval = GET_H_AUXR (GET_H_CR (FLD (f_op_C)));
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* lr_L_s12 : lr$_L$F0 $RB,[$s12] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,lr_L_s12_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ {
+ SI opval = GET_H_AUXR (FLD (f_s12));
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* lr_L_u6 : lr$_L$F0 $RB,[$U6] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,lr_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ {
+ SI opval = GET_H_AUXR (FLD (f_u6));
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* sr_L_r_r [$RC]: sr$_L$F0 $RB,[$RC] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,sr_L_r_r___RC_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ {
+ SI opval = GET_H_CR (FLD (f_op_B));
+ SET_H_AUXR (GET_H_CR (FLD (f_op_C)), opval);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* sr_L_s12 : sr$_L$F0 $RB,[$s12] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,sr_L_s12_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ {
+ SI opval = GET_H_CR (FLD (f_op_B));
+ SET_H_AUXR (FLD (f_s12), opval);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* sr_L_u6 : sr$_L$F0 $RB,[$U6] */
+
+static SEM_PC
+SEM_FN_NAME (a5f,sr_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ {
+ SI opval = GET_H_CR (FLD (f_op_B));
+ SET_H_AUXR (FLD (f_u6), opval);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* asl_L_r_r $RC: asl$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,asl_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asl_L_u6 : asl$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,asl_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (FLD (f_u6), FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (FLD (f_u6), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (FLD (f_u6), FLD (f_u6), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_ASL_s_go: asl$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (a5f,I16_GO_ASL_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ADDSI (tmp_C, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* asr_L_r_r $RC: asr$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,asr_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SRASI (GET_H_CR (FLD (f_op_C)), 1);
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (GET_H_CR (FLD (f_op_C)), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asr_L_u6 : asr$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,asr_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SRASI (FLD (f_u6), 1);
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (FLD (f_u6), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_ASR_s_go: asr$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (a5f,I16_GO_ASR_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = SRASI (tmp_C, 1);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* lsr_L_r_r $RC: lsr$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,lsr_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SRLSI (GET_H_CR (FLD (f_op_C)), 1);
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (GET_H_CR (FLD (f_op_C)), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* lsr_L_u6 : lsr$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,lsr_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SRLSI (FLD (f_u6), 1);
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (FLD (f_u6), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_LSR_s_go: lsr$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (a5f,I16_GO_LSR_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = SRLSI (tmp_C, 1);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ror_L_r_r $RC: ror$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ror_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (SRLSI (GET_H_CR (FLD (f_op_C)), 1), SLLSI (GET_H_CR (FLD (f_op_C)), 31));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (GET_H_CR (FLD (f_op_C)), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* ror_L_u6 : ror$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ror_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (SRLSI (FLD (f_u6), 1), SLLSI (FLD (f_u6), 31));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (FLD (f_u6), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* rrc_L_r_r $RC: rrc$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,rrc_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (SRLSI (GET_H_CR (FLD (f_op_C)), 1), SLLSI (ZEXTBISI (CPU (h_cbit)), 31));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (GET_H_CR (FLD (f_op_C)), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* rrc_L_u6 : rrc$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,rrc_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (SRLSI (FLD (f_u6), 1), SLLSI (ZEXTBISI (CPU (h_cbit)), 31));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (FLD (f_u6), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sexb_L_r_r $RC: sexb$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,sexb_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = EXTQISI ((GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sexb_L_u6 : sexb$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,sexb_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = EXTQISI ((FLD (f_u6)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_SEXB_s_go: sexb$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (a5f,I16_GO_SEXB_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = EXTQISI ((tmp_C));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* sexw_L_r_r $RC: sexw$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,sexw_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = EXTHISI ((GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sexw_L_u6 : sexw$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,sexw_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = EXTHISI ((FLD (f_u6)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_SEXW_s_go: sexw$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (a5f,I16_GO_SEXW_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = EXTHISI ((tmp_C));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* extb_L_r_r $RC: extb$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,extb_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ZEXTQISI ((GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* extb_L_u6 : extb$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,extb_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ZEXTQISI ((FLD (f_u6)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_EXTB_s_go: extb$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (a5f,I16_GO_EXTB_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ZEXTQISI ((tmp_C));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* extw_L_r_r $RC: extw$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,extw_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ZEXTHISI ((GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* extw_L_u6 : extw$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,extw_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ZEXTHISI ((FLD (f_u6)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_EXTW_s_go: extw$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (a5f,I16_GO_EXTW_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ZEXTHISI ((tmp_C));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* abs_L_r_r $RC: abs$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,abs_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ABSSI (({ SI tmp_res;
+ tmp_res = GET_H_CR (FLD (f_op_C));
+; tmp_res; }));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI ((GET_H_CR (FLD (f_op_C))), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (GET_H_CR (FLD (f_op_C)), 0x80000000);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_vbit);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* abs_L_u6 : abs$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,abs_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ABSSI (({ SI tmp_res;
+ tmp_res = FLD (f_u6);
+; tmp_res; }));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI ((FLD (f_u6)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (FLD (f_u6), 0x80000000);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_vbit);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_ABS_s_go: abs$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (a5f,I16_GO_ABS_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ABSSI (({ SI tmp_res;
+ tmp_res = tmp_C;
+; tmp_res; }));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* not_L_r_r $RC: not$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,not_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = INVSI (GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* not_L_u6 : not$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,not_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = INVSI (FLD (f_u6));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_NOT_s_go: not$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (a5f,I16_GO_NOT_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = INVSI (tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* rlc_L_r_r $RC: rlc$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,rlc_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (SLLSI (GET_H_CR (FLD (f_op_C)), 1), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SRLSI (GET_H_CR (FLD (f_op_C)), 31);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* rlc_L_u6 : rlc$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,rlc_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (SLLSI (FLD (f_u6), 1), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SRLSI (FLD (f_u6), 31);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_NEG_s_go: neg$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (a5f,I16_GO_NEG_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = NEGSI (tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* swi: swi */
+
+static SEM_PC
+SEM_FN_NAME (a5f,swi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+; /*clobber*/
+ {
+ USI opval = arc_trap (current_cpu, pc, 4, 0);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else if (0) {
+{
+; /*clobber*/
+ {
+ USI opval = arc_trap (current_cpu, pc, 4, 0);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+; /*clobber*/
+ {
+ USI opval = arc_trap (current_cpu, pc, 4, 0);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* trap_s: trap$_S $trapnum */
+
+static SEM_PC
+SEM_FN_NAME (a5f,trap_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_trap_s.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = arc_trap (current_cpu, pc, 2, FLD (f_trapnum));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+; /*clobber*/
+}
+}
+}
+ else if (0) {
+{
+ {
+ USI opval = arc_trap (current_cpu, pc, 2, FLD (f_trapnum));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+; /*clobber*/
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ {
+ USI opval = arc_trap (current_cpu, pc, 2, FLD (f_trapnum));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+; /*clobber*/
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* brk: brk */
+
+static SEM_PC
+SEM_FN_NAME (a5f,brk) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+arc_breakpoint (current_cpu, pc, 4);
+
+ return vpc;
+#undef FLD
+}
+
+/* brk_s: brk_s */
+
+static SEM_PC
+SEM_FN_NAME (a5f,brk_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+arc_breakpoint (current_cpu, pc, 2);
+
+ return vpc;
+#undef FLD
+}
+
+/* asl_L_s12 $RA,: asl$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,asl_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_s12), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_s12), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (32, ANDSI (FLD (f_s12), 31))), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asl_ccu6 $RA,: asl$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,asl_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (32, ANDSI (FLD (f_u6), 31))), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asl_L_u6 $RA,: asl$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,asl_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (32, ANDSI (FLD (f_u6), 31))), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asl_L_r_r $RA,$RC: asl$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,asl_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (32, ANDSI (GET_H_CR (FLD (f_op_C)), 31))), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asl_cc $RA,$RC: asl$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,asl_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (32, ANDSI (GET_H_CR (FLD (f_op_C)), 31))), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asl_s_cbu3: asl$_S $R_c,$R_b,$u3 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,asl_s_cbu3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u3);
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* asl_s_ssb: asl$_S $R_b,$R_b,$u5 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,asl_s_ssb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_ASLM_s_go: asl$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (a5f,I16_GO_ASLM_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* lsr_L_s12 $RA,: lsr$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,lsr_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_s12), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_s12), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_s12), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* lsr_ccu6 $RA,: lsr$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,lsr_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_u6), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* lsr_L_u6 $RA,: lsr$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,lsr_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_u6), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* lsr_L_r_r $RA,$RC: lsr$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,lsr_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* lsr_cc $RA,$RC: lsr$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,lsr_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* lsr_s_ssb: lsr$_S $R_b,$R_b,$u5 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,lsr_s_ssb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_LSRM_s_go: lsr$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (a5f,I16_GO_LSRM_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* asr_L_s12 $RA,: asr$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,asr_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_s12), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_s12), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_s12), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asr_ccu6 $RA,: asr$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,asr_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_u6), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asr_L_u6 $RA,: asr$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,asr_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_u6), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asr_L_r_r $RA,$RC: asr$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,asr_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asr_cc $RA,$RC: asr$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,asr_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asr_s_cbu3: asr$_S $R_c,$R_b,$u3 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,asr_s_cbu3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u3);
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* asr_s_ssb: asr$_S $R_b,$R_b,$u5 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,asr_s_ssb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_ASRM_s_go: asr$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (a5f,I16_GO_ASRM_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ror_L_s12 $RA,: ror$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ror_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (RORSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_s12), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_s12), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_s12), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* ror_ccu6 $RA,: ror$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ror_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (RORSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_u6), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* ror_L_u6 $RA,: ror$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ror_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (RORSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_u6), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* ror_L_r_r $RA,$RC: ror$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ror_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (RORSI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* ror_cc $RA,$RC: ror$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,ror_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (RORSI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mul64_L_s12 : mul64$_L$F1 $RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mul64_L_s12_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_s12)));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mul64_ccu6 : mul64$Qcondi$F1 $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mul64_ccu6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6)));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mul64_L_u6 : mul64$_L$F1 $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mul64_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6)));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mul64_L_r_r $RC: mul64$_L$F1 $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mul64_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mul64_cc $RC: mul64$Qcondi$F1 $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mul64_cc__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mul64_s_go: mul64$_S $R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mul64_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (EXTSIDI (GET_H_CR16 (FLD (f_op__b))), EXTSIDI (GET_H_CR16 (FLD (f_op__c))));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mulu64_L_s12 : mulu64$_L$F1 $RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mulu64_L_s12_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_s12)));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mulu64_ccu6 : mulu64$Qcondi$F1 $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mulu64_ccu6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_u6)));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mulu64_L_u6 : mulu64$_L$F1 $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mulu64_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_u6)));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mulu64_L_r_r $RC: mulu64$_L$F1 $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mulu64_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (GET_H_CR (FLD (f_op_C))));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mulu64_cc $RC: mulu64$Qcondi$F1 $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mulu64_cc__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (GET_H_CR (FLD (f_op_C))));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* adds_L_s12 $RA,: adds$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,adds_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = ADDDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_s12)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* adds_ccu6 $RA,: adds$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,adds_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = ADDDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* adds_L_u6 $RA,: adds$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,adds_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = ADDDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* adds_L_r_r $RA,$RC: adds$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,adds_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = ADDDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* adds_cc $RA,$RC: adds$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,adds_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = ADDDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* subs_L_s12 $RA,: subs$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,subs_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_s12)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* subs_ccu6 $RA,: subs$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,subs_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* subs_L_u6 $RA,: subs$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,subs_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* subs_L_r_r $RA,$RC: subs$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,subs_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* subs_cc $RA,$RC: subs$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,subs_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* divaw_L_s12 $RA,: divaw$_L$F0 $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,divaw_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ USI tmp_tmp;
+ tmp_tmp = SLLSI (GET_H_CR (FLD (f_op_B)), 1);
+; ((EQSI (ANDSI (SUBSI (tmp_tmp, FLD (f_s12)), 0x80000000), 0)) ? (ADDSI (SUBSI (tmp_tmp, FLD (f_s12)), 1)) : (tmp_tmp)); }));
+if (FLD (f_F)) {
+((void) 0); /*nop*/
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* divaw_ccu6 $RA,: divaw$Qcondi$F0 $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,divaw_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ USI tmp_tmp;
+ tmp_tmp = SLLSI (GET_H_CR (FLD (f_op_B)), 1);
+; ((EQSI (ANDSI (SUBSI (tmp_tmp, FLD (f_u6)), 0x80000000), 0)) ? (ADDSI (SUBSI (tmp_tmp, FLD (f_u6)), 1)) : (tmp_tmp)); }));
+if (FLD (f_F)) {
+((void) 0); /*nop*/
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* divaw_L_u6 $RA,: divaw$_L$F0 $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,divaw_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ USI tmp_tmp;
+ tmp_tmp = SLLSI (GET_H_CR (FLD (f_op_B)), 1);
+; ((EQSI (ANDSI (SUBSI (tmp_tmp, FLD (f_u6)), 0x80000000), 0)) ? (ADDSI (SUBSI (tmp_tmp, FLD (f_u6)), 1)) : (tmp_tmp)); }));
+if (FLD (f_F)) {
+((void) 0); /*nop*/
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* divaw_L_r_r $RA,$RC: divaw$_L$F0 $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,divaw_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ USI tmp_tmp;
+ tmp_tmp = SLLSI (GET_H_CR (FLD (f_op_B)), 1);
+; ((EQSI (ANDSI (SUBSI (tmp_tmp, GET_H_CR (FLD (f_op_C))), 0x80000000), 0)) ? (ADDSI (SUBSI (tmp_tmp, GET_H_CR (FLD (f_op_C))), 1)) : (tmp_tmp)); }));
+if (FLD (f_F)) {
+((void) 0); /*nop*/
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* divaw_cc $RA,$RC: divaw$Qcondi$F0 $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,divaw_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ USI tmp_tmp;
+ tmp_tmp = SLLSI (GET_H_CR (FLD (f_op_B)), 1);
+; ((EQSI (ANDSI (SUBSI (tmp_tmp, GET_H_CR (FLD (f_op_C))), 0x80000000), 0)) ? (ADDSI (SUBSI (tmp_tmp, GET_H_CR (FLD (f_op_C))), 1)) : (tmp_tmp)); }));
+if (FLD (f_F)) {
+((void) 0); /*nop*/
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asls_L_s12 $RA,: asls$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,asls_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((FLD (f_s12)), 31)) ? (SLLDI (tmp_b, 31)) : (LTSI ((FLD (f_s12)), -31)) ? (SRADI (tmp_b, 31)) : (GESI ((FLD (f_s12)), 0)) ? (SLLDI (tmp_b, (FLD (f_s12)))) : (SRASI (GET_H_CR (FLD (f_op_B)), NEGSI ((FLD (f_s12)))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asls_ccu6 $RA,: asls$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,asls_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((FLD (f_u6)), 31)) ? (SLLDI (tmp_b, 31)) : (LTSI ((FLD (f_u6)), -31)) ? (SRADI (tmp_b, 31)) : (GESI ((FLD (f_u6)), 0)) ? (SLLDI (tmp_b, (FLD (f_u6)))) : (SRASI (GET_H_CR (FLD (f_op_B)), NEGSI ((FLD (f_u6)))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asls_L_u6 $RA,: asls$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,asls_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((FLD (f_u6)), 31)) ? (SLLDI (tmp_b, 31)) : (LTSI ((FLD (f_u6)), -31)) ? (SRADI (tmp_b, 31)) : (GESI ((FLD (f_u6)), 0)) ? (SLLDI (tmp_b, (FLD (f_u6)))) : (SRASI (GET_H_CR (FLD (f_op_B)), NEGSI ((FLD (f_u6)))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asls_L_r_r $RA,$RC: asls$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,asls_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((GET_H_CR (FLD (f_op_C))), 31)) ? (SLLDI (tmp_b, 31)) : (LTSI ((GET_H_CR (FLD (f_op_C))), -31)) ? (SRADI (tmp_b, 31)) : (GESI ((GET_H_CR (FLD (f_op_C))), 0)) ? (SLLDI (tmp_b, (GET_H_CR (FLD (f_op_C))))) : (SRASI (GET_H_CR (FLD (f_op_B)), NEGSI ((GET_H_CR (FLD (f_op_C))))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asls_cc $RA,$RC: asls$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,asls_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((GET_H_CR (FLD (f_op_C))), 31)) ? (SLLDI (tmp_b, 31)) : (LTSI ((GET_H_CR (FLD (f_op_C))), -31)) ? (SRADI (tmp_b, 31)) : (GESI ((GET_H_CR (FLD (f_op_C))), 0)) ? (SLLDI (tmp_b, (GET_H_CR (FLD (f_op_C))))) : (SRASI (GET_H_CR (FLD (f_op_B)), NEGSI ((GET_H_CR (FLD (f_op_C))))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asrs_L_s12 $RA,: asrs$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,asrs_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((FLD (f_s12)), 31)) ? (SRADI (tmp_b, 31)) : (LTSI ((FLD (f_s12)), -31)) ? (SLLDI (tmp_b, 31)) : (GESI ((FLD (f_s12)), 0)) ? (SRADI (tmp_b, (FLD (f_s12)))) : (SLLSI (GET_H_CR (FLD (f_op_B)), NEGSI ((FLD (f_s12)))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asrs_ccu6 $RA,: asrs$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,asrs_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((FLD (f_u6)), 31)) ? (SRADI (tmp_b, 31)) : (LTSI ((FLD (f_u6)), -31)) ? (SLLDI (tmp_b, 31)) : (GESI ((FLD (f_u6)), 0)) ? (SRADI (tmp_b, (FLD (f_u6)))) : (SLLSI (GET_H_CR (FLD (f_op_B)), NEGSI ((FLD (f_u6)))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asrs_L_u6 $RA,: asrs$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,asrs_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((FLD (f_u6)), 31)) ? (SRADI (tmp_b, 31)) : (LTSI ((FLD (f_u6)), -31)) ? (SLLDI (tmp_b, 31)) : (GESI ((FLD (f_u6)), 0)) ? (SRADI (tmp_b, (FLD (f_u6)))) : (SLLSI (GET_H_CR (FLD (f_op_B)), NEGSI ((FLD (f_u6)))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asrs_L_r_r $RA,$RC: asrs$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,asrs_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((GET_H_CR (FLD (f_op_C))), 31)) ? (SRADI (tmp_b, 31)) : (LTSI ((GET_H_CR (FLD (f_op_C))), -31)) ? (SLLDI (tmp_b, 31)) : (GESI ((GET_H_CR (FLD (f_op_C))), 0)) ? (SRADI (tmp_b, (GET_H_CR (FLD (f_op_C))))) : (SLLSI (GET_H_CR (FLD (f_op_B)), NEGSI ((GET_H_CR (FLD (f_op_C))))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asrs_cc $RA,$RC: asrs$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,asrs_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((GET_H_CR (FLD (f_op_C))), 31)) ? (SRADI (tmp_b, 31)) : (LTSI ((GET_H_CR (FLD (f_op_C))), -31)) ? (SLLDI (tmp_b, 31)) : (GESI ((GET_H_CR (FLD (f_op_C))), 0)) ? (SRADI (tmp_b, (GET_H_CR (FLD (f_op_C))))) : (SLLSI (GET_H_CR (FLD (f_op_B)), NEGSI ((GET_H_CR (FLD (f_op_C))))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* addsdw_L_s12 $RA,: addsdw$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,addsdw_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((FLD (f_s12)), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((FLD (f_s12)), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* addsdw_ccu6 $RA,: addsdw$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,addsdw_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((FLD (f_u6)), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((FLD (f_u6)), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* addsdw_L_u6 $RA,: addsdw$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,addsdw_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((FLD (f_u6)), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((FLD (f_u6)), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* addsdw_L_r_r $RA,$RC: addsdw$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,addsdw_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* addsdw_cc $RA,$RC: addsdw$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,addsdw_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* subsdw_L_s12 $RA,: subsdw$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,subsdw_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((FLD (f_s12)), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((FLD (f_s12)), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* subsdw_ccu6 $RA,: subsdw$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,subsdw_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((FLD (f_u6)), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((FLD (f_u6)), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* subsdw_L_u6 $RA,: subsdw$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,subsdw_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((FLD (f_u6)), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((FLD (f_u6)), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* subsdw_L_r_r $RA,$RC: subsdw$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,subsdw_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* subsdw_cc $RA,$RC: subsdw$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,subsdw_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* swap_L_r_r $RC: swap$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,swap_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (RORSI (GET_H_CR (FLD (f_op_C)), 16));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* swap_L_u6 : swap$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,swap_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (RORSI (FLD (f_u6), 16));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* norm_L_r_r $RC: norm$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,norm_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_val;
+ SI tmp_bits;
+ tmp_val = ((GESI ((GET_H_CR (FLD (f_op_C))), 0)) ? ((GET_H_CR (FLD (f_op_C)))) : (INVSI ((GET_H_CR (FLD (f_op_C))))));
+; tmp_bits = 31;
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 4), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 4));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 4));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 3), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 3));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 3));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 2), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 2));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 2));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 1), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 1));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 1));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 0), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 0));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 0));
+}
+; tmp_bits; }));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* norm_L_u6 : norm$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,norm_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_val;
+ SI tmp_bits;
+ tmp_val = ((GESI ((FLD (f_u6)), 0)) ? ((FLD (f_u6))) : (INVSI ((FLD (f_u6)))));
+; tmp_bits = 31;
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 4), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 4));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 4));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 3), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 3));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 3));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 2), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 2));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 2));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 1), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 1));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 1));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 0), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 0));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 0));
+}
+; tmp_bits; }));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (FLD (f_u6), 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (FLD (f_u6), 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* rnd16_L_r_r $RC: rnd16$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,rnd16_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (({ DI tmp_tmp;
+ tmp_tmp = ADDDI (EXTSIDI (32768), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }), 16));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* rnd16_L_u6 : rnd16$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,rnd16_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (({ DI tmp_tmp;
+ tmp_tmp = ADDDI (EXTSIDI (32768), EXTSIDI (FLD (f_u6)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }), 16));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* abssw_L_r_r $RC: abssw$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,abssw_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_tmp;
+ tmp_tmp = ABSSI (EXTHISI ((GET_H_CR (FLD (f_op_C)))));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* abssw_L_u6 : abssw$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,abssw_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_tmp;
+ tmp_tmp = ABSSI (EXTHISI ((FLD (f_u6))));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* abss_L_r_r $RC: abss$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,abss_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (((GESI ((GET_H_CR (FLD (f_op_C))), 0)) ? (GET_H_CR (FLD (f_op_C))) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (0), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }))));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* abss_L_u6 : abss$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,abss_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (((GESI ((FLD (f_u6)), 0)) ? (FLD (f_u6)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (0), EXTSIDI (FLD (f_u6)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }))));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* negsw_L_r_r $RC: negsw$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,negsw_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_tmp;
+ tmp_tmp = EXTHISI ((GET_H_CR (FLD (f_op_C))));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* negsw_L_u6 : negsw$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,negsw_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_tmp;
+ tmp_tmp = EXTHISI ((FLD (f_u6)));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* negs_L_r_r $RC: negs$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,negs_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (0), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* negs_L_u6 : negs$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,negs_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (0), EXTSIDI (FLD (f_u6)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* normw_L_r_r $RC: normw$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,normw_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_val;
+ SI tmp_bits;
+ tmp_val = ((GESI (ORSI (SLLSI (GET_H_CR (FLD (f_op_C)), 16), ANDSI (GET_H_CR (FLD (f_op_C)), 65535)), 0)) ? (ORSI (SLLSI (GET_H_CR (FLD (f_op_C)), 16), ANDSI (GET_H_CR (FLD (f_op_C)), 65535))) : (INVSI (ORSI (SLLSI (GET_H_CR (FLD (f_op_C)), 16), ANDSI (GET_H_CR (FLD (f_op_C)), 65535)))));
+; tmp_bits = 31;
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 4), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 4));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 4));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 3), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 3));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 3));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 2), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 2));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 2));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 1), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 1));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 1));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 0), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 0));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 0));
+}
+; tmp_bits; }));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* normw_L_u6 : normw$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,normw_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_val;
+ SI tmp_bits;
+ tmp_val = ((GESI (ORSI (SLLSI (FLD (f_u6), 16), ANDSI (FLD (f_u6), 65535)), 0)) ? (ORSI (SLLSI (FLD (f_u6), 16), ANDSI (FLD (f_u6), 65535))) : (INVSI (ORSI (SLLSI (FLD (f_u6), 16), ANDSI (FLD (f_u6), 65535)))));
+; tmp_bits = 31;
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 4), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 4));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 4));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 3), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 3));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 3));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 2), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 2));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 2));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 1), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 1));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 1));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 0), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 0));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 0));
+}
+; tmp_bits; }));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* nop_s: nop_s */
+
+static SEM_PC
+SEM_FN_NAME (a5f,nop_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* unimp_s: unimp_s */
+
+static SEM_PC
+SEM_FN_NAME (a5f,unimp_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+cgen_rtx_error (current_cpu, "invalid insn");
+
+ return vpc;
+#undef FLD
+}
+
+/* pop_s_b: pop$_S $R_b */
+
+static SEM_PC
+SEM_FN_NAME (a5f,pop_s_b) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ SI opval = GETMEMSI (current_cpu, pc, GET_H_SP ());
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (GET_H_SP (), 4);
+ SET_H_SP (, opval);
+ TRACE_RESULT (current_cpu, abuf, "sp", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* pop_s_blink: pop$_S $R31 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,pop_s_blink) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ SI opval = GETMEMSI (current_cpu, pc, GET_H_SP ());
+ SET_H_R31 (, opval);
+ TRACE_RESULT (current_cpu, abuf, "r31", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (GET_H_SP (), 4);
+ SET_H_SP (, opval);
+ TRACE_RESULT (current_cpu, abuf, "sp", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* push_s_b: push$_S $R_b */
+
+static SEM_PC
+SEM_FN_NAME (a5f,push_s_b) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ SI opval = ADDSI (GET_H_SP (), -4);
+ SET_H_SP (, opval);
+ TRACE_RESULT (current_cpu, abuf, "sp", 'x', opval);
+ }
+ {
+ SI opval = GET_H_CR16 (FLD (f_op__b));
+ SETMEMSI (current_cpu, pc, GET_H_SP (), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* push_s_blink: push$_S $R31 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,push_s_blink) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ SI opval = ADDSI (GET_H_SP (), -4);
+ SET_H_SP (, opval);
+ TRACE_RESULT (current_cpu, abuf, "sp", 'x', opval);
+ }
+ {
+ SI opval = GET_H_R31 ();
+ SETMEMSI (current_cpu, pc, GET_H_SP (), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mullw_L_s12 $RA,: mullw$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mullw_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_s12), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mullw_ccu6 $RA,: mullw$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mullw_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_u6), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mullw_L_u6 $RA,: mullw$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mullw_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_u6), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mullw_L_r_r $RA,$RC: mullw$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mullw_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mullw_cc $RA,$RC: mullw$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mullw_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* maclw_L_s12 $RA,: maclw$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,maclw_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ SI tmp_SItmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_s12), 65535))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; {
+ BI opval = ANDBI (CPU (h_vbit), SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; if (NEBI (CPU (h_vbit), 0)) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; tmp_SItmp = ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp));
+; tmp_cur_s1bit = ORBI (tmp_cur_s1bit, CPU (h_vbit));
+; tmp_SItmp; });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* maclw_ccu6 $RA,: maclw$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,maclw_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ SI tmp_SItmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_u6), 65535))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; {
+ BI opval = ANDBI (CPU (h_vbit), SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; if (NEBI (CPU (h_vbit), 0)) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; tmp_SItmp = ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp));
+; tmp_cur_s1bit = ORBI (tmp_cur_s1bit, CPU (h_vbit));
+; tmp_SItmp; });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* maclw_L_u6 $RA,: maclw$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,maclw_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ SI tmp_SItmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_u6), 65535))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; {
+ BI opval = ANDBI (CPU (h_vbit), SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; if (NEBI (CPU (h_vbit), 0)) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; tmp_SItmp = ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp));
+; tmp_cur_s1bit = ORBI (tmp_cur_s1bit, CPU (h_vbit));
+; tmp_SItmp; });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* maclw_L_r_r $RA,$RC: maclw$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,maclw_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ SI tmp_SItmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), 65535))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; {
+ BI opval = ANDBI (CPU (h_vbit), SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; if (NEBI (CPU (h_vbit), 0)) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; tmp_SItmp = ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp));
+; tmp_cur_s1bit = ORBI (tmp_cur_s1bit, CPU (h_vbit));
+; tmp_SItmp; });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* maclw_cc $RA,$RC: maclw$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,maclw_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ SI tmp_SItmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), 65535))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; {
+ BI opval = ANDBI (CPU (h_vbit), SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; if (NEBI (CPU (h_vbit), 0)) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; tmp_SItmp = ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp));
+; tmp_cur_s1bit = ORBI (tmp_cur_s1bit, CPU (h_vbit));
+; tmp_SItmp; });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* machlw_L_s12 $RA,: machlw$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,machlw_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_s12), -65536))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = ANDBI (CPU (h_vbit), XORDI (tmp_old, tmp_tmp));
+; if (tmp_cur_s1bit) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* machlw_ccu6 $RA,: machlw$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,machlw_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_u6), -65536))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = ANDBI (CPU (h_vbit), XORDI (tmp_old, tmp_tmp));
+; if (tmp_cur_s1bit) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* machlw_L_u6 $RA,: machlw$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,machlw_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_u6), -65536))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = ANDBI (CPU (h_vbit), XORDI (tmp_old, tmp_tmp));
+; if (tmp_cur_s1bit) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* machlw_L_r_r $RA,$RC: machlw$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,machlw_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), -65536))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = ANDBI (CPU (h_vbit), XORDI (tmp_old, tmp_tmp));
+; if (tmp_cur_s1bit) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* machlw_cc $RA,$RC: machlw$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,machlw_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), -65536))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = ANDBI (CPU (h_vbit), XORDI (tmp_old, tmp_tmp));
+; if (tmp_cur_s1bit) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mululw_L_s12 $RA,: mululw$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mululw_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (FLD (f_s12), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mululw_ccu6 $RA,: mululw$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mululw_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (FLD (f_u6), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mululw_L_u6 $RA,: mululw$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mululw_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (FLD (f_u6), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mululw_L_r_r $RA,$RC: mululw$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mululw_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mululw_cc $RA,$RC: mululw$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,mululw_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* machulw_L_s12 $RA,: machulw$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,machulw_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (FLD (f_s12), -65536))));
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = (GTUDI (tmp_old, tmp_tmp)) ? (( tmp_tmp = -1, 1)) : (0);
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* machulw_ccu6 $RA,: machulw$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,machulw_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (FLD (f_u6), -65536))));
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = (GTUDI (tmp_old, tmp_tmp)) ? (( tmp_tmp = -1, 1)) : (0);
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* machulw_L_u6 $RA,: machulw$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (a5f,machulw_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (FLD (f_u6), -65536))));
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = (GTUDI (tmp_old, tmp_tmp)) ? (( tmp_tmp = -1, 1)) : (0);
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* machulw_L_r_r $RA,$RC: machulw$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,machulw_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), -65536))));
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = (GTUDI (tmp_old, tmp_tmp)) ? (( tmp_tmp = -1, 1)) : (0);
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* machulw_cc $RA,$RC: machulw$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (a5f,machulw_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), -65536))));
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = (GTUDI (tmp_old, tmp_tmp)) ? (( tmp_tmp = -1, 1)) : (0);
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* current_loop_end: */
+
+static SEM_PC
+SEM_FN_NAME (a5f,current_loop_end) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDBI (EQSI (pc, GET_H_AUXR (((UINT) 3))), NOTBI (CPU (h_lbit)))) {
+{
+ {
+ SI opval = ADDSI (GET_H_CR (((UINT) 60)), -1);
+ SET_H_CR (((UINT) 60), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GET_H_CR (((UINT) 60))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (GET_H_AUXR (((UINT) 2)), 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = GET_H_AUXR (((UINT) 2));
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* current_loop_end_after_branch: */
+
+static SEM_PC
+SEM_FN_NAME (a5f,current_loop_end_after_branch) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (
+#ifdef SEM_IN_SWITCH
+pbb_br_type != SEM_BRANCH_UNTAKEN
+#else
+CPU_PBB_BR_NPC (current_cpu) != SEM_BRANCH_UNTAKEN
+#endif
+) {
+
+#ifdef SEM_IN_SWITCH
+npc = pbb_br_npc; br_type = pbb_br_type;
+#else
+npc = CPU_PBB_BR_NPC (current_cpu); br_type = CPU_PBB_BR_TYPE (current_cpu);
+#endif
+}
+ else if (ANDBI (EQSI (pc, GET_H_AUXR (((UINT) 3))), NOTBI (CPU (h_lbit)))) {
+{
+ {
+ SI opval = ADDSI (GET_H_CR (((UINT) 60)), -1);
+ SET_H_CR (((UINT) 60), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GET_H_CR (((UINT) 60))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (GET_H_AUXR (((UINT) 2)), 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = GET_H_AUXR (((UINT) 2));
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* arc600_current_loop_end_after_branch: */
+
+static SEM_PC
+SEM_FN_NAME (a5f,arc600_current_loop_end_after_branch) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (
+#ifdef SEM_IN_SWITCH
+pbb_br_type != SEM_BRANCH_UNTAKEN
+#else
+CPU_PBB_BR_NPC (current_cpu) != SEM_BRANCH_UNTAKEN
+#endif
+) {
+{
+
+#ifdef SEM_IN_SWITCH
+npc = pbb_br_npc; br_type = pbb_br_type;
+#else
+npc = CPU_PBB_BR_NPC (current_cpu); br_type = CPU_PBB_BR_TYPE (current_cpu);
+#endif
+ {
+ SI opval = ADDSI (GET_H_CR (((UINT) 60)), -1);
+ SET_H_CR (((UINT) 60), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+ else if (ANDBI (EQSI (pc, GET_H_AUXR (((UINT) 3))), NOTBI (CPU (h_lbit)))) {
+{
+ {
+ SI opval = ADDSI (GET_H_CR (((UINT) 60)), -1);
+ SET_H_CR (((UINT) 60), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GET_H_CR (((UINT) 60))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (GET_H_AUXR (((UINT) 2)), 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = GET_H_AUXR (((UINT) 2));
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* Table of all semantic fns. */
+
+static const struct sem_fn_desc sem_fns[] = {
+ { A5F_INSN_X_INVALID, SEM_FN_NAME (a5f,x_invalid) },
+ { A5F_INSN_X_AFTER, SEM_FN_NAME (a5f,x_after) },
+ { A5F_INSN_X_BEFORE, SEM_FN_NAME (a5f,x_before) },
+ { A5F_INSN_X_CTI_CHAIN, SEM_FN_NAME (a5f,x_cti_chain) },
+ { A5F_INSN_X_CHAIN, SEM_FN_NAME (a5f,x_chain) },
+ { A5F_INSN_X_BEGIN, SEM_FN_NAME (a5f,x_begin) },
+ { A5F_INSN_B_S, SEM_FN_NAME (a5f,b_s) },
+ { A5F_INSN_BCC_S, SEM_FN_NAME (a5f,bcc_s) },
+ { A5F_INSN_BRCC_S, SEM_FN_NAME (a5f,brcc_s) },
+ { A5F_INSN_BCC_L, SEM_FN_NAME (a5f,bcc_l) },
+ { A5F_INSN_BCC_L_D, SEM_FN_NAME (a5f,bcc_l_d) },
+ { A5F_INSN_B_L, SEM_FN_NAME (a5f,b_l) },
+ { A5F_INSN_B_L_D, SEM_FN_NAME (a5f,b_l_d) },
+ { A5F_INSN_BRCC_RC, SEM_FN_NAME (a5f,brcc_RC) },
+ { A5F_INSN_BRCC_RC_D, SEM_FN_NAME (a5f,brcc_RC_d) },
+ { A5F_INSN_BRCC_U6, SEM_FN_NAME (a5f,brcc_U6) },
+ { A5F_INSN_BRCC_U6_D, SEM_FN_NAME (a5f,brcc_U6_d) },
+ { A5F_INSN_BL_S, SEM_FN_NAME (a5f,bl_s) },
+ { A5F_INSN_BLCC, SEM_FN_NAME (a5f,blcc) },
+ { A5F_INSN_BLCC_D, SEM_FN_NAME (a5f,blcc_d) },
+ { A5F_INSN_BL, SEM_FN_NAME (a5f,bl) },
+ { A5F_INSN_BL_D, SEM_FN_NAME (a5f,bl_d) },
+ { A5F_INSN_LD_ABS, SEM_FN_NAME (a5f,ld_abs) },
+ { A5F_INSN_LD__AW_ABS, SEM_FN_NAME (a5f,ld__AW_abs) },
+ { A5F_INSN_LD_AB_ABS, SEM_FN_NAME (a5f,ld_ab_abs) },
+ { A5F_INSN_LD_AS_ABS, SEM_FN_NAME (a5f,ld_as_abs) },
+ { A5F_INSN_LD_ABC, SEM_FN_NAME (a5f,ld_abc) },
+ { A5F_INSN_LD__AW_ABC, SEM_FN_NAME (a5f,ld__AW_abc) },
+ { A5F_INSN_LD_AB_ABC, SEM_FN_NAME (a5f,ld_ab_abc) },
+ { A5F_INSN_LD_AS_ABC, SEM_FN_NAME (a5f,ld_as_abc) },
+ { A5F_INSN_LD_S_ABC, SEM_FN_NAME (a5f,ld_s_abc) },
+ { A5F_INSN_LD_S_ABU, SEM_FN_NAME (a5f,ld_s_abu) },
+ { A5F_INSN_LD_S_ABSP, SEM_FN_NAME (a5f,ld_s_absp) },
+ { A5F_INSN_LD_S_GPREL, SEM_FN_NAME (a5f,ld_s_gprel) },
+ { A5F_INSN_LD_S_PCREL, SEM_FN_NAME (a5f,ld_s_pcrel) },
+ { A5F_INSN_LDB_ABS, SEM_FN_NAME (a5f,ldb_abs) },
+ { A5F_INSN_LDB__AW_ABS, SEM_FN_NAME (a5f,ldb__AW_abs) },
+ { A5F_INSN_LDB_AB_ABS, SEM_FN_NAME (a5f,ldb_ab_abs) },
+ { A5F_INSN_LDB_AS_ABS, SEM_FN_NAME (a5f,ldb_as_abs) },
+ { A5F_INSN_LDB_ABC, SEM_FN_NAME (a5f,ldb_abc) },
+ { A5F_INSN_LDB__AW_ABC, SEM_FN_NAME (a5f,ldb__AW_abc) },
+ { A5F_INSN_LDB_AB_ABC, SEM_FN_NAME (a5f,ldb_ab_abc) },
+ { A5F_INSN_LDB_AS_ABC, SEM_FN_NAME (a5f,ldb_as_abc) },
+ { A5F_INSN_LDB_S_ABC, SEM_FN_NAME (a5f,ldb_s_abc) },
+ { A5F_INSN_LDB_S_ABU, SEM_FN_NAME (a5f,ldb_s_abu) },
+ { A5F_INSN_LDB_S_ABSP, SEM_FN_NAME (a5f,ldb_s_absp) },
+ { A5F_INSN_LDB_S_GPREL, SEM_FN_NAME (a5f,ldb_s_gprel) },
+ { A5F_INSN_LDB_X_ABS, SEM_FN_NAME (a5f,ldb_x_abs) },
+ { A5F_INSN_LDB__AW_X_ABS, SEM_FN_NAME (a5f,ldb__AW_x_abs) },
+ { A5F_INSN_LDB_AB_X_ABS, SEM_FN_NAME (a5f,ldb_ab_x_abs) },
+ { A5F_INSN_LDB_AS_X_ABS, SEM_FN_NAME (a5f,ldb_as_x_abs) },
+ { A5F_INSN_LDB_X_ABC, SEM_FN_NAME (a5f,ldb_x_abc) },
+ { A5F_INSN_LDB__AW_X_ABC, SEM_FN_NAME (a5f,ldb__AW_x_abc) },
+ { A5F_INSN_LDB_AB_X_ABC, SEM_FN_NAME (a5f,ldb_ab_x_abc) },
+ { A5F_INSN_LDB_AS_X_ABC, SEM_FN_NAME (a5f,ldb_as_x_abc) },
+ { A5F_INSN_LDW_ABS, SEM_FN_NAME (a5f,ldw_abs) },
+ { A5F_INSN_LDW__AW_ABS, SEM_FN_NAME (a5f,ldw__AW_abs) },
+ { A5F_INSN_LDW_AB_ABS, SEM_FN_NAME (a5f,ldw_ab_abs) },
+ { A5F_INSN_LDW_AS_ABS, SEM_FN_NAME (a5f,ldw_as_abs) },
+ { A5F_INSN_LDW_ABC, SEM_FN_NAME (a5f,ldw_abc) },
+ { A5F_INSN_LDW__AW_ABC, SEM_FN_NAME (a5f,ldw__AW_abc) },
+ { A5F_INSN_LDW_AB_ABC, SEM_FN_NAME (a5f,ldw_ab_abc) },
+ { A5F_INSN_LDW_AS_ABC, SEM_FN_NAME (a5f,ldw_as_abc) },
+ { A5F_INSN_LDW_S_ABC, SEM_FN_NAME (a5f,ldw_s_abc) },
+ { A5F_INSN_LDW_S_ABU, SEM_FN_NAME (a5f,ldw_s_abu) },
+ { A5F_INSN_LDW_S_GPREL, SEM_FN_NAME (a5f,ldw_s_gprel) },
+ { A5F_INSN_LDW_X_ABS, SEM_FN_NAME (a5f,ldw_x_abs) },
+ { A5F_INSN_LDW__AW_X_ABS, SEM_FN_NAME (a5f,ldw__AW_x_abs) },
+ { A5F_INSN_LDW_AB_X_ABS, SEM_FN_NAME (a5f,ldw_ab_x_abs) },
+ { A5F_INSN_LDW_AS_X_ABS, SEM_FN_NAME (a5f,ldw_as_x_abs) },
+ { A5F_INSN_LDW_X_ABC, SEM_FN_NAME (a5f,ldw_x_abc) },
+ { A5F_INSN_LDW__AW_X_ABC, SEM_FN_NAME (a5f,ldw__AW_x_abc) },
+ { A5F_INSN_LDW_AB_X_ABC, SEM_FN_NAME (a5f,ldw_ab_x_abc) },
+ { A5F_INSN_LDW_AS_X_ABC, SEM_FN_NAME (a5f,ldw_as_x_abc) },
+ { A5F_INSN_LDW_S_X_ABU, SEM_FN_NAME (a5f,ldw_s_x_abu) },
+ { A5F_INSN_ST_ABS, SEM_FN_NAME (a5f,st_abs) },
+ { A5F_INSN_ST__AW_ABS, SEM_FN_NAME (a5f,st__AW_abs) },
+ { A5F_INSN_ST_AB_ABS, SEM_FN_NAME (a5f,st_ab_abs) },
+ { A5F_INSN_ST_AS_ABS, SEM_FN_NAME (a5f,st_as_abs) },
+ { A5F_INSN_ST_S_ABU, SEM_FN_NAME (a5f,st_s_abu) },
+ { A5F_INSN_ST_S_ABSP, SEM_FN_NAME (a5f,st_s_absp) },
+ { A5F_INSN_STB_ABS, SEM_FN_NAME (a5f,stb_abs) },
+ { A5F_INSN_STB__AW_ABS, SEM_FN_NAME (a5f,stb__AW_abs) },
+ { A5F_INSN_STB_AB_ABS, SEM_FN_NAME (a5f,stb_ab_abs) },
+ { A5F_INSN_STB_AS_ABS, SEM_FN_NAME (a5f,stb_as_abs) },
+ { A5F_INSN_STB_S_ABU, SEM_FN_NAME (a5f,stb_s_abu) },
+ { A5F_INSN_STB_S_ABSP, SEM_FN_NAME (a5f,stb_s_absp) },
+ { A5F_INSN_STW_ABS, SEM_FN_NAME (a5f,stw_abs) },
+ { A5F_INSN_STW__AW_ABS, SEM_FN_NAME (a5f,stw__AW_abs) },
+ { A5F_INSN_STW_AB_ABS, SEM_FN_NAME (a5f,stw_ab_abs) },
+ { A5F_INSN_STW_AS_ABS, SEM_FN_NAME (a5f,stw_as_abs) },
+ { A5F_INSN_STW_S_ABU, SEM_FN_NAME (a5f,stw_s_abu) },
+ { A5F_INSN_ADD_L_S12__RA_, SEM_FN_NAME (a5f,add_L_s12__RA_) },
+ { A5F_INSN_ADD_CCU6__RA_, SEM_FN_NAME (a5f,add_ccu6__RA_) },
+ { A5F_INSN_ADD_L_U6__RA_, SEM_FN_NAME (a5f,add_L_u6__RA_) },
+ { A5F_INSN_ADD_L_R_R__RA__RC, SEM_FN_NAME (a5f,add_L_r_r__RA__RC) },
+ { A5F_INSN_ADD_CC__RA__RC, SEM_FN_NAME (a5f,add_cc__RA__RC) },
+ { A5F_INSN_ADD_S_ABC, SEM_FN_NAME (a5f,add_s_abc) },
+ { A5F_INSN_ADD_S_CBU3, SEM_FN_NAME (a5f,add_s_cbu3) },
+ { A5F_INSN_ADD_S_MCAH, SEM_FN_NAME (a5f,add_s_mcah) },
+ { A5F_INSN_ADD_S_ABSP, SEM_FN_NAME (a5f,add_s_absp) },
+ { A5F_INSN_ADD_S_ASSPSP, SEM_FN_NAME (a5f,add_s_asspsp) },
+ { A5F_INSN_ADD_S_GP, SEM_FN_NAME (a5f,add_s_gp) },
+ { A5F_INSN_ADD_S_R_U7, SEM_FN_NAME (a5f,add_s_r_u7) },
+ { A5F_INSN_ADC_L_S12__RA_, SEM_FN_NAME (a5f,adc_L_s12__RA_) },
+ { A5F_INSN_ADC_CCU6__RA_, SEM_FN_NAME (a5f,adc_ccu6__RA_) },
+ { A5F_INSN_ADC_L_U6__RA_, SEM_FN_NAME (a5f,adc_L_u6__RA_) },
+ { A5F_INSN_ADC_L_R_R__RA__RC, SEM_FN_NAME (a5f,adc_L_r_r__RA__RC) },
+ { A5F_INSN_ADC_CC__RA__RC, SEM_FN_NAME (a5f,adc_cc__RA__RC) },
+ { A5F_INSN_SUB_L_S12__RA_, SEM_FN_NAME (a5f,sub_L_s12__RA_) },
+ { A5F_INSN_SUB_CCU6__RA_, SEM_FN_NAME (a5f,sub_ccu6__RA_) },
+ { A5F_INSN_SUB_L_U6__RA_, SEM_FN_NAME (a5f,sub_L_u6__RA_) },
+ { A5F_INSN_SUB_L_R_R__RA__RC, SEM_FN_NAME (a5f,sub_L_r_r__RA__RC) },
+ { A5F_INSN_SUB_CC__RA__RC, SEM_FN_NAME (a5f,sub_cc__RA__RC) },
+ { A5F_INSN_SUB_S_CBU3, SEM_FN_NAME (a5f,sub_s_cbu3) },
+ { A5F_INSN_I16_GO_SUB_S_GO, SEM_FN_NAME (a5f,I16_GO_SUB_s_go) },
+ { A5F_INSN_SUB_S_GO_SUB_NE, SEM_FN_NAME (a5f,sub_s_go_sub_ne) },
+ { A5F_INSN_SUB_S_SSB, SEM_FN_NAME (a5f,sub_s_ssb) },
+ { A5F_INSN_SUB_S_ASSPSP, SEM_FN_NAME (a5f,sub_s_asspsp) },
+ { A5F_INSN_SBC_L_S12__RA_, SEM_FN_NAME (a5f,sbc_L_s12__RA_) },
+ { A5F_INSN_SBC_CCU6__RA_, SEM_FN_NAME (a5f,sbc_ccu6__RA_) },
+ { A5F_INSN_SBC_L_U6__RA_, SEM_FN_NAME (a5f,sbc_L_u6__RA_) },
+ { A5F_INSN_SBC_L_R_R__RA__RC, SEM_FN_NAME (a5f,sbc_L_r_r__RA__RC) },
+ { A5F_INSN_SBC_CC__RA__RC, SEM_FN_NAME (a5f,sbc_cc__RA__RC) },
+ { A5F_INSN_AND_L_S12__RA_, SEM_FN_NAME (a5f,and_L_s12__RA_) },
+ { A5F_INSN_AND_CCU6__RA_, SEM_FN_NAME (a5f,and_ccu6__RA_) },
+ { A5F_INSN_AND_L_U6__RA_, SEM_FN_NAME (a5f,and_L_u6__RA_) },
+ { A5F_INSN_AND_L_R_R__RA__RC, SEM_FN_NAME (a5f,and_L_r_r__RA__RC) },
+ { A5F_INSN_AND_CC__RA__RC, SEM_FN_NAME (a5f,and_cc__RA__RC) },
+ { A5F_INSN_I16_GO_AND_S_GO, SEM_FN_NAME (a5f,I16_GO_AND_s_go) },
+ { A5F_INSN_OR_L_S12__RA_, SEM_FN_NAME (a5f,or_L_s12__RA_) },
+ { A5F_INSN_OR_CCU6__RA_, SEM_FN_NAME (a5f,or_ccu6__RA_) },
+ { A5F_INSN_OR_L_U6__RA_, SEM_FN_NAME (a5f,or_L_u6__RA_) },
+ { A5F_INSN_OR_L_R_R__RA__RC, SEM_FN_NAME (a5f,or_L_r_r__RA__RC) },
+ { A5F_INSN_OR_CC__RA__RC, SEM_FN_NAME (a5f,or_cc__RA__RC) },
+ { A5F_INSN_I16_GO_OR_S_GO, SEM_FN_NAME (a5f,I16_GO_OR_s_go) },
+ { A5F_INSN_BIC_L_S12__RA_, SEM_FN_NAME (a5f,bic_L_s12__RA_) },
+ { A5F_INSN_BIC_CCU6__RA_, SEM_FN_NAME (a5f,bic_ccu6__RA_) },
+ { A5F_INSN_BIC_L_U6__RA_, SEM_FN_NAME (a5f,bic_L_u6__RA_) },
+ { A5F_INSN_BIC_L_R_R__RA__RC, SEM_FN_NAME (a5f,bic_L_r_r__RA__RC) },
+ { A5F_INSN_BIC_CC__RA__RC, SEM_FN_NAME (a5f,bic_cc__RA__RC) },
+ { A5F_INSN_I16_GO_BIC_S_GO, SEM_FN_NAME (a5f,I16_GO_BIC_s_go) },
+ { A5F_INSN_XOR_L_S12__RA_, SEM_FN_NAME (a5f,xor_L_s12__RA_) },
+ { A5F_INSN_XOR_CCU6__RA_, SEM_FN_NAME (a5f,xor_ccu6__RA_) },
+ { A5F_INSN_XOR_L_U6__RA_, SEM_FN_NAME (a5f,xor_L_u6__RA_) },
+ { A5F_INSN_XOR_L_R_R__RA__RC, SEM_FN_NAME (a5f,xor_L_r_r__RA__RC) },
+ { A5F_INSN_XOR_CC__RA__RC, SEM_FN_NAME (a5f,xor_cc__RA__RC) },
+ { A5F_INSN_I16_GO_XOR_S_GO, SEM_FN_NAME (a5f,I16_GO_XOR_s_go) },
+ { A5F_INSN_MAX_L_S12__RA_, SEM_FN_NAME (a5f,max_L_s12__RA_) },
+ { A5F_INSN_MAX_CCU6__RA_, SEM_FN_NAME (a5f,max_ccu6__RA_) },
+ { A5F_INSN_MAX_L_U6__RA_, SEM_FN_NAME (a5f,max_L_u6__RA_) },
+ { A5F_INSN_MAX_L_R_R__RA__RC, SEM_FN_NAME (a5f,max_L_r_r__RA__RC) },
+ { A5F_INSN_MAX_CC__RA__RC, SEM_FN_NAME (a5f,max_cc__RA__RC) },
+ { A5F_INSN_MIN_L_S12__RA_, SEM_FN_NAME (a5f,min_L_s12__RA_) },
+ { A5F_INSN_MIN_CCU6__RA_, SEM_FN_NAME (a5f,min_ccu6__RA_) },
+ { A5F_INSN_MIN_L_U6__RA_, SEM_FN_NAME (a5f,min_L_u6__RA_) },
+ { A5F_INSN_MIN_L_R_R__RA__RC, SEM_FN_NAME (a5f,min_L_r_r__RA__RC) },
+ { A5F_INSN_MIN_CC__RA__RC, SEM_FN_NAME (a5f,min_cc__RA__RC) },
+ { A5F_INSN_MOV_L_S12_, SEM_FN_NAME (a5f,mov_L_s12_) },
+ { A5F_INSN_MOV_CCU6_, SEM_FN_NAME (a5f,mov_ccu6_) },
+ { A5F_INSN_MOV_L_U6_, SEM_FN_NAME (a5f,mov_L_u6_) },
+ { A5F_INSN_MOV_L_R_R__RC, SEM_FN_NAME (a5f,mov_L_r_r__RC) },
+ { A5F_INSN_MOV_CC__RC, SEM_FN_NAME (a5f,mov_cc__RC) },
+ { A5F_INSN_MOV_S_MCAH, SEM_FN_NAME (a5f,mov_s_mcah) },
+ { A5F_INSN_MOV_S_MCAHB, SEM_FN_NAME (a5f,mov_s_mcahb) },
+ { A5F_INSN_MOV_S_R_U7, SEM_FN_NAME (a5f,mov_s_r_u7) },
+ { A5F_INSN_TST_L_S12_, SEM_FN_NAME (a5f,tst_L_s12_) },
+ { A5F_INSN_TST_CCU6_, SEM_FN_NAME (a5f,tst_ccu6_) },
+ { A5F_INSN_TST_L_U6_, SEM_FN_NAME (a5f,tst_L_u6_) },
+ { A5F_INSN_TST_L_R_R__RC, SEM_FN_NAME (a5f,tst_L_r_r__RC) },
+ { A5F_INSN_TST_CC__RC, SEM_FN_NAME (a5f,tst_cc__RC) },
+ { A5F_INSN_TST_S_GO, SEM_FN_NAME (a5f,tst_s_go) },
+ { A5F_INSN_CMP_L_S12_, SEM_FN_NAME (a5f,cmp_L_s12_) },
+ { A5F_INSN_CMP_CCU6_, SEM_FN_NAME (a5f,cmp_ccu6_) },
+ { A5F_INSN_CMP_L_U6_, SEM_FN_NAME (a5f,cmp_L_u6_) },
+ { A5F_INSN_CMP_L_R_R__RC, SEM_FN_NAME (a5f,cmp_L_r_r__RC) },
+ { A5F_INSN_CMP_CC__RC, SEM_FN_NAME (a5f,cmp_cc__RC) },
+ { A5F_INSN_CMP_S_MCAH, SEM_FN_NAME (a5f,cmp_s_mcah) },
+ { A5F_INSN_CMP_S_R_U7, SEM_FN_NAME (a5f,cmp_s_r_u7) },
+ { A5F_INSN_RCMP_L_S12_, SEM_FN_NAME (a5f,rcmp_L_s12_) },
+ { A5F_INSN_RCMP_CCU6_, SEM_FN_NAME (a5f,rcmp_ccu6_) },
+ { A5F_INSN_RCMP_L_U6_, SEM_FN_NAME (a5f,rcmp_L_u6_) },
+ { A5F_INSN_RCMP_L_R_R__RC, SEM_FN_NAME (a5f,rcmp_L_r_r__RC) },
+ { A5F_INSN_RCMP_CC__RC, SEM_FN_NAME (a5f,rcmp_cc__RC) },
+ { A5F_INSN_RSUB_L_S12__RA_, SEM_FN_NAME (a5f,rsub_L_s12__RA_) },
+ { A5F_INSN_RSUB_CCU6__RA_, SEM_FN_NAME (a5f,rsub_ccu6__RA_) },
+ { A5F_INSN_RSUB_L_U6__RA_, SEM_FN_NAME (a5f,rsub_L_u6__RA_) },
+ { A5F_INSN_RSUB_L_R_R__RA__RC, SEM_FN_NAME (a5f,rsub_L_r_r__RA__RC) },
+ { A5F_INSN_RSUB_CC__RA__RC, SEM_FN_NAME (a5f,rsub_cc__RA__RC) },
+ { A5F_INSN_BSET_L_S12__RA_, SEM_FN_NAME (a5f,bset_L_s12__RA_) },
+ { A5F_INSN_BSET_CCU6__RA_, SEM_FN_NAME (a5f,bset_ccu6__RA_) },
+ { A5F_INSN_BSET_L_U6__RA_, SEM_FN_NAME (a5f,bset_L_u6__RA_) },
+ { A5F_INSN_BSET_L_R_R__RA__RC, SEM_FN_NAME (a5f,bset_L_r_r__RA__RC) },
+ { A5F_INSN_BSET_CC__RA__RC, SEM_FN_NAME (a5f,bset_cc__RA__RC) },
+ { A5F_INSN_BSET_S_SSB, SEM_FN_NAME (a5f,bset_s_ssb) },
+ { A5F_INSN_BCLR_L_S12__RA_, SEM_FN_NAME (a5f,bclr_L_s12__RA_) },
+ { A5F_INSN_BCLR_CCU6__RA_, SEM_FN_NAME (a5f,bclr_ccu6__RA_) },
+ { A5F_INSN_BCLR_L_U6__RA_, SEM_FN_NAME (a5f,bclr_L_u6__RA_) },
+ { A5F_INSN_BCLR_L_R_R__RA__RC, SEM_FN_NAME (a5f,bclr_L_r_r__RA__RC) },
+ { A5F_INSN_BCLR_CC__RA__RC, SEM_FN_NAME (a5f,bclr_cc__RA__RC) },
+ { A5F_INSN_BCLR_S_SSB, SEM_FN_NAME (a5f,bclr_s_ssb) },
+ { A5F_INSN_BTST_L_S12_, SEM_FN_NAME (a5f,btst_L_s12_) },
+ { A5F_INSN_BTST_CCU6_, SEM_FN_NAME (a5f,btst_ccu6_) },
+ { A5F_INSN_BTST_L_U6_, SEM_FN_NAME (a5f,btst_L_u6_) },
+ { A5F_INSN_BTST_L_R_R__RC, SEM_FN_NAME (a5f,btst_L_r_r__RC) },
+ { A5F_INSN_BTST_CC__RC, SEM_FN_NAME (a5f,btst_cc__RC) },
+ { A5F_INSN_BTST_S_SSB, SEM_FN_NAME (a5f,btst_s_ssb) },
+ { A5F_INSN_BXOR_L_S12__RA_, SEM_FN_NAME (a5f,bxor_L_s12__RA_) },
+ { A5F_INSN_BXOR_CCU6__RA_, SEM_FN_NAME (a5f,bxor_ccu6__RA_) },
+ { A5F_INSN_BXOR_L_U6__RA_, SEM_FN_NAME (a5f,bxor_L_u6__RA_) },
+ { A5F_INSN_BXOR_L_R_R__RA__RC, SEM_FN_NAME (a5f,bxor_L_r_r__RA__RC) },
+ { A5F_INSN_BXOR_CC__RA__RC, SEM_FN_NAME (a5f,bxor_cc__RA__RC) },
+ { A5F_INSN_BMSK_L_S12__RA_, SEM_FN_NAME (a5f,bmsk_L_s12__RA_) },
+ { A5F_INSN_BMSK_CCU6__RA_, SEM_FN_NAME (a5f,bmsk_ccu6__RA_) },
+ { A5F_INSN_BMSK_L_U6__RA_, SEM_FN_NAME (a5f,bmsk_L_u6__RA_) },
+ { A5F_INSN_BMSK_L_R_R__RA__RC, SEM_FN_NAME (a5f,bmsk_L_r_r__RA__RC) },
+ { A5F_INSN_BMSK_CC__RA__RC, SEM_FN_NAME (a5f,bmsk_cc__RA__RC) },
+ { A5F_INSN_BMSK_S_SSB, SEM_FN_NAME (a5f,bmsk_s_ssb) },
+ { A5F_INSN_ADD1_L_S12__RA_, SEM_FN_NAME (a5f,add1_L_s12__RA_) },
+ { A5F_INSN_ADD1_CCU6__RA_, SEM_FN_NAME (a5f,add1_ccu6__RA_) },
+ { A5F_INSN_ADD1_L_U6__RA_, SEM_FN_NAME (a5f,add1_L_u6__RA_) },
+ { A5F_INSN_ADD1_L_R_R__RA__RC, SEM_FN_NAME (a5f,add1_L_r_r__RA__RC) },
+ { A5F_INSN_ADD1_CC__RA__RC, SEM_FN_NAME (a5f,add1_cc__RA__RC) },
+ { A5F_INSN_I16_GO_ADD1_S_GO, SEM_FN_NAME (a5f,I16_GO_ADD1_s_go) },
+ { A5F_INSN_ADD2_L_S12__RA_, SEM_FN_NAME (a5f,add2_L_s12__RA_) },
+ { A5F_INSN_ADD2_CCU6__RA_, SEM_FN_NAME (a5f,add2_ccu6__RA_) },
+ { A5F_INSN_ADD2_L_U6__RA_, SEM_FN_NAME (a5f,add2_L_u6__RA_) },
+ { A5F_INSN_ADD2_L_R_R__RA__RC, SEM_FN_NAME (a5f,add2_L_r_r__RA__RC) },
+ { A5F_INSN_ADD2_CC__RA__RC, SEM_FN_NAME (a5f,add2_cc__RA__RC) },
+ { A5F_INSN_I16_GO_ADD2_S_GO, SEM_FN_NAME (a5f,I16_GO_ADD2_s_go) },
+ { A5F_INSN_ADD3_L_S12__RA_, SEM_FN_NAME (a5f,add3_L_s12__RA_) },
+ { A5F_INSN_ADD3_CCU6__RA_, SEM_FN_NAME (a5f,add3_ccu6__RA_) },
+ { A5F_INSN_ADD3_L_U6__RA_, SEM_FN_NAME (a5f,add3_L_u6__RA_) },
+ { A5F_INSN_ADD3_L_R_R__RA__RC, SEM_FN_NAME (a5f,add3_L_r_r__RA__RC) },
+ { A5F_INSN_ADD3_CC__RA__RC, SEM_FN_NAME (a5f,add3_cc__RA__RC) },
+ { A5F_INSN_I16_GO_ADD3_S_GO, SEM_FN_NAME (a5f,I16_GO_ADD3_s_go) },
+ { A5F_INSN_SUB1_L_S12__RA_, SEM_FN_NAME (a5f,sub1_L_s12__RA_) },
+ { A5F_INSN_SUB1_CCU6__RA_, SEM_FN_NAME (a5f,sub1_ccu6__RA_) },
+ { A5F_INSN_SUB1_L_U6__RA_, SEM_FN_NAME (a5f,sub1_L_u6__RA_) },
+ { A5F_INSN_SUB1_L_R_R__RA__RC, SEM_FN_NAME (a5f,sub1_L_r_r__RA__RC) },
+ { A5F_INSN_SUB1_CC__RA__RC, SEM_FN_NAME (a5f,sub1_cc__RA__RC) },
+ { A5F_INSN_SUB2_L_S12__RA_, SEM_FN_NAME (a5f,sub2_L_s12__RA_) },
+ { A5F_INSN_SUB2_CCU6__RA_, SEM_FN_NAME (a5f,sub2_ccu6__RA_) },
+ { A5F_INSN_SUB2_L_U6__RA_, SEM_FN_NAME (a5f,sub2_L_u6__RA_) },
+ { A5F_INSN_SUB2_L_R_R__RA__RC, SEM_FN_NAME (a5f,sub2_L_r_r__RA__RC) },
+ { A5F_INSN_SUB2_CC__RA__RC, SEM_FN_NAME (a5f,sub2_cc__RA__RC) },
+ { A5F_INSN_SUB3_L_S12__RA_, SEM_FN_NAME (a5f,sub3_L_s12__RA_) },
+ { A5F_INSN_SUB3_CCU6__RA_, SEM_FN_NAME (a5f,sub3_ccu6__RA_) },
+ { A5F_INSN_SUB3_L_U6__RA_, SEM_FN_NAME (a5f,sub3_L_u6__RA_) },
+ { A5F_INSN_SUB3_L_R_R__RA__RC, SEM_FN_NAME (a5f,sub3_L_r_r__RA__RC) },
+ { A5F_INSN_SUB3_CC__RA__RC, SEM_FN_NAME (a5f,sub3_cc__RA__RC) },
+ { A5F_INSN_MPY_L_S12__RA_, SEM_FN_NAME (a5f,mpy_L_s12__RA_) },
+ { A5F_INSN_MPY_CCU6__RA_, SEM_FN_NAME (a5f,mpy_ccu6__RA_) },
+ { A5F_INSN_MPY_L_U6__RA_, SEM_FN_NAME (a5f,mpy_L_u6__RA_) },
+ { A5F_INSN_MPY_L_R_R__RA__RC, SEM_FN_NAME (a5f,mpy_L_r_r__RA__RC) },
+ { A5F_INSN_MPY_CC__RA__RC, SEM_FN_NAME (a5f,mpy_cc__RA__RC) },
+ { A5F_INSN_MPYH_L_S12__RA_, SEM_FN_NAME (a5f,mpyh_L_s12__RA_) },
+ { A5F_INSN_MPYH_CCU6__RA_, SEM_FN_NAME (a5f,mpyh_ccu6__RA_) },
+ { A5F_INSN_MPYH_L_U6__RA_, SEM_FN_NAME (a5f,mpyh_L_u6__RA_) },
+ { A5F_INSN_MPYH_L_R_R__RA__RC, SEM_FN_NAME (a5f,mpyh_L_r_r__RA__RC) },
+ { A5F_INSN_MPYH_CC__RA__RC, SEM_FN_NAME (a5f,mpyh_cc__RA__RC) },
+ { A5F_INSN_MPYHU_L_S12__RA_, SEM_FN_NAME (a5f,mpyhu_L_s12__RA_) },
+ { A5F_INSN_MPYHU_CCU6__RA_, SEM_FN_NAME (a5f,mpyhu_ccu6__RA_) },
+ { A5F_INSN_MPYHU_L_U6__RA_, SEM_FN_NAME (a5f,mpyhu_L_u6__RA_) },
+ { A5F_INSN_MPYHU_L_R_R__RA__RC, SEM_FN_NAME (a5f,mpyhu_L_r_r__RA__RC) },
+ { A5F_INSN_MPYHU_CC__RA__RC, SEM_FN_NAME (a5f,mpyhu_cc__RA__RC) },
+ { A5F_INSN_MPYU_L_S12__RA_, SEM_FN_NAME (a5f,mpyu_L_s12__RA_) },
+ { A5F_INSN_MPYU_CCU6__RA_, SEM_FN_NAME (a5f,mpyu_ccu6__RA_) },
+ { A5F_INSN_MPYU_L_U6__RA_, SEM_FN_NAME (a5f,mpyu_L_u6__RA_) },
+ { A5F_INSN_MPYU_L_R_R__RA__RC, SEM_FN_NAME (a5f,mpyu_L_r_r__RA__RC) },
+ { A5F_INSN_MPYU_CC__RA__RC, SEM_FN_NAME (a5f,mpyu_cc__RA__RC) },
+ { A5F_INSN_J_L_R_R___RC_NOILINK_, SEM_FN_NAME (a5f,j_L_r_r___RC_noilink_) },
+ { A5F_INSN_J_CC___RC_NOILINK_, SEM_FN_NAME (a5f,j_cc___RC_noilink_) },
+ { A5F_INSN_J_L_R_R___RC_ILINK_, SEM_FN_NAME (a5f,j_L_r_r___RC_ilink_) },
+ { A5F_INSN_J_CC___RC_ILINK_, SEM_FN_NAME (a5f,j_cc___RC_ilink_) },
+ { A5F_INSN_J_L_S12_, SEM_FN_NAME (a5f,j_L_s12_) },
+ { A5F_INSN_J_CCU6_, SEM_FN_NAME (a5f,j_ccu6_) },
+ { A5F_INSN_J_L_U6_, SEM_FN_NAME (a5f,j_L_u6_) },
+ { A5F_INSN_J_S, SEM_FN_NAME (a5f,j_s) },
+ { A5F_INSN_J_S__S, SEM_FN_NAME (a5f,j_s__S) },
+ { A5F_INSN_J_SEQ__S, SEM_FN_NAME (a5f,j_seq__S) },
+ { A5F_INSN_J_SNE__S, SEM_FN_NAME (a5f,j_sne__S) },
+ { A5F_INSN_J_L_S12_D_, SEM_FN_NAME (a5f,j_L_s12_d_) },
+ { A5F_INSN_J_CCU6_D_, SEM_FN_NAME (a5f,j_ccu6_d_) },
+ { A5F_INSN_J_L_U6_D_, SEM_FN_NAME (a5f,j_L_u6_d_) },
+ { A5F_INSN_J_L_R_R_D___RC_, SEM_FN_NAME (a5f,j_L_r_r_d___RC_) },
+ { A5F_INSN_J_CC_D___RC_, SEM_FN_NAME (a5f,j_cc_d___RC_) },
+ { A5F_INSN_J_S_D, SEM_FN_NAME (a5f,j_s_d) },
+ { A5F_INSN_J_S__S_D, SEM_FN_NAME (a5f,j_s__S_d) },
+ { A5F_INSN_JL_L_S12_, SEM_FN_NAME (a5f,jl_L_s12_) },
+ { A5F_INSN_JL_CCU6_, SEM_FN_NAME (a5f,jl_ccu6_) },
+ { A5F_INSN_JL_L_U6_, SEM_FN_NAME (a5f,jl_L_u6_) },
+ { A5F_INSN_JL_S, SEM_FN_NAME (a5f,jl_s) },
+ { A5F_INSN_JL_L_R_R___RC_NOILINK_, SEM_FN_NAME (a5f,jl_L_r_r___RC_noilink_) },
+ { A5F_INSN_JL_CC___RC_NOILINK_, SEM_FN_NAME (a5f,jl_cc___RC_noilink_) },
+ { A5F_INSN_JL_L_S12_D_, SEM_FN_NAME (a5f,jl_L_s12_d_) },
+ { A5F_INSN_JL_CCU6_D_, SEM_FN_NAME (a5f,jl_ccu6_d_) },
+ { A5F_INSN_JL_L_U6_D_, SEM_FN_NAME (a5f,jl_L_u6_d_) },
+ { A5F_INSN_JL_L_R_R_D___RC_, SEM_FN_NAME (a5f,jl_L_r_r_d___RC_) },
+ { A5F_INSN_JL_CC_D___RC_, SEM_FN_NAME (a5f,jl_cc_d___RC_) },
+ { A5F_INSN_JL_S_D, SEM_FN_NAME (a5f,jl_s_d) },
+ { A5F_INSN_LP_L_S12_, SEM_FN_NAME (a5f,lp_L_s12_) },
+ { A5F_INSN_LPCC_CCU6, SEM_FN_NAME (a5f,lpcc_ccu6) },
+ { A5F_INSN_FLAG_L_S12_, SEM_FN_NAME (a5f,flag_L_s12_) },
+ { A5F_INSN_FLAG_CCU6_, SEM_FN_NAME (a5f,flag_ccu6_) },
+ { A5F_INSN_FLAG_L_U6_, SEM_FN_NAME (a5f,flag_L_u6_) },
+ { A5F_INSN_FLAG_L_R_R__RC, SEM_FN_NAME (a5f,flag_L_r_r__RC) },
+ { A5F_INSN_FLAG_CC__RC, SEM_FN_NAME (a5f,flag_cc__RC) },
+ { A5F_INSN_LR_L_R_R___RC_, SEM_FN_NAME (a5f,lr_L_r_r___RC_) },
+ { A5F_INSN_LR_L_S12_, SEM_FN_NAME (a5f,lr_L_s12_) },
+ { A5F_INSN_LR_L_U6_, SEM_FN_NAME (a5f,lr_L_u6_) },
+ { A5F_INSN_SR_L_R_R___RC_, SEM_FN_NAME (a5f,sr_L_r_r___RC_) },
+ { A5F_INSN_SR_L_S12_, SEM_FN_NAME (a5f,sr_L_s12_) },
+ { A5F_INSN_SR_L_U6_, SEM_FN_NAME (a5f,sr_L_u6_) },
+ { A5F_INSN_ASL_L_R_R__RC, SEM_FN_NAME (a5f,asl_L_r_r__RC) },
+ { A5F_INSN_ASL_L_U6_, SEM_FN_NAME (a5f,asl_L_u6_) },
+ { A5F_INSN_I16_GO_ASL_S_GO, SEM_FN_NAME (a5f,I16_GO_ASL_s_go) },
+ { A5F_INSN_ASR_L_R_R__RC, SEM_FN_NAME (a5f,asr_L_r_r__RC) },
+ { A5F_INSN_ASR_L_U6_, SEM_FN_NAME (a5f,asr_L_u6_) },
+ { A5F_INSN_I16_GO_ASR_S_GO, SEM_FN_NAME (a5f,I16_GO_ASR_s_go) },
+ { A5F_INSN_LSR_L_R_R__RC, SEM_FN_NAME (a5f,lsr_L_r_r__RC) },
+ { A5F_INSN_LSR_L_U6_, SEM_FN_NAME (a5f,lsr_L_u6_) },
+ { A5F_INSN_I16_GO_LSR_S_GO, SEM_FN_NAME (a5f,I16_GO_LSR_s_go) },
+ { A5F_INSN_ROR_L_R_R__RC, SEM_FN_NAME (a5f,ror_L_r_r__RC) },
+ { A5F_INSN_ROR_L_U6_, SEM_FN_NAME (a5f,ror_L_u6_) },
+ { A5F_INSN_RRC_L_R_R__RC, SEM_FN_NAME (a5f,rrc_L_r_r__RC) },
+ { A5F_INSN_RRC_L_U6_, SEM_FN_NAME (a5f,rrc_L_u6_) },
+ { A5F_INSN_SEXB_L_R_R__RC, SEM_FN_NAME (a5f,sexb_L_r_r__RC) },
+ { A5F_INSN_SEXB_L_U6_, SEM_FN_NAME (a5f,sexb_L_u6_) },
+ { A5F_INSN_I16_GO_SEXB_S_GO, SEM_FN_NAME (a5f,I16_GO_SEXB_s_go) },
+ { A5F_INSN_SEXW_L_R_R__RC, SEM_FN_NAME (a5f,sexw_L_r_r__RC) },
+ { A5F_INSN_SEXW_L_U6_, SEM_FN_NAME (a5f,sexw_L_u6_) },
+ { A5F_INSN_I16_GO_SEXW_S_GO, SEM_FN_NAME (a5f,I16_GO_SEXW_s_go) },
+ { A5F_INSN_EXTB_L_R_R__RC, SEM_FN_NAME (a5f,extb_L_r_r__RC) },
+ { A5F_INSN_EXTB_L_U6_, SEM_FN_NAME (a5f,extb_L_u6_) },
+ { A5F_INSN_I16_GO_EXTB_S_GO, SEM_FN_NAME (a5f,I16_GO_EXTB_s_go) },
+ { A5F_INSN_EXTW_L_R_R__RC, SEM_FN_NAME (a5f,extw_L_r_r__RC) },
+ { A5F_INSN_EXTW_L_U6_, SEM_FN_NAME (a5f,extw_L_u6_) },
+ { A5F_INSN_I16_GO_EXTW_S_GO, SEM_FN_NAME (a5f,I16_GO_EXTW_s_go) },
+ { A5F_INSN_ABS_L_R_R__RC, SEM_FN_NAME (a5f,abs_L_r_r__RC) },
+ { A5F_INSN_ABS_L_U6_, SEM_FN_NAME (a5f,abs_L_u6_) },
+ { A5F_INSN_I16_GO_ABS_S_GO, SEM_FN_NAME (a5f,I16_GO_ABS_s_go) },
+ { A5F_INSN_NOT_L_R_R__RC, SEM_FN_NAME (a5f,not_L_r_r__RC) },
+ { A5F_INSN_NOT_L_U6_, SEM_FN_NAME (a5f,not_L_u6_) },
+ { A5F_INSN_I16_GO_NOT_S_GO, SEM_FN_NAME (a5f,I16_GO_NOT_s_go) },
+ { A5F_INSN_RLC_L_R_R__RC, SEM_FN_NAME (a5f,rlc_L_r_r__RC) },
+ { A5F_INSN_RLC_L_U6_, SEM_FN_NAME (a5f,rlc_L_u6_) },
+ { A5F_INSN_I16_GO_NEG_S_GO, SEM_FN_NAME (a5f,I16_GO_NEG_s_go) },
+ { A5F_INSN_SWI, SEM_FN_NAME (a5f,swi) },
+ { A5F_INSN_TRAP_S, SEM_FN_NAME (a5f,trap_s) },
+ { A5F_INSN_BRK, SEM_FN_NAME (a5f,brk) },
+ { A5F_INSN_BRK_S, SEM_FN_NAME (a5f,brk_s) },
+ { A5F_INSN_ASL_L_S12__RA_, SEM_FN_NAME (a5f,asl_L_s12__RA_) },
+ { A5F_INSN_ASL_CCU6__RA_, SEM_FN_NAME (a5f,asl_ccu6__RA_) },
+ { A5F_INSN_ASL_L_U6__RA_, SEM_FN_NAME (a5f,asl_L_u6__RA_) },
+ { A5F_INSN_ASL_L_R_R__RA__RC, SEM_FN_NAME (a5f,asl_L_r_r__RA__RC) },
+ { A5F_INSN_ASL_CC__RA__RC, SEM_FN_NAME (a5f,asl_cc__RA__RC) },
+ { A5F_INSN_ASL_S_CBU3, SEM_FN_NAME (a5f,asl_s_cbu3) },
+ { A5F_INSN_ASL_S_SSB, SEM_FN_NAME (a5f,asl_s_ssb) },
+ { A5F_INSN_I16_GO_ASLM_S_GO, SEM_FN_NAME (a5f,I16_GO_ASLM_s_go) },
+ { A5F_INSN_LSR_L_S12__RA_, SEM_FN_NAME (a5f,lsr_L_s12__RA_) },
+ { A5F_INSN_LSR_CCU6__RA_, SEM_FN_NAME (a5f,lsr_ccu6__RA_) },
+ { A5F_INSN_LSR_L_U6__RA_, SEM_FN_NAME (a5f,lsr_L_u6__RA_) },
+ { A5F_INSN_LSR_L_R_R__RA__RC, SEM_FN_NAME (a5f,lsr_L_r_r__RA__RC) },
+ { A5F_INSN_LSR_CC__RA__RC, SEM_FN_NAME (a5f,lsr_cc__RA__RC) },
+ { A5F_INSN_LSR_S_SSB, SEM_FN_NAME (a5f,lsr_s_ssb) },
+ { A5F_INSN_I16_GO_LSRM_S_GO, SEM_FN_NAME (a5f,I16_GO_LSRM_s_go) },
+ { A5F_INSN_ASR_L_S12__RA_, SEM_FN_NAME (a5f,asr_L_s12__RA_) },
+ { A5F_INSN_ASR_CCU6__RA_, SEM_FN_NAME (a5f,asr_ccu6__RA_) },
+ { A5F_INSN_ASR_L_U6__RA_, SEM_FN_NAME (a5f,asr_L_u6__RA_) },
+ { A5F_INSN_ASR_L_R_R__RA__RC, SEM_FN_NAME (a5f,asr_L_r_r__RA__RC) },
+ { A5F_INSN_ASR_CC__RA__RC, SEM_FN_NAME (a5f,asr_cc__RA__RC) },
+ { A5F_INSN_ASR_S_CBU3, SEM_FN_NAME (a5f,asr_s_cbu3) },
+ { A5F_INSN_ASR_S_SSB, SEM_FN_NAME (a5f,asr_s_ssb) },
+ { A5F_INSN_I16_GO_ASRM_S_GO, SEM_FN_NAME (a5f,I16_GO_ASRM_s_go) },
+ { A5F_INSN_ROR_L_S12__RA_, SEM_FN_NAME (a5f,ror_L_s12__RA_) },
+ { A5F_INSN_ROR_CCU6__RA_, SEM_FN_NAME (a5f,ror_ccu6__RA_) },
+ { A5F_INSN_ROR_L_U6__RA_, SEM_FN_NAME (a5f,ror_L_u6__RA_) },
+ { A5F_INSN_ROR_L_R_R__RA__RC, SEM_FN_NAME (a5f,ror_L_r_r__RA__RC) },
+ { A5F_INSN_ROR_CC__RA__RC, SEM_FN_NAME (a5f,ror_cc__RA__RC) },
+ { A5F_INSN_MUL64_L_S12_, SEM_FN_NAME (a5f,mul64_L_s12_) },
+ { A5F_INSN_MUL64_CCU6_, SEM_FN_NAME (a5f,mul64_ccu6_) },
+ { A5F_INSN_MUL64_L_U6_, SEM_FN_NAME (a5f,mul64_L_u6_) },
+ { A5F_INSN_MUL64_L_R_R__RC, SEM_FN_NAME (a5f,mul64_L_r_r__RC) },
+ { A5F_INSN_MUL64_CC__RC, SEM_FN_NAME (a5f,mul64_cc__RC) },
+ { A5F_INSN_MUL64_S_GO, SEM_FN_NAME (a5f,mul64_s_go) },
+ { A5F_INSN_MULU64_L_S12_, SEM_FN_NAME (a5f,mulu64_L_s12_) },
+ { A5F_INSN_MULU64_CCU6_, SEM_FN_NAME (a5f,mulu64_ccu6_) },
+ { A5F_INSN_MULU64_L_U6_, SEM_FN_NAME (a5f,mulu64_L_u6_) },
+ { A5F_INSN_MULU64_L_R_R__RC, SEM_FN_NAME (a5f,mulu64_L_r_r__RC) },
+ { A5F_INSN_MULU64_CC__RC, SEM_FN_NAME (a5f,mulu64_cc__RC) },
+ { A5F_INSN_ADDS_L_S12__RA_, SEM_FN_NAME (a5f,adds_L_s12__RA_) },
+ { A5F_INSN_ADDS_CCU6__RA_, SEM_FN_NAME (a5f,adds_ccu6__RA_) },
+ { A5F_INSN_ADDS_L_U6__RA_, SEM_FN_NAME (a5f,adds_L_u6__RA_) },
+ { A5F_INSN_ADDS_L_R_R__RA__RC, SEM_FN_NAME (a5f,adds_L_r_r__RA__RC) },
+ { A5F_INSN_ADDS_CC__RA__RC, SEM_FN_NAME (a5f,adds_cc__RA__RC) },
+ { A5F_INSN_SUBS_L_S12__RA_, SEM_FN_NAME (a5f,subs_L_s12__RA_) },
+ { A5F_INSN_SUBS_CCU6__RA_, SEM_FN_NAME (a5f,subs_ccu6__RA_) },
+ { A5F_INSN_SUBS_L_U6__RA_, SEM_FN_NAME (a5f,subs_L_u6__RA_) },
+ { A5F_INSN_SUBS_L_R_R__RA__RC, SEM_FN_NAME (a5f,subs_L_r_r__RA__RC) },
+ { A5F_INSN_SUBS_CC__RA__RC, SEM_FN_NAME (a5f,subs_cc__RA__RC) },
+ { A5F_INSN_DIVAW_L_S12__RA_, SEM_FN_NAME (a5f,divaw_L_s12__RA_) },
+ { A5F_INSN_DIVAW_CCU6__RA_, SEM_FN_NAME (a5f,divaw_ccu6__RA_) },
+ { A5F_INSN_DIVAW_L_U6__RA_, SEM_FN_NAME (a5f,divaw_L_u6__RA_) },
+ { A5F_INSN_DIVAW_L_R_R__RA__RC, SEM_FN_NAME (a5f,divaw_L_r_r__RA__RC) },
+ { A5F_INSN_DIVAW_CC__RA__RC, SEM_FN_NAME (a5f,divaw_cc__RA__RC) },
+ { A5F_INSN_ASLS_L_S12__RA_, SEM_FN_NAME (a5f,asls_L_s12__RA_) },
+ { A5F_INSN_ASLS_CCU6__RA_, SEM_FN_NAME (a5f,asls_ccu6__RA_) },
+ { A5F_INSN_ASLS_L_U6__RA_, SEM_FN_NAME (a5f,asls_L_u6__RA_) },
+ { A5F_INSN_ASLS_L_R_R__RA__RC, SEM_FN_NAME (a5f,asls_L_r_r__RA__RC) },
+ { A5F_INSN_ASLS_CC__RA__RC, SEM_FN_NAME (a5f,asls_cc__RA__RC) },
+ { A5F_INSN_ASRS_L_S12__RA_, SEM_FN_NAME (a5f,asrs_L_s12__RA_) },
+ { A5F_INSN_ASRS_CCU6__RA_, SEM_FN_NAME (a5f,asrs_ccu6__RA_) },
+ { A5F_INSN_ASRS_L_U6__RA_, SEM_FN_NAME (a5f,asrs_L_u6__RA_) },
+ { A5F_INSN_ASRS_L_R_R__RA__RC, SEM_FN_NAME (a5f,asrs_L_r_r__RA__RC) },
+ { A5F_INSN_ASRS_CC__RA__RC, SEM_FN_NAME (a5f,asrs_cc__RA__RC) },
+ { A5F_INSN_ADDSDW_L_S12__RA_, SEM_FN_NAME (a5f,addsdw_L_s12__RA_) },
+ { A5F_INSN_ADDSDW_CCU6__RA_, SEM_FN_NAME (a5f,addsdw_ccu6__RA_) },
+ { A5F_INSN_ADDSDW_L_U6__RA_, SEM_FN_NAME (a5f,addsdw_L_u6__RA_) },
+ { A5F_INSN_ADDSDW_L_R_R__RA__RC, SEM_FN_NAME (a5f,addsdw_L_r_r__RA__RC) },
+ { A5F_INSN_ADDSDW_CC__RA__RC, SEM_FN_NAME (a5f,addsdw_cc__RA__RC) },
+ { A5F_INSN_SUBSDW_L_S12__RA_, SEM_FN_NAME (a5f,subsdw_L_s12__RA_) },
+ { A5F_INSN_SUBSDW_CCU6__RA_, SEM_FN_NAME (a5f,subsdw_ccu6__RA_) },
+ { A5F_INSN_SUBSDW_L_U6__RA_, SEM_FN_NAME (a5f,subsdw_L_u6__RA_) },
+ { A5F_INSN_SUBSDW_L_R_R__RA__RC, SEM_FN_NAME (a5f,subsdw_L_r_r__RA__RC) },
+ { A5F_INSN_SUBSDW_CC__RA__RC, SEM_FN_NAME (a5f,subsdw_cc__RA__RC) },
+ { A5F_INSN_SWAP_L_R_R__RC, SEM_FN_NAME (a5f,swap_L_r_r__RC) },
+ { A5F_INSN_SWAP_L_U6_, SEM_FN_NAME (a5f,swap_L_u6_) },
+ { A5F_INSN_NORM_L_R_R__RC, SEM_FN_NAME (a5f,norm_L_r_r__RC) },
+ { A5F_INSN_NORM_L_U6_, SEM_FN_NAME (a5f,norm_L_u6_) },
+ { A5F_INSN_RND16_L_R_R__RC, SEM_FN_NAME (a5f,rnd16_L_r_r__RC) },
+ { A5F_INSN_RND16_L_U6_, SEM_FN_NAME (a5f,rnd16_L_u6_) },
+ { A5F_INSN_ABSSW_L_R_R__RC, SEM_FN_NAME (a5f,abssw_L_r_r__RC) },
+ { A5F_INSN_ABSSW_L_U6_, SEM_FN_NAME (a5f,abssw_L_u6_) },
+ { A5F_INSN_ABSS_L_R_R__RC, SEM_FN_NAME (a5f,abss_L_r_r__RC) },
+ { A5F_INSN_ABSS_L_U6_, SEM_FN_NAME (a5f,abss_L_u6_) },
+ { A5F_INSN_NEGSW_L_R_R__RC, SEM_FN_NAME (a5f,negsw_L_r_r__RC) },
+ { A5F_INSN_NEGSW_L_U6_, SEM_FN_NAME (a5f,negsw_L_u6_) },
+ { A5F_INSN_NEGS_L_R_R__RC, SEM_FN_NAME (a5f,negs_L_r_r__RC) },
+ { A5F_INSN_NEGS_L_U6_, SEM_FN_NAME (a5f,negs_L_u6_) },
+ { A5F_INSN_NORMW_L_R_R__RC, SEM_FN_NAME (a5f,normw_L_r_r__RC) },
+ { A5F_INSN_NORMW_L_U6_, SEM_FN_NAME (a5f,normw_L_u6_) },
+ { A5F_INSN_NOP_S, SEM_FN_NAME (a5f,nop_s) },
+ { A5F_INSN_UNIMP_S, SEM_FN_NAME (a5f,unimp_s) },
+ { A5F_INSN_POP_S_B, SEM_FN_NAME (a5f,pop_s_b) },
+ { A5F_INSN_POP_S_BLINK, SEM_FN_NAME (a5f,pop_s_blink) },
+ { A5F_INSN_PUSH_S_B, SEM_FN_NAME (a5f,push_s_b) },
+ { A5F_INSN_PUSH_S_BLINK, SEM_FN_NAME (a5f,push_s_blink) },
+ { A5F_INSN_MULLW_L_S12__RA_, SEM_FN_NAME (a5f,mullw_L_s12__RA_) },
+ { A5F_INSN_MULLW_CCU6__RA_, SEM_FN_NAME (a5f,mullw_ccu6__RA_) },
+ { A5F_INSN_MULLW_L_U6__RA_, SEM_FN_NAME (a5f,mullw_L_u6__RA_) },
+ { A5F_INSN_MULLW_L_R_R__RA__RC, SEM_FN_NAME (a5f,mullw_L_r_r__RA__RC) },
+ { A5F_INSN_MULLW_CC__RA__RC, SEM_FN_NAME (a5f,mullw_cc__RA__RC) },
+ { A5F_INSN_MACLW_L_S12__RA_, SEM_FN_NAME (a5f,maclw_L_s12__RA_) },
+ { A5F_INSN_MACLW_CCU6__RA_, SEM_FN_NAME (a5f,maclw_ccu6__RA_) },
+ { A5F_INSN_MACLW_L_U6__RA_, SEM_FN_NAME (a5f,maclw_L_u6__RA_) },
+ { A5F_INSN_MACLW_L_R_R__RA__RC, SEM_FN_NAME (a5f,maclw_L_r_r__RA__RC) },
+ { A5F_INSN_MACLW_CC__RA__RC, SEM_FN_NAME (a5f,maclw_cc__RA__RC) },
+ { A5F_INSN_MACHLW_L_S12__RA_, SEM_FN_NAME (a5f,machlw_L_s12__RA_) },
+ { A5F_INSN_MACHLW_CCU6__RA_, SEM_FN_NAME (a5f,machlw_ccu6__RA_) },
+ { A5F_INSN_MACHLW_L_U6__RA_, SEM_FN_NAME (a5f,machlw_L_u6__RA_) },
+ { A5F_INSN_MACHLW_L_R_R__RA__RC, SEM_FN_NAME (a5f,machlw_L_r_r__RA__RC) },
+ { A5F_INSN_MACHLW_CC__RA__RC, SEM_FN_NAME (a5f,machlw_cc__RA__RC) },
+ { A5F_INSN_MULULW_L_S12__RA_, SEM_FN_NAME (a5f,mululw_L_s12__RA_) },
+ { A5F_INSN_MULULW_CCU6__RA_, SEM_FN_NAME (a5f,mululw_ccu6__RA_) },
+ { A5F_INSN_MULULW_L_U6__RA_, SEM_FN_NAME (a5f,mululw_L_u6__RA_) },
+ { A5F_INSN_MULULW_L_R_R__RA__RC, SEM_FN_NAME (a5f,mululw_L_r_r__RA__RC) },
+ { A5F_INSN_MULULW_CC__RA__RC, SEM_FN_NAME (a5f,mululw_cc__RA__RC) },
+ { A5F_INSN_MACHULW_L_S12__RA_, SEM_FN_NAME (a5f,machulw_L_s12__RA_) },
+ { A5F_INSN_MACHULW_CCU6__RA_, SEM_FN_NAME (a5f,machulw_ccu6__RA_) },
+ { A5F_INSN_MACHULW_L_U6__RA_, SEM_FN_NAME (a5f,machulw_L_u6__RA_) },
+ { A5F_INSN_MACHULW_L_R_R__RA__RC, SEM_FN_NAME (a5f,machulw_L_r_r__RA__RC) },
+ { A5F_INSN_MACHULW_CC__RA__RC, SEM_FN_NAME (a5f,machulw_cc__RA__RC) },
+ { A5F_INSN_CURRENT_LOOP_END, SEM_FN_NAME (a5f,current_loop_end) },
+ { A5F_INSN_CURRENT_LOOP_END_AFTER_BRANCH, SEM_FN_NAME (a5f,current_loop_end_after_branch) },
+ { A5F_INSN_ARC600_CURRENT_LOOP_END_AFTER_BRANCH, SEM_FN_NAME (a5f,arc600_current_loop_end_after_branch) },
+ { 0, 0 }
+};
+
+/* Add the semantic fns to IDESC_TABLE. */
+
+void
+SEM_FN_NAME (a5f,init_idesc_table) (SIM_CPU *current_cpu)
+{
+ IDESC *idesc_table = CPU_IDESC (current_cpu);
+ const struct sem_fn_desc *sf;
+ int mach_num = MACH_NUM (CPU_MACH (current_cpu));
+
+ for (sf = &sem_fns[0]; sf->fn != 0; ++sf)
+ {
+ const CGEN_INSN *insn = idesc_table[sf->index].idata;
+ int valid_p = (CGEN_INSN_VIRTUAL_P (insn)
+ || CGEN_INSN_MACH_HAS_P (insn, mach_num));
+#if FAST_P
+ if (valid_p)
+ idesc_table[sf->index].sem_fast = sf->fn;
+ else
+ idesc_table[sf->index].sem_fast = SEM_FN_NAME (a5f,x_invalid);
+#else
+ if (valid_p)
+ idesc_table[sf->index].sem_full = sf->fn;
+ else
+ idesc_table[sf->index].sem_full = SEM_FN_NAME (a5f,x_invalid);
+#endif
+ }
+}
+
diff --git a/sim/arc/sem6-switch.c b/sim/arc/sem6-switch.c
new file mode 100644
index 0000000..a03d7f4
--- /dev/null
+++ b/sim/arc/sem6-switch.c
@@ -0,0 +1,32975 @@
+/* Simulator instruction semantics for arc600f.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2007 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#ifdef DEFINE_LABELS
+
+ /* The labels have the case they have because the enum of insn types
+ is all uppercase and in the non-stdc case the insn symbol is built
+ into the enum name. */
+
+ static struct {
+ int index;
+ void *label;
+ } labels[] = {
+ { ARC600F_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
+ { ARC600F_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
+ { ARC600F_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
+ { ARC600F_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
+ { ARC600F_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
+ { ARC600F_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
+ { ARC600F_INSN_B_S, && case_sem_INSN_B_S },
+ { ARC600F_INSN_BCC_S, && case_sem_INSN_BCC_S },
+ { ARC600F_INSN_BRCC_S, && case_sem_INSN_BRCC_S },
+ { ARC600F_INSN_BCC_L, && case_sem_INSN_BCC_L },
+ { ARC600F_INSN_BCC_L_D, && case_sem_INSN_BCC_L_D },
+ { ARC600F_INSN_B_L, && case_sem_INSN_B_L },
+ { ARC600F_INSN_B_L_D, && case_sem_INSN_B_L_D },
+ { ARC600F_INSN_BRCC_RC, && case_sem_INSN_BRCC_RC },
+ { ARC600F_INSN_BRCC_RC_D, && case_sem_INSN_BRCC_RC_D },
+ { ARC600F_INSN_BRCC_U6, && case_sem_INSN_BRCC_U6 },
+ { ARC600F_INSN_BRCC_U6_D, && case_sem_INSN_BRCC_U6_D },
+ { ARC600F_INSN_BL_S, && case_sem_INSN_BL_S },
+ { ARC600F_INSN_BLCC, && case_sem_INSN_BLCC },
+ { ARC600F_INSN_BLCC_D, && case_sem_INSN_BLCC_D },
+ { ARC600F_INSN_BL, && case_sem_INSN_BL },
+ { ARC600F_INSN_BL_D, && case_sem_INSN_BL_D },
+ { ARC600F_INSN_LD_ABS, && case_sem_INSN_LD_ABS },
+ { ARC600F_INSN_LD__AW_ABS, && case_sem_INSN_LD__AW_ABS },
+ { ARC600F_INSN_LD_AB_ABS, && case_sem_INSN_LD_AB_ABS },
+ { ARC600F_INSN_LD_AS_ABS, && case_sem_INSN_LD_AS_ABS },
+ { ARC600F_INSN_LD_ABC, && case_sem_INSN_LD_ABC },
+ { ARC600F_INSN_LD__AW_ABC, && case_sem_INSN_LD__AW_ABC },
+ { ARC600F_INSN_LD_AB_ABC, && case_sem_INSN_LD_AB_ABC },
+ { ARC600F_INSN_LD_AS_ABC, && case_sem_INSN_LD_AS_ABC },
+ { ARC600F_INSN_LD_S_ABC, && case_sem_INSN_LD_S_ABC },
+ { ARC600F_INSN_LD_S_ABU, && case_sem_INSN_LD_S_ABU },
+ { ARC600F_INSN_LD_S_ABSP, && case_sem_INSN_LD_S_ABSP },
+ { ARC600F_INSN_LD_S_GPREL, && case_sem_INSN_LD_S_GPREL },
+ { ARC600F_INSN_LD_S_PCREL, && case_sem_INSN_LD_S_PCREL },
+ { ARC600F_INSN_LDB_ABS, && case_sem_INSN_LDB_ABS },
+ { ARC600F_INSN_LDB__AW_ABS, && case_sem_INSN_LDB__AW_ABS },
+ { ARC600F_INSN_LDB_AB_ABS, && case_sem_INSN_LDB_AB_ABS },
+ { ARC600F_INSN_LDB_AS_ABS, && case_sem_INSN_LDB_AS_ABS },
+ { ARC600F_INSN_LDB_ABC, && case_sem_INSN_LDB_ABC },
+ { ARC600F_INSN_LDB__AW_ABC, && case_sem_INSN_LDB__AW_ABC },
+ { ARC600F_INSN_LDB_AB_ABC, && case_sem_INSN_LDB_AB_ABC },
+ { ARC600F_INSN_LDB_AS_ABC, && case_sem_INSN_LDB_AS_ABC },
+ { ARC600F_INSN_LDB_S_ABC, && case_sem_INSN_LDB_S_ABC },
+ { ARC600F_INSN_LDB_S_ABU, && case_sem_INSN_LDB_S_ABU },
+ { ARC600F_INSN_LDB_S_ABSP, && case_sem_INSN_LDB_S_ABSP },
+ { ARC600F_INSN_LDB_S_GPREL, && case_sem_INSN_LDB_S_GPREL },
+ { ARC600F_INSN_LDB_X_ABS, && case_sem_INSN_LDB_X_ABS },
+ { ARC600F_INSN_LDB__AW_X_ABS, && case_sem_INSN_LDB__AW_X_ABS },
+ { ARC600F_INSN_LDB_AB_X_ABS, && case_sem_INSN_LDB_AB_X_ABS },
+ { ARC600F_INSN_LDB_AS_X_ABS, && case_sem_INSN_LDB_AS_X_ABS },
+ { ARC600F_INSN_LDB_X_ABC, && case_sem_INSN_LDB_X_ABC },
+ { ARC600F_INSN_LDB__AW_X_ABC, && case_sem_INSN_LDB__AW_X_ABC },
+ { ARC600F_INSN_LDB_AB_X_ABC, && case_sem_INSN_LDB_AB_X_ABC },
+ { ARC600F_INSN_LDB_AS_X_ABC, && case_sem_INSN_LDB_AS_X_ABC },
+ { ARC600F_INSN_LDW_ABS, && case_sem_INSN_LDW_ABS },
+ { ARC600F_INSN_LDW__AW_ABS, && case_sem_INSN_LDW__AW_ABS },
+ { ARC600F_INSN_LDW_AB_ABS, && case_sem_INSN_LDW_AB_ABS },
+ { ARC600F_INSN_LDW_AS_ABS, && case_sem_INSN_LDW_AS_ABS },
+ { ARC600F_INSN_LDW_ABC, && case_sem_INSN_LDW_ABC },
+ { ARC600F_INSN_LDW__AW_ABC, && case_sem_INSN_LDW__AW_ABC },
+ { ARC600F_INSN_LDW_AB_ABC, && case_sem_INSN_LDW_AB_ABC },
+ { ARC600F_INSN_LDW_AS_ABC, && case_sem_INSN_LDW_AS_ABC },
+ { ARC600F_INSN_LDW_S_ABC, && case_sem_INSN_LDW_S_ABC },
+ { ARC600F_INSN_LDW_S_ABU, && case_sem_INSN_LDW_S_ABU },
+ { ARC600F_INSN_LDW_S_GPREL, && case_sem_INSN_LDW_S_GPREL },
+ { ARC600F_INSN_LDW_X_ABS, && case_sem_INSN_LDW_X_ABS },
+ { ARC600F_INSN_LDW__AW_X_ABS, && case_sem_INSN_LDW__AW_X_ABS },
+ { ARC600F_INSN_LDW_AB_X_ABS, && case_sem_INSN_LDW_AB_X_ABS },
+ { ARC600F_INSN_LDW_AS_X_ABS, && case_sem_INSN_LDW_AS_X_ABS },
+ { ARC600F_INSN_LDW_X_ABC, && case_sem_INSN_LDW_X_ABC },
+ { ARC600F_INSN_LDW__AW_X_ABC, && case_sem_INSN_LDW__AW_X_ABC },
+ { ARC600F_INSN_LDW_AB_X_ABC, && case_sem_INSN_LDW_AB_X_ABC },
+ { ARC600F_INSN_LDW_AS_X_ABC, && case_sem_INSN_LDW_AS_X_ABC },
+ { ARC600F_INSN_LDW_S_X_ABU, && case_sem_INSN_LDW_S_X_ABU },
+ { ARC600F_INSN_ST_ABS, && case_sem_INSN_ST_ABS },
+ { ARC600F_INSN_ST__AW_ABS, && case_sem_INSN_ST__AW_ABS },
+ { ARC600F_INSN_ST_AB_ABS, && case_sem_INSN_ST_AB_ABS },
+ { ARC600F_INSN_ST_AS_ABS, && case_sem_INSN_ST_AS_ABS },
+ { ARC600F_INSN_ST_S_ABU, && case_sem_INSN_ST_S_ABU },
+ { ARC600F_INSN_ST_S_ABSP, && case_sem_INSN_ST_S_ABSP },
+ { ARC600F_INSN_STB_ABS, && case_sem_INSN_STB_ABS },
+ { ARC600F_INSN_STB__AW_ABS, && case_sem_INSN_STB__AW_ABS },
+ { ARC600F_INSN_STB_AB_ABS, && case_sem_INSN_STB_AB_ABS },
+ { ARC600F_INSN_STB_AS_ABS, && case_sem_INSN_STB_AS_ABS },
+ { ARC600F_INSN_STB_S_ABU, && case_sem_INSN_STB_S_ABU },
+ { ARC600F_INSN_STB_S_ABSP, && case_sem_INSN_STB_S_ABSP },
+ { ARC600F_INSN_STW_ABS, && case_sem_INSN_STW_ABS },
+ { ARC600F_INSN_STW__AW_ABS, && case_sem_INSN_STW__AW_ABS },
+ { ARC600F_INSN_STW_AB_ABS, && case_sem_INSN_STW_AB_ABS },
+ { ARC600F_INSN_STW_AS_ABS, && case_sem_INSN_STW_AS_ABS },
+ { ARC600F_INSN_STW_S_ABU, && case_sem_INSN_STW_S_ABU },
+ { ARC600F_INSN_ADD_L_S12__RA_, && case_sem_INSN_ADD_L_S12__RA_ },
+ { ARC600F_INSN_ADD_CCU6__RA_, && case_sem_INSN_ADD_CCU6__RA_ },
+ { ARC600F_INSN_ADD_L_U6__RA_, && case_sem_INSN_ADD_L_U6__RA_ },
+ { ARC600F_INSN_ADD_L_R_R__RA__RC, && case_sem_INSN_ADD_L_R_R__RA__RC },
+ { ARC600F_INSN_ADD_CC__RA__RC, && case_sem_INSN_ADD_CC__RA__RC },
+ { ARC600F_INSN_ADD_S_ABC, && case_sem_INSN_ADD_S_ABC },
+ { ARC600F_INSN_ADD_S_CBU3, && case_sem_INSN_ADD_S_CBU3 },
+ { ARC600F_INSN_ADD_S_MCAH, && case_sem_INSN_ADD_S_MCAH },
+ { ARC600F_INSN_ADD_S_ABSP, && case_sem_INSN_ADD_S_ABSP },
+ { ARC600F_INSN_ADD_S_ASSPSP, && case_sem_INSN_ADD_S_ASSPSP },
+ { ARC600F_INSN_ADD_S_GP, && case_sem_INSN_ADD_S_GP },
+ { ARC600F_INSN_ADD_S_R_U7, && case_sem_INSN_ADD_S_R_U7 },
+ { ARC600F_INSN_ADC_L_S12__RA_, && case_sem_INSN_ADC_L_S12__RA_ },
+ { ARC600F_INSN_ADC_CCU6__RA_, && case_sem_INSN_ADC_CCU6__RA_ },
+ { ARC600F_INSN_ADC_L_U6__RA_, && case_sem_INSN_ADC_L_U6__RA_ },
+ { ARC600F_INSN_ADC_L_R_R__RA__RC, && case_sem_INSN_ADC_L_R_R__RA__RC },
+ { ARC600F_INSN_ADC_CC__RA__RC, && case_sem_INSN_ADC_CC__RA__RC },
+ { ARC600F_INSN_SUB_L_S12__RA_, && case_sem_INSN_SUB_L_S12__RA_ },
+ { ARC600F_INSN_SUB_CCU6__RA_, && case_sem_INSN_SUB_CCU6__RA_ },
+ { ARC600F_INSN_SUB_L_U6__RA_, && case_sem_INSN_SUB_L_U6__RA_ },
+ { ARC600F_INSN_SUB_L_R_R__RA__RC, && case_sem_INSN_SUB_L_R_R__RA__RC },
+ { ARC600F_INSN_SUB_CC__RA__RC, && case_sem_INSN_SUB_CC__RA__RC },
+ { ARC600F_INSN_SUB_S_CBU3, && case_sem_INSN_SUB_S_CBU3 },
+ { ARC600F_INSN_I16_GO_SUB_S_GO, && case_sem_INSN_I16_GO_SUB_S_GO },
+ { ARC600F_INSN_SUB_S_GO_SUB_NE, && case_sem_INSN_SUB_S_GO_SUB_NE },
+ { ARC600F_INSN_SUB_S_SSB, && case_sem_INSN_SUB_S_SSB },
+ { ARC600F_INSN_SUB_S_ASSPSP, && case_sem_INSN_SUB_S_ASSPSP },
+ { ARC600F_INSN_SBC_L_S12__RA_, && case_sem_INSN_SBC_L_S12__RA_ },
+ { ARC600F_INSN_SBC_CCU6__RA_, && case_sem_INSN_SBC_CCU6__RA_ },
+ { ARC600F_INSN_SBC_L_U6__RA_, && case_sem_INSN_SBC_L_U6__RA_ },
+ { ARC600F_INSN_SBC_L_R_R__RA__RC, && case_sem_INSN_SBC_L_R_R__RA__RC },
+ { ARC600F_INSN_SBC_CC__RA__RC, && case_sem_INSN_SBC_CC__RA__RC },
+ { ARC600F_INSN_AND_L_S12__RA_, && case_sem_INSN_AND_L_S12__RA_ },
+ { ARC600F_INSN_AND_CCU6__RA_, && case_sem_INSN_AND_CCU6__RA_ },
+ { ARC600F_INSN_AND_L_U6__RA_, && case_sem_INSN_AND_L_U6__RA_ },
+ { ARC600F_INSN_AND_L_R_R__RA__RC, && case_sem_INSN_AND_L_R_R__RA__RC },
+ { ARC600F_INSN_AND_CC__RA__RC, && case_sem_INSN_AND_CC__RA__RC },
+ { ARC600F_INSN_I16_GO_AND_S_GO, && case_sem_INSN_I16_GO_AND_S_GO },
+ { ARC600F_INSN_OR_L_S12__RA_, && case_sem_INSN_OR_L_S12__RA_ },
+ { ARC600F_INSN_OR_CCU6__RA_, && case_sem_INSN_OR_CCU6__RA_ },
+ { ARC600F_INSN_OR_L_U6__RA_, && case_sem_INSN_OR_L_U6__RA_ },
+ { ARC600F_INSN_OR_L_R_R__RA__RC, && case_sem_INSN_OR_L_R_R__RA__RC },
+ { ARC600F_INSN_OR_CC__RA__RC, && case_sem_INSN_OR_CC__RA__RC },
+ { ARC600F_INSN_I16_GO_OR_S_GO, && case_sem_INSN_I16_GO_OR_S_GO },
+ { ARC600F_INSN_BIC_L_S12__RA_, && case_sem_INSN_BIC_L_S12__RA_ },
+ { ARC600F_INSN_BIC_CCU6__RA_, && case_sem_INSN_BIC_CCU6__RA_ },
+ { ARC600F_INSN_BIC_L_U6__RA_, && case_sem_INSN_BIC_L_U6__RA_ },
+ { ARC600F_INSN_BIC_L_R_R__RA__RC, && case_sem_INSN_BIC_L_R_R__RA__RC },
+ { ARC600F_INSN_BIC_CC__RA__RC, && case_sem_INSN_BIC_CC__RA__RC },
+ { ARC600F_INSN_I16_GO_BIC_S_GO, && case_sem_INSN_I16_GO_BIC_S_GO },
+ { ARC600F_INSN_XOR_L_S12__RA_, && case_sem_INSN_XOR_L_S12__RA_ },
+ { ARC600F_INSN_XOR_CCU6__RA_, && case_sem_INSN_XOR_CCU6__RA_ },
+ { ARC600F_INSN_XOR_L_U6__RA_, && case_sem_INSN_XOR_L_U6__RA_ },
+ { ARC600F_INSN_XOR_L_R_R__RA__RC, && case_sem_INSN_XOR_L_R_R__RA__RC },
+ { ARC600F_INSN_XOR_CC__RA__RC, && case_sem_INSN_XOR_CC__RA__RC },
+ { ARC600F_INSN_I16_GO_XOR_S_GO, && case_sem_INSN_I16_GO_XOR_S_GO },
+ { ARC600F_INSN_MAX_L_S12__RA_, && case_sem_INSN_MAX_L_S12__RA_ },
+ { ARC600F_INSN_MAX_CCU6__RA_, && case_sem_INSN_MAX_CCU6__RA_ },
+ { ARC600F_INSN_MAX_L_U6__RA_, && case_sem_INSN_MAX_L_U6__RA_ },
+ { ARC600F_INSN_MAX_L_R_R__RA__RC, && case_sem_INSN_MAX_L_R_R__RA__RC },
+ { ARC600F_INSN_MAX_CC__RA__RC, && case_sem_INSN_MAX_CC__RA__RC },
+ { ARC600F_INSN_MIN_L_S12__RA_, && case_sem_INSN_MIN_L_S12__RA_ },
+ { ARC600F_INSN_MIN_CCU6__RA_, && case_sem_INSN_MIN_CCU6__RA_ },
+ { ARC600F_INSN_MIN_L_U6__RA_, && case_sem_INSN_MIN_L_U6__RA_ },
+ { ARC600F_INSN_MIN_L_R_R__RA__RC, && case_sem_INSN_MIN_L_R_R__RA__RC },
+ { ARC600F_INSN_MIN_CC__RA__RC, && case_sem_INSN_MIN_CC__RA__RC },
+ { ARC600F_INSN_MOV_L_S12_, && case_sem_INSN_MOV_L_S12_ },
+ { ARC600F_INSN_MOV_CCU6_, && case_sem_INSN_MOV_CCU6_ },
+ { ARC600F_INSN_MOV_L_U6_, && case_sem_INSN_MOV_L_U6_ },
+ { ARC600F_INSN_MOV_L_R_R__RC, && case_sem_INSN_MOV_L_R_R__RC },
+ { ARC600F_INSN_MOV_CC__RC, && case_sem_INSN_MOV_CC__RC },
+ { ARC600F_INSN_MOV_S_MCAH, && case_sem_INSN_MOV_S_MCAH },
+ { ARC600F_INSN_MOV_S_MCAHB, && case_sem_INSN_MOV_S_MCAHB },
+ { ARC600F_INSN_MOV_S_R_U7, && case_sem_INSN_MOV_S_R_U7 },
+ { ARC600F_INSN_TST_L_S12_, && case_sem_INSN_TST_L_S12_ },
+ { ARC600F_INSN_TST_CCU6_, && case_sem_INSN_TST_CCU6_ },
+ { ARC600F_INSN_TST_L_U6_, && case_sem_INSN_TST_L_U6_ },
+ { ARC600F_INSN_TST_L_R_R__RC, && case_sem_INSN_TST_L_R_R__RC },
+ { ARC600F_INSN_TST_CC__RC, && case_sem_INSN_TST_CC__RC },
+ { ARC600F_INSN_TST_S_GO, && case_sem_INSN_TST_S_GO },
+ { ARC600F_INSN_CMP_L_S12_, && case_sem_INSN_CMP_L_S12_ },
+ { ARC600F_INSN_CMP_CCU6_, && case_sem_INSN_CMP_CCU6_ },
+ { ARC600F_INSN_CMP_L_U6_, && case_sem_INSN_CMP_L_U6_ },
+ { ARC600F_INSN_CMP_L_R_R__RC, && case_sem_INSN_CMP_L_R_R__RC },
+ { ARC600F_INSN_CMP_CC__RC, && case_sem_INSN_CMP_CC__RC },
+ { ARC600F_INSN_CMP_S_MCAH, && case_sem_INSN_CMP_S_MCAH },
+ { ARC600F_INSN_CMP_S_R_U7, && case_sem_INSN_CMP_S_R_U7 },
+ { ARC600F_INSN_RCMP_L_S12_, && case_sem_INSN_RCMP_L_S12_ },
+ { ARC600F_INSN_RCMP_CCU6_, && case_sem_INSN_RCMP_CCU6_ },
+ { ARC600F_INSN_RCMP_L_U6_, && case_sem_INSN_RCMP_L_U6_ },
+ { ARC600F_INSN_RCMP_L_R_R__RC, && case_sem_INSN_RCMP_L_R_R__RC },
+ { ARC600F_INSN_RCMP_CC__RC, && case_sem_INSN_RCMP_CC__RC },
+ { ARC600F_INSN_RSUB_L_S12__RA_, && case_sem_INSN_RSUB_L_S12__RA_ },
+ { ARC600F_INSN_RSUB_CCU6__RA_, && case_sem_INSN_RSUB_CCU6__RA_ },
+ { ARC600F_INSN_RSUB_L_U6__RA_, && case_sem_INSN_RSUB_L_U6__RA_ },
+ { ARC600F_INSN_RSUB_L_R_R__RA__RC, && case_sem_INSN_RSUB_L_R_R__RA__RC },
+ { ARC600F_INSN_RSUB_CC__RA__RC, && case_sem_INSN_RSUB_CC__RA__RC },
+ { ARC600F_INSN_BSET_L_S12__RA_, && case_sem_INSN_BSET_L_S12__RA_ },
+ { ARC600F_INSN_BSET_CCU6__RA_, && case_sem_INSN_BSET_CCU6__RA_ },
+ { ARC600F_INSN_BSET_L_U6__RA_, && case_sem_INSN_BSET_L_U6__RA_ },
+ { ARC600F_INSN_BSET_L_R_R__RA__RC, && case_sem_INSN_BSET_L_R_R__RA__RC },
+ { ARC600F_INSN_BSET_CC__RA__RC, && case_sem_INSN_BSET_CC__RA__RC },
+ { ARC600F_INSN_BSET_S_SSB, && case_sem_INSN_BSET_S_SSB },
+ { ARC600F_INSN_BCLR_L_S12__RA_, && case_sem_INSN_BCLR_L_S12__RA_ },
+ { ARC600F_INSN_BCLR_CCU6__RA_, && case_sem_INSN_BCLR_CCU6__RA_ },
+ { ARC600F_INSN_BCLR_L_U6__RA_, && case_sem_INSN_BCLR_L_U6__RA_ },
+ { ARC600F_INSN_BCLR_L_R_R__RA__RC, && case_sem_INSN_BCLR_L_R_R__RA__RC },
+ { ARC600F_INSN_BCLR_CC__RA__RC, && case_sem_INSN_BCLR_CC__RA__RC },
+ { ARC600F_INSN_BCLR_S_SSB, && case_sem_INSN_BCLR_S_SSB },
+ { ARC600F_INSN_BTST_L_S12_, && case_sem_INSN_BTST_L_S12_ },
+ { ARC600F_INSN_BTST_CCU6_, && case_sem_INSN_BTST_CCU6_ },
+ { ARC600F_INSN_BTST_L_U6_, && case_sem_INSN_BTST_L_U6_ },
+ { ARC600F_INSN_BTST_L_R_R__RC, && case_sem_INSN_BTST_L_R_R__RC },
+ { ARC600F_INSN_BTST_CC__RC, && case_sem_INSN_BTST_CC__RC },
+ { ARC600F_INSN_BTST_S_SSB, && case_sem_INSN_BTST_S_SSB },
+ { ARC600F_INSN_BXOR_L_S12__RA_, && case_sem_INSN_BXOR_L_S12__RA_ },
+ { ARC600F_INSN_BXOR_CCU6__RA_, && case_sem_INSN_BXOR_CCU6__RA_ },
+ { ARC600F_INSN_BXOR_L_U6__RA_, && case_sem_INSN_BXOR_L_U6__RA_ },
+ { ARC600F_INSN_BXOR_L_R_R__RA__RC, && case_sem_INSN_BXOR_L_R_R__RA__RC },
+ { ARC600F_INSN_BXOR_CC__RA__RC, && case_sem_INSN_BXOR_CC__RA__RC },
+ { ARC600F_INSN_BMSK_L_S12__RA_, && case_sem_INSN_BMSK_L_S12__RA_ },
+ { ARC600F_INSN_BMSK_CCU6__RA_, && case_sem_INSN_BMSK_CCU6__RA_ },
+ { ARC600F_INSN_BMSK_L_U6__RA_, && case_sem_INSN_BMSK_L_U6__RA_ },
+ { ARC600F_INSN_BMSK_L_R_R__RA__RC, && case_sem_INSN_BMSK_L_R_R__RA__RC },
+ { ARC600F_INSN_BMSK_CC__RA__RC, && case_sem_INSN_BMSK_CC__RA__RC },
+ { ARC600F_INSN_BMSK_S_SSB, && case_sem_INSN_BMSK_S_SSB },
+ { ARC600F_INSN_ADD1_L_S12__RA_, && case_sem_INSN_ADD1_L_S12__RA_ },
+ { ARC600F_INSN_ADD1_CCU6__RA_, && case_sem_INSN_ADD1_CCU6__RA_ },
+ { ARC600F_INSN_ADD1_L_U6__RA_, && case_sem_INSN_ADD1_L_U6__RA_ },
+ { ARC600F_INSN_ADD1_L_R_R__RA__RC, && case_sem_INSN_ADD1_L_R_R__RA__RC },
+ { ARC600F_INSN_ADD1_CC__RA__RC, && case_sem_INSN_ADD1_CC__RA__RC },
+ { ARC600F_INSN_I16_GO_ADD1_S_GO, && case_sem_INSN_I16_GO_ADD1_S_GO },
+ { ARC600F_INSN_ADD2_L_S12__RA_, && case_sem_INSN_ADD2_L_S12__RA_ },
+ { ARC600F_INSN_ADD2_CCU6__RA_, && case_sem_INSN_ADD2_CCU6__RA_ },
+ { ARC600F_INSN_ADD2_L_U6__RA_, && case_sem_INSN_ADD2_L_U6__RA_ },
+ { ARC600F_INSN_ADD2_L_R_R__RA__RC, && case_sem_INSN_ADD2_L_R_R__RA__RC },
+ { ARC600F_INSN_ADD2_CC__RA__RC, && case_sem_INSN_ADD2_CC__RA__RC },
+ { ARC600F_INSN_I16_GO_ADD2_S_GO, && case_sem_INSN_I16_GO_ADD2_S_GO },
+ { ARC600F_INSN_ADD3_L_S12__RA_, && case_sem_INSN_ADD3_L_S12__RA_ },
+ { ARC600F_INSN_ADD3_CCU6__RA_, && case_sem_INSN_ADD3_CCU6__RA_ },
+ { ARC600F_INSN_ADD3_L_U6__RA_, && case_sem_INSN_ADD3_L_U6__RA_ },
+ { ARC600F_INSN_ADD3_L_R_R__RA__RC, && case_sem_INSN_ADD3_L_R_R__RA__RC },
+ { ARC600F_INSN_ADD3_CC__RA__RC, && case_sem_INSN_ADD3_CC__RA__RC },
+ { ARC600F_INSN_I16_GO_ADD3_S_GO, && case_sem_INSN_I16_GO_ADD3_S_GO },
+ { ARC600F_INSN_SUB1_L_S12__RA_, && case_sem_INSN_SUB1_L_S12__RA_ },
+ { ARC600F_INSN_SUB1_CCU6__RA_, && case_sem_INSN_SUB1_CCU6__RA_ },
+ { ARC600F_INSN_SUB1_L_U6__RA_, && case_sem_INSN_SUB1_L_U6__RA_ },
+ { ARC600F_INSN_SUB1_L_R_R__RA__RC, && case_sem_INSN_SUB1_L_R_R__RA__RC },
+ { ARC600F_INSN_SUB1_CC__RA__RC, && case_sem_INSN_SUB1_CC__RA__RC },
+ { ARC600F_INSN_SUB2_L_S12__RA_, && case_sem_INSN_SUB2_L_S12__RA_ },
+ { ARC600F_INSN_SUB2_CCU6__RA_, && case_sem_INSN_SUB2_CCU6__RA_ },
+ { ARC600F_INSN_SUB2_L_U6__RA_, && case_sem_INSN_SUB2_L_U6__RA_ },
+ { ARC600F_INSN_SUB2_L_R_R__RA__RC, && case_sem_INSN_SUB2_L_R_R__RA__RC },
+ { ARC600F_INSN_SUB2_CC__RA__RC, && case_sem_INSN_SUB2_CC__RA__RC },
+ { ARC600F_INSN_SUB3_L_S12__RA_, && case_sem_INSN_SUB3_L_S12__RA_ },
+ { ARC600F_INSN_SUB3_CCU6__RA_, && case_sem_INSN_SUB3_CCU6__RA_ },
+ { ARC600F_INSN_SUB3_L_U6__RA_, && case_sem_INSN_SUB3_L_U6__RA_ },
+ { ARC600F_INSN_SUB3_L_R_R__RA__RC, && case_sem_INSN_SUB3_L_R_R__RA__RC },
+ { ARC600F_INSN_SUB3_CC__RA__RC, && case_sem_INSN_SUB3_CC__RA__RC },
+ { ARC600F_INSN_MPY_L_S12__RA_, && case_sem_INSN_MPY_L_S12__RA_ },
+ { ARC600F_INSN_MPY_CCU6__RA_, && case_sem_INSN_MPY_CCU6__RA_ },
+ { ARC600F_INSN_MPY_L_U6__RA_, && case_sem_INSN_MPY_L_U6__RA_ },
+ { ARC600F_INSN_MPY_L_R_R__RA__RC, && case_sem_INSN_MPY_L_R_R__RA__RC },
+ { ARC600F_INSN_MPY_CC__RA__RC, && case_sem_INSN_MPY_CC__RA__RC },
+ { ARC600F_INSN_MPYH_L_S12__RA_, && case_sem_INSN_MPYH_L_S12__RA_ },
+ { ARC600F_INSN_MPYH_CCU6__RA_, && case_sem_INSN_MPYH_CCU6__RA_ },
+ { ARC600F_INSN_MPYH_L_U6__RA_, && case_sem_INSN_MPYH_L_U6__RA_ },
+ { ARC600F_INSN_MPYH_L_R_R__RA__RC, && case_sem_INSN_MPYH_L_R_R__RA__RC },
+ { ARC600F_INSN_MPYH_CC__RA__RC, && case_sem_INSN_MPYH_CC__RA__RC },
+ { ARC600F_INSN_MPYHU_L_S12__RA_, && case_sem_INSN_MPYHU_L_S12__RA_ },
+ { ARC600F_INSN_MPYHU_CCU6__RA_, && case_sem_INSN_MPYHU_CCU6__RA_ },
+ { ARC600F_INSN_MPYHU_L_U6__RA_, && case_sem_INSN_MPYHU_L_U6__RA_ },
+ { ARC600F_INSN_MPYHU_L_R_R__RA__RC, && case_sem_INSN_MPYHU_L_R_R__RA__RC },
+ { ARC600F_INSN_MPYHU_CC__RA__RC, && case_sem_INSN_MPYHU_CC__RA__RC },
+ { ARC600F_INSN_MPYU_L_S12__RA_, && case_sem_INSN_MPYU_L_S12__RA_ },
+ { ARC600F_INSN_MPYU_CCU6__RA_, && case_sem_INSN_MPYU_CCU6__RA_ },
+ { ARC600F_INSN_MPYU_L_U6__RA_, && case_sem_INSN_MPYU_L_U6__RA_ },
+ { ARC600F_INSN_MPYU_L_R_R__RA__RC, && case_sem_INSN_MPYU_L_R_R__RA__RC },
+ { ARC600F_INSN_MPYU_CC__RA__RC, && case_sem_INSN_MPYU_CC__RA__RC },
+ { ARC600F_INSN_J_L_R_R___RC_NOILINK_, && case_sem_INSN_J_L_R_R___RC_NOILINK_ },
+ { ARC600F_INSN_J_CC___RC_NOILINK_, && case_sem_INSN_J_CC___RC_NOILINK_ },
+ { ARC600F_INSN_J_L_R_R___RC_ILINK_, && case_sem_INSN_J_L_R_R___RC_ILINK_ },
+ { ARC600F_INSN_J_CC___RC_ILINK_, && case_sem_INSN_J_CC___RC_ILINK_ },
+ { ARC600F_INSN_J_L_S12_, && case_sem_INSN_J_L_S12_ },
+ { ARC600F_INSN_J_CCU6_, && case_sem_INSN_J_CCU6_ },
+ { ARC600F_INSN_J_L_U6_, && case_sem_INSN_J_L_U6_ },
+ { ARC600F_INSN_J_S, && case_sem_INSN_J_S },
+ { ARC600F_INSN_J_S__S, && case_sem_INSN_J_S__S },
+ { ARC600F_INSN_J_SEQ__S, && case_sem_INSN_J_SEQ__S },
+ { ARC600F_INSN_J_SNE__S, && case_sem_INSN_J_SNE__S },
+ { ARC600F_INSN_J_L_S12_D_, && case_sem_INSN_J_L_S12_D_ },
+ { ARC600F_INSN_J_CCU6_D_, && case_sem_INSN_J_CCU6_D_ },
+ { ARC600F_INSN_J_L_U6_D_, && case_sem_INSN_J_L_U6_D_ },
+ { ARC600F_INSN_J_L_R_R_D___RC_, && case_sem_INSN_J_L_R_R_D___RC_ },
+ { ARC600F_INSN_J_CC_D___RC_, && case_sem_INSN_J_CC_D___RC_ },
+ { ARC600F_INSN_J_S_D, && case_sem_INSN_J_S_D },
+ { ARC600F_INSN_J_S__S_D, && case_sem_INSN_J_S__S_D },
+ { ARC600F_INSN_JL_L_S12_, && case_sem_INSN_JL_L_S12_ },
+ { ARC600F_INSN_JL_CCU6_, && case_sem_INSN_JL_CCU6_ },
+ { ARC600F_INSN_JL_L_U6_, && case_sem_INSN_JL_L_U6_ },
+ { ARC600F_INSN_JL_S, && case_sem_INSN_JL_S },
+ { ARC600F_INSN_JL_L_R_R___RC_NOILINK_, && case_sem_INSN_JL_L_R_R___RC_NOILINK_ },
+ { ARC600F_INSN_JL_CC___RC_NOILINK_, && case_sem_INSN_JL_CC___RC_NOILINK_ },
+ { ARC600F_INSN_JL_L_S12_D_, && case_sem_INSN_JL_L_S12_D_ },
+ { ARC600F_INSN_JL_CCU6_D_, && case_sem_INSN_JL_CCU6_D_ },
+ { ARC600F_INSN_JL_L_U6_D_, && case_sem_INSN_JL_L_U6_D_ },
+ { ARC600F_INSN_JL_L_R_R_D___RC_, && case_sem_INSN_JL_L_R_R_D___RC_ },
+ { ARC600F_INSN_JL_CC_D___RC_, && case_sem_INSN_JL_CC_D___RC_ },
+ { ARC600F_INSN_JL_S_D, && case_sem_INSN_JL_S_D },
+ { ARC600F_INSN_LP_L_S12_, && case_sem_INSN_LP_L_S12_ },
+ { ARC600F_INSN_LPCC_CCU6, && case_sem_INSN_LPCC_CCU6 },
+ { ARC600F_INSN_FLAG_L_S12_, && case_sem_INSN_FLAG_L_S12_ },
+ { ARC600F_INSN_FLAG_CCU6_, && case_sem_INSN_FLAG_CCU6_ },
+ { ARC600F_INSN_FLAG_L_U6_, && case_sem_INSN_FLAG_L_U6_ },
+ { ARC600F_INSN_FLAG_L_R_R__RC, && case_sem_INSN_FLAG_L_R_R__RC },
+ { ARC600F_INSN_FLAG_CC__RC, && case_sem_INSN_FLAG_CC__RC },
+ { ARC600F_INSN_LR_L_R_R___RC_, && case_sem_INSN_LR_L_R_R___RC_ },
+ { ARC600F_INSN_LR_L_S12_, && case_sem_INSN_LR_L_S12_ },
+ { ARC600F_INSN_LR_L_U6_, && case_sem_INSN_LR_L_U6_ },
+ { ARC600F_INSN_SR_L_R_R___RC_, && case_sem_INSN_SR_L_R_R___RC_ },
+ { ARC600F_INSN_SR_L_S12_, && case_sem_INSN_SR_L_S12_ },
+ { ARC600F_INSN_SR_L_U6_, && case_sem_INSN_SR_L_U6_ },
+ { ARC600F_INSN_ASL_L_R_R__RC, && case_sem_INSN_ASL_L_R_R__RC },
+ { ARC600F_INSN_ASL_L_U6_, && case_sem_INSN_ASL_L_U6_ },
+ { ARC600F_INSN_I16_GO_ASL_S_GO, && case_sem_INSN_I16_GO_ASL_S_GO },
+ { ARC600F_INSN_ASR_L_R_R__RC, && case_sem_INSN_ASR_L_R_R__RC },
+ { ARC600F_INSN_ASR_L_U6_, && case_sem_INSN_ASR_L_U6_ },
+ { ARC600F_INSN_I16_GO_ASR_S_GO, && case_sem_INSN_I16_GO_ASR_S_GO },
+ { ARC600F_INSN_LSR_L_R_R__RC, && case_sem_INSN_LSR_L_R_R__RC },
+ { ARC600F_INSN_LSR_L_U6_, && case_sem_INSN_LSR_L_U6_ },
+ { ARC600F_INSN_I16_GO_LSR_S_GO, && case_sem_INSN_I16_GO_LSR_S_GO },
+ { ARC600F_INSN_ROR_L_R_R__RC, && case_sem_INSN_ROR_L_R_R__RC },
+ { ARC600F_INSN_ROR_L_U6_, && case_sem_INSN_ROR_L_U6_ },
+ { ARC600F_INSN_RRC_L_R_R__RC, && case_sem_INSN_RRC_L_R_R__RC },
+ { ARC600F_INSN_RRC_L_U6_, && case_sem_INSN_RRC_L_U6_ },
+ { ARC600F_INSN_SEXB_L_R_R__RC, && case_sem_INSN_SEXB_L_R_R__RC },
+ { ARC600F_INSN_SEXB_L_U6_, && case_sem_INSN_SEXB_L_U6_ },
+ { ARC600F_INSN_I16_GO_SEXB_S_GO, && case_sem_INSN_I16_GO_SEXB_S_GO },
+ { ARC600F_INSN_SEXW_L_R_R__RC, && case_sem_INSN_SEXW_L_R_R__RC },
+ { ARC600F_INSN_SEXW_L_U6_, && case_sem_INSN_SEXW_L_U6_ },
+ { ARC600F_INSN_I16_GO_SEXW_S_GO, && case_sem_INSN_I16_GO_SEXW_S_GO },
+ { ARC600F_INSN_EXTB_L_R_R__RC, && case_sem_INSN_EXTB_L_R_R__RC },
+ { ARC600F_INSN_EXTB_L_U6_, && case_sem_INSN_EXTB_L_U6_ },
+ { ARC600F_INSN_I16_GO_EXTB_S_GO, && case_sem_INSN_I16_GO_EXTB_S_GO },
+ { ARC600F_INSN_EXTW_L_R_R__RC, && case_sem_INSN_EXTW_L_R_R__RC },
+ { ARC600F_INSN_EXTW_L_U6_, && case_sem_INSN_EXTW_L_U6_ },
+ { ARC600F_INSN_I16_GO_EXTW_S_GO, && case_sem_INSN_I16_GO_EXTW_S_GO },
+ { ARC600F_INSN_ABS_L_R_R__RC, && case_sem_INSN_ABS_L_R_R__RC },
+ { ARC600F_INSN_ABS_L_U6_, && case_sem_INSN_ABS_L_U6_ },
+ { ARC600F_INSN_I16_GO_ABS_S_GO, && case_sem_INSN_I16_GO_ABS_S_GO },
+ { ARC600F_INSN_NOT_L_R_R__RC, && case_sem_INSN_NOT_L_R_R__RC },
+ { ARC600F_INSN_NOT_L_U6_, && case_sem_INSN_NOT_L_U6_ },
+ { ARC600F_INSN_I16_GO_NOT_S_GO, && case_sem_INSN_I16_GO_NOT_S_GO },
+ { ARC600F_INSN_RLC_L_R_R__RC, && case_sem_INSN_RLC_L_R_R__RC },
+ { ARC600F_INSN_RLC_L_U6_, && case_sem_INSN_RLC_L_U6_ },
+ { ARC600F_INSN_I16_GO_NEG_S_GO, && case_sem_INSN_I16_GO_NEG_S_GO },
+ { ARC600F_INSN_SWI, && case_sem_INSN_SWI },
+ { ARC600F_INSN_TRAP_S, && case_sem_INSN_TRAP_S },
+ { ARC600F_INSN_BRK, && case_sem_INSN_BRK },
+ { ARC600F_INSN_BRK_S, && case_sem_INSN_BRK_S },
+ { ARC600F_INSN_ASL_L_S12__RA_, && case_sem_INSN_ASL_L_S12__RA_ },
+ { ARC600F_INSN_ASL_CCU6__RA_, && case_sem_INSN_ASL_CCU6__RA_ },
+ { ARC600F_INSN_ASL_L_U6__RA_, && case_sem_INSN_ASL_L_U6__RA_ },
+ { ARC600F_INSN_ASL_L_R_R__RA__RC, && case_sem_INSN_ASL_L_R_R__RA__RC },
+ { ARC600F_INSN_ASL_CC__RA__RC, && case_sem_INSN_ASL_CC__RA__RC },
+ { ARC600F_INSN_ASL_S_CBU3, && case_sem_INSN_ASL_S_CBU3 },
+ { ARC600F_INSN_ASL_S_SSB, && case_sem_INSN_ASL_S_SSB },
+ { ARC600F_INSN_I16_GO_ASLM_S_GO, && case_sem_INSN_I16_GO_ASLM_S_GO },
+ { ARC600F_INSN_LSR_L_S12__RA_, && case_sem_INSN_LSR_L_S12__RA_ },
+ { ARC600F_INSN_LSR_CCU6__RA_, && case_sem_INSN_LSR_CCU6__RA_ },
+ { ARC600F_INSN_LSR_L_U6__RA_, && case_sem_INSN_LSR_L_U6__RA_ },
+ { ARC600F_INSN_LSR_L_R_R__RA__RC, && case_sem_INSN_LSR_L_R_R__RA__RC },
+ { ARC600F_INSN_LSR_CC__RA__RC, && case_sem_INSN_LSR_CC__RA__RC },
+ { ARC600F_INSN_LSR_S_SSB, && case_sem_INSN_LSR_S_SSB },
+ { ARC600F_INSN_I16_GO_LSRM_S_GO, && case_sem_INSN_I16_GO_LSRM_S_GO },
+ { ARC600F_INSN_ASR_L_S12__RA_, && case_sem_INSN_ASR_L_S12__RA_ },
+ { ARC600F_INSN_ASR_CCU6__RA_, && case_sem_INSN_ASR_CCU6__RA_ },
+ { ARC600F_INSN_ASR_L_U6__RA_, && case_sem_INSN_ASR_L_U6__RA_ },
+ { ARC600F_INSN_ASR_L_R_R__RA__RC, && case_sem_INSN_ASR_L_R_R__RA__RC },
+ { ARC600F_INSN_ASR_CC__RA__RC, && case_sem_INSN_ASR_CC__RA__RC },
+ { ARC600F_INSN_ASR_S_CBU3, && case_sem_INSN_ASR_S_CBU3 },
+ { ARC600F_INSN_ASR_S_SSB, && case_sem_INSN_ASR_S_SSB },
+ { ARC600F_INSN_I16_GO_ASRM_S_GO, && case_sem_INSN_I16_GO_ASRM_S_GO },
+ { ARC600F_INSN_ROR_L_S12__RA_, && case_sem_INSN_ROR_L_S12__RA_ },
+ { ARC600F_INSN_ROR_CCU6__RA_, && case_sem_INSN_ROR_CCU6__RA_ },
+ { ARC600F_INSN_ROR_L_U6__RA_, && case_sem_INSN_ROR_L_U6__RA_ },
+ { ARC600F_INSN_ROR_L_R_R__RA__RC, && case_sem_INSN_ROR_L_R_R__RA__RC },
+ { ARC600F_INSN_ROR_CC__RA__RC, && case_sem_INSN_ROR_CC__RA__RC },
+ { ARC600F_INSN_MUL64_L_S12_, && case_sem_INSN_MUL64_L_S12_ },
+ { ARC600F_INSN_MUL64_CCU6_, && case_sem_INSN_MUL64_CCU6_ },
+ { ARC600F_INSN_MUL64_L_U6_, && case_sem_INSN_MUL64_L_U6_ },
+ { ARC600F_INSN_MUL64_L_R_R__RC, && case_sem_INSN_MUL64_L_R_R__RC },
+ { ARC600F_INSN_MUL64_CC__RC, && case_sem_INSN_MUL64_CC__RC },
+ { ARC600F_INSN_MUL64_S_GO, && case_sem_INSN_MUL64_S_GO },
+ { ARC600F_INSN_MULU64_L_S12_, && case_sem_INSN_MULU64_L_S12_ },
+ { ARC600F_INSN_MULU64_CCU6_, && case_sem_INSN_MULU64_CCU6_ },
+ { ARC600F_INSN_MULU64_L_U6_, && case_sem_INSN_MULU64_L_U6_ },
+ { ARC600F_INSN_MULU64_L_R_R__RC, && case_sem_INSN_MULU64_L_R_R__RC },
+ { ARC600F_INSN_MULU64_CC__RC, && case_sem_INSN_MULU64_CC__RC },
+ { ARC600F_INSN_ADDS_L_S12__RA_, && case_sem_INSN_ADDS_L_S12__RA_ },
+ { ARC600F_INSN_ADDS_CCU6__RA_, && case_sem_INSN_ADDS_CCU6__RA_ },
+ { ARC600F_INSN_ADDS_L_U6__RA_, && case_sem_INSN_ADDS_L_U6__RA_ },
+ { ARC600F_INSN_ADDS_L_R_R__RA__RC, && case_sem_INSN_ADDS_L_R_R__RA__RC },
+ { ARC600F_INSN_ADDS_CC__RA__RC, && case_sem_INSN_ADDS_CC__RA__RC },
+ { ARC600F_INSN_SUBS_L_S12__RA_, && case_sem_INSN_SUBS_L_S12__RA_ },
+ { ARC600F_INSN_SUBS_CCU6__RA_, && case_sem_INSN_SUBS_CCU6__RA_ },
+ { ARC600F_INSN_SUBS_L_U6__RA_, && case_sem_INSN_SUBS_L_U6__RA_ },
+ { ARC600F_INSN_SUBS_L_R_R__RA__RC, && case_sem_INSN_SUBS_L_R_R__RA__RC },
+ { ARC600F_INSN_SUBS_CC__RA__RC, && case_sem_INSN_SUBS_CC__RA__RC },
+ { ARC600F_INSN_DIVAW_L_S12__RA_, && case_sem_INSN_DIVAW_L_S12__RA_ },
+ { ARC600F_INSN_DIVAW_CCU6__RA_, && case_sem_INSN_DIVAW_CCU6__RA_ },
+ { ARC600F_INSN_DIVAW_L_U6__RA_, && case_sem_INSN_DIVAW_L_U6__RA_ },
+ { ARC600F_INSN_DIVAW_L_R_R__RA__RC, && case_sem_INSN_DIVAW_L_R_R__RA__RC },
+ { ARC600F_INSN_DIVAW_CC__RA__RC, && case_sem_INSN_DIVAW_CC__RA__RC },
+ { ARC600F_INSN_ASLS_L_S12__RA_, && case_sem_INSN_ASLS_L_S12__RA_ },
+ { ARC600F_INSN_ASLS_CCU6__RA_, && case_sem_INSN_ASLS_CCU6__RA_ },
+ { ARC600F_INSN_ASLS_L_U6__RA_, && case_sem_INSN_ASLS_L_U6__RA_ },
+ { ARC600F_INSN_ASLS_L_R_R__RA__RC, && case_sem_INSN_ASLS_L_R_R__RA__RC },
+ { ARC600F_INSN_ASLS_CC__RA__RC, && case_sem_INSN_ASLS_CC__RA__RC },
+ { ARC600F_INSN_ASRS_L_S12__RA_, && case_sem_INSN_ASRS_L_S12__RA_ },
+ { ARC600F_INSN_ASRS_CCU6__RA_, && case_sem_INSN_ASRS_CCU6__RA_ },
+ { ARC600F_INSN_ASRS_L_U6__RA_, && case_sem_INSN_ASRS_L_U6__RA_ },
+ { ARC600F_INSN_ASRS_L_R_R__RA__RC, && case_sem_INSN_ASRS_L_R_R__RA__RC },
+ { ARC600F_INSN_ASRS_CC__RA__RC, && case_sem_INSN_ASRS_CC__RA__RC },
+ { ARC600F_INSN_ADDSDW_L_S12__RA_, && case_sem_INSN_ADDSDW_L_S12__RA_ },
+ { ARC600F_INSN_ADDSDW_CCU6__RA_, && case_sem_INSN_ADDSDW_CCU6__RA_ },
+ { ARC600F_INSN_ADDSDW_L_U6__RA_, && case_sem_INSN_ADDSDW_L_U6__RA_ },
+ { ARC600F_INSN_ADDSDW_L_R_R__RA__RC, && case_sem_INSN_ADDSDW_L_R_R__RA__RC },
+ { ARC600F_INSN_ADDSDW_CC__RA__RC, && case_sem_INSN_ADDSDW_CC__RA__RC },
+ { ARC600F_INSN_SUBSDW_L_S12__RA_, && case_sem_INSN_SUBSDW_L_S12__RA_ },
+ { ARC600F_INSN_SUBSDW_CCU6__RA_, && case_sem_INSN_SUBSDW_CCU6__RA_ },
+ { ARC600F_INSN_SUBSDW_L_U6__RA_, && case_sem_INSN_SUBSDW_L_U6__RA_ },
+ { ARC600F_INSN_SUBSDW_L_R_R__RA__RC, && case_sem_INSN_SUBSDW_L_R_R__RA__RC },
+ { ARC600F_INSN_SUBSDW_CC__RA__RC, && case_sem_INSN_SUBSDW_CC__RA__RC },
+ { ARC600F_INSN_SWAP_L_R_R__RC, && case_sem_INSN_SWAP_L_R_R__RC },
+ { ARC600F_INSN_SWAP_L_U6_, && case_sem_INSN_SWAP_L_U6_ },
+ { ARC600F_INSN_NORM_L_R_R__RC, && case_sem_INSN_NORM_L_R_R__RC },
+ { ARC600F_INSN_NORM_L_U6_, && case_sem_INSN_NORM_L_U6_ },
+ { ARC600F_INSN_RND16_L_R_R__RC, && case_sem_INSN_RND16_L_R_R__RC },
+ { ARC600F_INSN_RND16_L_U6_, && case_sem_INSN_RND16_L_U6_ },
+ { ARC600F_INSN_ABSSW_L_R_R__RC, && case_sem_INSN_ABSSW_L_R_R__RC },
+ { ARC600F_INSN_ABSSW_L_U6_, && case_sem_INSN_ABSSW_L_U6_ },
+ { ARC600F_INSN_ABSS_L_R_R__RC, && case_sem_INSN_ABSS_L_R_R__RC },
+ { ARC600F_INSN_ABSS_L_U6_, && case_sem_INSN_ABSS_L_U6_ },
+ { ARC600F_INSN_NEGSW_L_R_R__RC, && case_sem_INSN_NEGSW_L_R_R__RC },
+ { ARC600F_INSN_NEGSW_L_U6_, && case_sem_INSN_NEGSW_L_U6_ },
+ { ARC600F_INSN_NEGS_L_R_R__RC, && case_sem_INSN_NEGS_L_R_R__RC },
+ { ARC600F_INSN_NEGS_L_U6_, && case_sem_INSN_NEGS_L_U6_ },
+ { ARC600F_INSN_NORMW_L_R_R__RC, && case_sem_INSN_NORMW_L_R_R__RC },
+ { ARC600F_INSN_NORMW_L_U6_, && case_sem_INSN_NORMW_L_U6_ },
+ { ARC600F_INSN_NOP_S, && case_sem_INSN_NOP_S },
+ { ARC600F_INSN_UNIMP_S, && case_sem_INSN_UNIMP_S },
+ { ARC600F_INSN_POP_S_B, && case_sem_INSN_POP_S_B },
+ { ARC600F_INSN_POP_S_BLINK, && case_sem_INSN_POP_S_BLINK },
+ { ARC600F_INSN_PUSH_S_B, && case_sem_INSN_PUSH_S_B },
+ { ARC600F_INSN_PUSH_S_BLINK, && case_sem_INSN_PUSH_S_BLINK },
+ { ARC600F_INSN_MULLW_L_S12__RA_, && case_sem_INSN_MULLW_L_S12__RA_ },
+ { ARC600F_INSN_MULLW_CCU6__RA_, && case_sem_INSN_MULLW_CCU6__RA_ },
+ { ARC600F_INSN_MULLW_L_U6__RA_, && case_sem_INSN_MULLW_L_U6__RA_ },
+ { ARC600F_INSN_MULLW_L_R_R__RA__RC, && case_sem_INSN_MULLW_L_R_R__RA__RC },
+ { ARC600F_INSN_MULLW_CC__RA__RC, && case_sem_INSN_MULLW_CC__RA__RC },
+ { ARC600F_INSN_MACLW_L_S12__RA_, && case_sem_INSN_MACLW_L_S12__RA_ },
+ { ARC600F_INSN_MACLW_CCU6__RA_, && case_sem_INSN_MACLW_CCU6__RA_ },
+ { ARC600F_INSN_MACLW_L_U6__RA_, && case_sem_INSN_MACLW_L_U6__RA_ },
+ { ARC600F_INSN_MACLW_L_R_R__RA__RC, && case_sem_INSN_MACLW_L_R_R__RA__RC },
+ { ARC600F_INSN_MACLW_CC__RA__RC, && case_sem_INSN_MACLW_CC__RA__RC },
+ { ARC600F_INSN_MACHLW_L_S12__RA_, && case_sem_INSN_MACHLW_L_S12__RA_ },
+ { ARC600F_INSN_MACHLW_CCU6__RA_, && case_sem_INSN_MACHLW_CCU6__RA_ },
+ { ARC600F_INSN_MACHLW_L_U6__RA_, && case_sem_INSN_MACHLW_L_U6__RA_ },
+ { ARC600F_INSN_MACHLW_L_R_R__RA__RC, && case_sem_INSN_MACHLW_L_R_R__RA__RC },
+ { ARC600F_INSN_MACHLW_CC__RA__RC, && case_sem_INSN_MACHLW_CC__RA__RC },
+ { ARC600F_INSN_MULULW_L_S12__RA_, && case_sem_INSN_MULULW_L_S12__RA_ },
+ { ARC600F_INSN_MULULW_CCU6__RA_, && case_sem_INSN_MULULW_CCU6__RA_ },
+ { ARC600F_INSN_MULULW_L_U6__RA_, && case_sem_INSN_MULULW_L_U6__RA_ },
+ { ARC600F_INSN_MULULW_L_R_R__RA__RC, && case_sem_INSN_MULULW_L_R_R__RA__RC },
+ { ARC600F_INSN_MULULW_CC__RA__RC, && case_sem_INSN_MULULW_CC__RA__RC },
+ { ARC600F_INSN_MACHULW_L_S12__RA_, && case_sem_INSN_MACHULW_L_S12__RA_ },
+ { ARC600F_INSN_MACHULW_CCU6__RA_, && case_sem_INSN_MACHULW_CCU6__RA_ },
+ { ARC600F_INSN_MACHULW_L_U6__RA_, && case_sem_INSN_MACHULW_L_U6__RA_ },
+ { ARC600F_INSN_MACHULW_L_R_R__RA__RC, && case_sem_INSN_MACHULW_L_R_R__RA__RC },
+ { ARC600F_INSN_MACHULW_CC__RA__RC, && case_sem_INSN_MACHULW_CC__RA__RC },
+ { ARC600F_INSN_CURRENT_LOOP_END, && case_sem_INSN_CURRENT_LOOP_END },
+ { ARC600F_INSN_CURRENT_LOOP_END_AFTER_BRANCH, && case_sem_INSN_CURRENT_LOOP_END_AFTER_BRANCH },
+ { ARC600F_INSN_ARC600_CURRENT_LOOP_END_AFTER_BRANCH, && case_sem_INSN_ARC600_CURRENT_LOOP_END_AFTER_BRANCH },
+ { 0, 0 }
+ };
+ int i;
+
+ for (i = 0; labels[i].label != 0; ++i)
+ {
+#if FAST_P
+ CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
+#else
+ CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
+#endif
+ }
+
+#undef DEFINE_LABELS
+#endif /* DEFINE_LABELS */
+
+#ifdef DEFINE_SWITCH
+
+/* If hyper-fast [well not unnecessarily slow] execution is selected, turn
+ off frills like tracing and profiling. */
+/* FIXME: A better way would be to have TRACE_RESULT check for something
+ that can cause it to be optimized out. Another way would be to emit
+ special handlers into the instruction "stream". */
+
+#if FAST_P
+#undef TRACE_RESULT
+#define TRACE_RESULT(cpu, abuf, name, type, val)
+#endif
+
+#undef GET_ATTR
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
+#else
+#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr)
+#endif
+
+{
+
+#if WITH_SCACHE_PBB
+
+/* Branch to next handler without going around main loop. */
+#define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
+SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
+
+#else /* ! WITH_SCACHE_PBB */
+
+#define NEXT(vpc) BREAK (sem)
+#ifdef __GNUC__
+#if FAST_P
+ SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
+#else
+ SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
+#endif
+#else
+ SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
+#endif
+
+#endif /* ! WITH_SCACHE_PBB */
+
+ {
+
+ CASE (sem, INSN_X_INVALID) : /* --invalid-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+ /* Update the recorded pc in the cpu state struct.
+ Only necessary for WITH_SCACHE case, but to avoid the
+ conditional compilation .... */
+ SET_H_PC (pc);
+ /* Virtual insns have zero size. Overwrite vpc with address of next insn
+ using the default-insn-bitsize spec. When executing insns in parallel
+ we may want to queue the fault and continue execution. */
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+ vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_AFTER) : /* --after-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_ARC600F
+ arc600f_pbb_after (current_cpu, sem_arg);
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_BEFORE) : /* --before-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_ARC600F
+ arc600f_pbb_before (current_cpu, sem_arg);
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_ARC600F
+#ifdef DEFINE_SWITCH
+ vpc = arc600f_pbb_cti_chain (current_cpu, sem_arg,
+ pbb_br_type, pbb_br_npc);
+ BREAK (sem);
+#else
+ /* FIXME: Allow provision of explicit ifmt spec in insn spec. */
+ vpc = arc600f_pbb_cti_chain (current_cpu, sem_arg,
+ CPU_PBB_BR_TYPE (current_cpu),
+ CPU_PBB_BR_NPC (current_cpu));
+#endif
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_CHAIN) : /* --chain-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_ARC600F
+ vpc = arc600f_pbb_chain (current_cpu, sem_arg);
+#ifdef DEFINE_SWITCH
+ BREAK (sem);
+#endif
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_BEGIN) : /* --begin-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_ARC600F
+#if defined DEFINE_SWITCH || defined FAST_P
+ /* In the switch case FAST_P is a constant, allowing several optimizations
+ in any called inline functions. */
+ vpc = arc600f_pbb_begin (current_cpu, FAST_P);
+#else
+#if 0 /* cgen engine can't handle dynamic fast/full switching yet. */
+ vpc = arc600f_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
+#else
+ vpc = arc600f_pbb_begin (current_cpu, 0);
+#endif
+#endif
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_B_S) : /* b$i2cond $label10 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_b_s.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GET_H_I2COND (FLD (f_cond_i2))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = FLD (i_label10);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = FLD (i_label10);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = FLD (i_label10);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BCC_S) : /* b$i3cond$_S $label7 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bcc_s.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GET_H_I3COND (FLD (f_cond_i3))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = FLD (i_label7);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = FLD (i_label7);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = FLD (i_label7);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BRCC_S) : /* br$RccS$_S $R_b,0,$label8 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_brcc_s.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if ((FLD (f_brscond) == 0) ? (EQSI (GET_H_CR16 (FLD (f_op__b)), 0)) : (FLD (f_brscond) == 1) ? (NESI (GET_H_CR16 (FLD (f_op__b)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = FLD (i_label8);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = FLD (i_label8);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = FLD (i_label8);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BCC_L) : /* b$Qcondb$_L $label21 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bcc_l.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+((void) 0); /*nop*/
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = FLD (i_label21);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = FLD (i_label21);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = FLD (i_label21);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BCC_L_D) : /* b$Qcondb$_L.d $label21 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bcc_l.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+((void) 0); /*nop*/
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (i_label21);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else if (1) {
+{
+ {
+ USI opval = FLD (i_label21);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ {
+ USI opval = FLD (i_label21);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_B_L) : /* b$uncondb$_L $label25 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_b_l.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = FLD (i_label25);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = FLD (i_label25);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = FLD (i_label25);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_B_L_D) : /* b$uncondb$_L.d $label25 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_b_l.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (i_label25);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else if (1) {
+{
+ {
+ USI opval = FLD (i_label25);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ {
+ USI opval = FLD (i_label25);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BRCC_RC) : /* b$Rcc $RB,$RC,$label9 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_brcc_RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BRCC_RC_D) : /* b$Rcc.d $RB,$RC,$label9 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_brcc_RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+{
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+{
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+{
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BRCC_U6) : /* b$Rcc $RB,$U6,$label9 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_brcc_U6.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BRCC_U6_D) : /* b$Rcc.d $RB,$U6,$label9 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_brcc_U6.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+{
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+{
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+{
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BL_S) : /* bl$uncondj$_S $label13a */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl_s.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ {
+ SI opval = ADDSI (pc, 2);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label13a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else if (0) {
+{
+ {
+ SI opval = ADDSI (pc, 2);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label13a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ {
+ SI opval = ADDSI (pc, 2);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label13a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BLCC) : /* bl$Qcondj$_L $label21 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_blcc.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+((void) 0); /*nop*/
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label21a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else if (0) {
+{
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label21a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label21a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BLCC_D) : /* bl$Qcondj$_L.d $label21 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_blcc.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+((void) 0); /*nop*/
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+{
+ {
+ USI opval = FLD (i_label21a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+{
+ {
+ USI opval = FLD (i_label21a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+{
+ {
+ USI opval = FLD (i_label21a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BL) : /* bl$uncondj$_L $label25a */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label25a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else if (0) {
+{
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label25a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label25a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BL_D) : /* bl$uncondj$_L.d $label25a */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (i_label25a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (i_label25a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (i_label25a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD_ABS) : /* ld$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD__AW_ABS) : /* ld$_AW$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD_AB_ABS) : /* ld.ab$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD_AS_ABS) : /* ld.as$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s9), 2));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD_ABC) : /* ld$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD__AW_ABC) : /* ld$_AW$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD_AB_ABC) : /* ld.ab$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD_AS_ABC) : /* ld.as$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 2));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD_S_ABC) : /* ld$_S $R_a,[$R_b,$R_c] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), GET_H_CR16 (FLD (f_op__c)));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR16 (FLD (f_op__a), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD_S_ABU) : /* ld$_S $R_c,[$R_b,$sc_u5_] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), FLD (f_u5x4));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD_S_ABSP) : /* ld$_S $R_b,[$SP,$u5x4] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_SP (), FLD (f_u5x4));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD_S_GPREL) : /* ld$_S $R_b,[$GP,$sc_s9_] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_gprel.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_GP (), FLD (f_s9x4));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_R0 (, opval);
+ TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD_S_PCREL) : /* ld$_S $R_b,[$PCL,$u8x4] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_pcrel.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (ANDSI (pc, -4), FLD (f_u8x4));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_ABS) : /* ldb$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB__AW_ABS) : /* ldb$_AW$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_AB_ABS) : /* ldb.ab$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_AS_ABS) : /* ldb.as$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), (cgen_rtx_error (current_cpu, "invalid insn"), 0));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_ABC) : /* ldb$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB__AW_ABC) : /* ldb$_AW$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_AB_ABC) : /* ldb.ab$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_AS_ABC) : /* ldb.as$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), (cgen_rtx_error (current_cpu, "invalid insn"), 0));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_S_ABC) : /* ldb$_S $R_a,[$R_b,$R_c] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), GET_H_CR16 (FLD (f_op__c)));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR16 (FLD (f_op__a), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_S_ABU) : /* ldb$_S $R_c,[$R_b,$sc_u5b] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), FLD (f_u5));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_S_ABSP) : /* ldb$_S $R_b,[$SP,$u5x4] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_SP (), FLD (f_u5x4));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_S_GPREL) : /* ldb$_S $R_b,[$GP,$sc_s9b] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldb_s_gprel.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_GP (), FLD (f_s9x1));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_R0 (, opval);
+ TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_X_ABS) : /* ldb.x$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB__AW_X_ABS) : /* ldb$_AW.x$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_AB_X_ABS) : /* ldb.ab.x$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_AS_X_ABS) : /* ldb.as.x$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), (cgen_rtx_error (current_cpu, "invalid insn"), 0));
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_X_ABC) : /* ldb.x$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB__AW_X_ABC) : /* ldb$_AW.x$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_AB_X_ABC) : /* ldb.ab.x$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_AS_X_ABC) : /* ldb.as.x$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), (cgen_rtx_error (current_cpu, "invalid insn"), 0));
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_ABS) : /* ldw$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW__AW_ABS) : /* ldw$_AW$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_AB_ABS) : /* ldw.ab$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_AS_ABS) : /* ldw.as$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s9), 1));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_ABC) : /* ldw$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW__AW_ABC) : /* ldw$_AW$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_AB_ABC) : /* ldw.ab$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_AS_ABC) : /* ldw.as$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 1));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_S_ABC) : /* ldw$_S $R_a,[$R_b,$R_c] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), GET_H_CR16 (FLD (f_op__c)));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR16 (FLD (f_op__a), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_S_ABU) : /* ldw$_S $R_c,[$R_b,$sc_u5w] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldw_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), FLD (f_u5x2));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_S_GPREL) : /* ldw$_S $R_b,[$GP,$sc_s9w] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldw_s_gprel.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_GP (), FLD (f_s9x2));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_R0 (, opval);
+ TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_X_ABS) : /* ldw.x$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW__AW_X_ABS) : /* ldw$_AW.x$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_AB_X_ABS) : /* ldw.ab.x$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_AS_X_ABS) : /* ldw.as.x$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s9), 1));
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_X_ABC) : /* ldw.x$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW__AW_X_ABC) : /* ldw$_AW.x$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_AB_X_ABC) : /* ldw.ab.x$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_AS_X_ABC) : /* ldw.as.x$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 1));
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_S_X_ABU) : /* ldw$_S.x $R_c,[$R_b,$sc_u5w] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldw_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), FLD (f_u5x2));
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ST_ABS) : /* st$STODi $RC,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMSI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ST__AW_ABS) : /* st$_AW$STODi $RC,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMSI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ST_AB_ABS) : /* st.ab$STODi $RC,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMSI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ST_AS_ABS) : /* st.as$STODi $RC,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s9), 2));
+ {
+ SI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMSI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ST_S_ABU) : /* st$_S $R_c,[$R_b,$sc_u5_] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), FLD (f_u5x4));
+ {
+ SI opval = GET_H_CR16 (FLD (f_op__c));
+ SETMEMSI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ST_S_ABSP) : /* st$_S $R_b,[$SP,$u5x4] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_SP (), FLD (f_u5x4));
+ {
+ SI opval = GET_H_CR16 (FLD (f_op__b));
+ SETMEMSI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STB_ABS) : /* stb$STODi $RC,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ QI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMQI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STB__AW_ABS) : /* stb$_AW$STODi $RC,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ QI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMQI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STB_AB_ABS) : /* stb.ab$STODi $RC,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ QI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMQI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STB_AS_ABS) : /* stb.as$STODi $RC,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), (cgen_rtx_error (current_cpu, "invalid insn"), 0));
+ {
+ QI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMQI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STB_S_ABU) : /* stb$_S $R_c,[$R_b,$sc_u5b] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), FLD (f_u5));
+ {
+ QI opval = GET_H_CR16 (FLD (f_op__c));
+ SETMEMQI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STB_S_ABSP) : /* stb$_S $R_b,[$SP,$u5x4] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_SP (), FLD (f_u5x4));
+ {
+ QI opval = GET_H_CR16 (FLD (f_op__b));
+ SETMEMQI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STW_ABS) : /* stw$STODi $RC,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ HI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMHI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STW__AW_ABS) : /* stw$_AW$STODi $RC,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ HI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMHI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STW_AB_ABS) : /* stw.ab$STODi $RC,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ HI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMHI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STW_AS_ABS) : /* stw.as$STODi $RC,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s9), 1));
+ {
+ HI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMHI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STW_S_ABU) : /* stw$_S $R_c,[$R_b,$sc_u5w] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldw_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), FLD (f_u5x2));
+ {
+ HI opval = GET_H_CR16 (FLD (f_op__c));
+ SETMEMHI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_L_S12__RA_) : /* add$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_CCU6__RA_) : /* add$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_L_U6__RA_) : /* add$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_L_R_R__RA__RC) : /* add$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_CC__RA__RC) : /* add$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_S_ABC) : /* add$_S $R_a,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ADDSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__a), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_S_CBU3) : /* add$_S $R_c,$R_b,$u3 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u3);
+ {
+ SI opval = ADDSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_S_MCAH) : /* add$_S $R_b,$R_b,$Rh */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+{
+if (EQSI (FLD (f_op_h), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 2));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (2, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_h), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR (FLD (f_op_h));
+ {
+ SI opval = ADDSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_S_ABSP) : /* add$_S $R_b,$SP,$u5x4 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_SP ();
+ tmp_C = FLD (f_u5x4);
+ {
+ SI opval = ADDSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_S_ASSPSP) : /* add$_S $SP,$SP,$u5x4 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_SP ();
+ tmp_C = FLD (f_u5x4);
+ {
+ SI opval = ADDSI (tmp_B, tmp_C);
+ SET_H_SP (, opval);
+ TRACE_RESULT (current_cpu, abuf, "sp", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_S_GP) : /* add$_S $R0,$GP,$s9x4 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_gprel.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_GP ();
+ tmp_C = FLD (f_s9x4);
+ {
+ SI opval = ADDSI (tmp_B, tmp_C);
+ SET_H_R0 (, opval);
+ TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_S_R_U7) : /* add$_S $R_b,$R_b,$u7 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_r_u7.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u7);
+ {
+ SI opval = ADDSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADC_L_S12__RA_) : /* adc$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDCSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADC_CCU6__RA_) : /* adc$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDCSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADC_L_U6__RA_) : /* adc$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDCSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADC_L_R_R__RA__RC) : /* adc$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDCSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADC_CC__RA__RC) : /* adc$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDCSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_L_S12__RA_) : /* sub$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_CCU6__RA_) : /* sub$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_L_U6__RA_) : /* sub$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_L_R_R__RA__RC) : /* sub$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_CC__RA__RC) : /* sub$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_S_CBU3) : /* sub$_S $R_c,$R_b,$u3 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u3);
+ {
+ SI opval = SUBSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_SUB_S_GO) : /* sub$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = SUBSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_S_GO_SUB_NE) : /* sub$_S $NE$R_b,$R_b,$R_b */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQBI (CPU (h_zbit), 0)) {
+ {
+ SI opval = 0;
+ SET_H_CR16 (FLD (f_op__b), opval);
+ written |= (1 << 1);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_S_SSB) : /* sub$_S $R_b,$R_b,$u5 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ {
+ SI opval = SUBSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_S_ASSPSP) : /* sub$_S $SP,$SP,$u5x4 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_SP ();
+ tmp_C = FLD (f_u5x4);
+ {
+ SI opval = SUBSI (tmp_B, tmp_C);
+ SET_H_SP (, opval);
+ TRACE_RESULT (current_cpu, abuf, "sp", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SBC_L_S12__RA_) : /* sbc$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBCSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SBC_CCU6__RA_) : /* sbc$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBCSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SBC_L_U6__RA_) : /* sbc$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBCSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SBC_L_R_R__RA__RC) : /* sbc$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBCSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SBC_CC__RA__RC) : /* sbc$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBCSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_AND_L_S12__RA_) : /* and$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_AND_CCU6__RA_) : /* and$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_AND_L_U6__RA_) : /* and$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_AND_L_R_R__RA__RC) : /* and$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_AND_CC__RA__RC) : /* and$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_AND_S_GO) : /* and$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ANDSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_OR_L_S12__RA_) : /* or$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_OR_CCU6__RA_) : /* or$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_OR_L_U6__RA_) : /* or$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_OR_L_R_R__RA__RC) : /* or$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_OR_CC__RA__RC) : /* or$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_OR_S_GO) : /* or$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ORSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BIC_L_S12__RA_) : /* bic$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (FLD (f_s12)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BIC_CCU6__RA_) : /* bic$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (FLD (f_u6)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BIC_L_U6__RA_) : /* bic$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (FLD (f_u6)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BIC_L_R_R__RA__RC) : /* bic$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BIC_CC__RA__RC) : /* bic$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_BIC_S_GO) : /* bic$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ANDSI (tmp_B, INVSI (tmp_C));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_XOR_L_S12__RA_) : /* xor$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_XOR_CCU6__RA_) : /* xor$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_XOR_L_U6__RA_) : /* xor$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_XOR_L_R_R__RA__RC) : /* xor$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_XOR_CC__RA__RC) : /* xor$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_XOR_S_GO) : /* xor$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = XORSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MAX_L_S12__RA_) : /* max$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (GTSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12))) ? (GET_H_CR (FLD (f_op_B))) : (FLD (f_s12));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = GESI (FLD (f_s12), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MAX_CCU6__RA_) : /* max$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (GTSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6))) ? (GET_H_CR (FLD (f_op_B))) : (FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = GESI (FLD (f_u6), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MAX_L_U6__RA_) : /* max$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (GTSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6))) ? (GET_H_CR (FLD (f_op_B))) : (FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = GESI (FLD (f_u6), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MAX_L_R_R__RA__RC) : /* max$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (GTSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)))) ? (GET_H_CR (FLD (f_op_B))) : (GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = GESI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MAX_CC__RA__RC) : /* max$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (GTSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)))) ? (GET_H_CR (FLD (f_op_B))) : (GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = GESI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MIN_L_S12__RA_) : /* min$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (LTSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12))) ? (GET_H_CR (FLD (f_op_B))) : (FLD (f_s12));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = LESI (FLD (f_s12), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MIN_CCU6__RA_) : /* min$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (LTSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6))) ? (GET_H_CR (FLD (f_op_B))) : (FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = LESI (FLD (f_u6), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MIN_L_U6__RA_) : /* min$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (LTSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6))) ? (GET_H_CR (FLD (f_op_B))) : (FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = LESI (FLD (f_u6), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MIN_L_R_R__RA__RC) : /* min$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (LTSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)))) ? (GET_H_CR (FLD (f_op_B))) : (GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = LESI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MIN_CC__RA__RC) : /* min$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (LTSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)))) ? (GET_H_CR (FLD (f_op_B))) : (GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = LESI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOV_L_S12_) : /* mov$_L$F $RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+ tmp_result = FLD (f_s12);
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GTSI (FLD (f_F), 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOV_CCU6_) : /* mov$Qcondi$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+((void) 0); /*nop*/
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+ tmp_result = FLD (f_u6);
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GTSI (FLD (f_F), 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 5);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOV_L_U6_) : /* mov$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+ tmp_result = FLD (f_u6);
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GTSI (FLD (f_F), 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOV_L_R_R__RC) : /* mov$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = GET_H_CR (FLD (f_op_C));
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GTSI (FLD (f_F), 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOV_CC__RC) : /* mov$Qcondi$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+ tmp_result = GET_H_CR (FLD (f_op_C));
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GTSI (FLD (f_F), 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOV_S_MCAH) : /* mov$_S $R_b,$Rh */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_h), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 2));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (2, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_h), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = GET_H_CR (FLD (f_op_h));
+ {
+ SI opval = tmp_result;
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+if (GTSI (-1, 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOV_S_MCAHB) : /* mov$_S $Rh,$R_b */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+ tmp_result = GET_H_CR16 (FLD (f_op__b));
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_h), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GTSI (-1, 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOV_S_R_U7) : /* mov$_S $R_b,$u7 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+ tmp_result = FLD (f_u8);
+ {
+ SI opval = tmp_result;
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+if (GTSI (-1, 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_TST_L_S12_) : /* tst$_L$F1 $RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_s12);
+ tmp_result = ANDSI (tmp_B, tmp_C);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_TST_CCU6_) : /* tst$Qcondi$F1 $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+ tmp_result = ANDSI (tmp_B, tmp_C);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_TST_L_U6_) : /* tst$_L$F1 $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+ tmp_result = ANDSI (tmp_B, tmp_C);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_TST_L_R_R__RC) : /* tst$_L$F1 $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+ tmp_result = ANDSI (tmp_B, tmp_C);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_TST_CC__RC) : /* tst$Qcondi$F1 $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+ tmp_result = ANDSI (tmp_B, tmp_C);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_TST_S_GO) : /* tst$_S $R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ tmp_result = ANDSI (tmp_B, tmp_C);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMP_L_S12_) : /* cmp$_L$F1 $RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (FLD (f_s12));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (FLD (f_s12));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMP_CCU6_) : /* cmp$Qcondi$F1 $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMP_L_U6_) : /* cmp$_L$F1 $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMP_L_R_R__RC) : /* cmp$_L$F1 $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMP_CC__RC) : /* cmp$Qcondi$F1 $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMP_S_MCAH) : /* cmp$_S $R_b,$Rh */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+{
+if (EQSI (FLD (f_op_h), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 2));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (2, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_h), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = EXTSIDI (GET_H_CR16 (FLD (f_op__b)));
+ tmp_C = EXTSIDI (GET_H_CR (FLD (f_op_h)));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR16 (FLD (f_op__b)));
+ tmp_C = ZEXTSIDI (GET_H_CR (FLD (f_op_h)));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMP_S_R_U7) : /* cmp$_S $R_b,$u7 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_r_u7.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = EXTSIDI (GET_H_CR16 (FLD (f_op__b)));
+ tmp_C = EXTSIDI (FLD (f_u7));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR16 (FLD (f_op__b)));
+ tmp_C = ZEXTSIDI (FLD (f_u7));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RCMP_L_S12_) : /* rcmp$_L$F1 $RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (FLD (f_s12));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (FLD (f_s12));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RCMP_CCU6_) : /* rcmp$Qcondi$F1 $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RCMP_L_U6_) : /* rcmp$_L$F1 $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RCMP_L_R_R__RC) : /* rcmp$_L$F1 $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RCMP_CC__RC) : /* rcmp$Qcondi$F1 $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RSUB_L_S12__RA_) : /* rsub$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (FLD (f_s12), GET_H_CR (FLD (f_op_B)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (FLD (f_s12), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (FLD (f_s12), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RSUB_CCU6__RA_) : /* rsub$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (FLD (f_u6), GET_H_CR (FLD (f_op_B)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (FLD (f_u6), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (FLD (f_u6), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RSUB_L_U6__RA_) : /* rsub$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (FLD (f_u6), GET_H_CR (FLD (f_op_B)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (FLD (f_u6), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (FLD (f_u6), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RSUB_L_R_R__RA__RC) : /* rsub$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RSUB_CC__RA__RC) : /* rsub$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BSET_L_S12__RA_) : /* bset$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (FLD (f_s12), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BSET_CCU6__RA_) : /* bset$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BSET_L_U6__RA_) : /* bset$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BSET_L_R_R__RA__RC) : /* bset$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BSET_CC__RA__RC) : /* bset$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BSET_S_SSB) : /* bset$_S $R_b,$R_b,$u5 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ {
+ SI opval = ORSI (tmp_B, SLLSI (1, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BCLR_L_S12__RA_) : /* bclr$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (SLLSI (1, ANDSI (FLD (f_s12), 31))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BCLR_CCU6__RA_) : /* bclr$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (SLLSI (1, ANDSI (FLD (f_u6), 31))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BCLR_L_U6__RA_) : /* bclr$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (SLLSI (1, ANDSI (FLD (f_u6), 31))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BCLR_L_R_R__RA__RC) : /* bclr$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BCLR_CC__RA__RC) : /* bclr$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BCLR_S_SSB) : /* bclr$_S $R_b,$R_b,$u5 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ {
+ SI opval = ANDSI (tmp_B, INVSI (SLLSI (1, ANDSI (tmp_C, 31))));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BTST_L_S12_) : /* btst$_L$F1 $RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_s12);
+ tmp_result = ANDSI (tmp_B, SLLSI (1, ANDSI (tmp_C, 31)));
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BTST_CCU6_) : /* btst$Qcondi$F1 $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+ tmp_result = ANDSI (tmp_B, SLLSI (1, ANDSI (tmp_C, 31)));
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BTST_L_U6_) : /* btst$_L$F1 $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+ tmp_result = ANDSI (tmp_B, SLLSI (1, ANDSI (tmp_C, 31)));
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BTST_L_R_R__RC) : /* btst$_L$F1 $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+ tmp_result = ANDSI (tmp_B, SLLSI (1, ANDSI (tmp_C, 31)));
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BTST_CC__RC) : /* btst$Qcondi$F1 $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+ tmp_result = ANDSI (tmp_B, SLLSI (1, ANDSI (tmp_C, 31)));
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BTST_S_SSB) : /* btst$_S $R_b,$u5 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ tmp_result = ANDSI (tmp_B, SLLSI (1, ANDSI (tmp_C, 31)));
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BXOR_L_S12__RA_) : /* bxor$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (FLD (f_s12), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BXOR_CCU6__RA_) : /* bxor$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BXOR_L_U6__RA_) : /* bxor$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BXOR_L_R_R__RA__RC) : /* bxor$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BXOR_CC__RA__RC) : /* bxor$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BMSK_L_S12__RA_) : /* bmsk$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), SUBSI (SLLSI (SLLSI (1, ANDSI (FLD (f_s12), 31)), 1), 1));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BMSK_CCU6__RA_) : /* bmsk$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), SUBSI (SLLSI (SLLSI (1, ANDSI (FLD (f_u6), 31)), 1), 1));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BMSK_L_U6__RA_) : /* bmsk$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), SUBSI (SLLSI (SLLSI (1, ANDSI (FLD (f_u6), 31)), 1), 1));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BMSK_L_R_R__RA__RC) : /* bmsk$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), SUBSI (SLLSI (SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31)), 1), 1));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BMSK_CC__RA__RC) : /* bmsk$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), SUBSI (SLLSI (SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31)), 1), 1));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BMSK_S_SSB) : /* bmsk$_S $R_b,$R_b,$u5 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ {
+ SI opval = ANDSI (tmp_B, SUBSI (SLLSI (SLLSI (1, ANDSI (tmp_C, 31)), 1), 1));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD1_L_S12__RA_) : /* add1$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s12), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_s12), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD1_CCU6__RA_) : /* add1$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD1_L_U6__RA_) : /* add1$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD1_L_R_R__RA__RC) : /* add1$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD1_CC__RA__RC) : /* add1$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_ADD1_S_GO) : /* add1$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ADDSI (tmp_B, SLLSI (tmp_C, 1));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD2_L_S12__RA_) : /* add2$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s12), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_s12), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD2_CCU6__RA_) : /* add2$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD2_L_U6__RA_) : /* add2$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD2_L_R_R__RA__RC) : /* add2$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD2_CC__RA__RC) : /* add2$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_ADD2_S_GO) : /* add2$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ADDSI (tmp_B, SLLSI (tmp_C, 2));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD3_L_S12__RA_) : /* add3$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s12), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_s12), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD3_CCU6__RA_) : /* add3$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD3_L_U6__RA_) : /* add3$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD3_L_R_R__RA__RC) : /* add3$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD3_CC__RA__RC) : /* add3$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_ADD3_S_GO) : /* add3$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ADDSI (tmp_B, SLLSI (tmp_C, 3));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB1_L_S12__RA_) : /* sub1$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s12), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_s12), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB1_CCU6__RA_) : /* sub1$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB1_L_U6__RA_) : /* sub1$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB1_L_R_R__RA__RC) : /* sub1$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB1_CC__RA__RC) : /* sub1$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB2_L_S12__RA_) : /* sub2$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s12), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_s12), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB2_CCU6__RA_) : /* sub2$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB2_L_U6__RA_) : /* sub2$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB2_L_R_R__RA__RC) : /* sub2$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB2_CC__RA__RC) : /* sub2$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB3_L_S12__RA_) : /* sub3$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s12), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_s12), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB3_CCU6__RA_) : /* sub3$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB3_L_U6__RA_) : /* sub3$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB3_L_R_R__RA__RC) : /* sub3$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB3_CC__RA__RC) : /* sub3$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPY_L_S12__RA_) : /* mpy$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (EXTSIDI (tmp_result), MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_s12))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPY_CCU6__RA_) : /* mpy$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (EXTSIDI (tmp_result), MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPY_L_U6__RA_) : /* mpy$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (EXTSIDI (tmp_result), MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPY_L_R_R__RA__RC) : /* mpy$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (EXTSIDI (tmp_result), MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C)))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPY_CC__RA__RC) : /* mpy$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (EXTSIDI (tmp_result), MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C)))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYH_L_S12__RA_) : /* mpyh$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_s12))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYH_CCU6__RA_) : /* mpyh$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYH_L_U6__RA_) : /* mpyh$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYH_L_R_R__RA__RC) : /* mpyh$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C)))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYH_CC__RA__RC) : /* mpyh$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C)))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYHU_L_S12__RA_) : /* mpyhu$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_s12))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYHU_CCU6__RA_) : /* mpyhu$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_u6))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYHU_L_U6__RA_) : /* mpyhu$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_u6))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYHU_L_R_R__RA__RC) : /* mpyhu$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (GET_H_CR (FLD (f_op_C)))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYHU_CC__RA__RC) : /* mpyhu$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (GET_H_CR (FLD (f_op_C)))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYU_L_S12__RA_) : /* mpyu$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (ZEXTSIDI (tmp_result), MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_s12))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYU_CCU6__RA_) : /* mpyu$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (ZEXTSIDI (tmp_result), MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_u6))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYU_L_U6__RA_) : /* mpyu$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (ZEXTSIDI (tmp_result), MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_u6))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYU_L_R_R__RA__RC) : /* mpyu$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (ZEXTSIDI (tmp_result), MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (GET_H_CR (FLD (f_op_C)))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYU_CC__RA__RC) : /* mpyu$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (ZEXTSIDI (tmp_result), MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (GET_H_CR (FLD (f_op_C)))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_L_R_R___RC_NOILINK_) : /* j$_L$F0 [$RC_noilink] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_CC___RC_NOILINK_) : /* j$Qcondi$F0 [$RC_noilink] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_L_R_R___RC_ILINK_) : /* j$_L$F1F [$RC_ilink] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_ILINKX (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_ILINKX (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_ILINKX (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_CC___RC_ILINK_) : /* j$Qcondi$F1F [$RC_ilink] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_ILINKX (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_ILINKX (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_ILINKX (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_L_S12_) : /* j$_L$F0 $s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_CCU6_) : /* j$Qcondi$F0 $U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_L_U6_) : /* j$_L$F0 $U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_S) : /* j$_S [$R_b] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_S__S) : /* j$_S [$R31] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_SEQ__S) : /* jeq$_S [$R31] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if (NEBI (CPU (h_zbit), 0)) {
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if (NEBI (CPU (h_zbit), 0)) {
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if (NEBI (CPU (h_zbit), 0)) {
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_SNE__S) : /* jne$_S [$R31] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if (EQBI (CPU (h_zbit), 0)) {
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if (EQBI (CPU (h_zbit), 0)) {
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if (EQBI (CPU (h_zbit), 0)) {
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_L_S12_D_) : /* j$_L$F0.d $s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_CCU6_D_) : /* j$Qcondi$F0.d $U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_L_U6_D_) : /* j$_L$F0.d $U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_L_R_R_D___RC_) : /* j$_L$F0.d [$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_CC_D___RC_) : /* j$Qcondi$F0.d [$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_S_D) : /* j$_S.d [$R_b] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_S__S_D) : /* j$_S.d [$R31] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JL_L_S12_) : /* jl$_L$F0 $s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JL_CCU6_) : /* jl$Qcondi$F0 $U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JL_L_U6_) : /* jl$_L$F0 $U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JL_S) : /* jl$_S [$R_b] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 2);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 2);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 2);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JL_L_R_R___RC_NOILINK_) : /* jl$_L$F0 [$RC_noilink] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, ((EQSI (FLD (f_op_C), 62)) ? (8) : (4)));
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, ((EQSI (FLD (f_op_C), 62)) ? (8) : (4)));
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, ((EQSI (FLD (f_op_C), 62)) ? (8) : (4)));
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JL_CC___RC_NOILINK_) : /* jl$Qcondi$F0 [$RC_noilink] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, ((EQSI (FLD (f_op_C), 62)) ? (8) : (4)));
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, ((EQSI (FLD (f_op_C), 62)) ? (8) : (4)));
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, ((EQSI (FLD (f_op_C), 62)) ? (8) : (4)));
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JL_L_S12_D_) : /* jl$_L$F0.d $s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JL_CCU6_D_) : /* jl$Qcondi$F0.d $U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JL_L_U6_D_) : /* jl$_L$F0.d $U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JL_L_R_R_D___RC_) : /* jl$_L$F0.d [$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JL_CC_D___RC_) : /* jl$Qcondi$F0.d [$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JL_S_D) : /* jl$_S.d [$R_b] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 2));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 2));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 2));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LP_L_S12_) : /* lp$_L$F0 $s12x2 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_lp_L_s12_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ SI opval = ADDSI (ANDSI (pc, -4), FLD (f_s12x2));
+ SET_H_AUXR (((UINT) 3), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_AUXR (((UINT) 2), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ SI opval = ADDSI (ANDSI (pc, -4), FLD (f_s12x2));
+ SET_H_AUXR (((UINT) 3), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_AUXR (((UINT) 2), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ SI opval = ADDSI (ANDSI (pc, -4), FLD (f_s12x2));
+ SET_H_AUXR (((UINT) 3), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_AUXR (((UINT) 2), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LPCC_CCU6) : /* lp$Qcondi$F0 $U6x2 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_lpcc_ccu6.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ SI opval = ADDSI (ANDSI (pc, -4), FLD (f_u6x2));
+ SET_H_AUXR (((UINT) 3), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_AUXR (((UINT) 2), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ SI opval = ADDSI (ANDSI (pc, -4), FLD (f_u6x2));
+ SET_H_AUXR (((UINT) 3), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_AUXR (((UINT) 2), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ SI opval = ADDSI (ANDSI (pc, -4), FLD (f_u6x2));
+ SET_H_AUXR (((UINT) 3), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_AUXR (((UINT) 2), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+}
+}
+} else {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = ADDSI (ANDSI (pc, -4), FLD (f_u6x2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = ADDSI (ANDSI (pc, -4), FLD (f_u6x2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = ADDSI (ANDSI (pc, -4), FLD (f_u6x2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FLAG_L_S12_) : /* flag$_L$F0 $s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (ANDSI (FLD (f_s12), 1)) {
+sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc, sim_exited, a5f_h_cr_get (current_cpu, 0));}
+ {
+ SI opval = FLD (f_s12);
+ SET_H_STATUS32 (((UINT) 0), opval);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FLAG_CCU6_) : /* flag$Qcondi$F0 $U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+if (ANDSI (FLD (f_u6), 1)) {
+sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc, sim_exited, a5f_h_cr_get (current_cpu, 0));}
+ {
+ SI opval = FLD (f_u6);
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FLAG_L_U6_) : /* flag$_L$F0 $U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (ANDSI (FLD (f_u6), 1)) {
+sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc, sim_exited, a5f_h_cr_get (current_cpu, 0));}
+ {
+ SI opval = FLD (f_u6);
+ SET_H_STATUS32 (((UINT) 0), opval);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FLAG_L_R_R__RC) : /* flag$_L$F0 $RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (ANDSI (GET_H_CR (FLD (f_op_C)), 1)) {
+sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc, sim_exited, a5f_h_cr_get (current_cpu, 0));}
+ {
+ SI opval = GET_H_CR (FLD (f_op_C));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FLAG_CC__RC) : /* flag$Qcondi$F0 $RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+if (ANDSI (GET_H_CR (FLD (f_op_C)), 1)) {
+sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc, sim_exited, a5f_h_cr_get (current_cpu, 0));}
+ {
+ SI opval = GET_H_CR (FLD (f_op_C));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LR_L_R_R___RC_) : /* lr$_L$F0 $RB,[$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ {
+ SI opval = GET_H_AUXR (GET_H_CR (FLD (f_op_C)));
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LR_L_S12_) : /* lr$_L$F0 $RB,[$s12] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ {
+ SI opval = GET_H_AUXR (FLD (f_s12));
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LR_L_U6_) : /* lr$_L$F0 $RB,[$U6] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ {
+ SI opval = GET_H_AUXR (FLD (f_u6));
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SR_L_R_R___RC_) : /* sr$_L$F0 $RB,[$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ {
+ SI opval = GET_H_CR (FLD (f_op_B));
+ SET_H_AUXR (GET_H_CR (FLD (f_op_C)), opval);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SR_L_S12_) : /* sr$_L$F0 $RB,[$s12] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ {
+ SI opval = GET_H_CR (FLD (f_op_B));
+ SET_H_AUXR (FLD (f_s12), opval);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SR_L_U6_) : /* sr$_L$F0 $RB,[$U6] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ {
+ SI opval = GET_H_CR (FLD (f_op_B));
+ SET_H_AUXR (FLD (f_u6), opval);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASL_L_R_R__RC) : /* asl$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASL_L_U6_) : /* asl$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (FLD (f_u6), FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (FLD (f_u6), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (FLD (f_u6), FLD (f_u6), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_ASL_S_GO) : /* asl$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ADDSI (tmp_C, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASR_L_R_R__RC) : /* asr$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SRASI (GET_H_CR (FLD (f_op_C)), 1);
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (GET_H_CR (FLD (f_op_C)), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASR_L_U6_) : /* asr$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SRASI (FLD (f_u6), 1);
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (FLD (f_u6), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_ASR_S_GO) : /* asr$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = SRASI (tmp_C, 1);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSR_L_R_R__RC) : /* lsr$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SRLSI (GET_H_CR (FLD (f_op_C)), 1);
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (GET_H_CR (FLD (f_op_C)), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSR_L_U6_) : /* lsr$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SRLSI (FLD (f_u6), 1);
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (FLD (f_u6), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_LSR_S_GO) : /* lsr$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = SRLSI (tmp_C, 1);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ROR_L_R_R__RC) : /* ror$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (SRLSI (GET_H_CR (FLD (f_op_C)), 1), SLLSI (GET_H_CR (FLD (f_op_C)), 31));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (GET_H_CR (FLD (f_op_C)), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ROR_L_U6_) : /* ror$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (SRLSI (FLD (f_u6), 1), SLLSI (FLD (f_u6), 31));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (FLD (f_u6), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RRC_L_R_R__RC) : /* rrc$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (SRLSI (GET_H_CR (FLD (f_op_C)), 1), SLLSI (ZEXTBISI (CPU (h_cbit)), 31));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (GET_H_CR (FLD (f_op_C)), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RRC_L_U6_) : /* rrc$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (SRLSI (FLD (f_u6), 1), SLLSI (ZEXTBISI (CPU (h_cbit)), 31));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (FLD (f_u6), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SEXB_L_R_R__RC) : /* sexb$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = EXTQISI ((GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SEXB_L_U6_) : /* sexb$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = EXTQISI ((FLD (f_u6)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_SEXB_S_GO) : /* sexb$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = EXTQISI ((tmp_C));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SEXW_L_R_R__RC) : /* sexw$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = EXTHISI ((GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SEXW_L_U6_) : /* sexw$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = EXTHISI ((FLD (f_u6)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_SEXW_S_GO) : /* sexw$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = EXTHISI ((tmp_C));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_EXTB_L_R_R__RC) : /* extb$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ZEXTQISI ((GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_EXTB_L_U6_) : /* extb$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ZEXTQISI ((FLD (f_u6)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_EXTB_S_GO) : /* extb$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ZEXTQISI ((tmp_C));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_EXTW_L_R_R__RC) : /* extw$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ZEXTHISI ((GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_EXTW_L_U6_) : /* extw$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ZEXTHISI ((FLD (f_u6)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_EXTW_S_GO) : /* extw$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ZEXTHISI ((tmp_C));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ABS_L_R_R__RC) : /* abs$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ABSSI (({ SI tmp_res;
+ tmp_res = GET_H_CR (FLD (f_op_C));
+; tmp_res; }));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI ((GET_H_CR (FLD (f_op_C))), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (GET_H_CR (FLD (f_op_C)), 0x80000000);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_vbit);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ABS_L_U6_) : /* abs$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ABSSI (({ SI tmp_res;
+ tmp_res = FLD (f_u6);
+; tmp_res; }));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI ((FLD (f_u6)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (FLD (f_u6), 0x80000000);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_vbit);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_ABS_S_GO) : /* abs$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ABSSI (({ SI tmp_res;
+ tmp_res = tmp_C;
+; tmp_res; }));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NOT_L_R_R__RC) : /* not$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = INVSI (GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NOT_L_U6_) : /* not$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = INVSI (FLD (f_u6));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_NOT_S_GO) : /* not$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = INVSI (tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RLC_L_R_R__RC) : /* rlc$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (SLLSI (GET_H_CR (FLD (f_op_C)), 1), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SRLSI (GET_H_CR (FLD (f_op_C)), 31);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RLC_L_U6_) : /* rlc$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (SLLSI (FLD (f_u6), 1), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SRLSI (FLD (f_u6), 31);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_NEG_S_GO) : /* neg$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = NEGSI (tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SWI) : /* swi */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+; /*clobber*/
+ {
+ USI opval = arc_trap (current_cpu, pc, 4, 0);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else if (0) {
+{
+; /*clobber*/
+ {
+ USI opval = arc_trap (current_cpu, pc, 4, 0);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+; /*clobber*/
+ {
+ USI opval = arc_trap (current_cpu, pc, 4, 0);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_TRAP_S) : /* trap$_S $trapnum */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_trap_s.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = arc_trap (current_cpu, pc, 2, FLD (f_trapnum));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+; /*clobber*/
+}
+}
+}
+ else if (0) {
+{
+ {
+ USI opval = arc_trap (current_cpu, pc, 2, FLD (f_trapnum));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+; /*clobber*/
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ {
+ USI opval = arc_trap (current_cpu, pc, 2, FLD (f_trapnum));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+; /*clobber*/
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BRK) : /* brk */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+arc_breakpoint (current_cpu, pc, 4);
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BRK_S) : /* brk_s */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+arc_breakpoint (current_cpu, pc, 2);
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASL_L_S12__RA_) : /* asl$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_s12), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_s12), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (32, ANDSI (FLD (f_s12), 31))), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASL_CCU6__RA_) : /* asl$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (32, ANDSI (FLD (f_u6), 31))), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASL_L_U6__RA_) : /* asl$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (32, ANDSI (FLD (f_u6), 31))), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASL_L_R_R__RA__RC) : /* asl$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (32, ANDSI (GET_H_CR (FLD (f_op_C)), 31))), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASL_CC__RA__RC) : /* asl$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (32, ANDSI (GET_H_CR (FLD (f_op_C)), 31))), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASL_S_CBU3) : /* asl$_S $R_c,$R_b,$u3 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u3);
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASL_S_SSB) : /* asl$_S $R_b,$R_b,$u5 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_ASLM_S_GO) : /* asl$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSR_L_S12__RA_) : /* lsr$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_s12), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_s12), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_s12), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSR_CCU6__RA_) : /* lsr$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_u6), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSR_L_U6__RA_) : /* lsr$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_u6), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSR_L_R_R__RA__RC) : /* lsr$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSR_CC__RA__RC) : /* lsr$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSR_S_SSB) : /* lsr$_S $R_b,$R_b,$u5 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_LSRM_S_GO) : /* lsr$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASR_L_S12__RA_) : /* asr$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_s12), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_s12), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_s12), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASR_CCU6__RA_) : /* asr$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_u6), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASR_L_U6__RA_) : /* asr$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_u6), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASR_L_R_R__RA__RC) : /* asr$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASR_CC__RA__RC) : /* asr$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASR_S_CBU3) : /* asr$_S $R_c,$R_b,$u3 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u3);
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASR_S_SSB) : /* asr$_S $R_b,$R_b,$u5 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_ASRM_S_GO) : /* asr$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ROR_L_S12__RA_) : /* ror$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (RORSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_s12), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_s12), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_s12), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ROR_CCU6__RA_) : /* ror$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (RORSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_u6), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ROR_L_U6__RA_) : /* ror$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (RORSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_u6), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ROR_L_R_R__RA__RC) : /* ror$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (RORSI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ROR_CC__RA__RC) : /* ror$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (RORSI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MUL64_L_S12_) : /* mul64$_L$F1 $RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_s12)));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MUL64_CCU6_) : /* mul64$Qcondi$F1 $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6)));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MUL64_L_U6_) : /* mul64$_L$F1 $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6)));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MUL64_L_R_R__RC) : /* mul64$_L$F1 $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MUL64_CC__RC) : /* mul64$Qcondi$F1 $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MUL64_S_GO) : /* mul64$_S $R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (EXTSIDI (GET_H_CR16 (FLD (f_op__b))), EXTSIDI (GET_H_CR16 (FLD (f_op__c))));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULU64_L_S12_) : /* mulu64$_L$F1 $RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_s12)));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULU64_CCU6_) : /* mulu64$Qcondi$F1 $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_u6)));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULU64_L_U6_) : /* mulu64$_L$F1 $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_u6)));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULU64_L_R_R__RC) : /* mulu64$_L$F1 $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (GET_H_CR (FLD (f_op_C))));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULU64_CC__RC) : /* mulu64$Qcondi$F1 $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (GET_H_CR (FLD (f_op_C))));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDS_L_S12__RA_) : /* adds$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = ADDDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_s12)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDS_CCU6__RA_) : /* adds$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = ADDDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDS_L_U6__RA_) : /* adds$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = ADDDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDS_L_R_R__RA__RC) : /* adds$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = ADDDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDS_CC__RA__RC) : /* adds$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = ADDDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBS_L_S12__RA_) : /* subs$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_s12)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBS_CCU6__RA_) : /* subs$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBS_L_U6__RA_) : /* subs$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBS_L_R_R__RA__RC) : /* subs$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBS_CC__RA__RC) : /* subs$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_DIVAW_L_S12__RA_) : /* divaw$_L$F0 $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ USI tmp_tmp;
+ tmp_tmp = SLLSI (GET_H_CR (FLD (f_op_B)), 1);
+; ((EQSI (ANDSI (SUBSI (tmp_tmp, FLD (f_s12)), 0x80000000), 0)) ? (ADDSI (SUBSI (tmp_tmp, FLD (f_s12)), 1)) : (tmp_tmp)); }));
+if (FLD (f_F)) {
+((void) 0); /*nop*/
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_DIVAW_CCU6__RA_) : /* divaw$Qcondi$F0 $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ USI tmp_tmp;
+ tmp_tmp = SLLSI (GET_H_CR (FLD (f_op_B)), 1);
+; ((EQSI (ANDSI (SUBSI (tmp_tmp, FLD (f_u6)), 0x80000000), 0)) ? (ADDSI (SUBSI (tmp_tmp, FLD (f_u6)), 1)) : (tmp_tmp)); }));
+if (FLD (f_F)) {
+((void) 0); /*nop*/
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_DIVAW_L_U6__RA_) : /* divaw$_L$F0 $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ USI tmp_tmp;
+ tmp_tmp = SLLSI (GET_H_CR (FLD (f_op_B)), 1);
+; ((EQSI (ANDSI (SUBSI (tmp_tmp, FLD (f_u6)), 0x80000000), 0)) ? (ADDSI (SUBSI (tmp_tmp, FLD (f_u6)), 1)) : (tmp_tmp)); }));
+if (FLD (f_F)) {
+((void) 0); /*nop*/
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_DIVAW_L_R_R__RA__RC) : /* divaw$_L$F0 $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ USI tmp_tmp;
+ tmp_tmp = SLLSI (GET_H_CR (FLD (f_op_B)), 1);
+; ((EQSI (ANDSI (SUBSI (tmp_tmp, GET_H_CR (FLD (f_op_C))), 0x80000000), 0)) ? (ADDSI (SUBSI (tmp_tmp, GET_H_CR (FLD (f_op_C))), 1)) : (tmp_tmp)); }));
+if (FLD (f_F)) {
+((void) 0); /*nop*/
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_DIVAW_CC__RA__RC) : /* divaw$Qcondi$F0 $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ USI tmp_tmp;
+ tmp_tmp = SLLSI (GET_H_CR (FLD (f_op_B)), 1);
+; ((EQSI (ANDSI (SUBSI (tmp_tmp, GET_H_CR (FLD (f_op_C))), 0x80000000), 0)) ? (ADDSI (SUBSI (tmp_tmp, GET_H_CR (FLD (f_op_C))), 1)) : (tmp_tmp)); }));
+if (FLD (f_F)) {
+((void) 0); /*nop*/
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASLS_L_S12__RA_) : /* asls$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((FLD (f_s12)), 31)) ? (SLLDI (tmp_b, 31)) : (LTSI ((FLD (f_s12)), -31)) ? (SRADI (tmp_b, 31)) : (GESI ((FLD (f_s12)), 0)) ? (SLLDI (tmp_b, (FLD (f_s12)))) : (SRASI (GET_H_CR (FLD (f_op_B)), NEGSI ((FLD (f_s12)))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASLS_CCU6__RA_) : /* asls$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((FLD (f_u6)), 31)) ? (SLLDI (tmp_b, 31)) : (LTSI ((FLD (f_u6)), -31)) ? (SRADI (tmp_b, 31)) : (GESI ((FLD (f_u6)), 0)) ? (SLLDI (tmp_b, (FLD (f_u6)))) : (SRASI (GET_H_CR (FLD (f_op_B)), NEGSI ((FLD (f_u6)))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASLS_L_U6__RA_) : /* asls$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((FLD (f_u6)), 31)) ? (SLLDI (tmp_b, 31)) : (LTSI ((FLD (f_u6)), -31)) ? (SRADI (tmp_b, 31)) : (GESI ((FLD (f_u6)), 0)) ? (SLLDI (tmp_b, (FLD (f_u6)))) : (SRASI (GET_H_CR (FLD (f_op_B)), NEGSI ((FLD (f_u6)))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASLS_L_R_R__RA__RC) : /* asls$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((GET_H_CR (FLD (f_op_C))), 31)) ? (SLLDI (tmp_b, 31)) : (LTSI ((GET_H_CR (FLD (f_op_C))), -31)) ? (SRADI (tmp_b, 31)) : (GESI ((GET_H_CR (FLD (f_op_C))), 0)) ? (SLLDI (tmp_b, (GET_H_CR (FLD (f_op_C))))) : (SRASI (GET_H_CR (FLD (f_op_B)), NEGSI ((GET_H_CR (FLD (f_op_C))))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASLS_CC__RA__RC) : /* asls$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((GET_H_CR (FLD (f_op_C))), 31)) ? (SLLDI (tmp_b, 31)) : (LTSI ((GET_H_CR (FLD (f_op_C))), -31)) ? (SRADI (tmp_b, 31)) : (GESI ((GET_H_CR (FLD (f_op_C))), 0)) ? (SLLDI (tmp_b, (GET_H_CR (FLD (f_op_C))))) : (SRASI (GET_H_CR (FLD (f_op_B)), NEGSI ((GET_H_CR (FLD (f_op_C))))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASRS_L_S12__RA_) : /* asrs$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((FLD (f_s12)), 31)) ? (SRADI (tmp_b, 31)) : (LTSI ((FLD (f_s12)), -31)) ? (SLLDI (tmp_b, 31)) : (GESI ((FLD (f_s12)), 0)) ? (SRADI (tmp_b, (FLD (f_s12)))) : (SLLSI (GET_H_CR (FLD (f_op_B)), NEGSI ((FLD (f_s12)))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASRS_CCU6__RA_) : /* asrs$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((FLD (f_u6)), 31)) ? (SRADI (tmp_b, 31)) : (LTSI ((FLD (f_u6)), -31)) ? (SLLDI (tmp_b, 31)) : (GESI ((FLD (f_u6)), 0)) ? (SRADI (tmp_b, (FLD (f_u6)))) : (SLLSI (GET_H_CR (FLD (f_op_B)), NEGSI ((FLD (f_u6)))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASRS_L_U6__RA_) : /* asrs$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((FLD (f_u6)), 31)) ? (SRADI (tmp_b, 31)) : (LTSI ((FLD (f_u6)), -31)) ? (SLLDI (tmp_b, 31)) : (GESI ((FLD (f_u6)), 0)) ? (SRADI (tmp_b, (FLD (f_u6)))) : (SLLSI (GET_H_CR (FLD (f_op_B)), NEGSI ((FLD (f_u6)))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASRS_L_R_R__RA__RC) : /* asrs$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((GET_H_CR (FLD (f_op_C))), 31)) ? (SRADI (tmp_b, 31)) : (LTSI ((GET_H_CR (FLD (f_op_C))), -31)) ? (SLLDI (tmp_b, 31)) : (GESI ((GET_H_CR (FLD (f_op_C))), 0)) ? (SRADI (tmp_b, (GET_H_CR (FLD (f_op_C))))) : (SLLSI (GET_H_CR (FLD (f_op_B)), NEGSI ((GET_H_CR (FLD (f_op_C))))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASRS_CC__RA__RC) : /* asrs$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((GET_H_CR (FLD (f_op_C))), 31)) ? (SRADI (tmp_b, 31)) : (LTSI ((GET_H_CR (FLD (f_op_C))), -31)) ? (SLLDI (tmp_b, 31)) : (GESI ((GET_H_CR (FLD (f_op_C))), 0)) ? (SRADI (tmp_b, (GET_H_CR (FLD (f_op_C))))) : (SLLSI (GET_H_CR (FLD (f_op_B)), NEGSI ((GET_H_CR (FLD (f_op_C))))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDSDW_L_S12__RA_) : /* addsdw$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((FLD (f_s12)), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((FLD (f_s12)), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDSDW_CCU6__RA_) : /* addsdw$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((FLD (f_u6)), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((FLD (f_u6)), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDSDW_L_U6__RA_) : /* addsdw$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((FLD (f_u6)), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((FLD (f_u6)), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDSDW_L_R_R__RA__RC) : /* addsdw$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDSDW_CC__RA__RC) : /* addsdw$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBSDW_L_S12__RA_) : /* subsdw$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((FLD (f_s12)), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((FLD (f_s12)), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBSDW_CCU6__RA_) : /* subsdw$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((FLD (f_u6)), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((FLD (f_u6)), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBSDW_L_U6__RA_) : /* subsdw$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((FLD (f_u6)), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((FLD (f_u6)), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBSDW_L_R_R__RA__RC) : /* subsdw$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBSDW_CC__RA__RC) : /* subsdw$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SWAP_L_R_R__RC) : /* swap$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (RORSI (GET_H_CR (FLD (f_op_C)), 16));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SWAP_L_U6_) : /* swap$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (RORSI (FLD (f_u6), 16));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NORM_L_R_R__RC) : /* norm$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_val;
+ SI tmp_bits;
+ tmp_val = ((GESI ((GET_H_CR (FLD (f_op_C))), 0)) ? ((GET_H_CR (FLD (f_op_C)))) : (INVSI ((GET_H_CR (FLD (f_op_C))))));
+; tmp_bits = 31;
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 4), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 4));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 4));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 3), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 3));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 3));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 2), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 2));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 2));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 1), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 1));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 1));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 0), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 0));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 0));
+}
+; tmp_bits; }));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NORM_L_U6_) : /* norm$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_val;
+ SI tmp_bits;
+ tmp_val = ((GESI ((FLD (f_u6)), 0)) ? ((FLD (f_u6))) : (INVSI ((FLD (f_u6)))));
+; tmp_bits = 31;
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 4), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 4));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 4));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 3), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 3));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 3));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 2), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 2));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 2));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 1), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 1));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 1));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 0), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 0));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 0));
+}
+; tmp_bits; }));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (FLD (f_u6), 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (FLD (f_u6), 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RND16_L_R_R__RC) : /* rnd16$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (({ DI tmp_tmp;
+ tmp_tmp = ADDDI (EXTSIDI (32768), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }), 16));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RND16_L_U6_) : /* rnd16$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (({ DI tmp_tmp;
+ tmp_tmp = ADDDI (EXTSIDI (32768), EXTSIDI (FLD (f_u6)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }), 16));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ABSSW_L_R_R__RC) : /* abssw$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_tmp;
+ tmp_tmp = ABSSI (EXTHISI ((GET_H_CR (FLD (f_op_C)))));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ABSSW_L_U6_) : /* abssw$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_tmp;
+ tmp_tmp = ABSSI (EXTHISI ((FLD (f_u6))));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ABSS_L_R_R__RC) : /* abss$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (((GESI ((GET_H_CR (FLD (f_op_C))), 0)) ? (GET_H_CR (FLD (f_op_C))) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (0), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }))));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ABSS_L_U6_) : /* abss$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (((GESI ((FLD (f_u6)), 0)) ? (FLD (f_u6)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (0), EXTSIDI (FLD (f_u6)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }))));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NEGSW_L_R_R__RC) : /* negsw$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_tmp;
+ tmp_tmp = EXTHISI ((GET_H_CR (FLD (f_op_C))));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NEGSW_L_U6_) : /* negsw$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_tmp;
+ tmp_tmp = EXTHISI ((FLD (f_u6)));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NEGS_L_R_R__RC) : /* negs$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (0), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NEGS_L_U6_) : /* negs$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (0), EXTSIDI (FLD (f_u6)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NORMW_L_R_R__RC) : /* normw$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_val;
+ SI tmp_bits;
+ tmp_val = ((GESI (ORSI (SLLSI (GET_H_CR (FLD (f_op_C)), 16), ANDSI (GET_H_CR (FLD (f_op_C)), 65535)), 0)) ? (ORSI (SLLSI (GET_H_CR (FLD (f_op_C)), 16), ANDSI (GET_H_CR (FLD (f_op_C)), 65535))) : (INVSI (ORSI (SLLSI (GET_H_CR (FLD (f_op_C)), 16), ANDSI (GET_H_CR (FLD (f_op_C)), 65535)))));
+; tmp_bits = 31;
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 4), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 4));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 4));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 3), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 3));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 3));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 2), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 2));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 2));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 1), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 1));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 1));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 0), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 0));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 0));
+}
+; tmp_bits; }));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NORMW_L_U6_) : /* normw$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_val;
+ SI tmp_bits;
+ tmp_val = ((GESI (ORSI (SLLSI (FLD (f_u6), 16), ANDSI (FLD (f_u6), 65535)), 0)) ? (ORSI (SLLSI (FLD (f_u6), 16), ANDSI (FLD (f_u6), 65535))) : (INVSI (ORSI (SLLSI (FLD (f_u6), 16), ANDSI (FLD (f_u6), 65535)))));
+; tmp_bits = 31;
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 4), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 4));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 4));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 3), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 3));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 3));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 2), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 2));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 2));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 1), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 1));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 1));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 0), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 0));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 0));
+}
+; tmp_bits; }));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NOP_S) : /* nop_s */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_UNIMP_S) : /* unimp_s */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+cgen_rtx_error (current_cpu, "invalid insn");
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_POP_S_B) : /* pop$_S $R_b */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ SI opval = GETMEMSI (current_cpu, pc, GET_H_SP ());
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (GET_H_SP (), 4);
+ SET_H_SP (, opval);
+ TRACE_RESULT (current_cpu, abuf, "sp", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_POP_S_BLINK) : /* pop$_S $R31 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ SI opval = GETMEMSI (current_cpu, pc, GET_H_SP ());
+ SET_H_R31 (, opval);
+ TRACE_RESULT (current_cpu, abuf, "r31", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (GET_H_SP (), 4);
+ SET_H_SP (, opval);
+ TRACE_RESULT (current_cpu, abuf, "sp", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_PUSH_S_B) : /* push$_S $R_b */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ SI opval = ADDSI (GET_H_SP (), -4);
+ SET_H_SP (, opval);
+ TRACE_RESULT (current_cpu, abuf, "sp", 'x', opval);
+ }
+ {
+ SI opval = GET_H_CR16 (FLD (f_op__b));
+ SETMEMSI (current_cpu, pc, GET_H_SP (), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_PUSH_S_BLINK) : /* push$_S $R31 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ SI opval = ADDSI (GET_H_SP (), -4);
+ SET_H_SP (, opval);
+ TRACE_RESULT (current_cpu, abuf, "sp", 'x', opval);
+ }
+ {
+ SI opval = GET_H_R31 ();
+ SETMEMSI (current_cpu, pc, GET_H_SP (), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULLW_L_S12__RA_) : /* mullw$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_s12), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULLW_CCU6__RA_) : /* mullw$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_u6), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULLW_L_U6__RA_) : /* mullw$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_u6), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULLW_L_R_R__RA__RC) : /* mullw$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULLW_CC__RA__RC) : /* mullw$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACLW_L_S12__RA_) : /* maclw$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ SI tmp_SItmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_s12), 65535))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; {
+ BI opval = ANDBI (CPU (h_vbit), SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; if (NEBI (CPU (h_vbit), 0)) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; tmp_SItmp = ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp));
+; tmp_cur_s1bit = ORBI (tmp_cur_s1bit, CPU (h_vbit));
+; tmp_SItmp; });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACLW_CCU6__RA_) : /* maclw$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ SI tmp_SItmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_u6), 65535))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; {
+ BI opval = ANDBI (CPU (h_vbit), SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; if (NEBI (CPU (h_vbit), 0)) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; tmp_SItmp = ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp));
+; tmp_cur_s1bit = ORBI (tmp_cur_s1bit, CPU (h_vbit));
+; tmp_SItmp; });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACLW_L_U6__RA_) : /* maclw$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ SI tmp_SItmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_u6), 65535))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; {
+ BI opval = ANDBI (CPU (h_vbit), SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; if (NEBI (CPU (h_vbit), 0)) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; tmp_SItmp = ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp));
+; tmp_cur_s1bit = ORBI (tmp_cur_s1bit, CPU (h_vbit));
+; tmp_SItmp; });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACLW_L_R_R__RA__RC) : /* maclw$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ SI tmp_SItmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), 65535))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; {
+ BI opval = ANDBI (CPU (h_vbit), SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; if (NEBI (CPU (h_vbit), 0)) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; tmp_SItmp = ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp));
+; tmp_cur_s1bit = ORBI (tmp_cur_s1bit, CPU (h_vbit));
+; tmp_SItmp; });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACLW_CC__RA__RC) : /* maclw$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ SI tmp_SItmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), 65535))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; {
+ BI opval = ANDBI (CPU (h_vbit), SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; if (NEBI (CPU (h_vbit), 0)) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; tmp_SItmp = ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp));
+; tmp_cur_s1bit = ORBI (tmp_cur_s1bit, CPU (h_vbit));
+; tmp_SItmp; });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACHLW_L_S12__RA_) : /* machlw$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_s12), -65536))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = ANDBI (CPU (h_vbit), XORDI (tmp_old, tmp_tmp));
+; if (tmp_cur_s1bit) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACHLW_CCU6__RA_) : /* machlw$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_u6), -65536))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = ANDBI (CPU (h_vbit), XORDI (tmp_old, tmp_tmp));
+; if (tmp_cur_s1bit) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACHLW_L_U6__RA_) : /* machlw$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_u6), -65536))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = ANDBI (CPU (h_vbit), XORDI (tmp_old, tmp_tmp));
+; if (tmp_cur_s1bit) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACHLW_L_R_R__RA__RC) : /* machlw$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), -65536))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = ANDBI (CPU (h_vbit), XORDI (tmp_old, tmp_tmp));
+; if (tmp_cur_s1bit) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACHLW_CC__RA__RC) : /* machlw$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), -65536))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = ANDBI (CPU (h_vbit), XORDI (tmp_old, tmp_tmp));
+; if (tmp_cur_s1bit) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULULW_L_S12__RA_) : /* mululw$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (FLD (f_s12), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULULW_CCU6__RA_) : /* mululw$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (FLD (f_u6), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULULW_L_U6__RA_) : /* mululw$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (FLD (f_u6), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULULW_L_R_R__RA__RC) : /* mululw$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULULW_CC__RA__RC) : /* mululw$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACHULW_L_S12__RA_) : /* machulw$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (FLD (f_s12), -65536))));
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = (GTUDI (tmp_old, tmp_tmp)) ? (( tmp_tmp = -1, 1)) : (0);
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACHULW_CCU6__RA_) : /* machulw$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (FLD (f_u6), -65536))));
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = (GTUDI (tmp_old, tmp_tmp)) ? (( tmp_tmp = -1, 1)) : (0);
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACHULW_L_U6__RA_) : /* machulw$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (FLD (f_u6), -65536))));
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = (GTUDI (tmp_old, tmp_tmp)) ? (( tmp_tmp = -1, 1)) : (0);
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACHULW_L_R_R__RA__RC) : /* machulw$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), -65536))));
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = (GTUDI (tmp_old, tmp_tmp)) ? (( tmp_tmp = -1, 1)) : (0);
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACHULW_CC__RA__RC) : /* machulw$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), -65536))));
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = (GTUDI (tmp_old, tmp_tmp)) ? (( tmp_tmp = -1, 1)) : (0);
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CURRENT_LOOP_END) : /* */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDBI (EQSI (pc, GET_H_AUXR (((UINT) 3))), NOTBI (CPU (h_lbit)))) {
+{
+ {
+ SI opval = ADDSI (GET_H_CR (((UINT) 60)), -1);
+ SET_H_CR (((UINT) 60), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GET_H_CR (((UINT) 60))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (GET_H_AUXR (((UINT) 2)), 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = GET_H_AUXR (((UINT) 2));
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CURRENT_LOOP_END_AFTER_BRANCH) : /* */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (
+#ifdef SEM_IN_SWITCH
+pbb_br_type != SEM_BRANCH_UNTAKEN
+#else
+CPU_PBB_BR_NPC (current_cpu) != SEM_BRANCH_UNTAKEN
+#endif
+) {
+
+#ifdef SEM_IN_SWITCH
+npc = pbb_br_npc; br_type = pbb_br_type;
+#else
+npc = CPU_PBB_BR_NPC (current_cpu); br_type = CPU_PBB_BR_TYPE (current_cpu);
+#endif
+}
+ else if (ANDBI (EQSI (pc, GET_H_AUXR (((UINT) 3))), NOTBI (CPU (h_lbit)))) {
+{
+ {
+ SI opval = ADDSI (GET_H_CR (((UINT) 60)), -1);
+ SET_H_CR (((UINT) 60), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GET_H_CR (((UINT) 60))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (GET_H_AUXR (((UINT) 2)), 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = GET_H_AUXR (((UINT) 2));
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ARC600_CURRENT_LOOP_END_AFTER_BRANCH) : /* */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (
+#ifdef SEM_IN_SWITCH
+pbb_br_type != SEM_BRANCH_UNTAKEN
+#else
+CPU_PBB_BR_NPC (current_cpu) != SEM_BRANCH_UNTAKEN
+#endif
+) {
+{
+
+#ifdef SEM_IN_SWITCH
+npc = pbb_br_npc; br_type = pbb_br_type;
+#else
+npc = CPU_PBB_BR_NPC (current_cpu); br_type = CPU_PBB_BR_TYPE (current_cpu);
+#endif
+ {
+ SI opval = ADDSI (GET_H_CR (((UINT) 60)), -1);
+ SET_H_CR (((UINT) 60), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+ else if (ANDBI (EQSI (pc, GET_H_AUXR (((UINT) 3))), NOTBI (CPU (h_lbit)))) {
+{
+ {
+ SI opval = ADDSI (GET_H_CR (((UINT) 60)), -1);
+ SET_H_CR (((UINT) 60), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GET_H_CR (((UINT) 60))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (GET_H_AUXR (((UINT) 2)), 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = GET_H_AUXR (((UINT) 2));
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+
+ }
+ ENDSWITCH (sem) /* End of semantic switch. */
+
+ /* At this point `vpc' contains the next insn to execute. */
+}
+
+#undef DEFINE_SWITCH
+#endif /* DEFINE_SWITCH */
diff --git a/sim/arc/sem6.c b/sim/arc/sem6.c
new file mode 100644
index 0000000..1e863ef
--- /dev/null
+++ b/sim/arc/sem6.c
@@ -0,0 +1,33906 @@
+/* Simulator instruction semantics for arc600f.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2007 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#define WANT_CPU arc600f
+#define WANT_CPU_ARC600F
+
+#include "sim-main.h"
+#include "cgen-mem.h"
+#include "cgen-ops.h"
+
+#undef GET_ATTR
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
+#else
+#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr)
+#endif
+
+/* This is used so that we can compile two copies of the semantic code,
+ one with full feature support and one without that runs fast(er).
+ FAST_P, when desired, is defined on the command line, -DFAST_P=1. */
+#if FAST_P
+#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_semf_,fn)
+#undef TRACE_RESULT
+#define TRACE_RESULT(cpu, abuf, name, type, val)
+#else
+#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_sem_,fn)
+#endif
+
+/* x-invalid: --invalid-- */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,x_invalid) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+ /* Update the recorded pc in the cpu state struct.
+ Only necessary for WITH_SCACHE case, but to avoid the
+ conditional compilation .... */
+ SET_H_PC (pc);
+ /* Virtual insns have zero size. Overwrite vpc with address of next insn
+ using the default-insn-bitsize spec. When executing insns in parallel
+ we may want to queue the fault and continue execution. */
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+ vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* x-after: --after-- */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,x_after) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_ARC600F
+ arc600f_pbb_after (current_cpu, sem_arg);
+#endif
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* x-before: --before-- */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,x_before) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_ARC600F
+ arc600f_pbb_before (current_cpu, sem_arg);
+#endif
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* x-cti-chain: --cti-chain-- */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_ARC600F
+#ifdef DEFINE_SWITCH
+ vpc = arc600f_pbb_cti_chain (current_cpu, sem_arg,
+ pbb_br_type, pbb_br_npc);
+ BREAK (sem);
+#else
+ /* FIXME: Allow provision of explicit ifmt spec in insn spec. */
+ vpc = arc600f_pbb_cti_chain (current_cpu, sem_arg,
+ CPU_PBB_BR_TYPE (current_cpu),
+ CPU_PBB_BR_NPC (current_cpu));
+#endif
+#endif
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* x-chain: --chain-- */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,x_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_ARC600F
+ vpc = arc600f_pbb_chain (current_cpu, sem_arg);
+#ifdef DEFINE_SWITCH
+ BREAK (sem);
+#endif
+#endif
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* x-begin: --begin-- */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_ARC600F
+#if defined DEFINE_SWITCH || defined FAST_P
+ /* In the switch case FAST_P is a constant, allowing several optimizations
+ in any called inline functions. */
+ vpc = arc600f_pbb_begin (current_cpu, FAST_P);
+#else
+#if 0 /* cgen engine can't handle dynamic fast/full switching yet. */
+ vpc = arc600f_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
+#else
+ vpc = arc600f_pbb_begin (current_cpu, 0);
+#endif
+#endif
+#endif
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* b_s: b$i2cond $label10 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,b_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_b_s.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GET_H_I2COND (FLD (f_cond_i2))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = FLD (i_label10);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = FLD (i_label10);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = FLD (i_label10);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* bcc_s: b$i3cond$_S $label7 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,bcc_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bcc_s.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GET_H_I3COND (FLD (f_cond_i3))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = FLD (i_label7);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = FLD (i_label7);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = FLD (i_label7);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* brcc_s: br$RccS$_S $R_b,0,$label8 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,brcc_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_brcc_s.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if ((FLD (f_brscond) == 0) ? (EQSI (GET_H_CR16 (FLD (f_op__b)), 0)) : (FLD (f_brscond) == 1) ? (NESI (GET_H_CR16 (FLD (f_op__b)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = FLD (i_label8);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = FLD (i_label8);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = FLD (i_label8);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* bcc_l: b$Qcondb$_L $label21 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,bcc_l) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bcc_l.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+((void) 0); /*nop*/
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = FLD (i_label21);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = FLD (i_label21);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = FLD (i_label21);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* bcc_l.d: b$Qcondb$_L.d $label21 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,bcc_l_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bcc_l.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+((void) 0); /*nop*/
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (i_label21);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else if (1) {
+{
+ {
+ USI opval = FLD (i_label21);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ {
+ USI opval = FLD (i_label21);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* b_l: b$uncondb$_L $label25 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,b_l) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_b_l.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = FLD (i_label25);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = FLD (i_label25);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = FLD (i_label25);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* b_l.d: b$uncondb$_L.d $label25 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,b_l_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_b_l.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (i_label25);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else if (1) {
+{
+ {
+ USI opval = FLD (i_label25);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ {
+ USI opval = FLD (i_label25);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* brcc_RC: b$Rcc $RB,$RC,$label9 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,brcc_RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_brcc_RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* brcc_RC.d: b$Rcc.d $RB,$RC,$label9 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,brcc_RC_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_brcc_RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+{
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+{
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+{
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* brcc_U6: b$Rcc $RB,$U6,$label9 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,brcc_U6) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_brcc_U6.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* brcc_U6.d: b$Rcc.d $RB,$U6,$label9 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,brcc_U6_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_brcc_U6.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+{
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+{
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+{
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* bl_s: bl$uncondj$_S $label13a */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,bl_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bl_s.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ {
+ SI opval = ADDSI (pc, 2);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label13a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else if (0) {
+{
+ {
+ SI opval = ADDSI (pc, 2);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label13a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ {
+ SI opval = ADDSI (pc, 2);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label13a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* blcc: bl$Qcondj$_L $label21 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,blcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_blcc.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+((void) 0); /*nop*/
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label21a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else if (0) {
+{
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label21a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label21a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* blcc.d: bl$Qcondj$_L.d $label21 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,blcc_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_blcc.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+((void) 0); /*nop*/
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+{
+ {
+ USI opval = FLD (i_label21a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+{
+ {
+ USI opval = FLD (i_label21a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+{
+ {
+ USI opval = FLD (i_label21a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* bl: bl$uncondj$_L $label25a */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,bl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bl.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label25a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else if (0) {
+{
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label25a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label25a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* bl.d: bl$uncondj$_L.d $label25a */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,bl_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bl.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (i_label25a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (i_label25a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (i_label25a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* ld_abs: ld$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ld_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ld$_AW_abs: ld$_AW$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ld__AW_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ld.ab_abs: ld.ab$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ld_ab_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ld.as_abs: ld.as$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ld_as_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s9), 2));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ld_abc: ld$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ld_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ld$_AW_abc: ld$_AW$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ld__AW_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ld.ab_abc: ld.ab$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ld_ab_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ld.as_abc: ld.as$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ld_as_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 2));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ld_s_abc: ld$_S $R_a,[$R_b,$R_c] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ld_s_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), GET_H_CR16 (FLD (f_op__c)));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR16 (FLD (f_op__a), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ld_s_abu: ld$_S $R_c,[$R_b,$sc_u5_] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ld_s_abu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), FLD (f_u5x4));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ld_s_absp: ld$_S $R_b,[$SP,$u5x4] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ld_s_absp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_SP (), FLD (f_u5x4));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ld_s_gprel: ld$_S $R_b,[$GP,$sc_s9_] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ld_s_gprel) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_gprel.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_GP (), FLD (f_s9x4));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_R0 (, opval);
+ TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ld_s_pcrel: ld$_S $R_b,[$PCL,$u8x4] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ld_s_pcrel) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_pcrel.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (ANDSI (pc, -4), FLD (f_u8x4));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb_abs: ldb$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ldb_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb$_AW_abs: ldb$_AW$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ldb__AW_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb.ab_abs: ldb.ab$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ldb_ab_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb.as_abs: ldb.as$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ldb_as_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), (cgen_rtx_error (current_cpu, "invalid insn"), 0));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb_abc: ldb$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ldb_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb$_AW_abc: ldb$_AW$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ldb__AW_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb.ab_abc: ldb.ab$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ldb_ab_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb.as_abc: ldb.as$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ldb_as_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), (cgen_rtx_error (current_cpu, "invalid insn"), 0));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb_s_abc: ldb$_S $R_a,[$R_b,$R_c] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ldb_s_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), GET_H_CR16 (FLD (f_op__c)));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR16 (FLD (f_op__a), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb_s_abu: ldb$_S $R_c,[$R_b,$sc_u5b] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ldb_s_abu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), FLD (f_u5));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb_s_absp: ldb$_S $R_b,[$SP,$u5x4] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ldb_s_absp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_SP (), FLD (f_u5x4));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb_s_gprel: ldb$_S $R_b,[$GP,$sc_s9b] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ldb_s_gprel) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_gprel.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_GP (), FLD (f_s9x1));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_R0 (, opval);
+ TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb.x_abs: ldb.x$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ldb_x_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb$_AW.x_abs: ldb$_AW.x$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ldb__AW_x_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb.ab.x_abs: ldb.ab.x$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ldb_ab_x_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb.as.x_abs: ldb.as.x$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ldb_as_x_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), (cgen_rtx_error (current_cpu, "invalid insn"), 0));
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb.x_abc: ldb.x$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ldb_x_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb$_AW.x_abc: ldb$_AW.x$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ldb__AW_x_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb.ab.x_abc: ldb.ab.x$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ldb_ab_x_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb.as.x_abc: ldb.as.x$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ldb_as_x_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), (cgen_rtx_error (current_cpu, "invalid insn"), 0));
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw_abs: ldw$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ldw_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw$_AW_abs: ldw$_AW$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ldw__AW_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw.ab_abs: ldw.ab$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ldw_ab_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw.as_abs: ldw.as$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ldw_as_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s9), 1));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw_abc: ldw$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ldw_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw$_AW_abc: ldw$_AW$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ldw__AW_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw.ab_abc: ldw.ab$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ldw_ab_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw.as_abc: ldw.as$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ldw_as_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 1));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw_s_abc: ldw$_S $R_a,[$R_b,$R_c] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ldw_s_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), GET_H_CR16 (FLD (f_op__c)));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR16 (FLD (f_op__a), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw_s_abu: ldw$_S $R_c,[$R_b,$sc_u5w] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ldw_s_abu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldw_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), FLD (f_u5x2));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw_s_gprel: ldw$_S $R_b,[$GP,$sc_s9w] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ldw_s_gprel) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldw_s_gprel.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_GP (), FLD (f_s9x2));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_R0 (, opval);
+ TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw.x_abs: ldw.x$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ldw_x_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw$_AW.x_abs: ldw$_AW.x$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ldw__AW_x_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw.ab.x_abs: ldw.ab.x$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ldw_ab_x_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw.as.x_abs: ldw.as.x$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ldw_as_x_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s9), 1));
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw.x_abc: ldw.x$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ldw_x_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw$_AW.x_abc: ldw$_AW.x$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ldw__AW_x_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw.ab.x_abc: ldw.ab.x$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ldw_ab_x_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw.as.x_abc: ldw.as.x$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ldw_as_x_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 1));
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw_s.x_abu: ldw$_S.x $R_c,[$R_b,$sc_u5w] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ldw_s_x_abu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldw_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), FLD (f_u5x2));
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* st_abs: st$STODi $RC,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,st_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMSI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* st$_AW_abs: st$_AW$STODi $RC,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,st__AW_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMSI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* st.ab_abs: st.ab$STODi $RC,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,st_ab_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMSI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* st.as_abs: st.as$STODi $RC,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,st_as_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s9), 2));
+ {
+ SI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMSI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* st_s_abu: st$_S $R_c,[$R_b,$sc_u5_] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,st_s_abu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), FLD (f_u5x4));
+ {
+ SI opval = GET_H_CR16 (FLD (f_op__c));
+ SETMEMSI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* st_s_absp: st$_S $R_b,[$SP,$u5x4] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,st_s_absp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_SP (), FLD (f_u5x4));
+ {
+ SI opval = GET_H_CR16 (FLD (f_op__b));
+ SETMEMSI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* stb_abs: stb$STODi $RC,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,stb_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ QI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMQI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* stb$_AW_abs: stb$_AW$STODi $RC,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,stb__AW_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ QI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMQI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* stb.ab_abs: stb.ab$STODi $RC,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,stb_ab_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ QI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMQI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* stb.as_abs: stb.as$STODi $RC,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,stb_as_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), (cgen_rtx_error (current_cpu, "invalid insn"), 0));
+ {
+ QI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMQI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* stb_s_abu: stb$_S $R_c,[$R_b,$sc_u5b] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,stb_s_abu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), FLD (f_u5));
+ {
+ QI opval = GET_H_CR16 (FLD (f_op__c));
+ SETMEMQI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* stb_s_absp: stb$_S $R_b,[$SP,$u5x4] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,stb_s_absp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_SP (), FLD (f_u5x4));
+ {
+ QI opval = GET_H_CR16 (FLD (f_op__b));
+ SETMEMQI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* stw_abs: stw$STODi $RC,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,stw_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ HI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMHI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* stw$_AW_abs: stw$_AW$STODi $RC,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,stw__AW_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ HI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMHI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* stw.ab_abs: stw.ab$STODi $RC,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,stw_ab_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ HI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMHI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* stw.as_abs: stw.as$STODi $RC,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,stw_as_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s9), 1));
+ {
+ HI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMHI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* stw_s_abu: stw$_S $R_c,[$R_b,$sc_u5w] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,stw_s_abu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldw_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), FLD (f_u5x2));
+ {
+ HI opval = GET_H_CR16 (FLD (f_op__c));
+ SETMEMHI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* add_L_s12 $RA,: add$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,add_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add_ccu6 $RA,: add$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,add_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add_L_u6 $RA,: add$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,add_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add_L_r_r $RA,$RC: add$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,add_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add_cc $RA,$RC: add$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,add_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add_s_abc: add$_S $R_a,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,add_s_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ADDSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__a), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* add_s_cbu3: add$_S $R_c,$R_b,$u3 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,add_s_cbu3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u3);
+ {
+ SI opval = ADDSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* add_s_mcah: add$_S $R_b,$R_b,$Rh */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,add_s_mcah) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+{
+if (EQSI (FLD (f_op_h), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 2));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (2, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_h), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR (FLD (f_op_h));
+ {
+ SI opval = ADDSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* add_s_absp: add$_S $R_b,$SP,$u5x4 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,add_s_absp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_SP ();
+ tmp_C = FLD (f_u5x4);
+ {
+ SI opval = ADDSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* add_s_asspsp: add$_S $SP,$SP,$u5x4 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,add_s_asspsp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_SP ();
+ tmp_C = FLD (f_u5x4);
+ {
+ SI opval = ADDSI (tmp_B, tmp_C);
+ SET_H_SP (, opval);
+ TRACE_RESULT (current_cpu, abuf, "sp", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* add_s_gp: add$_S $R0,$GP,$s9x4 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,add_s_gp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_gprel.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_GP ();
+ tmp_C = FLD (f_s9x4);
+ {
+ SI opval = ADDSI (tmp_B, tmp_C);
+ SET_H_R0 (, opval);
+ TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* add_s_r_u7: add$_S $R_b,$R_b,$u7 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,add_s_r_u7) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_r_u7.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u7);
+ {
+ SI opval = ADDSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* adc_L_s12 $RA,: adc$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,adc_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDCSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* adc_ccu6 $RA,: adc$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,adc_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDCSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* adc_L_u6 $RA,: adc$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,adc_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDCSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* adc_L_r_r $RA,$RC: adc$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,adc_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDCSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* adc_cc $RA,$RC: adc$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,adc_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDCSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub_L_s12 $RA,: sub$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,sub_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub_ccu6 $RA,: sub$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,sub_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub_L_u6 $RA,: sub$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,sub_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub_L_r_r $RA,$RC: sub$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,sub_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub_cc $RA,$RC: sub$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,sub_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub_s_cbu3: sub$_S $R_c,$R_b,$u3 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,sub_s_cbu3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u3);
+ {
+ SI opval = SUBSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_SUB_s_go: sub$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,I16_GO_SUB_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = SUBSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* sub_s_go_sub_ne: sub$_S $NE$R_b,$R_b,$R_b */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,sub_s_go_sub_ne) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQBI (CPU (h_zbit), 0)) {
+ {
+ SI opval = 0;
+ SET_H_CR16 (FLD (f_op__b), opval);
+ written |= (1 << 1);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub_s_ssb: sub$_S $R_b,$R_b,$u5 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,sub_s_ssb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ {
+ SI opval = SUBSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* sub_s_asspsp: sub$_S $SP,$SP,$u5x4 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,sub_s_asspsp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_SP ();
+ tmp_C = FLD (f_u5x4);
+ {
+ SI opval = SUBSI (tmp_B, tmp_C);
+ SET_H_SP (, opval);
+ TRACE_RESULT (current_cpu, abuf, "sp", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* sbc_L_s12 $RA,: sbc$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,sbc_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBCSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sbc_ccu6 $RA,: sbc$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,sbc_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBCSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sbc_L_u6 $RA,: sbc$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,sbc_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBCSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sbc_L_r_r $RA,$RC: sbc$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,sbc_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBCSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sbc_cc $RA,$RC: sbc$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,sbc_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBCSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* and_L_s12 $RA,: and$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,and_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* and_ccu6 $RA,: and$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,and_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* and_L_u6 $RA,: and$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,and_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* and_L_r_r $RA,$RC: and$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,and_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* and_cc $RA,$RC: and$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,and_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_AND_s_go: and$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,I16_GO_AND_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ANDSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* or_L_s12 $RA,: or$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,or_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* or_ccu6 $RA,: or$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,or_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* or_L_u6 $RA,: or$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,or_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* or_L_r_r $RA,$RC: or$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,or_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* or_cc $RA,$RC: or$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,or_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_OR_s_go: or$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,I16_GO_OR_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ORSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* bic_L_s12 $RA,: bic$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,bic_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (FLD (f_s12)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bic_ccu6 $RA,: bic$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,bic_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (FLD (f_u6)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bic_L_u6 $RA,: bic$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,bic_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (FLD (f_u6)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bic_L_r_r $RA,$RC: bic$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,bic_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bic_cc $RA,$RC: bic$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,bic_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_BIC_s_go: bic$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,I16_GO_BIC_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ANDSI (tmp_B, INVSI (tmp_C));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* xor_L_s12 $RA,: xor$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,xor_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* xor_ccu6 $RA,: xor$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,xor_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* xor_L_u6 $RA,: xor$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,xor_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* xor_L_r_r $RA,$RC: xor$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,xor_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* xor_cc $RA,$RC: xor$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,xor_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_XOR_s_go: xor$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,I16_GO_XOR_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = XORSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* max_L_s12 $RA,: max$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,max_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (GTSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12))) ? (GET_H_CR (FLD (f_op_B))) : (FLD (f_s12));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = GESI (FLD (f_s12), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* max_ccu6 $RA,: max$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,max_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (GTSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6))) ? (GET_H_CR (FLD (f_op_B))) : (FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = GESI (FLD (f_u6), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* max_L_u6 $RA,: max$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,max_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (GTSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6))) ? (GET_H_CR (FLD (f_op_B))) : (FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = GESI (FLD (f_u6), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* max_L_r_r $RA,$RC: max$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,max_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (GTSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)))) ? (GET_H_CR (FLD (f_op_B))) : (GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = GESI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* max_cc $RA,$RC: max$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,max_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (GTSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)))) ? (GET_H_CR (FLD (f_op_B))) : (GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = GESI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* min_L_s12 $RA,: min$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,min_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (LTSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12))) ? (GET_H_CR (FLD (f_op_B))) : (FLD (f_s12));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = LESI (FLD (f_s12), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* min_ccu6 $RA,: min$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,min_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (LTSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6))) ? (GET_H_CR (FLD (f_op_B))) : (FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = LESI (FLD (f_u6), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* min_L_u6 $RA,: min$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,min_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (LTSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6))) ? (GET_H_CR (FLD (f_op_B))) : (FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = LESI (FLD (f_u6), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* min_L_r_r $RA,$RC: min$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,min_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (LTSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)))) ? (GET_H_CR (FLD (f_op_B))) : (GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = LESI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* min_cc $RA,$RC: min$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,min_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (LTSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)))) ? (GET_H_CR (FLD (f_op_B))) : (GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = LESI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mov_L_s12 : mov$_L$F $RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mov_L_s12_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+ tmp_result = FLD (f_s12);
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GTSI (FLD (f_F), 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mov_ccu6 : mov$Qcondi$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mov_ccu6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+((void) 0); /*nop*/
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+ tmp_result = FLD (f_u6);
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GTSI (FLD (f_F), 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 5);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mov_L_u6 : mov$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mov_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+ tmp_result = FLD (f_u6);
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GTSI (FLD (f_F), 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mov_L_r_r $RC: mov$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mov_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = GET_H_CR (FLD (f_op_C));
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GTSI (FLD (f_F), 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mov_cc $RC: mov$Qcondi$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mov_cc__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+ tmp_result = GET_H_CR (FLD (f_op_C));
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GTSI (FLD (f_F), 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mov_s_mcah: mov$_S $R_b,$Rh */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mov_s_mcah) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_h), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 2));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (2, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_h), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = GET_H_CR (FLD (f_op_h));
+ {
+ SI opval = tmp_result;
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+if (GTSI (-1, 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mov_s_mcahb: mov$_S $Rh,$R_b */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mov_s_mcahb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+ tmp_result = GET_H_CR16 (FLD (f_op__b));
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_h), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GTSI (-1, 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mov_s_r_u7: mov$_S $R_b,$u7 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mov_s_r_u7) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+ tmp_result = FLD (f_u8);
+ {
+ SI opval = tmp_result;
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+if (GTSI (-1, 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* tst_L_s12 : tst$_L$F1 $RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,tst_L_s12_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_s12);
+ tmp_result = ANDSI (tmp_B, tmp_C);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* tst_ccu6 : tst$Qcondi$F1 $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,tst_ccu6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+ tmp_result = ANDSI (tmp_B, tmp_C);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* tst_L_u6 : tst$_L$F1 $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,tst_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+ tmp_result = ANDSI (tmp_B, tmp_C);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* tst_L_r_r $RC: tst$_L$F1 $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,tst_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+ tmp_result = ANDSI (tmp_B, tmp_C);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* tst_cc $RC: tst$Qcondi$F1 $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,tst_cc__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+ tmp_result = ANDSI (tmp_B, tmp_C);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* tst_s_go: tst$_S $R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,tst_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ tmp_result = ANDSI (tmp_B, tmp_C);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* cmp_L_s12 : cmp$_L$F1 $RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,cmp_L_s12_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (FLD (f_s12));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (FLD (f_s12));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* cmp_ccu6 : cmp$Qcondi$F1 $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,cmp_ccu6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* cmp_L_u6 : cmp$_L$F1 $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,cmp_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* cmp_L_r_r $RC: cmp$_L$F1 $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,cmp_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* cmp_cc $RC: cmp$Qcondi$F1 $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,cmp_cc__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* cmp_s_mcah: cmp$_S $R_b,$Rh */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,cmp_s_mcah) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+{
+if (EQSI (FLD (f_op_h), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 2));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (2, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_h), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = EXTSIDI (GET_H_CR16 (FLD (f_op__b)));
+ tmp_C = EXTSIDI (GET_H_CR (FLD (f_op_h)));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR16 (FLD (f_op__b)));
+ tmp_C = ZEXTSIDI (GET_H_CR (FLD (f_op_h)));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* cmp_s_r_u7: cmp$_S $R_b,$u7 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,cmp_s_r_u7) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_r_u7.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = EXTSIDI (GET_H_CR16 (FLD (f_op__b)));
+ tmp_C = EXTSIDI (FLD (f_u7));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR16 (FLD (f_op__b)));
+ tmp_C = ZEXTSIDI (FLD (f_u7));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* rcmp_L_s12 : rcmp$_L$F1 $RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,rcmp_L_s12_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (FLD (f_s12));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (FLD (f_s12));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* rcmp_ccu6 : rcmp$Qcondi$F1 $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,rcmp_ccu6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* rcmp_L_u6 : rcmp$_L$F1 $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,rcmp_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* rcmp_L_r_r $RC: rcmp$_L$F1 $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,rcmp_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* rcmp_cc $RC: rcmp$Qcondi$F1 $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,rcmp_cc__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* rsub_L_s12 $RA,: rsub$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,rsub_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (FLD (f_s12), GET_H_CR (FLD (f_op_B)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (FLD (f_s12), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (FLD (f_s12), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* rsub_ccu6 $RA,: rsub$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,rsub_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (FLD (f_u6), GET_H_CR (FLD (f_op_B)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (FLD (f_u6), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (FLD (f_u6), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* rsub_L_u6 $RA,: rsub$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,rsub_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (FLD (f_u6), GET_H_CR (FLD (f_op_B)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (FLD (f_u6), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (FLD (f_u6), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* rsub_L_r_r $RA,$RC: rsub$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,rsub_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* rsub_cc $RA,$RC: rsub$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,rsub_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bset_L_s12 $RA,: bset$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,bset_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (FLD (f_s12), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bset_ccu6 $RA,: bset$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,bset_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bset_L_u6 $RA,: bset$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,bset_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bset_L_r_r $RA,$RC: bset$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,bset_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bset_cc $RA,$RC: bset$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,bset_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bset_s_ssb: bset$_S $R_b,$R_b,$u5 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,bset_s_ssb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ {
+ SI opval = ORSI (tmp_B, SLLSI (1, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* bclr_L_s12 $RA,: bclr$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,bclr_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (SLLSI (1, ANDSI (FLD (f_s12), 31))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bclr_ccu6 $RA,: bclr$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,bclr_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (SLLSI (1, ANDSI (FLD (f_u6), 31))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bclr_L_u6 $RA,: bclr$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,bclr_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (SLLSI (1, ANDSI (FLD (f_u6), 31))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bclr_L_r_r $RA,$RC: bclr$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,bclr_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bclr_cc $RA,$RC: bclr$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,bclr_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bclr_s_ssb: bclr$_S $R_b,$R_b,$u5 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,bclr_s_ssb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ {
+ SI opval = ANDSI (tmp_B, INVSI (SLLSI (1, ANDSI (tmp_C, 31))));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* btst_L_s12 : btst$_L$F1 $RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,btst_L_s12_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_s12);
+ tmp_result = ANDSI (tmp_B, SLLSI (1, ANDSI (tmp_C, 31)));
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* btst_ccu6 : btst$Qcondi$F1 $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,btst_ccu6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+ tmp_result = ANDSI (tmp_B, SLLSI (1, ANDSI (tmp_C, 31)));
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* btst_L_u6 : btst$_L$F1 $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,btst_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+ tmp_result = ANDSI (tmp_B, SLLSI (1, ANDSI (tmp_C, 31)));
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* btst_L_r_r $RC: btst$_L$F1 $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,btst_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+ tmp_result = ANDSI (tmp_B, SLLSI (1, ANDSI (tmp_C, 31)));
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* btst_cc $RC: btst$Qcondi$F1 $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,btst_cc__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+ tmp_result = ANDSI (tmp_B, SLLSI (1, ANDSI (tmp_C, 31)));
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* btst_s_ssb: btst$_S $R_b,$u5 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,btst_s_ssb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ tmp_result = ANDSI (tmp_B, SLLSI (1, ANDSI (tmp_C, 31)));
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* bxor_L_s12 $RA,: bxor$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,bxor_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (FLD (f_s12), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bxor_ccu6 $RA,: bxor$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,bxor_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bxor_L_u6 $RA,: bxor$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,bxor_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bxor_L_r_r $RA,$RC: bxor$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,bxor_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bxor_cc $RA,$RC: bxor$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,bxor_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bmsk_L_s12 $RA,: bmsk$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,bmsk_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), SUBSI (SLLSI (SLLSI (1, ANDSI (FLD (f_s12), 31)), 1), 1));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bmsk_ccu6 $RA,: bmsk$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,bmsk_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), SUBSI (SLLSI (SLLSI (1, ANDSI (FLD (f_u6), 31)), 1), 1));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bmsk_L_u6 $RA,: bmsk$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,bmsk_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), SUBSI (SLLSI (SLLSI (1, ANDSI (FLD (f_u6), 31)), 1), 1));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bmsk_L_r_r $RA,$RC: bmsk$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,bmsk_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), SUBSI (SLLSI (SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31)), 1), 1));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bmsk_cc $RA,$RC: bmsk$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,bmsk_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), SUBSI (SLLSI (SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31)), 1), 1));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bmsk_s_ssb: bmsk$_S $R_b,$R_b,$u5 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,bmsk_s_ssb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ {
+ SI opval = ANDSI (tmp_B, SUBSI (SLLSI (SLLSI (1, ANDSI (tmp_C, 31)), 1), 1));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* add1_L_s12 $RA,: add1$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,add1_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s12), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_s12), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add1_ccu6 $RA,: add1$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,add1_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add1_L_u6 $RA,: add1$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,add1_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add1_L_r_r $RA,$RC: add1$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,add1_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add1_cc $RA,$RC: add1$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,add1_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_ADD1_s_go: add1$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,I16_GO_ADD1_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ADDSI (tmp_B, SLLSI (tmp_C, 1));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* add2_L_s12 $RA,: add2$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,add2_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s12), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_s12), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add2_ccu6 $RA,: add2$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,add2_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add2_L_u6 $RA,: add2$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,add2_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add2_L_r_r $RA,$RC: add2$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,add2_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add2_cc $RA,$RC: add2$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,add2_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_ADD2_s_go: add2$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,I16_GO_ADD2_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ADDSI (tmp_B, SLLSI (tmp_C, 2));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* add3_L_s12 $RA,: add3$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,add3_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s12), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_s12), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add3_ccu6 $RA,: add3$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,add3_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add3_L_u6 $RA,: add3$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,add3_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add3_L_r_r $RA,$RC: add3$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,add3_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add3_cc $RA,$RC: add3$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,add3_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_ADD3_s_go: add3$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,I16_GO_ADD3_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ADDSI (tmp_B, SLLSI (tmp_C, 3));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* sub1_L_s12 $RA,: sub1$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,sub1_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s12), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_s12), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub1_ccu6 $RA,: sub1$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,sub1_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub1_L_u6 $RA,: sub1$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,sub1_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub1_L_r_r $RA,$RC: sub1$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,sub1_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub1_cc $RA,$RC: sub1$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,sub1_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub2_L_s12 $RA,: sub2$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,sub2_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s12), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_s12), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub2_ccu6 $RA,: sub2$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,sub2_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub2_L_u6 $RA,: sub2$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,sub2_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub2_L_r_r $RA,$RC: sub2$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,sub2_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub2_cc $RA,$RC: sub2$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,sub2_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub3_L_s12 $RA,: sub3$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,sub3_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s12), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_s12), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub3_ccu6 $RA,: sub3$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,sub3_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub3_L_u6 $RA,: sub3$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,sub3_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub3_L_r_r $RA,$RC: sub3$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,sub3_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub3_cc $RA,$RC: sub3$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,sub3_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpy_L_s12 $RA,: mpy$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mpy_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (EXTSIDI (tmp_result), MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_s12))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpy_ccu6 $RA,: mpy$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mpy_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (EXTSIDI (tmp_result), MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpy_L_u6 $RA,: mpy$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mpy_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (EXTSIDI (tmp_result), MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpy_L_r_r $RA,$RC: mpy$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mpy_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (EXTSIDI (tmp_result), MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C)))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpy_cc $RA,$RC: mpy$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mpy_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (EXTSIDI (tmp_result), MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C)))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyh_L_s12 $RA,: mpyh$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mpyh_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_s12))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyh_ccu6 $RA,: mpyh$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mpyh_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyh_L_u6 $RA,: mpyh$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mpyh_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyh_L_r_r $RA,$RC: mpyh$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mpyh_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C)))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyh_cc $RA,$RC: mpyh$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mpyh_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C)))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyhu_L_s12 $RA,: mpyhu$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mpyhu_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_s12))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyhu_ccu6 $RA,: mpyhu$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mpyhu_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_u6))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyhu_L_u6 $RA,: mpyhu$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mpyhu_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_u6))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyhu_L_r_r $RA,$RC: mpyhu$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mpyhu_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (GET_H_CR (FLD (f_op_C)))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyhu_cc $RA,$RC: mpyhu$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mpyhu_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (GET_H_CR (FLD (f_op_C)))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyu_L_s12 $RA,: mpyu$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mpyu_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (ZEXTSIDI (tmp_result), MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_s12))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyu_ccu6 $RA,: mpyu$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mpyu_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (ZEXTSIDI (tmp_result), MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_u6))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyu_L_u6 $RA,: mpyu$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mpyu_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (ZEXTSIDI (tmp_result), MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_u6))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyu_L_r_r $RA,$RC: mpyu$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mpyu_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (ZEXTSIDI (tmp_result), MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (GET_H_CR (FLD (f_op_C)))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyu_cc $RA,$RC: mpyu$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mpyu_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (ZEXTSIDI (tmp_result), MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (GET_H_CR (FLD (f_op_C)))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* j_L_r_r [$RC_noilink]: j$_L$F0 [$RC_noilink] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,j_L_r_r___RC_noilink_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_cc [$RC_noilink]: j$Qcondi$F0 [$RC_noilink] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,j_cc___RC_noilink_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_L_r_r [$RC_ilink]: j$_L$F1F [$RC_ilink] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,j_L_r_r___RC_ilink_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_ILINKX (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_ILINKX (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_ILINKX (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_cc [$RC_ilink]: j$Qcondi$F1F [$RC_ilink] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,j_cc___RC_ilink_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_ILINKX (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_ILINKX (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_ILINKX (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_L_s12 : j$_L$F0 $s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,j_L_s12_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_ccu6 : j$Qcondi$F0 $U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,j_ccu6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_L_u6 : j$_L$F0 $U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,j_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_s: j$_S [$R_b] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,j_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_s$_S: j$_S [$R31] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,j_s__S) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_seq$_S: jeq$_S [$R31] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,j_seq__S) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if (NEBI (CPU (h_zbit), 0)) {
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if (NEBI (CPU (h_zbit), 0)) {
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if (NEBI (CPU (h_zbit), 0)) {
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_sne$_S: jne$_S [$R31] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,j_sne__S) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if (EQBI (CPU (h_zbit), 0)) {
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if (EQBI (CPU (h_zbit), 0)) {
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if (EQBI (CPU (h_zbit), 0)) {
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_L_s12.d : j$_L$F0.d $s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,j_L_s12_d_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_ccu6.d : j$Qcondi$F0.d $U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,j_ccu6_d_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_L_u6.d : j$_L$F0.d $U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,j_L_u6_d_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_L_r_r.d [$RC]: j$_L$F0.d [$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,j_L_r_r_d___RC_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_cc.d [$RC]: j$Qcondi$F0.d [$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,j_cc_d___RC_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_s.d: j$_S.d [$R_b] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,j_s_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_s$_S.d: j$_S.d [$R31] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,j_s__S_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jl_L_s12 : jl$_L$F0 $s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,jl_L_s12_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jl_ccu6 : jl$Qcondi$F0 $U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,jl_ccu6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jl_L_u6 : jl$_L$F0 $U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,jl_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jl_s: jl$_S [$R_b] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,jl_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 2);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 2);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 2);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jl_L_r_r [$RC_noilink]: jl$_L$F0 [$RC_noilink] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,jl_L_r_r___RC_noilink_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, ((EQSI (FLD (f_op_C), 62)) ? (8) : (4)));
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, ((EQSI (FLD (f_op_C), 62)) ? (8) : (4)));
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, ((EQSI (FLD (f_op_C), 62)) ? (8) : (4)));
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jl_cc [$RC_noilink]: jl$Qcondi$F0 [$RC_noilink] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,jl_cc___RC_noilink_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, ((EQSI (FLD (f_op_C), 62)) ? (8) : (4)));
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, ((EQSI (FLD (f_op_C), 62)) ? (8) : (4)));
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, ((EQSI (FLD (f_op_C), 62)) ? (8) : (4)));
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jl_L_s12.d : jl$_L$F0.d $s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,jl_L_s12_d_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jl_ccu6.d : jl$Qcondi$F0.d $U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,jl_ccu6_d_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jl_L_u6.d : jl$_L$F0.d $U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,jl_L_u6_d_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jl_L_r_r.d [$RC]: jl$_L$F0.d [$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,jl_L_r_r_d___RC_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jl_cc.d [$RC]: jl$Qcondi$F0.d [$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,jl_cc_d___RC_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jl_s.d: jl$_S.d [$R_b] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,jl_s_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 2));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 2));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 2));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* lp_L_s12 : lp$_L$F0 $s12x2 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,lp_L_s12_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lp_L_s12_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ SI opval = ADDSI (ANDSI (pc, -4), FLD (f_s12x2));
+ SET_H_AUXR (((UINT) 3), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_AUXR (((UINT) 2), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ SI opval = ADDSI (ANDSI (pc, -4), FLD (f_s12x2));
+ SET_H_AUXR (((UINT) 3), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_AUXR (((UINT) 2), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ SI opval = ADDSI (ANDSI (pc, -4), FLD (f_s12x2));
+ SET_H_AUXR (((UINT) 3), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_AUXR (((UINT) 2), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* lpcc_ccu6: lp$Qcondi$F0 $U6x2 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,lpcc_ccu6) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lpcc_ccu6.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ SI opval = ADDSI (ANDSI (pc, -4), FLD (f_u6x2));
+ SET_H_AUXR (((UINT) 3), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_AUXR (((UINT) 2), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ SI opval = ADDSI (ANDSI (pc, -4), FLD (f_u6x2));
+ SET_H_AUXR (((UINT) 3), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_AUXR (((UINT) 2), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ SI opval = ADDSI (ANDSI (pc, -4), FLD (f_u6x2));
+ SET_H_AUXR (((UINT) 3), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_AUXR (((UINT) 2), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+}
+}
+} else {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = ADDSI (ANDSI (pc, -4), FLD (f_u6x2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = ADDSI (ANDSI (pc, -4), FLD (f_u6x2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = ADDSI (ANDSI (pc, -4), FLD (f_u6x2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* flag_L_s12 : flag$_L$F0 $s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,flag_L_s12_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (ANDSI (FLD (f_s12), 1)) {
+sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc, sim_exited, a5f_h_cr_get (current_cpu, 0));}
+ {
+ SI opval = FLD (f_s12);
+ SET_H_STATUS32 (((UINT) 0), opval);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* flag_ccu6 : flag$Qcondi$F0 $U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,flag_ccu6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+if (ANDSI (FLD (f_u6), 1)) {
+sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc, sim_exited, a5f_h_cr_get (current_cpu, 0));}
+ {
+ SI opval = FLD (f_u6);
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* flag_L_u6 : flag$_L$F0 $U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,flag_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (ANDSI (FLD (f_u6), 1)) {
+sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc, sim_exited, a5f_h_cr_get (current_cpu, 0));}
+ {
+ SI opval = FLD (f_u6);
+ SET_H_STATUS32 (((UINT) 0), opval);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* flag_L_r_r $RC: flag$_L$F0 $RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,flag_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (ANDSI (GET_H_CR (FLD (f_op_C)), 1)) {
+sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc, sim_exited, a5f_h_cr_get (current_cpu, 0));}
+ {
+ SI opval = GET_H_CR (FLD (f_op_C));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* flag_cc $RC: flag$Qcondi$F0 $RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,flag_cc__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+if (ANDSI (GET_H_CR (FLD (f_op_C)), 1)) {
+sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc, sim_exited, a5f_h_cr_get (current_cpu, 0));}
+ {
+ SI opval = GET_H_CR (FLD (f_op_C));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* lr_L_r_r [$RC]: lr$_L$F0 $RB,[$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,lr_L_r_r___RC_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ {
+ SI opval = GET_H_AUXR (GET_H_CR (FLD (f_op_C)));
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* lr_L_s12 : lr$_L$F0 $RB,[$s12] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,lr_L_s12_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ {
+ SI opval = GET_H_AUXR (FLD (f_s12));
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* lr_L_u6 : lr$_L$F0 $RB,[$U6] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,lr_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ {
+ SI opval = GET_H_AUXR (FLD (f_u6));
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* sr_L_r_r [$RC]: sr$_L$F0 $RB,[$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,sr_L_r_r___RC_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ {
+ SI opval = GET_H_CR (FLD (f_op_B));
+ SET_H_AUXR (GET_H_CR (FLD (f_op_C)), opval);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* sr_L_s12 : sr$_L$F0 $RB,[$s12] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,sr_L_s12_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ {
+ SI opval = GET_H_CR (FLD (f_op_B));
+ SET_H_AUXR (FLD (f_s12), opval);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* sr_L_u6 : sr$_L$F0 $RB,[$U6] */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,sr_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ {
+ SI opval = GET_H_CR (FLD (f_op_B));
+ SET_H_AUXR (FLD (f_u6), opval);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* asl_L_r_r $RC: asl$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,asl_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asl_L_u6 : asl$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,asl_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (FLD (f_u6), FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (FLD (f_u6), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (FLD (f_u6), FLD (f_u6), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_ASL_s_go: asl$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,I16_GO_ASL_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ADDSI (tmp_C, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* asr_L_r_r $RC: asr$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,asr_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SRASI (GET_H_CR (FLD (f_op_C)), 1);
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (GET_H_CR (FLD (f_op_C)), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asr_L_u6 : asr$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,asr_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SRASI (FLD (f_u6), 1);
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (FLD (f_u6), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_ASR_s_go: asr$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,I16_GO_ASR_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = SRASI (tmp_C, 1);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* lsr_L_r_r $RC: lsr$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,lsr_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SRLSI (GET_H_CR (FLD (f_op_C)), 1);
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (GET_H_CR (FLD (f_op_C)), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* lsr_L_u6 : lsr$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,lsr_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SRLSI (FLD (f_u6), 1);
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (FLD (f_u6), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_LSR_s_go: lsr$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,I16_GO_LSR_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = SRLSI (tmp_C, 1);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ror_L_r_r $RC: ror$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ror_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (SRLSI (GET_H_CR (FLD (f_op_C)), 1), SLLSI (GET_H_CR (FLD (f_op_C)), 31));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (GET_H_CR (FLD (f_op_C)), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* ror_L_u6 : ror$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ror_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (SRLSI (FLD (f_u6), 1), SLLSI (FLD (f_u6), 31));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (FLD (f_u6), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* rrc_L_r_r $RC: rrc$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,rrc_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (SRLSI (GET_H_CR (FLD (f_op_C)), 1), SLLSI (ZEXTBISI (CPU (h_cbit)), 31));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (GET_H_CR (FLD (f_op_C)), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* rrc_L_u6 : rrc$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,rrc_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (SRLSI (FLD (f_u6), 1), SLLSI (ZEXTBISI (CPU (h_cbit)), 31));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (FLD (f_u6), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sexb_L_r_r $RC: sexb$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,sexb_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = EXTQISI ((GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sexb_L_u6 : sexb$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,sexb_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = EXTQISI ((FLD (f_u6)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_SEXB_s_go: sexb$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,I16_GO_SEXB_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = EXTQISI ((tmp_C));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* sexw_L_r_r $RC: sexw$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,sexw_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = EXTHISI ((GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sexw_L_u6 : sexw$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,sexw_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = EXTHISI ((FLD (f_u6)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_SEXW_s_go: sexw$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,I16_GO_SEXW_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = EXTHISI ((tmp_C));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* extb_L_r_r $RC: extb$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,extb_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ZEXTQISI ((GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* extb_L_u6 : extb$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,extb_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ZEXTQISI ((FLD (f_u6)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_EXTB_s_go: extb$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,I16_GO_EXTB_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ZEXTQISI ((tmp_C));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* extw_L_r_r $RC: extw$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,extw_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ZEXTHISI ((GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* extw_L_u6 : extw$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,extw_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ZEXTHISI ((FLD (f_u6)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_EXTW_s_go: extw$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,I16_GO_EXTW_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ZEXTHISI ((tmp_C));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* abs_L_r_r $RC: abs$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,abs_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ABSSI (({ SI tmp_res;
+ tmp_res = GET_H_CR (FLD (f_op_C));
+; tmp_res; }));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI ((GET_H_CR (FLD (f_op_C))), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (GET_H_CR (FLD (f_op_C)), 0x80000000);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_vbit);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* abs_L_u6 : abs$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,abs_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ABSSI (({ SI tmp_res;
+ tmp_res = FLD (f_u6);
+; tmp_res; }));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI ((FLD (f_u6)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (FLD (f_u6), 0x80000000);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_vbit);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_ABS_s_go: abs$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,I16_GO_ABS_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ABSSI (({ SI tmp_res;
+ tmp_res = tmp_C;
+; tmp_res; }));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* not_L_r_r $RC: not$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,not_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = INVSI (GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* not_L_u6 : not$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,not_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = INVSI (FLD (f_u6));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_NOT_s_go: not$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,I16_GO_NOT_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = INVSI (tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* rlc_L_r_r $RC: rlc$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,rlc_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (SLLSI (GET_H_CR (FLD (f_op_C)), 1), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SRLSI (GET_H_CR (FLD (f_op_C)), 31);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* rlc_L_u6 : rlc$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,rlc_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (SLLSI (FLD (f_u6), 1), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SRLSI (FLD (f_u6), 31);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_NEG_s_go: neg$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,I16_GO_NEG_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = NEGSI (tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* swi: swi */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,swi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+; /*clobber*/
+ {
+ USI opval = arc_trap (current_cpu, pc, 4, 0);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else if (0) {
+{
+; /*clobber*/
+ {
+ USI opval = arc_trap (current_cpu, pc, 4, 0);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+; /*clobber*/
+ {
+ USI opval = arc_trap (current_cpu, pc, 4, 0);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* trap_s: trap$_S $trapnum */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,trap_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_trap_s.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = arc_trap (current_cpu, pc, 2, FLD (f_trapnum));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+; /*clobber*/
+}
+}
+}
+ else if (0) {
+{
+ {
+ USI opval = arc_trap (current_cpu, pc, 2, FLD (f_trapnum));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+; /*clobber*/
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ {
+ USI opval = arc_trap (current_cpu, pc, 2, FLD (f_trapnum));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+; /*clobber*/
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* brk: brk */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,brk) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+arc_breakpoint (current_cpu, pc, 4);
+
+ return vpc;
+#undef FLD
+}
+
+/* brk_s: brk_s */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,brk_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+arc_breakpoint (current_cpu, pc, 2);
+
+ return vpc;
+#undef FLD
+}
+
+/* asl_L_s12 $RA,: asl$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,asl_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_s12), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_s12), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (32, ANDSI (FLD (f_s12), 31))), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asl_ccu6 $RA,: asl$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,asl_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (32, ANDSI (FLD (f_u6), 31))), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asl_L_u6 $RA,: asl$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,asl_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (32, ANDSI (FLD (f_u6), 31))), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asl_L_r_r $RA,$RC: asl$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,asl_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (32, ANDSI (GET_H_CR (FLD (f_op_C)), 31))), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asl_cc $RA,$RC: asl$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,asl_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (32, ANDSI (GET_H_CR (FLD (f_op_C)), 31))), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asl_s_cbu3: asl$_S $R_c,$R_b,$u3 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,asl_s_cbu3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u3);
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* asl_s_ssb: asl$_S $R_b,$R_b,$u5 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,asl_s_ssb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_ASLM_s_go: asl$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,I16_GO_ASLM_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* lsr_L_s12 $RA,: lsr$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,lsr_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_s12), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_s12), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_s12), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* lsr_ccu6 $RA,: lsr$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,lsr_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_u6), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* lsr_L_u6 $RA,: lsr$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,lsr_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_u6), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* lsr_L_r_r $RA,$RC: lsr$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,lsr_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* lsr_cc $RA,$RC: lsr$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,lsr_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* lsr_s_ssb: lsr$_S $R_b,$R_b,$u5 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,lsr_s_ssb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_LSRM_s_go: lsr$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,I16_GO_LSRM_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* asr_L_s12 $RA,: asr$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,asr_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_s12), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_s12), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_s12), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asr_ccu6 $RA,: asr$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,asr_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_u6), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asr_L_u6 $RA,: asr$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,asr_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_u6), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asr_L_r_r $RA,$RC: asr$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,asr_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asr_cc $RA,$RC: asr$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,asr_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asr_s_cbu3: asr$_S $R_c,$R_b,$u3 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,asr_s_cbu3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u3);
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* asr_s_ssb: asr$_S $R_b,$R_b,$u5 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,asr_s_ssb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_ASRM_s_go: asr$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,I16_GO_ASRM_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ror_L_s12 $RA,: ror$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ror_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (RORSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_s12), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_s12), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_s12), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* ror_ccu6 $RA,: ror$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ror_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (RORSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_u6), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* ror_L_u6 $RA,: ror$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ror_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (RORSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_u6), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* ror_L_r_r $RA,$RC: ror$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ror_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (RORSI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* ror_cc $RA,$RC: ror$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,ror_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (RORSI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mul64_L_s12 : mul64$_L$F1 $RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mul64_L_s12_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_s12)));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mul64_ccu6 : mul64$Qcondi$F1 $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mul64_ccu6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6)));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mul64_L_u6 : mul64$_L$F1 $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mul64_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6)));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mul64_L_r_r $RC: mul64$_L$F1 $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mul64_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mul64_cc $RC: mul64$Qcondi$F1 $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mul64_cc__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mul64_s_go: mul64$_S $R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mul64_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (EXTSIDI (GET_H_CR16 (FLD (f_op__b))), EXTSIDI (GET_H_CR16 (FLD (f_op__c))));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mulu64_L_s12 : mulu64$_L$F1 $RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mulu64_L_s12_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_s12)));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mulu64_ccu6 : mulu64$Qcondi$F1 $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mulu64_ccu6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_u6)));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mulu64_L_u6 : mulu64$_L$F1 $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mulu64_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_u6)));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mulu64_L_r_r $RC: mulu64$_L$F1 $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mulu64_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (GET_H_CR (FLD (f_op_C))));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mulu64_cc $RC: mulu64$Qcondi$F1 $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mulu64_cc__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (GET_H_CR (FLD (f_op_C))));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* adds_L_s12 $RA,: adds$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,adds_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = ADDDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_s12)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* adds_ccu6 $RA,: adds$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,adds_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = ADDDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* adds_L_u6 $RA,: adds$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,adds_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = ADDDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* adds_L_r_r $RA,$RC: adds$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,adds_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = ADDDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* adds_cc $RA,$RC: adds$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,adds_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = ADDDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* subs_L_s12 $RA,: subs$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,subs_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_s12)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* subs_ccu6 $RA,: subs$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,subs_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* subs_L_u6 $RA,: subs$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,subs_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* subs_L_r_r $RA,$RC: subs$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,subs_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* subs_cc $RA,$RC: subs$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,subs_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* divaw_L_s12 $RA,: divaw$_L$F0 $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,divaw_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ USI tmp_tmp;
+ tmp_tmp = SLLSI (GET_H_CR (FLD (f_op_B)), 1);
+; ((EQSI (ANDSI (SUBSI (tmp_tmp, FLD (f_s12)), 0x80000000), 0)) ? (ADDSI (SUBSI (tmp_tmp, FLD (f_s12)), 1)) : (tmp_tmp)); }));
+if (FLD (f_F)) {
+((void) 0); /*nop*/
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* divaw_ccu6 $RA,: divaw$Qcondi$F0 $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,divaw_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ USI tmp_tmp;
+ tmp_tmp = SLLSI (GET_H_CR (FLD (f_op_B)), 1);
+; ((EQSI (ANDSI (SUBSI (tmp_tmp, FLD (f_u6)), 0x80000000), 0)) ? (ADDSI (SUBSI (tmp_tmp, FLD (f_u6)), 1)) : (tmp_tmp)); }));
+if (FLD (f_F)) {
+((void) 0); /*nop*/
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* divaw_L_u6 $RA,: divaw$_L$F0 $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,divaw_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ USI tmp_tmp;
+ tmp_tmp = SLLSI (GET_H_CR (FLD (f_op_B)), 1);
+; ((EQSI (ANDSI (SUBSI (tmp_tmp, FLD (f_u6)), 0x80000000), 0)) ? (ADDSI (SUBSI (tmp_tmp, FLD (f_u6)), 1)) : (tmp_tmp)); }));
+if (FLD (f_F)) {
+((void) 0); /*nop*/
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* divaw_L_r_r $RA,$RC: divaw$_L$F0 $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,divaw_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ USI tmp_tmp;
+ tmp_tmp = SLLSI (GET_H_CR (FLD (f_op_B)), 1);
+; ((EQSI (ANDSI (SUBSI (tmp_tmp, GET_H_CR (FLD (f_op_C))), 0x80000000), 0)) ? (ADDSI (SUBSI (tmp_tmp, GET_H_CR (FLD (f_op_C))), 1)) : (tmp_tmp)); }));
+if (FLD (f_F)) {
+((void) 0); /*nop*/
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* divaw_cc $RA,$RC: divaw$Qcondi$F0 $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,divaw_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ USI tmp_tmp;
+ tmp_tmp = SLLSI (GET_H_CR (FLD (f_op_B)), 1);
+; ((EQSI (ANDSI (SUBSI (tmp_tmp, GET_H_CR (FLD (f_op_C))), 0x80000000), 0)) ? (ADDSI (SUBSI (tmp_tmp, GET_H_CR (FLD (f_op_C))), 1)) : (tmp_tmp)); }));
+if (FLD (f_F)) {
+((void) 0); /*nop*/
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asls_L_s12 $RA,: asls$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,asls_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((FLD (f_s12)), 31)) ? (SLLDI (tmp_b, 31)) : (LTSI ((FLD (f_s12)), -31)) ? (SRADI (tmp_b, 31)) : (GESI ((FLD (f_s12)), 0)) ? (SLLDI (tmp_b, (FLD (f_s12)))) : (SRASI (GET_H_CR (FLD (f_op_B)), NEGSI ((FLD (f_s12)))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asls_ccu6 $RA,: asls$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,asls_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((FLD (f_u6)), 31)) ? (SLLDI (tmp_b, 31)) : (LTSI ((FLD (f_u6)), -31)) ? (SRADI (tmp_b, 31)) : (GESI ((FLD (f_u6)), 0)) ? (SLLDI (tmp_b, (FLD (f_u6)))) : (SRASI (GET_H_CR (FLD (f_op_B)), NEGSI ((FLD (f_u6)))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asls_L_u6 $RA,: asls$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,asls_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((FLD (f_u6)), 31)) ? (SLLDI (tmp_b, 31)) : (LTSI ((FLD (f_u6)), -31)) ? (SRADI (tmp_b, 31)) : (GESI ((FLD (f_u6)), 0)) ? (SLLDI (tmp_b, (FLD (f_u6)))) : (SRASI (GET_H_CR (FLD (f_op_B)), NEGSI ((FLD (f_u6)))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asls_L_r_r $RA,$RC: asls$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,asls_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((GET_H_CR (FLD (f_op_C))), 31)) ? (SLLDI (tmp_b, 31)) : (LTSI ((GET_H_CR (FLD (f_op_C))), -31)) ? (SRADI (tmp_b, 31)) : (GESI ((GET_H_CR (FLD (f_op_C))), 0)) ? (SLLDI (tmp_b, (GET_H_CR (FLD (f_op_C))))) : (SRASI (GET_H_CR (FLD (f_op_B)), NEGSI ((GET_H_CR (FLD (f_op_C))))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asls_cc $RA,$RC: asls$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,asls_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((GET_H_CR (FLD (f_op_C))), 31)) ? (SLLDI (tmp_b, 31)) : (LTSI ((GET_H_CR (FLD (f_op_C))), -31)) ? (SRADI (tmp_b, 31)) : (GESI ((GET_H_CR (FLD (f_op_C))), 0)) ? (SLLDI (tmp_b, (GET_H_CR (FLD (f_op_C))))) : (SRASI (GET_H_CR (FLD (f_op_B)), NEGSI ((GET_H_CR (FLD (f_op_C))))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asrs_L_s12 $RA,: asrs$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,asrs_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((FLD (f_s12)), 31)) ? (SRADI (tmp_b, 31)) : (LTSI ((FLD (f_s12)), -31)) ? (SLLDI (tmp_b, 31)) : (GESI ((FLD (f_s12)), 0)) ? (SRADI (tmp_b, (FLD (f_s12)))) : (SLLSI (GET_H_CR (FLD (f_op_B)), NEGSI ((FLD (f_s12)))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asrs_ccu6 $RA,: asrs$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,asrs_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((FLD (f_u6)), 31)) ? (SRADI (tmp_b, 31)) : (LTSI ((FLD (f_u6)), -31)) ? (SLLDI (tmp_b, 31)) : (GESI ((FLD (f_u6)), 0)) ? (SRADI (tmp_b, (FLD (f_u6)))) : (SLLSI (GET_H_CR (FLD (f_op_B)), NEGSI ((FLD (f_u6)))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asrs_L_u6 $RA,: asrs$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,asrs_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((FLD (f_u6)), 31)) ? (SRADI (tmp_b, 31)) : (LTSI ((FLD (f_u6)), -31)) ? (SLLDI (tmp_b, 31)) : (GESI ((FLD (f_u6)), 0)) ? (SRADI (tmp_b, (FLD (f_u6)))) : (SLLSI (GET_H_CR (FLD (f_op_B)), NEGSI ((FLD (f_u6)))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asrs_L_r_r $RA,$RC: asrs$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,asrs_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((GET_H_CR (FLD (f_op_C))), 31)) ? (SRADI (tmp_b, 31)) : (LTSI ((GET_H_CR (FLD (f_op_C))), -31)) ? (SLLDI (tmp_b, 31)) : (GESI ((GET_H_CR (FLD (f_op_C))), 0)) ? (SRADI (tmp_b, (GET_H_CR (FLD (f_op_C))))) : (SLLSI (GET_H_CR (FLD (f_op_B)), NEGSI ((GET_H_CR (FLD (f_op_C))))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asrs_cc $RA,$RC: asrs$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,asrs_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((GET_H_CR (FLD (f_op_C))), 31)) ? (SRADI (tmp_b, 31)) : (LTSI ((GET_H_CR (FLD (f_op_C))), -31)) ? (SLLDI (tmp_b, 31)) : (GESI ((GET_H_CR (FLD (f_op_C))), 0)) ? (SRADI (tmp_b, (GET_H_CR (FLD (f_op_C))))) : (SLLSI (GET_H_CR (FLD (f_op_B)), NEGSI ((GET_H_CR (FLD (f_op_C))))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* addsdw_L_s12 $RA,: addsdw$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,addsdw_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((FLD (f_s12)), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((FLD (f_s12)), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* addsdw_ccu6 $RA,: addsdw$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,addsdw_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((FLD (f_u6)), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((FLD (f_u6)), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* addsdw_L_u6 $RA,: addsdw$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,addsdw_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((FLD (f_u6)), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((FLD (f_u6)), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* addsdw_L_r_r $RA,$RC: addsdw$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,addsdw_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* addsdw_cc $RA,$RC: addsdw$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,addsdw_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* subsdw_L_s12 $RA,: subsdw$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,subsdw_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((FLD (f_s12)), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((FLD (f_s12)), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* subsdw_ccu6 $RA,: subsdw$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,subsdw_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((FLD (f_u6)), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((FLD (f_u6)), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* subsdw_L_u6 $RA,: subsdw$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,subsdw_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((FLD (f_u6)), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((FLD (f_u6)), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* subsdw_L_r_r $RA,$RC: subsdw$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,subsdw_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* subsdw_cc $RA,$RC: subsdw$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,subsdw_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* swap_L_r_r $RC: swap$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,swap_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (RORSI (GET_H_CR (FLD (f_op_C)), 16));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* swap_L_u6 : swap$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,swap_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (RORSI (FLD (f_u6), 16));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* norm_L_r_r $RC: norm$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,norm_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_val;
+ SI tmp_bits;
+ tmp_val = ((GESI ((GET_H_CR (FLD (f_op_C))), 0)) ? ((GET_H_CR (FLD (f_op_C)))) : (INVSI ((GET_H_CR (FLD (f_op_C))))));
+; tmp_bits = 31;
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 4), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 4));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 4));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 3), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 3));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 3));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 2), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 2));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 2));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 1), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 1));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 1));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 0), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 0));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 0));
+}
+; tmp_bits; }));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* norm_L_u6 : norm$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,norm_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_val;
+ SI tmp_bits;
+ tmp_val = ((GESI ((FLD (f_u6)), 0)) ? ((FLD (f_u6))) : (INVSI ((FLD (f_u6)))));
+; tmp_bits = 31;
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 4), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 4));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 4));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 3), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 3));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 3));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 2), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 2));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 2));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 1), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 1));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 1));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 0), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 0));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 0));
+}
+; tmp_bits; }));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (FLD (f_u6), 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (FLD (f_u6), 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* rnd16_L_r_r $RC: rnd16$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,rnd16_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (({ DI tmp_tmp;
+ tmp_tmp = ADDDI (EXTSIDI (32768), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }), 16));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* rnd16_L_u6 : rnd16$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,rnd16_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (({ DI tmp_tmp;
+ tmp_tmp = ADDDI (EXTSIDI (32768), EXTSIDI (FLD (f_u6)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }), 16));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* abssw_L_r_r $RC: abssw$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,abssw_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_tmp;
+ tmp_tmp = ABSSI (EXTHISI ((GET_H_CR (FLD (f_op_C)))));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* abssw_L_u6 : abssw$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,abssw_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_tmp;
+ tmp_tmp = ABSSI (EXTHISI ((FLD (f_u6))));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* abss_L_r_r $RC: abss$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,abss_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (((GESI ((GET_H_CR (FLD (f_op_C))), 0)) ? (GET_H_CR (FLD (f_op_C))) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (0), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }))));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* abss_L_u6 : abss$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,abss_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (((GESI ((FLD (f_u6)), 0)) ? (FLD (f_u6)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (0), EXTSIDI (FLD (f_u6)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }))));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* negsw_L_r_r $RC: negsw$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,negsw_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_tmp;
+ tmp_tmp = EXTHISI ((GET_H_CR (FLD (f_op_C))));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* negsw_L_u6 : negsw$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,negsw_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_tmp;
+ tmp_tmp = EXTHISI ((FLD (f_u6)));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* negs_L_r_r $RC: negs$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,negs_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (0), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* negs_L_u6 : negs$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,negs_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (0), EXTSIDI (FLD (f_u6)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* normw_L_r_r $RC: normw$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,normw_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_val;
+ SI tmp_bits;
+ tmp_val = ((GESI (ORSI (SLLSI (GET_H_CR (FLD (f_op_C)), 16), ANDSI (GET_H_CR (FLD (f_op_C)), 65535)), 0)) ? (ORSI (SLLSI (GET_H_CR (FLD (f_op_C)), 16), ANDSI (GET_H_CR (FLD (f_op_C)), 65535))) : (INVSI (ORSI (SLLSI (GET_H_CR (FLD (f_op_C)), 16), ANDSI (GET_H_CR (FLD (f_op_C)), 65535)))));
+; tmp_bits = 31;
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 4), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 4));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 4));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 3), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 3));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 3));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 2), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 2));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 2));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 1), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 1));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 1));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 0), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 0));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 0));
+}
+; tmp_bits; }));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* normw_L_u6 : normw$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,normw_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_val;
+ SI tmp_bits;
+ tmp_val = ((GESI (ORSI (SLLSI (FLD (f_u6), 16), ANDSI (FLD (f_u6), 65535)), 0)) ? (ORSI (SLLSI (FLD (f_u6), 16), ANDSI (FLD (f_u6), 65535))) : (INVSI (ORSI (SLLSI (FLD (f_u6), 16), ANDSI (FLD (f_u6), 65535)))));
+; tmp_bits = 31;
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 4), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 4));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 4));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 3), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 3));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 3));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 2), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 2));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 2));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 1), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 1));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 1));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 0), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 0));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 0));
+}
+; tmp_bits; }));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* nop_s: nop_s */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,nop_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* unimp_s: unimp_s */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,unimp_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+cgen_rtx_error (current_cpu, "invalid insn");
+
+ return vpc;
+#undef FLD
+}
+
+/* pop_s_b: pop$_S $R_b */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,pop_s_b) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ SI opval = GETMEMSI (current_cpu, pc, GET_H_SP ());
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (GET_H_SP (), 4);
+ SET_H_SP (, opval);
+ TRACE_RESULT (current_cpu, abuf, "sp", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* pop_s_blink: pop$_S $R31 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,pop_s_blink) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ SI opval = GETMEMSI (current_cpu, pc, GET_H_SP ());
+ SET_H_R31 (, opval);
+ TRACE_RESULT (current_cpu, abuf, "r31", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (GET_H_SP (), 4);
+ SET_H_SP (, opval);
+ TRACE_RESULT (current_cpu, abuf, "sp", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* push_s_b: push$_S $R_b */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,push_s_b) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ SI opval = ADDSI (GET_H_SP (), -4);
+ SET_H_SP (, opval);
+ TRACE_RESULT (current_cpu, abuf, "sp", 'x', opval);
+ }
+ {
+ SI opval = GET_H_CR16 (FLD (f_op__b));
+ SETMEMSI (current_cpu, pc, GET_H_SP (), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* push_s_blink: push$_S $R31 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,push_s_blink) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ SI opval = ADDSI (GET_H_SP (), -4);
+ SET_H_SP (, opval);
+ TRACE_RESULT (current_cpu, abuf, "sp", 'x', opval);
+ }
+ {
+ SI opval = GET_H_R31 ();
+ SETMEMSI (current_cpu, pc, GET_H_SP (), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mullw_L_s12 $RA,: mullw$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mullw_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_s12), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mullw_ccu6 $RA,: mullw$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mullw_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_u6), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mullw_L_u6 $RA,: mullw$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mullw_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_u6), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mullw_L_r_r $RA,$RC: mullw$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mullw_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mullw_cc $RA,$RC: mullw$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mullw_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* maclw_L_s12 $RA,: maclw$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,maclw_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ SI tmp_SItmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_s12), 65535))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; {
+ BI opval = ANDBI (CPU (h_vbit), SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; if (NEBI (CPU (h_vbit), 0)) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; tmp_SItmp = ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp));
+; tmp_cur_s1bit = ORBI (tmp_cur_s1bit, CPU (h_vbit));
+; tmp_SItmp; });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* maclw_ccu6 $RA,: maclw$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,maclw_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ SI tmp_SItmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_u6), 65535))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; {
+ BI opval = ANDBI (CPU (h_vbit), SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; if (NEBI (CPU (h_vbit), 0)) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; tmp_SItmp = ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp));
+; tmp_cur_s1bit = ORBI (tmp_cur_s1bit, CPU (h_vbit));
+; tmp_SItmp; });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* maclw_L_u6 $RA,: maclw$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,maclw_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ SI tmp_SItmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_u6), 65535))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; {
+ BI opval = ANDBI (CPU (h_vbit), SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; if (NEBI (CPU (h_vbit), 0)) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; tmp_SItmp = ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp));
+; tmp_cur_s1bit = ORBI (tmp_cur_s1bit, CPU (h_vbit));
+; tmp_SItmp; });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* maclw_L_r_r $RA,$RC: maclw$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,maclw_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ SI tmp_SItmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), 65535))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; {
+ BI opval = ANDBI (CPU (h_vbit), SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; if (NEBI (CPU (h_vbit), 0)) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; tmp_SItmp = ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp));
+; tmp_cur_s1bit = ORBI (tmp_cur_s1bit, CPU (h_vbit));
+; tmp_SItmp; });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* maclw_cc $RA,$RC: maclw$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,maclw_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ SI tmp_SItmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), 65535))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; {
+ BI opval = ANDBI (CPU (h_vbit), SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; if (NEBI (CPU (h_vbit), 0)) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; tmp_SItmp = ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp));
+; tmp_cur_s1bit = ORBI (tmp_cur_s1bit, CPU (h_vbit));
+; tmp_SItmp; });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* machlw_L_s12 $RA,: machlw$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,machlw_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_s12), -65536))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = ANDBI (CPU (h_vbit), XORDI (tmp_old, tmp_tmp));
+; if (tmp_cur_s1bit) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* machlw_ccu6 $RA,: machlw$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,machlw_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_u6), -65536))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = ANDBI (CPU (h_vbit), XORDI (tmp_old, tmp_tmp));
+; if (tmp_cur_s1bit) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* machlw_L_u6 $RA,: machlw$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,machlw_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_u6), -65536))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = ANDBI (CPU (h_vbit), XORDI (tmp_old, tmp_tmp));
+; if (tmp_cur_s1bit) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* machlw_L_r_r $RA,$RC: machlw$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,machlw_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), -65536))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = ANDBI (CPU (h_vbit), XORDI (tmp_old, tmp_tmp));
+; if (tmp_cur_s1bit) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* machlw_cc $RA,$RC: machlw$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,machlw_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), -65536))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = ANDBI (CPU (h_vbit), XORDI (tmp_old, tmp_tmp));
+; if (tmp_cur_s1bit) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mululw_L_s12 $RA,: mululw$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mululw_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (FLD (f_s12), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mululw_ccu6 $RA,: mululw$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mululw_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (FLD (f_u6), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mululw_L_u6 $RA,: mululw$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mululw_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (FLD (f_u6), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mululw_L_r_r $RA,$RC: mululw$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mululw_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mululw_cc $RA,$RC: mululw$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,mululw_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* machulw_L_s12 $RA,: machulw$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,machulw_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (FLD (f_s12), -65536))));
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = (GTUDI (tmp_old, tmp_tmp)) ? (( tmp_tmp = -1, 1)) : (0);
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* machulw_ccu6 $RA,: machulw$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,machulw_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (FLD (f_u6), -65536))));
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = (GTUDI (tmp_old, tmp_tmp)) ? (( tmp_tmp = -1, 1)) : (0);
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* machulw_L_u6 $RA,: machulw$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,machulw_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (FLD (f_u6), -65536))));
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = (GTUDI (tmp_old, tmp_tmp)) ? (( tmp_tmp = -1, 1)) : (0);
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* machulw_L_r_r $RA,$RC: machulw$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,machulw_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), -65536))));
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = (GTUDI (tmp_old, tmp_tmp)) ? (( tmp_tmp = -1, 1)) : (0);
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* machulw_cc $RA,$RC: machulw$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,machulw_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), -65536))));
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = (GTUDI (tmp_old, tmp_tmp)) ? (( tmp_tmp = -1, 1)) : (0);
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* current_loop_end: */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,current_loop_end) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDBI (EQSI (pc, GET_H_AUXR (((UINT) 3))), NOTBI (CPU (h_lbit)))) {
+{
+ {
+ SI opval = ADDSI (GET_H_CR (((UINT) 60)), -1);
+ SET_H_CR (((UINT) 60), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GET_H_CR (((UINT) 60))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (GET_H_AUXR (((UINT) 2)), 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = GET_H_AUXR (((UINT) 2));
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* current_loop_end_after_branch: */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,current_loop_end_after_branch) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (
+#ifdef SEM_IN_SWITCH
+pbb_br_type != SEM_BRANCH_UNTAKEN
+#else
+CPU_PBB_BR_NPC (current_cpu) != SEM_BRANCH_UNTAKEN
+#endif
+) {
+
+#ifdef SEM_IN_SWITCH
+npc = pbb_br_npc; br_type = pbb_br_type;
+#else
+npc = CPU_PBB_BR_NPC (current_cpu); br_type = CPU_PBB_BR_TYPE (current_cpu);
+#endif
+}
+ else if (ANDBI (EQSI (pc, GET_H_AUXR (((UINT) 3))), NOTBI (CPU (h_lbit)))) {
+{
+ {
+ SI opval = ADDSI (GET_H_CR (((UINT) 60)), -1);
+ SET_H_CR (((UINT) 60), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GET_H_CR (((UINT) 60))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (GET_H_AUXR (((UINT) 2)), 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = GET_H_AUXR (((UINT) 2));
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* arc600_current_loop_end_after_branch: */
+
+static SEM_PC
+SEM_FN_NAME (arc600f,arc600_current_loop_end_after_branch) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (
+#ifdef SEM_IN_SWITCH
+pbb_br_type != SEM_BRANCH_UNTAKEN
+#else
+CPU_PBB_BR_NPC (current_cpu) != SEM_BRANCH_UNTAKEN
+#endif
+) {
+{
+
+#ifdef SEM_IN_SWITCH
+npc = pbb_br_npc; br_type = pbb_br_type;
+#else
+npc = CPU_PBB_BR_NPC (current_cpu); br_type = CPU_PBB_BR_TYPE (current_cpu);
+#endif
+ {
+ SI opval = ADDSI (GET_H_CR (((UINT) 60)), -1);
+ SET_H_CR (((UINT) 60), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+ else if (ANDBI (EQSI (pc, GET_H_AUXR (((UINT) 3))), NOTBI (CPU (h_lbit)))) {
+{
+ {
+ SI opval = ADDSI (GET_H_CR (((UINT) 60)), -1);
+ SET_H_CR (((UINT) 60), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GET_H_CR (((UINT) 60))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (GET_H_AUXR (((UINT) 2)), 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = GET_H_AUXR (((UINT) 2));
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* Table of all semantic fns. */
+
+static const struct sem_fn_desc sem_fns[] = {
+ { ARC600F_INSN_X_INVALID, SEM_FN_NAME (arc600f,x_invalid) },
+ { ARC600F_INSN_X_AFTER, SEM_FN_NAME (arc600f,x_after) },
+ { ARC600F_INSN_X_BEFORE, SEM_FN_NAME (arc600f,x_before) },
+ { ARC600F_INSN_X_CTI_CHAIN, SEM_FN_NAME (arc600f,x_cti_chain) },
+ { ARC600F_INSN_X_CHAIN, SEM_FN_NAME (arc600f,x_chain) },
+ { ARC600F_INSN_X_BEGIN, SEM_FN_NAME (arc600f,x_begin) },
+ { ARC600F_INSN_B_S, SEM_FN_NAME (arc600f,b_s) },
+ { ARC600F_INSN_BCC_S, SEM_FN_NAME (arc600f,bcc_s) },
+ { ARC600F_INSN_BRCC_S, SEM_FN_NAME (arc600f,brcc_s) },
+ { ARC600F_INSN_BCC_L, SEM_FN_NAME (arc600f,bcc_l) },
+ { ARC600F_INSN_BCC_L_D, SEM_FN_NAME (arc600f,bcc_l_d) },
+ { ARC600F_INSN_B_L, SEM_FN_NAME (arc600f,b_l) },
+ { ARC600F_INSN_B_L_D, SEM_FN_NAME (arc600f,b_l_d) },
+ { ARC600F_INSN_BRCC_RC, SEM_FN_NAME (arc600f,brcc_RC) },
+ { ARC600F_INSN_BRCC_RC_D, SEM_FN_NAME (arc600f,brcc_RC_d) },
+ { ARC600F_INSN_BRCC_U6, SEM_FN_NAME (arc600f,brcc_U6) },
+ { ARC600F_INSN_BRCC_U6_D, SEM_FN_NAME (arc600f,brcc_U6_d) },
+ { ARC600F_INSN_BL_S, SEM_FN_NAME (arc600f,bl_s) },
+ { ARC600F_INSN_BLCC, SEM_FN_NAME (arc600f,blcc) },
+ { ARC600F_INSN_BLCC_D, SEM_FN_NAME (arc600f,blcc_d) },
+ { ARC600F_INSN_BL, SEM_FN_NAME (arc600f,bl) },
+ { ARC600F_INSN_BL_D, SEM_FN_NAME (arc600f,bl_d) },
+ { ARC600F_INSN_LD_ABS, SEM_FN_NAME (arc600f,ld_abs) },
+ { ARC600F_INSN_LD__AW_ABS, SEM_FN_NAME (arc600f,ld__AW_abs) },
+ { ARC600F_INSN_LD_AB_ABS, SEM_FN_NAME (arc600f,ld_ab_abs) },
+ { ARC600F_INSN_LD_AS_ABS, SEM_FN_NAME (arc600f,ld_as_abs) },
+ { ARC600F_INSN_LD_ABC, SEM_FN_NAME (arc600f,ld_abc) },
+ { ARC600F_INSN_LD__AW_ABC, SEM_FN_NAME (arc600f,ld__AW_abc) },
+ { ARC600F_INSN_LD_AB_ABC, SEM_FN_NAME (arc600f,ld_ab_abc) },
+ { ARC600F_INSN_LD_AS_ABC, SEM_FN_NAME (arc600f,ld_as_abc) },
+ { ARC600F_INSN_LD_S_ABC, SEM_FN_NAME (arc600f,ld_s_abc) },
+ { ARC600F_INSN_LD_S_ABU, SEM_FN_NAME (arc600f,ld_s_abu) },
+ { ARC600F_INSN_LD_S_ABSP, SEM_FN_NAME (arc600f,ld_s_absp) },
+ { ARC600F_INSN_LD_S_GPREL, SEM_FN_NAME (arc600f,ld_s_gprel) },
+ { ARC600F_INSN_LD_S_PCREL, SEM_FN_NAME (arc600f,ld_s_pcrel) },
+ { ARC600F_INSN_LDB_ABS, SEM_FN_NAME (arc600f,ldb_abs) },
+ { ARC600F_INSN_LDB__AW_ABS, SEM_FN_NAME (arc600f,ldb__AW_abs) },
+ { ARC600F_INSN_LDB_AB_ABS, SEM_FN_NAME (arc600f,ldb_ab_abs) },
+ { ARC600F_INSN_LDB_AS_ABS, SEM_FN_NAME (arc600f,ldb_as_abs) },
+ { ARC600F_INSN_LDB_ABC, SEM_FN_NAME (arc600f,ldb_abc) },
+ { ARC600F_INSN_LDB__AW_ABC, SEM_FN_NAME (arc600f,ldb__AW_abc) },
+ { ARC600F_INSN_LDB_AB_ABC, SEM_FN_NAME (arc600f,ldb_ab_abc) },
+ { ARC600F_INSN_LDB_AS_ABC, SEM_FN_NAME (arc600f,ldb_as_abc) },
+ { ARC600F_INSN_LDB_S_ABC, SEM_FN_NAME (arc600f,ldb_s_abc) },
+ { ARC600F_INSN_LDB_S_ABU, SEM_FN_NAME (arc600f,ldb_s_abu) },
+ { ARC600F_INSN_LDB_S_ABSP, SEM_FN_NAME (arc600f,ldb_s_absp) },
+ { ARC600F_INSN_LDB_S_GPREL, SEM_FN_NAME (arc600f,ldb_s_gprel) },
+ { ARC600F_INSN_LDB_X_ABS, SEM_FN_NAME (arc600f,ldb_x_abs) },
+ { ARC600F_INSN_LDB__AW_X_ABS, SEM_FN_NAME (arc600f,ldb__AW_x_abs) },
+ { ARC600F_INSN_LDB_AB_X_ABS, SEM_FN_NAME (arc600f,ldb_ab_x_abs) },
+ { ARC600F_INSN_LDB_AS_X_ABS, SEM_FN_NAME (arc600f,ldb_as_x_abs) },
+ { ARC600F_INSN_LDB_X_ABC, SEM_FN_NAME (arc600f,ldb_x_abc) },
+ { ARC600F_INSN_LDB__AW_X_ABC, SEM_FN_NAME (arc600f,ldb__AW_x_abc) },
+ { ARC600F_INSN_LDB_AB_X_ABC, SEM_FN_NAME (arc600f,ldb_ab_x_abc) },
+ { ARC600F_INSN_LDB_AS_X_ABC, SEM_FN_NAME (arc600f,ldb_as_x_abc) },
+ { ARC600F_INSN_LDW_ABS, SEM_FN_NAME (arc600f,ldw_abs) },
+ { ARC600F_INSN_LDW__AW_ABS, SEM_FN_NAME (arc600f,ldw__AW_abs) },
+ { ARC600F_INSN_LDW_AB_ABS, SEM_FN_NAME (arc600f,ldw_ab_abs) },
+ { ARC600F_INSN_LDW_AS_ABS, SEM_FN_NAME (arc600f,ldw_as_abs) },
+ { ARC600F_INSN_LDW_ABC, SEM_FN_NAME (arc600f,ldw_abc) },
+ { ARC600F_INSN_LDW__AW_ABC, SEM_FN_NAME (arc600f,ldw__AW_abc) },
+ { ARC600F_INSN_LDW_AB_ABC, SEM_FN_NAME (arc600f,ldw_ab_abc) },
+ { ARC600F_INSN_LDW_AS_ABC, SEM_FN_NAME (arc600f,ldw_as_abc) },
+ { ARC600F_INSN_LDW_S_ABC, SEM_FN_NAME (arc600f,ldw_s_abc) },
+ { ARC600F_INSN_LDW_S_ABU, SEM_FN_NAME (arc600f,ldw_s_abu) },
+ { ARC600F_INSN_LDW_S_GPREL, SEM_FN_NAME (arc600f,ldw_s_gprel) },
+ { ARC600F_INSN_LDW_X_ABS, SEM_FN_NAME (arc600f,ldw_x_abs) },
+ { ARC600F_INSN_LDW__AW_X_ABS, SEM_FN_NAME (arc600f,ldw__AW_x_abs) },
+ { ARC600F_INSN_LDW_AB_X_ABS, SEM_FN_NAME (arc600f,ldw_ab_x_abs) },
+ { ARC600F_INSN_LDW_AS_X_ABS, SEM_FN_NAME (arc600f,ldw_as_x_abs) },
+ { ARC600F_INSN_LDW_X_ABC, SEM_FN_NAME (arc600f,ldw_x_abc) },
+ { ARC600F_INSN_LDW__AW_X_ABC, SEM_FN_NAME (arc600f,ldw__AW_x_abc) },
+ { ARC600F_INSN_LDW_AB_X_ABC, SEM_FN_NAME (arc600f,ldw_ab_x_abc) },
+ { ARC600F_INSN_LDW_AS_X_ABC, SEM_FN_NAME (arc600f,ldw_as_x_abc) },
+ { ARC600F_INSN_LDW_S_X_ABU, SEM_FN_NAME (arc600f,ldw_s_x_abu) },
+ { ARC600F_INSN_ST_ABS, SEM_FN_NAME (arc600f,st_abs) },
+ { ARC600F_INSN_ST__AW_ABS, SEM_FN_NAME (arc600f,st__AW_abs) },
+ { ARC600F_INSN_ST_AB_ABS, SEM_FN_NAME (arc600f,st_ab_abs) },
+ { ARC600F_INSN_ST_AS_ABS, SEM_FN_NAME (arc600f,st_as_abs) },
+ { ARC600F_INSN_ST_S_ABU, SEM_FN_NAME (arc600f,st_s_abu) },
+ { ARC600F_INSN_ST_S_ABSP, SEM_FN_NAME (arc600f,st_s_absp) },
+ { ARC600F_INSN_STB_ABS, SEM_FN_NAME (arc600f,stb_abs) },
+ { ARC600F_INSN_STB__AW_ABS, SEM_FN_NAME (arc600f,stb__AW_abs) },
+ { ARC600F_INSN_STB_AB_ABS, SEM_FN_NAME (arc600f,stb_ab_abs) },
+ { ARC600F_INSN_STB_AS_ABS, SEM_FN_NAME (arc600f,stb_as_abs) },
+ { ARC600F_INSN_STB_S_ABU, SEM_FN_NAME (arc600f,stb_s_abu) },
+ { ARC600F_INSN_STB_S_ABSP, SEM_FN_NAME (arc600f,stb_s_absp) },
+ { ARC600F_INSN_STW_ABS, SEM_FN_NAME (arc600f,stw_abs) },
+ { ARC600F_INSN_STW__AW_ABS, SEM_FN_NAME (arc600f,stw__AW_abs) },
+ { ARC600F_INSN_STW_AB_ABS, SEM_FN_NAME (arc600f,stw_ab_abs) },
+ { ARC600F_INSN_STW_AS_ABS, SEM_FN_NAME (arc600f,stw_as_abs) },
+ { ARC600F_INSN_STW_S_ABU, SEM_FN_NAME (arc600f,stw_s_abu) },
+ { ARC600F_INSN_ADD_L_S12__RA_, SEM_FN_NAME (arc600f,add_L_s12__RA_) },
+ { ARC600F_INSN_ADD_CCU6__RA_, SEM_FN_NAME (arc600f,add_ccu6__RA_) },
+ { ARC600F_INSN_ADD_L_U6__RA_, SEM_FN_NAME (arc600f,add_L_u6__RA_) },
+ { ARC600F_INSN_ADD_L_R_R__RA__RC, SEM_FN_NAME (arc600f,add_L_r_r__RA__RC) },
+ { ARC600F_INSN_ADD_CC__RA__RC, SEM_FN_NAME (arc600f,add_cc__RA__RC) },
+ { ARC600F_INSN_ADD_S_ABC, SEM_FN_NAME (arc600f,add_s_abc) },
+ { ARC600F_INSN_ADD_S_CBU3, SEM_FN_NAME (arc600f,add_s_cbu3) },
+ { ARC600F_INSN_ADD_S_MCAH, SEM_FN_NAME (arc600f,add_s_mcah) },
+ { ARC600F_INSN_ADD_S_ABSP, SEM_FN_NAME (arc600f,add_s_absp) },
+ { ARC600F_INSN_ADD_S_ASSPSP, SEM_FN_NAME (arc600f,add_s_asspsp) },
+ { ARC600F_INSN_ADD_S_GP, SEM_FN_NAME (arc600f,add_s_gp) },
+ { ARC600F_INSN_ADD_S_R_U7, SEM_FN_NAME (arc600f,add_s_r_u7) },
+ { ARC600F_INSN_ADC_L_S12__RA_, SEM_FN_NAME (arc600f,adc_L_s12__RA_) },
+ { ARC600F_INSN_ADC_CCU6__RA_, SEM_FN_NAME (arc600f,adc_ccu6__RA_) },
+ { ARC600F_INSN_ADC_L_U6__RA_, SEM_FN_NAME (arc600f,adc_L_u6__RA_) },
+ { ARC600F_INSN_ADC_L_R_R__RA__RC, SEM_FN_NAME (arc600f,adc_L_r_r__RA__RC) },
+ { ARC600F_INSN_ADC_CC__RA__RC, SEM_FN_NAME (arc600f,adc_cc__RA__RC) },
+ { ARC600F_INSN_SUB_L_S12__RA_, SEM_FN_NAME (arc600f,sub_L_s12__RA_) },
+ { ARC600F_INSN_SUB_CCU6__RA_, SEM_FN_NAME (arc600f,sub_ccu6__RA_) },
+ { ARC600F_INSN_SUB_L_U6__RA_, SEM_FN_NAME (arc600f,sub_L_u6__RA_) },
+ { ARC600F_INSN_SUB_L_R_R__RA__RC, SEM_FN_NAME (arc600f,sub_L_r_r__RA__RC) },
+ { ARC600F_INSN_SUB_CC__RA__RC, SEM_FN_NAME (arc600f,sub_cc__RA__RC) },
+ { ARC600F_INSN_SUB_S_CBU3, SEM_FN_NAME (arc600f,sub_s_cbu3) },
+ { ARC600F_INSN_I16_GO_SUB_S_GO, SEM_FN_NAME (arc600f,I16_GO_SUB_s_go) },
+ { ARC600F_INSN_SUB_S_GO_SUB_NE, SEM_FN_NAME (arc600f,sub_s_go_sub_ne) },
+ { ARC600F_INSN_SUB_S_SSB, SEM_FN_NAME (arc600f,sub_s_ssb) },
+ { ARC600F_INSN_SUB_S_ASSPSP, SEM_FN_NAME (arc600f,sub_s_asspsp) },
+ { ARC600F_INSN_SBC_L_S12__RA_, SEM_FN_NAME (arc600f,sbc_L_s12__RA_) },
+ { ARC600F_INSN_SBC_CCU6__RA_, SEM_FN_NAME (arc600f,sbc_ccu6__RA_) },
+ { ARC600F_INSN_SBC_L_U6__RA_, SEM_FN_NAME (arc600f,sbc_L_u6__RA_) },
+ { ARC600F_INSN_SBC_L_R_R__RA__RC, SEM_FN_NAME (arc600f,sbc_L_r_r__RA__RC) },
+ { ARC600F_INSN_SBC_CC__RA__RC, SEM_FN_NAME (arc600f,sbc_cc__RA__RC) },
+ { ARC600F_INSN_AND_L_S12__RA_, SEM_FN_NAME (arc600f,and_L_s12__RA_) },
+ { ARC600F_INSN_AND_CCU6__RA_, SEM_FN_NAME (arc600f,and_ccu6__RA_) },
+ { ARC600F_INSN_AND_L_U6__RA_, SEM_FN_NAME (arc600f,and_L_u6__RA_) },
+ { ARC600F_INSN_AND_L_R_R__RA__RC, SEM_FN_NAME (arc600f,and_L_r_r__RA__RC) },
+ { ARC600F_INSN_AND_CC__RA__RC, SEM_FN_NAME (arc600f,and_cc__RA__RC) },
+ { ARC600F_INSN_I16_GO_AND_S_GO, SEM_FN_NAME (arc600f,I16_GO_AND_s_go) },
+ { ARC600F_INSN_OR_L_S12__RA_, SEM_FN_NAME (arc600f,or_L_s12__RA_) },
+ { ARC600F_INSN_OR_CCU6__RA_, SEM_FN_NAME (arc600f,or_ccu6__RA_) },
+ { ARC600F_INSN_OR_L_U6__RA_, SEM_FN_NAME (arc600f,or_L_u6__RA_) },
+ { ARC600F_INSN_OR_L_R_R__RA__RC, SEM_FN_NAME (arc600f,or_L_r_r__RA__RC) },
+ { ARC600F_INSN_OR_CC__RA__RC, SEM_FN_NAME (arc600f,or_cc__RA__RC) },
+ { ARC600F_INSN_I16_GO_OR_S_GO, SEM_FN_NAME (arc600f,I16_GO_OR_s_go) },
+ { ARC600F_INSN_BIC_L_S12__RA_, SEM_FN_NAME (arc600f,bic_L_s12__RA_) },
+ { ARC600F_INSN_BIC_CCU6__RA_, SEM_FN_NAME (arc600f,bic_ccu6__RA_) },
+ { ARC600F_INSN_BIC_L_U6__RA_, SEM_FN_NAME (arc600f,bic_L_u6__RA_) },
+ { ARC600F_INSN_BIC_L_R_R__RA__RC, SEM_FN_NAME (arc600f,bic_L_r_r__RA__RC) },
+ { ARC600F_INSN_BIC_CC__RA__RC, SEM_FN_NAME (arc600f,bic_cc__RA__RC) },
+ { ARC600F_INSN_I16_GO_BIC_S_GO, SEM_FN_NAME (arc600f,I16_GO_BIC_s_go) },
+ { ARC600F_INSN_XOR_L_S12__RA_, SEM_FN_NAME (arc600f,xor_L_s12__RA_) },
+ { ARC600F_INSN_XOR_CCU6__RA_, SEM_FN_NAME (arc600f,xor_ccu6__RA_) },
+ { ARC600F_INSN_XOR_L_U6__RA_, SEM_FN_NAME (arc600f,xor_L_u6__RA_) },
+ { ARC600F_INSN_XOR_L_R_R__RA__RC, SEM_FN_NAME (arc600f,xor_L_r_r__RA__RC) },
+ { ARC600F_INSN_XOR_CC__RA__RC, SEM_FN_NAME (arc600f,xor_cc__RA__RC) },
+ { ARC600F_INSN_I16_GO_XOR_S_GO, SEM_FN_NAME (arc600f,I16_GO_XOR_s_go) },
+ { ARC600F_INSN_MAX_L_S12__RA_, SEM_FN_NAME (arc600f,max_L_s12__RA_) },
+ { ARC600F_INSN_MAX_CCU6__RA_, SEM_FN_NAME (arc600f,max_ccu6__RA_) },
+ { ARC600F_INSN_MAX_L_U6__RA_, SEM_FN_NAME (arc600f,max_L_u6__RA_) },
+ { ARC600F_INSN_MAX_L_R_R__RA__RC, SEM_FN_NAME (arc600f,max_L_r_r__RA__RC) },
+ { ARC600F_INSN_MAX_CC__RA__RC, SEM_FN_NAME (arc600f,max_cc__RA__RC) },
+ { ARC600F_INSN_MIN_L_S12__RA_, SEM_FN_NAME (arc600f,min_L_s12__RA_) },
+ { ARC600F_INSN_MIN_CCU6__RA_, SEM_FN_NAME (arc600f,min_ccu6__RA_) },
+ { ARC600F_INSN_MIN_L_U6__RA_, SEM_FN_NAME (arc600f,min_L_u6__RA_) },
+ { ARC600F_INSN_MIN_L_R_R__RA__RC, SEM_FN_NAME (arc600f,min_L_r_r__RA__RC) },
+ { ARC600F_INSN_MIN_CC__RA__RC, SEM_FN_NAME (arc600f,min_cc__RA__RC) },
+ { ARC600F_INSN_MOV_L_S12_, SEM_FN_NAME (arc600f,mov_L_s12_) },
+ { ARC600F_INSN_MOV_CCU6_, SEM_FN_NAME (arc600f,mov_ccu6_) },
+ { ARC600F_INSN_MOV_L_U6_, SEM_FN_NAME (arc600f,mov_L_u6_) },
+ { ARC600F_INSN_MOV_L_R_R__RC, SEM_FN_NAME (arc600f,mov_L_r_r__RC) },
+ { ARC600F_INSN_MOV_CC__RC, SEM_FN_NAME (arc600f,mov_cc__RC) },
+ { ARC600F_INSN_MOV_S_MCAH, SEM_FN_NAME (arc600f,mov_s_mcah) },
+ { ARC600F_INSN_MOV_S_MCAHB, SEM_FN_NAME (arc600f,mov_s_mcahb) },
+ { ARC600F_INSN_MOV_S_R_U7, SEM_FN_NAME (arc600f,mov_s_r_u7) },
+ { ARC600F_INSN_TST_L_S12_, SEM_FN_NAME (arc600f,tst_L_s12_) },
+ { ARC600F_INSN_TST_CCU6_, SEM_FN_NAME (arc600f,tst_ccu6_) },
+ { ARC600F_INSN_TST_L_U6_, SEM_FN_NAME (arc600f,tst_L_u6_) },
+ { ARC600F_INSN_TST_L_R_R__RC, SEM_FN_NAME (arc600f,tst_L_r_r__RC) },
+ { ARC600F_INSN_TST_CC__RC, SEM_FN_NAME (arc600f,tst_cc__RC) },
+ { ARC600F_INSN_TST_S_GO, SEM_FN_NAME (arc600f,tst_s_go) },
+ { ARC600F_INSN_CMP_L_S12_, SEM_FN_NAME (arc600f,cmp_L_s12_) },
+ { ARC600F_INSN_CMP_CCU6_, SEM_FN_NAME (arc600f,cmp_ccu6_) },
+ { ARC600F_INSN_CMP_L_U6_, SEM_FN_NAME (arc600f,cmp_L_u6_) },
+ { ARC600F_INSN_CMP_L_R_R__RC, SEM_FN_NAME (arc600f,cmp_L_r_r__RC) },
+ { ARC600F_INSN_CMP_CC__RC, SEM_FN_NAME (arc600f,cmp_cc__RC) },
+ { ARC600F_INSN_CMP_S_MCAH, SEM_FN_NAME (arc600f,cmp_s_mcah) },
+ { ARC600F_INSN_CMP_S_R_U7, SEM_FN_NAME (arc600f,cmp_s_r_u7) },
+ { ARC600F_INSN_RCMP_L_S12_, SEM_FN_NAME (arc600f,rcmp_L_s12_) },
+ { ARC600F_INSN_RCMP_CCU6_, SEM_FN_NAME (arc600f,rcmp_ccu6_) },
+ { ARC600F_INSN_RCMP_L_U6_, SEM_FN_NAME (arc600f,rcmp_L_u6_) },
+ { ARC600F_INSN_RCMP_L_R_R__RC, SEM_FN_NAME (arc600f,rcmp_L_r_r__RC) },
+ { ARC600F_INSN_RCMP_CC__RC, SEM_FN_NAME (arc600f,rcmp_cc__RC) },
+ { ARC600F_INSN_RSUB_L_S12__RA_, SEM_FN_NAME (arc600f,rsub_L_s12__RA_) },
+ { ARC600F_INSN_RSUB_CCU6__RA_, SEM_FN_NAME (arc600f,rsub_ccu6__RA_) },
+ { ARC600F_INSN_RSUB_L_U6__RA_, SEM_FN_NAME (arc600f,rsub_L_u6__RA_) },
+ { ARC600F_INSN_RSUB_L_R_R__RA__RC, SEM_FN_NAME (arc600f,rsub_L_r_r__RA__RC) },
+ { ARC600F_INSN_RSUB_CC__RA__RC, SEM_FN_NAME (arc600f,rsub_cc__RA__RC) },
+ { ARC600F_INSN_BSET_L_S12__RA_, SEM_FN_NAME (arc600f,bset_L_s12__RA_) },
+ { ARC600F_INSN_BSET_CCU6__RA_, SEM_FN_NAME (arc600f,bset_ccu6__RA_) },
+ { ARC600F_INSN_BSET_L_U6__RA_, SEM_FN_NAME (arc600f,bset_L_u6__RA_) },
+ { ARC600F_INSN_BSET_L_R_R__RA__RC, SEM_FN_NAME (arc600f,bset_L_r_r__RA__RC) },
+ { ARC600F_INSN_BSET_CC__RA__RC, SEM_FN_NAME (arc600f,bset_cc__RA__RC) },
+ { ARC600F_INSN_BSET_S_SSB, SEM_FN_NAME (arc600f,bset_s_ssb) },
+ { ARC600F_INSN_BCLR_L_S12__RA_, SEM_FN_NAME (arc600f,bclr_L_s12__RA_) },
+ { ARC600F_INSN_BCLR_CCU6__RA_, SEM_FN_NAME (arc600f,bclr_ccu6__RA_) },
+ { ARC600F_INSN_BCLR_L_U6__RA_, SEM_FN_NAME (arc600f,bclr_L_u6__RA_) },
+ { ARC600F_INSN_BCLR_L_R_R__RA__RC, SEM_FN_NAME (arc600f,bclr_L_r_r__RA__RC) },
+ { ARC600F_INSN_BCLR_CC__RA__RC, SEM_FN_NAME (arc600f,bclr_cc__RA__RC) },
+ { ARC600F_INSN_BCLR_S_SSB, SEM_FN_NAME (arc600f,bclr_s_ssb) },
+ { ARC600F_INSN_BTST_L_S12_, SEM_FN_NAME (arc600f,btst_L_s12_) },
+ { ARC600F_INSN_BTST_CCU6_, SEM_FN_NAME (arc600f,btst_ccu6_) },
+ { ARC600F_INSN_BTST_L_U6_, SEM_FN_NAME (arc600f,btst_L_u6_) },
+ { ARC600F_INSN_BTST_L_R_R__RC, SEM_FN_NAME (arc600f,btst_L_r_r__RC) },
+ { ARC600F_INSN_BTST_CC__RC, SEM_FN_NAME (arc600f,btst_cc__RC) },
+ { ARC600F_INSN_BTST_S_SSB, SEM_FN_NAME (arc600f,btst_s_ssb) },
+ { ARC600F_INSN_BXOR_L_S12__RA_, SEM_FN_NAME (arc600f,bxor_L_s12__RA_) },
+ { ARC600F_INSN_BXOR_CCU6__RA_, SEM_FN_NAME (arc600f,bxor_ccu6__RA_) },
+ { ARC600F_INSN_BXOR_L_U6__RA_, SEM_FN_NAME (arc600f,bxor_L_u6__RA_) },
+ { ARC600F_INSN_BXOR_L_R_R__RA__RC, SEM_FN_NAME (arc600f,bxor_L_r_r__RA__RC) },
+ { ARC600F_INSN_BXOR_CC__RA__RC, SEM_FN_NAME (arc600f,bxor_cc__RA__RC) },
+ { ARC600F_INSN_BMSK_L_S12__RA_, SEM_FN_NAME (arc600f,bmsk_L_s12__RA_) },
+ { ARC600F_INSN_BMSK_CCU6__RA_, SEM_FN_NAME (arc600f,bmsk_ccu6__RA_) },
+ { ARC600F_INSN_BMSK_L_U6__RA_, SEM_FN_NAME (arc600f,bmsk_L_u6__RA_) },
+ { ARC600F_INSN_BMSK_L_R_R__RA__RC, SEM_FN_NAME (arc600f,bmsk_L_r_r__RA__RC) },
+ { ARC600F_INSN_BMSK_CC__RA__RC, SEM_FN_NAME (arc600f,bmsk_cc__RA__RC) },
+ { ARC600F_INSN_BMSK_S_SSB, SEM_FN_NAME (arc600f,bmsk_s_ssb) },
+ { ARC600F_INSN_ADD1_L_S12__RA_, SEM_FN_NAME (arc600f,add1_L_s12__RA_) },
+ { ARC600F_INSN_ADD1_CCU6__RA_, SEM_FN_NAME (arc600f,add1_ccu6__RA_) },
+ { ARC600F_INSN_ADD1_L_U6__RA_, SEM_FN_NAME (arc600f,add1_L_u6__RA_) },
+ { ARC600F_INSN_ADD1_L_R_R__RA__RC, SEM_FN_NAME (arc600f,add1_L_r_r__RA__RC) },
+ { ARC600F_INSN_ADD1_CC__RA__RC, SEM_FN_NAME (arc600f,add1_cc__RA__RC) },
+ { ARC600F_INSN_I16_GO_ADD1_S_GO, SEM_FN_NAME (arc600f,I16_GO_ADD1_s_go) },
+ { ARC600F_INSN_ADD2_L_S12__RA_, SEM_FN_NAME (arc600f,add2_L_s12__RA_) },
+ { ARC600F_INSN_ADD2_CCU6__RA_, SEM_FN_NAME (arc600f,add2_ccu6__RA_) },
+ { ARC600F_INSN_ADD2_L_U6__RA_, SEM_FN_NAME (arc600f,add2_L_u6__RA_) },
+ { ARC600F_INSN_ADD2_L_R_R__RA__RC, SEM_FN_NAME (arc600f,add2_L_r_r__RA__RC) },
+ { ARC600F_INSN_ADD2_CC__RA__RC, SEM_FN_NAME (arc600f,add2_cc__RA__RC) },
+ { ARC600F_INSN_I16_GO_ADD2_S_GO, SEM_FN_NAME (arc600f,I16_GO_ADD2_s_go) },
+ { ARC600F_INSN_ADD3_L_S12__RA_, SEM_FN_NAME (arc600f,add3_L_s12__RA_) },
+ { ARC600F_INSN_ADD3_CCU6__RA_, SEM_FN_NAME (arc600f,add3_ccu6__RA_) },
+ { ARC600F_INSN_ADD3_L_U6__RA_, SEM_FN_NAME (arc600f,add3_L_u6__RA_) },
+ { ARC600F_INSN_ADD3_L_R_R__RA__RC, SEM_FN_NAME (arc600f,add3_L_r_r__RA__RC) },
+ { ARC600F_INSN_ADD3_CC__RA__RC, SEM_FN_NAME (arc600f,add3_cc__RA__RC) },
+ { ARC600F_INSN_I16_GO_ADD3_S_GO, SEM_FN_NAME (arc600f,I16_GO_ADD3_s_go) },
+ { ARC600F_INSN_SUB1_L_S12__RA_, SEM_FN_NAME (arc600f,sub1_L_s12__RA_) },
+ { ARC600F_INSN_SUB1_CCU6__RA_, SEM_FN_NAME (arc600f,sub1_ccu6__RA_) },
+ { ARC600F_INSN_SUB1_L_U6__RA_, SEM_FN_NAME (arc600f,sub1_L_u6__RA_) },
+ { ARC600F_INSN_SUB1_L_R_R__RA__RC, SEM_FN_NAME (arc600f,sub1_L_r_r__RA__RC) },
+ { ARC600F_INSN_SUB1_CC__RA__RC, SEM_FN_NAME (arc600f,sub1_cc__RA__RC) },
+ { ARC600F_INSN_SUB2_L_S12__RA_, SEM_FN_NAME (arc600f,sub2_L_s12__RA_) },
+ { ARC600F_INSN_SUB2_CCU6__RA_, SEM_FN_NAME (arc600f,sub2_ccu6__RA_) },
+ { ARC600F_INSN_SUB2_L_U6__RA_, SEM_FN_NAME (arc600f,sub2_L_u6__RA_) },
+ { ARC600F_INSN_SUB2_L_R_R__RA__RC, SEM_FN_NAME (arc600f,sub2_L_r_r__RA__RC) },
+ { ARC600F_INSN_SUB2_CC__RA__RC, SEM_FN_NAME (arc600f,sub2_cc__RA__RC) },
+ { ARC600F_INSN_SUB3_L_S12__RA_, SEM_FN_NAME (arc600f,sub3_L_s12__RA_) },
+ { ARC600F_INSN_SUB3_CCU6__RA_, SEM_FN_NAME (arc600f,sub3_ccu6__RA_) },
+ { ARC600F_INSN_SUB3_L_U6__RA_, SEM_FN_NAME (arc600f,sub3_L_u6__RA_) },
+ { ARC600F_INSN_SUB3_L_R_R__RA__RC, SEM_FN_NAME (arc600f,sub3_L_r_r__RA__RC) },
+ { ARC600F_INSN_SUB3_CC__RA__RC, SEM_FN_NAME (arc600f,sub3_cc__RA__RC) },
+ { ARC600F_INSN_MPY_L_S12__RA_, SEM_FN_NAME (arc600f,mpy_L_s12__RA_) },
+ { ARC600F_INSN_MPY_CCU6__RA_, SEM_FN_NAME (arc600f,mpy_ccu6__RA_) },
+ { ARC600F_INSN_MPY_L_U6__RA_, SEM_FN_NAME (arc600f,mpy_L_u6__RA_) },
+ { ARC600F_INSN_MPY_L_R_R__RA__RC, SEM_FN_NAME (arc600f,mpy_L_r_r__RA__RC) },
+ { ARC600F_INSN_MPY_CC__RA__RC, SEM_FN_NAME (arc600f,mpy_cc__RA__RC) },
+ { ARC600F_INSN_MPYH_L_S12__RA_, SEM_FN_NAME (arc600f,mpyh_L_s12__RA_) },
+ { ARC600F_INSN_MPYH_CCU6__RA_, SEM_FN_NAME (arc600f,mpyh_ccu6__RA_) },
+ { ARC600F_INSN_MPYH_L_U6__RA_, SEM_FN_NAME (arc600f,mpyh_L_u6__RA_) },
+ { ARC600F_INSN_MPYH_L_R_R__RA__RC, SEM_FN_NAME (arc600f,mpyh_L_r_r__RA__RC) },
+ { ARC600F_INSN_MPYH_CC__RA__RC, SEM_FN_NAME (arc600f,mpyh_cc__RA__RC) },
+ { ARC600F_INSN_MPYHU_L_S12__RA_, SEM_FN_NAME (arc600f,mpyhu_L_s12__RA_) },
+ { ARC600F_INSN_MPYHU_CCU6__RA_, SEM_FN_NAME (arc600f,mpyhu_ccu6__RA_) },
+ { ARC600F_INSN_MPYHU_L_U6__RA_, SEM_FN_NAME (arc600f,mpyhu_L_u6__RA_) },
+ { ARC600F_INSN_MPYHU_L_R_R__RA__RC, SEM_FN_NAME (arc600f,mpyhu_L_r_r__RA__RC) },
+ { ARC600F_INSN_MPYHU_CC__RA__RC, SEM_FN_NAME (arc600f,mpyhu_cc__RA__RC) },
+ { ARC600F_INSN_MPYU_L_S12__RA_, SEM_FN_NAME (arc600f,mpyu_L_s12__RA_) },
+ { ARC600F_INSN_MPYU_CCU6__RA_, SEM_FN_NAME (arc600f,mpyu_ccu6__RA_) },
+ { ARC600F_INSN_MPYU_L_U6__RA_, SEM_FN_NAME (arc600f,mpyu_L_u6__RA_) },
+ { ARC600F_INSN_MPYU_L_R_R__RA__RC, SEM_FN_NAME (arc600f,mpyu_L_r_r__RA__RC) },
+ { ARC600F_INSN_MPYU_CC__RA__RC, SEM_FN_NAME (arc600f,mpyu_cc__RA__RC) },
+ { ARC600F_INSN_J_L_R_R___RC_NOILINK_, SEM_FN_NAME (arc600f,j_L_r_r___RC_noilink_) },
+ { ARC600F_INSN_J_CC___RC_NOILINK_, SEM_FN_NAME (arc600f,j_cc___RC_noilink_) },
+ { ARC600F_INSN_J_L_R_R___RC_ILINK_, SEM_FN_NAME (arc600f,j_L_r_r___RC_ilink_) },
+ { ARC600F_INSN_J_CC___RC_ILINK_, SEM_FN_NAME (arc600f,j_cc___RC_ilink_) },
+ { ARC600F_INSN_J_L_S12_, SEM_FN_NAME (arc600f,j_L_s12_) },
+ { ARC600F_INSN_J_CCU6_, SEM_FN_NAME (arc600f,j_ccu6_) },
+ { ARC600F_INSN_J_L_U6_, SEM_FN_NAME (arc600f,j_L_u6_) },
+ { ARC600F_INSN_J_S, SEM_FN_NAME (arc600f,j_s) },
+ { ARC600F_INSN_J_S__S, SEM_FN_NAME (arc600f,j_s__S) },
+ { ARC600F_INSN_J_SEQ__S, SEM_FN_NAME (arc600f,j_seq__S) },
+ { ARC600F_INSN_J_SNE__S, SEM_FN_NAME (arc600f,j_sne__S) },
+ { ARC600F_INSN_J_L_S12_D_, SEM_FN_NAME (arc600f,j_L_s12_d_) },
+ { ARC600F_INSN_J_CCU6_D_, SEM_FN_NAME (arc600f,j_ccu6_d_) },
+ { ARC600F_INSN_J_L_U6_D_, SEM_FN_NAME (arc600f,j_L_u6_d_) },
+ { ARC600F_INSN_J_L_R_R_D___RC_, SEM_FN_NAME (arc600f,j_L_r_r_d___RC_) },
+ { ARC600F_INSN_J_CC_D___RC_, SEM_FN_NAME (arc600f,j_cc_d___RC_) },
+ { ARC600F_INSN_J_S_D, SEM_FN_NAME (arc600f,j_s_d) },
+ { ARC600F_INSN_J_S__S_D, SEM_FN_NAME (arc600f,j_s__S_d) },
+ { ARC600F_INSN_JL_L_S12_, SEM_FN_NAME (arc600f,jl_L_s12_) },
+ { ARC600F_INSN_JL_CCU6_, SEM_FN_NAME (arc600f,jl_ccu6_) },
+ { ARC600F_INSN_JL_L_U6_, SEM_FN_NAME (arc600f,jl_L_u6_) },
+ { ARC600F_INSN_JL_S, SEM_FN_NAME (arc600f,jl_s) },
+ { ARC600F_INSN_JL_L_R_R___RC_NOILINK_, SEM_FN_NAME (arc600f,jl_L_r_r___RC_noilink_) },
+ { ARC600F_INSN_JL_CC___RC_NOILINK_, SEM_FN_NAME (arc600f,jl_cc___RC_noilink_) },
+ { ARC600F_INSN_JL_L_S12_D_, SEM_FN_NAME (arc600f,jl_L_s12_d_) },
+ { ARC600F_INSN_JL_CCU6_D_, SEM_FN_NAME (arc600f,jl_ccu6_d_) },
+ { ARC600F_INSN_JL_L_U6_D_, SEM_FN_NAME (arc600f,jl_L_u6_d_) },
+ { ARC600F_INSN_JL_L_R_R_D___RC_, SEM_FN_NAME (arc600f,jl_L_r_r_d___RC_) },
+ { ARC600F_INSN_JL_CC_D___RC_, SEM_FN_NAME (arc600f,jl_cc_d___RC_) },
+ { ARC600F_INSN_JL_S_D, SEM_FN_NAME (arc600f,jl_s_d) },
+ { ARC600F_INSN_LP_L_S12_, SEM_FN_NAME (arc600f,lp_L_s12_) },
+ { ARC600F_INSN_LPCC_CCU6, SEM_FN_NAME (arc600f,lpcc_ccu6) },
+ { ARC600F_INSN_FLAG_L_S12_, SEM_FN_NAME (arc600f,flag_L_s12_) },
+ { ARC600F_INSN_FLAG_CCU6_, SEM_FN_NAME (arc600f,flag_ccu6_) },
+ { ARC600F_INSN_FLAG_L_U6_, SEM_FN_NAME (arc600f,flag_L_u6_) },
+ { ARC600F_INSN_FLAG_L_R_R__RC, SEM_FN_NAME (arc600f,flag_L_r_r__RC) },
+ { ARC600F_INSN_FLAG_CC__RC, SEM_FN_NAME (arc600f,flag_cc__RC) },
+ { ARC600F_INSN_LR_L_R_R___RC_, SEM_FN_NAME (arc600f,lr_L_r_r___RC_) },
+ { ARC600F_INSN_LR_L_S12_, SEM_FN_NAME (arc600f,lr_L_s12_) },
+ { ARC600F_INSN_LR_L_U6_, SEM_FN_NAME (arc600f,lr_L_u6_) },
+ { ARC600F_INSN_SR_L_R_R___RC_, SEM_FN_NAME (arc600f,sr_L_r_r___RC_) },
+ { ARC600F_INSN_SR_L_S12_, SEM_FN_NAME (arc600f,sr_L_s12_) },
+ { ARC600F_INSN_SR_L_U6_, SEM_FN_NAME (arc600f,sr_L_u6_) },
+ { ARC600F_INSN_ASL_L_R_R__RC, SEM_FN_NAME (arc600f,asl_L_r_r__RC) },
+ { ARC600F_INSN_ASL_L_U6_, SEM_FN_NAME (arc600f,asl_L_u6_) },
+ { ARC600F_INSN_I16_GO_ASL_S_GO, SEM_FN_NAME (arc600f,I16_GO_ASL_s_go) },
+ { ARC600F_INSN_ASR_L_R_R__RC, SEM_FN_NAME (arc600f,asr_L_r_r__RC) },
+ { ARC600F_INSN_ASR_L_U6_, SEM_FN_NAME (arc600f,asr_L_u6_) },
+ { ARC600F_INSN_I16_GO_ASR_S_GO, SEM_FN_NAME (arc600f,I16_GO_ASR_s_go) },
+ { ARC600F_INSN_LSR_L_R_R__RC, SEM_FN_NAME (arc600f,lsr_L_r_r__RC) },
+ { ARC600F_INSN_LSR_L_U6_, SEM_FN_NAME (arc600f,lsr_L_u6_) },
+ { ARC600F_INSN_I16_GO_LSR_S_GO, SEM_FN_NAME (arc600f,I16_GO_LSR_s_go) },
+ { ARC600F_INSN_ROR_L_R_R__RC, SEM_FN_NAME (arc600f,ror_L_r_r__RC) },
+ { ARC600F_INSN_ROR_L_U6_, SEM_FN_NAME (arc600f,ror_L_u6_) },
+ { ARC600F_INSN_RRC_L_R_R__RC, SEM_FN_NAME (arc600f,rrc_L_r_r__RC) },
+ { ARC600F_INSN_RRC_L_U6_, SEM_FN_NAME (arc600f,rrc_L_u6_) },
+ { ARC600F_INSN_SEXB_L_R_R__RC, SEM_FN_NAME (arc600f,sexb_L_r_r__RC) },
+ { ARC600F_INSN_SEXB_L_U6_, SEM_FN_NAME (arc600f,sexb_L_u6_) },
+ { ARC600F_INSN_I16_GO_SEXB_S_GO, SEM_FN_NAME (arc600f,I16_GO_SEXB_s_go) },
+ { ARC600F_INSN_SEXW_L_R_R__RC, SEM_FN_NAME (arc600f,sexw_L_r_r__RC) },
+ { ARC600F_INSN_SEXW_L_U6_, SEM_FN_NAME (arc600f,sexw_L_u6_) },
+ { ARC600F_INSN_I16_GO_SEXW_S_GO, SEM_FN_NAME (arc600f,I16_GO_SEXW_s_go) },
+ { ARC600F_INSN_EXTB_L_R_R__RC, SEM_FN_NAME (arc600f,extb_L_r_r__RC) },
+ { ARC600F_INSN_EXTB_L_U6_, SEM_FN_NAME (arc600f,extb_L_u6_) },
+ { ARC600F_INSN_I16_GO_EXTB_S_GO, SEM_FN_NAME (arc600f,I16_GO_EXTB_s_go) },
+ { ARC600F_INSN_EXTW_L_R_R__RC, SEM_FN_NAME (arc600f,extw_L_r_r__RC) },
+ { ARC600F_INSN_EXTW_L_U6_, SEM_FN_NAME (arc600f,extw_L_u6_) },
+ { ARC600F_INSN_I16_GO_EXTW_S_GO, SEM_FN_NAME (arc600f,I16_GO_EXTW_s_go) },
+ { ARC600F_INSN_ABS_L_R_R__RC, SEM_FN_NAME (arc600f,abs_L_r_r__RC) },
+ { ARC600F_INSN_ABS_L_U6_, SEM_FN_NAME (arc600f,abs_L_u6_) },
+ { ARC600F_INSN_I16_GO_ABS_S_GO, SEM_FN_NAME (arc600f,I16_GO_ABS_s_go) },
+ { ARC600F_INSN_NOT_L_R_R__RC, SEM_FN_NAME (arc600f,not_L_r_r__RC) },
+ { ARC600F_INSN_NOT_L_U6_, SEM_FN_NAME (arc600f,not_L_u6_) },
+ { ARC600F_INSN_I16_GO_NOT_S_GO, SEM_FN_NAME (arc600f,I16_GO_NOT_s_go) },
+ { ARC600F_INSN_RLC_L_R_R__RC, SEM_FN_NAME (arc600f,rlc_L_r_r__RC) },
+ { ARC600F_INSN_RLC_L_U6_, SEM_FN_NAME (arc600f,rlc_L_u6_) },
+ { ARC600F_INSN_I16_GO_NEG_S_GO, SEM_FN_NAME (arc600f,I16_GO_NEG_s_go) },
+ { ARC600F_INSN_SWI, SEM_FN_NAME (arc600f,swi) },
+ { ARC600F_INSN_TRAP_S, SEM_FN_NAME (arc600f,trap_s) },
+ { ARC600F_INSN_BRK, SEM_FN_NAME (arc600f,brk) },
+ { ARC600F_INSN_BRK_S, SEM_FN_NAME (arc600f,brk_s) },
+ { ARC600F_INSN_ASL_L_S12__RA_, SEM_FN_NAME (arc600f,asl_L_s12__RA_) },
+ { ARC600F_INSN_ASL_CCU6__RA_, SEM_FN_NAME (arc600f,asl_ccu6__RA_) },
+ { ARC600F_INSN_ASL_L_U6__RA_, SEM_FN_NAME (arc600f,asl_L_u6__RA_) },
+ { ARC600F_INSN_ASL_L_R_R__RA__RC, SEM_FN_NAME (arc600f,asl_L_r_r__RA__RC) },
+ { ARC600F_INSN_ASL_CC__RA__RC, SEM_FN_NAME (arc600f,asl_cc__RA__RC) },
+ { ARC600F_INSN_ASL_S_CBU3, SEM_FN_NAME (arc600f,asl_s_cbu3) },
+ { ARC600F_INSN_ASL_S_SSB, SEM_FN_NAME (arc600f,asl_s_ssb) },
+ { ARC600F_INSN_I16_GO_ASLM_S_GO, SEM_FN_NAME (arc600f,I16_GO_ASLM_s_go) },
+ { ARC600F_INSN_LSR_L_S12__RA_, SEM_FN_NAME (arc600f,lsr_L_s12__RA_) },
+ { ARC600F_INSN_LSR_CCU6__RA_, SEM_FN_NAME (arc600f,lsr_ccu6__RA_) },
+ { ARC600F_INSN_LSR_L_U6__RA_, SEM_FN_NAME (arc600f,lsr_L_u6__RA_) },
+ { ARC600F_INSN_LSR_L_R_R__RA__RC, SEM_FN_NAME (arc600f,lsr_L_r_r__RA__RC) },
+ { ARC600F_INSN_LSR_CC__RA__RC, SEM_FN_NAME (arc600f,lsr_cc__RA__RC) },
+ { ARC600F_INSN_LSR_S_SSB, SEM_FN_NAME (arc600f,lsr_s_ssb) },
+ { ARC600F_INSN_I16_GO_LSRM_S_GO, SEM_FN_NAME (arc600f,I16_GO_LSRM_s_go) },
+ { ARC600F_INSN_ASR_L_S12__RA_, SEM_FN_NAME (arc600f,asr_L_s12__RA_) },
+ { ARC600F_INSN_ASR_CCU6__RA_, SEM_FN_NAME (arc600f,asr_ccu6__RA_) },
+ { ARC600F_INSN_ASR_L_U6__RA_, SEM_FN_NAME (arc600f,asr_L_u6__RA_) },
+ { ARC600F_INSN_ASR_L_R_R__RA__RC, SEM_FN_NAME (arc600f,asr_L_r_r__RA__RC) },
+ { ARC600F_INSN_ASR_CC__RA__RC, SEM_FN_NAME (arc600f,asr_cc__RA__RC) },
+ { ARC600F_INSN_ASR_S_CBU3, SEM_FN_NAME (arc600f,asr_s_cbu3) },
+ { ARC600F_INSN_ASR_S_SSB, SEM_FN_NAME (arc600f,asr_s_ssb) },
+ { ARC600F_INSN_I16_GO_ASRM_S_GO, SEM_FN_NAME (arc600f,I16_GO_ASRM_s_go) },
+ { ARC600F_INSN_ROR_L_S12__RA_, SEM_FN_NAME (arc600f,ror_L_s12__RA_) },
+ { ARC600F_INSN_ROR_CCU6__RA_, SEM_FN_NAME (arc600f,ror_ccu6__RA_) },
+ { ARC600F_INSN_ROR_L_U6__RA_, SEM_FN_NAME (arc600f,ror_L_u6__RA_) },
+ { ARC600F_INSN_ROR_L_R_R__RA__RC, SEM_FN_NAME (arc600f,ror_L_r_r__RA__RC) },
+ { ARC600F_INSN_ROR_CC__RA__RC, SEM_FN_NAME (arc600f,ror_cc__RA__RC) },
+ { ARC600F_INSN_MUL64_L_S12_, SEM_FN_NAME (arc600f,mul64_L_s12_) },
+ { ARC600F_INSN_MUL64_CCU6_, SEM_FN_NAME (arc600f,mul64_ccu6_) },
+ { ARC600F_INSN_MUL64_L_U6_, SEM_FN_NAME (arc600f,mul64_L_u6_) },
+ { ARC600F_INSN_MUL64_L_R_R__RC, SEM_FN_NAME (arc600f,mul64_L_r_r__RC) },
+ { ARC600F_INSN_MUL64_CC__RC, SEM_FN_NAME (arc600f,mul64_cc__RC) },
+ { ARC600F_INSN_MUL64_S_GO, SEM_FN_NAME (arc600f,mul64_s_go) },
+ { ARC600F_INSN_MULU64_L_S12_, SEM_FN_NAME (arc600f,mulu64_L_s12_) },
+ { ARC600F_INSN_MULU64_CCU6_, SEM_FN_NAME (arc600f,mulu64_ccu6_) },
+ { ARC600F_INSN_MULU64_L_U6_, SEM_FN_NAME (arc600f,mulu64_L_u6_) },
+ { ARC600F_INSN_MULU64_L_R_R__RC, SEM_FN_NAME (arc600f,mulu64_L_r_r__RC) },
+ { ARC600F_INSN_MULU64_CC__RC, SEM_FN_NAME (arc600f,mulu64_cc__RC) },
+ { ARC600F_INSN_ADDS_L_S12__RA_, SEM_FN_NAME (arc600f,adds_L_s12__RA_) },
+ { ARC600F_INSN_ADDS_CCU6__RA_, SEM_FN_NAME (arc600f,adds_ccu6__RA_) },
+ { ARC600F_INSN_ADDS_L_U6__RA_, SEM_FN_NAME (arc600f,adds_L_u6__RA_) },
+ { ARC600F_INSN_ADDS_L_R_R__RA__RC, SEM_FN_NAME (arc600f,adds_L_r_r__RA__RC) },
+ { ARC600F_INSN_ADDS_CC__RA__RC, SEM_FN_NAME (arc600f,adds_cc__RA__RC) },
+ { ARC600F_INSN_SUBS_L_S12__RA_, SEM_FN_NAME (arc600f,subs_L_s12__RA_) },
+ { ARC600F_INSN_SUBS_CCU6__RA_, SEM_FN_NAME (arc600f,subs_ccu6__RA_) },
+ { ARC600F_INSN_SUBS_L_U6__RA_, SEM_FN_NAME (arc600f,subs_L_u6__RA_) },
+ { ARC600F_INSN_SUBS_L_R_R__RA__RC, SEM_FN_NAME (arc600f,subs_L_r_r__RA__RC) },
+ { ARC600F_INSN_SUBS_CC__RA__RC, SEM_FN_NAME (arc600f,subs_cc__RA__RC) },
+ { ARC600F_INSN_DIVAW_L_S12__RA_, SEM_FN_NAME (arc600f,divaw_L_s12__RA_) },
+ { ARC600F_INSN_DIVAW_CCU6__RA_, SEM_FN_NAME (arc600f,divaw_ccu6__RA_) },
+ { ARC600F_INSN_DIVAW_L_U6__RA_, SEM_FN_NAME (arc600f,divaw_L_u6__RA_) },
+ { ARC600F_INSN_DIVAW_L_R_R__RA__RC, SEM_FN_NAME (arc600f,divaw_L_r_r__RA__RC) },
+ { ARC600F_INSN_DIVAW_CC__RA__RC, SEM_FN_NAME (arc600f,divaw_cc__RA__RC) },
+ { ARC600F_INSN_ASLS_L_S12__RA_, SEM_FN_NAME (arc600f,asls_L_s12__RA_) },
+ { ARC600F_INSN_ASLS_CCU6__RA_, SEM_FN_NAME (arc600f,asls_ccu6__RA_) },
+ { ARC600F_INSN_ASLS_L_U6__RA_, SEM_FN_NAME (arc600f,asls_L_u6__RA_) },
+ { ARC600F_INSN_ASLS_L_R_R__RA__RC, SEM_FN_NAME (arc600f,asls_L_r_r__RA__RC) },
+ { ARC600F_INSN_ASLS_CC__RA__RC, SEM_FN_NAME (arc600f,asls_cc__RA__RC) },
+ { ARC600F_INSN_ASRS_L_S12__RA_, SEM_FN_NAME (arc600f,asrs_L_s12__RA_) },
+ { ARC600F_INSN_ASRS_CCU6__RA_, SEM_FN_NAME (arc600f,asrs_ccu6__RA_) },
+ { ARC600F_INSN_ASRS_L_U6__RA_, SEM_FN_NAME (arc600f,asrs_L_u6__RA_) },
+ { ARC600F_INSN_ASRS_L_R_R__RA__RC, SEM_FN_NAME (arc600f,asrs_L_r_r__RA__RC) },
+ { ARC600F_INSN_ASRS_CC__RA__RC, SEM_FN_NAME (arc600f,asrs_cc__RA__RC) },
+ { ARC600F_INSN_ADDSDW_L_S12__RA_, SEM_FN_NAME (arc600f,addsdw_L_s12__RA_) },
+ { ARC600F_INSN_ADDSDW_CCU6__RA_, SEM_FN_NAME (arc600f,addsdw_ccu6__RA_) },
+ { ARC600F_INSN_ADDSDW_L_U6__RA_, SEM_FN_NAME (arc600f,addsdw_L_u6__RA_) },
+ { ARC600F_INSN_ADDSDW_L_R_R__RA__RC, SEM_FN_NAME (arc600f,addsdw_L_r_r__RA__RC) },
+ { ARC600F_INSN_ADDSDW_CC__RA__RC, SEM_FN_NAME (arc600f,addsdw_cc__RA__RC) },
+ { ARC600F_INSN_SUBSDW_L_S12__RA_, SEM_FN_NAME (arc600f,subsdw_L_s12__RA_) },
+ { ARC600F_INSN_SUBSDW_CCU6__RA_, SEM_FN_NAME (arc600f,subsdw_ccu6__RA_) },
+ { ARC600F_INSN_SUBSDW_L_U6__RA_, SEM_FN_NAME (arc600f,subsdw_L_u6__RA_) },
+ { ARC600F_INSN_SUBSDW_L_R_R__RA__RC, SEM_FN_NAME (arc600f,subsdw_L_r_r__RA__RC) },
+ { ARC600F_INSN_SUBSDW_CC__RA__RC, SEM_FN_NAME (arc600f,subsdw_cc__RA__RC) },
+ { ARC600F_INSN_SWAP_L_R_R__RC, SEM_FN_NAME (arc600f,swap_L_r_r__RC) },
+ { ARC600F_INSN_SWAP_L_U6_, SEM_FN_NAME (arc600f,swap_L_u6_) },
+ { ARC600F_INSN_NORM_L_R_R__RC, SEM_FN_NAME (arc600f,norm_L_r_r__RC) },
+ { ARC600F_INSN_NORM_L_U6_, SEM_FN_NAME (arc600f,norm_L_u6_) },
+ { ARC600F_INSN_RND16_L_R_R__RC, SEM_FN_NAME (arc600f,rnd16_L_r_r__RC) },
+ { ARC600F_INSN_RND16_L_U6_, SEM_FN_NAME (arc600f,rnd16_L_u6_) },
+ { ARC600F_INSN_ABSSW_L_R_R__RC, SEM_FN_NAME (arc600f,abssw_L_r_r__RC) },
+ { ARC600F_INSN_ABSSW_L_U6_, SEM_FN_NAME (arc600f,abssw_L_u6_) },
+ { ARC600F_INSN_ABSS_L_R_R__RC, SEM_FN_NAME (arc600f,abss_L_r_r__RC) },
+ { ARC600F_INSN_ABSS_L_U6_, SEM_FN_NAME (arc600f,abss_L_u6_) },
+ { ARC600F_INSN_NEGSW_L_R_R__RC, SEM_FN_NAME (arc600f,negsw_L_r_r__RC) },
+ { ARC600F_INSN_NEGSW_L_U6_, SEM_FN_NAME (arc600f,negsw_L_u6_) },
+ { ARC600F_INSN_NEGS_L_R_R__RC, SEM_FN_NAME (arc600f,negs_L_r_r__RC) },
+ { ARC600F_INSN_NEGS_L_U6_, SEM_FN_NAME (arc600f,negs_L_u6_) },
+ { ARC600F_INSN_NORMW_L_R_R__RC, SEM_FN_NAME (arc600f,normw_L_r_r__RC) },
+ { ARC600F_INSN_NORMW_L_U6_, SEM_FN_NAME (arc600f,normw_L_u6_) },
+ { ARC600F_INSN_NOP_S, SEM_FN_NAME (arc600f,nop_s) },
+ { ARC600F_INSN_UNIMP_S, SEM_FN_NAME (arc600f,unimp_s) },
+ { ARC600F_INSN_POP_S_B, SEM_FN_NAME (arc600f,pop_s_b) },
+ { ARC600F_INSN_POP_S_BLINK, SEM_FN_NAME (arc600f,pop_s_blink) },
+ { ARC600F_INSN_PUSH_S_B, SEM_FN_NAME (arc600f,push_s_b) },
+ { ARC600F_INSN_PUSH_S_BLINK, SEM_FN_NAME (arc600f,push_s_blink) },
+ { ARC600F_INSN_MULLW_L_S12__RA_, SEM_FN_NAME (arc600f,mullw_L_s12__RA_) },
+ { ARC600F_INSN_MULLW_CCU6__RA_, SEM_FN_NAME (arc600f,mullw_ccu6__RA_) },
+ { ARC600F_INSN_MULLW_L_U6__RA_, SEM_FN_NAME (arc600f,mullw_L_u6__RA_) },
+ { ARC600F_INSN_MULLW_L_R_R__RA__RC, SEM_FN_NAME (arc600f,mullw_L_r_r__RA__RC) },
+ { ARC600F_INSN_MULLW_CC__RA__RC, SEM_FN_NAME (arc600f,mullw_cc__RA__RC) },
+ { ARC600F_INSN_MACLW_L_S12__RA_, SEM_FN_NAME (arc600f,maclw_L_s12__RA_) },
+ { ARC600F_INSN_MACLW_CCU6__RA_, SEM_FN_NAME (arc600f,maclw_ccu6__RA_) },
+ { ARC600F_INSN_MACLW_L_U6__RA_, SEM_FN_NAME (arc600f,maclw_L_u6__RA_) },
+ { ARC600F_INSN_MACLW_L_R_R__RA__RC, SEM_FN_NAME (arc600f,maclw_L_r_r__RA__RC) },
+ { ARC600F_INSN_MACLW_CC__RA__RC, SEM_FN_NAME (arc600f,maclw_cc__RA__RC) },
+ { ARC600F_INSN_MACHLW_L_S12__RA_, SEM_FN_NAME (arc600f,machlw_L_s12__RA_) },
+ { ARC600F_INSN_MACHLW_CCU6__RA_, SEM_FN_NAME (arc600f,machlw_ccu6__RA_) },
+ { ARC600F_INSN_MACHLW_L_U6__RA_, SEM_FN_NAME (arc600f,machlw_L_u6__RA_) },
+ { ARC600F_INSN_MACHLW_L_R_R__RA__RC, SEM_FN_NAME (arc600f,machlw_L_r_r__RA__RC) },
+ { ARC600F_INSN_MACHLW_CC__RA__RC, SEM_FN_NAME (arc600f,machlw_cc__RA__RC) },
+ { ARC600F_INSN_MULULW_L_S12__RA_, SEM_FN_NAME (arc600f,mululw_L_s12__RA_) },
+ { ARC600F_INSN_MULULW_CCU6__RA_, SEM_FN_NAME (arc600f,mululw_ccu6__RA_) },
+ { ARC600F_INSN_MULULW_L_U6__RA_, SEM_FN_NAME (arc600f,mululw_L_u6__RA_) },
+ { ARC600F_INSN_MULULW_L_R_R__RA__RC, SEM_FN_NAME (arc600f,mululw_L_r_r__RA__RC) },
+ { ARC600F_INSN_MULULW_CC__RA__RC, SEM_FN_NAME (arc600f,mululw_cc__RA__RC) },
+ { ARC600F_INSN_MACHULW_L_S12__RA_, SEM_FN_NAME (arc600f,machulw_L_s12__RA_) },
+ { ARC600F_INSN_MACHULW_CCU6__RA_, SEM_FN_NAME (arc600f,machulw_ccu6__RA_) },
+ { ARC600F_INSN_MACHULW_L_U6__RA_, SEM_FN_NAME (arc600f,machulw_L_u6__RA_) },
+ { ARC600F_INSN_MACHULW_L_R_R__RA__RC, SEM_FN_NAME (arc600f,machulw_L_r_r__RA__RC) },
+ { ARC600F_INSN_MACHULW_CC__RA__RC, SEM_FN_NAME (arc600f,machulw_cc__RA__RC) },
+ { ARC600F_INSN_CURRENT_LOOP_END, SEM_FN_NAME (arc600f,current_loop_end) },
+ { ARC600F_INSN_CURRENT_LOOP_END_AFTER_BRANCH, SEM_FN_NAME (arc600f,current_loop_end_after_branch) },
+ { ARC600F_INSN_ARC600_CURRENT_LOOP_END_AFTER_BRANCH, SEM_FN_NAME (arc600f,arc600_current_loop_end_after_branch) },
+ { 0, 0 }
+};
+
+/* Add the semantic fns to IDESC_TABLE. */
+
+void
+SEM_FN_NAME (arc600f,init_idesc_table) (SIM_CPU *current_cpu)
+{
+ IDESC *idesc_table = CPU_IDESC (current_cpu);
+ const struct sem_fn_desc *sf;
+ int mach_num = MACH_NUM (CPU_MACH (current_cpu));
+
+ for (sf = &sem_fns[0]; sf->fn != 0; ++sf)
+ {
+ const CGEN_INSN *insn = idesc_table[sf->index].idata;
+ int valid_p = (CGEN_INSN_VIRTUAL_P (insn)
+ || CGEN_INSN_MACH_HAS_P (insn, mach_num));
+#if FAST_P
+ if (valid_p)
+ idesc_table[sf->index].sem_fast = sf->fn;
+ else
+ idesc_table[sf->index].sem_fast = SEM_FN_NAME (arc600f,x_invalid);
+#else
+ if (valid_p)
+ idesc_table[sf->index].sem_full = sf->fn;
+ else
+ idesc_table[sf->index].sem_full = SEM_FN_NAME (arc600f,x_invalid);
+#endif
+ }
+}
+
diff --git a/sim/arc/sem7-switch.c b/sim/arc/sem7-switch.c
new file mode 100644
index 0000000..0726dc7
--- /dev/null
+++ b/sim/arc/sem7-switch.c
@@ -0,0 +1,33073 @@
+/* Simulator instruction semantics for arc700f.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2007 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#ifdef DEFINE_LABELS
+
+ /* The labels have the case they have because the enum of insn types
+ is all uppercase and in the non-stdc case the insn symbol is built
+ into the enum name. */
+
+ static struct {
+ int index;
+ void *label;
+ } labels[] = {
+ { ARC700F_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
+ { ARC700F_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
+ { ARC700F_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
+ { ARC700F_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
+ { ARC700F_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
+ { ARC700F_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
+ { ARC700F_INSN_B_S, && case_sem_INSN_B_S },
+ { ARC700F_INSN_BCC_S, && case_sem_INSN_BCC_S },
+ { ARC700F_INSN_BRCC_S, && case_sem_INSN_BRCC_S },
+ { ARC700F_INSN_BCC_L, && case_sem_INSN_BCC_L },
+ { ARC700F_INSN_BCC_L_D, && case_sem_INSN_BCC_L_D },
+ { ARC700F_INSN_B_L, && case_sem_INSN_B_L },
+ { ARC700F_INSN_B_L_D, && case_sem_INSN_B_L_D },
+ { ARC700F_INSN_BRCC_RC, && case_sem_INSN_BRCC_RC },
+ { ARC700F_INSN_BRCC_RC_D, && case_sem_INSN_BRCC_RC_D },
+ { ARC700F_INSN_BRCC_U6, && case_sem_INSN_BRCC_U6 },
+ { ARC700F_INSN_BRCC_U6_D, && case_sem_INSN_BRCC_U6_D },
+ { ARC700F_INSN_BL_S, && case_sem_INSN_BL_S },
+ { ARC700F_INSN_BLCC, && case_sem_INSN_BLCC },
+ { ARC700F_INSN_BLCC_D, && case_sem_INSN_BLCC_D },
+ { ARC700F_INSN_BL, && case_sem_INSN_BL },
+ { ARC700F_INSN_BL_D, && case_sem_INSN_BL_D },
+ { ARC700F_INSN_LD_ABS, && case_sem_INSN_LD_ABS },
+ { ARC700F_INSN_LD__AW_ABS, && case_sem_INSN_LD__AW_ABS },
+ { ARC700F_INSN_LD_AB_ABS, && case_sem_INSN_LD_AB_ABS },
+ { ARC700F_INSN_LD_AS_ABS, && case_sem_INSN_LD_AS_ABS },
+ { ARC700F_INSN_LD_ABC, && case_sem_INSN_LD_ABC },
+ { ARC700F_INSN_LD__AW_ABC, && case_sem_INSN_LD__AW_ABC },
+ { ARC700F_INSN_LD_AB_ABC, && case_sem_INSN_LD_AB_ABC },
+ { ARC700F_INSN_LD_AS_ABC, && case_sem_INSN_LD_AS_ABC },
+ { ARC700F_INSN_LD_S_ABC, && case_sem_INSN_LD_S_ABC },
+ { ARC700F_INSN_LD_S_ABU, && case_sem_INSN_LD_S_ABU },
+ { ARC700F_INSN_LD_S_ABSP, && case_sem_INSN_LD_S_ABSP },
+ { ARC700F_INSN_LD_S_GPREL, && case_sem_INSN_LD_S_GPREL },
+ { ARC700F_INSN_LD_S_PCREL, && case_sem_INSN_LD_S_PCREL },
+ { ARC700F_INSN_LDB_ABS, && case_sem_INSN_LDB_ABS },
+ { ARC700F_INSN_LDB__AW_ABS, && case_sem_INSN_LDB__AW_ABS },
+ { ARC700F_INSN_LDB_AB_ABS, && case_sem_INSN_LDB_AB_ABS },
+ { ARC700F_INSN_LDB_AS_ABS, && case_sem_INSN_LDB_AS_ABS },
+ { ARC700F_INSN_LDB_ABC, && case_sem_INSN_LDB_ABC },
+ { ARC700F_INSN_LDB__AW_ABC, && case_sem_INSN_LDB__AW_ABC },
+ { ARC700F_INSN_LDB_AB_ABC, && case_sem_INSN_LDB_AB_ABC },
+ { ARC700F_INSN_LDB_AS_ABC, && case_sem_INSN_LDB_AS_ABC },
+ { ARC700F_INSN_LDB_S_ABC, && case_sem_INSN_LDB_S_ABC },
+ { ARC700F_INSN_LDB_S_ABU, && case_sem_INSN_LDB_S_ABU },
+ { ARC700F_INSN_LDB_S_ABSP, && case_sem_INSN_LDB_S_ABSP },
+ { ARC700F_INSN_LDB_S_GPREL, && case_sem_INSN_LDB_S_GPREL },
+ { ARC700F_INSN_LDB_X_ABS, && case_sem_INSN_LDB_X_ABS },
+ { ARC700F_INSN_LDB__AW_X_ABS, && case_sem_INSN_LDB__AW_X_ABS },
+ { ARC700F_INSN_LDB_AB_X_ABS, && case_sem_INSN_LDB_AB_X_ABS },
+ { ARC700F_INSN_LDB_AS_X_ABS, && case_sem_INSN_LDB_AS_X_ABS },
+ { ARC700F_INSN_LDB_X_ABC, && case_sem_INSN_LDB_X_ABC },
+ { ARC700F_INSN_LDB__AW_X_ABC, && case_sem_INSN_LDB__AW_X_ABC },
+ { ARC700F_INSN_LDB_AB_X_ABC, && case_sem_INSN_LDB_AB_X_ABC },
+ { ARC700F_INSN_LDB_AS_X_ABC, && case_sem_INSN_LDB_AS_X_ABC },
+ { ARC700F_INSN_LDW_ABS, && case_sem_INSN_LDW_ABS },
+ { ARC700F_INSN_LDW__AW_ABS, && case_sem_INSN_LDW__AW_ABS },
+ { ARC700F_INSN_LDW_AB_ABS, && case_sem_INSN_LDW_AB_ABS },
+ { ARC700F_INSN_LDW_AS_ABS, && case_sem_INSN_LDW_AS_ABS },
+ { ARC700F_INSN_LDW_ABC, && case_sem_INSN_LDW_ABC },
+ { ARC700F_INSN_LDW__AW_ABC, && case_sem_INSN_LDW__AW_ABC },
+ { ARC700F_INSN_LDW_AB_ABC, && case_sem_INSN_LDW_AB_ABC },
+ { ARC700F_INSN_LDW_AS_ABC, && case_sem_INSN_LDW_AS_ABC },
+ { ARC700F_INSN_LDW_S_ABC, && case_sem_INSN_LDW_S_ABC },
+ { ARC700F_INSN_LDW_S_ABU, && case_sem_INSN_LDW_S_ABU },
+ { ARC700F_INSN_LDW_S_GPREL, && case_sem_INSN_LDW_S_GPREL },
+ { ARC700F_INSN_LDW_X_ABS, && case_sem_INSN_LDW_X_ABS },
+ { ARC700F_INSN_LDW__AW_X_ABS, && case_sem_INSN_LDW__AW_X_ABS },
+ { ARC700F_INSN_LDW_AB_X_ABS, && case_sem_INSN_LDW_AB_X_ABS },
+ { ARC700F_INSN_LDW_AS_X_ABS, && case_sem_INSN_LDW_AS_X_ABS },
+ { ARC700F_INSN_LDW_X_ABC, && case_sem_INSN_LDW_X_ABC },
+ { ARC700F_INSN_LDW__AW_X_ABC, && case_sem_INSN_LDW__AW_X_ABC },
+ { ARC700F_INSN_LDW_AB_X_ABC, && case_sem_INSN_LDW_AB_X_ABC },
+ { ARC700F_INSN_LDW_AS_X_ABC, && case_sem_INSN_LDW_AS_X_ABC },
+ { ARC700F_INSN_LDW_S_X_ABU, && case_sem_INSN_LDW_S_X_ABU },
+ { ARC700F_INSN_ST_ABS, && case_sem_INSN_ST_ABS },
+ { ARC700F_INSN_ST__AW_ABS, && case_sem_INSN_ST__AW_ABS },
+ { ARC700F_INSN_ST_AB_ABS, && case_sem_INSN_ST_AB_ABS },
+ { ARC700F_INSN_ST_AS_ABS, && case_sem_INSN_ST_AS_ABS },
+ { ARC700F_INSN_ST_S_ABU, && case_sem_INSN_ST_S_ABU },
+ { ARC700F_INSN_ST_S_ABSP, && case_sem_INSN_ST_S_ABSP },
+ { ARC700F_INSN_STB_ABS, && case_sem_INSN_STB_ABS },
+ { ARC700F_INSN_STB__AW_ABS, && case_sem_INSN_STB__AW_ABS },
+ { ARC700F_INSN_STB_AB_ABS, && case_sem_INSN_STB_AB_ABS },
+ { ARC700F_INSN_STB_AS_ABS, && case_sem_INSN_STB_AS_ABS },
+ { ARC700F_INSN_STB_S_ABU, && case_sem_INSN_STB_S_ABU },
+ { ARC700F_INSN_STB_S_ABSP, && case_sem_INSN_STB_S_ABSP },
+ { ARC700F_INSN_STW_ABS, && case_sem_INSN_STW_ABS },
+ { ARC700F_INSN_STW__AW_ABS, && case_sem_INSN_STW__AW_ABS },
+ { ARC700F_INSN_STW_AB_ABS, && case_sem_INSN_STW_AB_ABS },
+ { ARC700F_INSN_STW_AS_ABS, && case_sem_INSN_STW_AS_ABS },
+ { ARC700F_INSN_STW_S_ABU, && case_sem_INSN_STW_S_ABU },
+ { ARC700F_INSN_ADD_L_S12__RA_, && case_sem_INSN_ADD_L_S12__RA_ },
+ { ARC700F_INSN_ADD_CCU6__RA_, && case_sem_INSN_ADD_CCU6__RA_ },
+ { ARC700F_INSN_ADD_L_U6__RA_, && case_sem_INSN_ADD_L_U6__RA_ },
+ { ARC700F_INSN_ADD_L_R_R__RA__RC, && case_sem_INSN_ADD_L_R_R__RA__RC },
+ { ARC700F_INSN_ADD_CC__RA__RC, && case_sem_INSN_ADD_CC__RA__RC },
+ { ARC700F_INSN_ADD_S_ABC, && case_sem_INSN_ADD_S_ABC },
+ { ARC700F_INSN_ADD_S_CBU3, && case_sem_INSN_ADD_S_CBU3 },
+ { ARC700F_INSN_ADD_S_MCAH, && case_sem_INSN_ADD_S_MCAH },
+ { ARC700F_INSN_ADD_S_ABSP, && case_sem_INSN_ADD_S_ABSP },
+ { ARC700F_INSN_ADD_S_ASSPSP, && case_sem_INSN_ADD_S_ASSPSP },
+ { ARC700F_INSN_ADD_S_GP, && case_sem_INSN_ADD_S_GP },
+ { ARC700F_INSN_ADD_S_R_U7, && case_sem_INSN_ADD_S_R_U7 },
+ { ARC700F_INSN_ADC_L_S12__RA_, && case_sem_INSN_ADC_L_S12__RA_ },
+ { ARC700F_INSN_ADC_CCU6__RA_, && case_sem_INSN_ADC_CCU6__RA_ },
+ { ARC700F_INSN_ADC_L_U6__RA_, && case_sem_INSN_ADC_L_U6__RA_ },
+ { ARC700F_INSN_ADC_L_R_R__RA__RC, && case_sem_INSN_ADC_L_R_R__RA__RC },
+ { ARC700F_INSN_ADC_CC__RA__RC, && case_sem_INSN_ADC_CC__RA__RC },
+ { ARC700F_INSN_SUB_L_S12__RA_, && case_sem_INSN_SUB_L_S12__RA_ },
+ { ARC700F_INSN_SUB_CCU6__RA_, && case_sem_INSN_SUB_CCU6__RA_ },
+ { ARC700F_INSN_SUB_L_U6__RA_, && case_sem_INSN_SUB_L_U6__RA_ },
+ { ARC700F_INSN_SUB_L_R_R__RA__RC, && case_sem_INSN_SUB_L_R_R__RA__RC },
+ { ARC700F_INSN_SUB_CC__RA__RC, && case_sem_INSN_SUB_CC__RA__RC },
+ { ARC700F_INSN_SUB_S_CBU3, && case_sem_INSN_SUB_S_CBU3 },
+ { ARC700F_INSN_I16_GO_SUB_S_GO, && case_sem_INSN_I16_GO_SUB_S_GO },
+ { ARC700F_INSN_SUB_S_GO_SUB_NE, && case_sem_INSN_SUB_S_GO_SUB_NE },
+ { ARC700F_INSN_SUB_S_SSB, && case_sem_INSN_SUB_S_SSB },
+ { ARC700F_INSN_SUB_S_ASSPSP, && case_sem_INSN_SUB_S_ASSPSP },
+ { ARC700F_INSN_SBC_L_S12__RA_, && case_sem_INSN_SBC_L_S12__RA_ },
+ { ARC700F_INSN_SBC_CCU6__RA_, && case_sem_INSN_SBC_CCU6__RA_ },
+ { ARC700F_INSN_SBC_L_U6__RA_, && case_sem_INSN_SBC_L_U6__RA_ },
+ { ARC700F_INSN_SBC_L_R_R__RA__RC, && case_sem_INSN_SBC_L_R_R__RA__RC },
+ { ARC700F_INSN_SBC_CC__RA__RC, && case_sem_INSN_SBC_CC__RA__RC },
+ { ARC700F_INSN_AND_L_S12__RA_, && case_sem_INSN_AND_L_S12__RA_ },
+ { ARC700F_INSN_AND_CCU6__RA_, && case_sem_INSN_AND_CCU6__RA_ },
+ { ARC700F_INSN_AND_L_U6__RA_, && case_sem_INSN_AND_L_U6__RA_ },
+ { ARC700F_INSN_AND_L_R_R__RA__RC, && case_sem_INSN_AND_L_R_R__RA__RC },
+ { ARC700F_INSN_AND_CC__RA__RC, && case_sem_INSN_AND_CC__RA__RC },
+ { ARC700F_INSN_I16_GO_AND_S_GO, && case_sem_INSN_I16_GO_AND_S_GO },
+ { ARC700F_INSN_OR_L_S12__RA_, && case_sem_INSN_OR_L_S12__RA_ },
+ { ARC700F_INSN_OR_CCU6__RA_, && case_sem_INSN_OR_CCU6__RA_ },
+ { ARC700F_INSN_OR_L_U6__RA_, && case_sem_INSN_OR_L_U6__RA_ },
+ { ARC700F_INSN_OR_L_R_R__RA__RC, && case_sem_INSN_OR_L_R_R__RA__RC },
+ { ARC700F_INSN_OR_CC__RA__RC, && case_sem_INSN_OR_CC__RA__RC },
+ { ARC700F_INSN_I16_GO_OR_S_GO, && case_sem_INSN_I16_GO_OR_S_GO },
+ { ARC700F_INSN_BIC_L_S12__RA_, && case_sem_INSN_BIC_L_S12__RA_ },
+ { ARC700F_INSN_BIC_CCU6__RA_, && case_sem_INSN_BIC_CCU6__RA_ },
+ { ARC700F_INSN_BIC_L_U6__RA_, && case_sem_INSN_BIC_L_U6__RA_ },
+ { ARC700F_INSN_BIC_L_R_R__RA__RC, && case_sem_INSN_BIC_L_R_R__RA__RC },
+ { ARC700F_INSN_BIC_CC__RA__RC, && case_sem_INSN_BIC_CC__RA__RC },
+ { ARC700F_INSN_I16_GO_BIC_S_GO, && case_sem_INSN_I16_GO_BIC_S_GO },
+ { ARC700F_INSN_XOR_L_S12__RA_, && case_sem_INSN_XOR_L_S12__RA_ },
+ { ARC700F_INSN_XOR_CCU6__RA_, && case_sem_INSN_XOR_CCU6__RA_ },
+ { ARC700F_INSN_XOR_L_U6__RA_, && case_sem_INSN_XOR_L_U6__RA_ },
+ { ARC700F_INSN_XOR_L_R_R__RA__RC, && case_sem_INSN_XOR_L_R_R__RA__RC },
+ { ARC700F_INSN_XOR_CC__RA__RC, && case_sem_INSN_XOR_CC__RA__RC },
+ { ARC700F_INSN_I16_GO_XOR_S_GO, && case_sem_INSN_I16_GO_XOR_S_GO },
+ { ARC700F_INSN_MAX_L_S12__RA_, && case_sem_INSN_MAX_L_S12__RA_ },
+ { ARC700F_INSN_MAX_CCU6__RA_, && case_sem_INSN_MAX_CCU6__RA_ },
+ { ARC700F_INSN_MAX_L_U6__RA_, && case_sem_INSN_MAX_L_U6__RA_ },
+ { ARC700F_INSN_MAX_L_R_R__RA__RC, && case_sem_INSN_MAX_L_R_R__RA__RC },
+ { ARC700F_INSN_MAX_CC__RA__RC, && case_sem_INSN_MAX_CC__RA__RC },
+ { ARC700F_INSN_MIN_L_S12__RA_, && case_sem_INSN_MIN_L_S12__RA_ },
+ { ARC700F_INSN_MIN_CCU6__RA_, && case_sem_INSN_MIN_CCU6__RA_ },
+ { ARC700F_INSN_MIN_L_U6__RA_, && case_sem_INSN_MIN_L_U6__RA_ },
+ { ARC700F_INSN_MIN_L_R_R__RA__RC, && case_sem_INSN_MIN_L_R_R__RA__RC },
+ { ARC700F_INSN_MIN_CC__RA__RC, && case_sem_INSN_MIN_CC__RA__RC },
+ { ARC700F_INSN_MOV_L_S12_, && case_sem_INSN_MOV_L_S12_ },
+ { ARC700F_INSN_MOV_CCU6_, && case_sem_INSN_MOV_CCU6_ },
+ { ARC700F_INSN_MOV_L_U6_, && case_sem_INSN_MOV_L_U6_ },
+ { ARC700F_INSN_MOV_L_R_R__RC, && case_sem_INSN_MOV_L_R_R__RC },
+ { ARC700F_INSN_MOV_CC__RC, && case_sem_INSN_MOV_CC__RC },
+ { ARC700F_INSN_MOV_S_MCAH, && case_sem_INSN_MOV_S_MCAH },
+ { ARC700F_INSN_MOV_S_MCAHB, && case_sem_INSN_MOV_S_MCAHB },
+ { ARC700F_INSN_MOV_S_R_U7, && case_sem_INSN_MOV_S_R_U7 },
+ { ARC700F_INSN_TST_L_S12_, && case_sem_INSN_TST_L_S12_ },
+ { ARC700F_INSN_TST_CCU6_, && case_sem_INSN_TST_CCU6_ },
+ { ARC700F_INSN_TST_L_U6_, && case_sem_INSN_TST_L_U6_ },
+ { ARC700F_INSN_TST_L_R_R__RC, && case_sem_INSN_TST_L_R_R__RC },
+ { ARC700F_INSN_TST_CC__RC, && case_sem_INSN_TST_CC__RC },
+ { ARC700F_INSN_TST_S_GO, && case_sem_INSN_TST_S_GO },
+ { ARC700F_INSN_CMP_L_S12_, && case_sem_INSN_CMP_L_S12_ },
+ { ARC700F_INSN_CMP_CCU6_, && case_sem_INSN_CMP_CCU6_ },
+ { ARC700F_INSN_CMP_L_U6_, && case_sem_INSN_CMP_L_U6_ },
+ { ARC700F_INSN_CMP_L_R_R__RC, && case_sem_INSN_CMP_L_R_R__RC },
+ { ARC700F_INSN_CMP_CC__RC, && case_sem_INSN_CMP_CC__RC },
+ { ARC700F_INSN_CMP_S_MCAH, && case_sem_INSN_CMP_S_MCAH },
+ { ARC700F_INSN_CMP_S_R_U7, && case_sem_INSN_CMP_S_R_U7 },
+ { ARC700F_INSN_RCMP_L_S12_, && case_sem_INSN_RCMP_L_S12_ },
+ { ARC700F_INSN_RCMP_CCU6_, && case_sem_INSN_RCMP_CCU6_ },
+ { ARC700F_INSN_RCMP_L_U6_, && case_sem_INSN_RCMP_L_U6_ },
+ { ARC700F_INSN_RCMP_L_R_R__RC, && case_sem_INSN_RCMP_L_R_R__RC },
+ { ARC700F_INSN_RCMP_CC__RC, && case_sem_INSN_RCMP_CC__RC },
+ { ARC700F_INSN_RSUB_L_S12__RA_, && case_sem_INSN_RSUB_L_S12__RA_ },
+ { ARC700F_INSN_RSUB_CCU6__RA_, && case_sem_INSN_RSUB_CCU6__RA_ },
+ { ARC700F_INSN_RSUB_L_U6__RA_, && case_sem_INSN_RSUB_L_U6__RA_ },
+ { ARC700F_INSN_RSUB_L_R_R__RA__RC, && case_sem_INSN_RSUB_L_R_R__RA__RC },
+ { ARC700F_INSN_RSUB_CC__RA__RC, && case_sem_INSN_RSUB_CC__RA__RC },
+ { ARC700F_INSN_BSET_L_S12__RA_, && case_sem_INSN_BSET_L_S12__RA_ },
+ { ARC700F_INSN_BSET_CCU6__RA_, && case_sem_INSN_BSET_CCU6__RA_ },
+ { ARC700F_INSN_BSET_L_U6__RA_, && case_sem_INSN_BSET_L_U6__RA_ },
+ { ARC700F_INSN_BSET_L_R_R__RA__RC, && case_sem_INSN_BSET_L_R_R__RA__RC },
+ { ARC700F_INSN_BSET_CC__RA__RC, && case_sem_INSN_BSET_CC__RA__RC },
+ { ARC700F_INSN_BSET_S_SSB, && case_sem_INSN_BSET_S_SSB },
+ { ARC700F_INSN_BCLR_L_S12__RA_, && case_sem_INSN_BCLR_L_S12__RA_ },
+ { ARC700F_INSN_BCLR_CCU6__RA_, && case_sem_INSN_BCLR_CCU6__RA_ },
+ { ARC700F_INSN_BCLR_L_U6__RA_, && case_sem_INSN_BCLR_L_U6__RA_ },
+ { ARC700F_INSN_BCLR_L_R_R__RA__RC, && case_sem_INSN_BCLR_L_R_R__RA__RC },
+ { ARC700F_INSN_BCLR_CC__RA__RC, && case_sem_INSN_BCLR_CC__RA__RC },
+ { ARC700F_INSN_BCLR_S_SSB, && case_sem_INSN_BCLR_S_SSB },
+ { ARC700F_INSN_BTST_L_S12_, && case_sem_INSN_BTST_L_S12_ },
+ { ARC700F_INSN_BTST_CCU6_, && case_sem_INSN_BTST_CCU6_ },
+ { ARC700F_INSN_BTST_L_U6_, && case_sem_INSN_BTST_L_U6_ },
+ { ARC700F_INSN_BTST_L_R_R__RC, && case_sem_INSN_BTST_L_R_R__RC },
+ { ARC700F_INSN_BTST_CC__RC, && case_sem_INSN_BTST_CC__RC },
+ { ARC700F_INSN_BTST_S_SSB, && case_sem_INSN_BTST_S_SSB },
+ { ARC700F_INSN_BXOR_L_S12__RA_, && case_sem_INSN_BXOR_L_S12__RA_ },
+ { ARC700F_INSN_BXOR_CCU6__RA_, && case_sem_INSN_BXOR_CCU6__RA_ },
+ { ARC700F_INSN_BXOR_L_U6__RA_, && case_sem_INSN_BXOR_L_U6__RA_ },
+ { ARC700F_INSN_BXOR_L_R_R__RA__RC, && case_sem_INSN_BXOR_L_R_R__RA__RC },
+ { ARC700F_INSN_BXOR_CC__RA__RC, && case_sem_INSN_BXOR_CC__RA__RC },
+ { ARC700F_INSN_BMSK_L_S12__RA_, && case_sem_INSN_BMSK_L_S12__RA_ },
+ { ARC700F_INSN_BMSK_CCU6__RA_, && case_sem_INSN_BMSK_CCU6__RA_ },
+ { ARC700F_INSN_BMSK_L_U6__RA_, && case_sem_INSN_BMSK_L_U6__RA_ },
+ { ARC700F_INSN_BMSK_L_R_R__RA__RC, && case_sem_INSN_BMSK_L_R_R__RA__RC },
+ { ARC700F_INSN_BMSK_CC__RA__RC, && case_sem_INSN_BMSK_CC__RA__RC },
+ { ARC700F_INSN_BMSK_S_SSB, && case_sem_INSN_BMSK_S_SSB },
+ { ARC700F_INSN_ADD1_L_S12__RA_, && case_sem_INSN_ADD1_L_S12__RA_ },
+ { ARC700F_INSN_ADD1_CCU6__RA_, && case_sem_INSN_ADD1_CCU6__RA_ },
+ { ARC700F_INSN_ADD1_L_U6__RA_, && case_sem_INSN_ADD1_L_U6__RA_ },
+ { ARC700F_INSN_ADD1_L_R_R__RA__RC, && case_sem_INSN_ADD1_L_R_R__RA__RC },
+ { ARC700F_INSN_ADD1_CC__RA__RC, && case_sem_INSN_ADD1_CC__RA__RC },
+ { ARC700F_INSN_I16_GO_ADD1_S_GO, && case_sem_INSN_I16_GO_ADD1_S_GO },
+ { ARC700F_INSN_ADD2_L_S12__RA_, && case_sem_INSN_ADD2_L_S12__RA_ },
+ { ARC700F_INSN_ADD2_CCU6__RA_, && case_sem_INSN_ADD2_CCU6__RA_ },
+ { ARC700F_INSN_ADD2_L_U6__RA_, && case_sem_INSN_ADD2_L_U6__RA_ },
+ { ARC700F_INSN_ADD2_L_R_R__RA__RC, && case_sem_INSN_ADD2_L_R_R__RA__RC },
+ { ARC700F_INSN_ADD2_CC__RA__RC, && case_sem_INSN_ADD2_CC__RA__RC },
+ { ARC700F_INSN_I16_GO_ADD2_S_GO, && case_sem_INSN_I16_GO_ADD2_S_GO },
+ { ARC700F_INSN_ADD3_L_S12__RA_, && case_sem_INSN_ADD3_L_S12__RA_ },
+ { ARC700F_INSN_ADD3_CCU6__RA_, && case_sem_INSN_ADD3_CCU6__RA_ },
+ { ARC700F_INSN_ADD3_L_U6__RA_, && case_sem_INSN_ADD3_L_U6__RA_ },
+ { ARC700F_INSN_ADD3_L_R_R__RA__RC, && case_sem_INSN_ADD3_L_R_R__RA__RC },
+ { ARC700F_INSN_ADD3_CC__RA__RC, && case_sem_INSN_ADD3_CC__RA__RC },
+ { ARC700F_INSN_I16_GO_ADD3_S_GO, && case_sem_INSN_I16_GO_ADD3_S_GO },
+ { ARC700F_INSN_SUB1_L_S12__RA_, && case_sem_INSN_SUB1_L_S12__RA_ },
+ { ARC700F_INSN_SUB1_CCU6__RA_, && case_sem_INSN_SUB1_CCU6__RA_ },
+ { ARC700F_INSN_SUB1_L_U6__RA_, && case_sem_INSN_SUB1_L_U6__RA_ },
+ { ARC700F_INSN_SUB1_L_R_R__RA__RC, && case_sem_INSN_SUB1_L_R_R__RA__RC },
+ { ARC700F_INSN_SUB1_CC__RA__RC, && case_sem_INSN_SUB1_CC__RA__RC },
+ { ARC700F_INSN_SUB2_L_S12__RA_, && case_sem_INSN_SUB2_L_S12__RA_ },
+ { ARC700F_INSN_SUB2_CCU6__RA_, && case_sem_INSN_SUB2_CCU6__RA_ },
+ { ARC700F_INSN_SUB2_L_U6__RA_, && case_sem_INSN_SUB2_L_U6__RA_ },
+ { ARC700F_INSN_SUB2_L_R_R__RA__RC, && case_sem_INSN_SUB2_L_R_R__RA__RC },
+ { ARC700F_INSN_SUB2_CC__RA__RC, && case_sem_INSN_SUB2_CC__RA__RC },
+ { ARC700F_INSN_SUB3_L_S12__RA_, && case_sem_INSN_SUB3_L_S12__RA_ },
+ { ARC700F_INSN_SUB3_CCU6__RA_, && case_sem_INSN_SUB3_CCU6__RA_ },
+ { ARC700F_INSN_SUB3_L_U6__RA_, && case_sem_INSN_SUB3_L_U6__RA_ },
+ { ARC700F_INSN_SUB3_L_R_R__RA__RC, && case_sem_INSN_SUB3_L_R_R__RA__RC },
+ { ARC700F_INSN_SUB3_CC__RA__RC, && case_sem_INSN_SUB3_CC__RA__RC },
+ { ARC700F_INSN_MPY_L_S12__RA_, && case_sem_INSN_MPY_L_S12__RA_ },
+ { ARC700F_INSN_MPY_CCU6__RA_, && case_sem_INSN_MPY_CCU6__RA_ },
+ { ARC700F_INSN_MPY_L_U6__RA_, && case_sem_INSN_MPY_L_U6__RA_ },
+ { ARC700F_INSN_MPY_L_R_R__RA__RC, && case_sem_INSN_MPY_L_R_R__RA__RC },
+ { ARC700F_INSN_MPY_CC__RA__RC, && case_sem_INSN_MPY_CC__RA__RC },
+ { ARC700F_INSN_MPYH_L_S12__RA_, && case_sem_INSN_MPYH_L_S12__RA_ },
+ { ARC700F_INSN_MPYH_CCU6__RA_, && case_sem_INSN_MPYH_CCU6__RA_ },
+ { ARC700F_INSN_MPYH_L_U6__RA_, && case_sem_INSN_MPYH_L_U6__RA_ },
+ { ARC700F_INSN_MPYH_L_R_R__RA__RC, && case_sem_INSN_MPYH_L_R_R__RA__RC },
+ { ARC700F_INSN_MPYH_CC__RA__RC, && case_sem_INSN_MPYH_CC__RA__RC },
+ { ARC700F_INSN_MPYHU_L_S12__RA_, && case_sem_INSN_MPYHU_L_S12__RA_ },
+ { ARC700F_INSN_MPYHU_CCU6__RA_, && case_sem_INSN_MPYHU_CCU6__RA_ },
+ { ARC700F_INSN_MPYHU_L_U6__RA_, && case_sem_INSN_MPYHU_L_U6__RA_ },
+ { ARC700F_INSN_MPYHU_L_R_R__RA__RC, && case_sem_INSN_MPYHU_L_R_R__RA__RC },
+ { ARC700F_INSN_MPYHU_CC__RA__RC, && case_sem_INSN_MPYHU_CC__RA__RC },
+ { ARC700F_INSN_MPYU_L_S12__RA_, && case_sem_INSN_MPYU_L_S12__RA_ },
+ { ARC700F_INSN_MPYU_CCU6__RA_, && case_sem_INSN_MPYU_CCU6__RA_ },
+ { ARC700F_INSN_MPYU_L_U6__RA_, && case_sem_INSN_MPYU_L_U6__RA_ },
+ { ARC700F_INSN_MPYU_L_R_R__RA__RC, && case_sem_INSN_MPYU_L_R_R__RA__RC },
+ { ARC700F_INSN_MPYU_CC__RA__RC, && case_sem_INSN_MPYU_CC__RA__RC },
+ { ARC700F_INSN_J_L_R_R___RC_NOILINK_, && case_sem_INSN_J_L_R_R___RC_NOILINK_ },
+ { ARC700F_INSN_J_CC___RC_NOILINK_, && case_sem_INSN_J_CC___RC_NOILINK_ },
+ { ARC700F_INSN_J_L_R_R___RC_ILINK_, && case_sem_INSN_J_L_R_R___RC_ILINK_ },
+ { ARC700F_INSN_J_CC___RC_ILINK_, && case_sem_INSN_J_CC___RC_ILINK_ },
+ { ARC700F_INSN_J_L_S12_, && case_sem_INSN_J_L_S12_ },
+ { ARC700F_INSN_J_CCU6_, && case_sem_INSN_J_CCU6_ },
+ { ARC700F_INSN_J_L_U6_, && case_sem_INSN_J_L_U6_ },
+ { ARC700F_INSN_J_S, && case_sem_INSN_J_S },
+ { ARC700F_INSN_J_S__S, && case_sem_INSN_J_S__S },
+ { ARC700F_INSN_J_SEQ__S, && case_sem_INSN_J_SEQ__S },
+ { ARC700F_INSN_J_SNE__S, && case_sem_INSN_J_SNE__S },
+ { ARC700F_INSN_J_L_S12_D_, && case_sem_INSN_J_L_S12_D_ },
+ { ARC700F_INSN_J_CCU6_D_, && case_sem_INSN_J_CCU6_D_ },
+ { ARC700F_INSN_J_L_U6_D_, && case_sem_INSN_J_L_U6_D_ },
+ { ARC700F_INSN_J_L_R_R_D___RC_, && case_sem_INSN_J_L_R_R_D___RC_ },
+ { ARC700F_INSN_J_CC_D___RC_, && case_sem_INSN_J_CC_D___RC_ },
+ { ARC700F_INSN_J_S_D, && case_sem_INSN_J_S_D },
+ { ARC700F_INSN_J_S__S_D, && case_sem_INSN_J_S__S_D },
+ { ARC700F_INSN_JL_L_S12_, && case_sem_INSN_JL_L_S12_ },
+ { ARC700F_INSN_JL_CCU6_, && case_sem_INSN_JL_CCU6_ },
+ { ARC700F_INSN_JL_L_U6_, && case_sem_INSN_JL_L_U6_ },
+ { ARC700F_INSN_JL_S, && case_sem_INSN_JL_S },
+ { ARC700F_INSN_JL_L_R_R___RC_NOILINK_, && case_sem_INSN_JL_L_R_R___RC_NOILINK_ },
+ { ARC700F_INSN_JL_CC___RC_NOILINK_, && case_sem_INSN_JL_CC___RC_NOILINK_ },
+ { ARC700F_INSN_JL_L_S12_D_, && case_sem_INSN_JL_L_S12_D_ },
+ { ARC700F_INSN_JL_CCU6_D_, && case_sem_INSN_JL_CCU6_D_ },
+ { ARC700F_INSN_JL_L_U6_D_, && case_sem_INSN_JL_L_U6_D_ },
+ { ARC700F_INSN_JL_L_R_R_D___RC_, && case_sem_INSN_JL_L_R_R_D___RC_ },
+ { ARC700F_INSN_JL_CC_D___RC_, && case_sem_INSN_JL_CC_D___RC_ },
+ { ARC700F_INSN_JL_S_D, && case_sem_INSN_JL_S_D },
+ { ARC700F_INSN_LP_L_S12_, && case_sem_INSN_LP_L_S12_ },
+ { ARC700F_INSN_LPCC_CCU6, && case_sem_INSN_LPCC_CCU6 },
+ { ARC700F_INSN_FLAG_L_S12_, && case_sem_INSN_FLAG_L_S12_ },
+ { ARC700F_INSN_FLAG_CCU6_, && case_sem_INSN_FLAG_CCU6_ },
+ { ARC700F_INSN_FLAG_L_U6_, && case_sem_INSN_FLAG_L_U6_ },
+ { ARC700F_INSN_FLAG_L_R_R__RC, && case_sem_INSN_FLAG_L_R_R__RC },
+ { ARC700F_INSN_FLAG_CC__RC, && case_sem_INSN_FLAG_CC__RC },
+ { ARC700F_INSN_LR_L_R_R___RC_, && case_sem_INSN_LR_L_R_R___RC_ },
+ { ARC700F_INSN_LR_L_S12_, && case_sem_INSN_LR_L_S12_ },
+ { ARC700F_INSN_LR_L_U6_, && case_sem_INSN_LR_L_U6_ },
+ { ARC700F_INSN_SR_L_R_R___RC_, && case_sem_INSN_SR_L_R_R___RC_ },
+ { ARC700F_INSN_SR_L_S12_, && case_sem_INSN_SR_L_S12_ },
+ { ARC700F_INSN_SR_L_U6_, && case_sem_INSN_SR_L_U6_ },
+ { ARC700F_INSN_ASL_L_R_R__RC, && case_sem_INSN_ASL_L_R_R__RC },
+ { ARC700F_INSN_ASL_L_U6_, && case_sem_INSN_ASL_L_U6_ },
+ { ARC700F_INSN_I16_GO_ASL_S_GO, && case_sem_INSN_I16_GO_ASL_S_GO },
+ { ARC700F_INSN_ASR_L_R_R__RC, && case_sem_INSN_ASR_L_R_R__RC },
+ { ARC700F_INSN_ASR_L_U6_, && case_sem_INSN_ASR_L_U6_ },
+ { ARC700F_INSN_I16_GO_ASR_S_GO, && case_sem_INSN_I16_GO_ASR_S_GO },
+ { ARC700F_INSN_LSR_L_R_R__RC, && case_sem_INSN_LSR_L_R_R__RC },
+ { ARC700F_INSN_LSR_L_U6_, && case_sem_INSN_LSR_L_U6_ },
+ { ARC700F_INSN_I16_GO_LSR_S_GO, && case_sem_INSN_I16_GO_LSR_S_GO },
+ { ARC700F_INSN_ROR_L_R_R__RC, && case_sem_INSN_ROR_L_R_R__RC },
+ { ARC700F_INSN_ROR_L_U6_, && case_sem_INSN_ROR_L_U6_ },
+ { ARC700F_INSN_RRC_L_R_R__RC, && case_sem_INSN_RRC_L_R_R__RC },
+ { ARC700F_INSN_RRC_L_U6_, && case_sem_INSN_RRC_L_U6_ },
+ { ARC700F_INSN_SEXB_L_R_R__RC, && case_sem_INSN_SEXB_L_R_R__RC },
+ { ARC700F_INSN_SEXB_L_U6_, && case_sem_INSN_SEXB_L_U6_ },
+ { ARC700F_INSN_I16_GO_SEXB_S_GO, && case_sem_INSN_I16_GO_SEXB_S_GO },
+ { ARC700F_INSN_SEXW_L_R_R__RC, && case_sem_INSN_SEXW_L_R_R__RC },
+ { ARC700F_INSN_SEXW_L_U6_, && case_sem_INSN_SEXW_L_U6_ },
+ { ARC700F_INSN_I16_GO_SEXW_S_GO, && case_sem_INSN_I16_GO_SEXW_S_GO },
+ { ARC700F_INSN_EXTB_L_R_R__RC, && case_sem_INSN_EXTB_L_R_R__RC },
+ { ARC700F_INSN_EXTB_L_U6_, && case_sem_INSN_EXTB_L_U6_ },
+ { ARC700F_INSN_I16_GO_EXTB_S_GO, && case_sem_INSN_I16_GO_EXTB_S_GO },
+ { ARC700F_INSN_EXTW_L_R_R__RC, && case_sem_INSN_EXTW_L_R_R__RC },
+ { ARC700F_INSN_EXTW_L_U6_, && case_sem_INSN_EXTW_L_U6_ },
+ { ARC700F_INSN_I16_GO_EXTW_S_GO, && case_sem_INSN_I16_GO_EXTW_S_GO },
+ { ARC700F_INSN_ABS_L_R_R__RC, && case_sem_INSN_ABS_L_R_R__RC },
+ { ARC700F_INSN_ABS_L_U6_, && case_sem_INSN_ABS_L_U6_ },
+ { ARC700F_INSN_I16_GO_ABS_S_GO, && case_sem_INSN_I16_GO_ABS_S_GO },
+ { ARC700F_INSN_NOT_L_R_R__RC, && case_sem_INSN_NOT_L_R_R__RC },
+ { ARC700F_INSN_NOT_L_U6_, && case_sem_INSN_NOT_L_U6_ },
+ { ARC700F_INSN_I16_GO_NOT_S_GO, && case_sem_INSN_I16_GO_NOT_S_GO },
+ { ARC700F_INSN_RLC_L_R_R__RC, && case_sem_INSN_RLC_L_R_R__RC },
+ { ARC700F_INSN_RLC_L_U6_, && case_sem_INSN_RLC_L_U6_ },
+ { ARC700F_INSN_EX_L_R_R__RC, && case_sem_INSN_EX_L_R_R__RC },
+ { ARC700F_INSN_EX_L_U6_, && case_sem_INSN_EX_L_U6_ },
+ { ARC700F_INSN_I16_GO_NEG_S_GO, && case_sem_INSN_I16_GO_NEG_S_GO },
+ { ARC700F_INSN_SWI, && case_sem_INSN_SWI },
+ { ARC700F_INSN_TRAP_S, && case_sem_INSN_TRAP_S },
+ { ARC700F_INSN_BRK, && case_sem_INSN_BRK },
+ { ARC700F_INSN_BRK_S, && case_sem_INSN_BRK_S },
+ { ARC700F_INSN_ASL_L_S12__RA_, && case_sem_INSN_ASL_L_S12__RA_ },
+ { ARC700F_INSN_ASL_CCU6__RA_, && case_sem_INSN_ASL_CCU6__RA_ },
+ { ARC700F_INSN_ASL_L_U6__RA_, && case_sem_INSN_ASL_L_U6__RA_ },
+ { ARC700F_INSN_ASL_L_R_R__RA__RC, && case_sem_INSN_ASL_L_R_R__RA__RC },
+ { ARC700F_INSN_ASL_CC__RA__RC, && case_sem_INSN_ASL_CC__RA__RC },
+ { ARC700F_INSN_ASL_S_CBU3, && case_sem_INSN_ASL_S_CBU3 },
+ { ARC700F_INSN_ASL_S_SSB, && case_sem_INSN_ASL_S_SSB },
+ { ARC700F_INSN_I16_GO_ASLM_S_GO, && case_sem_INSN_I16_GO_ASLM_S_GO },
+ { ARC700F_INSN_LSR_L_S12__RA_, && case_sem_INSN_LSR_L_S12__RA_ },
+ { ARC700F_INSN_LSR_CCU6__RA_, && case_sem_INSN_LSR_CCU6__RA_ },
+ { ARC700F_INSN_LSR_L_U6__RA_, && case_sem_INSN_LSR_L_U6__RA_ },
+ { ARC700F_INSN_LSR_L_R_R__RA__RC, && case_sem_INSN_LSR_L_R_R__RA__RC },
+ { ARC700F_INSN_LSR_CC__RA__RC, && case_sem_INSN_LSR_CC__RA__RC },
+ { ARC700F_INSN_LSR_S_SSB, && case_sem_INSN_LSR_S_SSB },
+ { ARC700F_INSN_I16_GO_LSRM_S_GO, && case_sem_INSN_I16_GO_LSRM_S_GO },
+ { ARC700F_INSN_ASR_L_S12__RA_, && case_sem_INSN_ASR_L_S12__RA_ },
+ { ARC700F_INSN_ASR_CCU6__RA_, && case_sem_INSN_ASR_CCU6__RA_ },
+ { ARC700F_INSN_ASR_L_U6__RA_, && case_sem_INSN_ASR_L_U6__RA_ },
+ { ARC700F_INSN_ASR_L_R_R__RA__RC, && case_sem_INSN_ASR_L_R_R__RA__RC },
+ { ARC700F_INSN_ASR_CC__RA__RC, && case_sem_INSN_ASR_CC__RA__RC },
+ { ARC700F_INSN_ASR_S_CBU3, && case_sem_INSN_ASR_S_CBU3 },
+ { ARC700F_INSN_ASR_S_SSB, && case_sem_INSN_ASR_S_SSB },
+ { ARC700F_INSN_I16_GO_ASRM_S_GO, && case_sem_INSN_I16_GO_ASRM_S_GO },
+ { ARC700F_INSN_ROR_L_S12__RA_, && case_sem_INSN_ROR_L_S12__RA_ },
+ { ARC700F_INSN_ROR_CCU6__RA_, && case_sem_INSN_ROR_CCU6__RA_ },
+ { ARC700F_INSN_ROR_L_U6__RA_, && case_sem_INSN_ROR_L_U6__RA_ },
+ { ARC700F_INSN_ROR_L_R_R__RA__RC, && case_sem_INSN_ROR_L_R_R__RA__RC },
+ { ARC700F_INSN_ROR_CC__RA__RC, && case_sem_INSN_ROR_CC__RA__RC },
+ { ARC700F_INSN_MUL64_L_S12_, && case_sem_INSN_MUL64_L_S12_ },
+ { ARC700F_INSN_MUL64_CCU6_, && case_sem_INSN_MUL64_CCU6_ },
+ { ARC700F_INSN_MUL64_L_U6_, && case_sem_INSN_MUL64_L_U6_ },
+ { ARC700F_INSN_MUL64_L_R_R__RC, && case_sem_INSN_MUL64_L_R_R__RC },
+ { ARC700F_INSN_MUL64_CC__RC, && case_sem_INSN_MUL64_CC__RC },
+ { ARC700F_INSN_MUL64_S_GO, && case_sem_INSN_MUL64_S_GO },
+ { ARC700F_INSN_MULU64_L_S12_, && case_sem_INSN_MULU64_L_S12_ },
+ { ARC700F_INSN_MULU64_CCU6_, && case_sem_INSN_MULU64_CCU6_ },
+ { ARC700F_INSN_MULU64_L_U6_, && case_sem_INSN_MULU64_L_U6_ },
+ { ARC700F_INSN_MULU64_L_R_R__RC, && case_sem_INSN_MULU64_L_R_R__RC },
+ { ARC700F_INSN_MULU64_CC__RC, && case_sem_INSN_MULU64_CC__RC },
+ { ARC700F_INSN_ADDS_L_S12__RA_, && case_sem_INSN_ADDS_L_S12__RA_ },
+ { ARC700F_INSN_ADDS_CCU6__RA_, && case_sem_INSN_ADDS_CCU6__RA_ },
+ { ARC700F_INSN_ADDS_L_U6__RA_, && case_sem_INSN_ADDS_L_U6__RA_ },
+ { ARC700F_INSN_ADDS_L_R_R__RA__RC, && case_sem_INSN_ADDS_L_R_R__RA__RC },
+ { ARC700F_INSN_ADDS_CC__RA__RC, && case_sem_INSN_ADDS_CC__RA__RC },
+ { ARC700F_INSN_SUBS_L_S12__RA_, && case_sem_INSN_SUBS_L_S12__RA_ },
+ { ARC700F_INSN_SUBS_CCU6__RA_, && case_sem_INSN_SUBS_CCU6__RA_ },
+ { ARC700F_INSN_SUBS_L_U6__RA_, && case_sem_INSN_SUBS_L_U6__RA_ },
+ { ARC700F_INSN_SUBS_L_R_R__RA__RC, && case_sem_INSN_SUBS_L_R_R__RA__RC },
+ { ARC700F_INSN_SUBS_CC__RA__RC, && case_sem_INSN_SUBS_CC__RA__RC },
+ { ARC700F_INSN_DIVAW_L_S12__RA_, && case_sem_INSN_DIVAW_L_S12__RA_ },
+ { ARC700F_INSN_DIVAW_CCU6__RA_, && case_sem_INSN_DIVAW_CCU6__RA_ },
+ { ARC700F_INSN_DIVAW_L_U6__RA_, && case_sem_INSN_DIVAW_L_U6__RA_ },
+ { ARC700F_INSN_DIVAW_L_R_R__RA__RC, && case_sem_INSN_DIVAW_L_R_R__RA__RC },
+ { ARC700F_INSN_DIVAW_CC__RA__RC, && case_sem_INSN_DIVAW_CC__RA__RC },
+ { ARC700F_INSN_ASLS_L_S12__RA_, && case_sem_INSN_ASLS_L_S12__RA_ },
+ { ARC700F_INSN_ASLS_CCU6__RA_, && case_sem_INSN_ASLS_CCU6__RA_ },
+ { ARC700F_INSN_ASLS_L_U6__RA_, && case_sem_INSN_ASLS_L_U6__RA_ },
+ { ARC700F_INSN_ASLS_L_R_R__RA__RC, && case_sem_INSN_ASLS_L_R_R__RA__RC },
+ { ARC700F_INSN_ASLS_CC__RA__RC, && case_sem_INSN_ASLS_CC__RA__RC },
+ { ARC700F_INSN_ASRS_L_S12__RA_, && case_sem_INSN_ASRS_L_S12__RA_ },
+ { ARC700F_INSN_ASRS_CCU6__RA_, && case_sem_INSN_ASRS_CCU6__RA_ },
+ { ARC700F_INSN_ASRS_L_U6__RA_, && case_sem_INSN_ASRS_L_U6__RA_ },
+ { ARC700F_INSN_ASRS_L_R_R__RA__RC, && case_sem_INSN_ASRS_L_R_R__RA__RC },
+ { ARC700F_INSN_ASRS_CC__RA__RC, && case_sem_INSN_ASRS_CC__RA__RC },
+ { ARC700F_INSN_ADDSDW_L_S12__RA_, && case_sem_INSN_ADDSDW_L_S12__RA_ },
+ { ARC700F_INSN_ADDSDW_CCU6__RA_, && case_sem_INSN_ADDSDW_CCU6__RA_ },
+ { ARC700F_INSN_ADDSDW_L_U6__RA_, && case_sem_INSN_ADDSDW_L_U6__RA_ },
+ { ARC700F_INSN_ADDSDW_L_R_R__RA__RC, && case_sem_INSN_ADDSDW_L_R_R__RA__RC },
+ { ARC700F_INSN_ADDSDW_CC__RA__RC, && case_sem_INSN_ADDSDW_CC__RA__RC },
+ { ARC700F_INSN_SUBSDW_L_S12__RA_, && case_sem_INSN_SUBSDW_L_S12__RA_ },
+ { ARC700F_INSN_SUBSDW_CCU6__RA_, && case_sem_INSN_SUBSDW_CCU6__RA_ },
+ { ARC700F_INSN_SUBSDW_L_U6__RA_, && case_sem_INSN_SUBSDW_L_U6__RA_ },
+ { ARC700F_INSN_SUBSDW_L_R_R__RA__RC, && case_sem_INSN_SUBSDW_L_R_R__RA__RC },
+ { ARC700F_INSN_SUBSDW_CC__RA__RC, && case_sem_INSN_SUBSDW_CC__RA__RC },
+ { ARC700F_INSN_SWAP_L_R_R__RC, && case_sem_INSN_SWAP_L_R_R__RC },
+ { ARC700F_INSN_SWAP_L_U6_, && case_sem_INSN_SWAP_L_U6_ },
+ { ARC700F_INSN_NORM_L_R_R__RC, && case_sem_INSN_NORM_L_R_R__RC },
+ { ARC700F_INSN_NORM_L_U6_, && case_sem_INSN_NORM_L_U6_ },
+ { ARC700F_INSN_RND16_L_R_R__RC, && case_sem_INSN_RND16_L_R_R__RC },
+ { ARC700F_INSN_RND16_L_U6_, && case_sem_INSN_RND16_L_U6_ },
+ { ARC700F_INSN_ABSSW_L_R_R__RC, && case_sem_INSN_ABSSW_L_R_R__RC },
+ { ARC700F_INSN_ABSSW_L_U6_, && case_sem_INSN_ABSSW_L_U6_ },
+ { ARC700F_INSN_ABSS_L_R_R__RC, && case_sem_INSN_ABSS_L_R_R__RC },
+ { ARC700F_INSN_ABSS_L_U6_, && case_sem_INSN_ABSS_L_U6_ },
+ { ARC700F_INSN_NEGSW_L_R_R__RC, && case_sem_INSN_NEGSW_L_R_R__RC },
+ { ARC700F_INSN_NEGSW_L_U6_, && case_sem_INSN_NEGSW_L_U6_ },
+ { ARC700F_INSN_NEGS_L_R_R__RC, && case_sem_INSN_NEGS_L_R_R__RC },
+ { ARC700F_INSN_NEGS_L_U6_, && case_sem_INSN_NEGS_L_U6_ },
+ { ARC700F_INSN_NORMW_L_R_R__RC, && case_sem_INSN_NORMW_L_R_R__RC },
+ { ARC700F_INSN_NORMW_L_U6_, && case_sem_INSN_NORMW_L_U6_ },
+ { ARC700F_INSN_NOP_S, && case_sem_INSN_NOP_S },
+ { ARC700F_INSN_UNIMP_S, && case_sem_INSN_UNIMP_S },
+ { ARC700F_INSN_POP_S_B, && case_sem_INSN_POP_S_B },
+ { ARC700F_INSN_POP_S_BLINK, && case_sem_INSN_POP_S_BLINK },
+ { ARC700F_INSN_PUSH_S_B, && case_sem_INSN_PUSH_S_B },
+ { ARC700F_INSN_PUSH_S_BLINK, && case_sem_INSN_PUSH_S_BLINK },
+ { ARC700F_INSN_MULLW_L_S12__RA_, && case_sem_INSN_MULLW_L_S12__RA_ },
+ { ARC700F_INSN_MULLW_CCU6__RA_, && case_sem_INSN_MULLW_CCU6__RA_ },
+ { ARC700F_INSN_MULLW_L_U6__RA_, && case_sem_INSN_MULLW_L_U6__RA_ },
+ { ARC700F_INSN_MULLW_L_R_R__RA__RC, && case_sem_INSN_MULLW_L_R_R__RA__RC },
+ { ARC700F_INSN_MULLW_CC__RA__RC, && case_sem_INSN_MULLW_CC__RA__RC },
+ { ARC700F_INSN_MACLW_L_S12__RA_, && case_sem_INSN_MACLW_L_S12__RA_ },
+ { ARC700F_INSN_MACLW_CCU6__RA_, && case_sem_INSN_MACLW_CCU6__RA_ },
+ { ARC700F_INSN_MACLW_L_U6__RA_, && case_sem_INSN_MACLW_L_U6__RA_ },
+ { ARC700F_INSN_MACLW_L_R_R__RA__RC, && case_sem_INSN_MACLW_L_R_R__RA__RC },
+ { ARC700F_INSN_MACLW_CC__RA__RC, && case_sem_INSN_MACLW_CC__RA__RC },
+ { ARC700F_INSN_MACHLW_L_S12__RA_, && case_sem_INSN_MACHLW_L_S12__RA_ },
+ { ARC700F_INSN_MACHLW_CCU6__RA_, && case_sem_INSN_MACHLW_CCU6__RA_ },
+ { ARC700F_INSN_MACHLW_L_U6__RA_, && case_sem_INSN_MACHLW_L_U6__RA_ },
+ { ARC700F_INSN_MACHLW_L_R_R__RA__RC, && case_sem_INSN_MACHLW_L_R_R__RA__RC },
+ { ARC700F_INSN_MACHLW_CC__RA__RC, && case_sem_INSN_MACHLW_CC__RA__RC },
+ { ARC700F_INSN_MULULW_L_S12__RA_, && case_sem_INSN_MULULW_L_S12__RA_ },
+ { ARC700F_INSN_MULULW_CCU6__RA_, && case_sem_INSN_MULULW_CCU6__RA_ },
+ { ARC700F_INSN_MULULW_L_U6__RA_, && case_sem_INSN_MULULW_L_U6__RA_ },
+ { ARC700F_INSN_MULULW_L_R_R__RA__RC, && case_sem_INSN_MULULW_L_R_R__RA__RC },
+ { ARC700F_INSN_MULULW_CC__RA__RC, && case_sem_INSN_MULULW_CC__RA__RC },
+ { ARC700F_INSN_MACHULW_L_S12__RA_, && case_sem_INSN_MACHULW_L_S12__RA_ },
+ { ARC700F_INSN_MACHULW_CCU6__RA_, && case_sem_INSN_MACHULW_CCU6__RA_ },
+ { ARC700F_INSN_MACHULW_L_U6__RA_, && case_sem_INSN_MACHULW_L_U6__RA_ },
+ { ARC700F_INSN_MACHULW_L_R_R__RA__RC, && case_sem_INSN_MACHULW_L_R_R__RA__RC },
+ { ARC700F_INSN_MACHULW_CC__RA__RC, && case_sem_INSN_MACHULW_CC__RA__RC },
+ { ARC700F_INSN_CURRENT_LOOP_END, && case_sem_INSN_CURRENT_LOOP_END },
+ { ARC700F_INSN_CURRENT_LOOP_END_AFTER_BRANCH, && case_sem_INSN_CURRENT_LOOP_END_AFTER_BRANCH },
+ { ARC700F_INSN_ARC600_CURRENT_LOOP_END_AFTER_BRANCH, && case_sem_INSN_ARC600_CURRENT_LOOP_END_AFTER_BRANCH },
+ { 0, 0 }
+ };
+ int i;
+
+ for (i = 0; labels[i].label != 0; ++i)
+ {
+#if FAST_P
+ CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
+#else
+ CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
+#endif
+ }
+
+#undef DEFINE_LABELS
+#endif /* DEFINE_LABELS */
+
+#ifdef DEFINE_SWITCH
+
+/* If hyper-fast [well not unnecessarily slow] execution is selected, turn
+ off frills like tracing and profiling. */
+/* FIXME: A better way would be to have TRACE_RESULT check for something
+ that can cause it to be optimized out. Another way would be to emit
+ special handlers into the instruction "stream". */
+
+#if FAST_P
+#undef TRACE_RESULT
+#define TRACE_RESULT(cpu, abuf, name, type, val)
+#endif
+
+#undef GET_ATTR
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
+#else
+#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr)
+#endif
+
+{
+
+#if WITH_SCACHE_PBB
+
+/* Branch to next handler without going around main loop. */
+#define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
+SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
+
+#else /* ! WITH_SCACHE_PBB */
+
+#define NEXT(vpc) BREAK (sem)
+#ifdef __GNUC__
+#if FAST_P
+ SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
+#else
+ SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
+#endif
+#else
+ SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
+#endif
+
+#endif /* ! WITH_SCACHE_PBB */
+
+ {
+
+ CASE (sem, INSN_X_INVALID) : /* --invalid-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+ /* Update the recorded pc in the cpu state struct.
+ Only necessary for WITH_SCACHE case, but to avoid the
+ conditional compilation .... */
+ SET_H_PC (pc);
+ /* Virtual insns have zero size. Overwrite vpc with address of next insn
+ using the default-insn-bitsize spec. When executing insns in parallel
+ we may want to queue the fault and continue execution. */
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+ vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_AFTER) : /* --after-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_ARC700F
+ arc700f_pbb_after (current_cpu, sem_arg);
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_BEFORE) : /* --before-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_ARC700F
+ arc700f_pbb_before (current_cpu, sem_arg);
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_ARC700F
+#ifdef DEFINE_SWITCH
+ vpc = arc700f_pbb_cti_chain (current_cpu, sem_arg,
+ pbb_br_type, pbb_br_npc);
+ BREAK (sem);
+#else
+ /* FIXME: Allow provision of explicit ifmt spec in insn spec. */
+ vpc = arc700f_pbb_cti_chain (current_cpu, sem_arg,
+ CPU_PBB_BR_TYPE (current_cpu),
+ CPU_PBB_BR_NPC (current_cpu));
+#endif
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_CHAIN) : /* --chain-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_ARC700F
+ vpc = arc700f_pbb_chain (current_cpu, sem_arg);
+#ifdef DEFINE_SWITCH
+ BREAK (sem);
+#endif
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_BEGIN) : /* --begin-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_ARC700F
+#if defined DEFINE_SWITCH || defined FAST_P
+ /* In the switch case FAST_P is a constant, allowing several optimizations
+ in any called inline functions. */
+ vpc = arc700f_pbb_begin (current_cpu, FAST_P);
+#else
+#if 0 /* cgen engine can't handle dynamic fast/full switching yet. */
+ vpc = arc700f_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
+#else
+ vpc = arc700f_pbb_begin (current_cpu, 0);
+#endif
+#endif
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_B_S) : /* b$i2cond $label10 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_b_s.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GET_H_I2COND (FLD (f_cond_i2))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = FLD (i_label10);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = FLD (i_label10);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = FLD (i_label10);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BCC_S) : /* b$i3cond$_S $label7 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bcc_s.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GET_H_I3COND (FLD (f_cond_i3))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = FLD (i_label7);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = FLD (i_label7);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = FLD (i_label7);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BRCC_S) : /* br$RccS$_S $R_b,0,$label8 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_brcc_s.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if ((FLD (f_brscond) == 0) ? (EQSI (GET_H_CR16 (FLD (f_op__b)), 0)) : (FLD (f_brscond) == 1) ? (NESI (GET_H_CR16 (FLD (f_op__b)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = FLD (i_label8);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = FLD (i_label8);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = FLD (i_label8);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BCC_L) : /* b$Qcondb$_L $label21 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bcc_l.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+((void) 0); /*nop*/
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = FLD (i_label21);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = FLD (i_label21);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = FLD (i_label21);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BCC_L_D) : /* b$Qcondb$_L.d $label21 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bcc_l.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+((void) 0); /*nop*/
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (i_label21);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else if (1) {
+{
+ {
+ USI opval = FLD (i_label21);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ {
+ USI opval = FLD (i_label21);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_B_L) : /* b$uncondb$_L $label25 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_b_l.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = FLD (i_label25);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = FLD (i_label25);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = FLD (i_label25);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_B_L_D) : /* b$uncondb$_L.d $label25 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_b_l.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (i_label25);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else if (1) {
+{
+ {
+ USI opval = FLD (i_label25);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ {
+ USI opval = FLD (i_label25);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BRCC_RC) : /* b$Rcc $RB,$RC,$label9 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_brcc_RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BRCC_RC_D) : /* b$Rcc.d $RB,$RC,$label9 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_brcc_RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+{
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+{
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+{
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BRCC_U6) : /* b$Rcc $RB,$U6,$label9 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_brcc_U6.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BRCC_U6_D) : /* b$Rcc.d $RB,$U6,$label9 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_brcc_U6.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+{
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+{
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+{
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BL_S) : /* bl$uncondj$_S $label13a */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl_s.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ {
+ SI opval = ADDSI (pc, 2);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label13a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else if (0) {
+{
+ {
+ SI opval = ADDSI (pc, 2);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label13a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ {
+ SI opval = ADDSI (pc, 2);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label13a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BLCC) : /* bl$Qcondj$_L $label21 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_blcc.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+((void) 0); /*nop*/
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label21a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else if (0) {
+{
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label21a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label21a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BLCC_D) : /* bl$Qcondj$_L.d $label21 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_blcc.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+((void) 0); /*nop*/
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+{
+ {
+ USI opval = FLD (i_label21a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+{
+ {
+ USI opval = FLD (i_label21a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+{
+ {
+ USI opval = FLD (i_label21a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BL) : /* bl$uncondj$_L $label25a */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label25a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else if (0) {
+{
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label25a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label25a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BL_D) : /* bl$uncondj$_L.d $label25a */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (i_label25a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (i_label25a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (i_label25a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD_ABS) : /* ld$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD__AW_ABS) : /* ld$_AW$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD_AB_ABS) : /* ld.ab$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD_AS_ABS) : /* ld.as$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s9), 2));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD_ABC) : /* ld$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD__AW_ABC) : /* ld$_AW$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD_AB_ABC) : /* ld.ab$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD_AS_ABC) : /* ld.as$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 2));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD_S_ABC) : /* ld$_S $R_a,[$R_b,$R_c] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), GET_H_CR16 (FLD (f_op__c)));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR16 (FLD (f_op__a), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD_S_ABU) : /* ld$_S $R_c,[$R_b,$sc_u5_] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), FLD (f_u5x4));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD_S_ABSP) : /* ld$_S $R_b,[$SP,$u5x4] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_SP (), FLD (f_u5x4));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD_S_GPREL) : /* ld$_S $R_b,[$GP,$sc_s9_] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_gprel.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_GP (), FLD (f_s9x4));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_R0 (, opval);
+ TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD_S_PCREL) : /* ld$_S $R_b,[$PCL,$u8x4] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_pcrel.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (ANDSI (pc, -4), FLD (f_u8x4));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_ABS) : /* ldb$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB__AW_ABS) : /* ldb$_AW$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_AB_ABS) : /* ldb.ab$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_AS_ABS) : /* ldb.as$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), (cgen_rtx_error (current_cpu, "invalid insn"), 0));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_ABC) : /* ldb$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB__AW_ABC) : /* ldb$_AW$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_AB_ABC) : /* ldb.ab$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_AS_ABC) : /* ldb.as$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), (cgen_rtx_error (current_cpu, "invalid insn"), 0));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_S_ABC) : /* ldb$_S $R_a,[$R_b,$R_c] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), GET_H_CR16 (FLD (f_op__c)));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR16 (FLD (f_op__a), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_S_ABU) : /* ldb$_S $R_c,[$R_b,$sc_u5b] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), FLD (f_u5));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_S_ABSP) : /* ldb$_S $R_b,[$SP,$u5x4] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_SP (), FLD (f_u5x4));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_S_GPREL) : /* ldb$_S $R_b,[$GP,$sc_s9b] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldb_s_gprel.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_GP (), FLD (f_s9x1));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_R0 (, opval);
+ TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_X_ABS) : /* ldb.x$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB__AW_X_ABS) : /* ldb$_AW.x$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_AB_X_ABS) : /* ldb.ab.x$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_AS_X_ABS) : /* ldb.as.x$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), (cgen_rtx_error (current_cpu, "invalid insn"), 0));
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_X_ABC) : /* ldb.x$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB__AW_X_ABC) : /* ldb$_AW.x$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_AB_X_ABC) : /* ldb.ab.x$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_AS_X_ABC) : /* ldb.as.x$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), (cgen_rtx_error (current_cpu, "invalid insn"), 0));
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_ABS) : /* ldw$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW__AW_ABS) : /* ldw$_AW$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_AB_ABS) : /* ldw.ab$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_AS_ABS) : /* ldw.as$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s9), 1));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_ABC) : /* ldw$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW__AW_ABC) : /* ldw$_AW$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_AB_ABC) : /* ldw.ab$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_AS_ABC) : /* ldw.as$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 1));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_S_ABC) : /* ldw$_S $R_a,[$R_b,$R_c] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), GET_H_CR16 (FLD (f_op__c)));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR16 (FLD (f_op__a), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_S_ABU) : /* ldw$_S $R_c,[$R_b,$sc_u5w] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldw_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), FLD (f_u5x2));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_S_GPREL) : /* ldw$_S $R_b,[$GP,$sc_s9w] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldw_s_gprel.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_GP (), FLD (f_s9x2));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_R0 (, opval);
+ TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_X_ABS) : /* ldw.x$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW__AW_X_ABS) : /* ldw$_AW.x$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_AB_X_ABS) : /* ldw.ab.x$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_AS_X_ABS) : /* ldw.as.x$LDODi $RA,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s9), 1));
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_X_ABC) : /* ldw.x$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW__AW_X_ABC) : /* ldw$_AW.x$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_AB_X_ABC) : /* ldw.ab.x$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_AS_X_ABC) : /* ldw.as.x$LDRDi $RA,[$RB,$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 1));
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW_S_X_ABU) : /* ldw$_S.x $R_c,[$R_b,$sc_u5w] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldw_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), FLD (f_u5x2));
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ST_ABS) : /* st$STODi $RC,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMSI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ST__AW_ABS) : /* st$_AW$STODi $RC,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMSI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ST_AB_ABS) : /* st.ab$STODi $RC,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMSI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ST_AS_ABS) : /* st.as$STODi $RC,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s9), 2));
+ {
+ SI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMSI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ST_S_ABU) : /* st$_S $R_c,[$R_b,$sc_u5_] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), FLD (f_u5x4));
+ {
+ SI opval = GET_H_CR16 (FLD (f_op__c));
+ SETMEMSI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ST_S_ABSP) : /* st$_S $R_b,[$SP,$u5x4] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_SP (), FLD (f_u5x4));
+ {
+ SI opval = GET_H_CR16 (FLD (f_op__b));
+ SETMEMSI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STB_ABS) : /* stb$STODi $RC,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ QI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMQI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STB__AW_ABS) : /* stb$_AW$STODi $RC,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ QI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMQI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STB_AB_ABS) : /* stb.ab$STODi $RC,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ QI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMQI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STB_AS_ABS) : /* stb.as$STODi $RC,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), (cgen_rtx_error (current_cpu, "invalid insn"), 0));
+ {
+ QI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMQI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STB_S_ABU) : /* stb$_S $R_c,[$R_b,$sc_u5b] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), FLD (f_u5));
+ {
+ QI opval = GET_H_CR16 (FLD (f_op__c));
+ SETMEMQI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STB_S_ABSP) : /* stb$_S $R_b,[$SP,$u5x4] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_SP (), FLD (f_u5x4));
+ {
+ QI opval = GET_H_CR16 (FLD (f_op__b));
+ SETMEMQI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STW_ABS) : /* stw$STODi $RC,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ HI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMHI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STW__AW_ABS) : /* stw$_AW$STODi $RC,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ HI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMHI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STW_AB_ABS) : /* stw.ab$STODi $RC,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ HI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMHI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STW_AS_ABS) : /* stw.as$STODi $RC,[$RB,$s9] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s9), 1));
+ {
+ HI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMHI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STW_S_ABU) : /* stw$_S $R_c,[$R_b,$sc_u5w] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldw_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), FLD (f_u5x2));
+ {
+ HI opval = GET_H_CR16 (FLD (f_op__c));
+ SETMEMHI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_L_S12__RA_) : /* add$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_CCU6__RA_) : /* add$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_L_U6__RA_) : /* add$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_L_R_R__RA__RC) : /* add$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_CC__RA__RC) : /* add$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_S_ABC) : /* add$_S $R_a,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ADDSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__a), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_S_CBU3) : /* add$_S $R_c,$R_b,$u3 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u3);
+ {
+ SI opval = ADDSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_S_MCAH) : /* add$_S $R_b,$R_b,$Rh */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+{
+if (EQSI (FLD (f_op_h), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 2));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (2, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_h), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR (FLD (f_op_h));
+ {
+ SI opval = ADDSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_S_ABSP) : /* add$_S $R_b,$SP,$u5x4 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_SP ();
+ tmp_C = FLD (f_u5x4);
+ {
+ SI opval = ADDSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_S_ASSPSP) : /* add$_S $SP,$SP,$u5x4 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_SP ();
+ tmp_C = FLD (f_u5x4);
+ {
+ SI opval = ADDSI (tmp_B, tmp_C);
+ SET_H_SP (, opval);
+ TRACE_RESULT (current_cpu, abuf, "sp", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_S_GP) : /* add$_S $R0,$GP,$s9x4 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_gprel.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_GP ();
+ tmp_C = FLD (f_s9x4);
+ {
+ SI opval = ADDSI (tmp_B, tmp_C);
+ SET_H_R0 (, opval);
+ TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_S_R_U7) : /* add$_S $R_b,$R_b,$u7 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_r_u7.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u7);
+ {
+ SI opval = ADDSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADC_L_S12__RA_) : /* adc$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDCSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADC_CCU6__RA_) : /* adc$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDCSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADC_L_U6__RA_) : /* adc$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDCSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADC_L_R_R__RA__RC) : /* adc$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDCSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADC_CC__RA__RC) : /* adc$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDCSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_L_S12__RA_) : /* sub$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_CCU6__RA_) : /* sub$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_L_U6__RA_) : /* sub$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_L_R_R__RA__RC) : /* sub$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_CC__RA__RC) : /* sub$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_S_CBU3) : /* sub$_S $R_c,$R_b,$u3 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u3);
+ {
+ SI opval = SUBSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_SUB_S_GO) : /* sub$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = SUBSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_S_GO_SUB_NE) : /* sub$_S $NE$R_b,$R_b,$R_b */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQBI (CPU (h_zbit), 0)) {
+ {
+ SI opval = 0;
+ SET_H_CR16 (FLD (f_op__b), opval);
+ written |= (1 << 1);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_S_SSB) : /* sub$_S $R_b,$R_b,$u5 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ {
+ SI opval = SUBSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_S_ASSPSP) : /* sub$_S $SP,$SP,$u5x4 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_SP ();
+ tmp_C = FLD (f_u5x4);
+ {
+ SI opval = SUBSI (tmp_B, tmp_C);
+ SET_H_SP (, opval);
+ TRACE_RESULT (current_cpu, abuf, "sp", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SBC_L_S12__RA_) : /* sbc$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBCSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SBC_CCU6__RA_) : /* sbc$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBCSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SBC_L_U6__RA_) : /* sbc$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBCSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SBC_L_R_R__RA__RC) : /* sbc$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBCSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SBC_CC__RA__RC) : /* sbc$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBCSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_AND_L_S12__RA_) : /* and$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_AND_CCU6__RA_) : /* and$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_AND_L_U6__RA_) : /* and$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_AND_L_R_R__RA__RC) : /* and$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_AND_CC__RA__RC) : /* and$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_AND_S_GO) : /* and$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ANDSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_OR_L_S12__RA_) : /* or$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_OR_CCU6__RA_) : /* or$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_OR_L_U6__RA_) : /* or$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_OR_L_R_R__RA__RC) : /* or$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_OR_CC__RA__RC) : /* or$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_OR_S_GO) : /* or$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ORSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BIC_L_S12__RA_) : /* bic$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (FLD (f_s12)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BIC_CCU6__RA_) : /* bic$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (FLD (f_u6)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BIC_L_U6__RA_) : /* bic$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (FLD (f_u6)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BIC_L_R_R__RA__RC) : /* bic$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BIC_CC__RA__RC) : /* bic$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_BIC_S_GO) : /* bic$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ANDSI (tmp_B, INVSI (tmp_C));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_XOR_L_S12__RA_) : /* xor$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_XOR_CCU6__RA_) : /* xor$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_XOR_L_U6__RA_) : /* xor$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_XOR_L_R_R__RA__RC) : /* xor$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_XOR_CC__RA__RC) : /* xor$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_XOR_S_GO) : /* xor$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = XORSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MAX_L_S12__RA_) : /* max$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (GTSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12))) ? (GET_H_CR (FLD (f_op_B))) : (FLD (f_s12));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = GESI (FLD (f_s12), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MAX_CCU6__RA_) : /* max$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (GTSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6))) ? (GET_H_CR (FLD (f_op_B))) : (FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = GESI (FLD (f_u6), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MAX_L_U6__RA_) : /* max$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (GTSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6))) ? (GET_H_CR (FLD (f_op_B))) : (FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = GESI (FLD (f_u6), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MAX_L_R_R__RA__RC) : /* max$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (GTSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)))) ? (GET_H_CR (FLD (f_op_B))) : (GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = GESI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MAX_CC__RA__RC) : /* max$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (GTSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)))) ? (GET_H_CR (FLD (f_op_B))) : (GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = GESI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MIN_L_S12__RA_) : /* min$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (LTSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12))) ? (GET_H_CR (FLD (f_op_B))) : (FLD (f_s12));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = LESI (FLD (f_s12), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MIN_CCU6__RA_) : /* min$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (LTSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6))) ? (GET_H_CR (FLD (f_op_B))) : (FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = LESI (FLD (f_u6), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MIN_L_U6__RA_) : /* min$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (LTSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6))) ? (GET_H_CR (FLD (f_op_B))) : (FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = LESI (FLD (f_u6), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MIN_L_R_R__RA__RC) : /* min$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (LTSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)))) ? (GET_H_CR (FLD (f_op_B))) : (GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = LESI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MIN_CC__RA__RC) : /* min$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (LTSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)))) ? (GET_H_CR (FLD (f_op_B))) : (GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = LESI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOV_L_S12_) : /* mov$_L$F $RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+ tmp_result = FLD (f_s12);
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GTSI (FLD (f_F), 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOV_CCU6_) : /* mov$Qcondi$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+((void) 0); /*nop*/
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+ tmp_result = FLD (f_u6);
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GTSI (FLD (f_F), 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 5);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOV_L_U6_) : /* mov$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+ tmp_result = FLD (f_u6);
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GTSI (FLD (f_F), 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOV_L_R_R__RC) : /* mov$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = GET_H_CR (FLD (f_op_C));
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GTSI (FLD (f_F), 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOV_CC__RC) : /* mov$Qcondi$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+ tmp_result = GET_H_CR (FLD (f_op_C));
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GTSI (FLD (f_F), 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOV_S_MCAH) : /* mov$_S $R_b,$Rh */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_h), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 2));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (2, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_h), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = GET_H_CR (FLD (f_op_h));
+ {
+ SI opval = tmp_result;
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+if (GTSI (-1, 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOV_S_MCAHB) : /* mov$_S $Rh,$R_b */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+ tmp_result = GET_H_CR16 (FLD (f_op__b));
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_h), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GTSI (-1, 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOV_S_R_U7) : /* mov$_S $R_b,$u7 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+ tmp_result = FLD (f_u8);
+ {
+ SI opval = tmp_result;
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+if (GTSI (-1, 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_TST_L_S12_) : /* tst$_L$F1 $RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_s12);
+ tmp_result = ANDSI (tmp_B, tmp_C);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_TST_CCU6_) : /* tst$Qcondi$F1 $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+ tmp_result = ANDSI (tmp_B, tmp_C);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_TST_L_U6_) : /* tst$_L$F1 $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+ tmp_result = ANDSI (tmp_B, tmp_C);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_TST_L_R_R__RC) : /* tst$_L$F1 $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+ tmp_result = ANDSI (tmp_B, tmp_C);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_TST_CC__RC) : /* tst$Qcondi$F1 $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+ tmp_result = ANDSI (tmp_B, tmp_C);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_TST_S_GO) : /* tst$_S $R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ tmp_result = ANDSI (tmp_B, tmp_C);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMP_L_S12_) : /* cmp$_L$F1 $RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (FLD (f_s12));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (FLD (f_s12));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMP_CCU6_) : /* cmp$Qcondi$F1 $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMP_L_U6_) : /* cmp$_L$F1 $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMP_L_R_R__RC) : /* cmp$_L$F1 $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMP_CC__RC) : /* cmp$Qcondi$F1 $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMP_S_MCAH) : /* cmp$_S $R_b,$Rh */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+{
+if (EQSI (FLD (f_op_h), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 2));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (2, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_h), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = EXTSIDI (GET_H_CR16 (FLD (f_op__b)));
+ tmp_C = EXTSIDI (GET_H_CR (FLD (f_op_h)));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR16 (FLD (f_op__b)));
+ tmp_C = ZEXTSIDI (GET_H_CR (FLD (f_op_h)));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMP_S_R_U7) : /* cmp$_S $R_b,$u7 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_r_u7.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = EXTSIDI (GET_H_CR16 (FLD (f_op__b)));
+ tmp_C = EXTSIDI (FLD (f_u7));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR16 (FLD (f_op__b)));
+ tmp_C = ZEXTSIDI (FLD (f_u7));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RCMP_L_S12_) : /* rcmp$_L$F1 $RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (FLD (f_s12));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (FLD (f_s12));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RCMP_CCU6_) : /* rcmp$Qcondi$F1 $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RCMP_L_U6_) : /* rcmp$_L$F1 $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RCMP_L_R_R__RC) : /* rcmp$_L$F1 $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RCMP_CC__RC) : /* rcmp$Qcondi$F1 $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RSUB_L_S12__RA_) : /* rsub$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (FLD (f_s12), GET_H_CR (FLD (f_op_B)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (FLD (f_s12), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (FLD (f_s12), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RSUB_CCU6__RA_) : /* rsub$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (FLD (f_u6), GET_H_CR (FLD (f_op_B)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (FLD (f_u6), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (FLD (f_u6), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RSUB_L_U6__RA_) : /* rsub$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (FLD (f_u6), GET_H_CR (FLD (f_op_B)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (FLD (f_u6), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (FLD (f_u6), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RSUB_L_R_R__RA__RC) : /* rsub$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RSUB_CC__RA__RC) : /* rsub$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BSET_L_S12__RA_) : /* bset$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (FLD (f_s12), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BSET_CCU6__RA_) : /* bset$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BSET_L_U6__RA_) : /* bset$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BSET_L_R_R__RA__RC) : /* bset$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BSET_CC__RA__RC) : /* bset$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BSET_S_SSB) : /* bset$_S $R_b,$R_b,$u5 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ {
+ SI opval = ORSI (tmp_B, SLLSI (1, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BCLR_L_S12__RA_) : /* bclr$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (SLLSI (1, ANDSI (FLD (f_s12), 31))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BCLR_CCU6__RA_) : /* bclr$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (SLLSI (1, ANDSI (FLD (f_u6), 31))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BCLR_L_U6__RA_) : /* bclr$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (SLLSI (1, ANDSI (FLD (f_u6), 31))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BCLR_L_R_R__RA__RC) : /* bclr$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BCLR_CC__RA__RC) : /* bclr$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BCLR_S_SSB) : /* bclr$_S $R_b,$R_b,$u5 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ {
+ SI opval = ANDSI (tmp_B, INVSI (SLLSI (1, ANDSI (tmp_C, 31))));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BTST_L_S12_) : /* btst$_L$F1 $RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_s12);
+ tmp_result = ANDSI (tmp_B, SLLSI (1, ANDSI (tmp_C, 31)));
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BTST_CCU6_) : /* btst$Qcondi$F1 $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+ tmp_result = ANDSI (tmp_B, SLLSI (1, ANDSI (tmp_C, 31)));
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BTST_L_U6_) : /* btst$_L$F1 $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+ tmp_result = ANDSI (tmp_B, SLLSI (1, ANDSI (tmp_C, 31)));
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BTST_L_R_R__RC) : /* btst$_L$F1 $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+ tmp_result = ANDSI (tmp_B, SLLSI (1, ANDSI (tmp_C, 31)));
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BTST_CC__RC) : /* btst$Qcondi$F1 $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+ tmp_result = ANDSI (tmp_B, SLLSI (1, ANDSI (tmp_C, 31)));
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BTST_S_SSB) : /* btst$_S $R_b,$u5 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ tmp_result = ANDSI (tmp_B, SLLSI (1, ANDSI (tmp_C, 31)));
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BXOR_L_S12__RA_) : /* bxor$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (FLD (f_s12), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BXOR_CCU6__RA_) : /* bxor$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BXOR_L_U6__RA_) : /* bxor$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BXOR_L_R_R__RA__RC) : /* bxor$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BXOR_CC__RA__RC) : /* bxor$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BMSK_L_S12__RA_) : /* bmsk$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), SUBSI (SLLSI (SLLSI (1, ANDSI (FLD (f_s12), 31)), 1), 1));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BMSK_CCU6__RA_) : /* bmsk$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), SUBSI (SLLSI (SLLSI (1, ANDSI (FLD (f_u6), 31)), 1), 1));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BMSK_L_U6__RA_) : /* bmsk$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), SUBSI (SLLSI (SLLSI (1, ANDSI (FLD (f_u6), 31)), 1), 1));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BMSK_L_R_R__RA__RC) : /* bmsk$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), SUBSI (SLLSI (SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31)), 1), 1));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BMSK_CC__RA__RC) : /* bmsk$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), SUBSI (SLLSI (SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31)), 1), 1));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BMSK_S_SSB) : /* bmsk$_S $R_b,$R_b,$u5 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ {
+ SI opval = ANDSI (tmp_B, SUBSI (SLLSI (SLLSI (1, ANDSI (tmp_C, 31)), 1), 1));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD1_L_S12__RA_) : /* add1$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s12), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_s12), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD1_CCU6__RA_) : /* add1$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD1_L_U6__RA_) : /* add1$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD1_L_R_R__RA__RC) : /* add1$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD1_CC__RA__RC) : /* add1$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_ADD1_S_GO) : /* add1$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ADDSI (tmp_B, SLLSI (tmp_C, 1));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD2_L_S12__RA_) : /* add2$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s12), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_s12), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD2_CCU6__RA_) : /* add2$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD2_L_U6__RA_) : /* add2$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD2_L_R_R__RA__RC) : /* add2$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD2_CC__RA__RC) : /* add2$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_ADD2_S_GO) : /* add2$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ADDSI (tmp_B, SLLSI (tmp_C, 2));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD3_L_S12__RA_) : /* add3$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s12), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_s12), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD3_CCU6__RA_) : /* add3$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD3_L_U6__RA_) : /* add3$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD3_L_R_R__RA__RC) : /* add3$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD3_CC__RA__RC) : /* add3$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_ADD3_S_GO) : /* add3$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ADDSI (tmp_B, SLLSI (tmp_C, 3));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB1_L_S12__RA_) : /* sub1$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s12), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_s12), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB1_CCU6__RA_) : /* sub1$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB1_L_U6__RA_) : /* sub1$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB1_L_R_R__RA__RC) : /* sub1$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB1_CC__RA__RC) : /* sub1$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB2_L_S12__RA_) : /* sub2$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s12), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_s12), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB2_CCU6__RA_) : /* sub2$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB2_L_U6__RA_) : /* sub2$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB2_L_R_R__RA__RC) : /* sub2$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB2_CC__RA__RC) : /* sub2$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB3_L_S12__RA_) : /* sub3$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s12), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_s12), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB3_CCU6__RA_) : /* sub3$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB3_L_U6__RA_) : /* sub3$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB3_L_R_R__RA__RC) : /* sub3$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB3_CC__RA__RC) : /* sub3$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPY_L_S12__RA_) : /* mpy$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (EXTSIDI (tmp_result), MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_s12))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPY_CCU6__RA_) : /* mpy$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (EXTSIDI (tmp_result), MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPY_L_U6__RA_) : /* mpy$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (EXTSIDI (tmp_result), MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPY_L_R_R__RA__RC) : /* mpy$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (EXTSIDI (tmp_result), MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C)))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPY_CC__RA__RC) : /* mpy$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (EXTSIDI (tmp_result), MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C)))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYH_L_S12__RA_) : /* mpyh$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_s12))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYH_CCU6__RA_) : /* mpyh$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYH_L_U6__RA_) : /* mpyh$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYH_L_R_R__RA__RC) : /* mpyh$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C)))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYH_CC__RA__RC) : /* mpyh$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C)))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYHU_L_S12__RA_) : /* mpyhu$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_s12))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYHU_CCU6__RA_) : /* mpyhu$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_u6))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYHU_L_U6__RA_) : /* mpyhu$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_u6))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYHU_L_R_R__RA__RC) : /* mpyhu$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (GET_H_CR (FLD (f_op_C)))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYHU_CC__RA__RC) : /* mpyhu$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (GET_H_CR (FLD (f_op_C)))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYU_L_S12__RA_) : /* mpyu$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (ZEXTSIDI (tmp_result), MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_s12))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYU_CCU6__RA_) : /* mpyu$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (ZEXTSIDI (tmp_result), MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_u6))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYU_L_U6__RA_) : /* mpyu$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (ZEXTSIDI (tmp_result), MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_u6))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYU_L_R_R__RA__RC) : /* mpyu$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (ZEXTSIDI (tmp_result), MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (GET_H_CR (FLD (f_op_C)))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPYU_CC__RA__RC) : /* mpyu$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (ZEXTSIDI (tmp_result), MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (GET_H_CR (FLD (f_op_C)))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_L_R_R___RC_NOILINK_) : /* j$_L$F0 [$RC_noilink] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_CC___RC_NOILINK_) : /* j$Qcondi$F0 [$RC_noilink] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_L_R_R___RC_ILINK_) : /* j$_L$F1F [$RC_ilink] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_ILINKX (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_ILINKX (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_ILINKX (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_CC___RC_ILINK_) : /* j$Qcondi$F1F [$RC_ilink] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_ILINKX (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_ILINKX (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_ILINKX (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_L_S12_) : /* j$_L$F0 $s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_CCU6_) : /* j$Qcondi$F0 $U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_L_U6_) : /* j$_L$F0 $U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_S) : /* j$_S [$R_b] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_S__S) : /* j$_S [$R31] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_SEQ__S) : /* jeq$_S [$R31] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if (NEBI (CPU (h_zbit), 0)) {
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if (NEBI (CPU (h_zbit), 0)) {
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if (NEBI (CPU (h_zbit), 0)) {
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_SNE__S) : /* jne$_S [$R31] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if (EQBI (CPU (h_zbit), 0)) {
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if (EQBI (CPU (h_zbit), 0)) {
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if (EQBI (CPU (h_zbit), 0)) {
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_L_S12_D_) : /* j$_L$F0.d $s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_CCU6_D_) : /* j$Qcondi$F0.d $U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_L_U6_D_) : /* j$_L$F0.d $U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_L_R_R_D___RC_) : /* j$_L$F0.d [$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_CC_D___RC_) : /* j$Qcondi$F0.d [$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_S_D) : /* j$_S.d [$R_b] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_J_S__S_D) : /* j$_S.d [$R31] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JL_L_S12_) : /* jl$_L$F0 $s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JL_CCU6_) : /* jl$Qcondi$F0 $U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JL_L_U6_) : /* jl$_L$F0 $U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JL_S) : /* jl$_S [$R_b] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 2);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 2);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 2);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JL_L_R_R___RC_NOILINK_) : /* jl$_L$F0 [$RC_noilink] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, ((EQSI (FLD (f_op_C), 62)) ? (8) : (4)));
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, ((EQSI (FLD (f_op_C), 62)) ? (8) : (4)));
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, ((EQSI (FLD (f_op_C), 62)) ? (8) : (4)));
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JL_CC___RC_NOILINK_) : /* jl$Qcondi$F0 [$RC_noilink] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, ((EQSI (FLD (f_op_C), 62)) ? (8) : (4)));
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, ((EQSI (FLD (f_op_C), 62)) ? (8) : (4)));
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, ((EQSI (FLD (f_op_C), 62)) ? (8) : (4)));
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JL_L_S12_D_) : /* jl$_L$F0.d $s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JL_CCU6_D_) : /* jl$Qcondi$F0.d $U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JL_L_U6_D_) : /* jl$_L$F0.d $U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JL_L_R_R_D___RC_) : /* jl$_L$F0.d [$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JL_CC_D___RC_) : /* jl$Qcondi$F0.d [$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JL_S_D) : /* jl$_S.d [$R_b] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 2));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 2));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 2));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LP_L_S12_) : /* lp$_L$F0 $s12x2 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_lp_L_s12_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ SI opval = ADDSI (ANDSI (pc, -4), FLD (f_s12x2));
+ SET_H_AUXR (((UINT) 3), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_AUXR (((UINT) 2), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ SI opval = ADDSI (ANDSI (pc, -4), FLD (f_s12x2));
+ SET_H_AUXR (((UINT) 3), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_AUXR (((UINT) 2), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ SI opval = ADDSI (ANDSI (pc, -4), FLD (f_s12x2));
+ SET_H_AUXR (((UINT) 3), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_AUXR (((UINT) 2), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LPCC_CCU6) : /* lp$Qcondi$F0 $U6x2 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_lpcc_ccu6.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ SI opval = ADDSI (ANDSI (pc, -4), FLD (f_u6x2));
+ SET_H_AUXR (((UINT) 3), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_AUXR (((UINT) 2), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ SI opval = ADDSI (ANDSI (pc, -4), FLD (f_u6x2));
+ SET_H_AUXR (((UINT) 3), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_AUXR (((UINT) 2), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ SI opval = ADDSI (ANDSI (pc, -4), FLD (f_u6x2));
+ SET_H_AUXR (((UINT) 3), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_AUXR (((UINT) 2), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+}
+}
+} else {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = ADDSI (ANDSI (pc, -4), FLD (f_u6x2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = ADDSI (ANDSI (pc, -4), FLD (f_u6x2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = ADDSI (ANDSI (pc, -4), FLD (f_u6x2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FLAG_L_S12_) : /* flag$_L$F0 $s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (ANDSI (FLD (f_s12), 1)) {
+sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc, sim_exited, a5f_h_cr_get (current_cpu, 0));}
+ {
+ SI opval = FLD (f_s12);
+ SET_H_STATUS32 (((UINT) 0), opval);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FLAG_CCU6_) : /* flag$Qcondi$F0 $U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+if (ANDSI (FLD (f_u6), 1)) {
+sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc, sim_exited, a5f_h_cr_get (current_cpu, 0));}
+ {
+ SI opval = FLD (f_u6);
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FLAG_L_U6_) : /* flag$_L$F0 $U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (ANDSI (FLD (f_u6), 1)) {
+sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc, sim_exited, a5f_h_cr_get (current_cpu, 0));}
+ {
+ SI opval = FLD (f_u6);
+ SET_H_STATUS32 (((UINT) 0), opval);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FLAG_L_R_R__RC) : /* flag$_L$F0 $RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (ANDSI (GET_H_CR (FLD (f_op_C)), 1)) {
+sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc, sim_exited, a5f_h_cr_get (current_cpu, 0));}
+ {
+ SI opval = GET_H_CR (FLD (f_op_C));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FLAG_CC__RC) : /* flag$Qcondi$F0 $RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+if (ANDSI (GET_H_CR (FLD (f_op_C)), 1)) {
+sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc, sim_exited, a5f_h_cr_get (current_cpu, 0));}
+ {
+ SI opval = GET_H_CR (FLD (f_op_C));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LR_L_R_R___RC_) : /* lr$_L$F0 $RB,[$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ {
+ SI opval = GET_H_AUXR (GET_H_CR (FLD (f_op_C)));
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LR_L_S12_) : /* lr$_L$F0 $RB,[$s12] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ {
+ SI opval = GET_H_AUXR (FLD (f_s12));
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LR_L_U6_) : /* lr$_L$F0 $RB,[$U6] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ {
+ SI opval = GET_H_AUXR (FLD (f_u6));
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SR_L_R_R___RC_) : /* sr$_L$F0 $RB,[$RC] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ {
+ SI opval = GET_H_CR (FLD (f_op_B));
+ SET_H_AUXR (GET_H_CR (FLD (f_op_C)), opval);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SR_L_S12_) : /* sr$_L$F0 $RB,[$s12] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ {
+ SI opval = GET_H_CR (FLD (f_op_B));
+ SET_H_AUXR (FLD (f_s12), opval);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SR_L_U6_) : /* sr$_L$F0 $RB,[$U6] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ {
+ SI opval = GET_H_CR (FLD (f_op_B));
+ SET_H_AUXR (FLD (f_u6), opval);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASL_L_R_R__RC) : /* asl$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASL_L_U6_) : /* asl$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (FLD (f_u6), FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (FLD (f_u6), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (FLD (f_u6), FLD (f_u6), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_ASL_S_GO) : /* asl$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ADDSI (tmp_C, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASR_L_R_R__RC) : /* asr$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SRASI (GET_H_CR (FLD (f_op_C)), 1);
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (GET_H_CR (FLD (f_op_C)), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASR_L_U6_) : /* asr$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SRASI (FLD (f_u6), 1);
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (FLD (f_u6), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_ASR_S_GO) : /* asr$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = SRASI (tmp_C, 1);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSR_L_R_R__RC) : /* lsr$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SRLSI (GET_H_CR (FLD (f_op_C)), 1);
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (GET_H_CR (FLD (f_op_C)), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSR_L_U6_) : /* lsr$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SRLSI (FLD (f_u6), 1);
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (FLD (f_u6), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_LSR_S_GO) : /* lsr$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = SRLSI (tmp_C, 1);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ROR_L_R_R__RC) : /* ror$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (SRLSI (GET_H_CR (FLD (f_op_C)), 1), SLLSI (GET_H_CR (FLD (f_op_C)), 31));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (GET_H_CR (FLD (f_op_C)), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ROR_L_U6_) : /* ror$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (SRLSI (FLD (f_u6), 1), SLLSI (FLD (f_u6), 31));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (FLD (f_u6), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RRC_L_R_R__RC) : /* rrc$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (SRLSI (GET_H_CR (FLD (f_op_C)), 1), SLLSI (ZEXTBISI (CPU (h_cbit)), 31));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (GET_H_CR (FLD (f_op_C)), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RRC_L_U6_) : /* rrc$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (SRLSI (FLD (f_u6), 1), SLLSI (ZEXTBISI (CPU (h_cbit)), 31));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (FLD (f_u6), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SEXB_L_R_R__RC) : /* sexb$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = EXTQISI ((GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SEXB_L_U6_) : /* sexb$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = EXTQISI ((FLD (f_u6)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_SEXB_S_GO) : /* sexb$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = EXTQISI ((tmp_C));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SEXW_L_R_R__RC) : /* sexw$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = EXTHISI ((GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SEXW_L_U6_) : /* sexw$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = EXTHISI ((FLD (f_u6)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_SEXW_S_GO) : /* sexw$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = EXTHISI ((tmp_C));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_EXTB_L_R_R__RC) : /* extb$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ZEXTQISI ((GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_EXTB_L_U6_) : /* extb$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ZEXTQISI ((FLD (f_u6)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_EXTB_S_GO) : /* extb$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ZEXTQISI ((tmp_C));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_EXTW_L_R_R__RC) : /* extw$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ZEXTHISI ((GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_EXTW_L_U6_) : /* extw$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ZEXTHISI ((FLD (f_u6)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_EXTW_S_GO) : /* extw$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ZEXTHISI ((tmp_C));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ABS_L_R_R__RC) : /* abs$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ABSSI (({ SI tmp_res;
+ tmp_res = GET_H_CR (FLD (f_op_C));
+; tmp_res; }));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI ((GET_H_CR (FLD (f_op_C))), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (GET_H_CR (FLD (f_op_C)), 0x80000000);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_vbit);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ABS_L_U6_) : /* abs$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ABSSI (({ SI tmp_res;
+ tmp_res = FLD (f_u6);
+; tmp_res; }));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI ((FLD (f_u6)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (FLD (f_u6), 0x80000000);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_vbit);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_ABS_S_GO) : /* abs$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ABSSI (({ SI tmp_res;
+ tmp_res = tmp_C;
+; tmp_res; }));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NOT_L_R_R__RC) : /* not$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = INVSI (GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NOT_L_U6_) : /* not$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = INVSI (FLD (f_u6));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_NOT_S_GO) : /* not$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = INVSI (tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RLC_L_R_R__RC) : /* rlc$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (SLLSI (GET_H_CR (FLD (f_op_C)), 1), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SRLSI (GET_H_CR (FLD (f_op_C)), 31);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RLC_L_U6_) : /* rlc$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (SLLSI (FLD (f_u6), 1), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SRLSI (FLD (f_u6), 31);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_EX_L_R_R__RC) : /* ex$_L$EXDi $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ SI tmp_dummy;
+ {
+ SI opval = GET_H_CR (FLD (f_op_B));
+ SETMEMSI (current_cpu, pc, GET_H_CR (FLD (f_op_C)), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+; GETMEMSI (current_cpu, pc, GET_H_CR (FLD (f_op_C))); });
+if (FLD (f_F)) {
+((void) 0); /*nop*/
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_EX_L_U6_) : /* ex$_L$EXDi $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ SI tmp_dummy;
+ {
+ SI opval = GET_H_CR (FLD (f_op_B));
+ SETMEMSI (current_cpu, pc, FLD (f_u6), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+; GETMEMSI (current_cpu, pc, FLD (f_u6)); });
+if (FLD (f_F)) {
+((void) 0); /*nop*/
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_NEG_S_GO) : /* neg$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = NEGSI (tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SWI) : /* swi */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+; /*clobber*/
+ {
+ USI opval = arc_trap (current_cpu, pc, 4, 0);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else if (0) {
+{
+; /*clobber*/
+ {
+ USI opval = arc_trap (current_cpu, pc, 4, 0);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+; /*clobber*/
+ {
+ USI opval = arc_trap (current_cpu, pc, 4, 0);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_TRAP_S) : /* trap$_S $trapnum */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_trap_s.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = arc_trap (current_cpu, pc, 2, FLD (f_trapnum));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+; /*clobber*/
+}
+}
+}
+ else if (0) {
+{
+ {
+ USI opval = arc_trap (current_cpu, pc, 2, FLD (f_trapnum));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+; /*clobber*/
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ {
+ USI opval = arc_trap (current_cpu, pc, 2, FLD (f_trapnum));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+; /*clobber*/
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BRK) : /* brk */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+arc_breakpoint (current_cpu, pc, 4);
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BRK_S) : /* brk_s */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+arc_breakpoint (current_cpu, pc, 2);
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASL_L_S12__RA_) : /* asl$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_s12), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_s12), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (32, ANDSI (FLD (f_s12), 31))), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASL_CCU6__RA_) : /* asl$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (32, ANDSI (FLD (f_u6), 31))), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASL_L_U6__RA_) : /* asl$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (32, ANDSI (FLD (f_u6), 31))), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASL_L_R_R__RA__RC) : /* asl$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (32, ANDSI (GET_H_CR (FLD (f_op_C)), 31))), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASL_CC__RA__RC) : /* asl$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (32, ANDSI (GET_H_CR (FLD (f_op_C)), 31))), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASL_S_CBU3) : /* asl$_S $R_c,$R_b,$u3 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u3);
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASL_S_SSB) : /* asl$_S $R_b,$R_b,$u5 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_ASLM_S_GO) : /* asl$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSR_L_S12__RA_) : /* lsr$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_s12), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_s12), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_s12), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSR_CCU6__RA_) : /* lsr$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_u6), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSR_L_U6__RA_) : /* lsr$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_u6), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSR_L_R_R__RA__RC) : /* lsr$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSR_CC__RA__RC) : /* lsr$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSR_S_SSB) : /* lsr$_S $R_b,$R_b,$u5 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_LSRM_S_GO) : /* lsr$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASR_L_S12__RA_) : /* asr$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_s12), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_s12), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_s12), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASR_CCU6__RA_) : /* asr$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_u6), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASR_L_U6__RA_) : /* asr$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_u6), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASR_L_R_R__RA__RC) : /* asr$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASR_CC__RA__RC) : /* asr$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASR_S_CBU3) : /* asr$_S $R_c,$R_b,$u3 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u3);
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASR_S_SSB) : /* asr$_S $R_b,$R_b,$u5 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_I16_GO_ASRM_S_GO) : /* asr$_S $R_b,$R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ROR_L_S12__RA_) : /* ror$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (RORSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_s12), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_s12), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_s12), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ROR_CCU6__RA_) : /* ror$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (RORSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_u6), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ROR_L_U6__RA_) : /* ror$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (RORSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_u6), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ROR_L_R_R__RA__RC) : /* ror$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (RORSI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ROR_CC__RA__RC) : /* ror$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (RORSI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MUL64_L_S12_) : /* mul64$_L$F1 $RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_s12)));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MUL64_CCU6_) : /* mul64$Qcondi$F1 $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6)));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MUL64_L_U6_) : /* mul64$_L$F1 $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6)));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MUL64_L_R_R__RC) : /* mul64$_L$F1 $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MUL64_CC__RC) : /* mul64$Qcondi$F1 $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MUL64_S_GO) : /* mul64$_S $R_b,$R_c */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (EXTSIDI (GET_H_CR16 (FLD (f_op__b))), EXTSIDI (GET_H_CR16 (FLD (f_op__c))));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULU64_L_S12_) : /* mulu64$_L$F1 $RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_s12)));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULU64_CCU6_) : /* mulu64$Qcondi$F1 $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_u6)));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULU64_L_U6_) : /* mulu64$_L$F1 $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_u6)));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULU64_L_R_R__RC) : /* mulu64$_L$F1 $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (GET_H_CR (FLD (f_op_C))));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULU64_CC__RC) : /* mulu64$Qcondi$F1 $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (GET_H_CR (FLD (f_op_C))));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDS_L_S12__RA_) : /* adds$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = ADDDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_s12)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDS_CCU6__RA_) : /* adds$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = ADDDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDS_L_U6__RA_) : /* adds$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = ADDDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDS_L_R_R__RA__RC) : /* adds$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = ADDDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDS_CC__RA__RC) : /* adds$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = ADDDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBS_L_S12__RA_) : /* subs$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_s12)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBS_CCU6__RA_) : /* subs$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBS_L_U6__RA_) : /* subs$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBS_L_R_R__RA__RC) : /* subs$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBS_CC__RA__RC) : /* subs$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_DIVAW_L_S12__RA_) : /* divaw$_L$F0 $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ USI tmp_tmp;
+ tmp_tmp = SLLSI (GET_H_CR (FLD (f_op_B)), 1);
+; ((EQSI (ANDSI (SUBSI (tmp_tmp, FLD (f_s12)), 0x80000000), 0)) ? (ADDSI (SUBSI (tmp_tmp, FLD (f_s12)), 1)) : (tmp_tmp)); }));
+if (FLD (f_F)) {
+((void) 0); /*nop*/
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_DIVAW_CCU6__RA_) : /* divaw$Qcondi$F0 $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ USI tmp_tmp;
+ tmp_tmp = SLLSI (GET_H_CR (FLD (f_op_B)), 1);
+; ((EQSI (ANDSI (SUBSI (tmp_tmp, FLD (f_u6)), 0x80000000), 0)) ? (ADDSI (SUBSI (tmp_tmp, FLD (f_u6)), 1)) : (tmp_tmp)); }));
+if (FLD (f_F)) {
+((void) 0); /*nop*/
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_DIVAW_L_U6__RA_) : /* divaw$_L$F0 $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ USI tmp_tmp;
+ tmp_tmp = SLLSI (GET_H_CR (FLD (f_op_B)), 1);
+; ((EQSI (ANDSI (SUBSI (tmp_tmp, FLD (f_u6)), 0x80000000), 0)) ? (ADDSI (SUBSI (tmp_tmp, FLD (f_u6)), 1)) : (tmp_tmp)); }));
+if (FLD (f_F)) {
+((void) 0); /*nop*/
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_DIVAW_L_R_R__RA__RC) : /* divaw$_L$F0 $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ USI tmp_tmp;
+ tmp_tmp = SLLSI (GET_H_CR (FLD (f_op_B)), 1);
+; ((EQSI (ANDSI (SUBSI (tmp_tmp, GET_H_CR (FLD (f_op_C))), 0x80000000), 0)) ? (ADDSI (SUBSI (tmp_tmp, GET_H_CR (FLD (f_op_C))), 1)) : (tmp_tmp)); }));
+if (FLD (f_F)) {
+((void) 0); /*nop*/
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_DIVAW_CC__RA__RC) : /* divaw$Qcondi$F0 $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ USI tmp_tmp;
+ tmp_tmp = SLLSI (GET_H_CR (FLD (f_op_B)), 1);
+; ((EQSI (ANDSI (SUBSI (tmp_tmp, GET_H_CR (FLD (f_op_C))), 0x80000000), 0)) ? (ADDSI (SUBSI (tmp_tmp, GET_H_CR (FLD (f_op_C))), 1)) : (tmp_tmp)); }));
+if (FLD (f_F)) {
+((void) 0); /*nop*/
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASLS_L_S12__RA_) : /* asls$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((FLD (f_s12)), 31)) ? (SLLDI (tmp_b, 31)) : (LTSI ((FLD (f_s12)), -31)) ? (SRADI (tmp_b, 31)) : (GESI ((FLD (f_s12)), 0)) ? (SLLDI (tmp_b, (FLD (f_s12)))) : (SRASI (GET_H_CR (FLD (f_op_B)), NEGSI ((FLD (f_s12)))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASLS_CCU6__RA_) : /* asls$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((FLD (f_u6)), 31)) ? (SLLDI (tmp_b, 31)) : (LTSI ((FLD (f_u6)), -31)) ? (SRADI (tmp_b, 31)) : (GESI ((FLD (f_u6)), 0)) ? (SLLDI (tmp_b, (FLD (f_u6)))) : (SRASI (GET_H_CR (FLD (f_op_B)), NEGSI ((FLD (f_u6)))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASLS_L_U6__RA_) : /* asls$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((FLD (f_u6)), 31)) ? (SLLDI (tmp_b, 31)) : (LTSI ((FLD (f_u6)), -31)) ? (SRADI (tmp_b, 31)) : (GESI ((FLD (f_u6)), 0)) ? (SLLDI (tmp_b, (FLD (f_u6)))) : (SRASI (GET_H_CR (FLD (f_op_B)), NEGSI ((FLD (f_u6)))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASLS_L_R_R__RA__RC) : /* asls$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((GET_H_CR (FLD (f_op_C))), 31)) ? (SLLDI (tmp_b, 31)) : (LTSI ((GET_H_CR (FLD (f_op_C))), -31)) ? (SRADI (tmp_b, 31)) : (GESI ((GET_H_CR (FLD (f_op_C))), 0)) ? (SLLDI (tmp_b, (GET_H_CR (FLD (f_op_C))))) : (SRASI (GET_H_CR (FLD (f_op_B)), NEGSI ((GET_H_CR (FLD (f_op_C))))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASLS_CC__RA__RC) : /* asls$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((GET_H_CR (FLD (f_op_C))), 31)) ? (SLLDI (tmp_b, 31)) : (LTSI ((GET_H_CR (FLD (f_op_C))), -31)) ? (SRADI (tmp_b, 31)) : (GESI ((GET_H_CR (FLD (f_op_C))), 0)) ? (SLLDI (tmp_b, (GET_H_CR (FLD (f_op_C))))) : (SRASI (GET_H_CR (FLD (f_op_B)), NEGSI ((GET_H_CR (FLD (f_op_C))))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASRS_L_S12__RA_) : /* asrs$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((FLD (f_s12)), 31)) ? (SRADI (tmp_b, 31)) : (LTSI ((FLD (f_s12)), -31)) ? (SLLDI (tmp_b, 31)) : (GESI ((FLD (f_s12)), 0)) ? (SRADI (tmp_b, (FLD (f_s12)))) : (SLLSI (GET_H_CR (FLD (f_op_B)), NEGSI ((FLD (f_s12)))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASRS_CCU6__RA_) : /* asrs$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((FLD (f_u6)), 31)) ? (SRADI (tmp_b, 31)) : (LTSI ((FLD (f_u6)), -31)) ? (SLLDI (tmp_b, 31)) : (GESI ((FLD (f_u6)), 0)) ? (SRADI (tmp_b, (FLD (f_u6)))) : (SLLSI (GET_H_CR (FLD (f_op_B)), NEGSI ((FLD (f_u6)))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASRS_L_U6__RA_) : /* asrs$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((FLD (f_u6)), 31)) ? (SRADI (tmp_b, 31)) : (LTSI ((FLD (f_u6)), -31)) ? (SLLDI (tmp_b, 31)) : (GESI ((FLD (f_u6)), 0)) ? (SRADI (tmp_b, (FLD (f_u6)))) : (SLLSI (GET_H_CR (FLD (f_op_B)), NEGSI ((FLD (f_u6)))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASRS_L_R_R__RA__RC) : /* asrs$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((GET_H_CR (FLD (f_op_C))), 31)) ? (SRADI (tmp_b, 31)) : (LTSI ((GET_H_CR (FLD (f_op_C))), -31)) ? (SLLDI (tmp_b, 31)) : (GESI ((GET_H_CR (FLD (f_op_C))), 0)) ? (SRADI (tmp_b, (GET_H_CR (FLD (f_op_C))))) : (SLLSI (GET_H_CR (FLD (f_op_B)), NEGSI ((GET_H_CR (FLD (f_op_C))))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASRS_CC__RA__RC) : /* asrs$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((GET_H_CR (FLD (f_op_C))), 31)) ? (SRADI (tmp_b, 31)) : (LTSI ((GET_H_CR (FLD (f_op_C))), -31)) ? (SLLDI (tmp_b, 31)) : (GESI ((GET_H_CR (FLD (f_op_C))), 0)) ? (SRADI (tmp_b, (GET_H_CR (FLD (f_op_C))))) : (SLLSI (GET_H_CR (FLD (f_op_B)), NEGSI ((GET_H_CR (FLD (f_op_C))))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDSDW_L_S12__RA_) : /* addsdw$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((FLD (f_s12)), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((FLD (f_s12)), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDSDW_CCU6__RA_) : /* addsdw$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((FLD (f_u6)), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((FLD (f_u6)), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDSDW_L_U6__RA_) : /* addsdw$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((FLD (f_u6)), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((FLD (f_u6)), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDSDW_L_R_R__RA__RC) : /* addsdw$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDSDW_CC__RA__RC) : /* addsdw$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBSDW_L_S12__RA_) : /* subsdw$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((FLD (f_s12)), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((FLD (f_s12)), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBSDW_CCU6__RA_) : /* subsdw$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((FLD (f_u6)), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((FLD (f_u6)), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBSDW_L_U6__RA_) : /* subsdw$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((FLD (f_u6)), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((FLD (f_u6)), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBSDW_L_R_R__RA__RC) : /* subsdw$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBSDW_CC__RA__RC) : /* subsdw$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SWAP_L_R_R__RC) : /* swap$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (RORSI (GET_H_CR (FLD (f_op_C)), 16));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SWAP_L_U6_) : /* swap$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (RORSI (FLD (f_u6), 16));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NORM_L_R_R__RC) : /* norm$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_val;
+ SI tmp_bits;
+ tmp_val = ((GESI ((GET_H_CR (FLD (f_op_C))), 0)) ? ((GET_H_CR (FLD (f_op_C)))) : (INVSI ((GET_H_CR (FLD (f_op_C))))));
+; tmp_bits = 31;
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 4), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 4));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 4));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 3), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 3));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 3));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 2), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 2));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 2));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 1), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 1));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 1));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 0), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 0));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 0));
+}
+; tmp_bits; }));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NORM_L_U6_) : /* norm$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_val;
+ SI tmp_bits;
+ tmp_val = ((GESI ((FLD (f_u6)), 0)) ? ((FLD (f_u6))) : (INVSI ((FLD (f_u6)))));
+; tmp_bits = 31;
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 4), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 4));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 4));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 3), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 3));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 3));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 2), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 2));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 2));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 1), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 1));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 1));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 0), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 0));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 0));
+}
+; tmp_bits; }));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (FLD (f_u6), 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (FLD (f_u6), 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RND16_L_R_R__RC) : /* rnd16$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (({ DI tmp_tmp;
+ tmp_tmp = ADDDI (EXTSIDI (32768), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }), 16));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RND16_L_U6_) : /* rnd16$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (({ DI tmp_tmp;
+ tmp_tmp = ADDDI (EXTSIDI (32768), EXTSIDI (FLD (f_u6)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }), 16));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ABSSW_L_R_R__RC) : /* abssw$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_tmp;
+ tmp_tmp = ABSSI (EXTHISI ((GET_H_CR (FLD (f_op_C)))));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ABSSW_L_U6_) : /* abssw$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_tmp;
+ tmp_tmp = ABSSI (EXTHISI ((FLD (f_u6))));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ABSS_L_R_R__RC) : /* abss$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (((GESI ((GET_H_CR (FLD (f_op_C))), 0)) ? (GET_H_CR (FLD (f_op_C))) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (0), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }))));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ABSS_L_U6_) : /* abss$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (((GESI ((FLD (f_u6)), 0)) ? (FLD (f_u6)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (0), EXTSIDI (FLD (f_u6)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }))));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NEGSW_L_R_R__RC) : /* negsw$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_tmp;
+ tmp_tmp = EXTHISI ((GET_H_CR (FLD (f_op_C))));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NEGSW_L_U6_) : /* negsw$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_tmp;
+ tmp_tmp = EXTHISI ((FLD (f_u6)));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NEGS_L_R_R__RC) : /* negs$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (0), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NEGS_L_U6_) : /* negs$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (0), EXTSIDI (FLD (f_u6)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NORMW_L_R_R__RC) : /* normw$_L$F $RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_val;
+ SI tmp_bits;
+ tmp_val = ((GESI (ORSI (SLLSI (GET_H_CR (FLD (f_op_C)), 16), ANDSI (GET_H_CR (FLD (f_op_C)), 65535)), 0)) ? (ORSI (SLLSI (GET_H_CR (FLD (f_op_C)), 16), ANDSI (GET_H_CR (FLD (f_op_C)), 65535))) : (INVSI (ORSI (SLLSI (GET_H_CR (FLD (f_op_C)), 16), ANDSI (GET_H_CR (FLD (f_op_C)), 65535)))));
+; tmp_bits = 31;
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 4), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 4));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 4));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 3), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 3));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 3));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 2), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 2));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 2));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 1), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 1));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 1));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 0), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 0));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 0));
+}
+; tmp_bits; }));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NORMW_L_U6_) : /* normw$_L$F $RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_val;
+ SI tmp_bits;
+ tmp_val = ((GESI (ORSI (SLLSI (FLD (f_u6), 16), ANDSI (FLD (f_u6), 65535)), 0)) ? (ORSI (SLLSI (FLD (f_u6), 16), ANDSI (FLD (f_u6), 65535))) : (INVSI (ORSI (SLLSI (FLD (f_u6), 16), ANDSI (FLD (f_u6), 65535)))));
+; tmp_bits = 31;
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 4), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 4));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 4));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 3), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 3));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 3));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 2), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 2));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 2));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 1), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 1));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 1));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 0), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 0));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 0));
+}
+; tmp_bits; }));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NOP_S) : /* nop_s */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_UNIMP_S) : /* unimp_s */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+cgen_rtx_error (current_cpu, "invalid insn");
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_POP_S_B) : /* pop$_S $R_b */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ SI opval = GETMEMSI (current_cpu, pc, GET_H_SP ());
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (GET_H_SP (), 4);
+ SET_H_SP (, opval);
+ TRACE_RESULT (current_cpu, abuf, "sp", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_POP_S_BLINK) : /* pop$_S $R31 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ SI opval = GETMEMSI (current_cpu, pc, GET_H_SP ());
+ SET_H_R31 (, opval);
+ TRACE_RESULT (current_cpu, abuf, "r31", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (GET_H_SP (), 4);
+ SET_H_SP (, opval);
+ TRACE_RESULT (current_cpu, abuf, "sp", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_PUSH_S_B) : /* push$_S $R_b */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ SI opval = ADDSI (GET_H_SP (), -4);
+ SET_H_SP (, opval);
+ TRACE_RESULT (current_cpu, abuf, "sp", 'x', opval);
+ }
+ {
+ SI opval = GET_H_CR16 (FLD (f_op__b));
+ SETMEMSI (current_cpu, pc, GET_H_SP (), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_PUSH_S_BLINK) : /* push$_S $R31 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ SI opval = ADDSI (GET_H_SP (), -4);
+ SET_H_SP (, opval);
+ TRACE_RESULT (current_cpu, abuf, "sp", 'x', opval);
+ }
+ {
+ SI opval = GET_H_R31 ();
+ SETMEMSI (current_cpu, pc, GET_H_SP (), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULLW_L_S12__RA_) : /* mullw$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_s12), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULLW_CCU6__RA_) : /* mullw$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_u6), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULLW_L_U6__RA_) : /* mullw$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_u6), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULLW_L_R_R__RA__RC) : /* mullw$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULLW_CC__RA__RC) : /* mullw$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACLW_L_S12__RA_) : /* maclw$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ SI tmp_SItmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_s12), 65535))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; {
+ BI opval = ANDBI (CPU (h_vbit), SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; if (NEBI (CPU (h_vbit), 0)) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; tmp_SItmp = ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp));
+; tmp_cur_s1bit = ORBI (tmp_cur_s1bit, CPU (h_vbit));
+; tmp_SItmp; });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACLW_CCU6__RA_) : /* maclw$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ SI tmp_SItmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_u6), 65535))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; {
+ BI opval = ANDBI (CPU (h_vbit), SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; if (NEBI (CPU (h_vbit), 0)) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; tmp_SItmp = ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp));
+; tmp_cur_s1bit = ORBI (tmp_cur_s1bit, CPU (h_vbit));
+; tmp_SItmp; });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACLW_L_U6__RA_) : /* maclw$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ SI tmp_SItmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_u6), 65535))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; {
+ BI opval = ANDBI (CPU (h_vbit), SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; if (NEBI (CPU (h_vbit), 0)) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; tmp_SItmp = ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp));
+; tmp_cur_s1bit = ORBI (tmp_cur_s1bit, CPU (h_vbit));
+; tmp_SItmp; });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACLW_L_R_R__RA__RC) : /* maclw$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ SI tmp_SItmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), 65535))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; {
+ BI opval = ANDBI (CPU (h_vbit), SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; if (NEBI (CPU (h_vbit), 0)) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; tmp_SItmp = ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp));
+; tmp_cur_s1bit = ORBI (tmp_cur_s1bit, CPU (h_vbit));
+; tmp_SItmp; });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACLW_CC__RA__RC) : /* maclw$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ SI tmp_SItmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), 65535))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; {
+ BI opval = ANDBI (CPU (h_vbit), SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; if (NEBI (CPU (h_vbit), 0)) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; tmp_SItmp = ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp));
+; tmp_cur_s1bit = ORBI (tmp_cur_s1bit, CPU (h_vbit));
+; tmp_SItmp; });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACHLW_L_S12__RA_) : /* machlw$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_s12), -65536))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = ANDBI (CPU (h_vbit), XORDI (tmp_old, tmp_tmp));
+; if (tmp_cur_s1bit) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACHLW_CCU6__RA_) : /* machlw$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_u6), -65536))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = ANDBI (CPU (h_vbit), XORDI (tmp_old, tmp_tmp));
+; if (tmp_cur_s1bit) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACHLW_L_U6__RA_) : /* machlw$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_u6), -65536))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = ANDBI (CPU (h_vbit), XORDI (tmp_old, tmp_tmp));
+; if (tmp_cur_s1bit) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACHLW_L_R_R__RA__RC) : /* machlw$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), -65536))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = ANDBI (CPU (h_vbit), XORDI (tmp_old, tmp_tmp));
+; if (tmp_cur_s1bit) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACHLW_CC__RA__RC) : /* machlw$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), -65536))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = ANDBI (CPU (h_vbit), XORDI (tmp_old, tmp_tmp));
+; if (tmp_cur_s1bit) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULULW_L_S12__RA_) : /* mululw$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (FLD (f_s12), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULULW_CCU6__RA_) : /* mululw$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (FLD (f_u6), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULULW_L_U6__RA_) : /* mululw$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (FLD (f_u6), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULULW_L_R_R__RA__RC) : /* mululw$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULULW_CC__RA__RC) : /* mululw$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACHULW_L_S12__RA_) : /* machulw$_L$F $RB,$RB,$s12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (FLD (f_s12), -65536))));
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = (GTUDI (tmp_old, tmp_tmp)) ? (( tmp_tmp = -1, 1)) : (0);
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACHULW_CCU6__RA_) : /* machulw$Qcondi$F $RB,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (FLD (f_u6), -65536))));
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = (GTUDI (tmp_old, tmp_tmp)) ? (( tmp_tmp = -1, 1)) : (0);
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACHULW_L_U6__RA_) : /* machulw$_L$F $RA,$RB,$U6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (FLD (f_u6), -65536))));
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = (GTUDI (tmp_old, tmp_tmp)) ? (( tmp_tmp = -1, 1)) : (0);
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACHULW_L_R_R__RA__RC) : /* machulw$_L$F $RA,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), -65536))));
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = (GTUDI (tmp_old, tmp_tmp)) ? (( tmp_tmp = -1, 1)) : (0);
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACHULW_CC__RA__RC) : /* machulw$Qcondi$F $RB,$RB,$RC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), -65536))));
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = (GTUDI (tmp_old, tmp_tmp)) ? (( tmp_tmp = -1, 1)) : (0);
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CURRENT_LOOP_END) : /* */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDBI (EQSI (pc, GET_H_AUXR (((UINT) 3))), NOTBI (CPU (h_lbit)))) {
+{
+ {
+ SI opval = ADDSI (GET_H_CR (((UINT) 60)), -1);
+ SET_H_CR (((UINT) 60), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GET_H_CR (((UINT) 60))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (GET_H_AUXR (((UINT) 2)), 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = GET_H_AUXR (((UINT) 2));
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CURRENT_LOOP_END_AFTER_BRANCH) : /* */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (
+#ifdef SEM_IN_SWITCH
+pbb_br_type != SEM_BRANCH_UNTAKEN
+#else
+CPU_PBB_BR_NPC (current_cpu) != SEM_BRANCH_UNTAKEN
+#endif
+) {
+
+#ifdef SEM_IN_SWITCH
+npc = pbb_br_npc; br_type = pbb_br_type;
+#else
+npc = CPU_PBB_BR_NPC (current_cpu); br_type = CPU_PBB_BR_TYPE (current_cpu);
+#endif
+}
+ else if (ANDBI (EQSI (pc, GET_H_AUXR (((UINT) 3))), NOTBI (CPU (h_lbit)))) {
+{
+ {
+ SI opval = ADDSI (GET_H_CR (((UINT) 60)), -1);
+ SET_H_CR (((UINT) 60), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GET_H_CR (((UINT) 60))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (GET_H_AUXR (((UINT) 2)), 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = GET_H_AUXR (((UINT) 2));
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ARC600_CURRENT_LOOP_END_AFTER_BRANCH) : /* */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (
+#ifdef SEM_IN_SWITCH
+pbb_br_type != SEM_BRANCH_UNTAKEN
+#else
+CPU_PBB_BR_NPC (current_cpu) != SEM_BRANCH_UNTAKEN
+#endif
+) {
+{
+
+#ifdef SEM_IN_SWITCH
+npc = pbb_br_npc; br_type = pbb_br_type;
+#else
+npc = CPU_PBB_BR_NPC (current_cpu); br_type = CPU_PBB_BR_TYPE (current_cpu);
+#endif
+ {
+ SI opval = ADDSI (GET_H_CR (((UINT) 60)), -1);
+ SET_H_CR (((UINT) 60), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+ else if (ANDBI (EQSI (pc, GET_H_AUXR (((UINT) 3))), NOTBI (CPU (h_lbit)))) {
+{
+ {
+ SI opval = ADDSI (GET_H_CR (((UINT) 60)), -1);
+ SET_H_CR (((UINT) 60), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GET_H_CR (((UINT) 60))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (GET_H_AUXR (((UINT) 2)), 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = GET_H_AUXR (((UINT) 2));
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+
+ }
+ ENDSWITCH (sem) /* End of semantic switch. */
+
+ /* At this point `vpc' contains the next insn to execute. */
+}
+
+#undef DEFINE_SWITCH
+#endif /* DEFINE_SWITCH */
diff --git a/sim/arc/sem7.c b/sim/arc/sem7.c
new file mode 100644
index 0000000..1ab771e
--- /dev/null
+++ b/sim/arc/sem7.c
@@ -0,0 +1,34008 @@
+/* Simulator instruction semantics for arc700f.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2007 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#define WANT_CPU arc700f
+#define WANT_CPU_ARC700F
+
+#include "sim-main.h"
+#include "cgen-mem.h"
+#include "cgen-ops.h"
+
+#undef GET_ATTR
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
+#else
+#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr)
+#endif
+
+/* This is used so that we can compile two copies of the semantic code,
+ one with full feature support and one without that runs fast(er).
+ FAST_P, when desired, is defined on the command line, -DFAST_P=1. */
+#if FAST_P
+#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_semf_,fn)
+#undef TRACE_RESULT
+#define TRACE_RESULT(cpu, abuf, name, type, val)
+#else
+#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_sem_,fn)
+#endif
+
+/* x-invalid: --invalid-- */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,x_invalid) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+ /* Update the recorded pc in the cpu state struct.
+ Only necessary for WITH_SCACHE case, but to avoid the
+ conditional compilation .... */
+ SET_H_PC (pc);
+ /* Virtual insns have zero size. Overwrite vpc with address of next insn
+ using the default-insn-bitsize spec. When executing insns in parallel
+ we may want to queue the fault and continue execution. */
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+ vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* x-after: --after-- */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,x_after) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_ARC700F
+ arc700f_pbb_after (current_cpu, sem_arg);
+#endif
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* x-before: --before-- */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,x_before) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_ARC700F
+ arc700f_pbb_before (current_cpu, sem_arg);
+#endif
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* x-cti-chain: --cti-chain-- */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_ARC700F
+#ifdef DEFINE_SWITCH
+ vpc = arc700f_pbb_cti_chain (current_cpu, sem_arg,
+ pbb_br_type, pbb_br_npc);
+ BREAK (sem);
+#else
+ /* FIXME: Allow provision of explicit ifmt spec in insn spec. */
+ vpc = arc700f_pbb_cti_chain (current_cpu, sem_arg,
+ CPU_PBB_BR_TYPE (current_cpu),
+ CPU_PBB_BR_NPC (current_cpu));
+#endif
+#endif
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* x-chain: --chain-- */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,x_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_ARC700F
+ vpc = arc700f_pbb_chain (current_cpu, sem_arg);
+#ifdef DEFINE_SWITCH
+ BREAK (sem);
+#endif
+#endif
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* x-begin: --begin-- */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_ARC700F
+#if defined DEFINE_SWITCH || defined FAST_P
+ /* In the switch case FAST_P is a constant, allowing several optimizations
+ in any called inline functions. */
+ vpc = arc700f_pbb_begin (current_cpu, FAST_P);
+#else
+#if 0 /* cgen engine can't handle dynamic fast/full switching yet. */
+ vpc = arc700f_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
+#else
+ vpc = arc700f_pbb_begin (current_cpu, 0);
+#endif
+#endif
+#endif
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* b_s: b$i2cond $label10 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,b_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_b_s.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GET_H_I2COND (FLD (f_cond_i2))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = FLD (i_label10);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = FLD (i_label10);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = FLD (i_label10);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* bcc_s: b$i3cond$_S $label7 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,bcc_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bcc_s.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GET_H_I3COND (FLD (f_cond_i3))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = FLD (i_label7);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = FLD (i_label7);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = FLD (i_label7);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* brcc_s: br$RccS$_S $R_b,0,$label8 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,brcc_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_brcc_s.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if ((FLD (f_brscond) == 0) ? (EQSI (GET_H_CR16 (FLD (f_op__b)), 0)) : (FLD (f_brscond) == 1) ? (NESI (GET_H_CR16 (FLD (f_op__b)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = FLD (i_label8);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = FLD (i_label8);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = FLD (i_label8);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* bcc_l: b$Qcondb$_L $label21 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,bcc_l) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bcc_l.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+((void) 0); /*nop*/
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = FLD (i_label21);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = FLD (i_label21);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = FLD (i_label21);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* bcc_l.d: b$Qcondb$_L.d $label21 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,bcc_l_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bcc_l.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+((void) 0); /*nop*/
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (i_label21);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else if (1) {
+{
+ {
+ USI opval = FLD (i_label21);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ {
+ USI opval = FLD (i_label21);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* b_l: b$uncondb$_L $label25 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,b_l) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_b_l.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = FLD (i_label25);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = FLD (i_label25);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = FLD (i_label25);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* b_l.d: b$uncondb$_L.d $label25 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,b_l_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_b_l.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (i_label25);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else if (1) {
+{
+ {
+ USI opval = FLD (i_label25);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ {
+ USI opval = FLD (i_label25);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* brcc_RC: b$Rcc $RB,$RC,$label9 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,brcc_RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_brcc_RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* brcc_RC.d: b$Rcc.d $RB,$RC,$label9 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,brcc_RC_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_brcc_RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+{
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+{
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+{
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* brcc_U6: b$Rcc $RB,$U6,$label9 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,brcc_U6) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_brcc_U6.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* brcc_U6.d: b$Rcc.d $RB,$U6,$label9 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,brcc_U6_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_brcc_U6.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+{
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+{
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_condition;
+ SI tmp_B;
+ SI tmp_C;
+ tmp_condition = FLD (f_brcond);
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+if ((tmp_condition == CONDBR_REQ) ? (EQSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RNE) ? (NESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLT) ? (LTSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RGE) ? (GESI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RLO) ? (LTUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_RHS) ? (GEUSI (tmp_B, tmp_C)) : (tmp_condition == CONDBR_BIT0) ? (EQSI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : (tmp_condition == CONDBR_BIT1) ? (NESI (ANDSI (tmp_B, SLLSI (1, tmp_C)), 0)) : ((cgen_rtx_error (current_cpu, "unreachable - put in because of parser error"), 0))) {
+{
+ {
+ USI opval = FLD (i_label9);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* bl_s: bl$uncondj$_S $label13a */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,bl_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bl_s.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ {
+ SI opval = ADDSI (pc, 2);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label13a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else if (0) {
+{
+ {
+ SI opval = ADDSI (pc, 2);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label13a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ {
+ SI opval = ADDSI (pc, 2);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label13a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* blcc: bl$Qcondj$_L $label21 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,blcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_blcc.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+((void) 0); /*nop*/
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label21a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else if (0) {
+{
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label21a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label21a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* blcc.d: bl$Qcondj$_L.d $label21 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,blcc_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_blcc.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+((void) 0); /*nop*/
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+{
+ {
+ USI opval = FLD (i_label21a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+{
+ {
+ USI opval = FLD (i_label21a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+{
+ {
+ USI opval = FLD (i_label21a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* bl: bl$uncondj$_L $label25a */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,bl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bl.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label25a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else if (0) {
+{
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label25a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_label25a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* bl.d: bl$uncondj$_L.d $label25a */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,bl_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bl.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (i_label25a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (i_label25a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (i_label25a);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* ld_abs: ld$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ld_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ld$_AW_abs: ld$_AW$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ld__AW_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ld.ab_abs: ld.ab$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ld_ab_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ld.as_abs: ld.as$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ld_as_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s9), 2));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ld_abc: ld$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ld_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ld$_AW_abc: ld$_AW$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ld__AW_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ld.ab_abc: ld.ab$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ld_ab_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ld.as_abc: ld.as$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ld_as_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 2));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ld_s_abc: ld$_S $R_a,[$R_b,$R_c] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ld_s_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), GET_H_CR16 (FLD (f_op__c)));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR16 (FLD (f_op__a), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ld_s_abu: ld$_S $R_c,[$R_b,$sc_u5_] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ld_s_abu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), FLD (f_u5x4));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ld_s_absp: ld$_S $R_b,[$SP,$u5x4] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ld_s_absp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_SP (), FLD (f_u5x4));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ld_s_gprel: ld$_S $R_b,[$GP,$sc_s9_] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ld_s_gprel) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_gprel.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_GP (), FLD (f_s9x4));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_R0 (, opval);
+ TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ld_s_pcrel: ld$_S $R_b,[$PCL,$u8x4] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ld_s_pcrel) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_pcrel.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (ANDSI (pc, -4), FLD (f_u8x4));
+ {
+ SI opval = GETMEMSI (current_cpu, pc, tmp_eaddr);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb_abs: ldb$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ldb_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb$_AW_abs: ldb$_AW$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ldb__AW_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb.ab_abs: ldb.ab$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ldb_ab_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb.as_abs: ldb.as$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ldb_as_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), (cgen_rtx_error (current_cpu, "invalid insn"), 0));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb_abc: ldb$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ldb_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb$_AW_abc: ldb$_AW$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ldb__AW_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb.ab_abc: ldb.ab$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ldb_ab_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb.as_abc: ldb.as$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ldb_as_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), (cgen_rtx_error (current_cpu, "invalid insn"), 0));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb_s_abc: ldb$_S $R_a,[$R_b,$R_c] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ldb_s_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), GET_H_CR16 (FLD (f_op__c)));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR16 (FLD (f_op__a), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb_s_abu: ldb$_S $R_c,[$R_b,$sc_u5b] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ldb_s_abu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), FLD (f_u5));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb_s_absp: ldb$_S $R_b,[$SP,$u5x4] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ldb_s_absp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_SP (), FLD (f_u5x4));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb_s_gprel: ldb$_S $R_b,[$GP,$sc_s9b] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ldb_s_gprel) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_gprel.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_GP (), FLD (f_s9x1));
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_R0 (, opval);
+ TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb.x_abs: ldb.x$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ldb_x_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb$_AW.x_abs: ldb$_AW.x$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ldb__AW_x_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb.ab.x_abs: ldb.ab.x$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ldb_ab_x_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb.as.x_abs: ldb.as.x$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ldb_as_x_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), (cgen_rtx_error (current_cpu, "invalid insn"), 0));
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb.x_abc: ldb.x$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ldb_x_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb$_AW.x_abc: ldb$_AW.x$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ldb__AW_x_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb.ab.x_abc: ldb.ab.x$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ldb_ab_x_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb.as.x_abc: ldb.as.x$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ldb_as_x_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), (cgen_rtx_error (current_cpu, "invalid insn"), 0));
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw_abs: ldw$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ldw_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw$_AW_abs: ldw$_AW$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ldw__AW_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw.ab_abs: ldw.ab$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ldw_ab_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw.as_abs: ldw.as$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ldw_as_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s9), 1));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw_abc: ldw$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ldw_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw$_AW_abc: ldw$_AW$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ldw__AW_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw.ab_abc: ldw.ab$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ldw_ab_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw.as_abc: ldw.as$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ldw_as_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 1));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw_s_abc: ldw$_S $R_a,[$R_b,$R_c] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ldw_s_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), GET_H_CR16 (FLD (f_op__c)));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR16 (FLD (f_op__a), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw_s_abu: ldw$_S $R_c,[$R_b,$sc_u5w] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ldw_s_abu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldw_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), FLD (f_u5x2));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw_s_gprel: ldw$_S $R_b,[$GP,$sc_s9w] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ldw_s_gprel) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldw_s_gprel.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_GP (), FLD (f_s9x2));
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_R0 (, opval);
+ TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw.x_abs: ldw.x$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ldw_x_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw$_AW.x_abs: ldw$_AW.x$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ldw__AW_x_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw.ab.x_abs: ldw.ab.x$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ldw_ab_x_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw.as.x_abs: ldw.as.x$LDODi $RA,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ldw_as_x_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s9), 1));
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw.x_abc: ldw.x$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ldw_x_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw$_AW.x_abc: ldw$_AW.x$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ldw__AW_x_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw.ab.x_abc: ldw.ab.x$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ldw_ab_x_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw.as.x_abc: ldw.as.x$LDRDi $RA,[$RB,$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ldw_as_x_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 1));
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw_s.x_abu: ldw$_S.x $R_c,[$R_b,$sc_u5w] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ldw_s_x_abu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldw_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), FLD (f_u5x2));
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, tmp_eaddr));
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* st_abs: st$STODi $RC,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,st_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMSI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* st$_AW_abs: st$_AW$STODi $RC,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,st__AW_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMSI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* st.ab_abs: st.ab$STODi $RC,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,st_ab_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ SI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMSI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* st.as_abs: st.as$STODi $RC,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,st_as_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s9), 2));
+ {
+ SI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMSI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* st_s_abu: st$_S $R_c,[$R_b,$sc_u5_] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,st_s_abu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), FLD (f_u5x4));
+ {
+ SI opval = GET_H_CR16 (FLD (f_op__c));
+ SETMEMSI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* st_s_absp: st$_S $R_b,[$SP,$u5x4] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,st_s_absp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_SP (), FLD (f_u5x4));
+ {
+ SI opval = GET_H_CR16 (FLD (f_op__b));
+ SETMEMSI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* stb_abs: stb$STODi $RC,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,stb_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ QI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMQI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* stb$_AW_abs: stb$_AW$STODi $RC,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,stb__AW_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ QI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMQI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* stb.ab_abs: stb.ab$STODi $RC,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,stb_ab_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ QI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMQI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* stb.as_abs: stb.as$STODi $RC,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,stb_as_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), (cgen_rtx_error (current_cpu, "invalid insn"), 0));
+ {
+ QI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMQI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* stb_s_abu: stb$_S $R_c,[$R_b,$sc_u5b] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,stb_s_abu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), FLD (f_u5));
+ {
+ QI opval = GET_H_CR16 (FLD (f_op__c));
+ SETMEMQI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* stb_s_absp: stb$_S $R_b,[$SP,$u5x4] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,stb_s_absp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_SP (), FLD (f_u5x4));
+ {
+ QI opval = GET_H_CR16 (FLD (f_op__b));
+ SETMEMQI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* stw_abs: stw$STODi $RC,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,stw_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ HI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMHI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* stw$_AW_abs: stw$_AW$STODi $RC,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,stw__AW_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ {
+ SI opval = tmp_eaddr;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ HI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMHI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* stw.ab_abs: stw.ab$STODi $RC,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,stw_ab_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_sum;
+ SI tmp_eaddr;
+ tmp_sum = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s9));
+ tmp_eaddr = GET_H_CR (FLD (f_op_B));
+ {
+ HI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMHI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ SI opval = tmp_sum;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* stw.as_abs: stw.as$STODi $RC,[$RB,$s9] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,stw_as_abs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s9), 1));
+ {
+ HI opval = GET_H_CR (FLD (f_op_C));
+ SETMEMHI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* stw_s_abu: stw$_S $R_c,[$R_b,$sc_u5w] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,stw_s_abu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldw_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_eaddr;
+ tmp_eaddr = ADDSI (GET_H_CR16 (FLD (f_op__b)), FLD (f_u5x2));
+ {
+ HI opval = GET_H_CR16 (FLD (f_op__c));
+ SETMEMHI (current_cpu, pc, tmp_eaddr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* add_L_s12 $RA,: add$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,add_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add_ccu6 $RA,: add$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,add_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add_L_u6 $RA,: add$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,add_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add_L_r_r $RA,$RC: add$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,add_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add_cc $RA,$RC: add$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,add_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add_s_abc: add$_S $R_a,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,add_s_abc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abc.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ADDSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__a), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* add_s_cbu3: add$_S $R_c,$R_b,$u3 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,add_s_cbu3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u3);
+ {
+ SI opval = ADDSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* add_s_mcah: add$_S $R_b,$R_b,$Rh */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,add_s_mcah) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+{
+if (EQSI (FLD (f_op_h), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 2));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (2, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_h), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR (FLD (f_op_h));
+ {
+ SI opval = ADDSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* add_s_absp: add$_S $R_b,$SP,$u5x4 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,add_s_absp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_SP ();
+ tmp_C = FLD (f_u5x4);
+ {
+ SI opval = ADDSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* add_s_asspsp: add$_S $SP,$SP,$u5x4 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,add_s_asspsp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_SP ();
+ tmp_C = FLD (f_u5x4);
+ {
+ SI opval = ADDSI (tmp_B, tmp_C);
+ SET_H_SP (, opval);
+ TRACE_RESULT (current_cpu, abuf, "sp", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* add_s_gp: add$_S $R0,$GP,$s9x4 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,add_s_gp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_gprel.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_GP ();
+ tmp_C = FLD (f_s9x4);
+ {
+ SI opval = ADDSI (tmp_B, tmp_C);
+ SET_H_R0 (, opval);
+ TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* add_s_r_u7: add$_S $R_b,$R_b,$u7 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,add_s_r_u7) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_r_u7.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u7);
+ {
+ SI opval = ADDSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* adc_L_s12 $RA,: adc$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,adc_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDCSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* adc_ccu6 $RA,: adc$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,adc_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDCSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* adc_L_u6 $RA,: adc$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,adc_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDCSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* adc_L_r_r $RA,$RC: adc$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,adc_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDCSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* adc_cc $RA,$RC: adc$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,adc_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDCSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub_L_s12 $RA,: sub$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,sub_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub_ccu6 $RA,: sub$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,sub_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub_L_u6 $RA,: sub$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,sub_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub_L_r_r $RA,$RC: sub$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,sub_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub_cc $RA,$RC: sub$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,sub_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub_s_cbu3: sub$_S $R_c,$R_b,$u3 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,sub_s_cbu3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u3);
+ {
+ SI opval = SUBSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_SUB_s_go: sub$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,I16_GO_SUB_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = SUBSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* sub_s_go_sub_ne: sub$_S $NE$R_b,$R_b,$R_b */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,sub_s_go_sub_ne) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQBI (CPU (h_zbit), 0)) {
+ {
+ SI opval = 0;
+ SET_H_CR16 (FLD (f_op__b), opval);
+ written |= (1 << 1);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub_s_ssb: sub$_S $R_b,$R_b,$u5 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,sub_s_ssb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ {
+ SI opval = SUBSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* sub_s_asspsp: sub$_S $SP,$SP,$u5x4 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,sub_s_asspsp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_SP ();
+ tmp_C = FLD (f_u5x4);
+ {
+ SI opval = SUBSI (tmp_B, tmp_C);
+ SET_H_SP (, opval);
+ TRACE_RESULT (current_cpu, abuf, "sp", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* sbc_L_s12 $RA,: sbc$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,sbc_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBCSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sbc_ccu6 $RA,: sbc$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,sbc_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBCSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sbc_L_u6 $RA,: sbc$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,sbc_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBCSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sbc_L_r_r $RA,$RC: sbc$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,sbc_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBCSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sbc_cc $RA,$RC: sbc$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,sbc_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBCSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* and_L_s12 $RA,: and$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,and_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* and_ccu6 $RA,: and$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,and_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* and_L_u6 $RA,: and$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,and_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* and_L_r_r $RA,$RC: and$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,and_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* and_cc $RA,$RC: and$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,and_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_AND_s_go: and$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,I16_GO_AND_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ANDSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* or_L_s12 $RA,: or$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,or_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* or_ccu6 $RA,: or$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,or_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* or_L_u6 $RA,: or$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,or_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* or_L_r_r $RA,$RC: or$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,or_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* or_cc $RA,$RC: or$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,or_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_OR_s_go: or$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,I16_GO_OR_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ORSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* bic_L_s12 $RA,: bic$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,bic_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (FLD (f_s12)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bic_ccu6 $RA,: bic$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,bic_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (FLD (f_u6)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bic_L_u6 $RA,: bic$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,bic_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (FLD (f_u6)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bic_L_r_r $RA,$RC: bic$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,bic_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bic_cc $RA,$RC: bic$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,bic_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_BIC_s_go: bic$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,I16_GO_BIC_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ANDSI (tmp_B, INVSI (tmp_C));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* xor_L_s12 $RA,: xor$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,xor_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* xor_ccu6 $RA,: xor$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,xor_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* xor_L_u6 $RA,: xor$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,xor_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* xor_L_r_r $RA,$RC: xor$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,xor_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* xor_cc $RA,$RC: xor$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,xor_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_XOR_s_go: xor$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,I16_GO_XOR_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = XORSI (tmp_B, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* max_L_s12 $RA,: max$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,max_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (GTSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12))) ? (GET_H_CR (FLD (f_op_B))) : (FLD (f_s12));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = GESI (FLD (f_s12), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* max_ccu6 $RA,: max$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,max_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (GTSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6))) ? (GET_H_CR (FLD (f_op_B))) : (FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = GESI (FLD (f_u6), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* max_L_u6 $RA,: max$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,max_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (GTSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6))) ? (GET_H_CR (FLD (f_op_B))) : (FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = GESI (FLD (f_u6), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* max_L_r_r $RA,$RC: max$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,max_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (GTSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)))) ? (GET_H_CR (FLD (f_op_B))) : (GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = GESI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* max_cc $RA,$RC: max$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,max_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (GTSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)))) ? (GET_H_CR (FLD (f_op_B))) : (GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = GESI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* min_L_s12 $RA,: min$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,min_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (LTSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12))) ? (GET_H_CR (FLD (f_op_B))) : (FLD (f_s12));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = LESI (FLD (f_s12), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* min_ccu6 $RA,: min$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,min_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (LTSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6))) ? (GET_H_CR (FLD (f_op_B))) : (FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = LESI (FLD (f_u6), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* min_L_u6 $RA,: min$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,min_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (LTSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6))) ? (GET_H_CR (FLD (f_op_B))) : (FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = LESI (FLD (f_u6), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* min_L_r_r $RA,$RC: min$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,min_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (LTSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)))) ? (GET_H_CR (FLD (f_op_B))) : (GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = LESI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* min_cc $RA,$RC: min$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,min_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (LTSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)))) ? (GET_H_CR (FLD (f_op_B))) : (GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = LESI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mov_L_s12 : mov$_L$F $RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mov_L_s12_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+ tmp_result = FLD (f_s12);
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GTSI (FLD (f_F), 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mov_ccu6 : mov$Qcondi$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mov_ccu6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+((void) 0); /*nop*/
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+ tmp_result = FLD (f_u6);
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GTSI (FLD (f_F), 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 5);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mov_L_u6 : mov$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mov_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+ tmp_result = FLD (f_u6);
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GTSI (FLD (f_F), 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mov_L_r_r $RC: mov$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mov_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = GET_H_CR (FLD (f_op_C));
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GTSI (FLD (f_F), 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mov_cc $RC: mov$Qcondi$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mov_cc__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+ tmp_result = GET_H_CR (FLD (f_op_C));
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GTSI (FLD (f_F), 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mov_s_mcah: mov$_S $R_b,$Rh */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mov_s_mcah) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_h), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 2));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (2, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_h), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = GET_H_CR (FLD (f_op_h));
+ {
+ SI opval = tmp_result;
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+if (GTSI (-1, 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mov_s_mcahb: mov$_S $Rh,$R_b */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mov_s_mcahb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+ tmp_result = GET_H_CR16 (FLD (f_op__b));
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_h), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GTSI (-1, 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mov_s_r_u7: mov$_S $R_b,$u7 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mov_s_r_u7) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+ tmp_result = FLD (f_u8);
+ {
+ SI opval = tmp_result;
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+if (GTSI (-1, 0)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* tst_L_s12 : tst$_L$F1 $RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,tst_L_s12_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_s12);
+ tmp_result = ANDSI (tmp_B, tmp_C);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* tst_ccu6 : tst$Qcondi$F1 $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,tst_ccu6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+ tmp_result = ANDSI (tmp_B, tmp_C);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* tst_L_u6 : tst$_L$F1 $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,tst_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+ tmp_result = ANDSI (tmp_B, tmp_C);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* tst_L_r_r $RC: tst$_L$F1 $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,tst_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+ tmp_result = ANDSI (tmp_B, tmp_C);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* tst_cc $RC: tst$Qcondi$F1 $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,tst_cc__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+ tmp_result = ANDSI (tmp_B, tmp_C);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* tst_s_go: tst$_S $R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,tst_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ tmp_result = ANDSI (tmp_B, tmp_C);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* cmp_L_s12 : cmp$_L$F1 $RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,cmp_L_s12_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (FLD (f_s12));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (FLD (f_s12));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* cmp_ccu6 : cmp$Qcondi$F1 $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,cmp_ccu6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* cmp_L_u6 : cmp$_L$F1 $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,cmp_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* cmp_L_r_r $RC: cmp$_L$F1 $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,cmp_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* cmp_cc $RC: cmp$Qcondi$F1 $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,cmp_cc__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* cmp_s_mcah: cmp$_S $R_b,$Rh */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,cmp_s_mcah) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_mcah.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+{
+if (EQSI (FLD (f_op_h), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 2));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (2, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_h), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = EXTSIDI (GET_H_CR16 (FLD (f_op__b)));
+ tmp_C = EXTSIDI (GET_H_CR (FLD (f_op_h)));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR16 (FLD (f_op__b)));
+ tmp_C = ZEXTSIDI (GET_H_CR (FLD (f_op_h)));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* cmp_s_r_u7: cmp$_S $R_b,$u7 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,cmp_s_r_u7) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_r_u7.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = EXTSIDI (GET_H_CR16 (FLD (f_op__b)));
+ tmp_C = EXTSIDI (FLD (f_u7));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR16 (FLD (f_op__b)));
+ tmp_C = ZEXTSIDI (FLD (f_u7));
+ tmp_tmp = SUBDI (tmp_B, tmp_C);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* rcmp_L_s12 : rcmp$_L$F1 $RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,rcmp_L_s12_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (FLD (f_s12));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (FLD (f_s12));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* rcmp_ccu6 : rcmp$Qcondi$F1 $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,rcmp_ccu6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* rcmp_L_u6 : rcmp$_L$F1 $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,rcmp_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (FLD (f_u6));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* rcmp_L_r_r $RC: rcmp$_L$F1 $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,rcmp_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* rcmp_cc $RC: rcmp$Qcondi$F1 $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,rcmp_cc__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ DI tmp_tmp;
+ DI tmp_B;
+ DI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = EXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ tmp_result = SUBWORDDISI (tmp_tmp, 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEBI (LTSI (tmp_result, 0), LTDI (tmp_tmp, 0));
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ tmp_B = ZEXTSIDI (GET_H_CR (FLD (f_op_B)));
+ tmp_C = ZEXTSIDI (GET_H_CR (FLD (f_op_C)));
+ tmp_tmp = SUBDI (tmp_C, tmp_B);
+ {
+ BI opval = LTDI (tmp_tmp, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* rsub_L_s12 $RA,: rsub$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,rsub_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (FLD (f_s12), GET_H_CR (FLD (f_op_B)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (FLD (f_s12), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (FLD (f_s12), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* rsub_ccu6 $RA,: rsub$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,rsub_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (FLD (f_u6), GET_H_CR (FLD (f_op_B)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (FLD (f_u6), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (FLD (f_u6), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* rsub_L_u6 $RA,: rsub$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,rsub_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (FLD (f_u6), GET_H_CR (FLD (f_op_B)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (FLD (f_u6), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (FLD (f_u6), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* rsub_L_r_r $RA,$RC: rsub$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,rsub_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* rsub_cc $RA,$RC: rsub$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,rsub_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_B)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bset_L_s12 $RA,: bset$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,bset_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (FLD (f_s12), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bset_ccu6 $RA,: bset$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,bset_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bset_L_u6 $RA,: bset$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,bset_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bset_L_r_r $RA,$RC: bset$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,bset_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bset_cc $RA,$RC: bset$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,bset_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bset_s_ssb: bset$_S $R_b,$R_b,$u5 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,bset_s_ssb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ {
+ SI opval = ORSI (tmp_B, SLLSI (1, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* bclr_L_s12 $RA,: bclr$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,bclr_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (SLLSI (1, ANDSI (FLD (f_s12), 31))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bclr_ccu6 $RA,: bclr$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,bclr_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (SLLSI (1, ANDSI (FLD (f_u6), 31))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bclr_L_u6 $RA,: bclr$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,bclr_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (SLLSI (1, ANDSI (FLD (f_u6), 31))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bclr_L_r_r $RA,$RC: bclr$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,bclr_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bclr_cc $RA,$RC: bclr$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,bclr_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), INVSI (SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bclr_s_ssb: bclr$_S $R_b,$R_b,$u5 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,bclr_s_ssb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ {
+ SI opval = ANDSI (tmp_B, INVSI (SLLSI (1, ANDSI (tmp_C, 31))));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* btst_L_s12 : btst$_L$F1 $RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,btst_L_s12_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_s12);
+ tmp_result = ANDSI (tmp_B, SLLSI (1, ANDSI (tmp_C, 31)));
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* btst_ccu6 : btst$Qcondi$F1 $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,btst_ccu6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+ tmp_result = ANDSI (tmp_B, SLLSI (1, ANDSI (tmp_C, 31)));
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* btst_L_u6 : btst$_L$F1 $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,btst_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = FLD (f_u6);
+ tmp_result = ANDSI (tmp_B, SLLSI (1, ANDSI (tmp_C, 31)));
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* btst_L_r_r $RC: btst$_L$F1 $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,btst_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+ tmp_result = ANDSI (tmp_B, SLLSI (1, ANDSI (tmp_C, 31)));
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* btst_cc $RC: btst$Qcondi$F1 $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,btst_cc__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR (FLD (f_op_B));
+ tmp_C = GET_H_CR (FLD (f_op_C));
+ tmp_result = ANDSI (tmp_B, SLLSI (1, ANDSI (tmp_C, 31)));
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* btst_s_ssb: btst$_S $R_b,$u5 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,btst_s_ssb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ tmp_result = ANDSI (tmp_B, SLLSI (1, ANDSI (tmp_C, 31)));
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* bxor_L_s12 $RA,: bxor$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,bxor_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (FLD (f_s12), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bxor_ccu6 $RA,: bxor$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,bxor_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bxor_L_u6 $RA,: bxor$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,bxor_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bxor_L_r_r $RA,$RC: bxor$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,bxor_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bxor_cc $RA,$RC: bxor$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,bxor_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = XORSI (GET_H_CR (FLD (f_op_B)), SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bmsk_L_s12 $RA,: bmsk$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,bmsk_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), SUBSI (SLLSI (SLLSI (1, ANDSI (FLD (f_s12), 31)), 1), 1));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bmsk_ccu6 $RA,: bmsk$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,bmsk_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), SUBSI (SLLSI (SLLSI (1, ANDSI (FLD (f_u6), 31)), 1), 1));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bmsk_L_u6 $RA,: bmsk$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,bmsk_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), SUBSI (SLLSI (SLLSI (1, ANDSI (FLD (f_u6), 31)), 1), 1));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bmsk_L_r_r $RA,$RC: bmsk$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,bmsk_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), SUBSI (SLLSI (SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31)), 1), 1));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bmsk_cc $RA,$RC: bmsk$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,bmsk_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ANDSI (GET_H_CR (FLD (f_op_B)), SUBSI (SLLSI (SLLSI (1, ANDSI (GET_H_CR (FLD (f_op_C)), 31)), 1), 1));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* bmsk_s_ssb: bmsk$_S $R_b,$R_b,$u5 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,bmsk_s_ssb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ {
+ SI opval = ANDSI (tmp_B, SUBSI (SLLSI (SLLSI (1, ANDSI (tmp_C, 31)), 1), 1));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* add1_L_s12 $RA,: add1$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,add1_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s12), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_s12), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add1_ccu6 $RA,: add1$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,add1_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add1_L_u6 $RA,: add1$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,add1_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add1_L_r_r $RA,$RC: add1$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,add1_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add1_cc $RA,$RC: add1$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,add1_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_ADD1_s_go: add1$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,I16_GO_ADD1_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ADDSI (tmp_B, SLLSI (tmp_C, 1));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* add2_L_s12 $RA,: add2$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,add2_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s12), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_s12), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add2_ccu6 $RA,: add2$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,add2_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add2_L_u6 $RA,: add2$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,add2_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add2_L_r_r $RA,$RC: add2$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,add2_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add2_cc $RA,$RC: add2$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,add2_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_ADD2_s_go: add2$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,I16_GO_ADD2_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ADDSI (tmp_B, SLLSI (tmp_C, 2));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* add3_L_s12 $RA,: add3$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,add3_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s12), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_s12), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add3_ccu6 $RA,: add3$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,add3_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add3_L_u6 $RA,: add3$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,add3_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add3_L_r_r $RA,$RC: add3$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,add3_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* add3_cc $RA,$RC: add3$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,add3_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_ADD3_s_go: add3$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,I16_GO_ADD3_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ADDSI (tmp_B, SLLSI (tmp_C, 3));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* sub1_L_s12 $RA,: sub1$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,sub1_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s12), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_s12), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub1_ccu6 $RA,: sub1$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,sub1_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub1_L_u6 $RA,: sub1$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,sub1_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub1_L_r_r $RA,$RC: sub1$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,sub1_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub1_cc $RA,$RC: sub1$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,sub1_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 1));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 1);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub2_L_s12 $RA,: sub2$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,sub2_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s12), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_s12), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub2_ccu6 $RA,: sub2$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,sub2_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub2_L_u6 $RA,: sub2$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,sub2_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub2_L_r_r $RA,$RC: sub2$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,sub2_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub2_cc $RA,$RC: sub2$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,sub2_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 2));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 2);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub3_L_s12 $RA,: sub3$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,sub3_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_s12), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_s12), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub3_ccu6 $RA,: sub3$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,sub3_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub3_L_u6 $RA,: sub3$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,sub3_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (FLD (f_u6), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (FLD (f_u6), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub3_L_r_r $RA,$RC: sub3$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,sub3_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sub3_cc $RA,$RC: sub3$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,sub3_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = SUBSI (GET_H_CR (FLD (f_op_B)), SLLSI (GET_H_CR (FLD (f_op_C)), 3));
+if (FLD (f_F)) {
+{
+ SI tmp_sC;
+ tmp_sC = SLLSI (GET_H_CR (FLD (f_op_C)), 3);
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SUBOFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = SUBCFSI (GET_H_CR (FLD (f_op_B)), tmp_sC, 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpy_L_s12 $RA,: mpy$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mpy_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (EXTSIDI (tmp_result), MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_s12))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpy_ccu6 $RA,: mpy$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mpy_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (EXTSIDI (tmp_result), MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpy_L_u6 $RA,: mpy$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mpy_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (EXTSIDI (tmp_result), MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpy_L_r_r $RA,$RC: mpy$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mpy_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (EXTSIDI (tmp_result), MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C)))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpy_cc $RA,$RC: mpy$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mpy_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (EXTSIDI (tmp_result), MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C)))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyh_L_s12 $RA,: mpyh$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mpyh_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_s12))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyh_ccu6 $RA,: mpyh$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mpyh_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyh_L_u6 $RA,: mpyh$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mpyh_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyh_L_r_r $RA,$RC: mpyh$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mpyh_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C)))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyh_cc $RA,$RC: mpyh$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mpyh_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C)))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyhu_L_s12 $RA,: mpyhu$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mpyhu_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_s12))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyhu_ccu6 $RA,: mpyhu$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mpyhu_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_u6))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyhu_L_u6 $RA,: mpyhu$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mpyhu_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_u6))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyhu_L_r_r $RA,$RC: mpyhu$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mpyhu_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (GET_H_CR (FLD (f_op_C)))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyhu_cc $RA,$RC: mpyhu$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mpyhu_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SUBWORDDISI (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (GET_H_CR (FLD (f_op_C)))), 0));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyu_L_s12 $RA,: mpyu$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mpyu_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), FLD (f_s12)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (ZEXTSIDI (tmp_result), MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_s12))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyu_ccu6 $RA,: mpyu$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mpyu_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (ZEXTSIDI (tmp_result), MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_u6))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyu_L_u6 $RA,: mpyu$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mpyu_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), FLD (f_u6)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (ZEXTSIDI (tmp_result), MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_u6))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyu_L_r_r $RA,$RC: mpyu$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mpyu_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (ZEXTSIDI (tmp_result), MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (GET_H_CR (FLD (f_op_C)))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mpyu_cc $RA,$RC: mpyu$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mpyu_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULSI (GET_H_CR (FLD (f_op_B)), GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = NEDI (ZEXTSIDI (tmp_result), MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (GET_H_CR (FLD (f_op_C)))));
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* j_L_r_r [$RC_noilink]: j$_L$F0 [$RC_noilink] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,j_L_r_r___RC_noilink_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_cc [$RC_noilink]: j$Qcondi$F0 [$RC_noilink] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,j_cc___RC_noilink_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_L_r_r [$RC_ilink]: j$_L$F1F [$RC_ilink] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,j_L_r_r___RC_ilink_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_ILINKX (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_ILINKX (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_ILINKX (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_cc [$RC_ilink]: j$Qcondi$F1F [$RC_ilink] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,j_cc___RC_ilink_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_ILINKX (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_ILINKX (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ switch (FLD (f_op_Cj))
+ {
+ case 29 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 11));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ case 30 : {
+if (FLD (f_F)) {
+ {
+ SI opval = GET_H_AUXR (((UINT) 12));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 24);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+} else {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ default : {
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+}
+ break;
+ }
+ {
+ USI opval = GET_H_ILINKX (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 25);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_L_s12 : j$_L$F0 $s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,j_L_s12_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_ccu6 : j$Qcondi$F0 $U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,j_ccu6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_L_u6 : j$_L$F0 $U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,j_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (FLD (f_F)) {
+cgen_rtx_error (current_cpu, "invalid insn");
+}
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_s: j$_S [$R_b] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,j_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_s$_S: j$_S [$R31] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,j_s__S) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_seq$_S: jeq$_S [$R31] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,j_seq__S) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if (NEBI (CPU (h_zbit), 0)) {
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if (NEBI (CPU (h_zbit), 0)) {
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if (NEBI (CPU (h_zbit), 0)) {
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_sne$_S: jne$_S [$R31] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,j_sne__S) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if (EQBI (CPU (h_zbit), 0)) {
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if (EQBI (CPU (h_zbit), 0)) {
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if (EQBI (CPU (h_zbit), 0)) {
+{
+((void) 0); /*nop*/
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_L_s12.d : j$_L$F0.d $s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,j_L_s12_d_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_ccu6.d : j$Qcondi$F0.d $U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,j_ccu6_d_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_L_u6.d : j$_L$F0.d $U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,j_L_u6_d_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_L_r_r.d [$RC]: j$_L$F0.d [$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,j_L_r_r_d___RC_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_cc.d [$RC]: j$Qcondi$F0.d [$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,j_cc_d___RC_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_s.d: j$_S.d [$R_b] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,j_s_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* j_s$_S.d: j$_S.d [$R31] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,j_s__S_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_R31 ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jl_L_s12 : jl$_L$F0 $s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,jl_L_s12_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jl_ccu6 : jl$Qcondi$F0 $U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,jl_ccu6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jl_L_u6 : jl$_L$F0 $U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,jl_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jl_s: jl$_S [$R_b] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,jl_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 2);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 2);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 2);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jl_L_r_r [$RC_noilink]: jl$_L$F0 [$RC_noilink] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,jl_L_r_r___RC_noilink_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, ((EQSI (FLD (f_op_C), 62)) ? (8) : (4)));
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, ((EQSI (FLD (f_op_C), 62)) ? (8) : (4)));
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, ((EQSI (FLD (f_op_C), 62)) ? (8) : (4)));
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jl_cc [$RC_noilink]: jl$Qcondi$F0 [$RC_noilink] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,jl_cc___RC_noilink_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, ((EQSI (FLD (f_op_C), 62)) ? (8) : (4)));
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, ((EQSI (FLD (f_op_C), 62)) ? (8) : (4)));
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ USI opval = GET_H_NOILINK (FLD (f_op_Cj));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, ((EQSI (FLD (f_op_C), 62)) ? (8) : (4)));
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jl_L_s12.d : jl$_L$F0.d $s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,jl_L_s12_d_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_s12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jl_ccu6.d : jl$Qcondi$F0.d $U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,jl_ccu6_d_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jl_L_u6.d : jl$_L$F0.d $U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,jl_L_u6_d_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (f_u6);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jl_L_r_r.d [$RC]: jl$_L$F0.d [$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,jl_L_r_r_d___RC_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jl_cc.d [$RC]: jl$Qcondi$F0.d [$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,jl_cc_d___RC_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR (FLD (f_op_C));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jl_s.d: jl$_S.d [$R_b] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,jl_s_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 2));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+}
+ else if (1) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 2));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ HI tmp_nword;
+ tmp_nword = GETMEMHI (current_cpu, pc, ADDSI (pc, 2));
+if (ANDHI (ANDHI (tmp_nword, SRAHI (tmp_nword, 1)), 40960)) {
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_CR (((UINT) 31), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_CR16 (FLD (f_op__b));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* lp_L_s12 : lp$_L$F0 $s12x2 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,lp_L_s12_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lp_L_s12_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ SI opval = ADDSI (ANDSI (pc, -4), FLD (f_s12x2));
+ SET_H_AUXR (((UINT) 3), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_AUXR (((UINT) 2), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ SI opval = ADDSI (ANDSI (pc, -4), FLD (f_s12x2));
+ SET_H_AUXR (((UINT) 3), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_AUXR (((UINT) 2), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+ {
+ SI opval = ADDSI (ANDSI (pc, -4), FLD (f_s12x2));
+ SET_H_AUXR (((UINT) 3), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_AUXR (((UINT) 2), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* lpcc_ccu6: lp$Qcondi$F0 $U6x2 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,lpcc_ccu6) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lpcc_ccu6.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ SI opval = ADDSI (ANDSI (pc, -4), FLD (f_u6x2));
+ SET_H_AUXR (((UINT) 3), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_AUXR (((UINT) 2), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (0) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ SI opval = ADDSI (ANDSI (pc, -4), FLD (f_u6x2));
+ SET_H_AUXR (((UINT) 3), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_AUXR (((UINT) 2), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+ {
+ SI opval = ADDSI (ANDSI (pc, -4), FLD (f_u6x2));
+ SET_H_AUXR (((UINT) 3), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_AUXR (((UINT) 2), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+}
+}
+} else {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = ADDSI (ANDSI (pc, -4), FLD (f_u6x2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = ADDSI (ANDSI (pc, -4), FLD (f_u6x2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = ADDSI (ANDSI (pc, -4), FLD (f_u6x2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* flag_L_s12 : flag$_L$F0 $s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,flag_L_s12_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (ANDSI (FLD (f_s12), 1)) {
+sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc, sim_exited, a5f_h_cr_get (current_cpu, 0));}
+ {
+ SI opval = FLD (f_s12);
+ SET_H_STATUS32 (((UINT) 0), opval);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* flag_ccu6 : flag$Qcondi$F0 $U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,flag_ccu6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+if (ANDSI (FLD (f_u6), 1)) {
+sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc, sim_exited, a5f_h_cr_get (current_cpu, 0));}
+ {
+ SI opval = FLD (f_u6);
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* flag_L_u6 : flag$_L$F0 $U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,flag_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (ANDSI (FLD (f_u6), 1)) {
+sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc, sim_exited, a5f_h_cr_get (current_cpu, 0));}
+ {
+ SI opval = FLD (f_u6);
+ SET_H_STATUS32 (((UINT) 0), opval);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* flag_L_r_r $RC: flag$_L$F0 $RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,flag_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+{
+if (ANDSI (GET_H_CR (FLD (f_op_C)), 1)) {
+sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc, sim_exited, a5f_h_cr_get (current_cpu, 0));}
+ {
+ SI opval = GET_H_CR (FLD (f_op_C));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* flag_cc $RC: flag$Qcondi$F0 $RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,flag_cc__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+{
+if (ANDSI (GET_H_CR (FLD (f_op_C)), 1)) {
+sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc, sim_exited, a5f_h_cr_get (current_cpu, 0));}
+ {
+ SI opval = GET_H_CR (FLD (f_op_C));
+ SET_H_STATUS32 (((UINT) 0), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "status32", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* lr_L_r_r [$RC]: lr$_L$F0 $RB,[$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,lr_L_r_r___RC_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ {
+ SI opval = GET_H_AUXR (GET_H_CR (FLD (f_op_C)));
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* lr_L_s12 : lr$_L$F0 $RB,[$s12] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,lr_L_s12_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ {
+ SI opval = GET_H_AUXR (FLD (f_s12));
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* lr_L_u6 : lr$_L$F0 $RB,[$U6] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,lr_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ {
+ SI opval = GET_H_AUXR (FLD (f_u6));
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* sr_L_r_r [$RC]: sr$_L$F0 $RB,[$RC] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,sr_L_r_r___RC_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ {
+ SI opval = GET_H_CR (FLD (f_op_B));
+ SET_H_AUXR (GET_H_CR (FLD (f_op_C)), opval);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* sr_L_s12 : sr$_L$F0 $RB,[$s12] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,sr_L_s12_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ {
+ SI opval = GET_H_CR (FLD (f_op_B));
+ SET_H_AUXR (FLD (f_s12), opval);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* sr_L_u6 : sr$_L$F0 $RB,[$U6] */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,sr_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ {
+ SI opval = GET_H_CR (FLD (f_op_B));
+ SET_H_AUXR (FLD (f_u6), opval);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+}
+
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* asl_L_r_r $RC: asl$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,asl_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (GET_H_CR (FLD (f_op_C)), GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asl_L_u6 : asl$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,asl_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ADDSI (FLD (f_u6), FLD (f_u6));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ADDOFSI (FLD (f_u6), FLD (f_u6), 0);
+ CPU (h_vbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = ADDCFSI (FLD (f_u6), FLD (f_u6), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_ASL_s_go: asl$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,I16_GO_ASL_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ADDSI (tmp_C, tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* asr_L_r_r $RC: asr$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,asr_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SRASI (GET_H_CR (FLD (f_op_C)), 1);
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (GET_H_CR (FLD (f_op_C)), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asr_L_u6 : asr$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,asr_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SRASI (FLD (f_u6), 1);
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (FLD (f_u6), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_ASR_s_go: asr$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,I16_GO_ASR_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = SRASI (tmp_C, 1);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* lsr_L_r_r $RC: lsr$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,lsr_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SRLSI (GET_H_CR (FLD (f_op_C)), 1);
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (GET_H_CR (FLD (f_op_C)), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* lsr_L_u6 : lsr$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,lsr_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = SRLSI (FLD (f_u6), 1);
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (FLD (f_u6), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_LSR_s_go: lsr$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,I16_GO_LSR_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = SRLSI (tmp_C, 1);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ror_L_r_r $RC: ror$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ror_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (SRLSI (GET_H_CR (FLD (f_op_C)), 1), SLLSI (GET_H_CR (FLD (f_op_C)), 31));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (GET_H_CR (FLD (f_op_C)), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* ror_L_u6 : ror$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ror_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (SRLSI (FLD (f_u6), 1), SLLSI (FLD (f_u6), 31));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (FLD (f_u6), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* rrc_L_r_r $RC: rrc$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,rrc_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (SRLSI (GET_H_CR (FLD (f_op_C)), 1), SLLSI (ZEXTBISI (CPU (h_cbit)), 31));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (GET_H_CR (FLD (f_op_C)), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* rrc_L_u6 : rrc$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,rrc_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (SRLSI (FLD (f_u6), 1), SLLSI (ZEXTBISI (CPU (h_cbit)), 31));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ANDSI (FLD (f_u6), 1);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sexb_L_r_r $RC: sexb$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,sexb_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = EXTQISI ((GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sexb_L_u6 : sexb$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,sexb_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = EXTQISI ((FLD (f_u6)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_SEXB_s_go: sexb$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,I16_GO_SEXB_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = EXTQISI ((tmp_C));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* sexw_L_r_r $RC: sexw$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,sexw_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = EXTHISI ((GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sexw_L_u6 : sexw$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,sexw_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = EXTHISI ((FLD (f_u6)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_SEXW_s_go: sexw$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,I16_GO_SEXW_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = EXTHISI ((tmp_C));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* extb_L_r_r $RC: extb$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,extb_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ZEXTQISI ((GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* extb_L_u6 : extb$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,extb_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ZEXTQISI ((FLD (f_u6)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_EXTB_s_go: extb$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,I16_GO_EXTB_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ZEXTQISI ((tmp_C));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* extw_L_r_r $RC: extw$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,extw_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ZEXTHISI ((GET_H_CR (FLD (f_op_C))));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* extw_L_u6 : extw$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,extw_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ZEXTHISI ((FLD (f_u6)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_EXTW_s_go: extw$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,I16_GO_EXTW_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ZEXTHISI ((tmp_C));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* abs_L_r_r $RC: abs$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,abs_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ABSSI (({ SI tmp_res;
+ tmp_res = GET_H_CR (FLD (f_op_C));
+; tmp_res; }));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI ((GET_H_CR (FLD (f_op_C))), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (GET_H_CR (FLD (f_op_C)), 0x80000000);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_vbit);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* abs_L_u6 : abs$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,abs_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ABSSI (({ SI tmp_res;
+ tmp_res = FLD (f_u6);
+; tmp_res; }));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI ((FLD (f_u6)), 0);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (FLD (f_u6), 0x80000000);
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_vbit);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_ABS_s_go: abs$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,I16_GO_ABS_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = ABSSI (({ SI tmp_res;
+ tmp_res = tmp_C;
+; tmp_res; }));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* not_L_r_r $RC: not$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,not_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = INVSI (GET_H_CR (FLD (f_op_C)));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* not_L_u6 : not$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,not_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = INVSI (FLD (f_u6));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_NOT_s_go: not$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,I16_GO_NOT_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = INVSI (tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* rlc_L_r_r $RC: rlc$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,rlc_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (SLLSI (GET_H_CR (FLD (f_op_C)), 1), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SRLSI (GET_H_CR (FLD (f_op_C)), 31);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* rlc_L_u6 : rlc$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,rlc_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ORSI (SLLSI (FLD (f_u6), 1), CPU (h_cbit));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = SRLSI (FLD (f_u6), 31);
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* ex_L_r_r $RC: ex$_L$EXDi $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ex_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ SI tmp_dummy;
+ {
+ SI opval = GET_H_CR (FLD (f_op_B));
+ SETMEMSI (current_cpu, pc, GET_H_CR (FLD (f_op_C)), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+; GETMEMSI (current_cpu, pc, GET_H_CR (FLD (f_op_C))); });
+if (FLD (f_F)) {
+((void) 0); /*nop*/
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ex_L_u6 : ex$_L$EXDi $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ex_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ SI tmp_dummy;
+ {
+ SI opval = GET_H_CR (FLD (f_op_B));
+ SETMEMSI (current_cpu, pc, FLD (f_u6), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+; GETMEMSI (current_cpu, pc, FLD (f_u6)); });
+if (FLD (f_F)) {
+((void) 0); /*nop*/
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_NEG_s_go: neg$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,I16_GO_NEG_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = NEGSI (tmp_C);
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* swi: swi */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,swi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+; /*clobber*/
+ {
+ USI opval = arc_trap (current_cpu, pc, 4, 0);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+ else if (0) {
+{
+; /*clobber*/
+ {
+ USI opval = arc_trap (current_cpu, pc, 4, 0);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+; /*clobber*/
+ {
+ USI opval = arc_trap (current_cpu, pc, 4, 0);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* trap_s: trap$_S $trapnum */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,trap_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_trap_s.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (pc, 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = arc_trap (current_cpu, pc, 2, FLD (f_trapnum));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+; /*clobber*/
+}
+}
+}
+ else if (0) {
+{
+ {
+ USI opval = arc_trap (current_cpu, pc, 2, FLD (f_trapnum));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+; /*clobber*/
+}
+}
+ else {
+{
+ {
+ SI opval = pc;
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+{
+ {
+ USI opval = arc_trap (current_cpu, pc, 2, FLD (f_trapnum));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+; /*clobber*/
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* brk: brk */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,brk) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+arc_breakpoint (current_cpu, pc, 4);
+
+ return vpc;
+#undef FLD
+}
+
+/* brk_s: brk_s */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,brk_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+arc_breakpoint (current_cpu, pc, 2);
+
+ return vpc;
+#undef FLD
+}
+
+/* asl_L_s12 $RA,: asl$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,asl_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_s12), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_s12), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (32, ANDSI (FLD (f_s12), 31))), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asl_ccu6 $RA,: asl$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,asl_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (32, ANDSI (FLD (f_u6), 31))), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asl_L_u6 $RA,: asl$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,asl_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (32, ANDSI (FLD (f_u6), 31))), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asl_L_r_r $RA,$RC: asl$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,asl_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (32, ANDSI (GET_H_CR (FLD (f_op_C)), 31))), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asl_cc $RA,$RC: asl$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,asl_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (32, ANDSI (GET_H_CR (FLD (f_op_C)), 31))), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asl_s_cbu3: asl$_S $R_c,$R_b,$u3 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,asl_s_cbu3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u3);
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* asl_s_ssb: asl$_S $R_b,$R_b,$u5 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,asl_s_ssb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_ASLM_s_go: asl$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,I16_GO_ASLM_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SLLSI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* lsr_L_s12 $RA,: lsr$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,lsr_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_s12), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_s12), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_s12), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* lsr_ccu6 $RA,: lsr$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,lsr_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_u6), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* lsr_L_u6 $RA,: lsr$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,lsr_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_u6), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* lsr_L_r_r $RA,$RC: lsr$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,lsr_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* lsr_cc $RA,$RC: lsr$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,lsr_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* lsr_s_ssb: lsr$_S $R_b,$R_b,$u5 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,lsr_s_ssb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_LSRM_s_go: lsr$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,I16_GO_LSRM_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* asr_L_s12 $RA,: asr$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,asr_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_s12), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_s12), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_s12), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asr_ccu6 $RA,: asr$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,asr_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_u6), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asr_L_u6 $RA,: asr$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,asr_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_u6), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asr_L_r_r $RA,$RC: asr$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,asr_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asr_cc $RA,$RC: asr$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,asr_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asr_s_cbu3: asr$_S $R_c,$R_b,$u3 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,asr_s_cbu3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u3);
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__c), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* asr_s_ssb: asr$_S $R_b,$R_b,$u5 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,asr_s_ssb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldb_s_abu.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = FLD (f_u5);
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* I16_GO_ASRM_s_go: asr$_S $R_b,$R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,I16_GO_ASRM_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ SI tmp_B;
+ SI tmp_C;
+((void) 0); /*nop*/
+ tmp_B = GET_H_CR16 (FLD (f_op__b));
+ tmp_C = GET_H_CR16 (FLD (f_op__c));
+ {
+ SI opval = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRASI (tmp_B, ANDSI (tmp_C, 31)));
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* ror_L_s12 $RA,: ror$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ror_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (RORSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_s12), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_s12), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_s12), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* ror_ccu6 $RA,: ror$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ror_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (RORSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_u6), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* ror_L_u6 $RA,: ror$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ror_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (RORSI (GET_H_CR (FLD (f_op_B)), ANDSI (FLD (f_u6), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (FLD (f_u6), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (FLD (f_u6), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* ror_L_r_r $RA,$RC: ror$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ror_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (RORSI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* ror_cc $RA,$RC: ror$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,ror_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (RORSI (GET_H_CR (FLD (f_op_B)), ANDSI (GET_H_CR (FLD (f_op_C)), 31)));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 0)) ? (0) : (ANDSI (SRLSI (GET_H_CR (FLD (f_op_B)), SUBSI (ANDSI (GET_H_CR (FLD (f_op_C)), 31), 1)), 1)));
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mul64_L_s12 : mul64$_L$F1 $RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mul64_L_s12_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_s12)));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mul64_ccu6 : mul64$Qcondi$F1 $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mul64_ccu6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6)));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mul64_L_u6 : mul64$_L$F1 $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mul64_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6)));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mul64_L_r_r $RC: mul64$_L$F1 $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mul64_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mul64_cc $RC: mul64$Qcondi$F1 $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mul64_cc__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mul64_s_go: mul64$_S $R_b,$R_c */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mul64_s_go) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_s_cbu3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (EXTSIDI (GET_H_CR16 (FLD (f_op__b))), EXTSIDI (GET_H_CR16 (FLD (f_op__c))));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mulu64_L_s12 : mulu64$_L$F1 $RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mulu64_L_s12_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_s12)));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mulu64_ccu6 : mulu64$Qcondi$F1 $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mulu64_ccu6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_u6)));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mulu64_L_u6 : mulu64$_L$F1 $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mulu64_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (FLD (f_u6)));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mulu64_L_r_r $RC: mulu64$_L$F1 $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mulu64_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_abs.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (GET_H_CR (FLD (f_op_C))));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mulu64_cc $RC: mulu64$Qcondi$F1 $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mulu64_cc__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+((void) 0); /*nop*/
+if ((0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (1)) {
+{
+ DI tmp_result;
+ tmp_result = MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (GET_H_CR (FLD (f_op_C))));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (SRLDI (tmp_result, 16), 1);
+ SET_H_CR (((UINT) 58), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_CR (((UINT) 59), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* adds_L_s12 $RA,: adds$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,adds_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = ADDDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_s12)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* adds_ccu6 $RA,: adds$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,adds_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = ADDDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* adds_L_u6 $RA,: adds$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,adds_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = ADDDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* adds_L_r_r $RA,$RC: adds$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,adds_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = ADDDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* adds_cc $RA,$RC: adds$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,adds_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = ADDDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* subs_L_s12 $RA,: subs$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,subs_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_s12)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* subs_ccu6 $RA,: subs$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,subs_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* subs_L_u6 $RA,: subs$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,subs_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (FLD (f_u6)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* subs_L_r_r $RA,$RC: subs$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,subs_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* subs_cc $RA,$RC: subs$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,subs_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* divaw_L_s12 $RA,: divaw$_L$F0 $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,divaw_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ USI tmp_tmp;
+ tmp_tmp = SLLSI (GET_H_CR (FLD (f_op_B)), 1);
+; ((EQSI (ANDSI (SUBSI (tmp_tmp, FLD (f_s12)), 0x80000000), 0)) ? (ADDSI (SUBSI (tmp_tmp, FLD (f_s12)), 1)) : (tmp_tmp)); }));
+if (FLD (f_F)) {
+((void) 0); /*nop*/
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* divaw_ccu6 $RA,: divaw$Qcondi$F0 $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,divaw_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ USI tmp_tmp;
+ tmp_tmp = SLLSI (GET_H_CR (FLD (f_op_B)), 1);
+; ((EQSI (ANDSI (SUBSI (tmp_tmp, FLD (f_u6)), 0x80000000), 0)) ? (ADDSI (SUBSI (tmp_tmp, FLD (f_u6)), 1)) : (tmp_tmp)); }));
+if (FLD (f_F)) {
+((void) 0); /*nop*/
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* divaw_L_u6 $RA,: divaw$_L$F0 $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,divaw_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ USI tmp_tmp;
+ tmp_tmp = SLLSI (GET_H_CR (FLD (f_op_B)), 1);
+; ((EQSI (ANDSI (SUBSI (tmp_tmp, FLD (f_u6)), 0x80000000), 0)) ? (ADDSI (SUBSI (tmp_tmp, FLD (f_u6)), 1)) : (tmp_tmp)); }));
+if (FLD (f_F)) {
+((void) 0); /*nop*/
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* divaw_L_r_r $RA,$RC: divaw$_L$F0 $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,divaw_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ USI tmp_tmp;
+ tmp_tmp = SLLSI (GET_H_CR (FLD (f_op_B)), 1);
+; ((EQSI (ANDSI (SUBSI (tmp_tmp, GET_H_CR (FLD (f_op_C))), 0x80000000), 0)) ? (ADDSI (SUBSI (tmp_tmp, GET_H_CR (FLD (f_op_C))), 1)) : (tmp_tmp)); }));
+if (FLD (f_F)) {
+((void) 0); /*nop*/
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* divaw_cc $RA,$RC: divaw$Qcondi$F0 $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,divaw_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ USI tmp_tmp;
+ tmp_tmp = SLLSI (GET_H_CR (FLD (f_op_B)), 1);
+; ((EQSI (ANDSI (SUBSI (tmp_tmp, GET_H_CR (FLD (f_op_C))), 0x80000000), 0)) ? (ADDSI (SUBSI (tmp_tmp, GET_H_CR (FLD (f_op_C))), 1)) : (tmp_tmp)); }));
+if (FLD (f_F)) {
+((void) 0); /*nop*/
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asls_L_s12 $RA,: asls$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,asls_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((FLD (f_s12)), 31)) ? (SLLDI (tmp_b, 31)) : (LTSI ((FLD (f_s12)), -31)) ? (SRADI (tmp_b, 31)) : (GESI ((FLD (f_s12)), 0)) ? (SLLDI (tmp_b, (FLD (f_s12)))) : (SRASI (GET_H_CR (FLD (f_op_B)), NEGSI ((FLD (f_s12)))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asls_ccu6 $RA,: asls$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,asls_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((FLD (f_u6)), 31)) ? (SLLDI (tmp_b, 31)) : (LTSI ((FLD (f_u6)), -31)) ? (SRADI (tmp_b, 31)) : (GESI ((FLD (f_u6)), 0)) ? (SLLDI (tmp_b, (FLD (f_u6)))) : (SRASI (GET_H_CR (FLD (f_op_B)), NEGSI ((FLD (f_u6)))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asls_L_u6 $RA,: asls$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,asls_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((FLD (f_u6)), 31)) ? (SLLDI (tmp_b, 31)) : (LTSI ((FLD (f_u6)), -31)) ? (SRADI (tmp_b, 31)) : (GESI ((FLD (f_u6)), 0)) ? (SLLDI (tmp_b, (FLD (f_u6)))) : (SRASI (GET_H_CR (FLD (f_op_B)), NEGSI ((FLD (f_u6)))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asls_L_r_r $RA,$RC: asls$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,asls_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((GET_H_CR (FLD (f_op_C))), 31)) ? (SLLDI (tmp_b, 31)) : (LTSI ((GET_H_CR (FLD (f_op_C))), -31)) ? (SRADI (tmp_b, 31)) : (GESI ((GET_H_CR (FLD (f_op_C))), 0)) ? (SLLDI (tmp_b, (GET_H_CR (FLD (f_op_C))))) : (SRASI (GET_H_CR (FLD (f_op_B)), NEGSI ((GET_H_CR (FLD (f_op_C))))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asls_cc $RA,$RC: asls$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,asls_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((GET_H_CR (FLD (f_op_C))), 31)) ? (SLLDI (tmp_b, 31)) : (LTSI ((GET_H_CR (FLD (f_op_C))), -31)) ? (SRADI (tmp_b, 31)) : (GESI ((GET_H_CR (FLD (f_op_C))), 0)) ? (SLLDI (tmp_b, (GET_H_CR (FLD (f_op_C))))) : (SRASI (GET_H_CR (FLD (f_op_B)), NEGSI ((GET_H_CR (FLD (f_op_C))))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asrs_L_s12 $RA,: asrs$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,asrs_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((FLD (f_s12)), 31)) ? (SRADI (tmp_b, 31)) : (LTSI ((FLD (f_s12)), -31)) ? (SLLDI (tmp_b, 31)) : (GESI ((FLD (f_s12)), 0)) ? (SRADI (tmp_b, (FLD (f_s12)))) : (SLLSI (GET_H_CR (FLD (f_op_B)), NEGSI ((FLD (f_s12)))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asrs_ccu6 $RA,: asrs$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,asrs_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((FLD (f_u6)), 31)) ? (SRADI (tmp_b, 31)) : (LTSI ((FLD (f_u6)), -31)) ? (SLLDI (tmp_b, 31)) : (GESI ((FLD (f_u6)), 0)) ? (SRADI (tmp_b, (FLD (f_u6)))) : (SLLSI (GET_H_CR (FLD (f_op_B)), NEGSI ((FLD (f_u6)))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asrs_L_u6 $RA,: asrs$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,asrs_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((FLD (f_u6)), 31)) ? (SRADI (tmp_b, 31)) : (LTSI ((FLD (f_u6)), -31)) ? (SLLDI (tmp_b, 31)) : (GESI ((FLD (f_u6)), 0)) ? (SRADI (tmp_b, (FLD (f_u6)))) : (SLLSI (GET_H_CR (FLD (f_op_B)), NEGSI ((FLD (f_u6)))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asrs_L_r_r $RA,$RC: asrs$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,asrs_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((GET_H_CR (FLD (f_op_C))), 31)) ? (SRADI (tmp_b, 31)) : (LTSI ((GET_H_CR (FLD (f_op_C))), -31)) ? (SLLDI (tmp_b, 31)) : (GESI ((GET_H_CR (FLD (f_op_C))), 0)) ? (SRADI (tmp_b, (GET_H_CR (FLD (f_op_C))))) : (SLLSI (GET_H_CR (FLD (f_op_B)), NEGSI ((GET_H_CR (FLD (f_op_C))))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* asrs_cc $RA,$RC: asrs$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,asrs_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_b;
+ tmp_b = EXTSIDI (GET_H_CR (FLD (f_op_B)));
+; tmp_b = (EQDI (tmp_b, 0)) ? (0) : (GTSI ((GET_H_CR (FLD (f_op_C))), 31)) ? (SRADI (tmp_b, 31)) : (LTSI ((GET_H_CR (FLD (f_op_C))), -31)) ? (SLLDI (tmp_b, 31)) : (GESI ((GET_H_CR (FLD (f_op_C))), 0)) ? (SRADI (tmp_b, (GET_H_CR (FLD (f_op_C))))) : (SLLSI (GET_H_CR (FLD (f_op_B)), NEGSI ((GET_H_CR (FLD (f_op_C))))));
+; ((GTDI (tmp_b, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_b, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_b)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* addsdw_L_s12 $RA,: addsdw$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,addsdw_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((FLD (f_s12)), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((FLD (f_s12)), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* addsdw_ccu6 $RA,: addsdw$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,addsdw_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((FLD (f_u6)), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((FLD (f_u6)), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* addsdw_L_u6 $RA,: addsdw$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,addsdw_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((FLD (f_u6)), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((FLD (f_u6)), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* addsdw_L_r_r $RA,$RC: addsdw$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,addsdw_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* addsdw_cc $RA,$RC: addsdw$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,addsdw_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = ADDHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* subsdw_L_s12 $RA,: subsdw$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,subsdw_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((FLD (f_s12)), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((FLD (f_s12)), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* subsdw_ccu6 $RA,: subsdw$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,subsdw_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((FLD (f_u6)), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((FLD (f_u6)), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* subsdw_L_u6 $RA,: subsdw$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,subsdw_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((FLD (f_u6)), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((FLD (f_u6)), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* subsdw_L_r_r $RA,$RC: subsdw$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,subsdw_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* subsdw_cc $RA,$RC: subsdw$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,subsdw_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_C_SI;
+ HI tmp_res1;
+ HI tmp_res2;
+ tmp_res2 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 1), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 1));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; tmp_cur_s2bit = tmp_cur_s1bit;
+; tmp_res1 = ({ SI tmp_tmp;
+ tmp_tmp = SUBHI (SUBWORDSIHI (GET_H_CR (FLD (f_op_B)), 0), SUBWORDSIHI ((GET_H_CR (FLD (f_op_C))), 0));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); });
+; ORHI (SLLHI (tmp_res1, 16), tmp_res2); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = ORBI (tmp_cur_s1bit, tmp_cur_s2bit);
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+}
+if (tmp_cur_s2bit) {
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* swap_L_r_r $RC: swap$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,swap_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (RORSI (GET_H_CR (FLD (f_op_C)), 16));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* swap_L_u6 : swap$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,swap_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (RORSI (FLD (f_u6), 16));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* norm_L_r_r $RC: norm$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,norm_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_val;
+ SI tmp_bits;
+ tmp_val = ((GESI ((GET_H_CR (FLD (f_op_C))), 0)) ? ((GET_H_CR (FLD (f_op_C)))) : (INVSI ((GET_H_CR (FLD (f_op_C))))));
+; tmp_bits = 31;
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 4), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 4));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 4));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 3), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 3));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 3));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 2), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 2));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 2));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 1), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 1));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 1));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 0), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 0));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 0));
+}
+; tmp_bits; }));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (GET_H_CR (FLD (f_op_C)), 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* norm_L_u6 : norm$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,norm_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_val;
+ SI tmp_bits;
+ tmp_val = ((GESI ((FLD (f_u6)), 0)) ? ((FLD (f_u6))) : (INVSI ((FLD (f_u6)))));
+; tmp_bits = 31;
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 4), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 4));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 4));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 3), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 3));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 3));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 2), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 2));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 2));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 1), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 1));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 1));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 0), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 0));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 0));
+}
+; tmp_bits; }));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (FLD (f_u6), 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (FLD (f_u6), 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* rnd16_L_r_r $RC: rnd16$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,rnd16_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (({ DI tmp_tmp;
+ tmp_tmp = ADDDI (EXTSIDI (32768), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }), 16));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* rnd16_L_u6 : rnd16$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,rnd16_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (SRLSI (({ DI tmp_tmp;
+ tmp_tmp = ADDDI (EXTSIDI (32768), EXTSIDI (FLD (f_u6)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }), 16));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* abssw_L_r_r $RC: abssw$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,abssw_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_tmp;
+ tmp_tmp = ABSSI (EXTHISI ((GET_H_CR (FLD (f_op_C)))));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* abssw_L_u6 : abssw$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,abssw_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_tmp;
+ tmp_tmp = ABSSI (EXTHISI ((FLD (f_u6))));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* abss_L_r_r $RC: abss$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,abss_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (((GESI ((GET_H_CR (FLD (f_op_C))), 0)) ? (GET_H_CR (FLD (f_op_C))) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (0), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }))));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* abss_L_u6 : abss$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,abss_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (((GESI ((FLD (f_u6)), 0)) ? (FLD (f_u6)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (0), EXTSIDI (FLD (f_u6)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }))));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* negsw_L_r_r $RC: negsw$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,negsw_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_tmp;
+ tmp_tmp = EXTHISI ((GET_H_CR (FLD (f_op_C))));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* negsw_L_u6 : negsw$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,negsw_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_tmp;
+ tmp_tmp = EXTHISI ((FLD (f_u6)));
+; (GTSI (tmp_tmp, 32767)) ? ( tmp_cur_s1bit = 1, 32767) : (LTSI (tmp_tmp, -32768)) ? ( tmp_cur_s1bit = 1, -32768) : (tmp_tmp); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* negs_L_r_r $RC: negs$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,negs_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (0), EXTSIDI (GET_H_CR (FLD (f_op_C))));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* negs_L_u6 : negs$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,negs_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ DI tmp_tmp;
+ tmp_tmp = SUBDI (EXTSIDI (0), EXTSIDI (FLD (f_u6)));
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); }));
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* normw_L_r_r $RC: normw$_L$F $RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,normw_L_r_r__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_C), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_C), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_val;
+ SI tmp_bits;
+ tmp_val = ((GESI (ORSI (SLLSI (GET_H_CR (FLD (f_op_C)), 16), ANDSI (GET_H_CR (FLD (f_op_C)), 65535)), 0)) ? (ORSI (SLLSI (GET_H_CR (FLD (f_op_C)), 16), ANDSI (GET_H_CR (FLD (f_op_C)), 65535))) : (INVSI (ORSI (SLLSI (GET_H_CR (FLD (f_op_C)), 16), ANDSI (GET_H_CR (FLD (f_op_C)), 65535)))));
+; tmp_bits = 31;
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 4), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 4));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 4));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 3), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 3));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 3));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 2), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 2));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 2));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 1), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 1));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 1));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 0), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 0));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 0));
+}
+; tmp_bits; }));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* normw_L_u6 : normw$_L$F $RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,normw_L_u6_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (({ SI tmp_val;
+ SI tmp_bits;
+ tmp_val = ((GESI (ORSI (SLLSI (FLD (f_u6), 16), ANDSI (FLD (f_u6), 65535)), 0)) ? (ORSI (SLLSI (FLD (f_u6), 16), ANDSI (FLD (f_u6), 65535))) : (INVSI (ORSI (SLLSI (FLD (f_u6), 16), ANDSI (FLD (f_u6), 65535)))));
+; tmp_bits = 31;
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 4), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 4));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 4));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 3), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 3));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 3));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 2), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 2));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 2));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 1), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 1));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 1));
+}
+; if (GESI (tmp_val, SLLSI (1, SUBSI (SLLSI (1, 0), 1)))) {
+ tmp_val = SRLSI (tmp_val, SLLSI (1, 0));
+ tmp_bits = SUBSI (tmp_bits, SLLSI (1, 0));
+}
+; tmp_bits; }));
+if (FLD (f_F)) {
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* nop_s: nop_s */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,nop_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* unimp_s: unimp_s */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,unimp_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+cgen_rtx_error (current_cpu, "invalid insn");
+
+ return vpc;
+#undef FLD
+}
+
+/* pop_s_b: pop$_S $R_b */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,pop_s_b) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ SI opval = GETMEMSI (current_cpu, pc, GET_H_SP ());
+ SET_H_CR16 (FLD (f_op__b), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr16", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (GET_H_SP (), 4);
+ SET_H_SP (, opval);
+ TRACE_RESULT (current_cpu, abuf, "sp", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* pop_s_blink: pop$_S $R31 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,pop_s_blink) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ SI opval = GETMEMSI (current_cpu, pc, GET_H_SP ());
+ SET_H_R31 (, opval);
+ TRACE_RESULT (current_cpu, abuf, "r31", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (GET_H_SP (), 4);
+ SET_H_SP (, opval);
+ TRACE_RESULT (current_cpu, abuf, "sp", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* push_s_b: push$_S $R_b */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,push_s_b) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mov_s_r_u7.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ SI opval = ADDSI (GET_H_SP (), -4);
+ SET_H_SP (, opval);
+ TRACE_RESULT (current_cpu, abuf, "sp", 'x', opval);
+ }
+ {
+ SI opval = GET_H_CR16 (FLD (f_op__b));
+ SETMEMSI (current_cpu, pc, GET_H_SP (), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* push_s_blink: push$_S $R31 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,push_s_blink) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ SI opval = ADDSI (GET_H_SP (), -4);
+ SET_H_SP (, opval);
+ TRACE_RESULT (current_cpu, abuf, "sp", 'x', opval);
+ }
+ {
+ SI opval = GET_H_R31 ();
+ SETMEMSI (current_cpu, pc, GET_H_SP (), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mullw_L_s12 $RA,: mullw$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mullw_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_s12), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mullw_ccu6 $RA,: mullw$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mullw_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_u6), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mullw_L_u6 $RA,: mullw$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mullw_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_u6), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mullw_L_r_r $RA,$RC: mullw$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mullw_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mullw_cc $RA,$RC: mullw$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mullw_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* maclw_L_s12 $RA,: maclw$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,maclw_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ SI tmp_SItmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_s12), 65535))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; {
+ BI opval = ANDBI (CPU (h_vbit), SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; if (NEBI (CPU (h_vbit), 0)) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; tmp_SItmp = ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp));
+; tmp_cur_s1bit = ORBI (tmp_cur_s1bit, CPU (h_vbit));
+; tmp_SItmp; });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* maclw_ccu6 $RA,: maclw$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,maclw_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ SI tmp_SItmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_u6), 65535))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; {
+ BI opval = ANDBI (CPU (h_vbit), SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; if (NEBI (CPU (h_vbit), 0)) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; tmp_SItmp = ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp));
+; tmp_cur_s1bit = ORBI (tmp_cur_s1bit, CPU (h_vbit));
+; tmp_SItmp; });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* maclw_L_u6 $RA,: maclw$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,maclw_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ SI tmp_SItmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_u6), 65535))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; {
+ BI opval = ANDBI (CPU (h_vbit), SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; if (NEBI (CPU (h_vbit), 0)) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; tmp_SItmp = ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp));
+; tmp_cur_s1bit = ORBI (tmp_cur_s1bit, CPU (h_vbit));
+; tmp_SItmp; });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* maclw_L_r_r $RA,$RC: maclw$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,maclw_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ SI tmp_SItmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), 65535))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; {
+ BI opval = ANDBI (CPU (h_vbit), SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; if (NEBI (CPU (h_vbit), 0)) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; tmp_SItmp = ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp));
+; tmp_cur_s1bit = ORBI (tmp_cur_s1bit, CPU (h_vbit));
+; tmp_SItmp; });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* maclw_cc $RA,$RC: maclw$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,maclw_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ SI tmp_SItmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), 65535))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; {
+ BI opval = ANDBI (CPU (h_vbit), SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; if (NEBI (CPU (h_vbit), 0)) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; tmp_SItmp = ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp));
+; tmp_cur_s1bit = ORBI (tmp_cur_s1bit, CPU (h_vbit));
+; tmp_SItmp; });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* machlw_L_s12 $RA,: machlw$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,machlw_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_s12), -65536))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = ANDBI (CPU (h_vbit), XORDI (tmp_old, tmp_tmp));
+; if (tmp_cur_s1bit) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* machlw_ccu6 $RA,: machlw$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,machlw_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_u6), -65536))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = ANDBI (CPU (h_vbit), XORDI (tmp_old, tmp_tmp));
+; if (tmp_cur_s1bit) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* machlw_L_u6 $RA,: machlw$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,machlw_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (FLD (f_u6), -65536))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = ANDBI (CPU (h_vbit), XORDI (tmp_old, tmp_tmp));
+; if (tmp_cur_s1bit) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* machlw_L_r_r $RA,$RC: machlw$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,machlw_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), -65536))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = ANDBI (CPU (h_vbit), XORDI (tmp_old, tmp_tmp));
+; if (tmp_cur_s1bit) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* machlw_cc $RA,$RC: machlw$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,machlw_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (EXTSIDI (GET_H_CR (FLD (f_op_B))), EXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), -65536))));
+; {
+ BI opval = NOTDI (SRLDI (XORDI (tmp_old, tmp_tmp), 63));
+ CPU (h_vbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = ANDBI (CPU (h_vbit), XORDI (tmp_old, tmp_tmp));
+; if (tmp_cur_s1bit) {
+ tmp_tmp = XORDI (SRADI (tmp_old, 63), SRLSI (-1, 1));
+}
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mululw_L_s12 $RA,: mululw$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mululw_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (FLD (f_s12), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mululw_ccu6 $RA,: mululw$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mululw_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (FLD (f_u6), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mululw_L_u6 $RA,: mululw$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mululw_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (FLD (f_u6), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mululw_L_r_r $RA,$RC: mululw$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mululw_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mululw_cc $RA,$RC: mululw$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,mululw_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_tmp;
+ tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), 65535))));
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; ((GTDI (tmp_tmp, 2147483647)) ? ( tmp_cur_s1bit = 1, 2147483647) : (LTDI (tmp_tmp, ADDSI (-2147483647, -1))) ? ( tmp_cur_s1bit = 1, ADDSI (-2147483647, -1)) : ( tmp_cur_s1bit = 0, tmp_tmp)); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* machulw_L_s12 $RA,: machulw$_L$F $RB,$RB,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,machulw_L_s12__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_s12__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (FLD (f_s12), -65536))));
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = (GTUDI (tmp_old, tmp_tmp)) ? (( tmp_tmp = -1, 1)) : (0);
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* machulw_ccu6 $RA,: machulw$Qcondi$F $RB,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,machulw_ccu6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_ccu6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (FLD (f_u6), -65536))));
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = (GTUDI (tmp_old, tmp_tmp)) ? (( tmp_tmp = -1, 1)) : (0);
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* machulw_L_u6 $RA,: machulw$_L$F $RA,$RB,$U6 */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,machulw_L_u6__RA_) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_u6__RA_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (EQSI (FLD (f_op_B), 62)) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (EQSI (FLD (f_op_B), 63)) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (FLD (f_u6), -65536))));
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = (GTUDI (tmp_old, tmp_tmp)) ? (( tmp_tmp = -1, 1)) : (0);
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* machulw_L_r_r $RA,$RC: machulw$_L$F $RA,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,machulw_L_r_r__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_L_r_r__RA__RC.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), -65536))));
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = (GTUDI (tmp_old, tmp_tmp)) ? (( tmp_tmp = -1, 1)) : (0);
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_A), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* machulw_cc $RA,$RC: machulw$Qcondi$F $RB,$RB,$RC */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,machulw_cc__RA__RC) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_j_cc___RC_noilink_.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+if (ORBI (EQSI (FLD (f_op_B), 62), EQSI (FLD (f_op_C), 62))) {
+{
+ HI tmp_high;
+ HI tmp_low;
+ tmp_high = GETMEMHI (current_cpu, pc, ADDSI (pc, 4));
+ tmp_low = GETMEMHI (current_cpu, pc, ADDSI (pc, ADDSI (4, 2)));
+CPU (h_cr[((UINT) 62)]) = ORSI (SLLSI (ZEXTHISI (tmp_high), 16), ZEXTHISI (tmp_low));
+}
+}
+if (ORBI (EQSI (FLD (f_op_B), 63), EQSI (FLD (f_op_C), 63))) {
+CPU (h_cr[((UINT) 63)]) = ANDSI (pc, -4);
+}
+}
+if (GET_H_QCONDB (FLD (f_cond_Q))) {
+{
+ SI tmp_result;
+ BI tmp_cur_s1bit;
+ BI tmp_cur_s2bit;
+((void) 0); /*nop*/
+ tmp_result = ({ DI tmp_old;
+ DI tmp_tmp;
+ tmp_old = ADDDI (SLLDI (ZEXTSIDI (GET_H_CR (((UINT) 56))), 32), ZEXTSIDI (GET_H_CR (((UINT) 57))));
+; tmp_tmp = (0) ? ((cgen_rtx_error (current_cpu, "invalid insn"), 0)) : (MULDI (ZEXTSIDI (GET_H_CR (FLD (f_op_B))), ZEXTSIDI (ANDSI (GET_H_CR (FLD (f_op_C)), -65536))));
+; tmp_tmp = ADDDI (tmp_old, tmp_tmp);
+; tmp_cur_s1bit = (GTUDI (tmp_old, tmp_tmp)) ? (( tmp_tmp = -1, 1)) : (0);
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 1);
+ SET_H_CR (((UINT) 57), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; {
+ SI opval = SUBWORDDISI (tmp_tmp, 0);
+ SET_H_CR (((UINT) 56), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+; SUBWORDDISI (tmp_tmp, 0); });
+if (FLD (f_F)) {
+{
+{
+ {
+ BI opval = LTSI (tmp_result, 0);
+ CPU (h_nbit) = opval;
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = EQSI (tmp_result, 0);
+ CPU (h_zbit) = opval;
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+ {
+ BI opval = tmp_cur_s1bit;
+ CPU (h_vbit) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+if (tmp_cur_s1bit) {
+ {
+ BI opval = 1;
+ CPU (h_s1bit) = opval;
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "s1bit", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_s2bit) = opval;
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "s2bit", 'x', opval);
+ }
+}
+}
+}
+ {
+ SI opval = tmp_result;
+ SET_H_CR (FLD (f_op_B), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* current_loop_end: */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,current_loop_end) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDBI (EQSI (pc, GET_H_AUXR (((UINT) 3))), NOTBI (CPU (h_lbit)))) {
+{
+ {
+ SI opval = ADDSI (GET_H_CR (((UINT) 60)), -1);
+ SET_H_CR (((UINT) 60), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GET_H_CR (((UINT) 60))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (GET_H_AUXR (((UINT) 2)), 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = GET_H_AUXR (((UINT) 2));
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* current_loop_end_after_branch: */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,current_loop_end_after_branch) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (
+#ifdef SEM_IN_SWITCH
+pbb_br_type != SEM_BRANCH_UNTAKEN
+#else
+CPU_PBB_BR_NPC (current_cpu) != SEM_BRANCH_UNTAKEN
+#endif
+) {
+
+#ifdef SEM_IN_SWITCH
+npc = pbb_br_npc; br_type = pbb_br_type;
+#else
+npc = CPU_PBB_BR_NPC (current_cpu); br_type = CPU_PBB_BR_TYPE (current_cpu);
+#endif
+}
+ else if (ANDBI (EQSI (pc, GET_H_AUXR (((UINT) 3))), NOTBI (CPU (h_lbit)))) {
+{
+ {
+ SI opval = ADDSI (GET_H_CR (((UINT) 60)), -1);
+ SET_H_CR (((UINT) 60), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GET_H_CR (((UINT) 60))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (GET_H_AUXR (((UINT) 2)), 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = GET_H_AUXR (((UINT) 2));
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* arc600_current_loop_end_after_branch: */
+
+static SEM_PC
+SEM_FN_NAME (arc700f,arc600_current_loop_end_after_branch) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (
+#ifdef SEM_IN_SWITCH
+pbb_br_type != SEM_BRANCH_UNTAKEN
+#else
+CPU_PBB_BR_NPC (current_cpu) != SEM_BRANCH_UNTAKEN
+#endif
+) {
+{
+
+#ifdef SEM_IN_SWITCH
+npc = pbb_br_npc; br_type = pbb_br_type;
+#else
+npc = CPU_PBB_BR_NPC (current_cpu); br_type = CPU_PBB_BR_TYPE (current_cpu);
+#endif
+ {
+ SI opval = ADDSI (GET_H_CR (((UINT) 60)), -1);
+ SET_H_CR (((UINT) 60), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+}
+}
+ else if (ANDBI (EQSI (pc, GET_H_AUXR (((UINT) 3))), NOTBI (CPU (h_lbit)))) {
+{
+ {
+ SI opval = ADDSI (GET_H_CR (((UINT) 60)), -1);
+ SET_H_CR (((UINT) 60), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+if (GET_H_CR (((UINT) 60))) {
+if (ANDIF (GESI (SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)])), 0), ANDIF (CPU (h_e1), ANDSI (GET_H_AUXR (((UINT) 34)), 1)))) {
+{
+ {
+ SI opval = SUBSI (CPU_INSN_COUNT (current_cpu), CPU (h_timer_expire[((UINT) 0)]));
+ SET_H_AUXR (((UINT) 33), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+if (CPU (h_ubit)) {
+{
+ SI tmp_countp;
+ UHI tmp_count;
+ tmp_countp = ADDSI (ANDSI (SRLSI (GET_H_AUXR (((UINT) 2)), 1), -2), CPU (h_prof_offset[((UINT) 0)]));
+ tmp_count = ADDHI (GETMEMUHI (current_cpu, pc, tmp_countp), 1);
+if (tmp_count) {
+ {
+ UHI opval = tmp_count;
+ SETMEMUHI (current_cpu, pc, tmp_countp, opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+ else if (0) {
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+ else {
+{
+ {
+ SI opval = GET_H_AUXR (((UINT) 2));
+ SET_H_CR (((UINT) 29), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+ {
+ SI opval = GET_H_STATUS32 (((UINT) 0));
+ SET_H_AUXR (((UINT) 11), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "auxr", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ CPU (h_e1) = opval;
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "e1", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_AUXR (((UINT) 37)), 24);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+} else {
+ {
+ USI opval = GET_H_AUXR (((UINT) 2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* Table of all semantic fns. */
+
+static const struct sem_fn_desc sem_fns[] = {
+ { ARC700F_INSN_X_INVALID, SEM_FN_NAME (arc700f,x_invalid) },
+ { ARC700F_INSN_X_AFTER, SEM_FN_NAME (arc700f,x_after) },
+ { ARC700F_INSN_X_BEFORE, SEM_FN_NAME (arc700f,x_before) },
+ { ARC700F_INSN_X_CTI_CHAIN, SEM_FN_NAME (arc700f,x_cti_chain) },
+ { ARC700F_INSN_X_CHAIN, SEM_FN_NAME (arc700f,x_chain) },
+ { ARC700F_INSN_X_BEGIN, SEM_FN_NAME (arc700f,x_begin) },
+ { ARC700F_INSN_B_S, SEM_FN_NAME (arc700f,b_s) },
+ { ARC700F_INSN_BCC_S, SEM_FN_NAME (arc700f,bcc_s) },
+ { ARC700F_INSN_BRCC_S, SEM_FN_NAME (arc700f,brcc_s) },
+ { ARC700F_INSN_BCC_L, SEM_FN_NAME (arc700f,bcc_l) },
+ { ARC700F_INSN_BCC_L_D, SEM_FN_NAME (arc700f,bcc_l_d) },
+ { ARC700F_INSN_B_L, SEM_FN_NAME (arc700f,b_l) },
+ { ARC700F_INSN_B_L_D, SEM_FN_NAME (arc700f,b_l_d) },
+ { ARC700F_INSN_BRCC_RC, SEM_FN_NAME (arc700f,brcc_RC) },
+ { ARC700F_INSN_BRCC_RC_D, SEM_FN_NAME (arc700f,brcc_RC_d) },
+ { ARC700F_INSN_BRCC_U6, SEM_FN_NAME (arc700f,brcc_U6) },
+ { ARC700F_INSN_BRCC_U6_D, SEM_FN_NAME (arc700f,brcc_U6_d) },
+ { ARC700F_INSN_BL_S, SEM_FN_NAME (arc700f,bl_s) },
+ { ARC700F_INSN_BLCC, SEM_FN_NAME (arc700f,blcc) },
+ { ARC700F_INSN_BLCC_D, SEM_FN_NAME (arc700f,blcc_d) },
+ { ARC700F_INSN_BL, SEM_FN_NAME (arc700f,bl) },
+ { ARC700F_INSN_BL_D, SEM_FN_NAME (arc700f,bl_d) },
+ { ARC700F_INSN_LD_ABS, SEM_FN_NAME (arc700f,ld_abs) },
+ { ARC700F_INSN_LD__AW_ABS, SEM_FN_NAME (arc700f,ld__AW_abs) },
+ { ARC700F_INSN_LD_AB_ABS, SEM_FN_NAME (arc700f,ld_ab_abs) },
+ { ARC700F_INSN_LD_AS_ABS, SEM_FN_NAME (arc700f,ld_as_abs) },
+ { ARC700F_INSN_LD_ABC, SEM_FN_NAME (arc700f,ld_abc) },
+ { ARC700F_INSN_LD__AW_ABC, SEM_FN_NAME (arc700f,ld__AW_abc) },
+ { ARC700F_INSN_LD_AB_ABC, SEM_FN_NAME (arc700f,ld_ab_abc) },
+ { ARC700F_INSN_LD_AS_ABC, SEM_FN_NAME (arc700f,ld_as_abc) },
+ { ARC700F_INSN_LD_S_ABC, SEM_FN_NAME (arc700f,ld_s_abc) },
+ { ARC700F_INSN_LD_S_ABU, SEM_FN_NAME (arc700f,ld_s_abu) },
+ { ARC700F_INSN_LD_S_ABSP, SEM_FN_NAME (arc700f,ld_s_absp) },
+ { ARC700F_INSN_LD_S_GPREL, SEM_FN_NAME (arc700f,ld_s_gprel) },
+ { ARC700F_INSN_LD_S_PCREL, SEM_FN_NAME (arc700f,ld_s_pcrel) },
+ { ARC700F_INSN_LDB_ABS, SEM_FN_NAME (arc700f,ldb_abs) },
+ { ARC700F_INSN_LDB__AW_ABS, SEM_FN_NAME (arc700f,ldb__AW_abs) },
+ { ARC700F_INSN_LDB_AB_ABS, SEM_FN_NAME (arc700f,ldb_ab_abs) },
+ { ARC700F_INSN_LDB_AS_ABS, SEM_FN_NAME (arc700f,ldb_as_abs) },
+ { ARC700F_INSN_LDB_ABC, SEM_FN_NAME (arc700f,ldb_abc) },
+ { ARC700F_INSN_LDB__AW_ABC, SEM_FN_NAME (arc700f,ldb__AW_abc) },
+ { ARC700F_INSN_LDB_AB_ABC, SEM_FN_NAME (arc700f,ldb_ab_abc) },
+ { ARC700F_INSN_LDB_AS_ABC, SEM_FN_NAME (arc700f,ldb_as_abc) },
+ { ARC700F_INSN_LDB_S_ABC, SEM_FN_NAME (arc700f,ldb_s_abc) },
+ { ARC700F_INSN_LDB_S_ABU, SEM_FN_NAME (arc700f,ldb_s_abu) },
+ { ARC700F_INSN_LDB_S_ABSP, SEM_FN_NAME (arc700f,ldb_s_absp) },
+ { ARC700F_INSN_LDB_S_GPREL, SEM_FN_NAME (arc700f,ldb_s_gprel) },
+ { ARC700F_INSN_LDB_X_ABS, SEM_FN_NAME (arc700f,ldb_x_abs) },
+ { ARC700F_INSN_LDB__AW_X_ABS, SEM_FN_NAME (arc700f,ldb__AW_x_abs) },
+ { ARC700F_INSN_LDB_AB_X_ABS, SEM_FN_NAME (arc700f,ldb_ab_x_abs) },
+ { ARC700F_INSN_LDB_AS_X_ABS, SEM_FN_NAME (arc700f,ldb_as_x_abs) },
+ { ARC700F_INSN_LDB_X_ABC, SEM_FN_NAME (arc700f,ldb_x_abc) },
+ { ARC700F_INSN_LDB__AW_X_ABC, SEM_FN_NAME (arc700f,ldb__AW_x_abc) },
+ { ARC700F_INSN_LDB_AB_X_ABC, SEM_FN_NAME (arc700f,ldb_ab_x_abc) },
+ { ARC700F_INSN_LDB_AS_X_ABC, SEM_FN_NAME (arc700f,ldb_as_x_abc) },
+ { ARC700F_INSN_LDW_ABS, SEM_FN_NAME (arc700f,ldw_abs) },
+ { ARC700F_INSN_LDW__AW_ABS, SEM_FN_NAME (arc700f,ldw__AW_abs) },
+ { ARC700F_INSN_LDW_AB_ABS, SEM_FN_NAME (arc700f,ldw_ab_abs) },
+ { ARC700F_INSN_LDW_AS_ABS, SEM_FN_NAME (arc700f,ldw_as_abs) },
+ { ARC700F_INSN_LDW_ABC, SEM_FN_NAME (arc700f,ldw_abc) },
+ { ARC700F_INSN_LDW__AW_ABC, SEM_FN_NAME (arc700f,ldw__AW_abc) },
+ { ARC700F_INSN_LDW_AB_ABC, SEM_FN_NAME (arc700f,ldw_ab_abc) },
+ { ARC700F_INSN_LDW_AS_ABC, SEM_FN_NAME (arc700f,ldw_as_abc) },
+ { ARC700F_INSN_LDW_S_ABC, SEM_FN_NAME (arc700f,ldw_s_abc) },
+ { ARC700F_INSN_LDW_S_ABU, SEM_FN_NAME (arc700f,ldw_s_abu) },
+ { ARC700F_INSN_LDW_S_GPREL, SEM_FN_NAME (arc700f,ldw_s_gprel) },
+ { ARC700F_INSN_LDW_X_ABS, SEM_FN_NAME (arc700f,ldw_x_abs) },
+ { ARC700F_INSN_LDW__AW_X_ABS, SEM_FN_NAME (arc700f,ldw__AW_x_abs) },
+ { ARC700F_INSN_LDW_AB_X_ABS, SEM_FN_NAME (arc700f,ldw_ab_x_abs) },
+ { ARC700F_INSN_LDW_AS_X_ABS, SEM_FN_NAME (arc700f,ldw_as_x_abs) },
+ { ARC700F_INSN_LDW_X_ABC, SEM_FN_NAME (arc700f,ldw_x_abc) },
+ { ARC700F_INSN_LDW__AW_X_ABC, SEM_FN_NAME (arc700f,ldw__AW_x_abc) },
+ { ARC700F_INSN_LDW_AB_X_ABC, SEM_FN_NAME (arc700f,ldw_ab_x_abc) },
+ { ARC700F_INSN_LDW_AS_X_ABC, SEM_FN_NAME (arc700f,ldw_as_x_abc) },
+ { ARC700F_INSN_LDW_S_X_ABU, SEM_FN_NAME (arc700f,ldw_s_x_abu) },
+ { ARC700F_INSN_ST_ABS, SEM_FN_NAME (arc700f,st_abs) },
+ { ARC700F_INSN_ST__AW_ABS, SEM_FN_NAME (arc700f,st__AW_abs) },
+ { ARC700F_INSN_ST_AB_ABS, SEM_FN_NAME (arc700f,st_ab_abs) },
+ { ARC700F_INSN_ST_AS_ABS, SEM_FN_NAME (arc700f,st_as_abs) },
+ { ARC700F_INSN_ST_S_ABU, SEM_FN_NAME (arc700f,st_s_abu) },
+ { ARC700F_INSN_ST_S_ABSP, SEM_FN_NAME (arc700f,st_s_absp) },
+ { ARC700F_INSN_STB_ABS, SEM_FN_NAME (arc700f,stb_abs) },
+ { ARC700F_INSN_STB__AW_ABS, SEM_FN_NAME (arc700f,stb__AW_abs) },
+ { ARC700F_INSN_STB_AB_ABS, SEM_FN_NAME (arc700f,stb_ab_abs) },
+ { ARC700F_INSN_STB_AS_ABS, SEM_FN_NAME (arc700f,stb_as_abs) },
+ { ARC700F_INSN_STB_S_ABU, SEM_FN_NAME (arc700f,stb_s_abu) },
+ { ARC700F_INSN_STB_S_ABSP, SEM_FN_NAME (arc700f,stb_s_absp) },
+ { ARC700F_INSN_STW_ABS, SEM_FN_NAME (arc700f,stw_abs) },
+ { ARC700F_INSN_STW__AW_ABS, SEM_FN_NAME (arc700f,stw__AW_abs) },
+ { ARC700F_INSN_STW_AB_ABS, SEM_FN_NAME (arc700f,stw_ab_abs) },
+ { ARC700F_INSN_STW_AS_ABS, SEM_FN_NAME (arc700f,stw_as_abs) },
+ { ARC700F_INSN_STW_S_ABU, SEM_FN_NAME (arc700f,stw_s_abu) },
+ { ARC700F_INSN_ADD_L_S12__RA_, SEM_FN_NAME (arc700f,add_L_s12__RA_) },
+ { ARC700F_INSN_ADD_CCU6__RA_, SEM_FN_NAME (arc700f,add_ccu6__RA_) },
+ { ARC700F_INSN_ADD_L_U6__RA_, SEM_FN_NAME (arc700f,add_L_u6__RA_) },
+ { ARC700F_INSN_ADD_L_R_R__RA__RC, SEM_FN_NAME (arc700f,add_L_r_r__RA__RC) },
+ { ARC700F_INSN_ADD_CC__RA__RC, SEM_FN_NAME (arc700f,add_cc__RA__RC) },
+ { ARC700F_INSN_ADD_S_ABC, SEM_FN_NAME (arc700f,add_s_abc) },
+ { ARC700F_INSN_ADD_S_CBU3, SEM_FN_NAME (arc700f,add_s_cbu3) },
+ { ARC700F_INSN_ADD_S_MCAH, SEM_FN_NAME (arc700f,add_s_mcah) },
+ { ARC700F_INSN_ADD_S_ABSP, SEM_FN_NAME (arc700f,add_s_absp) },
+ { ARC700F_INSN_ADD_S_ASSPSP, SEM_FN_NAME (arc700f,add_s_asspsp) },
+ { ARC700F_INSN_ADD_S_GP, SEM_FN_NAME (arc700f,add_s_gp) },
+ { ARC700F_INSN_ADD_S_R_U7, SEM_FN_NAME (arc700f,add_s_r_u7) },
+ { ARC700F_INSN_ADC_L_S12__RA_, SEM_FN_NAME (arc700f,adc_L_s12__RA_) },
+ { ARC700F_INSN_ADC_CCU6__RA_, SEM_FN_NAME (arc700f,adc_ccu6__RA_) },
+ { ARC700F_INSN_ADC_L_U6__RA_, SEM_FN_NAME (arc700f,adc_L_u6__RA_) },
+ { ARC700F_INSN_ADC_L_R_R__RA__RC, SEM_FN_NAME (arc700f,adc_L_r_r__RA__RC) },
+ { ARC700F_INSN_ADC_CC__RA__RC, SEM_FN_NAME (arc700f,adc_cc__RA__RC) },
+ { ARC700F_INSN_SUB_L_S12__RA_, SEM_FN_NAME (arc700f,sub_L_s12__RA_) },
+ { ARC700F_INSN_SUB_CCU6__RA_, SEM_FN_NAME (arc700f,sub_ccu6__RA_) },
+ { ARC700F_INSN_SUB_L_U6__RA_, SEM_FN_NAME (arc700f,sub_L_u6__RA_) },
+ { ARC700F_INSN_SUB_L_R_R__RA__RC, SEM_FN_NAME (arc700f,sub_L_r_r__RA__RC) },
+ { ARC700F_INSN_SUB_CC__RA__RC, SEM_FN_NAME (arc700f,sub_cc__RA__RC) },
+ { ARC700F_INSN_SUB_S_CBU3, SEM_FN_NAME (arc700f,sub_s_cbu3) },
+ { ARC700F_INSN_I16_GO_SUB_S_GO, SEM_FN_NAME (arc700f,I16_GO_SUB_s_go) },
+ { ARC700F_INSN_SUB_S_GO_SUB_NE, SEM_FN_NAME (arc700f,sub_s_go_sub_ne) },
+ { ARC700F_INSN_SUB_S_SSB, SEM_FN_NAME (arc700f,sub_s_ssb) },
+ { ARC700F_INSN_SUB_S_ASSPSP, SEM_FN_NAME (arc700f,sub_s_asspsp) },
+ { ARC700F_INSN_SBC_L_S12__RA_, SEM_FN_NAME (arc700f,sbc_L_s12__RA_) },
+ { ARC700F_INSN_SBC_CCU6__RA_, SEM_FN_NAME (arc700f,sbc_ccu6__RA_) },
+ { ARC700F_INSN_SBC_L_U6__RA_, SEM_FN_NAME (arc700f,sbc_L_u6__RA_) },
+ { ARC700F_INSN_SBC_L_R_R__RA__RC, SEM_FN_NAME (arc700f,sbc_L_r_r__RA__RC) },
+ { ARC700F_INSN_SBC_CC__RA__RC, SEM_FN_NAME (arc700f,sbc_cc__RA__RC) },
+ { ARC700F_INSN_AND_L_S12__RA_, SEM_FN_NAME (arc700f,and_L_s12__RA_) },
+ { ARC700F_INSN_AND_CCU6__RA_, SEM_FN_NAME (arc700f,and_ccu6__RA_) },
+ { ARC700F_INSN_AND_L_U6__RA_, SEM_FN_NAME (arc700f,and_L_u6__RA_) },
+ { ARC700F_INSN_AND_L_R_R__RA__RC, SEM_FN_NAME (arc700f,and_L_r_r__RA__RC) },
+ { ARC700F_INSN_AND_CC__RA__RC, SEM_FN_NAME (arc700f,and_cc__RA__RC) },
+ { ARC700F_INSN_I16_GO_AND_S_GO, SEM_FN_NAME (arc700f,I16_GO_AND_s_go) },
+ { ARC700F_INSN_OR_L_S12__RA_, SEM_FN_NAME (arc700f,or_L_s12__RA_) },
+ { ARC700F_INSN_OR_CCU6__RA_, SEM_FN_NAME (arc700f,or_ccu6__RA_) },
+ { ARC700F_INSN_OR_L_U6__RA_, SEM_FN_NAME (arc700f,or_L_u6__RA_) },
+ { ARC700F_INSN_OR_L_R_R__RA__RC, SEM_FN_NAME (arc700f,or_L_r_r__RA__RC) },
+ { ARC700F_INSN_OR_CC__RA__RC, SEM_FN_NAME (arc700f,or_cc__RA__RC) },
+ { ARC700F_INSN_I16_GO_OR_S_GO, SEM_FN_NAME (arc700f,I16_GO_OR_s_go) },
+ { ARC700F_INSN_BIC_L_S12__RA_, SEM_FN_NAME (arc700f,bic_L_s12__RA_) },
+ { ARC700F_INSN_BIC_CCU6__RA_, SEM_FN_NAME (arc700f,bic_ccu6__RA_) },
+ { ARC700F_INSN_BIC_L_U6__RA_, SEM_FN_NAME (arc700f,bic_L_u6__RA_) },
+ { ARC700F_INSN_BIC_L_R_R__RA__RC, SEM_FN_NAME (arc700f,bic_L_r_r__RA__RC) },
+ { ARC700F_INSN_BIC_CC__RA__RC, SEM_FN_NAME (arc700f,bic_cc__RA__RC) },
+ { ARC700F_INSN_I16_GO_BIC_S_GO, SEM_FN_NAME (arc700f,I16_GO_BIC_s_go) },
+ { ARC700F_INSN_XOR_L_S12__RA_, SEM_FN_NAME (arc700f,xor_L_s12__RA_) },
+ { ARC700F_INSN_XOR_CCU6__RA_, SEM_FN_NAME (arc700f,xor_ccu6__RA_) },
+ { ARC700F_INSN_XOR_L_U6__RA_, SEM_FN_NAME (arc700f,xor_L_u6__RA_) },
+ { ARC700F_INSN_XOR_L_R_R__RA__RC, SEM_FN_NAME (arc700f,xor_L_r_r__RA__RC) },
+ { ARC700F_INSN_XOR_CC__RA__RC, SEM_FN_NAME (arc700f,xor_cc__RA__RC) },
+ { ARC700F_INSN_I16_GO_XOR_S_GO, SEM_FN_NAME (arc700f,I16_GO_XOR_s_go) },
+ { ARC700F_INSN_MAX_L_S12__RA_, SEM_FN_NAME (arc700f,max_L_s12__RA_) },
+ { ARC700F_INSN_MAX_CCU6__RA_, SEM_FN_NAME (arc700f,max_ccu6__RA_) },
+ { ARC700F_INSN_MAX_L_U6__RA_, SEM_FN_NAME (arc700f,max_L_u6__RA_) },
+ { ARC700F_INSN_MAX_L_R_R__RA__RC, SEM_FN_NAME (arc700f,max_L_r_r__RA__RC) },
+ { ARC700F_INSN_MAX_CC__RA__RC, SEM_FN_NAME (arc700f,max_cc__RA__RC) },
+ { ARC700F_INSN_MIN_L_S12__RA_, SEM_FN_NAME (arc700f,min_L_s12__RA_) },
+ { ARC700F_INSN_MIN_CCU6__RA_, SEM_FN_NAME (arc700f,min_ccu6__RA_) },
+ { ARC700F_INSN_MIN_L_U6__RA_, SEM_FN_NAME (arc700f,min_L_u6__RA_) },
+ { ARC700F_INSN_MIN_L_R_R__RA__RC, SEM_FN_NAME (arc700f,min_L_r_r__RA__RC) },
+ { ARC700F_INSN_MIN_CC__RA__RC, SEM_FN_NAME (arc700f,min_cc__RA__RC) },
+ { ARC700F_INSN_MOV_L_S12_, SEM_FN_NAME (arc700f,mov_L_s12_) },
+ { ARC700F_INSN_MOV_CCU6_, SEM_FN_NAME (arc700f,mov_ccu6_) },
+ { ARC700F_INSN_MOV_L_U6_, SEM_FN_NAME (arc700f,mov_L_u6_) },
+ { ARC700F_INSN_MOV_L_R_R__RC, SEM_FN_NAME (arc700f,mov_L_r_r__RC) },
+ { ARC700F_INSN_MOV_CC__RC, SEM_FN_NAME (arc700f,mov_cc__RC) },
+ { ARC700F_INSN_MOV_S_MCAH, SEM_FN_NAME (arc700f,mov_s_mcah) },
+ { ARC700F_INSN_MOV_S_MCAHB, SEM_FN_NAME (arc700f,mov_s_mcahb) },
+ { ARC700F_INSN_MOV_S_R_U7, SEM_FN_NAME (arc700f,mov_s_r_u7) },
+ { ARC700F_INSN_TST_L_S12_, SEM_FN_NAME (arc700f,tst_L_s12_) },
+ { ARC700F_INSN_TST_CCU6_, SEM_FN_NAME (arc700f,tst_ccu6_) },
+ { ARC700F_INSN_TST_L_U6_, SEM_FN_NAME (arc700f,tst_L_u6_) },
+ { ARC700F_INSN_TST_L_R_R__RC, SEM_FN_NAME (arc700f,tst_L_r_r__RC) },
+ { ARC700F_INSN_TST_CC__RC, SEM_FN_NAME (arc700f,tst_cc__RC) },
+ { ARC700F_INSN_TST_S_GO, SEM_FN_NAME (arc700f,tst_s_go) },
+ { ARC700F_INSN_CMP_L_S12_, SEM_FN_NAME (arc700f,cmp_L_s12_) },
+ { ARC700F_INSN_CMP_CCU6_, SEM_FN_NAME (arc700f,cmp_ccu6_) },
+ { ARC700F_INSN_CMP_L_U6_, SEM_FN_NAME (arc700f,cmp_L_u6_) },
+ { ARC700F_INSN_CMP_L_R_R__RC, SEM_FN_NAME (arc700f,cmp_L_r_r__RC) },
+ { ARC700F_INSN_CMP_CC__RC, SEM_FN_NAME (arc700f,cmp_cc__RC) },
+ { ARC700F_INSN_CMP_S_MCAH, SEM_FN_NAME (arc700f,cmp_s_mcah) },
+ { ARC700F_INSN_CMP_S_R_U7, SEM_FN_NAME (arc700f,cmp_s_r_u7) },
+ { ARC700F_INSN_RCMP_L_S12_, SEM_FN_NAME (arc700f,rcmp_L_s12_) },
+ { ARC700F_INSN_RCMP_CCU6_, SEM_FN_NAME (arc700f,rcmp_ccu6_) },
+ { ARC700F_INSN_RCMP_L_U6_, SEM_FN_NAME (arc700f,rcmp_L_u6_) },
+ { ARC700F_INSN_RCMP_L_R_R__RC, SEM_FN_NAME (arc700f,rcmp_L_r_r__RC) },
+ { ARC700F_INSN_RCMP_CC__RC, SEM_FN_NAME (arc700f,rcmp_cc__RC) },
+ { ARC700F_INSN_RSUB_L_S12__RA_, SEM_FN_NAME (arc700f,rsub_L_s12__RA_) },
+ { ARC700F_INSN_RSUB_CCU6__RA_, SEM_FN_NAME (arc700f,rsub_ccu6__RA_) },
+ { ARC700F_INSN_RSUB_L_U6__RA_, SEM_FN_NAME (arc700f,rsub_L_u6__RA_) },
+ { ARC700F_INSN_RSUB_L_R_R__RA__RC, SEM_FN_NAME (arc700f,rsub_L_r_r__RA__RC) },
+ { ARC700F_INSN_RSUB_CC__RA__RC, SEM_FN_NAME (arc700f,rsub_cc__RA__RC) },
+ { ARC700F_INSN_BSET_L_S12__RA_, SEM_FN_NAME (arc700f,bset_L_s12__RA_) },
+ { ARC700F_INSN_BSET_CCU6__RA_, SEM_FN_NAME (arc700f,bset_ccu6__RA_) },
+ { ARC700F_INSN_BSET_L_U6__RA_, SEM_FN_NAME (arc700f,bset_L_u6__RA_) },
+ { ARC700F_INSN_BSET_L_R_R__RA__RC, SEM_FN_NAME (arc700f,bset_L_r_r__RA__RC) },
+ { ARC700F_INSN_BSET_CC__RA__RC, SEM_FN_NAME (arc700f,bset_cc__RA__RC) },
+ { ARC700F_INSN_BSET_S_SSB, SEM_FN_NAME (arc700f,bset_s_ssb) },
+ { ARC700F_INSN_BCLR_L_S12__RA_, SEM_FN_NAME (arc700f,bclr_L_s12__RA_) },
+ { ARC700F_INSN_BCLR_CCU6__RA_, SEM_FN_NAME (arc700f,bclr_ccu6__RA_) },
+ { ARC700F_INSN_BCLR_L_U6__RA_, SEM_FN_NAME (arc700f,bclr_L_u6__RA_) },
+ { ARC700F_INSN_BCLR_L_R_R__RA__RC, SEM_FN_NAME (arc700f,bclr_L_r_r__RA__RC) },
+ { ARC700F_INSN_BCLR_CC__RA__RC, SEM_FN_NAME (arc700f,bclr_cc__RA__RC) },
+ { ARC700F_INSN_BCLR_S_SSB, SEM_FN_NAME (arc700f,bclr_s_ssb) },
+ { ARC700F_INSN_BTST_L_S12_, SEM_FN_NAME (arc700f,btst_L_s12_) },
+ { ARC700F_INSN_BTST_CCU6_, SEM_FN_NAME (arc700f,btst_ccu6_) },
+ { ARC700F_INSN_BTST_L_U6_, SEM_FN_NAME (arc700f,btst_L_u6_) },
+ { ARC700F_INSN_BTST_L_R_R__RC, SEM_FN_NAME (arc700f,btst_L_r_r__RC) },
+ { ARC700F_INSN_BTST_CC__RC, SEM_FN_NAME (arc700f,btst_cc__RC) },
+ { ARC700F_INSN_BTST_S_SSB, SEM_FN_NAME (arc700f,btst_s_ssb) },
+ { ARC700F_INSN_BXOR_L_S12__RA_, SEM_FN_NAME (arc700f,bxor_L_s12__RA_) },
+ { ARC700F_INSN_BXOR_CCU6__RA_, SEM_FN_NAME (arc700f,bxor_ccu6__RA_) },
+ { ARC700F_INSN_BXOR_L_U6__RA_, SEM_FN_NAME (arc700f,bxor_L_u6__RA_) },
+ { ARC700F_INSN_BXOR_L_R_R__RA__RC, SEM_FN_NAME (arc700f,bxor_L_r_r__RA__RC) },
+ { ARC700F_INSN_BXOR_CC__RA__RC, SEM_FN_NAME (arc700f,bxor_cc__RA__RC) },
+ { ARC700F_INSN_BMSK_L_S12__RA_, SEM_FN_NAME (arc700f,bmsk_L_s12__RA_) },
+ { ARC700F_INSN_BMSK_CCU6__RA_, SEM_FN_NAME (arc700f,bmsk_ccu6__RA_) },
+ { ARC700F_INSN_BMSK_L_U6__RA_, SEM_FN_NAME (arc700f,bmsk_L_u6__RA_) },
+ { ARC700F_INSN_BMSK_L_R_R__RA__RC, SEM_FN_NAME (arc700f,bmsk_L_r_r__RA__RC) },
+ { ARC700F_INSN_BMSK_CC__RA__RC, SEM_FN_NAME (arc700f,bmsk_cc__RA__RC) },
+ { ARC700F_INSN_BMSK_S_SSB, SEM_FN_NAME (arc700f,bmsk_s_ssb) },
+ { ARC700F_INSN_ADD1_L_S12__RA_, SEM_FN_NAME (arc700f,add1_L_s12__RA_) },
+ { ARC700F_INSN_ADD1_CCU6__RA_, SEM_FN_NAME (arc700f,add1_ccu6__RA_) },
+ { ARC700F_INSN_ADD1_L_U6__RA_, SEM_FN_NAME (arc700f,add1_L_u6__RA_) },
+ { ARC700F_INSN_ADD1_L_R_R__RA__RC, SEM_FN_NAME (arc700f,add1_L_r_r__RA__RC) },
+ { ARC700F_INSN_ADD1_CC__RA__RC, SEM_FN_NAME (arc700f,add1_cc__RA__RC) },
+ { ARC700F_INSN_I16_GO_ADD1_S_GO, SEM_FN_NAME (arc700f,I16_GO_ADD1_s_go) },
+ { ARC700F_INSN_ADD2_L_S12__RA_, SEM_FN_NAME (arc700f,add2_L_s12__RA_) },
+ { ARC700F_INSN_ADD2_CCU6__RA_, SEM_FN_NAME (arc700f,add2_ccu6__RA_) },
+ { ARC700F_INSN_ADD2_L_U6__RA_, SEM_FN_NAME (arc700f,add2_L_u6__RA_) },
+ { ARC700F_INSN_ADD2_L_R_R__RA__RC, SEM_FN_NAME (arc700f,add2_L_r_r__RA__RC) },
+ { ARC700F_INSN_ADD2_CC__RA__RC, SEM_FN_NAME (arc700f,add2_cc__RA__RC) },
+ { ARC700F_INSN_I16_GO_ADD2_S_GO, SEM_FN_NAME (arc700f,I16_GO_ADD2_s_go) },
+ { ARC700F_INSN_ADD3_L_S12__RA_, SEM_FN_NAME (arc700f,add3_L_s12__RA_) },
+ { ARC700F_INSN_ADD3_CCU6__RA_, SEM_FN_NAME (arc700f,add3_ccu6__RA_) },
+ { ARC700F_INSN_ADD3_L_U6__RA_, SEM_FN_NAME (arc700f,add3_L_u6__RA_) },
+ { ARC700F_INSN_ADD3_L_R_R__RA__RC, SEM_FN_NAME (arc700f,add3_L_r_r__RA__RC) },
+ { ARC700F_INSN_ADD3_CC__RA__RC, SEM_FN_NAME (arc700f,add3_cc__RA__RC) },
+ { ARC700F_INSN_I16_GO_ADD3_S_GO, SEM_FN_NAME (arc700f,I16_GO_ADD3_s_go) },
+ { ARC700F_INSN_SUB1_L_S12__RA_, SEM_FN_NAME (arc700f,sub1_L_s12__RA_) },
+ { ARC700F_INSN_SUB1_CCU6__RA_, SEM_FN_NAME (arc700f,sub1_ccu6__RA_) },
+ { ARC700F_INSN_SUB1_L_U6__RA_, SEM_FN_NAME (arc700f,sub1_L_u6__RA_) },
+ { ARC700F_INSN_SUB1_L_R_R__RA__RC, SEM_FN_NAME (arc700f,sub1_L_r_r__RA__RC) },
+ { ARC700F_INSN_SUB1_CC__RA__RC, SEM_FN_NAME (arc700f,sub1_cc__RA__RC) },
+ { ARC700F_INSN_SUB2_L_S12__RA_, SEM_FN_NAME (arc700f,sub2_L_s12__RA_) },
+ { ARC700F_INSN_SUB2_CCU6__RA_, SEM_FN_NAME (arc700f,sub2_ccu6__RA_) },
+ { ARC700F_INSN_SUB2_L_U6__RA_, SEM_FN_NAME (arc700f,sub2_L_u6__RA_) },
+ { ARC700F_INSN_SUB2_L_R_R__RA__RC, SEM_FN_NAME (arc700f,sub2_L_r_r__RA__RC) },
+ { ARC700F_INSN_SUB2_CC__RA__RC, SEM_FN_NAME (arc700f,sub2_cc__RA__RC) },
+ { ARC700F_INSN_SUB3_L_S12__RA_, SEM_FN_NAME (arc700f,sub3_L_s12__RA_) },
+ { ARC700F_INSN_SUB3_CCU6__RA_, SEM_FN_NAME (arc700f,sub3_ccu6__RA_) },
+ { ARC700F_INSN_SUB3_L_U6__RA_, SEM_FN_NAME (arc700f,sub3_L_u6__RA_) },
+ { ARC700F_INSN_SUB3_L_R_R__RA__RC, SEM_FN_NAME (arc700f,sub3_L_r_r__RA__RC) },
+ { ARC700F_INSN_SUB3_CC__RA__RC, SEM_FN_NAME (arc700f,sub3_cc__RA__RC) },
+ { ARC700F_INSN_MPY_L_S12__RA_, SEM_FN_NAME (arc700f,mpy_L_s12__RA_) },
+ { ARC700F_INSN_MPY_CCU6__RA_, SEM_FN_NAME (arc700f,mpy_ccu6__RA_) },
+ { ARC700F_INSN_MPY_L_U6__RA_, SEM_FN_NAME (arc700f,mpy_L_u6__RA_) },
+ { ARC700F_INSN_MPY_L_R_R__RA__RC, SEM_FN_NAME (arc700f,mpy_L_r_r__RA__RC) },
+ { ARC700F_INSN_MPY_CC__RA__RC, SEM_FN_NAME (arc700f,mpy_cc__RA__RC) },
+ { ARC700F_INSN_MPYH_L_S12__RA_, SEM_FN_NAME (arc700f,mpyh_L_s12__RA_) },
+ { ARC700F_INSN_MPYH_CCU6__RA_, SEM_FN_NAME (arc700f,mpyh_ccu6__RA_) },
+ { ARC700F_INSN_MPYH_L_U6__RA_, SEM_FN_NAME (arc700f,mpyh_L_u6__RA_) },
+ { ARC700F_INSN_MPYH_L_R_R__RA__RC, SEM_FN_NAME (arc700f,mpyh_L_r_r__RA__RC) },
+ { ARC700F_INSN_MPYH_CC__RA__RC, SEM_FN_NAME (arc700f,mpyh_cc__RA__RC) },
+ { ARC700F_INSN_MPYHU_L_S12__RA_, SEM_FN_NAME (arc700f,mpyhu_L_s12__RA_) },
+ { ARC700F_INSN_MPYHU_CCU6__RA_, SEM_FN_NAME (arc700f,mpyhu_ccu6__RA_) },
+ { ARC700F_INSN_MPYHU_L_U6__RA_, SEM_FN_NAME (arc700f,mpyhu_L_u6__RA_) },
+ { ARC700F_INSN_MPYHU_L_R_R__RA__RC, SEM_FN_NAME (arc700f,mpyhu_L_r_r__RA__RC) },
+ { ARC700F_INSN_MPYHU_CC__RA__RC, SEM_FN_NAME (arc700f,mpyhu_cc__RA__RC) },
+ { ARC700F_INSN_MPYU_L_S12__RA_, SEM_FN_NAME (arc700f,mpyu_L_s12__RA_) },
+ { ARC700F_INSN_MPYU_CCU6__RA_, SEM_FN_NAME (arc700f,mpyu_ccu6__RA_) },
+ { ARC700F_INSN_MPYU_L_U6__RA_, SEM_FN_NAME (arc700f,mpyu_L_u6__RA_) },
+ { ARC700F_INSN_MPYU_L_R_R__RA__RC, SEM_FN_NAME (arc700f,mpyu_L_r_r__RA__RC) },
+ { ARC700F_INSN_MPYU_CC__RA__RC, SEM_FN_NAME (arc700f,mpyu_cc__RA__RC) },
+ { ARC700F_INSN_J_L_R_R___RC_NOILINK_, SEM_FN_NAME (arc700f,j_L_r_r___RC_noilink_) },
+ { ARC700F_INSN_J_CC___RC_NOILINK_, SEM_FN_NAME (arc700f,j_cc___RC_noilink_) },
+ { ARC700F_INSN_J_L_R_R___RC_ILINK_, SEM_FN_NAME (arc700f,j_L_r_r___RC_ilink_) },
+ { ARC700F_INSN_J_CC___RC_ILINK_, SEM_FN_NAME (arc700f,j_cc___RC_ilink_) },
+ { ARC700F_INSN_J_L_S12_, SEM_FN_NAME (arc700f,j_L_s12_) },
+ { ARC700F_INSN_J_CCU6_, SEM_FN_NAME (arc700f,j_ccu6_) },
+ { ARC700F_INSN_J_L_U6_, SEM_FN_NAME (arc700f,j_L_u6_) },
+ { ARC700F_INSN_J_S, SEM_FN_NAME (arc700f,j_s) },
+ { ARC700F_INSN_J_S__S, SEM_FN_NAME (arc700f,j_s__S) },
+ { ARC700F_INSN_J_SEQ__S, SEM_FN_NAME (arc700f,j_seq__S) },
+ { ARC700F_INSN_J_SNE__S, SEM_FN_NAME (arc700f,j_sne__S) },
+ { ARC700F_INSN_J_L_S12_D_, SEM_FN_NAME (arc700f,j_L_s12_d_) },
+ { ARC700F_INSN_J_CCU6_D_, SEM_FN_NAME (arc700f,j_ccu6_d_) },
+ { ARC700F_INSN_J_L_U6_D_, SEM_FN_NAME (arc700f,j_L_u6_d_) },
+ { ARC700F_INSN_J_L_R_R_D___RC_, SEM_FN_NAME (arc700f,j_L_r_r_d___RC_) },
+ { ARC700F_INSN_J_CC_D___RC_, SEM_FN_NAME (arc700f,j_cc_d___RC_) },
+ { ARC700F_INSN_J_S_D, SEM_FN_NAME (arc700f,j_s_d) },
+ { ARC700F_INSN_J_S__S_D, SEM_FN_NAME (arc700f,j_s__S_d) },
+ { ARC700F_INSN_JL_L_S12_, SEM_FN_NAME (arc700f,jl_L_s12_) },
+ { ARC700F_INSN_JL_CCU6_, SEM_FN_NAME (arc700f,jl_ccu6_) },
+ { ARC700F_INSN_JL_L_U6_, SEM_FN_NAME (arc700f,jl_L_u6_) },
+ { ARC700F_INSN_JL_S, SEM_FN_NAME (arc700f,jl_s) },
+ { ARC700F_INSN_JL_L_R_R___RC_NOILINK_, SEM_FN_NAME (arc700f,jl_L_r_r___RC_noilink_) },
+ { ARC700F_INSN_JL_CC___RC_NOILINK_, SEM_FN_NAME (arc700f,jl_cc___RC_noilink_) },
+ { ARC700F_INSN_JL_L_S12_D_, SEM_FN_NAME (arc700f,jl_L_s12_d_) },
+ { ARC700F_INSN_JL_CCU6_D_, SEM_FN_NAME (arc700f,jl_ccu6_d_) },
+ { ARC700F_INSN_JL_L_U6_D_, SEM_FN_NAME (arc700f,jl_L_u6_d_) },
+ { ARC700F_INSN_JL_L_R_R_D___RC_, SEM_FN_NAME (arc700f,jl_L_r_r_d___RC_) },
+ { ARC700F_INSN_JL_CC_D___RC_, SEM_FN_NAME (arc700f,jl_cc_d___RC_) },
+ { ARC700F_INSN_JL_S_D, SEM_FN_NAME (arc700f,jl_s_d) },
+ { ARC700F_INSN_LP_L_S12_, SEM_FN_NAME (arc700f,lp_L_s12_) },
+ { ARC700F_INSN_LPCC_CCU6, SEM_FN_NAME (arc700f,lpcc_ccu6) },
+ { ARC700F_INSN_FLAG_L_S12_, SEM_FN_NAME (arc700f,flag_L_s12_) },
+ { ARC700F_INSN_FLAG_CCU6_, SEM_FN_NAME (arc700f,flag_ccu6_) },
+ { ARC700F_INSN_FLAG_L_U6_, SEM_FN_NAME (arc700f,flag_L_u6_) },
+ { ARC700F_INSN_FLAG_L_R_R__RC, SEM_FN_NAME (arc700f,flag_L_r_r__RC) },
+ { ARC700F_INSN_FLAG_CC__RC, SEM_FN_NAME (arc700f,flag_cc__RC) },
+ { ARC700F_INSN_LR_L_R_R___RC_, SEM_FN_NAME (arc700f,lr_L_r_r___RC_) },
+ { ARC700F_INSN_LR_L_S12_, SEM_FN_NAME (arc700f,lr_L_s12_) },
+ { ARC700F_INSN_LR_L_U6_, SEM_FN_NAME (arc700f,lr_L_u6_) },
+ { ARC700F_INSN_SR_L_R_R___RC_, SEM_FN_NAME (arc700f,sr_L_r_r___RC_) },
+ { ARC700F_INSN_SR_L_S12_, SEM_FN_NAME (arc700f,sr_L_s12_) },
+ { ARC700F_INSN_SR_L_U6_, SEM_FN_NAME (arc700f,sr_L_u6_) },
+ { ARC700F_INSN_ASL_L_R_R__RC, SEM_FN_NAME (arc700f,asl_L_r_r__RC) },
+ { ARC700F_INSN_ASL_L_U6_, SEM_FN_NAME (arc700f,asl_L_u6_) },
+ { ARC700F_INSN_I16_GO_ASL_S_GO, SEM_FN_NAME (arc700f,I16_GO_ASL_s_go) },
+ { ARC700F_INSN_ASR_L_R_R__RC, SEM_FN_NAME (arc700f,asr_L_r_r__RC) },
+ { ARC700F_INSN_ASR_L_U6_, SEM_FN_NAME (arc700f,asr_L_u6_) },
+ { ARC700F_INSN_I16_GO_ASR_S_GO, SEM_FN_NAME (arc700f,I16_GO_ASR_s_go) },
+ { ARC700F_INSN_LSR_L_R_R__RC, SEM_FN_NAME (arc700f,lsr_L_r_r__RC) },
+ { ARC700F_INSN_LSR_L_U6_, SEM_FN_NAME (arc700f,lsr_L_u6_) },
+ { ARC700F_INSN_I16_GO_LSR_S_GO, SEM_FN_NAME (arc700f,I16_GO_LSR_s_go) },
+ { ARC700F_INSN_ROR_L_R_R__RC, SEM_FN_NAME (arc700f,ror_L_r_r__RC) },
+ { ARC700F_INSN_ROR_L_U6_, SEM_FN_NAME (arc700f,ror_L_u6_) },
+ { ARC700F_INSN_RRC_L_R_R__RC, SEM_FN_NAME (arc700f,rrc_L_r_r__RC) },
+ { ARC700F_INSN_RRC_L_U6_, SEM_FN_NAME (arc700f,rrc_L_u6_) },
+ { ARC700F_INSN_SEXB_L_R_R__RC, SEM_FN_NAME (arc700f,sexb_L_r_r__RC) },
+ { ARC700F_INSN_SEXB_L_U6_, SEM_FN_NAME (arc700f,sexb_L_u6_) },
+ { ARC700F_INSN_I16_GO_SEXB_S_GO, SEM_FN_NAME (arc700f,I16_GO_SEXB_s_go) },
+ { ARC700F_INSN_SEXW_L_R_R__RC, SEM_FN_NAME (arc700f,sexw_L_r_r__RC) },
+ { ARC700F_INSN_SEXW_L_U6_, SEM_FN_NAME (arc700f,sexw_L_u6_) },
+ { ARC700F_INSN_I16_GO_SEXW_S_GO, SEM_FN_NAME (arc700f,I16_GO_SEXW_s_go) },
+ { ARC700F_INSN_EXTB_L_R_R__RC, SEM_FN_NAME (arc700f,extb_L_r_r__RC) },
+ { ARC700F_INSN_EXTB_L_U6_, SEM_FN_NAME (arc700f,extb_L_u6_) },
+ { ARC700F_INSN_I16_GO_EXTB_S_GO, SEM_FN_NAME (arc700f,I16_GO_EXTB_s_go) },
+ { ARC700F_INSN_EXTW_L_R_R__RC, SEM_FN_NAME (arc700f,extw_L_r_r__RC) },
+ { ARC700F_INSN_EXTW_L_U6_, SEM_FN_NAME (arc700f,extw_L_u6_) },
+ { ARC700F_INSN_I16_GO_EXTW_S_GO, SEM_FN_NAME (arc700f,I16_GO_EXTW_s_go) },
+ { ARC700F_INSN_ABS_L_R_R__RC, SEM_FN_NAME (arc700f,abs_L_r_r__RC) },
+ { ARC700F_INSN_ABS_L_U6_, SEM_FN_NAME (arc700f,abs_L_u6_) },
+ { ARC700F_INSN_I16_GO_ABS_S_GO, SEM_FN_NAME (arc700f,I16_GO_ABS_s_go) },
+ { ARC700F_INSN_NOT_L_R_R__RC, SEM_FN_NAME (arc700f,not_L_r_r__RC) },
+ { ARC700F_INSN_NOT_L_U6_, SEM_FN_NAME (arc700f,not_L_u6_) },
+ { ARC700F_INSN_I16_GO_NOT_S_GO, SEM_FN_NAME (arc700f,I16_GO_NOT_s_go) },
+ { ARC700F_INSN_RLC_L_R_R__RC, SEM_FN_NAME (arc700f,rlc_L_r_r__RC) },
+ { ARC700F_INSN_RLC_L_U6_, SEM_FN_NAME (arc700f,rlc_L_u6_) },
+ { ARC700F_INSN_EX_L_R_R__RC, SEM_FN_NAME (arc700f,ex_L_r_r__RC) },
+ { ARC700F_INSN_EX_L_U6_, SEM_FN_NAME (arc700f,ex_L_u6_) },
+ { ARC700F_INSN_I16_GO_NEG_S_GO, SEM_FN_NAME (arc700f,I16_GO_NEG_s_go) },
+ { ARC700F_INSN_SWI, SEM_FN_NAME (arc700f,swi) },
+ { ARC700F_INSN_TRAP_S, SEM_FN_NAME (arc700f,trap_s) },
+ { ARC700F_INSN_BRK, SEM_FN_NAME (arc700f,brk) },
+ { ARC700F_INSN_BRK_S, SEM_FN_NAME (arc700f,brk_s) },
+ { ARC700F_INSN_ASL_L_S12__RA_, SEM_FN_NAME (arc700f,asl_L_s12__RA_) },
+ { ARC700F_INSN_ASL_CCU6__RA_, SEM_FN_NAME (arc700f,asl_ccu6__RA_) },
+ { ARC700F_INSN_ASL_L_U6__RA_, SEM_FN_NAME (arc700f,asl_L_u6__RA_) },
+ { ARC700F_INSN_ASL_L_R_R__RA__RC, SEM_FN_NAME (arc700f,asl_L_r_r__RA__RC) },
+ { ARC700F_INSN_ASL_CC__RA__RC, SEM_FN_NAME (arc700f,asl_cc__RA__RC) },
+ { ARC700F_INSN_ASL_S_CBU3, SEM_FN_NAME (arc700f,asl_s_cbu3) },
+ { ARC700F_INSN_ASL_S_SSB, SEM_FN_NAME (arc700f,asl_s_ssb) },
+ { ARC700F_INSN_I16_GO_ASLM_S_GO, SEM_FN_NAME (arc700f,I16_GO_ASLM_s_go) },
+ { ARC700F_INSN_LSR_L_S12__RA_, SEM_FN_NAME (arc700f,lsr_L_s12__RA_) },
+ { ARC700F_INSN_LSR_CCU6__RA_, SEM_FN_NAME (arc700f,lsr_ccu6__RA_) },
+ { ARC700F_INSN_LSR_L_U6__RA_, SEM_FN_NAME (arc700f,lsr_L_u6__RA_) },
+ { ARC700F_INSN_LSR_L_R_R__RA__RC, SEM_FN_NAME (arc700f,lsr_L_r_r__RA__RC) },
+ { ARC700F_INSN_LSR_CC__RA__RC, SEM_FN_NAME (arc700f,lsr_cc__RA__RC) },
+ { ARC700F_INSN_LSR_S_SSB, SEM_FN_NAME (arc700f,lsr_s_ssb) },
+ { ARC700F_INSN_I16_GO_LSRM_S_GO, SEM_FN_NAME (arc700f,I16_GO_LSRM_s_go) },
+ { ARC700F_INSN_ASR_L_S12__RA_, SEM_FN_NAME (arc700f,asr_L_s12__RA_) },
+ { ARC700F_INSN_ASR_CCU6__RA_, SEM_FN_NAME (arc700f,asr_ccu6__RA_) },
+ { ARC700F_INSN_ASR_L_U6__RA_, SEM_FN_NAME (arc700f,asr_L_u6__RA_) },
+ { ARC700F_INSN_ASR_L_R_R__RA__RC, SEM_FN_NAME (arc700f,asr_L_r_r__RA__RC) },
+ { ARC700F_INSN_ASR_CC__RA__RC, SEM_FN_NAME (arc700f,asr_cc__RA__RC) },
+ { ARC700F_INSN_ASR_S_CBU3, SEM_FN_NAME (arc700f,asr_s_cbu3) },
+ { ARC700F_INSN_ASR_S_SSB, SEM_FN_NAME (arc700f,asr_s_ssb) },
+ { ARC700F_INSN_I16_GO_ASRM_S_GO, SEM_FN_NAME (arc700f,I16_GO_ASRM_s_go) },
+ { ARC700F_INSN_ROR_L_S12__RA_, SEM_FN_NAME (arc700f,ror_L_s12__RA_) },
+ { ARC700F_INSN_ROR_CCU6__RA_, SEM_FN_NAME (arc700f,ror_ccu6__RA_) },
+ { ARC700F_INSN_ROR_L_U6__RA_, SEM_FN_NAME (arc700f,ror_L_u6__RA_) },
+ { ARC700F_INSN_ROR_L_R_R__RA__RC, SEM_FN_NAME (arc700f,ror_L_r_r__RA__RC) },
+ { ARC700F_INSN_ROR_CC__RA__RC, SEM_FN_NAME (arc700f,ror_cc__RA__RC) },
+ { ARC700F_INSN_MUL64_L_S12_, SEM_FN_NAME (arc700f,mul64_L_s12_) },
+ { ARC700F_INSN_MUL64_CCU6_, SEM_FN_NAME (arc700f,mul64_ccu6_) },
+ { ARC700F_INSN_MUL64_L_U6_, SEM_FN_NAME (arc700f,mul64_L_u6_) },
+ { ARC700F_INSN_MUL64_L_R_R__RC, SEM_FN_NAME (arc700f,mul64_L_r_r__RC) },
+ { ARC700F_INSN_MUL64_CC__RC, SEM_FN_NAME (arc700f,mul64_cc__RC) },
+ { ARC700F_INSN_MUL64_S_GO, SEM_FN_NAME (arc700f,mul64_s_go) },
+ { ARC700F_INSN_MULU64_L_S12_, SEM_FN_NAME (arc700f,mulu64_L_s12_) },
+ { ARC700F_INSN_MULU64_CCU6_, SEM_FN_NAME (arc700f,mulu64_ccu6_) },
+ { ARC700F_INSN_MULU64_L_U6_, SEM_FN_NAME (arc700f,mulu64_L_u6_) },
+ { ARC700F_INSN_MULU64_L_R_R__RC, SEM_FN_NAME (arc700f,mulu64_L_r_r__RC) },
+ { ARC700F_INSN_MULU64_CC__RC, SEM_FN_NAME (arc700f,mulu64_cc__RC) },
+ { ARC700F_INSN_ADDS_L_S12__RA_, SEM_FN_NAME (arc700f,adds_L_s12__RA_) },
+ { ARC700F_INSN_ADDS_CCU6__RA_, SEM_FN_NAME (arc700f,adds_ccu6__RA_) },
+ { ARC700F_INSN_ADDS_L_U6__RA_, SEM_FN_NAME (arc700f,adds_L_u6__RA_) },
+ { ARC700F_INSN_ADDS_L_R_R__RA__RC, SEM_FN_NAME (arc700f,adds_L_r_r__RA__RC) },
+ { ARC700F_INSN_ADDS_CC__RA__RC, SEM_FN_NAME (arc700f,adds_cc__RA__RC) },
+ { ARC700F_INSN_SUBS_L_S12__RA_, SEM_FN_NAME (arc700f,subs_L_s12__RA_) },
+ { ARC700F_INSN_SUBS_CCU6__RA_, SEM_FN_NAME (arc700f,subs_ccu6__RA_) },
+ { ARC700F_INSN_SUBS_L_U6__RA_, SEM_FN_NAME (arc700f,subs_L_u6__RA_) },
+ { ARC700F_INSN_SUBS_L_R_R__RA__RC, SEM_FN_NAME (arc700f,subs_L_r_r__RA__RC) },
+ { ARC700F_INSN_SUBS_CC__RA__RC, SEM_FN_NAME (arc700f,subs_cc__RA__RC) },
+ { ARC700F_INSN_DIVAW_L_S12__RA_, SEM_FN_NAME (arc700f,divaw_L_s12__RA_) },
+ { ARC700F_INSN_DIVAW_CCU6__RA_, SEM_FN_NAME (arc700f,divaw_ccu6__RA_) },
+ { ARC700F_INSN_DIVAW_L_U6__RA_, SEM_FN_NAME (arc700f,divaw_L_u6__RA_) },
+ { ARC700F_INSN_DIVAW_L_R_R__RA__RC, SEM_FN_NAME (arc700f,divaw_L_r_r__RA__RC) },
+ { ARC700F_INSN_DIVAW_CC__RA__RC, SEM_FN_NAME (arc700f,divaw_cc__RA__RC) },
+ { ARC700F_INSN_ASLS_L_S12__RA_, SEM_FN_NAME (arc700f,asls_L_s12__RA_) },
+ { ARC700F_INSN_ASLS_CCU6__RA_, SEM_FN_NAME (arc700f,asls_ccu6__RA_) },
+ { ARC700F_INSN_ASLS_L_U6__RA_, SEM_FN_NAME (arc700f,asls_L_u6__RA_) },
+ { ARC700F_INSN_ASLS_L_R_R__RA__RC, SEM_FN_NAME (arc700f,asls_L_r_r__RA__RC) },
+ { ARC700F_INSN_ASLS_CC__RA__RC, SEM_FN_NAME (arc700f,asls_cc__RA__RC) },
+ { ARC700F_INSN_ASRS_L_S12__RA_, SEM_FN_NAME (arc700f,asrs_L_s12__RA_) },
+ { ARC700F_INSN_ASRS_CCU6__RA_, SEM_FN_NAME (arc700f,asrs_ccu6__RA_) },
+ { ARC700F_INSN_ASRS_L_U6__RA_, SEM_FN_NAME (arc700f,asrs_L_u6__RA_) },
+ { ARC700F_INSN_ASRS_L_R_R__RA__RC, SEM_FN_NAME (arc700f,asrs_L_r_r__RA__RC) },
+ { ARC700F_INSN_ASRS_CC__RA__RC, SEM_FN_NAME (arc700f,asrs_cc__RA__RC) },
+ { ARC700F_INSN_ADDSDW_L_S12__RA_, SEM_FN_NAME (arc700f,addsdw_L_s12__RA_) },
+ { ARC700F_INSN_ADDSDW_CCU6__RA_, SEM_FN_NAME (arc700f,addsdw_ccu6__RA_) },
+ { ARC700F_INSN_ADDSDW_L_U6__RA_, SEM_FN_NAME (arc700f,addsdw_L_u6__RA_) },
+ { ARC700F_INSN_ADDSDW_L_R_R__RA__RC, SEM_FN_NAME (arc700f,addsdw_L_r_r__RA__RC) },
+ { ARC700F_INSN_ADDSDW_CC__RA__RC, SEM_FN_NAME (arc700f,addsdw_cc__RA__RC) },
+ { ARC700F_INSN_SUBSDW_L_S12__RA_, SEM_FN_NAME (arc700f,subsdw_L_s12__RA_) },
+ { ARC700F_INSN_SUBSDW_CCU6__RA_, SEM_FN_NAME (arc700f,subsdw_ccu6__RA_) },
+ { ARC700F_INSN_SUBSDW_L_U6__RA_, SEM_FN_NAME (arc700f,subsdw_L_u6__RA_) },
+ { ARC700F_INSN_SUBSDW_L_R_R__RA__RC, SEM_FN_NAME (arc700f,subsdw_L_r_r__RA__RC) },
+ { ARC700F_INSN_SUBSDW_CC__RA__RC, SEM_FN_NAME (arc700f,subsdw_cc__RA__RC) },
+ { ARC700F_INSN_SWAP_L_R_R__RC, SEM_FN_NAME (arc700f,swap_L_r_r__RC) },
+ { ARC700F_INSN_SWAP_L_U6_, SEM_FN_NAME (arc700f,swap_L_u6_) },
+ { ARC700F_INSN_NORM_L_R_R__RC, SEM_FN_NAME (arc700f,norm_L_r_r__RC) },
+ { ARC700F_INSN_NORM_L_U6_, SEM_FN_NAME (arc700f,norm_L_u6_) },
+ { ARC700F_INSN_RND16_L_R_R__RC, SEM_FN_NAME (arc700f,rnd16_L_r_r__RC) },
+ { ARC700F_INSN_RND16_L_U6_, SEM_FN_NAME (arc700f,rnd16_L_u6_) },
+ { ARC700F_INSN_ABSSW_L_R_R__RC, SEM_FN_NAME (arc700f,abssw_L_r_r__RC) },
+ { ARC700F_INSN_ABSSW_L_U6_, SEM_FN_NAME (arc700f,abssw_L_u6_) },
+ { ARC700F_INSN_ABSS_L_R_R__RC, SEM_FN_NAME (arc700f,abss_L_r_r__RC) },
+ { ARC700F_INSN_ABSS_L_U6_, SEM_FN_NAME (arc700f,abss_L_u6_) },
+ { ARC700F_INSN_NEGSW_L_R_R__RC, SEM_FN_NAME (arc700f,negsw_L_r_r__RC) },
+ { ARC700F_INSN_NEGSW_L_U6_, SEM_FN_NAME (arc700f,negsw_L_u6_) },
+ { ARC700F_INSN_NEGS_L_R_R__RC, SEM_FN_NAME (arc700f,negs_L_r_r__RC) },
+ { ARC700F_INSN_NEGS_L_U6_, SEM_FN_NAME (arc700f,negs_L_u6_) },
+ { ARC700F_INSN_NORMW_L_R_R__RC, SEM_FN_NAME (arc700f,normw_L_r_r__RC) },
+ { ARC700F_INSN_NORMW_L_U6_, SEM_FN_NAME (arc700f,normw_L_u6_) },
+ { ARC700F_INSN_NOP_S, SEM_FN_NAME (arc700f,nop_s) },
+ { ARC700F_INSN_UNIMP_S, SEM_FN_NAME (arc700f,unimp_s) },
+ { ARC700F_INSN_POP_S_B, SEM_FN_NAME (arc700f,pop_s_b) },
+ { ARC700F_INSN_POP_S_BLINK, SEM_FN_NAME (arc700f,pop_s_blink) },
+ { ARC700F_INSN_PUSH_S_B, SEM_FN_NAME (arc700f,push_s_b) },
+ { ARC700F_INSN_PUSH_S_BLINK, SEM_FN_NAME (arc700f,push_s_blink) },
+ { ARC700F_INSN_MULLW_L_S12__RA_, SEM_FN_NAME (arc700f,mullw_L_s12__RA_) },
+ { ARC700F_INSN_MULLW_CCU6__RA_, SEM_FN_NAME (arc700f,mullw_ccu6__RA_) },
+ { ARC700F_INSN_MULLW_L_U6__RA_, SEM_FN_NAME (arc700f,mullw_L_u6__RA_) },
+ { ARC700F_INSN_MULLW_L_R_R__RA__RC, SEM_FN_NAME (arc700f,mullw_L_r_r__RA__RC) },
+ { ARC700F_INSN_MULLW_CC__RA__RC, SEM_FN_NAME (arc700f,mullw_cc__RA__RC) },
+ { ARC700F_INSN_MACLW_L_S12__RA_, SEM_FN_NAME (arc700f,maclw_L_s12__RA_) },
+ { ARC700F_INSN_MACLW_CCU6__RA_, SEM_FN_NAME (arc700f,maclw_ccu6__RA_) },
+ { ARC700F_INSN_MACLW_L_U6__RA_, SEM_FN_NAME (arc700f,maclw_L_u6__RA_) },
+ { ARC700F_INSN_MACLW_L_R_R__RA__RC, SEM_FN_NAME (arc700f,maclw_L_r_r__RA__RC) },
+ { ARC700F_INSN_MACLW_CC__RA__RC, SEM_FN_NAME (arc700f,maclw_cc__RA__RC) },
+ { ARC700F_INSN_MACHLW_L_S12__RA_, SEM_FN_NAME (arc700f,machlw_L_s12__RA_) },
+ { ARC700F_INSN_MACHLW_CCU6__RA_, SEM_FN_NAME (arc700f,machlw_ccu6__RA_) },
+ { ARC700F_INSN_MACHLW_L_U6__RA_, SEM_FN_NAME (arc700f,machlw_L_u6__RA_) },
+ { ARC700F_INSN_MACHLW_L_R_R__RA__RC, SEM_FN_NAME (arc700f,machlw_L_r_r__RA__RC) },
+ { ARC700F_INSN_MACHLW_CC__RA__RC, SEM_FN_NAME (arc700f,machlw_cc__RA__RC) },
+ { ARC700F_INSN_MULULW_L_S12__RA_, SEM_FN_NAME (arc700f,mululw_L_s12__RA_) },
+ { ARC700F_INSN_MULULW_CCU6__RA_, SEM_FN_NAME (arc700f,mululw_ccu6__RA_) },
+ { ARC700F_INSN_MULULW_L_U6__RA_, SEM_FN_NAME (arc700f,mululw_L_u6__RA_) },
+ { ARC700F_INSN_MULULW_L_R_R__RA__RC, SEM_FN_NAME (arc700f,mululw_L_r_r__RA__RC) },
+ { ARC700F_INSN_MULULW_CC__RA__RC, SEM_FN_NAME (arc700f,mululw_cc__RA__RC) },
+ { ARC700F_INSN_MACHULW_L_S12__RA_, SEM_FN_NAME (arc700f,machulw_L_s12__RA_) },
+ { ARC700F_INSN_MACHULW_CCU6__RA_, SEM_FN_NAME (arc700f,machulw_ccu6__RA_) },
+ { ARC700F_INSN_MACHULW_L_U6__RA_, SEM_FN_NAME (arc700f,machulw_L_u6__RA_) },
+ { ARC700F_INSN_MACHULW_L_R_R__RA__RC, SEM_FN_NAME (arc700f,machulw_L_r_r__RA__RC) },
+ { ARC700F_INSN_MACHULW_CC__RA__RC, SEM_FN_NAME (arc700f,machulw_cc__RA__RC) },
+ { ARC700F_INSN_CURRENT_LOOP_END, SEM_FN_NAME (arc700f,current_loop_end) },
+ { ARC700F_INSN_CURRENT_LOOP_END_AFTER_BRANCH, SEM_FN_NAME (arc700f,current_loop_end_after_branch) },
+ { ARC700F_INSN_ARC600_CURRENT_LOOP_END_AFTER_BRANCH, SEM_FN_NAME (arc700f,arc600_current_loop_end_after_branch) },
+ { 0, 0 }
+};
+
+/* Add the semantic fns to IDESC_TABLE. */
+
+void
+SEM_FN_NAME (arc700f,init_idesc_table) (SIM_CPU *current_cpu)
+{
+ IDESC *idesc_table = CPU_IDESC (current_cpu);
+ const struct sem_fn_desc *sf;
+ int mach_num = MACH_NUM (CPU_MACH (current_cpu));
+
+ for (sf = &sem_fns[0]; sf->fn != 0; ++sf)
+ {
+ const CGEN_INSN *insn = idesc_table[sf->index].idata;
+ int valid_p = (CGEN_INSN_VIRTUAL_P (insn)
+ || CGEN_INSN_MACH_HAS_P (insn, mach_num));
+#if FAST_P
+ if (valid_p)
+ idesc_table[sf->index].sem_fast = sf->fn;
+ else
+ idesc_table[sf->index].sem_fast = SEM_FN_NAME (arc700f,x_invalid);
+#else
+ if (valid_p)
+ idesc_table[sf->index].sem_full = sf->fn;
+ else
+ idesc_table[sf->index].sem_full = SEM_FN_NAME (arc700f,x_invalid);
+#endif
+ }
+}
+
diff --git a/sim/arc/sim-if.c b/sim/arc/sim-if.c
new file mode 100644
index 0000000..be4d99e
--- /dev/null
+++ b/sim/arc/sim-if.c
@@ -0,0 +1,460 @@
+/* Main simulator entry points specific to the ARC.
+ Copyright (C) 1996, 1997, 1998, 1999, 2003, 2004, 2005, 2006, 2007, 2008
+ Free Software Foundation, Inc.
+
+ This file is part of GDB, the GNU debugger.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2, or (at your option)
+ any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+#include "sim-main.h"
+#include "sim-options.h"
+#include "libiberty.h"
+#include "bfd.h"
+
+#ifdef HAVE_STRING_H
+#include <string.h>
+#else
+#ifdef HAVE_STRINGS_H
+#include <strings.h>
+#endif
+#endif
+#ifdef HAVE_STDLIB_H
+#include <stdlib.h>
+#endif
+
+static void free_state (SIM_DESC);
+static void print_arc_misc_cpu (SIM_CPU *cpu, int verbose);
+
+/* Records simulator descriptor so utilities like arc_dump_regs can be
+ called from gdb. */
+SIM_DESC current_state;
+
+/* Cover function of sim_state_free to free the cpu buffers as well. */
+
+static void
+free_state (SIM_DESC sd)
+{
+ if (STATE_MODULES (sd) != NULL)
+ sim_module_uninstall (sd);
+ sim_cpu_free_all (sd);
+ sim_state_free (sd);
+}
+
+/* Find out heap and stack end boundaries, and return required memory
+ size; if this cannot be calcualted, return DEFAULT_MEMSIZE.
+ If INIT_P is nonzero, initialize memory above the stack with argv and envp.
+ If this initialization fails, return 0. */
+static int
+init_stack (struct bfd *abfd, char **argv,
+ SIM_DESC sd, int default_memsize, int init_p)
+{
+ USI stack_start = 0, stack_top = 0, heap_start = 0, heap_end = 0;
+ USI prog_end = 0;
+ char *null_env = NULL;
+ char **envp = &null_env;
+ int argc;
+ char **cpp, **rpp, *str;
+ size_t len;
+ int cp, wpp;
+ int n_ptr = 0, cnt;
+ /* All CPUs have the same memory map, apparently. */
+ SIM_CPU *cpu = STATE_CPU (sd, 0);
+ bfd_byte buf[4];
+
+ if (abfd)
+ {
+ asection *s;
+
+ for (s = abfd->sections; s; s = s->next)
+ if (strcmp (bfd_get_section_name (abfd, s), ".stack") == 0)
+ {
+ stack_start = bfd_get_section_vma (abfd, s);
+ stack_top = stack_start + bfd_section_size (abfd, s);
+ stack_top &= -4; /* 4 == target pointer size */
+ default_memsize = stack_top;
+ }
+ else if (strcmp (bfd_get_section_name (abfd, s), ".heap") == 0)
+ {
+ heap_start = bfd_get_section_vma (abfd, s);
+ heap_end = heap_start + bfd_section_size (abfd, s);
+ }
+ else
+ {
+ USI s_end
+ = bfd_get_section_vma (abfd, s) + bfd_section_size (abfd, s);
+
+ if (prog_end < s_end)
+ prog_end = s_end;
+ }
+ if (heap_end == 0)
+ {
+ if (prog_end > stack_start)
+ return 0;
+ heap_start = prog_end;
+ heap_end = stack_start;
+ }
+ if (!argv)
+ n_ptr == 1;
+ else
+ {
+ for (cpp = envp, len = 0, cnt = 2; cnt--; cpp = argv)
+ {
+ argc = 0;
+ for (rpp = cpp; *rpp; rpp++)
+ argc++, len += strlen (*rpp) + 1;
+ n_ptr += argc + 1;
+ }
+ }
+ n_ptr ++; //* For uclibc aux_dat */
+ if (!stack_top)
+ stack_top = (default_memsize + 3) & -4; /* 4 == target pointer size */
+ wpp = stack_top + 4;
+ cp = wpp + n_ptr * 4;
+ default_memsize = cp + len;
+ /* Round up to multiple of 32. strlen expects memory to come in chunks
+ that are at least cache-line (32 bytes) sized. */
+ default_memsize += 31;
+ default_memsize &= -32;
+ }
+ if (abfd && init_p)
+ {
+ int little_endian_p = bfd_little_endian (abfd);
+
+ if (stack_top <= stack_start)
+ {
+ host_callback *callback = STATE_CALLBACK (sd);
+
+ (*callback->printf_filtered) (callback, "stack overflow\n");
+ return 0;
+ }
+
+ /* Can't use sim_core_write_unaligned_4 without everything
+ initialized when tracing, and then these writes would get into
+ the trace. */
+#define write_dword(addr, data) \
+ do \
+ { \
+ USI data_ = data; \
+ USI addr_ = addr; \
+ if (little_endian_p) \
+ bfd_putl32 (data_, buf); \
+ else \
+ bfd_putb32 (data_, buf); \
+ if (sim_core_write_buffer (sd, cpu, 0, buf, addr_, 4) != 4) \
+ return 0; \
+ } \
+ while (0)
+
+ write_dword (stack_top, argc);
+ for (cpp = argv, cnt = 2; cnt--; cpp = envp)
+ {
+ for (rpp = cpp; str = *cpp++;)
+ {
+ len = strlen (str) + 1;
+ if (sim_core_write_buffer (sd, cpu, 0, str, cp, len) != len)
+ return 0;
+ write_dword (wpp, cp);
+ cp += len;
+ wpp += 4;
+ }
+ write_dword (wpp, 0);
+ wpp += 4;
+ }
+ write_dword (wpp, 0);
+ sd->heap_start = heap_start;
+ sd->heap_end = heap_end;
+ sd->stack_top = stack_top;
+ }
+ return default_memsize;
+}
+
+/* Create an instance of the simulator. */
+
+SIM_DESC
+sim_open (kind, callback, abfd, argv)
+ SIM_OPEN_KIND kind;
+ host_callback *callback;
+ struct bfd *abfd;
+ char **argv;
+{
+ SIM_DESC sd = sim_state_alloc (kind, callback);
+ char c;
+ int i;
+ int default_memsize;
+ char ** prog_argv;
+
+ /* The cpu data is kept in a separately allocated chunk of memory. */
+ if (sim_cpu_alloc_all (sd, 1, cgen_cpu_max_extra_bytes ()) != SIM_RC_OK)
+ {
+ free_state (sd);
+ return 0;
+ }
+
+#if 0 /* FIXME: pc is in mach-specific struct */
+ /* FIXME: watchpoints code shouldn't need this */
+ {
+ SIM_CPU *current_cpu = STATE_CPU (sd, 0);
+ STATE_WATCHPOINTS (sd)->pc = &(PC);
+ STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
+ }
+#endif
+
+ if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
+ {
+ free_state (sd);
+ return 0;
+ }
+
+#ifdef HAVE_DV_SOCKSER /* FIXME: was done differently before */
+ if (dv_sockser_install (sd) != SIM_RC_OK)
+ {
+ free_state (sd);
+ return 0;
+ }
+#endif
+
+#if 0 /* FIXME: 'twould be nice if we could do this */
+ /* These options override any module options.
+ Obviously ambiguity should be avoided, however the caller may wish to
+ augment the meaning of an option. */
+ if (extra_options != NULL)
+ sim_add_option_table (sd, extra_options);
+#endif
+
+ /* getopt will print the error message so we just have to exit if this fails.
+ FIXME: Hmmm... in the case of gdb we need getopt to call
+ print_filtered. */
+ if (sim_parse_args (sd, argv) != SIM_RC_OK)
+ {
+ free_state (sd);
+ return 0;
+ }
+
+ /* Check for/establish the reference program image, and set arch info. */
+ if (sim_analyze_program (sd,
+ (STATE_PROG_ARGV (sd) != NULL
+ ? *STATE_PROG_ARGV (sd)
+ : NULL),
+ abfd) != SIM_RC_OK)
+ {
+ free_state (sd);
+ return 0;
+ }
+
+ prog_argv = STATE_PROG_ARGV (sd);
+ if (!abfd)
+ {
+ char *name;
+
+ /* FIXME: If the test below fails, we will use ARC_DEFAULT_MEMSIZE.
+ We should have some way to remember this, so that we can
+ emit an error in sim_create_inferior if the required memory
+ size is larger. */
+ if (prog_argv != NULL && *prog_argv != NULL)
+ {
+ name = *prog_argv;
+ abfd = bfd_openr (name, 0);
+ if (abfd == NULL || !bfd_check_format (abfd, bfd_object))
+ {
+ free_state (sd);
+ return 0;
+ }
+ }
+ }
+
+ default_memsize
+ = init_stack (abfd, prog_argv, sd, ARC_DEFAULT_MEM_SIZE, 0);
+ /* Allocate core managed memory if none specified by user.
+ Use address 4 here in case the user wanted address 0 unmapped. */
+ if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0)
+ sim_do_commandf (sd, "memory region 0,0x%x", default_memsize);
+
+ if (!init_stack (abfd, prog_argv, sd, default_memsize, 1)
+ /* Establish any remaining configuration options. */
+ || sim_config (sd) != SIM_RC_OK)
+ {
+ free_state (sd);
+ return 0;
+ }
+
+ if (sim_post_argv_init (sd) != SIM_RC_OK)
+ {
+ free_state (sd);
+ return 0;
+ }
+
+ /* Open a copy of the cpu descriptor table. */
+ {
+ CGEN_CPU_DESC cd
+ = arc_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name,
+ (abfd && bfd_little_endian (abfd)
+ ? CGEN_ENDIAN_LITTLE: CGEN_ENDIAN_BIG));
+ for (i = 0; i < MAX_NR_PROCESSORS; ++i)
+ {
+ SIM_CPU *cpu = STATE_CPU (sd, i);
+ CPU_CPU_DESC (cpu) = cd;
+ CPU_DISASSEMBLER (cpu) = sim_cgen_disassemble_insn;
+ }
+ arc_cgen_init_dis (cd);
+ }
+
+ /* Initialize various cgen things not done by common framework.
+ Must be done after arc_cgen_cpu_open. */
+ cgen_init (sd);
+
+ for (c = 0; c < MAX_NR_PROCESSORS; ++c)
+ {
+ /* Only needed for profiling, but the structure member is small. */
+ memset (CPU_ARC_MISC_PROFILE (STATE_CPU (sd, i)), 0,
+ sizeof (* CPU_ARC_MISC_PROFILE (STATE_CPU (sd, i))));
+ /* Hook in callback for reporting these stats */
+ PROFILE_INFO_CPU_CALLBACK (CPU_PROFILE_DATA (STATE_CPU (sd, i)))
+ = print_arc_misc_cpu;
+ }
+
+ /* Store in a global so things like sparc32_dump_regs can be invoked
+ from the gdb command line. */
+ current_state = sd;
+
+ return sd;
+}
+
+void
+sim_close (sd, quitting)
+ SIM_DESC sd;
+ int quitting;
+{
+ arc_cgen_cpu_close (CPU_CPU_DESC (STATE_CPU (sd, 0)));
+ sim_module_uninstall (sd);
+}
+
+SIM_RC
+sim_create_inferior (sd, abfd, argv, envp)
+ SIM_DESC sd;
+ struct bfd *abfd;
+ char **argv;
+ char **envp;
+{
+ SIM_CPU *current_cpu = STATE_CPU (sd, 0);
+ SIM_ADDR addr;
+
+ if (abfd != NULL)
+ addr = bfd_get_start_address (abfd);
+ else
+ addr = 0;
+ sim_pc_set (current_cpu, addr);
+ /* Initialize stack pointer. */
+ if (!sd->stack_top
+ && !init_stack (abfd, argv, sd, 1, 1))
+ return 0;
+ current_cpu->endbrk = sd->heap_start;
+
+ a5f_h_cr_set (current_cpu, 28, (sd)->stack_top);
+ /* Set r0/r1 to argc / argv */
+ a5f_h_cr_set (current_cpu, 0, GETMEMSI (current_cpu, 0, sd->stack_top));
+ a5f_h_cr_set (current_cpu, 1, sd->stack_top+4);
+
+#ifdef ARC_LINUX
+ m32rbf_h_cr_set (current_cpu,
+ arc_decode_gdb_ctrl_regnum(SPI_REGNUM), 0x1f00000);
+ m32rbf_h_cr_set (current_cpu,
+ arc_decode_gdb_ctrl_regnum(SPU_REGNUM), 0x1f00000);
+#endif
+
+#if 0
+ STATE_ARGV (sd) = sim_copy_argv (argv);
+ STATE_ENVP (sd) = sim_copy_argv (envp);
+#endif
+
+ return SIM_RC_OK;
+}
+
+/* PROFILE_CPU_CALLBACK */
+
+static void
+print_arc_misc_cpu (SIM_CPU *cpu, int verbose)
+{
+ SIM_DESC sd = CPU_STATE (cpu);
+ char buf[20];
+
+ if (CPU_PROFILE_FLAGS (cpu) [PROFILE_INSN_IDX])
+ {
+ sim_io_printf (sd, "Miscellaneous Statistics\n\n");
+ sim_io_printf (sd, " %-*s %s\n\n",
+ PROFILE_LABEL_WIDTH, "Fill nops:",
+ sim_add_commas (buf, sizeof (buf),
+ CPU_ARC_MISC_PROFILE (cpu)->fillnop_count));
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_m32rx)
+ sim_io_printf (sd, " %-*s %s\n\n",
+ PROFILE_LABEL_WIDTH, "Parallel insns:",
+ sim_add_commas (buf, sizeof (buf),
+ CPU_ARC_MISC_PROFILE (cpu)->parallel_count));
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_m32r2)
+ sim_io_printf (sd, " %-*s %s\n\n",
+ PROFILE_LABEL_WIDTH, "Parallel insns:",
+ sim_add_commas (buf, sizeof (buf),
+ CPU_ARC_MISC_PROFILE (cpu)->parallel_count));
+ }
+}
+
+void
+sim_do_command (sd, cmd)
+ SIM_DESC sd;
+ char *cmd;
+{
+ char **argv;
+
+ if (cmd == NULL)
+ return;
+
+ argv = buildargv (cmd);
+
+ if (argv[0] != NULL
+ && strcasecmp (argv[0], "info") == 0
+ && argv[1] != NULL
+ && strncasecmp (argv[1], "reg", 3) == 0)
+ {
+ SI val;
+
+ /* We only support printing bbpsw,bbpc here as there is no equivalent
+ functionality in gdb. */
+ if (argv[2] == NULL)
+ sim_io_eprintf (sd, "Missing register in `%s'\n", cmd);
+ else if (argv[3] != NULL)
+ sim_io_eprintf (sd, "Too many arguments in `%s'\n", cmd);
+#if 0
+ else if (strcasecmp (argv[2], "bbpsw") == 0)
+ {
+ val = m32rbf_h_cr_get (STATE_CPU (sd, 0), H_CR_BBPSW);
+ sim_io_printf (sd, "bbpsw 0x%x %d\n", val, val);
+ }
+ else if (strcasecmp (argv[2], "bbpc") == 0)
+ {
+ val = m32rbf_h_cr_get (STATE_CPU (sd, 0), H_CR_BBPC);
+ sim_io_printf (sd, "bbpc 0x%x %d\n", val, val);
+ }
+#endif
+ else
+ sim_io_eprintf (sd, "Printing of register `%s' not supported with `sim info'\n",
+ argv[2]);
+ }
+ else
+ {
+ if (sim_args_command (sd, cmd) != SIM_RC_OK)
+ sim_io_eprintf (sd, "Unknown sim command `%s'\n", cmd);
+ }
+
+ freeargv (argv);
+}
diff --git a/sim/arc/sim-main.h b/sim/arc/sim-main.h
new file mode 100644
index 0000000..05c7ab3
--- /dev/null
+++ b/sim/arc/sim-main.h
@@ -0,0 +1,98 @@
+/* Main header for the arc.
+ Copyright (C) 2004, 2005, 2006, 2007 Free Software Foundation, Inc. */
+
+#ifndef SIM_MAIN_H
+#define SIM_MAIN_H
+
+struct _sim_cpu; /* FIXME: should be in sim-basics.h */
+typedef struct _sim_cpu SIM_CPU;
+
+#include "symcat.h"
+#include "sim-basics.h"
+#include "cgen-types.h"
+#include "arc-desc.h"
+#include "arc-opc.h"
+#include "arch.h"
+
+/* These must be defined before sim-base.h. */
+typedef USI sim_cia;
+
+#define CIA_GET(cpu) CPU_PC_GET (cpu)
+#define CIA_SET(cpu,val) CPU_PC_SET ((cpu), (val))
+
+#define SIM_ENGINE_HALT_HOOK(sd, cpu, cia) \
+do { \
+ if (cpu) /* null if ctrl-c */ \
+ sim_pc_set ((cpu), (cia)); \
+} while (0)
+#define SIM_ENGINE_RESTART_HOOK(sd, cpu, cia) \
+do { \
+ sim_pc_set ((cpu), (cia)); \
+} while (0)
+
+#include "sim-base.h"
+#include "cgen-sim.h"
+#include "arc-sim.h"
+#include "opcode/cgen.h"
+
+/* The _sim_cpu struct. */
+
+struct _sim_cpu {
+ /* sim/common cpu base. */
+ sim_cpu_base base;
+
+ /* Static parts of cgen. */
+ CGEN_CPU cgen_cpu;
+
+ ARC_MISC_PROFILE arc_misc_profile;
+#define CPU_ARC_MISC_PROFILE(cpu) (& (cpu)->arc_misc_profile)
+
+ /* Simulator environment data. */
+ USI endbrk;
+
+ /* CPU specific parts go here.
+ Note that in files that don't need to access these pieces WANT_CPU_FOO
+ won't be defined and thus these parts won't appear. This is ok in the
+ sense that things work. It is a source of bugs though.
+ One has to of course be careful to not take the size of this
+ struct and no structure members accessed in non-cpu specific files can
+ go after here. Oh for a better language. */
+ /* ??? all the CPU registers are considered to be CPU specific, even the
+ ones that are present in all members of all CPU families of the
+ architecture. */
+#if defined (WANT_CPU_A5F)
+ A5F_CPU_DATA cpu_data;
+#endif
+#if defined (WANT_CPU_ARC600F)
+ ARC600F_CPU_DATA cpu_data;
+#elif defined (WANT_CPU_ARC700F)
+ ARC700F_CPU_DATA cpu_data;
+#endif
+};
+
+/* The sim_state struct. */
+
+struct sim_state {
+ sim_cpu *cpu;
+#define STATE_CPU(sd, n) (/*&*/ (sd)->cpu)
+
+ CGEN_STATE cgen_state;
+ unsigned int heap_start;
+ unsigned int heap_end;
+ unsigned int stack_top;
+
+ sim_state_base base;
+};
+
+/* Misc. */
+
+/* Catch address exceptions. */
+extern SIM_CORE_SIGNAL_FN arc_core_signal;
+#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
+arc_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
+ (TRANSFER), (ERROR))
+
+/* Default memory size. */
+#define ARC_DEFAULT_MEM_SIZE 0x2000000 /* 32M */
+
+#endif /* SIM_MAIN_H */
diff --git a/sim/arc/tconfig.in b/sim/arc/tconfig.in
new file mode 100644
index 0000000..ded104a
--- /dev/null
+++ b/sim/arc/tconfig.in
@@ -0,0 +1,47 @@
+/* ARC target configuration file. -*- C -*- */
+
+#ifndef ARC_TCONFIG_H
+#define ARC_TCONFIG_H
+
+/* Define this if the simulator can vary the size of memory.
+ See the xxx simulator for an example.
+ This enables the `-m size' option.
+ The memory size is stored in STATE_MEM_SIZE. */
+/* Not used for ARC since we use the memory module. */
+/* #define SIM_HAVE_MEM_SIZE */
+
+/* See sim-hload.c. We properly handle LMA. */
+#define SIM_HANDLES_LMA 1
+
+/* For MSPR support. FIXME: revisit. */
+#define WITH_DEVICES 1
+
+/* FIXME: Revisit. */
+#ifdef HAVE_DV_SOCKSER
+MODULE_INSTALL_FN dv_sockser_install;
+#define MODULE_LIST dv_sockser_install,
+#endif
+
+#if 0
+/* Enable watchpoints. */
+#define WITH_WATCHPOINTS 1
+#endif
+
+/* Define this to enable the intrinsic breakpoint mechanism. */
+/* FIXME: may be able to remove SIM_HAVE_BREAKPOINT since it essentially
+ duplicates ifdef SIM_BREAKPOINT (right?) */
+#if 0
+#define SIM_HAVE_BREAKPOINTS
+#define SIM_BREAKPOINT { 0x10, 0xf1 }
+#define SIM_BREAKPOINT_SIZE 2
+#endif
+#if 0
+#define HAVE_DV_SOCKSER
+#endif
+
+/* This is a global setting. Different cpu families can't mix-n-match -scache
+ and -pbb. However some cpu families may use -simple while others use
+ one of -scache/-pbb. */
+#define WITH_SCACHE_PBB 1
+
+#endif /* ARC_TCONFIG_H */
diff --git a/sim/arc/traps.c b/sim/arc/traps.c
new file mode 100644
index 0000000..6702523
--- /dev/null
+++ b/sim/arc/traps.c
@@ -0,0 +1,398 @@
+/* arc exception, interrupt, and trap (EIT) support
+ Copyright (C) 1998, 2003, 2004, 2005 Free Software Foundation, Inc.
+
+ This file is part of GDB, the GNU debugger.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2, or (at your option)
+ any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+#include "sim-main.h"
+#include "targ-vals.h"
+#include <sys/stat.h>
+#include <sys/time.h>
+#include "gdb/target-io/arc.h"
+
+#define TRAP_FLUSH_CACHE 12
+
+/* The semantic code invokes this for invalid (unrecognized) instructions. */
+
+SEM_PC
+sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC pc)
+{
+ SIM_DESC sd = CPU_STATE (current_cpu);
+
+#if 0
+ if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
+ {
+ h_bsm_set (current_cpu, h_sm_get (current_cpu));
+ h_bie_set (current_cpu, h_ie_get (current_cpu));
+ h_bcond_set (current_cpu, h_cond_get (current_cpu));
+ /* sm not changed */
+ h_ie_set (current_cpu, 0);
+ h_cond_set (current_cpu, 0);
+
+ h_bpc_set (current_cpu, cia);
+
+ sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
+ EIT_RSVD_INSN_ADDR);
+ }
+ else
+#endif
+ sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL);
+
+ return pc;
+}
+
+/* Process an address exception. */
+
+void
+arc_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia,
+ unsigned int map, int nr_bytes, address_word addr,
+ transfer_type transfer, sim_core_signals sig)
+{
+#if 0 /* FIXME */
+ if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
+ {
+ m32rbf_h_cr_set (current_cpu, H_CR_BBPC,
+ m32rbf_h_cr_get (current_cpu, H_CR_BPC));
+ switch (MACH_NUM (CPU_MACH (current_cpu)))
+ {
+ case MACH_M32R:
+ m32rbf_h_bpsw_set (current_cpu, m32rbf_h_psw_get (current_cpu));
+ /* sm not changed. */
+ m32rbf_h_psw_set (current_cpu, m32rbf_h_psw_get (current_cpu) & 0x80);
+ break;
+ case MACH_M32RX:
+ m32rxf_h_bpsw_set (current_cpu, m32rxf_h_psw_get (current_cpu));
+ /* sm not changed. */
+ m32rxf_h_psw_set (current_cpu, m32rxf_h_psw_get (current_cpu) & 0x80);
+ break;
+ case MACH_M32R2:
+ m32r2f_h_bpsw_set (current_cpu, m32r2f_h_psw_get (current_cpu));
+ /* sm not changed. */
+ m32r2f_h_psw_set (current_cpu, m32r2f_h_psw_get (current_cpu) & 0x80);
+ break;
+ default:
+ abort ();
+ }
+
+ m32rbf_h_cr_set (current_cpu, H_CR_BPC, cia);
+
+ sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
+ EIT_ADDR_EXCP_ADDR);
+ }
+ else
+#endif
+ sim_core_signal (sd, current_cpu, cia, map, nr_bytes, addr,
+ transfer, sig);
+}
+
+/* Read/write functions for system call interface. */
+
+static int
+syscall_read_mem (host_callback *cb, struct cb_syscall *sc,
+ unsigned long taddr, char *buf, int bytes)
+{
+ SIM_DESC sd = (SIM_DESC) sc->p1;
+ SIM_CPU *cpu = (SIM_CPU *) sc->p2;
+
+ return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes);
+}
+
+static int
+syscall_write_mem (host_callback *cb, struct cb_syscall *sc,
+ unsigned long taddr, const char *buf, int bytes)
+{
+ SIM_DESC sd = (SIM_DESC) sc->p1;
+ SIM_CPU *cpu = (SIM_CPU *) sc->p2;
+
+ return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes);
+}
+
+static CB_RC arc_syscall (host_callback *, CB_SYSCALL *);
+
+/* Trap support.
+ The result is the pc address to continue at.
+ Preprocessing like saving the various registers has already been done. */
+
+USI
+arc_trap (SIM_CPU *current_cpu, PCADDR pc, int insn_len, int num)
+{
+ SIM_DESC sd = CPU_STATE (current_cpu);
+ host_callback *cb = STATE_CALLBACK (sd);
+
+#ifndef LIBC_FIXED
+if (num == TRAP_BREAKPOINT)
+ num = TRAP_SYSCALL;
+#endif
+#ifdef SIM_HAVE_BREAKPOINTS
+ /* Check for breakpoints "owned" by the simulator first, regardless
+ of --environment. */
+ if (num == TRAP_BREAKPOINT)
+ {
+ /* First try sim-break.c. If it's a breakpoint the simulator "owns"
+ it doesn't return. Otherwise it returns and let's us try. */
+ sim_handle_breakpoint (sd, current_cpu, pc);
+ /* Fall through. */
+ }
+#endif
+
+ if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
+ {
+#if 0
+ /* The new pc is the trap vector entry.
+ We assume there's a branch there to some handler.
+ /* USI new_pc = EIT_TRAP_BASE_ADDR + num * 4; */
+ USI new_pc = /* A5 / ARC600 */
+ a5f_h_auxr_get (current_cpu, 37 /* INT_VECTOR_BASE */) + 0x10;
+ USI new_pc = /* ARC700 */
+ a5f_h_auxr_get (current_cpu, 37 /* INT_VECTOR_BASE */) + 0x128;
+ return new_pc;
+#endif
+abort ();
+ }
+
+ switch (num)
+ {
+ case TRAP_SYSCALL :
+ {
+ CB_SYSCALL s;
+
+ CB_SYSCALL_INIT (&s);
+ s.func = a5f_h_cr_get (current_cpu, 8);
+ s.arg1 = a5f_h_cr_get (current_cpu, 0);
+ s.arg2 = a5f_h_cr_get (current_cpu, 1);
+ s.arg3 = a5f_h_cr_get (current_cpu, 2);
+ s.arg4 = a5f_h_cr_get (current_cpu, 3);
+
+ if (s.func == TARGET_SYS_exit)
+ {
+ sim_engine_halt (sd, current_cpu, NULL, pc, sim_exited, s.arg1);
+ }
+
+ s.p1 = (PTR) sd;
+ s.p2 = (PTR) current_cpu;
+ s.read_mem = syscall_read_mem;
+ s.write_mem = syscall_write_mem;
+ arc_syscall (cb, &s);
+ a5f_h_cr_set (current_cpu, 0, s.errcode ? -s.errcode : s.result);
+ break;
+ }
+
+ case TRAP_BREAKPOINT:
+ sim_engine_halt (sd, current_cpu, NULL, pc,
+ sim_stopped, SIM_SIGTRAP);
+ break;
+
+#if 0
+ case TRAP_FLUSH_CACHE:
+ /* Do nothing. */
+ break;
+#endif
+
+ default :
+ {
+#if 0
+ /* USI new_pc = EIT_TRAP_BASE_ADDR + num * 4; */
+ /* Use cr5 as EVB (EIT Vector Base) register. */
+ USI new_pc = m32rbf_h_cr_get (current_cpu, 5) + 0x40 + num * 4;
+ return new_pc;
+#endif
+abort();
+ }
+ }
+
+ return pc + insn_len;
+}
+
+void
+arc_breakpoint (SIM_CPU *current_cpu, PCADDR pc, int insn_len)
+{
+ SIM_DESC sd = CPU_STATE (current_cpu);
+
+ sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
+}
+
+/* If the generic simulator call said ENOSYS, then let's try the
+ ones we know ourselves.
+
+ The convention is to provide *very limited* functionality on an
+ as-needed basis, only what's covered by the test-suite, tests
+ added when functionality changes and abort with a descriptive
+ message for *everything* else. Where there's no test-case, we
+ just abort. */
+static CB_RC
+arc_syscall (host_callback *cb, CB_SYSCALL *s)
+{
+ SIM_CPU *current_cpu = s->p2;
+ SIM_DESC sd = CPU_STATE (current_cpu);
+
+ s->errcode = 0;
+ switch (s->func)
+ {
+ case TARGET_SYS_brk:
+ /* Most often, we just return the argument, like the Linux
+ kernel. */
+ s->result = s->arg1;
+
+ if (s->arg1 == 0)
+ s->result = current_cpu->endbrk;
+ else if (s->arg1 <= sd->heap_end)
+ current_cpu->endbrk = s->arg1;
+ else
+ {
+ s->result = -1;
+ s->errcode = TARGET_ENOMEM;
+ break;
+ }
+ break;
+ {
+ struct stat st;
+ struct fio_arc_stat buf;
+ int retval;
+ int errcode;
+ int e;
+ char *path;
+
+ case TARGET_SYS_stat:
+ errcode = get_path (cb, s, s->arg1, &path);
+ if (errcode)
+ {
+ s->result = -1;
+ s->errcode = cb_host_to_target_errno (cb, errcode);
+ break;
+ }
+ retval = stat (path, &st);
+ free (path);
+ goto do_stat;
+ case TARGET_SYS_fstat:
+ retval = fdbad (cb, s->arg1);
+ if (retval)
+ {
+ s->result = -1;
+ s->errcode = TARGET_EINVAL;
+ break;
+ }
+ retval = fstat (fdmap (cb, s->arg1), &st);
+ do_stat:
+
+ s->result = retval;
+ e = CURRENT_HOST_BYTE_ORDER ^ CURRENT_TARGET_BYTE_ORDER;
+#define E2(v) (e ? swap_2(v) : (v))
+#define E4(v) (e ? swap_4(v) : (v))
+#define E8(v) (e ? swap_8(v) : (v))
+
+ buf.tgt_st_dev = E4 (st.st_dev);
+ buf.tgt_st_ino = E4 (st.st_ino);
+ buf.tgt_st_mode = E2 (st.st_mode);
+ buf.tgt_st_nlink = E2 (st.st_nlink);
+ buf.tgt_st_uid = E2 (st.st_uid);
+ buf.tgt_st_gid = E2 (st.st_gid);
+ buf.tgt_st_rdev = E4 (st.st_rdev);
+ buf.tgt_st_size = E4 (st.st_size);
+ buf.tgt_st_blksize = E4 (st.st_blksize);
+ buf.tgt_st_blocks = E4 (st.st_blocks);
+ buf.tgt_st_atime = E8 (st.st_atime);
+ buf.tgt_st_mtime = E8 (st.st_mtime);
+ buf.tgt_st_ctime = E8 (st.st_ctime);
+ memset (&buf.tgt_st_reserved, 0, sizeof buf.tgt_st_reserved);
+ if ((*s->write_mem) (cb, s, s->arg2, (char *) &buf, sizeof buf)
+ != sizeof buf)
+ {
+ s->result = -1;
+ s->errcode = TARGET_EINVAL;
+ break;
+ }
+ if (!retval)
+ break;
+ handle_error:
+ s->errcode = (*cb->get_errno) (cb);
+ }
+ case TARGET_SYS_gettimeofday:
+ {
+ struct timeval tv;
+ struct timezone tz;
+ struct fio_timeval buf;
+ int retval;
+ int e;
+
+ if (s->arg2)
+ /* FIXME */;
+ retval = gettimeofday (&tv, s->arg2 ? &tz : 0);
+ s->result = retval;
+ e = CURRENT_HOST_BYTE_ORDER ^ CURRENT_TARGET_BYTE_ORDER;
+ buf.tgt_tv_sec = E8 (tv.tv_sec);
+ buf.tgt_tv_usec = E4 (tv.tv_usec);
+ if ((*s->write_mem) (cb, s, s->arg1, (char *) &buf, sizeof buf)
+ != sizeof buf)
+ {
+ s->result = -1;
+ s->errcode = TARGET_EINVAL;
+ break;
+ }
+ if (retval)
+ goto handle_error;
+ break;
+ s->errcode = (*cb->get_errno) (cb);
+ }
+ case TARGET_SYS_setitimer:
+ /* This implements only minimal functionality for prof-freq.c to work. */
+ if (s->arg1 != ITIMER_REAL)
+ {
+ s->result = -1;
+ s->errcode = TARGET_EINVAL;
+ break;
+ }
+ s->result = 0;
+ if (s->arg3)
+ {
+ struct fio_timeval buf;
+ int e;
+
+ e = CURRENT_HOST_BYTE_ORDER ^ CURRENT_TARGET_BYTE_ORDER;
+ buf.tgt_tv_sec = E4 (0);
+ buf.tgt_tv_usec = E4 (100);
+ if ((*s->write_mem) (cb, s, s->arg3, (char *) &buf, sizeof buf)
+ != sizeof buf)
+ {
+ s->result = -1;
+ s->errcode = TARGET_EINVAL;
+ break;
+ }
+ }
+ break;
+ case TARGET_SYS_profil:
+ if (s->arg1)
+ {
+ if (s->arg4 != 0x8000)
+ {
+ s->result = -1;
+ s->errcode = TARGET_EINVAL;
+ break;
+ }
+ a5f_h_ubit_set (current_cpu, 1);
+ a5f_h_prof_offset_set (current_cpu, 0, s->arg1 - (s->arg3 >> 1));
+ a5f_h_e1_set (current_cpu, 1);
+ a5f_h_auxr_set (current_cpu, 0x23 /* LIMIT0 */, 100);
+ a5f_h_auxr_set (current_cpu, 0x22 /* CONTROL0 */, 3);
+ }
+ else
+ a5f_h_auxr_set (current_cpu, 0x22 /* CONTROL0 */, 0);
+ s->result = 0;
+ break;
+ default:
+ return cb_syscall (cb, s);
+ }
+ return CB_RC_OK;
+}
diff --git a/sim/common/callback.c b/sim/common/callback.c
index 6134055..c0a4407 100644
--- a/sim/common/callback.c
+++ b/sim/common/callback.c
@@ -92,8 +92,8 @@
static void os_vprintf_filtered PARAMS ((host_callback *, const char *, va_list));
static void os_evprintf_filtered PARAMS ((host_callback *, const char *, va_list));
static void os_error PARAMS ((host_callback *, const char *, ...));
-static int fdmap PARAMS ((host_callback *, int));
-static int fdbad PARAMS ((host_callback *, int));
+int fdmap PARAMS ((host_callback *, int));
+int fdbad PARAMS ((host_callback *, int));
static int wrap PARAMS ((host_callback *, int));
/* Set the callback copy of errno from what we see now. */
@@ -110,7 +110,7 @@
/* Make sure the FD provided is ok. If not, return non-zero
and set errno. */
-static int
+int
fdbad (p, fd)
host_callback *p;
int fd;
@@ -123,7 +123,7 @@
return 0;
}
-static int
+int
fdmap (p, fd)
host_callback *p;
int fd;
diff --git a/sim/common/cgen-trace.c b/sim/common/cgen-trace.c
index 17cfa97..ceeb7e1 100644
--- a/sim/common/cgen-trace.c
+++ b/sim/common/cgen-trace.c
@@ -377,7 +377,11 @@
CGEN_CPU_DESC cd = CPU_CPU_DESC (cpu);
CGEN_EXTRACT_INFO ex_info;
CGEN_FIELDS *fields = alloca (CGEN_CPU_SIZEOF_FIELDS (cd));
+#ifdef CGEN_INSN_DISASM_BITSIZE
+ int insn_bit_length = CGEN_INSN_DISASM_BITSIZE (insn);
+#else
int insn_bit_length = CGEN_INSN_BITSIZE (insn);
+#endif
int insn_length = insn_bit_length / 8;
sfile.buffer = sfile.current = buf;
@@ -421,10 +425,14 @@
length = (*CGEN_EXTRACT_FN (cd, insn)) (cd, insn, &ex_info, insn_value, fields, pc);
/* Result of extract fn is in bits. */
+#ifdef CGEN_INSN_DISASM_BITSIZE
+ if (length <= insn_bit_length)
+#else
/* ??? This assumes that each instruction has a fixed length (and thus
for insns with multiple versions of variable lengths they would each
have their own table entry). */
if (length == insn_bit_length)
+#endif
{
(*CGEN_PRINT_FN (cd, insn)) (cd, &disasm_info, insn, fields, pc, length);
}
diff --git a/sim/common/gennltvals.sh b/sim/common/gennltvals.sh
index 8e8ad54..ec4d49a 100644
--- a/sim/common/gennltvals.sh
+++ b/sim/common/gennltvals.sh
@@ -19,6 +19,9 @@
$shell ${srccom}/gentvals.sh "" signal ${srcroot}/newlib/libc/include \
"signal.h sys/signal.h" 'SIG[A-Z0-9]*' "${cpp}"
+$shell ${srccom}/gentvals.sh "arc" open ${srcroot}/newlib/libc/include \
+ "../sys/arc/sys/fcntl.h" 'O_[A-Z0-9]*' "${cpp}"
+
$shell ${srccom}/gentvals.sh "" open ${srcroot}/newlib/libc/include \
"fcntl.h sys/fcntl.h" 'O_[A-Z0-9]*' "${cpp}"
@@ -29,6 +32,10 @@
# Note that there is a standard syscall.h file (libgloss/syscall.h) now which
# hopefully more targets can use.
+dir=libgloss/arc target=arc
+$shell ${srccom}/gentvals.sh $target sys ${srcroot}/$dir \
+ "syscall.h" 'SYS_[_A-Za-z0-9]*' "${cpp}"
+
dir=newlib/libc/sys/d10v/sys target=d10v
$shell ${srccom}/gentvals.sh $target sys ${srcroot}/$dir \
"syscall.h" 'SYS_[_A-Za-z0-9]*' "${cpp}"
diff --git a/sim/common/gentvals.sh b/sim/common/gentvals.sh
index 6dd7315..514978e 100644
--- a/sim/common/gentvals.sh
+++ b/sim/common/gentvals.sh
@@ -39,10 +39,12 @@
if test -z "$target"
then
+ echo "#ifndef NL_${type}_tgt_specific"
echo "#ifdef ${type}_defs"
else
echo "#ifdef NL_TARGET_$target"
echo "#ifdef ${type}_defs"
+ echo "#define NL_${type}_tgt_specific"
fi
for f in $files
@@ -65,6 +67,7 @@
then
echo "/* end $type target macros */"
echo "#endif"
+ echo "#endif"
else
echo "/* end $target $type target macros */"
echo "#endif"
diff --git a/sim/common/nltvals.def b/sim/common/nltvals.def
index 9139dc4..12ee2a8 100644
--- a/sim/common/nltvals.def
+++ b/sim/common/nltvals.def
@@ -1,420 +1,722 @@
/* Newlib/libgloss macro values needed by remote target support. */
/* This file is machine generated by gennltvals.sh. */
+#ifndef NL_errno_tgt_specific
#ifdef errno_defs
/* from errno.h */
/* from sys/errno.h */
/* begin errno target macros */
- { "E2BIG", 7 },
- { "EACCES", 13 },
- { "EADDRINUSE", 112 },
- { "EADDRNOTAVAIL", 125 },
- { "EADV", 68 },
- { "EAFNOSUPPORT", 106 },
- { "EAGAIN", 11 },
- { "EALREADY", 120 },
- { "EBADE", 50 },
- { "EBADF", 9 },
- { "EBADFD", 81 },
- { "EBADMSG", 77 },
- { "EBADR", 51 },
- { "EBADRQC", 54 },
- { "EBADSLT", 55 },
- { "EBFONT", 57 },
- { "EBUSY", 16 },
- { "ECHILD", 10 },
- { "ECHRNG", 37 },
- { "ECOMM", 70 },
- { "ECONNABORTED", 113 },
- { "ECONNREFUSED", 111 },
- { "ECONNRESET", 104 },
- { "EDEADLK", 45 },
- { "EDEADLOCK", 56 },
- { "EDESTADDRREQ", 121 },
- { "EDOM", 33 },
- { "EDOTDOT", 76 },
- { "EDQUOT", 132 },
- { "EEXIST", 17 },
- { "EFAULT", 14 },
- { "EFBIG", 27 },
- { "EHOSTDOWN", 117 },
- { "EHOSTUNREACH", 118 },
- { "EIDRM", 36 },
- { "EINPROGRESS", 119 },
- { "EINTR", 4 },
- { "EINVAL", 22 },
- { "EIO", 5 },
- { "EISCONN", 127 },
- { "EISDIR", 21 },
- { "EL2HLT", 44 },
- { "EL2NSYNC", 38 },
- { "EL3HLT", 39 },
- { "EL3RST", 40 },
- { "ELBIN", 75 },
- { "ELIBACC", 83 },
- { "ELIBBAD", 84 },
- { "ELIBEXEC", 87 },
- { "ELIBMAX", 86 },
- { "ELIBSCN", 85 },
- { "ELNRNG", 41 },
- { "ELOOP", 92 },
- { "EMFILE", 24 },
- { "EMLINK", 31 },
- { "EMSGSIZE", 122 },
- { "EMULTIHOP", 74 },
- { "ENAMETOOLONG", 91 },
- { "ENETDOWN", 115 },
- { "ENETRESET", 126 },
- { "ENETUNREACH", 114 },
- { "ENFILE", 23 },
- { "ENMFILE", 89 },
- { "ENOANO", 53 },
- { "ENOBUFS", 105 },
- { "ENOCSI", 43 },
- { "ENODATA", 61 },
- { "ENODEV", 19 },
- { "ENOENT", 2 },
- { "ENOEXEC", 8 },
- { "ENOLCK", 46 },
- { "ENOLINK", 67 },
- { "ENOMEM", 12 },
- { "ENOMSG", 35 },
- { "ENONET", 64 },
- { "ENOPKG", 65 },
- { "ENOPROTOOPT", 109 },
- { "ENOSPC", 28 },
- { "ENOSR", 63 },
- { "ENOSTR", 60 },
- { "ENOSYS", 88 },
- { "ENOTBLK", 15 },
- { "ENOTCONN", 128 },
- { "ENOTDIR", 20 },
- { "ENOTEMPTY", 90 },
- { "ENOTSOCK", 108 },
- { "ENOTSUP", 134 },
- { "ENOTTY", 25 },
- { "ENOTUNIQ", 80 },
- { "ENXIO", 6 },
- { "EOPNOTSUPP", 95 },
- { "EPERM", 1 },
- { "EPFNOSUPPORT", 96 },
- { "EPIPE", 32 },
- { "EPROCLIM", 130 },
- { "EPROTO", 71 },
- { "EPROTONOSUPPORT", 123 },
- { "EPROTOTYPE", 107 },
- { "ERANGE", 34 },
- { "EREMCHG", 82 },
- { "EREMOTE", 66 },
- { "EROFS", 30 },
- { "ESHUTDOWN", 110 },
- { "ESOCKTNOSUPPORT", 124 },
- { "ESPIPE", 29 },
- { "ESRCH", 3 },
- { "ESRMNT", 69 },
- { "ESTALE", 133 },
- { "ETIME", 62 },
- { "ETIMEDOUT", 116 },
- { "ETOOMANYREFS", 129 },
- { "ETXTBSY", 26 },
- { "EUNATCH", 42 },
- { "EUSERS", 131 },
- { "EWOULDBLOCK", 11 },
- { "EXDEV", 18 },
- { "EXFULL", 52 },
+ { "E2BIG", 7 },
+ { "EACCES", 13 },
+ { "EADDRINUSE", 112 },
+ { "EADDRNOTAVAIL", 125 },
+ { "EADV", 68 },
+ { "EAFNOSUPPORT", 106 },
+ { "EAGAIN", 11 },
+ { "EALREADY", 120 },
+ { "EBADE", 50 },
+ { "EBADF", 9 },
+ { "EBADFD", 81 },
+ { "EBADMSG", 77 },
+ { "EBADR", 51 },
+ { "EBADRQC", 54 },
+ { "EBADSLT", 55 },
+ { "EBFONT", 57 },
+ { "EBUSY", 16 },
+ { "ECANCELED", 140 },
+ { "ECASECLASH", 137 },
+ { "ECHILD", 10 },
+ { "ECHRNG", 37 },
+ { "ECOMM", 70 },
+ { "ECONNABORTED", 113 },
+ { "ECONNREFUSED", 111 },
+ { "ECONNRESET", 104 },
+ { "EDEADLK", 45 },
+ { "EDEADLOCK", 56 },
+ { "EDESTADDRREQ", 121 },
+ { "EDOM", 33 },
+ { "EDOTDOT", 76 },
+ { "EDQUOT", 132 },
+ { "EEXIST", 17 },
+ { "EFAULT", 14 },
+ { "EFBIG", 27 },
+ { "EFTYPE", 79 },
+ { "EHOSTDOWN", 117 },
+ { "EHOSTUNREACH", 118 },
+ { "EIDRM", 36 },
+ { "EILSEQ", 138 },
+ { "EINPROGRESS", 119 },
+ { "EINTR", 4 },
+ { "EINVAL", 22 },
+ { "EIO", 5 },
+ { "EISCONN", 127 },
+ { "EISDIR", 21 },
+ { "EL2HLT", 44 },
+ { "EL2NSYNC", 38 },
+ { "EL3HLT", 39 },
+ { "EL3RST", 40 },
+ { "ELBIN", 75 },
+ { "ELIBACC", 83 },
+ { "ELIBBAD", 84 },
+ { "ELIBEXEC", 87 },
+ { "ELIBMAX", 86 },
+ { "ELIBSCN", 85 },
+ { "ELNRNG", 41 },
+ { "ELOOP", 92 },
+ { "EMFILE", 24 },
+ { "EMLINK", 31 },
+ { "EMSGSIZE", 122 },
+ { "EMULTIHOP", 74 },
+ { "ENAMETOOLONG", 91 },
+ { "ENETDOWN", 115 },
+ { "ENETRESET", 126 },
+ { "ENETUNREACH", 114 },
+ { "ENFILE", 23 },
+ { "ENMFILE", 89 },
+ { "ENOANO", 53 },
+ { "ENOBUFS", 105 },
+ { "ENOCSI", 43 },
+ { "ENODATA", 61 },
+ { "ENODEV", 19 },
+ { "ENOENT", 2 },
+ { "ENOEXEC", 8 },
+ { "ENOLCK", 46 },
+ { "ENOLINK", 67 },
+ { "ENOMEDIUM", 135 },
+ { "ENOMEM", 12 },
+ { "ENOMSG", 35 },
+ { "ENONET", 64 },
+ { "ENOPKG", 65 },
+ { "ENOPROTOOPT", 109 },
+ { "ENOSHARE", 136 },
+ { "ENOSPC", 28 },
+ { "ENOSR", 63 },
+ { "ENOSTR", 60 },
+ { "ENOSYS", 88 },
+ { "ENOTBLK", 15 },
+ { "ENOTCONN", 128 },
+ { "ENOTDIR", 20 },
+ { "ENOTEMPTY", 90 },
+ { "ENOTSOCK", 108 },
+ { "ENOTSUP", 134 },
+ { "ENOTTY", 25 },
+ { "ENOTUNIQ", 80 },
+ { "ENXIO", 6 },
+ { "EOPNOTSUPP", 95 },
+ { "EOVERFLOW", 139 },
+ { "EPERM", 1 },
+ { "EPFNOSUPPORT", 96 },
+ { "EPIPE", 32 },
+ { "EPROCLIM", 130 },
+ { "EPROTO", 71 },
+ { "EPROTONOSUPPORT", 123 },
+ { "EPROTOTYPE", 107 },
+ { "ERANGE", 34 },
+ { "EREMCHG", 82 },
+ { "EREMOTE", 66 },
+ { "EROFS", 30 },
+ { "ESHUTDOWN", 110 },
+ { "ESOCKTNOSUPPORT", 124 },
+ { "ESPIPE", 29 },
+ { "ESRCH", 3 },
+ { "ESRMNT", 69 },
+ { "ESTALE", 133 },
+ { "ETIME", 62 },
+ { "ETIMEDOUT", 116 },
+ { "ETOOMANYREFS", 129 },
+ { "ETXTBSY", 26 },
+ { "EUNATCH", 42 },
+ { "EUSERS", 131 },
+ { "EWOULDBLOCK", 11 },
+ { "EXDEV", 18 },
+ { "EXFULL", 52 },
/* end errno target macros */
#endif
+#endif
+#ifndef NL_signal_tgt_specific
#ifdef signal_defs
/* from signal.h */
/* from sys/signal.h */
/* begin signal target macros */
- { "SIGABRT", 6 },
- { "SIGALRM", 14 },
- { "SIGBUS", 10 },
- { "SIGCHLD", 20 },
- { "SIGCLD", 20 },
- { "SIGCONT", 19 },
- { "SIGEMT", 7 },
- { "SIGFPE", 8 },
- { "SIGHUP", 1 },
- { "SIGILL", 4 },
- { "SIGINT", 2 },
- { "SIGIO", 23 },
- { "SIGIOT", 6 },
- { "SIGKILL", 9 },
- { "SIGLOST", 29 },
- { "SIGPIPE", 13 },
- { "SIGPOLL", 23 },
- { "SIGPROF", 27 },
- { "SIGQUIT", 3 },
- { "SIGSEGV", 11 },
- { "SIGSTOP", 17 },
- { "SIGSYS", 12 },
- { "SIGTERM", 15 },
- { "SIGTRAP", 5 },
- { "SIGTSTP", 18 },
- { "SIGTTIN", 21 },
- { "SIGTTOU", 22 },
- { "SIGURG", 16 },
- { "SIGUSR1", 30 },
- { "SIGUSR2", 31 },
- { "SIGVTALRM", 26 },
- { "SIGWINCH", 28 },
- { "SIGXCPU", 24 },
- { "SIGXFSZ", 25 },
+ { "SIGABRT", 6 },
+ { "SIGALRM", 14 },
+ { "SIGBUS", 10 },
+ { "SIGCHLD", 20 },
+ { "SIGCLD", 20 },
+ { "SIGCONT", 19 },
+ { "SIGEMT", 7 },
+ { "SIGFPE", 8 },
+ { "SIGHUP", 1 },
+ { "SIGILL", 4 },
+ { "SIGINT", 2 },
+ { "SIGIO", 23 },
+ { "SIGIOT", 6 },
+ { "SIGKILL", 9 },
+ { "SIGLOST", 29 },
+ { "SIGPIPE", 13 },
+ { "SIGPOLL", 23 },
+ { "SIGPROF", 27 },
+ { "SIGQUIT", 3 },
+ { "SIGSEGV", 11 },
+ { "SIGSTOP", 17 },
+ { "SIGSYS", 12 },
+ { "SIGTERM", 15 },
+ { "SIGTRAP", 5 },
+ { "SIGTSTP", 18 },
+ { "SIGTTIN", 21 },
+ { "SIGTTOU", 22 },
+ { "SIGURG", 16 },
+ { "SIGUSR1", 30 },
+ { "SIGUSR2", 31 },
+ { "SIGVTALRM", 26 },
+ { "SIGWINCH", 28 },
+ { "SIGXCPU", 24 },
+ { "SIGXFSZ", 25 },
/* end signal target macros */
#endif
+#endif
+#ifdef NL_TARGET_arc
+#ifdef open_defs
+#define NL_open_tgt_specific
+/* from ../sys/arc/sys/fcntl.h */
+/* begin arc open target macros */
+ { "O_ACCMODE", (0|1|2) },
+ { "O_APPEND", 0x0400 },
+ { "O_CREAT", 0x0040 },
+ { "O_EXCL", 0x0080 },
+ { "O_NOCTTY", 0x0100 },
+ { "O_NONBLOCK", 0x0800 },
+ { "O_RDONLY", 0 },
+ { "O_RDWR", 2 },
+ { "O_SYNC", 0x1000 },
+ { "O_TRUNC", 0x0200 },
+ { "O_WRONLY", 1 },
+/* end arc open target macros */
+#endif
+#endif
+#ifndef NL_open_tgt_specific
#ifdef open_defs
/* from fcntl.h */
/* from sys/fcntl.h */
/* begin open target macros */
- { "O_ACCMODE", (0 | 1 | 2 ) },
- { "O_APPEND", 0x0008 },
- { "O_CREAT", 0x0200 },
- { "O_EXCL", 0x0800 },
- { "O_NOCTTY", 0x8000 },
- { "O_NONBLOCK", 0x4000 },
- { "O_RDONLY", 0 },
- { "O_RDWR", 2 },
- { "O_SYNC", 0x2000 },
- { "O_TRUNC", 0x0400 },
- { "O_WRONLY", 1 },
+ { "O_ACCMODE", (0|1|2) },
+ { "O_APPEND", 0x0008 },
+ { "O_CREAT", 0x0200 },
+ { "O_EXCL", 0x0800 },
+ { "O_NOCTTY", 0x8000 },
+ { "O_NONBLOCK", 0x4000 },
+ { "O_RDONLY", 0 },
+ { "O_RDWR", 2 },
+ { "O_SYNC", 0x2000 },
+ { "O_TRUNC", 0x0400 },
+ { "O_WRONLY", 1 },
/* end open target macros */
#endif
+#endif
+#ifdef NL_TARGET_arc
+#ifdef sys_defs
+#define NL_sys_tgt_specific
+/* from syscall.h */
+/* begin arc sys target macros */
+ { "SYS_access", 33 },
+ { "SYS_acct", 51 },
+ { "SYS_adjtimex", 124 },
+ { "SYS_afs_syscall", 137 },
+ { "SYS_alarm", 27 },
+ { "SYS_bdflush", 134 },
+ { "SYS_break", 17 },
+ { "SYS_brk", 45 },
+ { "SYS_cacheflush", 123 },
+ { "SYS_capget", 184 },
+ { "SYS_capset", 185 },
+ { "SYS_chdir", 12 },
+ { "SYS_chmod", 15 },
+ { "SYS_chown", 16 },
+ { "SYS_chown32", 198 },
+ { "SYS_chroot", 61 },
+ { "SYS_clone", 120 },
+ { "SYS_close", 6 },
+ { "SYS_creat", 8 },
+ { "SYS_create_module", 127 },
+ { "SYS_delete_module", 129 },
+ { "SYS_dup", 41 },
+ { "SYS_dup2", 63 },
+ { "SYS_execve", 11 },
+ { "SYS_exit", 1 },
+ { "SYS_fchdir", 133 },
+ { "SYS_fchmod", 94 },
+ { "SYS_fchown", 95 },
+ { "SYS_fchown32", 207 },
+ { "SYS_fcntl", 55 },
+ { "SYS_fcntl64", 221 },
+ { "SYS_fdatasync", 148 },
+ { "SYS_flock", 143 },
+ { "SYS_fork", 2 },
+ { "SYS_fstat", 108 },
+ { "SYS_fstat64", 197 },
+ { "SYS_fstatfs", 100 },
+ { "SYS_fsync", 118 },
+ { "SYS_ftime", 35 },
+ { "SYS_ftruncate", 93 },
+ { "SYS_ftruncate64", 194 },
+ { "SYS_getcwd", 183 },
+ { "SYS_getdents", 141 },
+ { "SYS_getdents64", 220 },
+ { "SYS_getegid", 50 },
+ { "SYS_getegid32", 202 },
+ { "SYS_geteuid", 49 },
+ { "SYS_geteuid32", 201 },
+ { "SYS_getgid", 47 },
+ { "SYS_getgid32", 200 },
+ { "SYS_getgroups", 80 },
+ { "SYS_getgroups32", 205 },
+ { "SYS_getitimer", 105 },
+ { "SYS_get_kernel_syms", 130 },
+ { "SYS_getpgid", 132 },
+ { "SYS_getpgrp", 65 },
+ { "SYS_getpid", 20 },
+ { "SYS_getpmsg", 188 },
+ { "SYS_getppid", 64 },
+ { "SYS_getpriority", 96 },
+ { "SYS_getresgid", 171 },
+ { "SYS_getresgid32", 211 },
+ { "SYS_getresuid", 165 },
+ { "SYS_getresuid32", 209 },
+ { "SYS_getrlimit", 191 },
+ { "SYS_getrusage", 77 },
+ { "SYS_getsid", 147 },
+ { "SYS_gettid", 224 },
+ { "SYS_gettimeofday", 78 },
+ { "SYS_getuid", 24 },
+ { "SYS_getuid32", 199 },
+ { "SYS_gtty", 32 },
+ { "SYS_idle", 112 },
+ { "SYS_init_module", 128 },
+ { "SYS_ioctl", 54 },
+ { "SYS_ioperm", 101 },
+ { "SYS_iopl", 110 },
+ { "SYS_ipc", 117 },
+ { "SYS_kill", 37 },
+ { "SYS_lchown", 182 },
+ { "SYS_lchown32", 212 },
+ { "SYS_link", 9 },
+ { "SYS__llseek", 140 },
+ { "SYS_lock", 53 },
+ { "SYS_lseek", 19 },
+ { "SYS_lstat", 107 },
+ { "SYS_lstat64", 196 },
+ { "SYS_mkdir", 39 },
+ { "SYS_mknod", 14 },
+ { "SYS_mlock", 150 },
+ { "SYS_mlockall", 152 },
+ { "SYS_mmap", 90 },
+ { "SYS_mmap2", 192 },
+ { "SYS_mount", 21 },
+ { "SYS_mprotect", 125 },
+ { "SYS_mpx", 56 },
+ { "SYS_mremap", 163 },
+ { "SYS_msync", 144 },
+ { "SYS_munlock", 151 },
+ { "SYS_munlockall", 153 },
+ { "SYS_munmap", 91 },
+ { "SYS_nanosleep", 162 },
+ { "SYS__newselect", 142 },
+ { "SYS_nfsservctl", 169 },
+ { "SYS_nice", 34 },
+ { "SYS_oldfstat", 28 },
+ { "SYS_old_getrlimit", 76 },
+ { "SYS_oldlstat", 84 },
+ { "SYS_oldolduname", 59 },
+ { "SYS_oldstat", 18 },
+ { "SYS_olduname", 109 },
+ { "SYS_open", 5 },
+ { "SYS_pause", 29 },
+ { "SYS_personality", 136 },
+ { "SYS_pipe", 42 },
+ { "SYS_pivot_root", 217 },
+ { "SYS_poll", 168 },
+ { "SYS_prctl", 172 },
+ { "SYS_pread", 180 },
+ { "SYS_prof", 44 },
+ { "SYS_profil", 98 },
+ { "SYS_ptrace", 26 },
+ { "SYS_putpmsg", 189 },
+ { "SYS_pwrite", 181 },
+ { "SYS_query_module", 167 },
+ { "SYS_quotactl", 131 },
+ { "SYS_read", 3 },
+ { "SYS_readdir", 89 },
+ { "SYS_readlink", 85 },
+ { "SYS_readv", 145 },
+ { "SYS_reboot", 88 },
+ { "SYS_rename", 38 },
+ { "SYS_rmdir", 40 },
+ { "SYS_rt_sigaction", 174 },
+ { "SYS_rt_sigpending", 176 },
+ { "SYS_rt_sigprocmask", 175 },
+ { "SYS_rt_sigqueueinfo", 178 },
+ { "SYS_rt_sigreturn", 173 },
+ { "SYS_rt_sigsuspend", 179 },
+ { "SYS_rt_sigtimedwait", 177 },
+ { "SYS_sched_getparam", 155 },
+ { "SYS_sched_get_priority_max", 159 },
+ { "SYS_sched_get_priority_min", 160 },
+ { "SYS_sched_getscheduler", 157 },
+ { "SYS_sched_rr_get_interval", 161 },
+ { "SYS_sched_setparam", 154 },
+ { "SYS_sched_setscheduler", 156 },
+ { "SYS_sched_yield", 158 },
+ { "SYS_select", 82 },
+ { "SYS_sendfile", 187 },
+ { "SYS_setdomainname", 121 },
+ { "SYS_setfsgid", 139 },
+ { "SYS_setfsgid32", 216 },
+ { "SYS_setfsuid", 138 },
+ { "SYS_setfsuid32", 215 },
+ { "SYS_setgid", 46 },
+ { "SYS_setgid32", 214 },
+ { "SYS_setgroups", 81 },
+ { "SYS_setgroups32", 206 },
+ { "SYS_sethostname", 74 },
+ { "SYS_setitimer", 104 },
+ { "SYS_setpgid", 57 },
+ { "SYS_setpriority", 97 },
+ { "SYS_setregid", 71 },
+ { "SYS_setregid32", 204 },
+ { "SYS_setresgid", 170 },
+ { "SYS_setresgid32", 210 },
+ { "SYS_setresuid", 164 },
+ { "SYS_setresuid32", 208 },
+ { "SYS_setreuid", 70 },
+ { "SYS_setreuid32", 203 },
+ { "SYS_setrlimit", 75 },
+ { "SYS_setsid", 66 },
+ { "SYS_settimeofday", 79 },
+ { "SYS_setuid", 23 },
+ { "SYS_setuid32", 213 },
+ { "SYS_sgetmask", 68 },
+ { "SYS_sigaction", 67 },
+ { "SYS_sigaltstack", 186 },
+ { "SYS_signal", 48 },
+ { "SYS_sigpending", 73 },
+ { "SYS_sigprocmask", 126 },
+ { "SYS_sigreturn", 119 },
+ { "SYS_sigsuspend", 72 },
+ { "SYS_socketcall", 102 },
+ { "SYS_ssetmask", 69 },
+ { "SYS_stat", 106 },
+ { "SYS_stat64", 195 },
+ { "SYS_statfs", 99 },
+ { "SYS_stime", 25 },
+ { "SYS_stty", 31 },
+ { "SYS_swapoff", 115 },
+ { "SYS_swapon", 87 },
+ { "SYS_symlink", 83 },
+ { "SYS_sync", 36 },
+ { "SYS__sysctl", 149 },
+ { "SYS_sysfs", 135 },
+ { "SYS_sysinfo", 116 },
+ { "SYS_syslog", 103 },
+ { "SYS_time", 13 },
+ { "SYS_times", 43 },
+ { "SYS_truncate", 92 },
+ { "SYS_truncate64", 193 },
+ { "SYS_ulimit", 58 },
+ { "SYS_umask", 60 },
+ { "SYS_umount", 22 },
+ { "SYS_umount2", 52 },
+ { "SYS_uname", 122 },
+ { "SYS_unlink", 10 },
+ { "SYS_uselib", 86 },
+ { "SYS_ustat", 62 },
+ { "SYS_utime", 30 },
+ { "SYS_vfork", 190 },
+ { "SYS_vhangup", 111 },
+ { "SYS_vm86", 113 },
+ { "SYS_wait4", 114 },
+ { "SYS_waitpid", 7 },
+ { "SYS_write", 4 },
+ { "SYS_writev", 146 },
+/* end arc sys target macros */
+#endif
+#endif
#ifdef NL_TARGET_d10v
#ifdef sys_defs
+#define NL_sys_tgt_specific
/* from syscall.h */
/* begin d10v sys target macros */
- { "SYS_ARG", 24 },
- { "SYS_chdir", 12 },
- { "SYS_chmod", 15 },
- { "SYS_chown", 16 },
- { "SYS_close", 6 },
- { "SYS_creat", 8 },
- { "SYS_execv", 11 },
- { "SYS_execve", 59 },
- { "SYS_exit", 1 },
- { "SYS_fork", 2 },
- { "SYS_fstat", 22 },
- { "SYS_getpid", 20 },
- { "SYS_isatty", 21 },
- { "SYS_kill", 60 },
- { "SYS_link", 9 },
- { "SYS_lseek", 19 },
- { "SYS_mknod", 14 },
- { "SYS_open", 5 },
- { "SYS_pipe", 42 },
- { "SYS_read", 3 },
- { "SYS_stat", 38 },
- { "SYS_time", 23 },
- { "SYS_unlink", 10 },
- { "SYS_utime", 201 },
- { "SYS_wait", 202 },
- { "SYS_wait4", 7 },
- { "SYS_write", 4 },
+ { "SYS_ARG", 24 },
+ { "SYS_chdir", 12 },
+ { "SYS_chmod", 15 },
+ { "SYS_chown", 16 },
+ { "SYS_close", 6 },
+ { "SYS_creat", 8 },
+ { "SYS_execv", 11 },
+ { "SYS_execve", 59 },
+ { "SYS_exit", 1 },
+ { "SYS_fork", 2 },
+ { "SYS_fstat", 22 },
+ { "SYS_getpid", 20 },
+ { "SYS_isatty", 21 },
+ { "SYS_kill", 60 },
+ { "SYS_link", 9 },
+ { "SYS_lseek", 19 },
+ { "SYS_mknod", 14 },
+ { "SYS_open", 5 },
+ { "SYS_pipe", 42 },
+ { "SYS_read", 3 },
+ { "SYS_stat", 38 },
+ { "SYS_time", 23 },
+ { "SYS_unlink", 10 },
+ { "SYS_utime", 201 },
+ { "SYS_wait", 202 },
+ { "SYS_wait4", 7 },
+ { "SYS_write", 4 },
/* end d10v sys target macros */
#endif
#endif
#ifdef NL_TARGET_fr30
#ifdef sys_defs
+#define NL_sys_tgt_specific
/* from syscall.h */
/* begin fr30 sys target macros */
- { "SYS_argv", 13 },
- { "SYS_argvlen", 12 },
- { "SYS_chdir", 14 },
- { "SYS_chmod", 16 },
- { "SYS_close", 3 },
- { "SYS_exit", 1 },
- { "SYS_fstat", 10 },
- { "SYS_getpid", 8 },
- { "SYS_kill", 9 },
- { "SYS_lseek", 6 },
- { "SYS_open", 2 },
- { "SYS_read", 4 },
- { "SYS_stat", 15 },
- { "SYS_time", 18 },
- { "SYS_unlink", 7 },
- { "SYS_utime", 17 },
- { "SYS_write", 5 },
+ { "SYS_argc", 22 },
+ { "SYS_argn", 24 },
+ { "SYS_argnlen", 23 },
+ { "SYS_argv", 13 },
+ { "SYS_argvlen", 12 },
+ { "SYS_chdir", 14 },
+ { "SYS_chmod", 16 },
+ { "SYS_close", 3 },
+ { "SYS_exit", 1 },
+ { "SYS_fstat", 10 },
+ { "SYS_getpid", 8 },
+ { "SYS_gettimeofday", 19 },
+ { "SYS_kill", 9 },
+ { "SYS_link", 21 },
+ { "SYS_lseek", 6 },
+ { "SYS_open", 2 },
+ { "SYS_read", 4 },
+ { "SYS_stat", 15 },
+ { "SYS_time", 18 },
+ { "SYS_times", 20 },
+ { "SYS_unlink", 7 },
+ { "SYS_utime", 17 },
+ { "SYS_write", 5 },
/* end fr30 sys target macros */
#endif
#endif
#ifdef NL_TARGET_frv
#ifdef sys_defs
+#define NL_sys_tgt_specific
/* from syscall.h */
/* begin frv sys target macros */
- { "SYS_argv", 13 },
- { "SYS_argvlen", 12 },
- { "SYS_chdir", 14 },
- { "SYS_chmod", 16 },
- { "SYS_close", 3 },
- { "SYS_exit", 1 },
- { "SYS_fstat", 10 },
- { "SYS_getpid", 8 },
- { "SYS_gettimeofday", 19 },
- { "SYS_kill", 9 },
- { "SYS_lseek", 6 },
- { "SYS_open", 2 },
- { "SYS_read", 4 },
- { "SYS_stat", 15 },
- { "SYS_time", 18 },
- { "SYS_times", 20 },
- { "SYS_unlink", 7 },
- { "SYS_utime", 17 },
- { "SYS_write", 5 },
+ { "SYS_argc", 22 },
+ { "SYS_argn", 24 },
+ { "SYS_argnlen", 23 },
+ { "SYS_argv", 13 },
+ { "SYS_argvlen", 12 },
+ { "SYS_chdir", 14 },
+ { "SYS_chmod", 16 },
+ { "SYS_close", 3 },
+ { "SYS_exit", 1 },
+ { "SYS_fstat", 10 },
+ { "SYS_getpid", 8 },
+ { "SYS_gettimeofday", 19 },
+ { "SYS_kill", 9 },
+ { "SYS_link", 21 },
+ { "SYS_lseek", 6 },
+ { "SYS_open", 2 },
+ { "SYS_read", 4 },
+ { "SYS_stat", 15 },
+ { "SYS_time", 18 },
+ { "SYS_times", 20 },
+ { "SYS_unlink", 7 },
+ { "SYS_utime", 17 },
+ { "SYS_write", 5 },
/* end frv sys target macros */
#endif
#endif
#ifdef NL_TARGET_i960
#ifdef sys_defs
+#define NL_sys_tgt_specific
/* from syscall.h */
/* begin i960 sys target macros */
- { "SYS_argv", 13 },
- { "SYS_argvlen", 12 },
- { "SYS_chdir", 14 },
- { "SYS_chmod", 16 },
- { "SYS_close", 234 },
- { "SYS_exit", 257 },
- { "SYS_fstat", 10 },
- { "SYS_getpid", 8 },
- { "SYS_kill", 9 },
- { "SYS_lseek", 233 },
- { "SYS_open", 230 },
- { "SYS_read", 231 },
- { "SYS_stat", 15 },
- { "SYS_time", 18 },
- { "SYS_unlink", 7 },
- { "SYS_utime", 17 },
- { "SYS_write", 232 },
+ { "SYS_argv", 13 },
+ { "SYS_argvlen", 12 },
+ { "SYS_chdir", 14 },
+ { "SYS_chmod", 16 },
+ { "SYS_close", 234 },
+ { "SYS_exit", 257 },
+ { "SYS_fstat", 10 },
+ { "SYS_getpid", 8 },
+ { "SYS_kill", 9 },
+ { "SYS_lseek", 233 },
+ { "SYS_open", 230 },
+ { "SYS_read", 231 },
+ { "SYS_stat", 15 },
+ { "SYS_time", 18 },
+ { "SYS_unlink", 7 },
+ { "SYS_utime", 17 },
+ { "SYS_write", 232 },
/* end i960 sys target macros */
#endif
#endif
#ifdef NL_TARGET_m32r
#ifdef sys_defs
+#define NL_sys_tgt_specific
/* from syscall.h */
/* begin m32r sys target macros */
- { "SYS_argv", 13 },
- { "SYS_argvlen", 12 },
- { "SYS_chdir", 14 },
- { "SYS_chmod", 16 },
- { "SYS_close", 3 },
- { "SYS_exit", 1 },
- { "SYS_fstat", 10 },
- { "SYS_getpid", 8 },
- { "SYS_kill", 9 },
- { "SYS_lseek", 6 },
- { "SYS_open", 2 },
- { "SYS_read", 4 },
- { "SYS_stat", 15 },
- { "SYS_time", 18 },
- { "SYS_unlink", 7 },
- { "SYS_utime", 17 },
- { "SYS_write", 5 },
+ { "SYS_argc", 22 },
+ { "SYS_argn", 24 },
+ { "SYS_argnlen", 23 },
+ { "SYS_argv", 13 },
+ { "SYS_argvlen", 12 },
+ { "SYS_chdir", 14 },
+ { "SYS_chmod", 16 },
+ { "SYS_close", 3 },
+ { "SYS_exit", 1 },
+ { "SYS_fstat", 10 },
+ { "SYS_getpid", 8 },
+ { "SYS_gettimeofday", 19 },
+ { "SYS_kill", 9 },
+ { "SYS_link", 21 },
+ { "SYS_lseek", 6 },
+ { "SYS_open", 2 },
+ { "SYS_read", 4 },
+ { "SYS_stat", 15 },
+ { "SYS_time", 18 },
+ { "SYS_times", 20 },
+ { "SYS_unlink", 7 },
+ { "SYS_utime", 17 },
+ { "SYS_write", 5 },
/* end m32r sys target macros */
#endif
#endif
#ifdef NL_TARGET_mn10200
#ifdef sys_defs
+#define NL_sys_tgt_specific
/* from syscall.h */
/* begin mn10200 sys target macros */
- { "SYS_argv", 13 },
- { "SYS_argvlen", 12 },
- { "SYS_chdir", 14 },
- { "SYS_chmod", 16 },
- { "SYS_close", 3 },
- { "SYS_exit", 1 },
- { "SYS_fstat", 10 },
- { "SYS_getpid", 8 },
- { "SYS_kill", 9 },
- { "SYS_lseek", 6 },
- { "SYS_open", 2 },
- { "SYS_read", 4 },
- { "SYS_stat", 15 },
- { "SYS_time", 18 },
- { "SYS_unlink", 7 },
- { "SYS_utime", 17 },
- { "SYS_write", 5 },
+ { "SYS_argc", 22 },
+ { "SYS_argn", 24 },
+ { "SYS_argnlen", 23 },
+ { "SYS_argv", 13 },
+ { "SYS_argvlen", 12 },
+ { "SYS_chdir", 14 },
+ { "SYS_chmod", 16 },
+ { "SYS_close", 3 },
+ { "SYS_exit", 1 },
+ { "SYS_fstat", 10 },
+ { "SYS_getpid", 8 },
+ { "SYS_gettimeofday", 19 },
+ { "SYS_kill", 9 },
+ { "SYS_link", 21 },
+ { "SYS_lseek", 6 },
+ { "SYS_open", 2 },
+ { "SYS_read", 4 },
+ { "SYS_stat", 15 },
+ { "SYS_time", 18 },
+ { "SYS_times", 20 },
+ { "SYS_unlink", 7 },
+ { "SYS_utime", 17 },
+ { "SYS_write", 5 },
/* end mn10200 sys target macros */
#endif
#endif
#ifdef NL_TARGET_mn10300
#ifdef sys_defs
+#define NL_sys_tgt_specific
/* from syscall.h */
/* begin mn10300 sys target macros */
- { "SYS_argv", 13 },
- { "SYS_argvlen", 12 },
- { "SYS_chdir", 14 },
- { "SYS_chmod", 16 },
- { "SYS_close", 3 },
- { "SYS_exit", 1 },
- { "SYS_fstat", 10 },
- { "SYS_getpid", 8 },
- { "SYS_kill", 9 },
- { "SYS_lseek", 6 },
- { "SYS_open", 2 },
- { "SYS_read", 4 },
- { "SYS_stat", 15 },
- { "SYS_time", 18 },
- { "SYS_unlink", 7 },
- { "SYS_utime", 17 },
- { "SYS_write", 5 },
+ { "SYS_argc", 22 },
+ { "SYS_argn", 24 },
+ { "SYS_argnlen", 23 },
+ { "SYS_argv", 13 },
+ { "SYS_argvlen", 12 },
+ { "SYS_chdir", 14 },
+ { "SYS_chmod", 16 },
+ { "SYS_close", 3 },
+ { "SYS_exit", 1 },
+ { "SYS_fstat", 10 },
+ { "SYS_getpid", 8 },
+ { "SYS_gettimeofday", 19 },
+ { "SYS_kill", 9 },
+ { "SYS_link", 21 },
+ { "SYS_lseek", 6 },
+ { "SYS_open", 2 },
+ { "SYS_read", 4 },
+ { "SYS_stat", 15 },
+ { "SYS_time", 18 },
+ { "SYS_times", 20 },
+ { "SYS_unlink", 7 },
+ { "SYS_utime", 17 },
+ { "SYS_write", 5 },
/* end mn10300 sys target macros */
#endif
#endif
#ifdef NL_TARGET_sparc
#ifdef sys_defs
+#define NL_sys_tgt_specific
/* from syscall.h */
/* begin sparc sys target macros */
- { "SYS_argv", 13 },
- { "SYS_argvlen", 12 },
- { "SYS_chdir", 14 },
- { "SYS_chmod", 16 },
- { "SYS_close", 3 },
- { "SYS_exit", 1 },
- { "SYS_fstat", 10 },
- { "SYS_getpid", 8 },
- { "SYS_kill", 9 },
- { "SYS_lseek", 6 },
- { "SYS_open", 2 },
- { "SYS_read", 4 },
- { "SYS_stat", 15 },
- { "SYS_time", 18 },
- { "SYS_unlink", 7 },
- { "SYS_utime", 17 },
- { "SYS_write", 5 },
+ { "SYS_argc", 22 },
+ { "SYS_argn", 24 },
+ { "SYS_argnlen", 23 },
+ { "SYS_argv", 13 },
+ { "SYS_argvlen", 12 },
+ { "SYS_chdir", 14 },
+ { "SYS_chmod", 16 },
+ { "SYS_close", 3 },
+ { "SYS_exit", 1 },
+ { "SYS_fstat", 10 },
+ { "SYS_getpid", 8 },
+ { "SYS_gettimeofday", 19 },
+ { "SYS_kill", 9 },
+ { "SYS_link", 21 },
+ { "SYS_lseek", 6 },
+ { "SYS_open", 2 },
+ { "SYS_read", 4 },
+ { "SYS_stat", 15 },
+ { "SYS_time", 18 },
+ { "SYS_times", 20 },
+ { "SYS_unlink", 7 },
+ { "SYS_utime", 17 },
+ { "SYS_write", 5 },
/* end sparc sys target macros */
#endif
#endif
#ifdef NL_TARGET_v850
#ifdef sys_defs
+#define NL_sys_tgt_specific
/* from syscall.h */
/* begin v850 sys target macros */
- { "SYS_ARG", 24 },
- { "SYS_chdir", 12 },
- { "SYS_chmod", 15 },
- { "SYS_chown", 16 },
- { "SYS_close", 6 },
- { "SYS_creat", 8 },
- { "SYS_execv", 11 },
- { "SYS_execve", 59 },
- { "SYS_exit", 1 },
- { "SYS_fork", 2 },
- { "SYS_fstat", 22 },
- { "SYS_getpid", 20 },
- { "SYS_gettimeofday", 116 },
- { "SYS_isatty", 21 },
- { "SYS_link", 9 },
- { "SYS_lseek", 19 },
- { "SYS_mknod", 14 },
- { "SYS_open", 5 },
- { "SYS_pipe", 42 },
- { "SYS_read", 3 },
- { "SYS_stat", 38 },
- { "SYS_time", 23 },
- { "SYS_unlink", 10 },
- { "SYS_utime", 201 },
- { "SYS_wait", 202 },
- { "SYS_wait4", 7 },
- { "SYS_write", 4 },
+ { "SYS_ARG", 24 },
+ { "SYS_chdir", 12 },
+ { "SYS_chmod", 15 },
+ { "SYS_chown", 16 },
+ { "SYS_close", 6 },
+ { "SYS_creat", 8 },
+ { "SYS_execv", 11 },
+ { "SYS_execve", 59 },
+ { "SYS_exit", 1 },
+ { "SYS_fork", 2 },
+ { "SYS_fstat", 22 },
+ { "SYS_getpid", 20 },
+ { "SYS_gettimeofday", 116 },
+ { "SYS_isatty", 21 },
+ { "SYS_link", 9 },
+ { "SYS_lseek", 19 },
+ { "SYS_mknod", 14 },
+ { "SYS_open", 5 },
+ { "SYS_pipe", 42 },
+ { "SYS_read", 3 },
+ { "SYS_stat", 38 },
+ { "SYS_time", 23 },
+ { "SYS_unlink", 10 },
+ { "SYS_utime", 201 },
+ { "SYS_wait", 202 },
+ { "SYS_wait4", 7 },
+ { "SYS_write", 4 },
/* end v850 sys target macros */
#endif
#endif
diff --git a/sim/common/sim-utils.c b/sim/common/sim-utils.c
index 6f319dc..34ed2c2 100644
--- a/sim/common/sim-utils.c
+++ b/sim/common/sim-utils.c
@@ -52,15 +52,13 @@
Set by sim_resume. */
struct sim_state *current_state;
-/* Allocate zero filled memory with xmalloc - xmalloc aborts of the
+/* Allocate zero filled memory with xcalloc - xcalloc aborts if the
allocation fails. */
void *
zalloc (unsigned long size)
{
- void *memory = (void *) xmalloc (size);
- memset (memory, 0, size);
- return memory;
+ return xcalloc (1, size);
}
void
@@ -409,4 +407,76 @@
}
}
+/* Functions to call from debugger. */
+static void
+dump_hex (SIM_CPU *cpu, USI start, USI num)
+{
+ USI next_line = start;
+ while (num--)
+ {
+ if (start == next_line)
+ {
+ printf ("\n%8x ", start);
+ next_line = start + 16;
+ }
+ else
+ printf (" ");
+ printf ("%8x", GETMEMSI (cpu, 0, start));
+ start += 4;
+ if (start < 4)
+ break;
+ }
+ printf ("\n");
+ fflush (stdout);
+}
+
+static void
+dump_strn_1 (SIM_CPU *cpu, USI start, USI len, int end_char)
+{
+ USI next_line = start;
+ int c;
+
+ while (len--)
+ {
+ if (start == next_line)
+ {
+ printf ("\n%8x ", start);
+ next_line = start + 16;
+ }
+ else
+ printf (" ");
+ c = (char) GETMEMUQI (cpu, 0, start);
+ if (isgraph ((char) c))
+ printf (" %c", c);
+ else switch (c)
+ {
+ default:
+ c = c & 0xff;
+ printf ("%02x", c);
+ }
+ start += 1;
+ if (c == end_char)
+ break;
+ }
+ printf ("\n");
+ fflush (stdout);
+}
+
+static void
+dump_asc (SIM_CPU *cpu, USI start, USI len)
+{
+ dump_strn_1 (cpu, start, len, 32767);
+}
+
+static void
+dump_str (SIM_CPU *cpu, USI start)
+{
+ dump_strn_1 (cpu, start, -1, 0);
+}
+
+static void
+dump_strn (SIM_CPU *cpu, USI start, USI len)
+{
+ dump_strn_1 (cpu, start, len, 0);
+}
diff --git a/sim/common/syscall.c b/sim/common/syscall.c
index 74509c6..b0b98b5 100644
--- a/sim/common/syscall.c
+++ b/sim/common/syscall.c
@@ -109,7 +109,7 @@
simulator_sysroot if the string starts with '/'.
If an error occurs, no buffer is left malloc'd. */
-static int
+int
get_path (cb, sc, addr, bufp)
host_callback *cb;
CB_SYSCALL *sc;
diff --git a/sim/configure b/sim/configure
index ac45dab..236caf4 100755
--- a/sim/configure
+++ b/sim/configure
@@ -272,6 +272,7 @@
PACKAGE_BUGREPORT=
ac_unique_file="Makefile.in"
+ac_subdirs_all="$ac_subdirs_all arc"
ac_subdirs_all="$ac_subdirs_all arm"
ac_subdirs_all="$ac_subdirs_all cris"
ac_subdirs_all="$ac_subdirs_all d10v"
@@ -3416,6 +3417,13 @@
common=yes
igen=no
case "${target}" in
+ arc-*-*)
+
+
+subdirs="$subdirs arc"
+
+ testsuite=yes
+ ;;
arm*-*-* | thumb*-*-* | strongarm*-*-* | xscale-*-*)
diff --git a/sim/configure.ac b/sim/configure.ac
index 48f590f..c417278 100644
--- a/sim/configure.ac
+++ b/sim/configure.ac
@@ -47,6 +47,10 @@
common=yes
igen=no
case "${target}" in
+ arc-*-*)
+ AC_CONFIG_SUBDIRS(arc)
+ testsuite=yes
+ ;;
arm*-*-* | thumb*-*-* | strongarm*-*-* | xscale-*-*)
AC_CONFIG_SUBDIRS(arm)
testsuite=yes
