blob: 0979b6696b03cc4bc2278378c55d42c0b284007f [file] [log] [blame]
/* Disassemble ADI Blackfin Instructions.
Copyright (C) 2005-2016 Free Software Foundation, Inc.
This file is part of libopcodes.
This library is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include "sysdep.h"
#include <stdio.h>
#include "opcode/bfin.h"
#ifndef PRINTF
#define PRINTF printf
#endif
#ifndef EXIT
#define EXIT exit
#endif
typedef long TIword;
#define HOST_LONG_WORD_SIZE (sizeof (long) * 8)
#define XFIELD(w,p,s) (((w) & ((1 << (s)) - 1) << (p)) >> (p))
#define SIGNEXTEND(v, n) ((v << (HOST_LONG_WORD_SIZE - (n))) >> (HOST_LONG_WORD_SIZE - (n)))
#define MASKBITS(val, bits) (val & ((1 << bits) - 1))
#include "dis-asm.h"
typedef unsigned int bu32;
struct private
{
TIword iw0;
bfd_boolean comment, parallel;
};
typedef enum
{
c_0, c_1, c_4, c_2, c_uimm2, c_uimm3, c_imm3, c_pcrel4,
c_imm4, c_uimm4s4, c_uimm4s4d, c_uimm4, c_uimm4s2, c_negimm5s4, c_imm5, c_imm5d, c_uimm5, c_imm6,
c_imm7, c_imm7d, c_imm8, c_uimm8, c_pcrel8, c_uimm8s4, c_pcrel8s4, c_lppcrel10, c_pcrel10,
c_pcrel12, c_imm16s4, c_luimm16, c_imm16, c_imm16d, c_huimm16, c_rimm16, c_imm16s2, c_uimm16s4,
c_uimm16s4d, c_uimm16, c_pcrel24, c_uimm32, c_imm32, c_huimm32, c_huimm32e,
} const_forms_t;
static const struct
{
const char *name;
const int nbits;
const char reloc;
const char issigned;
const char pcrel;
const char scale;
const char offset;
const char negative;
const char positive;
const char decimal;
const char leading;
const char exact;
} constant_formats[] =
{
{ "0", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
{ "1", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
{ "4", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
{ "2", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
{ "uimm2", 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{ "uimm3", 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{ "imm3", 3, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
{ "pcrel4", 4, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
{ "imm4", 4, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
{ "uimm4s4", 4, 0, 0, 0, 2, 0, 0, 1, 0, 0, 0},
{ "uimm4s4d", 4, 0, 0, 0, 2, 0, 0, 1, 1, 0, 0},
{ "uimm4", 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{ "uimm4s2", 4, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0},
{ "negimm5s4", 5, 0, 1, 0, 2, 0, 1, 0, 0, 0, 0},
{ "imm5", 5, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
{ "imm5d", 5, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0},
{ "uimm5", 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{ "imm6", 6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
{ "imm7", 7, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
{ "imm7d", 7, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
{ "imm8", 8, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
{ "uimm8", 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{ "pcrel8", 8, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
{ "uimm8s4", 8, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
{ "pcrel8s4", 8, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0},
{ "lppcrel10", 10, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
{ "pcrel10", 10, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
{ "pcrel12", 12, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
{ "imm16s4", 16, 0, 1, 0, 2, 0, 0, 0, 0, 0, 0},
{ "luimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{ "imm16", 16, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
{ "imm16d", 16, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
{ "huimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{ "rimm16", 16, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0},
{ "imm16s2", 16, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0},
{ "uimm16s4", 16, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
{ "uimm16s4d", 16, 0, 0, 0, 2, 0, 0, 0, 1, 0, 0},
{ "uimm16", 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{ "pcrel24", 24, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
{ "uimm32", 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{ "imm32", 32, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
{ "huimm32", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{ "huimm32e", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1},
};
static const char *
fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info *outf)
{
static char buf[60];
if (constant_formats[cf].reloc)
{
bfd_vma ea = (((constant_formats[cf].pcrel ? SIGNEXTEND (x, constant_formats[cf].nbits)
: x) + constant_formats[cf].offset) << constant_formats[cf].scale);
if (constant_formats[cf].pcrel)
ea += pc;
/* truncate to 32-bits for proper symbol lookup/matching */
ea = (bu32)ea;
if (outf->symbol_at_address_func (ea, outf) || !constant_formats[cf].exact)
{
outf->print_address_func (ea, outf);
return "";
}
else
{
sprintf (buf, "%lx", (unsigned long) x);
return buf;
}
}
/* Negative constants have an implied sign bit. */
if (constant_formats[cf].negative)
{
int nb = constant_formats[cf].nbits + 1;
x = x | (1 << constant_formats[cf].nbits);
x = SIGNEXTEND (x, nb);
}
else
x = constant_formats[cf].issigned ? SIGNEXTEND (x, constant_formats[cf].nbits) : x;
if (constant_formats[cf].offset)
x += constant_formats[cf].offset;
if (constant_formats[cf].scale)
x <<= constant_formats[cf].scale;
if (constant_formats[cf].decimal)
sprintf (buf, "%*li", constant_formats[cf].leading, x);
else
{
if (constant_formats[cf].issigned && x < 0)
sprintf (buf, "-0x%lx", (unsigned long)(- x));
else
sprintf (buf, "0x%lx", (unsigned long) x);
}
return buf;
}
static bu32
fmtconst_val (const_forms_t cf, unsigned int x, unsigned int pc)
{
if (0 && constant_formats[cf].reloc)
{
bu32 ea = (((constant_formats[cf].pcrel
? SIGNEXTEND (x, constant_formats[cf].nbits)
: x) + constant_formats[cf].offset)
<< constant_formats[cf].scale);
if (constant_formats[cf].pcrel)
ea += pc;
return ea;
}
/* Negative constants have an implied sign bit. */
if (constant_formats[cf].negative)
{
int nb = constant_formats[cf].nbits + 1;
x = x | (1 << constant_formats[cf].nbits);
x = SIGNEXTEND (x, nb);
}
else if (constant_formats[cf].issigned)
x = SIGNEXTEND (x, constant_formats[cf].nbits);
x += constant_formats[cf].offset;
x <<= constant_formats[cf].scale;
return x;
}
enum machine_registers
{
REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
REG_R1_0, REG_R3_2, REG_R5_4, REG_R7_6, REG_P0, REG_P1, REG_P2, REG_P3,
REG_P4, REG_P5, REG_SP, REG_FP, REG_A0x, REG_A1x, REG_A0w, REG_A1w,
REG_A0, REG_A1, REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1,
REG_M2, REG_M3, REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1,
REG_L2, REG_L3,
REG_AZ, REG_AN, REG_AC0, REG_AC1, REG_AV0, REG_AV1, REG_AV0S, REG_AV1S,
REG_AQ, REG_V, REG_VS,
REG_sftreset, REG_omode, REG_excause, REG_emucause, REG_idle_req, REG_hwerrcause, REG_CC, REG_LC0,
REG_LC1, REG_ASTAT, REG_RETS, REG_LT0, REG_LB0, REG_LT1, REG_LB1,
REG_CYCLES, REG_CYCLES2, REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN,
REG_RETE, REG_EMUDAT, REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6,
REG_BR7, REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
REG_AC0_COPY, REG_V_COPY, REG_RND_MOD,
REG_LASTREG,
};
enum reg_class
{
rc_dregs_lo, rc_dregs_hi, rc_dregs, rc_dregs_pair, rc_pregs, rc_spfp, rc_dregs_hilo, rc_accum_ext,
rc_accum_word, rc_accum, rc_iregs, rc_mregs, rc_bregs, rc_lregs, rc_dpregs, rc_gregs,
rc_regs, rc_statbits, rc_ignore_bits, rc_ccstat, rc_counters, rc_dregs2_sysregs1, rc_open, rc_sysregs2,
rc_sysregs3, rc_allregs,
LIM_REG_CLASSES
};
static const char * const reg_names[] =
{
"R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L",
"R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H",
"R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
"R1:0", "R3:2", "R5:4", "R7:6", "P0", "P1", "P2", "P3",
"P4", "P5", "SP", "FP", "A0.X", "A1.X", "A0.W", "A1.W",
"A0", "A1", "I0", "I1", "I2", "I3", "M0", "M1",
"M2", "M3", "B0", "B1", "B2", "B3", "L0", "L1",
"L2", "L3",
"AZ", "AN", "AC0", "AC1", "AV0", "AV1", "AV0S", "AV1S",
"AQ", "V", "VS",
"sftreset", "omode", "excause", "emucause", "idle_req", "hwerrcause", "CC", "LC0",
"LC1", "ASTAT", "RETS", "LT0", "LB0", "LT1", "LB1",
"CYCLES", "CYCLES2", "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN",
"RETE", "EMUDAT",
"R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B",
"P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L",
"P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H",
"I0.L", "I1.L", "I2.L", "I3.L", "M0.L", "M1.L", "M2.L", "M3.L",
"B0.L", "B1.L", "B2.L", "B3.L", "L0.L", "L1.L", "L2.L", "L3.L",
"I0.H", "I1.H", "I2.H", "I3.H", "M0.H", "M1.H", "M2.H", "M3.H",
"B0.H", "B1.H", "B2.H", "B3.H", "L0.H", "L1.H", "L2.H", "L3.H",
"AC0_COPY", "V_COPY", "RND_MOD",
"LASTREG",
0
};
#define REGNAME(x) ((x) < REG_LASTREG ? (reg_names[x]) : "...... Illegal register .......")
/* RL(0..7). */
static const enum machine_registers decode_dregs_lo[] =
{
REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
};
#define dregs_lo(x) REGNAME (decode_dregs_lo[(x) & 7])
/* RH(0..7). */
static const enum machine_registers decode_dregs_hi[] =
{
REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
};
#define dregs_hi(x) REGNAME (decode_dregs_hi[(x) & 7])
/* R(0..7). */
static const enum machine_registers decode_dregs[] =
{
REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
};
#define dregs(x) REGNAME (decode_dregs[(x) & 7])
/* R BYTE(0..7). */
static const enum machine_registers decode_dregs_byte[] =
{
REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, REG_BR7,
};
#define dregs_byte(x) REGNAME (decode_dregs_byte[(x) & 7])
/* P(0..5) SP FP. */
static const enum machine_registers decode_pregs[] =
{
REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
};
#define pregs(x) REGNAME (decode_pregs[(x) & 7])
#define spfp(x) REGNAME (decode_spfp[(x) & 1])
#define dregs_hilo(x, i) REGNAME (decode_dregs_hilo[((i) << 3) | (x)])
#define accum_ext(x) REGNAME (decode_accum_ext[(x) & 1])
#define accum_word(x) REGNAME (decode_accum_word[(x) & 1])
#define accum(x) REGNAME (decode_accum[(x) & 1])
/* I(0..3). */
static const enum machine_registers decode_iregs[] =
{
REG_I0, REG_I1, REG_I2, REG_I3,
};
#define iregs(x) REGNAME (decode_iregs[(x) & 3])
/* M(0..3). */
static const enum machine_registers decode_mregs[] =
{
REG_M0, REG_M1, REG_M2, REG_M3,
};
#define mregs(x) REGNAME (decode_mregs[(x) & 3])
#define bregs(x) REGNAME (decode_bregs[(x) & 3])
#define lregs(x) REGNAME (decode_lregs[(x) & 3])
/* dregs pregs. */
static const enum machine_registers decode_dpregs[] =
{
REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
};
#define dpregs(x) REGNAME (decode_dpregs[(x) & 15])
/* [dregs pregs]. */
static const enum machine_registers decode_gregs[] =
{
REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
};
#define gregs(x, i) REGNAME (decode_gregs[((i) << 3) | (x)])
/* [dregs pregs (iregs mregs) (bregs lregs)]. */
static const enum machine_registers decode_regs[] =
{
REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
};
#define regs(x, i) REGNAME (decode_regs[((i) << 3) | (x)])
/* [dregs pregs (iregs mregs) (bregs lregs) Low Half]. */
static const enum machine_registers decode_regs_lo[] =
{
REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
};
#define regs_lo(x, i) REGNAME (decode_regs_lo[((i) << 3) | (x)])
/* [dregs pregs (iregs mregs) (bregs lregs) High Half]. */
static const enum machine_registers decode_regs_hi[] =
{
REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
};
#define regs_hi(x, i) REGNAME (decode_regs_hi[((i) << 3) | (x)])
static const enum machine_registers decode_statbits[] =
{
REG_AZ, REG_AN, REG_AC0_COPY, REG_V_COPY,
REG_LASTREG, REG_LASTREG, REG_AQ, REG_LASTREG,
REG_RND_MOD, REG_LASTREG, REG_LASTREG, REG_LASTREG,
REG_AC0, REG_AC1, REG_LASTREG, REG_LASTREG,
REG_AV0, REG_AV0S, REG_AV1, REG_AV1S,
REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
REG_V, REG_VS, REG_LASTREG, REG_LASTREG,
REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
};
#define statbits(x) REGNAME (decode_statbits[(x) & 31])
/* LC0 LC1. */
static const enum machine_registers decode_counters[] =
{
REG_LC0, REG_LC1,
};
#define counters(x) REGNAME (decode_counters[(x) & 1])
#define dregs2_sysregs1(x) REGNAME (decode_dregs2_sysregs1[(x) & 7])
/* [dregs pregs (iregs mregs) (bregs lregs)
dregs2_sysregs1 open sysregs2 sysregs3]. */
static const enum machine_registers decode_allregs[] =
{
REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_LASTREG, REG_LASTREG, REG_ASTAT, REG_RETS,
REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2,
REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT,
REG_LASTREG,
};
#define IS_DREG(g,r) ((g) == 0 && (r) < 8)
#define IS_PREG(g,r) ((g) == 1 && (r) < 8)
#define IS_AREG(g,r) ((g) == 4 && (r) >= 0 && (r) < 4)
#define IS_GENREG(g,r) ((((g) == 0 || (g) == 1) && (r) < 8) || IS_AREG (g, r))
#define IS_DAGREG(g,r) (((g) == 2 || (g) == 3) && (r) < 8)
#define IS_SYSREG(g,r) \
(((g) == 4 && ((r) == 6 || (r) == 7)) || (g) == 6 || (g) == 7)
#define IS_RESERVEDREG(g,r) \
(((r) > 7) || ((g) == 4 && ((r) == 4 || (r) == 5)) || (g) == 5)
#define allreg(r,g) (!IS_RESERVEDREG (g, r))
#define mostreg(r,g) (!(IS_DREG (g, r) || IS_PREG (g, r) || IS_RESERVEDREG (g, r)))
#define allregs(x, i) REGNAME (decode_allregs[((i) << 3) | (x)])
#define uimm16s4(x) fmtconst (c_uimm16s4, x, 0, outf)
#define uimm16s4d(x) fmtconst (c_uimm16s4d, x, 0, outf)
#define pcrel4(x) fmtconst (c_pcrel4, x, pc, outf)
#define pcrel8(x) fmtconst (c_pcrel8, x, pc, outf)
#define pcrel8s4(x) fmtconst (c_pcrel8s4, x, pc, outf)
#define pcrel10(x) fmtconst (c_pcrel10, x, pc, outf)
#define pcrel12(x) fmtconst (c_pcrel12, x, pc, outf)
#define negimm5s4(x) fmtconst (c_negimm5s4, x, 0, outf)
#define rimm16(x) fmtconst (c_rimm16, x, 0, outf)
#define huimm16(x) fmtconst (c_huimm16, x, 0, outf)
#define imm16(x) fmtconst (c_imm16, x, 0, outf)
#define imm16d(x) fmtconst (c_imm16d, x, 0, outf)
#define uimm2(x) fmtconst (c_uimm2, x, 0, outf)
#define uimm3(x) fmtconst (c_uimm3, x, 0, outf)
#define luimm16(x) fmtconst (c_luimm16, x, 0, outf)
#define uimm4(x) fmtconst (c_uimm4, x, 0, outf)
#define uimm5(x) fmtconst (c_uimm5, x, 0, outf)
#define imm16s2(x) fmtconst (c_imm16s2, x, 0, outf)
#define uimm8(x) fmtconst (c_uimm8, x, 0, outf)
#define imm16s4(x) fmtconst (c_imm16s4, x, 0, outf)
#define uimm4s2(x) fmtconst (c_uimm4s2, x, 0, outf)
#define uimm4s4(x) fmtconst (c_uimm4s4, x, 0, outf)
#define uimm4s4d(x) fmtconst (c_uimm4s4d, x, 0, outf)
#define lppcrel10(x) fmtconst (c_lppcrel10, x, pc, outf)
#define imm3(x) fmtconst (c_imm3, x, 0, outf)
#define imm4(x) fmtconst (c_imm4, x, 0, outf)
#define uimm8s4(x) fmtconst (c_uimm8s4, x, 0, outf)
#define imm5(x) fmtconst (c_imm5, x, 0, outf)
#define imm5d(x) fmtconst (c_imm5d, x, 0, outf)
#define imm6(x) fmtconst (c_imm6, x, 0, outf)
#define imm7(x) fmtconst (c_imm7, x, 0, outf)
#define imm7d(x) fmtconst (c_imm7d, x, 0, outf)
#define imm8(x) fmtconst (c_imm8, x, 0, outf)
#define pcrel24(x) fmtconst (c_pcrel24, x, pc, outf)
#define uimm16(x) fmtconst (c_uimm16, x, 0, outf)
#define uimm32(x) fmtconst (c_uimm32, x, 0, outf)
#define imm32(x) fmtconst (c_imm32, x, 0, outf)
#define huimm32(x) fmtconst (c_huimm32, x, 0, outf)
#define huimm32e(x) fmtconst (c_huimm32e, x, 0, outf)
#define imm7_val(x) fmtconst_val (c_imm7, x, 0)
#define imm16_val(x) fmtconst_val (c_uimm16, x, 0)
#define luimm16_val(x) fmtconst_val (c_luimm16, x, 0)
/* (arch.pm)arch_disassembler_functions. */
#ifndef OUTS
#define OUTS(p, txt) (p)->fprintf_func ((p)->stream, "%s", txt)
#endif
#define OUT(p, txt, ...) (p)->fprintf_func ((p)->stream, txt, ## __VA_ARGS__)
static void
amod0 (int s0, int x0, disassemble_info *outf)
{
if (s0 == 1 && x0 == 0)
OUTS (outf, " (S)");
else if (s0 == 0 && x0 == 1)
OUTS (outf, " (CO)");
else if (s0 == 1 && x0 == 1)
OUTS (outf, " (SCO)");
}
static void
amod1 (int s0, int x0, disassemble_info *outf)
{
if (s0 == 0 && x0 == 0)
OUTS (outf, " (NS)");
else if (s0 == 1 && x0 == 0)
OUTS (outf, " (S)");
}
static void
amod0amod2 (int s0, int x0, int aop0, disassemble_info *outf)
{
if (s0 == 1 && x0 == 0 && aop0 == 0)
OUTS (outf, " (S)");
else if (s0 == 0 && x0 == 1 && aop0 == 0)
OUTS (outf, " (CO)");
else if (s0 == 1 && x0 == 1 && aop0 == 0)
OUTS (outf, " (SCO)");
else if (s0 == 0 && x0 == 0 && aop0 == 2)
OUTS (outf, " (ASR)");
else if (s0 == 1 && x0 == 0 && aop0 == 2)
OUTS (outf, " (S, ASR)");
else if (s0 == 0 && x0 == 1 && aop0 == 2)
OUTS (outf, " (CO, ASR)");
else if (s0 == 1 && x0 == 1 && aop0 == 2)
OUTS (outf, " (SCO, ASR)");
else if (s0 == 0 && x0 == 0 && aop0 == 3)
OUTS (outf, " (ASL)");
else if (s0 == 1 && x0 == 0 && aop0 == 3)
OUTS (outf, " (S, ASL)");
else if (s0 == 0 && x0 == 1 && aop0 == 3)
OUTS (outf, " (CO, ASL)");
else if (s0 == 1 && x0 == 1 && aop0 == 3)
OUTS (outf, " (SCO, ASL)");
}
static void
searchmod (int r0, disassemble_info *outf)
{
if (r0 == 0)
OUTS (outf, "GT");
else if (r0 == 1)
OUTS (outf, "GE");
else if (r0 == 2)
OUTS (outf, "LT");
else if (r0 == 3)
OUTS (outf, "LE");
}
static void
aligndir (int r0, disassemble_info *outf)
{
if (r0 == 1)
OUTS (outf, " (R)");
}
static int
decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info *outf)
{
const char *s0, *s1;
if (h0)
s0 = dregs_hi (src0);
else
s0 = dregs_lo (src0);
if (h1)
s1 = dregs_hi (src1);
else
s1 = dregs_lo (src1);
OUTS (outf, s0);
OUTS (outf, " * ");
OUTS (outf, s1);
return 0;
}
static int
decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info *outf)
{
const char *a;
const char *sop = "<unknown op>";
if (which)
a = "A1";
else
a = "A0";
if (op == 3)
{
OUTS (outf, a);
return 0;
}
switch (op)
{
case 0: sop = " = "; break;
case 1: sop = " += "; break;
case 2: sop = " -= "; break;
default: break;
}
OUTS (outf, a);
OUTS (outf, sop);
decode_multfunc (h0, h1, src0, src1, outf);
return 0;
}
static void
decode_optmode (int mod, int MM, disassemble_info *outf)
{
if (mod == 0 && MM == 0)
return;
OUTS (outf, " (");
if (MM && !mod)
{
OUTS (outf, "M)");
return;
}
if (MM)
OUTS (outf, "M, ");
if (mod == M_S2RND)
OUTS (outf, "S2RND");
else if (mod == M_T)
OUTS (outf, "T");
else if (mod == M_W32)
OUTS (outf, "W32");
else if (mod == M_FU)
OUTS (outf, "FU");
else if (mod == M_TFU)
OUTS (outf, "TFU");
else if (mod == M_IS)
OUTS (outf, "IS");
else if (mod == M_ISS2)
OUTS (outf, "ISS2");
else if (mod == M_IH)
OUTS (outf, "IH");
else if (mod == M_IU)
OUTS (outf, "IU");
else
abort ();
OUTS (outf, ")");
}
static struct saved_state
{
bu32 dpregs[16], iregs[4], mregs[4], bregs[4], lregs[4];
bu32 ax[2], aw[2];
bu32 lt[2], lc[2], lb[2];
bu32 rets;
} saved_state;
#define DREG(x) (saved_state.dpregs[x])
#define GREG(x, i) DPREG ((x) | ((i) << 3))
#define DPREG(x) (saved_state.dpregs[x])
#define DREG(x) (saved_state.dpregs[x])
#define PREG(x) (saved_state.dpregs[(x) + 8])
#define SPREG PREG (6)
#define FPREG PREG (7)
#define IREG(x) (saved_state.iregs[x])
#define MREG(x) (saved_state.mregs[x])
#define BREG(x) (saved_state.bregs[x])
#define LREG(x) (saved_state.lregs[x])
#define AXREG(x) (saved_state.ax[x])
#define AWREG(x) (saved_state.aw[x])
#define LCREG(x) (saved_state.lc[x])
#define LTREG(x) (saved_state.lt[x])
#define LBREG(x) (saved_state.lb[x])
#define RETSREG (saved_state.rets)
static bu32 *
get_allreg (int grp, int reg)
{
int fullreg = (grp << 3) | reg;
/* REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
REG_A0x, REG_A0w, REG_A1x, REG_A1w, , , REG_ASTAT, REG_RETS,
, , , , , , , ,
REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES,
REG_CYCLES2,
REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE,
REG_LASTREG */
switch (fullreg >> 2)
{
case 0: case 1: return &DREG (reg);
case 2: case 3: return &PREG (reg);
case 4: return &IREG (reg & 3);
case 5: return &MREG (reg & 3);
case 6: return &BREG (reg & 3);
case 7: return &LREG (reg & 3);
default:
switch (fullreg)
{
case 32: return &AXREG (0);
case 33: return &AWREG (0);
case 34: return &AXREG (1);
case 35: return &AWREG (1);
case 39: return &RETSREG;
case 48: return &LCREG (0);
case 49: return &LTREG (0);
case 50: return &LBREG (0);
case 51: return &LCREG (1);
case 52: return &LTREG (1);
case 53: return &LBREG (1);
}
}
abort ();
}
static int
decode_ProgCtrl_0 (TIword iw0, disassemble_info *outf)
{
struct private *priv = outf->private_data;
/* ProgCtrl
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
int poprnd = ((iw0 >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask);
int prgfunc = ((iw0 >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask);
if (prgfunc == 0 && poprnd == 0)
OUTS (outf, "NOP");
else if (priv->parallel)
return 0;
else if (prgfunc == 1 && poprnd == 0)
OUTS (outf, "RTS");
else if (prgfunc == 1 && poprnd == 1)
OUTS (outf, "RTI");
else if (prgfunc == 1 && poprnd == 2)
OUTS (outf, "RTX");
else if (prgfunc == 1 && poprnd == 3)
OUTS (outf, "RTN");
else if (prgfunc == 1 && poprnd == 4)
OUTS (outf, "RTE");
else if (prgfunc == 2 && poprnd == 0)
OUTS (outf, "IDLE");
else if (prgfunc == 2 && poprnd == 3)
OUTS (outf, "CSYNC");
else if (prgfunc == 2 && poprnd == 4)
OUTS (outf, "SSYNC");
else if (prgfunc == 2 && poprnd == 5)
OUTS (outf, "EMUEXCPT");
else if (prgfunc == 3 && IS_DREG (0, poprnd))
{
OUTS (outf, "CLI ");
OUTS (outf, dregs (poprnd));
}
else if (prgfunc == 4 && IS_DREG (0, poprnd))
{
OUTS (outf, "STI ");
OUTS (outf, dregs (poprnd));
}
else if (prgfunc == 5 && IS_PREG (1, poprnd))
{
OUTS (outf, "JUMP (");
OUTS (outf, pregs (poprnd));
OUTS (outf, ")");
}
else if (prgfunc == 6 && IS_PREG (1, poprnd))
{
OUTS (outf, "CALL (");
OUTS (outf, pregs (poprnd));
OUTS (outf, ")");
}
else if (prgfunc == 7 && IS_PREG (1, poprnd))
{
OUTS (outf, "CALL (PC + ");
OUTS (outf, pregs (poprnd));
OUTS (outf, ")");
}
else if (prgfunc == 8 && IS_PREG (1, poprnd))
{
OUTS (outf, "JUMP (PC + ");
OUTS (outf, pregs (poprnd));
OUTS (outf, ")");
}
else if (prgfunc == 9)
{
OUTS (outf, "RAISE ");
OUTS (outf, uimm4 (poprnd));
}
else if (prgfunc == 10)
{
OUTS (outf, "EXCPT ");
OUTS (outf, uimm4 (poprnd));
}
else if (prgfunc == 11 && IS_PREG (1, poprnd) && poprnd <= 5)
{
OUTS (outf, "TESTSET (");
OUTS (outf, pregs (poprnd));
OUTS (outf, ")");
}
else
return 0;
return 2;
}
static int
decode_CaCTRL_0 (TIword iw0, disassemble_info *outf)
{
struct private *priv = outf->private_data;
/* CaCTRL
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
int a = ((iw0 >> CaCTRL_a_bits) & CaCTRL_a_mask);
int op = ((iw0 >> CaCTRL_op_bits) & CaCTRL_op_mask);
int reg = ((iw0 >> CaCTRL_reg_bits) & CaCTRL_reg_mask);
if (priv->parallel)
return 0;
if (a == 0 && op == 0)
{
OUTS (outf, "PREFETCH[");
OUTS (outf, pregs (reg));
OUTS (outf, "]");
}
else if (a == 0 && op == 1)
{
OUTS (outf, "FLUSHINV[");
OUTS (outf, pregs (reg));
OUTS (outf, "]");
}
else if (a == 0 && op == 2)
{
OUTS (outf, "FLUSH[");
OUTS (outf, pregs (reg));
OUTS (outf, "]");
}
else if (a == 0 && op == 3)
{
OUTS (outf, "IFLUSH[");
OUTS (outf, pregs (reg));
OUTS (outf, "]");
}
else if (a == 1 && op == 0)
{
OUTS (outf, "PREFETCH[");
OUTS (outf, pregs (reg));
OUTS (outf, "++]");
}
else if (a == 1 && op == 1)
{
OUTS (outf, "FLUSHINV[");
OUTS (outf, pregs (reg));
OUTS (outf, "++]");
}
else if (a == 1 && op == 2)
{
OUTS (outf, "FLUSH[");
OUTS (outf, pregs (reg));
OUTS (outf, "++]");
}
else if (a == 1 && op == 3)
{
OUTS (outf, "IFLUSH[");
OUTS (outf, pregs (reg));
OUTS (outf, "++]");
}
else
return 0;
return 2;
}
static int
decode_PushPopReg_0 (TIword iw0, disassemble_info *outf)
{
struct private *priv = outf->private_data;
/* PushPopReg
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
int W = ((iw0 >> PushPopReg_W_bits) & PushPopReg_W_mask);
int grp = ((iw0 >> PushPopReg_grp_bits) & PushPopReg_grp_mask);
int reg = ((iw0 >> PushPopReg_reg_bits) & PushPopReg_reg_mask);
if (priv->parallel)
return 0;
if (W == 0 && mostreg (reg, grp))
{
OUTS (outf, allregs (reg, grp));
OUTS (outf, " = [SP++]");
}
else if (W == 1 && allreg (reg, grp) && !(grp == 1 && reg == 6))
{
OUTS (outf, "[--SP] = ");
OUTS (outf, allregs (reg, grp));
}
else
return 0;
return 2;
}
static int
decode_PushPopMultiple_0 (TIword iw0, disassemble_info *outf)
{
struct private *priv = outf->private_data;
/* PushPopMultiple
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
int p = ((iw0 >> PushPopMultiple_p_bits) & PushPopMultiple_p_mask);
int d = ((iw0 >> PushPopMultiple_d_bits) & PushPopMultiple_d_mask);
int W = ((iw0 >> PushPopMultiple_W_bits) & PushPopMultiple_W_mask);
int dr = ((iw0 >> PushPopMultiple_dr_bits) & PushPopMultiple_dr_mask);
int pr = ((iw0 >> PushPopMultiple_pr_bits) & PushPopMultiple_pr_mask);
if (priv->parallel)
return 0;
if (pr > 5)
return 0;
if (W == 1 && d == 1 && p == 1)
{
OUTS (outf, "[--SP] = (R7:");
OUTS (outf, imm5d (dr));
OUTS (outf, ", P5:");
OUTS (outf, imm5d (pr));
OUTS (outf, ")");
}
else if (W == 1 && d == 1 && p == 0 && pr == 0)
{
OUTS (outf, "[--SP] = (R7:");
OUTS (outf, imm5d (dr));
OUTS (outf, ")");
}
else if (W == 1 && d == 0 && p == 1 && dr == 0)
{
OUTS (outf, "[--SP] = (P5:");
OUTS (outf, imm5d (pr));
OUTS (outf, ")");
}
else if (W == 0 && d == 1 && p == 1)
{
OUTS (outf, "(R7:");
OUTS (outf, imm5d (dr));
OUTS (outf, ", P5:");
OUTS (outf, imm5d (pr));
OUTS (outf, ") = [SP++]");
}
else if (W == 0 && d == 1 && p == 0 && pr == 0)
{
OUTS (outf, "(R7:");
OUTS (outf, imm5d (dr));
OUTS (outf, ") = [SP++]");
}
else if (W == 0 && d == 0 && p == 1 && dr == 0)
{
OUTS (outf, "(P5:");
OUTS (outf, imm5d (pr));
OUTS (outf, ") = [SP++]");
}
else
return 0;
return 2;
}
static int
decode_ccMV_0 (TIword iw0, disassemble_info *outf)
{
struct private *priv = outf->private_data;
/* ccMV
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
int s = ((iw0 >> CCmv_s_bits) & CCmv_s_mask);
int d = ((iw0 >> CCmv_d_bits) & CCmv_d_mask);
int T = ((iw0 >> CCmv_T_bits) & CCmv_T_mask);
int src = ((iw0 >> CCmv_src_bits) & CCmv_src_mask);
int dst = ((iw0 >> CCmv_dst_bits) & CCmv_dst_mask);
if (priv->parallel)
return 0;
if (T == 1)
{
OUTS (outf, "IF CC ");
OUTS (outf, gregs (dst, d));
OUTS (outf, " = ");
OUTS (outf, gregs (src, s));
}
else if (T == 0)
{
OUTS (outf, "IF !CC ");
OUTS (outf, gregs (dst, d));
OUTS (outf, " = ");
OUTS (outf, gregs (src, s));
}
else
return 0;
return 2;
}
static int
decode_CCflag_0 (TIword iw0, disassemble_info *outf)
{
struct private *priv = outf->private_data;
/* CCflag
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
int x = ((iw0 >> CCflag_x_bits) & CCflag_x_mask);
int y = ((iw0 >> CCflag_y_bits) & CCflag_y_mask);
int I = ((iw0 >> CCflag_I_bits) & CCflag_I_mask);
int G = ((iw0 >> CCflag_G_bits) & CCflag_G_mask);
int opc = ((iw0 >> CCflag_opc_bits) & CCflag_opc_mask);
if (priv->parallel)
return 0;
if (opc == 0 && I == 0 && G == 0)
{
OUTS (outf, "CC = ");
OUTS (outf, dregs (x));
OUTS (outf, " == ");
OUTS (outf, dregs (y));
}
else if (opc == 1 && I == 0 && G == 0)
{
OUTS (outf, "CC = ");
OUTS (outf, dregs (x));
OUTS (outf, " < ");
OUTS (outf, dregs (y));
}
else if (opc == 2 && I == 0 && G == 0)
{
OUTS (outf, "CC = ");
OUTS (outf, dregs (x));
OUTS (outf, " <= ");
OUTS (outf, dregs (y));
}
else if (opc == 3 && I == 0 && G == 0)
{
OUTS (outf, "CC = ");
OUTS (outf, dregs (x));
OUTS (outf, " < ");
OUTS (outf, dregs (y));
OUTS (outf, " (IU)");
}
else if (opc == 4 && I == 0 && G == 0)
{
OUTS (outf, "CC = ");
OUTS (outf, dregs (x));
OUTS (outf, " <= ");
OUTS (outf, dregs (y));
OUTS (outf, " (IU)");
}
else if (opc == 0 && I == 1 && G == 0)
{
OUTS (outf, "CC = ");
OUTS (outf, dregs (x));
OUTS (outf, " == ");
OUTS (outf, imm3 (y));
}
else if (opc == 1 && I == 1 && G == 0)
{
OUTS (outf, "CC = ");
OUTS (outf, dregs (x));
OUTS (outf, " < ");
OUTS (outf, imm3 (y));
}
else if (opc == 2 && I == 1 && G == 0)
{
OUTS (outf, "CC = ");
OUTS (outf, dregs (x));
OUTS (outf, " <= ");
OUTS (outf, imm3 (y));
}
else if (opc == 3 && I == 1 && G == 0)
{
OUTS (outf, "CC = ");
OUTS (outf, dregs (x));
OUTS (outf, " < ");
OUTS (outf, uimm3 (y));
OUTS (outf, " (IU)");
}
else if (opc == 4 && I == 1 && G == 0)
{
OUTS (outf, "CC = ");
OUTS (outf, dregs (x));
OUTS (outf, " <= ");
OUTS (outf, uimm3 (y));
OUTS (outf, " (IU)");
}
else if (opc == 0 && I == 0 && G == 1)
{
OUTS (outf, "CC = ");
OUTS (outf, pregs (x));
OUTS (outf, " == ");
OUTS (outf, pregs (y));
}
else if (opc == 1 && I == 0 && G == 1)
{
OUTS (outf, "CC = ");
OUTS (outf, pregs (x));
OUTS (outf, " < ");
OUTS (outf, pregs (y));
}
else if (opc == 2 && I == 0 && G == 1)
{
OUTS (outf, "CC = ");
OUTS (outf, pregs (x));
OUTS (outf, " <= ");
OUTS (outf, pregs (y));
}
else if (opc == 3 && I == 0 && G == 1)
{
OUTS (outf, "CC = ");
OUTS (outf, pregs (x));
OUTS (outf, " < ");
OUTS (outf, pregs (y));
OUTS (outf, " (IU)");
}
else if (opc == 4 && I == 0 && G == 1)
{
OUTS (outf, "CC = ");
OUTS (outf, pregs (x));
OUTS (outf, " <= ");
OUTS (outf, pregs (y));
OUTS (outf, " (IU)");
}
else if (opc == 0 && I == 1 && G == 1)
{
OUTS (outf, "CC = ");
OUTS (outf, pregs (x));
OUTS (outf, " == ");
OUTS (outf, imm3 (y));
}
else if (opc == 1 && I == 1 && G == 1)
{
OUTS (outf, "CC = ");
OUTS (outf, pregs (x));
OUTS (outf, " < ");
OUTS (outf, imm3 (y));
}
else if (opc == 2 && I == 1 && G == 1)
{
OUTS (outf, "CC = ");
OUTS (outf, pregs (x));
OUTS (outf, " <= ");
OUTS (outf, imm3 (y));
}
else if (opc == 3 && I == 1 && G == 1)
{
OUTS (outf, "CC = ");
OUTS (outf, pregs (x));
OUTS (outf, " < ");
OUTS (outf, uimm3 (y));
OUTS (outf, " (IU)");
}
else if (opc == 4 && I == 1 && G == 1)
{
OUTS (outf, "CC = ");
OUTS (outf, pregs (x));
OUTS (outf, " <= ");
OUTS (outf, uimm3 (y));
OUTS (outf, " (IU)");
}
else if (opc == 5 && I == 0 && G == 0 && x == 0 && y == 0)
OUTS (outf, "CC = A0 == A1");
else if (opc == 6 && I == 0 && G == 0 && x == 0 && y == 0)
OUTS (outf, "CC = A0 < A1");
else if (opc == 7 && I == 0 && G == 0 && x == 0 && y == 0)
OUTS (outf, "CC = A0 <= A1");
else
return 0;
return 2;
}
static int
decode_CC2dreg_0 (TIword iw0, disassemble_info *outf)
{
struct private *priv = outf->private_data;
/* CC2dreg
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
int op = ((iw0 >> CC2dreg_op_bits) & CC2dreg_op_mask);
int reg = ((iw0 >> CC2dreg_reg_bits) & CC2dreg_reg_mask);
if (priv->parallel)
return 0;
if (op == 0)
{
OUTS (outf, dregs (reg));
OUTS (outf, " = CC");
}
else if (op == 1)
{
OUTS (outf, "CC = ");
OUTS (outf, dregs (reg));
}
else if (op == 3 && reg == 0)
OUTS (outf, "CC = !CC");
else
return 0;
return 2;
}
static int
decode_CC2stat_0 (TIword iw0, disassemble_info *outf)
{
struct private *priv = outf->private_data;
/* CC2stat
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
int D = ((iw0 >> CC2stat_D_bits) & CC2stat_D_mask);
int op = ((iw0 >> CC2stat_op_bits) & CC2stat_op_mask);
int cbit = ((iw0 >> CC2stat_cbit_bits) & CC2stat_cbit_mask);
const char *bitname = statbits (cbit);
const char * const op_names[] = { "", "|", "&", "^" } ;
if (priv->parallel)
return 0;
if (decode_statbits[cbit] == REG_LASTREG)
{
/* All ASTAT bits except CC may be operated on in hardware, but may
not have a dedicated insn, so still decode "valid" insns. */
static char bitnames[64];
if (cbit != 5)
sprintf (bitnames, "ASTAT[%i /* unused bit */]", cbit);
else
return 0;
bitname = bitnames;
}
if (D == 0)
OUT (outf, "CC %s= %s", op_names[op], bitname);
else
OUT (outf, "%s %s= CC", bitname, op_names[op]);
return 2;
}
static int
decode_BRCC_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
{
struct private *priv = outf->private_data;
/* BRCC
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 0 | 0 | 0 | 1 |.T.|.B.|.offset................................|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
int B = ((iw0 >> BRCC_B_bits) & BRCC_B_mask);
int T = ((iw0 >> BRCC_T_bits) & BRCC_T_mask);
int offset = ((iw0 >> BRCC_offset_bits) & BRCC_offset_mask);
if (priv->parallel)
return 0;
if (T == 1 && B == 1)
{
OUTS (outf, "IF CC JUMP 0x");
OUTS (outf, pcrel10 (offset));
OUTS (outf, " (BP)");
}
else if (T == 0 && B == 1)
{
OUTS (outf, "IF !CC JUMP 0x");
OUTS (outf, pcrel10 (offset));
OUTS (outf, " (BP)");
}
else if (T == 1)
{
OUTS (outf, "IF CC JUMP 0x");
OUTS (outf, pcrel10 (offset));
}
else if (T == 0)
{
OUTS (outf, "IF !CC JUMP 0x");
OUTS (outf, pcrel10 (offset));
}
else
return 0;
return 2;
}
static int
decode_UJUMP_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
{
struct private *priv = outf->private_data;
/* UJUMP
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 0 | 0 | 1 | 0 |.offset........................................|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
int offset = ((iw0 >> UJump_offset_bits) & UJump_offset_mask);
if (priv->parallel)
return 0;
OUTS (outf, "JUMP.S 0x");
OUTS (outf, pcrel12 (offset));
return 2;
}
static int
decode_REGMV_0 (TIword iw0, disassemble_info *outf)
{
/* REGMV
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
int gs = ((iw0 >> RegMv_gs_bits) & RegMv_gs_mask);
int gd = ((iw0 >> RegMv_gd_bits) & RegMv_gd_mask);
int src = ((iw0 >> RegMv_src_bits) & RegMv_src_mask);
int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask);
/* Reserved slots cannot be a src/dst. */
if (IS_RESERVEDREG (gs, src) || IS_RESERVEDREG (gd, dst))
goto invalid_move;
/* Standard register moves */
if ((gs < 2) || /* Dregs/Pregs as source */
(gd < 2) || /* Dregs/Pregs as dest */
(gs == 4 && src < 4) || /* Accumulators as source */
(gd == 4 && dst < 4 && (gs < 4)) || /* Accumulators as dest */
(gs == 7 && src == 7 && !(gd == 4 && dst < 4)) || /* EMUDAT as src */
(gd == 7 && dst == 7)) /* EMUDAT as dest */
goto valid_move;
/* dareg = dareg (IMBL) */
if (gs < 4 && gd < 4)
goto valid_move;
/* USP can be src to sysregs, but not dagregs. */
if ((gs == 7 && src == 0) && (gd >= 4))
goto valid_move;
/* USP can move between genregs (only check Accumulators). */
if (((gs == 7 && src == 0) && (gd == 4 && dst < 4)) ||
((gd == 7 && dst == 0) && (gs == 4 && src < 4)))
goto valid_move;
/* Still here ? Invalid reg pair. */
invalid_move:
return 0;
valid_move:
OUTS (outf, allregs (dst, gd));
OUTS (outf, " = ");
OUTS (outf, allregs (src, gs));
return 2;
}
static int
decode_ALU2op_0 (TIword iw0, disassemble_info *outf)
{
/* ALU2op
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
int src = ((iw0 >> ALU2op_src_bits) & ALU2op_src_mask);
int opc = ((iw0 >> ALU2op_opc_bits) & ALU2op_opc_mask);
int dst = ((iw0 >> ALU2op_dst_bits) & ALU2op_dst_mask);
if (opc == 0)
{
OUTS (outf, dregs (dst));
OUTS (outf, " >>>= ");
OUTS (outf, dregs (src));
}
else if (opc == 1)
{
OUTS (outf, dregs (dst));
OUTS (outf, " >>= ");
OUTS (outf, dregs (src));
}
else if (opc == 2)
{
OUTS (outf, dregs (dst));
OUTS (outf, " <<= ");
OUTS (outf, dregs (src));
}
else if (opc == 3)
{
OUTS (outf, dregs (dst));
OUTS (outf, " *= ");
OUTS (outf, dregs (src));
}
else if (opc == 4)
{
OUTS (outf, dregs (dst));
OUTS (outf, " = (");
OUTS (outf, dregs (dst));
OUTS (outf, " + ");
OUTS (outf, dregs (src));
OUTS (outf, ") << 0x1");
}
else if (opc == 5)
{
OUTS (outf, dregs (dst));
OUTS (outf, " = (");
OUTS (outf, dregs (dst));
OUTS (outf, " + ");
OUTS (outf, dregs (src));
OUTS (outf, ") << 0x2");
}
else if (opc == 8)
{
OUTS (outf, "DIVQ (");
OUTS (outf, dregs (dst));
OUTS (outf, ", ");
OUTS (outf, dregs (src));
OUTS (outf, ")");
}
else if (opc == 9)
{
OUTS (outf, "DIVS (");
OUTS (outf, dregs (dst));
OUTS (outf, ", ");
OUTS (outf, dregs (src));
OUTS (outf, ")");
}
else if (opc == 10)
{
OUTS (outf, dregs (dst));
OUTS (outf, " = ");
OUTS (outf, dregs_lo (src));
OUTS (outf, " (X)");
}
else if (opc == 11)
{
OUTS (outf, dregs (dst));
OUTS (outf, " = ");
OUTS (outf, dregs_lo (src));
OUTS (outf, " (Z)");
}
else if (opc == 12)
{
OUTS (outf, dregs (dst));
OUTS (outf, " = ");
OUTS (outf, dregs_byte (src));
OUTS (outf, " (X)");
}
else if (opc == 13)
{
OUTS (outf, dregs (dst));
OUTS (outf, " = ");
OUTS (outf, dregs_byte (src));
OUTS (outf, " (Z)");
}
else if (opc == 14)
{
OUTS (outf, dregs (dst));
OUTS (outf, " = -");
OUTS (outf, dregs (src));
}
else if (opc == 15)
{
OUTS (outf, dregs (dst));
OUTS (outf, " =~ ");
OUTS (outf, dregs (src));
}
else
return 0;
return 2;
}
static int
decode_PTR2op_0 (TIword iw0, disassemble_info *outf)
{
/* PTR2op
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
int src = ((iw0 >> PTR2op_src_bits) & PTR2op_dst_mask);
int opc = ((iw0 >> PTR2op_opc_bits) & PTR2op_opc_mask);
int dst = ((iw0 >> PTR2op_dst_bits) & PTR2op_dst_mask);
if (opc == 0)
{
OUTS (outf, pregs (dst));
OUTS (outf, " -= ");
OUTS (outf, pregs (src));
}
else if (opc == 1)
{
OUTS (outf, pregs (dst));
OUTS (outf, " = ");
OUTS (outf, pregs (src));
OUTS (outf, " << 0x2");
}
else if (opc == 3)
{
OUTS (outf, pregs (dst));
OUTS (outf, " = ");
OUTS (outf, pregs (src));
OUTS (outf, " >> 0x2");
}
else if (opc == 4)
{
OUTS (outf, pregs (dst));
OUTS (outf, " = ");
OUTS (outf, pregs (src));
OUTS (outf, " >> 0x1");
}
else if (opc == 5)
{
OUTS (outf, pregs (dst));
OUTS (outf, " += ");
OUTS (outf, pregs (src));
OUTS (outf, " (BREV)");
}
else if (opc == 6)
{
OUTS (outf, pregs (dst));
OUTS (outf, " = (");
OUTS (outf, pregs (dst));
OUTS (outf, " + ");
OUTS (outf, pregs (src));
OUTS (outf, ") << 0x1");
}
else if (opc == 7)
{
OUTS (outf, pregs (dst));
OUTS (outf, " = (");
OUTS (outf, pregs (dst));
OUTS (outf, " + ");
OUTS (outf, pregs (src));
OUTS (outf, ") << 0x2");
}
else
return 0;
return 2;
}
static int
decode_LOGI2op_0 (TIword iw0, disassemble_info *outf)
{
struct private *priv = outf->private_data;
/* LOGI2op
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
int src = ((iw0 >> LOGI2op_src_bits) & LOGI2op_src_mask);
int opc = ((iw0 >> LOGI2op_opc_bits) & LOGI2op_opc_mask);
int dst = ((iw0 >> LOGI2op_dst_bits) & LOGI2op_dst_mask);
if (priv->parallel)
return 0;
if (opc == 0)
{
OUTS (outf, "CC = !BITTST (");
OUTS (outf, dregs (dst));
OUTS (outf, ", ");
OUTS (outf, uimm5 (src));
OUTS (outf, ");\t\t/* bit");
OUTS (outf, imm7d (src));
OUTS (outf, " */");
priv->comment = TRUE;
}
else if (opc == 1)
{
OUTS (outf, "CC = BITTST (");
OUTS (outf, dregs (dst));
OUTS (outf, ", ");
OUTS (outf, uimm5 (src));
OUTS (outf, ");\t\t/* bit");
OUTS (outf, imm7d (src));
OUTS (outf, " */");
priv->comment = TRUE;
}
else if (opc == 2)
{
OUTS (outf, "BITSET (");
OUTS (outf, dregs (dst));
OUTS (outf, ", ");
OUTS (outf, uimm5 (src));
OUTS (outf, ");\t\t/* bit");
OUTS (outf, imm7d (src));
OUTS (outf, " */");
priv->comment = TRUE;
}
else if (opc == 3)
{
OUTS (outf, "BITTGL (");
OUTS (outf, dregs (dst));
OUTS (outf, ", ");
OUTS (outf, uimm5 (src));
OUTS (outf, ");\t\t/* bit");
OUTS (outf, imm7d (src));
OUTS (outf, " */");
priv->comment = TRUE;
}
else if (opc == 4)
{
OUTS (outf, "BITCLR (");
OUTS (outf, dregs (dst));
OUTS (outf, ", ");
OUTS (outf, uimm5 (src));
OUTS (outf, ");\t\t/* bit");
OUTS (outf, imm7d (src));
OUTS (outf, " */");
priv->comment = TRUE;
}
else if (opc == 5)
{
OUTS (outf, dregs (dst));
OUTS (outf, " >>>= ");
OUTS (outf, uimm5 (src));
}
else if (opc == 6)
{
OUTS (outf, dregs (dst));
OUTS (outf, " >>= ");
OUTS (outf, uimm5 (src));
}
else if (opc == 7)
{
OUTS (outf, dregs (dst));
OUTS (outf, " <<= ");
OUTS (outf, uimm5 (src));
}
else
return 0;
return 2;
}
static int
decode_COMP3op_0 (TIword iw0, disassemble_info *outf)
{
/* COMP3op
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
int opc = ((iw0 >> COMP3op_opc_bits) & COMP3op_opc_mask);
int dst = ((iw0 >> COMP3op_dst_bits) & COMP3op_dst_mask);
int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask);
int src1 = ((iw0 >> COMP3op_src1_bits) & COMP3op_src1_mask);
if (opc == 5 && src1 == src0)
{
OUTS (outf, pregs (dst));
OUTS (outf, " = ");
OUTS (outf, pregs (src0));
OUTS (outf, " << 0x1");
}
else if (opc == 1)
{
OUTS (outf, dregs (dst));
OUTS (outf, " = ");
OUTS (outf, dregs (src0));
OUTS (outf, " - ");
OUTS (outf, dregs (src1));
}
else if (opc == 2)
{
OUTS (outf, dregs (dst));
OUTS (outf, " = ");
OUTS (outf, dregs (src0));
OUTS (outf, " & ");
OUTS (outf, dregs (src1));
}
else if (opc == 3)
{
OUTS (outf, dregs (dst));
OUTS (outf, " = ");
OUTS (outf, dregs (src0));
OUTS (outf, " | ");
OUTS (outf, dregs (src1));
}
else if (opc == 4)
{
OUTS (outf, dregs (dst));
OUTS (outf, " = ");
OUTS (outf, dregs (src0));
OUTS (outf, " ^ ");
OUTS (outf, dregs (src1));
}
else if (opc == 5)
{
OUTS (outf, pregs (dst));
OUTS (outf, " = ");
OUTS (outf, pregs (src0));
OUTS (outf, " + ");
OUTS (outf, pregs (src1));
}
else if (opc == 6)
{
OUTS (outf, pregs (dst));
OUTS (outf, " = ");
OUTS (outf, pregs (src0));
OUTS (outf, " + (");
OUTS (outf, pregs (src1));
OUTS (outf, " << 0x1)");
}
else if (opc == 7)
{
OUTS (outf, pregs (dst));
OUTS (outf, " = ");
OUTS (outf, pregs (src0));
OUTS (outf, " + (");
OUTS (outf, pregs (src1));
OUTS (outf, " << 0x2)");
}
else if (opc == 0)
{
OUTS (outf, dregs (dst));
OUTS (outf, " = ");
OUTS (outf, dregs (src0));
OUTS (outf, " + ");
OUTS (outf, dregs (src1));
}
else
return 0;
return 2;
}
static int
decode_COMPI2opD_0 (TIword iw0, disassemble_info *outf)
{
struct private *priv = outf->private_data;
/* COMPI2opD
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 0 | 1 | 1 | 0 | 0 |.op|..src......................|.dst.......|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
int op = ((iw0 >> COMPI2opD_op_bits) & COMPI2opD_op_mask);
int dst = ((iw0 >> COMPI2opD_dst_bits) & COMPI2opD_dst_mask);
int src = ((iw0 >> COMPI2opD_src_bits) & COMPI2opD_src_mask);
bu32 *pval = get_allreg (0, dst);
if (priv->parallel)
return 0;
/* Since we don't have 32-bit immediate loads, we allow the disassembler
to combine them, so it prints out the right values.
Here we keep track of the registers. */
if (op == 0)
{
*pval = imm7_val (src);
if (src & 0x40)
*pval |= 0xFFFFFF80;
else
*pval &= 0x7F;
}
if (op == 0)
{
OUTS (outf, dregs (dst));
OUTS (outf, " = ");
OUTS (outf, imm7 (src));
OUTS (outf, " (X);\t\t/*\t\t");
OUTS (outf, dregs (dst));
OUTS (outf, "=");
OUTS (outf, uimm32 (*pval));
OUTS (outf, "(");
OUTS (outf, imm32 (*pval));
OUTS (outf, ") */");
priv->comment = TRUE;
}
else if (op == 1)
{
OUTS (outf, dregs (dst));
OUTS (outf, " += ");
OUTS (outf, imm7 (src));
OUTS (outf, ";\t\t/* (");
OUTS (outf, imm7d (src));
OUTS (outf, ") */");
priv->comment = TRUE;
}
else
return 0;
return 2;
}
static int
decode_COMPI2opP_0 (TIword iw0, disassemble_info *outf)
{
struct private *priv = outf->private_data;
/* COMPI2opP
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
int op = ((iw0 >> COMPI2opP_op_bits) & COMPI2opP_op_mask);
int src = ((iw0 >> COMPI2opP_src_bits) & COMPI2opP_src_mask);
int dst = ((iw0 >> COMPI2opP_dst_bits) & COMPI2opP_dst_mask);
bu32 *pval = get_allreg (1, dst);
if (priv->parallel)
return 0;
if (op == 0)
{
*pval = imm7_val (src);
if (src & 0x40)
*pval |= 0xFFFFFF80;
else
*pval &= 0x7F;
}
if (op == 0)
{
OUTS (outf, pregs (dst));
OUTS (outf, " = ");
OUTS (outf, imm7 (src));
OUTS (outf, " (X);\t\t/*\t\t");
OUTS (outf, pregs (dst));
OUTS (outf, "=");
OUTS (outf, uimm32 (*pval));
OUTS (outf, "(");
OUTS (outf, imm32 (*pval));
OUTS (outf, ") */");
priv->comment = TRUE;
}
else if (op == 1)
{
OUTS (outf, pregs (dst));
OUTS (outf, " += ");
OUTS (outf, imm7 (src));
OUTS (outf, ";\t\t/* (");
OUTS (outf, imm7d (src));
OUTS (outf, ") */");
priv->comment = TRUE;
}
else
return 0;
return 2;
}
static int
decode_LDSTpmod_0 (TIword iw0, disassemble_info *outf)
{
/* LDSTpmod
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
int W = ((iw0 >> LDSTpmod_W_bits) & LDSTpmod_W_mask);
int aop = ((iw0 >> LDSTpmod_aop_bits) & LDSTpmod_aop_mask);
int idx = ((iw0 >> LDSTpmod_idx_bits) & LDSTpmod_idx_mask);
int ptr = ((iw0 >> LDSTpmod_ptr_bits) & LDSTpmod_ptr_mask);
int reg = ((iw0 >> LDSTpmod_reg_bits) & LDSTpmod_reg_mask);
if (aop == 1 && W == 0 && idx == ptr)
{
OUTS (outf, dregs_lo (reg));
OUTS (outf, " = W[");
OUTS (outf, pregs (ptr));
OUTS (outf, "]");
}
else if (aop == 2 && W == 0 && idx == ptr)
{
OUTS (outf, dregs_hi (reg));
OUTS (outf, " = W[");
OUTS (outf, pregs (ptr));
OUTS (outf, "]");
}
else if (aop == 1 && W == 1 && idx == ptr)
{
OUTS (outf, "W[");
OUTS (outf, pregs (ptr));
OUTS (outf, "] = ");
OUTS (outf, dregs_lo (reg));
}
else if (aop == 2 && W == 1 && idx == ptr)
{
OUTS (outf, "W[");
OUTS (outf, pregs (ptr));
OUTS (outf, "] = ");
OUTS (outf, dregs_hi (reg));
}
else if (aop == 0 && W == 0)
{
OUTS (outf, dregs (reg));
OUTS (outf, " = [");
OUTS (outf, pregs (ptr));
OUTS (outf, " ++ ");
OUTS (outf, pregs (idx));
OUTS (outf, "]");
}
else if (aop == 1 && W == 0)
{
OUTS (outf, dregs_lo (reg));
OUTS (outf, " = W[");
OUTS (outf, pregs (ptr));
OUTS (outf, " ++ ");
OUTS (outf, pregs (idx));
OUTS (outf, "]");
}
else if (aop == 2 && W == 0)
{
OUTS (outf, dregs_hi (reg));
OUTS (outf, " = W[");
OUTS (outf, pregs (ptr));
OUTS (outf, " ++ ");
OUTS (outf, pregs (idx));
OUTS (outf, "]");
}
else if (aop == 3 && W == 0)
{
OUTS (outf, dregs (reg));
OUTS (outf, " = W[");
OUTS (outf, pregs (ptr));
OUTS (outf, " ++ ");
OUTS (outf, pregs (idx));
OUTS (outf, "] (Z)");
}
else if (aop == 3 && W == 1)
{
OUTS (outf, dregs (reg));
OUTS (outf, " = W[");
OUTS (outf, pregs (ptr));
OUTS (outf, " ++ ");
OUTS (outf, pregs (idx));
OUTS (outf, "] (X)");
}
else if (aop == 0 && W == 1)
{
OUTS (outf, "[");
OUTS (outf, pregs (ptr));
OUTS (outf, " ++ ");
OUTS (outf, pregs (idx));
OUTS (outf, "] = ");
OUTS (outf, dregs (reg));
}
else if (aop == 1 && W == 1)
{
OUTS (outf, "W[");
OUTS (outf, pregs (ptr));
OUTS (outf, " ++ ");
OUTS (outf, pregs (idx));
OUTS (outf, "] = ");
OUTS (outf, dregs_lo (reg));
}
else if (aop == 2 && W == 1)
{
OUTS (outf, "W[");
OUTS (outf, pregs (ptr));
OUTS (outf, " ++ ");
OUTS (outf, pregs (idx));
OUTS (outf, "] = ");
OUTS (outf, dregs_hi (reg));
}
else
return 0;
return 2;
}
static int
decode_dagMODim_0 (TIword iw0, disassemble_info *outf)
{
/* dagMODim
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
int i = ((iw0 >> DagMODim_i_bits) & DagMODim_i_mask);
int m = ((iw0 >> DagMODim_m_bits) & DagMODim_m_mask);
int br = ((iw0 >> DagMODim_br_bits) & DagMODim_br_mask);
int op = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask);
if (op == 0 && br == 1)
{
OUTS (outf, iregs (i));
OUTS (outf, " += ");
OUTS (outf, mregs (m));
OUTS (outf, " (BREV)");
}
else if (op == 0)
{
OUTS (outf, iregs (i));
OUTS (outf, " += ");
OUTS (outf, mregs (m));
}
else if (op == 1 && br == 0)
{
OUTS (outf, iregs (i));
OUTS (outf, " -= ");
OUTS (outf, mregs (m));
}
else
return 0;
return 2;
}
static int
decode_dagMODik_0 (TIword iw0, disassemble_info *outf)
{
struct private *priv = outf->private_data;
/* dagMODik
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
int i = ((iw0 >> DagMODik_i_bits) & DagMODik_i_mask);
int op = ((iw0 >> DagMODik_op_bits) & DagMODik_op_mask);
if (op == 0)
{
OUTS (outf, iregs (i));
OUTS (outf, " += 0x2");
}
else if (op == 1)
{
OUTS (outf, iregs (i));
OUTS (outf, " -= 0x2");
}
else if (op == 2)
{
OUTS (outf, iregs (i));
OUTS (outf, " += 0x4");
}
else if (op == 3)
{
OUTS (outf, iregs (i));
OUTS (outf, " -= 0x4");
}
else
return 0;
if (!priv->parallel)
{
OUTS (outf, ";\t\t/* ( ");
if (op == 0 || op == 1)
OUTS (outf, "2");
else if (op == 2 || op == 3)
OUTS (outf, "4");
OUTS (outf, ") */");
priv->comment = TRUE;
}
return 2;
}
static int
decode_dspLDST_0 (TIword iw0, disassemble_info *outf)
{
/* dspLDST
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
int i = ((iw0 >> DspLDST_i_bits) & DspLDST_i_mask);
int m = ((iw0 >> DspLDST_m_bits) & DspLDST_m_mask);
int W = ((iw0 >> DspLDST_W_bits) & DspLDST_W_mask);
int aop = ((iw0 >> DspLDST_aop_bits) & DspLDST_aop_mask);
int reg = ((iw0 >> DspLDST_reg_bits) & DspLDST_reg_mask);
if (aop == 0 && W == 0 && m == 0)
{
OUTS (outf, dregs (reg));
OUTS (outf, " = [");
OUTS (outf, iregs (i));
OUTS (outf, "++]");
}
else if (aop == 0 && W == 0 && m == 1)
{
OUTS (outf, dregs_lo (reg));
OUTS (outf, " = W[");
OUTS (outf, iregs (i));
OUTS (outf, "++]");
}
else if (aop == 0 && W == 0 && m == 2)
{
OUTS (outf, dregs_hi (reg));
OUTS (outf, " = W[");
OUTS (outf, iregs (i));
OUTS (outf, "++]");
}
else if (aop == 1 && W == 0 && m == 0)
{
OUTS (outf, dregs (reg));
OUTS (outf, " = [");
OUTS (outf, iregs (i));
OUTS (outf, "--]");
}
else if (aop == 1 && W == 0 && m == 1)
{
OUTS (outf, dregs_lo (reg));
OUTS (outf, " = W[");
OUTS (outf, iregs (i));
OUTS (outf, "--]");
}
else if (aop == 1 && W == 0 && m == 2)
{
OUTS (outf, dregs_hi (reg));
OUTS (outf, " = W[");
OUTS (outf, iregs (i));
OUTS (outf, "--]");
}
else if (aop == 2 && W == 0 && m == 0)
{
OUTS (outf, dregs (reg));
OUTS (outf, " = [");
OUTS (outf, iregs (i));
OUTS (outf, "]");
}
else if (aop == 2 && W == 0 && m == 1)
{
OUTS (outf, dregs_lo (reg));
OUTS (outf, " = W[");
OUTS (outf, iregs (i));
OUTS (outf, "]");
}
else if (aop == 2 && W == 0 && m == 2)
{
OUTS (outf, dregs_hi (reg));
OUTS (outf, " = W[");
OUTS (outf, iregs (i));
OUTS (outf, "]");
}
else if (aop == 0 && W == 1 && m == 0)
{
OUTS (outf, "[");
OUTS (outf, iregs (i));
OUTS (outf, "++] = ");
OUTS (outf, dregs (reg));
}
else if (aop == 0 && W == 1 && m == 1)
{
OUTS (outf, "W[");
OUTS (outf, iregs (i));
OUTS (outf, "++] = ");
OUTS (outf, dregs_lo (reg));
}
else if (aop == 0 && W == 1 && m == 2)
{
OUTS (outf, "W[");
OUTS (outf, iregs (i));
OUTS (outf, "++] = ");
OUTS (outf, dregs_hi (reg));
}
else if (aop == 1 && W == 1 && m == 0)
{
OUTS (outf, "[");
OUTS (outf, iregs (i));
OUTS (outf, "--] = ");
OUTS (outf, dregs (reg));
}
else if (aop == 1 && W == 1 && m == 1)
{
OUTS (outf, "W[");
OUTS (outf, iregs (i));
OUTS (outf, "--] = ");
OUTS (outf, dregs_lo (reg));
}
else if (aop == 1 && W == 1 && m == 2)
{
OUTS (outf, "W[");
OUTS (outf, iregs (i));
OUTS (outf, "--] = ");
OUTS (outf, dregs_hi (reg));
}
else if (aop == 2 && W == 1 && m == 0)
{
OUTS (outf, "[");
OUTS (outf, iregs (i));
OUTS (outf, "] = ");
OUTS (outf, dregs (reg));
}
else if (aop == 2 && W == 1 && m == 1)
{
OUTS (outf, "W[");
OUTS (outf, iregs (i));
OUTS (outf, "] = ");
OUTS (outf, dregs_lo (reg));
}
else if (aop == 2 && W == 1 && m == 2)
{
OUTS (outf, "W[");
OUTS (outf, iregs (i));
OUTS (outf, "] = ");
OUTS (outf, dregs_hi (reg));
}
else if (aop == 3 && W == 0)
{
OUTS (outf, dregs (reg));
OUTS (outf, " = [");
OUTS (outf, iregs (i));
OUTS (outf, " ++ ");
OUTS (outf, mregs (m));
OUTS (outf, "]");
}
else if (aop == 3 && W == 1)
{
OUTS (outf, "[");
OUTS (outf, iregs (i));
OUTS (outf, " ++ ");
OUTS (outf, mregs (m));
OUTS (outf, "] = ");
OUTS (outf, dregs (reg));
}
else
return 0;
return 2;
}
static int
decode_LDST_0 (TIword iw0, disassemble_info *outf)
{
/* LDST
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
int Z = ((iw0 >> LDST_Z_bits) & LDST_Z_mask);
int W = ((iw0 >> LDST_W_bits) & LDST_W_mask);
int sz = ((iw0 >> LDST_sz_bits) & LDST_sz_mask);
int aop = ((iw0 >> LDST_aop_bits) & LDST_aop_mask);
int reg = ((iw0 >> LDST_reg_bits) & LDST_reg_mask);
int ptr = ((iw0 >> LDST_ptr_bits) & LDST_ptr_mask);
if (aop == 0 && sz == 0 && Z == 0 && W == 0)
{
OUTS (outf, dregs (reg));
OUTS (outf, " = [");
OUTS (outf, pregs (ptr));
OUTS (outf, "++]");
}
else if (aop == 0 && sz == 0 && Z == 1 && W == 0 && reg != ptr)
{
OUTS (outf, pregs (reg));
OUTS (outf, " = [");
OUTS (outf, pregs (ptr));
OUTS (outf, "++]");
}
else if (aop == 0 && sz == 1 && Z == 0 && W == 0)
{
OUTS (outf, dregs (reg));
OUTS (outf, " = W[");
OUTS (outf, pregs (ptr));
OUTS (outf, "++] (Z)");
}
else if (aop == 0 && sz == 1 && Z == 1 && W == 0)
{
OUTS (outf, dregs (reg));
OUTS (outf, " = W[");
OUTS (outf, pregs (ptr));
OUTS (outf, "++] (X)");
}
else if (aop == 0 && sz == 2 && Z == 0 && W == 0)
{
OUTS (outf, dregs (reg));
OUTS (outf, " = B[");
OUTS (outf, pregs (ptr));
OUTS (outf, "++] (Z)");
}
else if (aop == 0 && sz == 2 && Z == 1 && W == 0)
{
OUTS (outf, dregs (reg));
OUTS (outf, " = B[");
OUTS (outf, pregs (ptr));
OUTS (outf, "++] (X)");
}
else if (aop == 1 && sz == 0 && Z == 0 && W == 0)
{
OUTS (outf, dregs (reg));
OUTS (outf, " = [");
OUTS (outf, pregs (ptr));
OUTS (outf, "--]");
}
else if (aop == 1 && sz == 0 && Z == 1 && W == 0 && reg != ptr)
{
OUTS (outf, pregs (reg));
OUTS (outf, " = [");
OUTS (outf, pregs (ptr));
OUTS (outf, "--]");
}
else if (aop == 1 && sz == 1 && Z == 0 && W == 0)
{
OUTS (outf, dregs (reg));
OUTS (outf, " = W[");
OUTS (outf, pregs (ptr));
OUTS (outf, "--] (Z)");
}
else if (aop == 1 && sz == 1 && Z == 1 && W == 0)
{
OUTS (outf, dregs (reg));
OUTS (outf, " = W[");
OUTS (outf, pregs (ptr));
OUTS