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b836cb185eb423846e42ec8eeaf07033ed39c1c7
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sim
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testsuite
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sim
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bfin
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lp0.s
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//
Assert that loops can have coincidental loop ends.
# mach: bfin
.include
"testutils.inc"
start
P0
=
3
;
R1
=
0
;
LSETUP
(
out0
,
out1
)
LC0
=
P0
;
out0
:
LSETUP
(
out1
,
out1
)
LC1
=
P0
;
out1
:
R1
+=
1
;
DBGA
(
R1.L
,
9
);
pass