| /* Main simulator entry points specific to the SH5. |
| Copyright (C) 2000-2016 Free Software Foundation, Inc. |
| Contributed by Cygnus Solutions. |
| |
| This file is part of the GNU simulators. |
| |
| This program is free software; you can redistribute it and/or modify |
| it under the terms of the GNU General Public License as published by |
| the Free Software Foundation; either version 3 of the License, or |
| (at your option) any later version. |
| |
| This program is distributed in the hope that it will be useful, |
| but WITHOUT ANY WARRANTY; without even the implied warranty of |
| MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| GNU General Public License for more details. |
| |
| You should have received a copy of the GNU General Public License |
| along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| |
| #include "config.h" |
| #include "libiberty.h" |
| #include "bfd.h" |
| #include "sim-main.h" |
| #ifdef HAVE_STDLIB_H |
| #include <stdlib.h> |
| #endif |
| #include "sim-options.h" |
| #include "dis-asm.h" |
| |
| static void free_state (SIM_DESC); |
| |
| /* Since we don't build the cgen-opcode table, we use a wrapper around |
| the existing disassembler from libopcodes. */ |
| static CGEN_DISASSEMBLER sh64_disassemble_insn; |
| |
| /* Cover function of sim_state_free to free the cpu buffers as well. */ |
| |
| static void |
| free_state (SIM_DESC sd) |
| { |
| if (STATE_MODULES (sd) != NULL) |
| sim_module_uninstall (sd); |
| sim_cpu_free_all (sd); |
| sim_state_free (sd); |
| } |
| |
| /* Create an instance of the simulator. */ |
| |
| SIM_DESC |
| sim_open (kind, callback, abfd, argv) |
| SIM_OPEN_KIND kind; |
| host_callback *callback; |
| struct bfd *abfd; |
| char * const *argv; |
| { |
| char c; |
| int i; |
| SIM_DESC sd = sim_state_alloc (kind, callback); |
| |
| /* The cpu data is kept in a separately allocated chunk of memory. */ |
| if (sim_cpu_alloc_all (sd, 1, cgen_cpu_max_extra_bytes ()) != SIM_RC_OK) |
| { |
| free_state (sd); |
| return 0; |
| } |
| |
| #if 0 /* FIXME: pc is in mach-specific struct */ |
| /* FIXME: watchpoints code shouldn't need this */ |
| { |
| SIM_CPU *current_cpu = STATE_CPU (sd, 0); |
| STATE_WATCHPOINTS (sd)->pc = &(PC); |
| STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC); |
| } |
| #endif |
| |
| if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) |
| { |
| free_state (sd); |
| return 0; |
| } |
| |
| /* The parser will print an error message for us, so we silently return. */ |
| if (sim_parse_args (sd, argv) != SIM_RC_OK) |
| { |
| free_state (sd); |
| return 0; |
| } |
| |
| /* Allocate core managed memory if none specified by user. |
| Use address 4 here in case the user wanted address 0 unmapped. */ |
| if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0) |
| sim_do_commandf (sd, "memory region 0,0x%x", SH64_DEFAULT_MEM_SIZE); |
| |
| /* Add a small memory region way up in the address space to handle |
| writes to invalidate an instruction cache line. This is used for |
| trampolines. Since we don't simulate the cache, this memory just |
| avoids bus errors. 64K ought to do. */ |
| sim_do_command (sd," memory region 0xf0000000,0x10000"); |
| |
| /* check for/establish the reference program image */ |
| if (sim_analyze_program (sd, |
| (STATE_PROG_ARGV (sd) != NULL |
| ? *STATE_PROG_ARGV (sd) |
| : NULL), |
| abfd) != SIM_RC_OK) |
| { |
| free_state (sd); |
| return 0; |
| } |
| |
| /* Establish any remaining configuration options. */ |
| if (sim_config (sd) != SIM_RC_OK) |
| { |
| free_state (sd); |
| return 0; |
| } |
| |
| if (sim_post_argv_init (sd) != SIM_RC_OK) |
| { |
| free_state (sd); |
| return 0; |
| } |
| |
| /* Open a copy of the cpu descriptor table. */ |
| { |
| CGEN_CPU_DESC cd = sh_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name, |
| CGEN_ENDIAN_BIG); |
| |
| for (i = 0; i < MAX_NR_PROCESSORS; ++i) |
| { |
| SIM_CPU *cpu = STATE_CPU (sd, i); |
| CPU_CPU_DESC (cpu) = cd; |
| CPU_DISASSEMBLER (cpu) = sh64_disassemble_insn; |
| } |
| } |
| |
| /* Clear idesc table pointers for good measure. */ |
| sh64_idesc_media = sh64_idesc_compact = NULL; |
| |
| /* Initialize various cgen things not done by common framework. |
| Must be done after sh_cgen_cpu_open. */ |
| cgen_init (sd); |
| |
| return sd; |
| } |
| |
| SIM_RC |
| sim_create_inferior (sd, abfd, argv, envp) |
| SIM_DESC sd; |
| struct bfd *abfd; |
| char * const *argv; |
| char * const *envp; |
| { |
| SIM_CPU *current_cpu = STATE_CPU (sd, 0); |
| SIM_ADDR addr; |
| |
| if (abfd != NULL) |
| addr = bfd_get_start_address (abfd); |
| else |
| addr = 0; |
| sim_pc_set (current_cpu, addr); |
| |
| /* Standalone mode (i.e. `run`) will take care of the argv for us in |
| sim_open() -> sim_parse_args(). But in debug mode (i.e. 'target sim' |
| with `gdb`), we need to handle it because the user can change the |
| argv on the fly via gdb's 'run'. */ |
| if (STATE_PROG_ARGV (sd) != argv) |
| { |
| freeargv (STATE_PROG_ARGV (sd)); |
| STATE_PROG_ARGV (sd) = dupargv (argv); |
| } |
| |
| return SIM_RC_OK; |
| } |
| |
| /* Disassemble an instruction. */ |
| |
| static void |
| sh64_disassemble_insn (SIM_CPU *cpu, const CGEN_INSN *insn, |
| const ARGBUF *abuf, IADDR pc, char *buf) |
| { |
| struct disassemble_info disasm_info; |
| SFILE sfile; |
| SIM_DESC sd = CPU_STATE (cpu); |
| |
| sfile.buffer = sfile.current = buf; |
| INIT_DISASSEMBLE_INFO (disasm_info, (FILE *) &sfile, |
| (fprintf_ftype) sim_disasm_sprintf); |
| |
| disasm_info.arch = bfd_get_arch (STATE_PROG_BFD (sd)); |
| disasm_info.mach = bfd_get_mach (STATE_PROG_BFD (sd)); |
| disasm_info.endian = |
| (bfd_big_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_BIG |
| : bfd_little_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_LITTLE |
| : BFD_ENDIAN_UNKNOWN); |
| disasm_info.read_memory_func = sim_disasm_read_memory; |
| disasm_info.memory_error_func = sim_disasm_perror_memory; |
| disasm_info.application_data = (PTR) cpu; |
| |
| if (sh64_h_ism_get (cpu) == ISM_MEDIA) |
| print_insn_sh64x_media (pc, &disasm_info); |
| else |
| print_insn_sh (pc, &disasm_info); |
| } |