| //Original:/testcases/core/c_dsp32alu_rh_m/c_dsp32alu_rh_m.dsp | |
| // Spec Reference: dsp32alu dreg (half) | |
| # mach: bfin | |
| .include "testutils.inc" | |
| start | |
| imm32 r0, 0x89678911; | |
| imm32 r1, 0x2189ab1d; | |
| imm32 r2, 0x34145515; | |
| imm32 r3, 0x46617717; | |
| imm32 r4, 0x5678191b; | |
| imm32 r5, 0x6789a11d; | |
| imm32 r6, 0x74445515; | |
| imm32 r7, 0x86667771; | |
| R0.H = R0.L - R0.L (NS); | |
| R1.H = R0.L - R1.H (NS); | |
| R2.H = R0.H - R2.L (NS); | |
| R3.H = R0.H - R3.H (NS); | |
| R4.H = R0.L - R4.L (NS); | |
| R5.H = R0.L - R5.H (NS); | |
| R6.H = R0.H - R6.L (NS); | |
| R7.H = R0.H - R7.H (NS); | |
| CHECKREG r4, 0x6FF6191B; | |
| CHECKREG r5, 0x2188A11D; | |
| CHECKREG r6, 0xAAEB5515; | |
| CHECKREG r7, 0x799A7771; | |
| CHECKREG r4, 0x6FF6191B; | |
| CHECKREG r5, 0x2188A11D; | |
| CHECKREG r6, 0xAAEB5515; | |
| CHECKREG r7, 0x799A7771; | |
| imm32 r0, 0x25678911; | |
| imm32 r1, 0x2789ab1d; | |
| imm32 r2, 0x38445515; | |
| imm32 r3, 0x468a7717; | |
| imm32 r4, 0x5678e91b; | |
| imm32 r5, 0x6789af1d; | |
| imm32 r6, 0x744455f5; | |
| imm32 r7, 0x8666777f; | |
| R0.H = R1.L - R0.L (NS); | |
| R1.H = R1.L - R1.H (NS); | |
| R2.H = R1.H - R2.L (NS); | |
| R3.H = R1.H - R3.H (NS); | |
| R4.H = R1.L - R4.L (NS); | |
| R5.H = R1.L - R5.H (NS); | |
| R6.H = R1.H - R6.L (NS); | |
| R7.H = R1.H - R7.H (NS); | |
| CHECKREG r4, 0xC202E91B; | |
| CHECKREG r5, 0x4394AF1D; | |
| CHECKREG r6, 0x2D9F55F5; | |
| CHECKREG r7, 0xFD2E777F; | |
| CHECKREG r4, 0xC202E91B; | |
| CHECKREG r5, 0x4394AF1D; | |
| CHECKREG r6, 0x2D9F55F5; | |
| CHECKREG r7, 0xFD2E777F; | |
| imm32 r0, 0x78678911; | |
| imm32 r1, 0x2789ab1d; | |
| imm32 r2, 0x34885515; | |
| imm32 r3, 0x466aa717; | |
| imm32 r4, 0x5678891b; | |
| imm32 r5, 0x6789aa1d; | |
| imm32 r6, 0x74445aa5; | |
| imm32 r7, 0x866677a7; | |
| R0.H = R2.L - R0.L (NS); | |
| R1.H = R2.L - R1.H (NS); | |
| R2.H = R2.H - R2.L (NS); | |
| R3.H = R2.H - R3.H (NS); | |
| R4.H = R2.L - R4.L (NS); | |
| R5.H = R2.L - R5.H (NS); | |
| R6.H = R2.H - R6.L (NS); | |
| R7.H = R2.H - R7.H (NS); | |
| CHECKREG r4, 0xCBFA891B; | |
| CHECKREG r5, 0xED8CAA1D; | |
| CHECKREG r6, 0x84CE5AA5; | |
| CHECKREG r7, 0x590D77A7; | |
| CHECKREG r4, 0xCBFA891B; | |
| CHECKREG r5, 0xED8CAA1D; | |
| CHECKREG r6, 0x84CE5AA5; | |
| CHECKREG r7, 0x590D77A7; | |
| imm32 r0, 0xb5678911; | |
| imm32 r1, 0xb789ab1d; | |
| imm32 r2, 0x3b445515; | |
| imm32 r3, 0x46b67717; | |
| imm32 r4, 0x567b891b; | |
| imm32 r5, 0x6789bb1d; | |
| imm32 r6, 0x74445b15; | |
| imm32 r7, 0x866677b7; | |
| R0.H = R3.L - R0.L (NS); | |
| R1.H = R3.L - R1.H (NS); | |
| R2.H = R3.H - R2.L (NS); | |
| R3.H = R3.H - R3.H (NS); | |
| R4.H = R3.L - R4.L (NS); | |
| R5.H = R3.L - R5.H (NS); | |
| R6.H = R3.H - R6.L (NS); | |
| R7.H = R3.H - R7.H (NS); | |
| CHECKREG r4, 0xEDFC891B; | |
| CHECKREG r5, 0x0F8EBB1D; | |
| CHECKREG r6, 0xA4EB5B15; | |
| CHECKREG r7, 0x799A77B7; | |
| CHECKREG r4, 0xEDFC891B; | |
| CHECKREG r5, 0x0F8EBB1D; | |
| CHECKREG r6, 0xA4EB5B15; | |
| CHECKREG r7, 0x799A77B7; | |
| imm32 r0, 0x15678911; | |
| imm32 r1, 0x2789ab1d; | |
| imm32 r2, 0x34445515; | |
| imm32 r3, 0x46667717; | |
| imm32 r4, 0x5678891b; | |
| imm32 r5, 0x6789ab1d; | |
| imm32 r6, 0x74445515; | |
| imm32 r7, 0x86667777; | |
| R0.H = R4.L - R0.L (NS); | |
| R1.H = R4.L - R1.H (NS); | |
| R2.H = R4.H - R2.L (NS); | |
| R3.H = R4.H - R3.H (NS); | |
| R4.H = R4.L - R4.L (NS); | |
| R5.H = R4.L - R5.H (NS); | |
| R6.H = R4.H - R6.L (NS); | |
| R7.H = R4.H - R7.H (NS); | |
| CHECKREG r4, 0x0000891B; | |
| CHECKREG r5, 0x2192AB1D; | |
| CHECKREG r6, 0xAAEB5515; | |
| CHECKREG r7, 0x799A7777; | |
| CHECKREG r4, 0x0000891B; | |
| CHECKREG r5, 0x2192AB1D; | |
| CHECKREG r6, 0xAAEB5515; | |
| CHECKREG r7, 0x799A7777; | |
| imm32 r0, 0xcc678911; | |
| imm32 r1, 0xc789ab1d; | |
| imm32 r2, 0x3c445515; | |
| imm32 r3, 0x46c67717; | |
| imm32 r4, 0x567c891b; | |
| imm32 r5, 0x6789cb1d; | |
| imm32 r6, 0x74445c15; | |
| imm32 r7, 0x866677c7; | |
| R0.H = R5.L - R0.L (NS); | |
| R1.H = R5.L - R1.H (NS); | |
| R2.H = R5.H - R2.L (NS); | |
| R3.H = R5.H - R3.H (NS); | |
| R4.H = R5.L - R4.L (NS); | |
| R5.H = R5.L - R5.H (NS); | |
| R6.H = R5.H - R6.L (NS); | |
| R7.H = R5.H - R7.H (NS); | |
| CHECKREG r4, 0x4202891B; | |
| CHECKREG r5, 0x6394CB1D; | |
| CHECKREG r6, 0x077F5C15; | |
| CHECKREG r7, 0xDD2E77C7; | |
| CHECKREG r4, 0x4202891B; | |
| CHECKREG r5, 0x6394CB1D; | |
| CHECKREG r6, 0x077F5C15; | |
| CHECKREG r7, 0xDD2E77C7; | |
| imm32 r0, 0x15678911; | |
| imm32 r1, 0x2789ab1d; | |
| imm32 r2, 0x34445515; | |
| imm32 r3, 0x46667717; | |
| imm32 r4, 0x5678891b; | |
| imm32 r5, 0x6789ab1d; | |
| imm32 r6, 0x74445515; | |
| imm32 r7, 0x86667777; | |
| R0.H = R6.L - R0.L (NS); | |
| R1.H = R6.L - R1.H (NS); | |
| R2.H = R6.H - R2.L (NS); | |
| R3.H = R6.H - R3.H (NS); | |
| R4.H = R6.L - R4.L (NS); | |
| R5.H = R6.L - R5.H (NS); | |
| R6.H = R6.H - R6.L (NS); | |
| R7.H = R6.H - R7.H (NS); | |
| CHECKREG r4, 0xCBFA891B; | |
| CHECKREG r5, 0xED8CAB1D; | |
| CHECKREG r6, 0x1F2F5515; | |
| CHECKREG r7, 0x98C97777; | |
| CHECKREG r4, 0xCBFA891B; | |
| CHECKREG r5, 0xED8CAB1D; | |
| CHECKREG r6, 0x1F2F5515; | |
| CHECKREG r7, 0x98C97777; | |
| imm32 r0, 0xd5678911; | |
| imm32 r1, 0x2e89ab1d; | |
| imm32 r2, 0x34445515; | |
| imm32 r3, 0x46667e17; | |
| imm32 r4, 0x56e8891b; | |
| imm32 r5, 0x678eab1d; | |
| imm32 r6, 0x7444e515; | |
| imm32 r7, 0x86667e77; | |
| R0.H = R7.L - R0.L (NS); | |
| R1.H = R7.L - R1.H (NS); | |
| R2.H = R7.H - R2.L (NS); | |
| R3.H = R7.H - R3.H (NS); | |
| R4.H = R7.L - R4.L (NS); | |
| R5.H = R7.L - R5.H (NS); | |
| R6.H = R7.H - R6.L (NS); | |
| R7.H = R7.H - R7.H (NS); | |
| CHECKREG r4, 0xF55C891B; | |
| CHECKREG r5, 0x16E9AB1D; | |
| CHECKREG r6, 0xA151E515; | |
| CHECKREG r7, 0x00007E77; | |
| CHECKREG r4, 0xF55C891B; | |
| CHECKREG r5, 0x16E9AB1D; | |
| CHECKREG r6, 0xA151E515; | |
| CHECKREG r7, 0x00007E77; | |
| imm32 r0, 0xff678911; | |
| imm32 r1, 0x2789ab1d; | |
| imm32 r2, 0x34ff5515; | |
| imm32 r3, 0x4666f717; | |
| imm32 r4, 0x567f891b; | |
| imm32 r5, 0x6789fb1d; | |
| imm32 r6, 0x74445f15; | |
| imm32 r7, 0x866677f7; | |
| R6.H = R2.L - R3.L (S); | |
| R1.H = R4.L - R5.H (S); | |
| R5.H = R7.H - R2.L (S); | |
| R3.H = R0.H - R0.H (S); | |
| R0.H = R3.L - R4.L (S); | |
| R2.H = R5.L - R7.H (S); | |
| R7.H = R6.H - R7.L (S); | |
| R4.H = R1.H - R6.H (S); | |
| CHECKREG r4, 0x8000891B; | |
| CHECKREG r5, 0x8000FB1D; | |
| CHECKREG r6, 0x5DFE5F15; | |
| CHECKREG r7, 0xE60777F7; | |
| CHECKREG r4, 0x8000891B; | |
| CHECKREG r5, 0x8000FB1D; | |
| CHECKREG r6, 0x5DFE5F15; | |
| CHECKREG r7, 0xE60777F7; | |
| imm32 r0, 0x15678911; | |
| imm32 r1, 0x2789ab1d; | |
| imm32 r2, 0x34445515; | |
| imm32 r3, 0x46667717; | |
| imm32 r4, 0x5678891b; | |
| imm32 r5, 0x6789ab1d; | |
| imm32 r6, 0x74445515; | |
| imm32 r7, 0x86667777; | |
| R3.H = R4.L - R0.L (S); | |
| R1.H = R6.L - R3.H (S); | |
| R4.H = R3.H - R2.L (S); | |
| R6.H = R7.H - R1.H (S); | |
| R2.H = R5.L - R4.L (S); | |
| R7.H = R2.L - R7.H (S); | |
| R0.H = R1.H - R6.L (S); | |
| R5.H = R0.H - R5.H (S); | |
| CHECKREG r4, 0xAAF5891B; | |
| CHECKREG r5, 0x986DAB1D; | |
| CHECKREG r6, 0x80005515; | |
| CHECKREG r7, 0x7FFF7777; | |
| CHECKREG r4, 0xAAF5891B; | |
| CHECKREG r5, 0x986DAB1D; | |
| CHECKREG r6, 0x80005515; | |
| CHECKREG r7, 0x7FFF7777; | |
| pass |