| 2016-05-06 Nick Clifton <nickc@redhat.com> |
| |
| * simulator.c (do_FMLA_by_element): New function. |
| (do_vec_op2): Call it. |
| |
| 2016-04-27 Nick Clifton <nickc@redhat.com> |
| |
| * simulator.c: Add TRACE_DECODE statements to all emulation |
| functions. |
| |
| 2016-03-30 Nick Clifton <nickc@redhat.com> |
| |
| * cpustate.c (aarch64_set_reg_s32): New function. |
| (aarch64_set_reg_u32): New function. |
| (aarch64_get_FP_half): Place half precision value into the correct |
| slot of the union. |
| (aarch64_set_FP_half): Likewise. |
| * cpustate.h: Add prototypes for aarch64_set_reg_s32 and |
| aarch64_set_reg_u32. |
| * memory.c (FETCH_FUNC): Cast the read value to the access type |
| before converting it to the return type. Rename to FETCH_FUNC64. |
| (FETCH_FUNC32): New macro. Duplicates FETCH_FUNC64 but for 32-bit |
| accesses. Use for 32-bit memory access functions. |
| * simulator.c (ldrsb_wb): Use sign extension not zero extension. |
| (ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise. |
| (ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise. |
| (ldrsh_scale_ext, ldrsw_abs): Likewise. |
| (ldrh32_abs): Store 32 bit value not 64-bits. |
| (ldrh32_wb, ldrh32_scale_ext): Likewise. |
| (do_vec_MOV_immediate): Fix computation of val. |
| (do_vec_MVNI): Likewise. |
| (DO_VEC_WIDENING_MUL): New macro. |
| (do_vec_mull): Use new macro. |
| (do_vec_mul): Use new macro. |
| (do_vec_MLA): Read values before writing. |
| (do_vec_xtl): Likewise. |
| (do_vec_SSHL): Select correct shift value. |
| (do_vec_USHL): Likewise. |
| (do_scalar_UCVTF): New function. |
| (do_scalar_vec): Call new function. |
| (store_pair_u64): Treat reads of SP as reads of XZR. |
| |
| 2016-03-29 Nick Clifton <nickc@redhat.com> |
| |
| * cpustate.c: Remove space after asterisk in function parameters. |
| * decode.h (greg): Delete unused function. |
| (vreg, shift, extension, scaling, writeback, condcode): Likewise. |
| * simulator.c: Use INSTR macro in more places. |
| (HALT_NYI): Use sim_io_eprintf in place of fprintf. |
| Remove extraneous whitespace. |
| |
| 2016-03-23 Nick Clifton <nickc@redhat.com> |
| |
| * cpustate.c (aarch64_get_FP_half): New function. Read a vector |
| register as a half precision floating point number. |
| (aarch64_set_FP_half): New function. Similar, but for setting |
| a half precision register. |
| (aarch64_get_thread_id): New function. Returns the value of the |
| CPU's TPIDR register. |
| (aarch64_get_FPCR): New function. Returns the value of the CPU's |
| floating point control register. |
| (aarch64_set_FPCR): New function. Set the value of the CPU's FPCR |
| register. |
| * cpustate.h: Add prototypes for new functions. |
| * sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields. |
| * memory.c: Use unaligned core access functions for all memory |
| reads and writes. |
| * simulator.c (HALT_NYI): Generate an error message if tracing |
| will not tell the user why the simulator is halting. |
| (HALT_UNREACHABLE): Delete. Delete (unneeded) uses of the macro. |
| (INSTR): New time-saver macro. |
| (fldrb_abs): New function. Loads an 8-bit value using a scaled |
| offset. |
| (fldrh_abs): New function. Likewise for 16-bit values. |
| (do_vec_SSHL): Allow for negative shift values. |
| (do_vec_USHL): Likewise. |
| (do_vec_SHL): Correct computation of shift amount. |
| (do_vec_SSHR_USHR): Correct decision of signed vs unsigned |
| shifts and computation of shift value. |
| (clz): New function. Counts leading zero bits. |
| (do_vec_CLZ): New function. Implements CLZ (vector). |
| (do_vec_MOV_element): Call do_vec_CLZ. |
| (dexSimpleFPCondCompare): Implement. |
| (do_FCVT_half_to_single): New function. Implements one of the |
| FCVT operations. |
| (do_FCVT_half_to_double): New function. Likewise. |
| (do_FCVT_single_to_half): New function. Likewise. |
| (do_FCVT_double_to_half): New function. Likewise. |
| (dexSimpleFPDataProc1Source): Call new FCVT functions. |
| (do_scalar_SHL): Handle negative shifts. |
| (do_scalar_shift): Handle SSHR. |
| (do_scalar_USHL): New function. |
| (do_double_add): Simplify to just performing a double precision |
| add operation. Move remaining code into... |
| (do_scalar_vec): ... New function. |
| (dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs |
| functions. |
| (system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR |
| registers. |
| (system_set): New function. |
| (do_MSR_immediate): New function. Stub for now. |
| (do_MSR_reg): New function. Likewise. Partially implements MSR |
| instruction. |
| (do_SYS): New function. Stub for now, |
| (dexSystem): Call new functions. |
| |
| 2016-03-18 Nick Clifton <nickc@redhat.com> |
| |
| * cpustate.c: Remove spurious spaces from TRACE strings. |
| Print hex equivalents of floats and doubles. |
| Check element number against array size when accessing vector |
| registers. |
| (GET_VEC_ELEMENT): Fix off by one error checking for an invalid |
| element index. |
| (SET_VEC_ELEMENT): Likewise. |
| (GET_VEC_ELEMENT): And fix thinko using macro arguments. |
| |
| * memory.c: Trace memory reads when --trace-memory is enabled. |
| Remove float and double load and store functions. |
| * memory.h (aarch64_get_mem_float): Delete prototype. |
| (aarch64_get_mem_double): Likewise. |
| (aarch64_set_mem_float): Likewise. |
| (aarch64_set_mem_double): Likewise. |
| * simulator (IS_SET): Always return either 0 or 1. |
| (IS_CLEAR): Likewise. |
| (fldrs_pcrel): Load and store floats using 32-bit memory accesses |
| and doubles using 64-bit memory accesses. |
| (fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise. |
| (fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise. |
| (fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise. |
| (fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise. |
| (store_pair_double, load_pair_float, load_pair_double): Likewise. |
| (do_vec_MUL_by_element): New function. |
| (do_vec_op2): Call do_vec_MUL_by_element. |
| (do_scalar_NEG): New function. |
| (do_double_add): Call do_scalar_NEG. |
| |
| 2016-03-03 Nick Clifton <nickc@redhat.com> |
| |
| * simulator.c (set_flags_for_sub32): Correct type of signbit. |
| (CondCompare): Swap interpretation of bit 30. |
| (DO_ADDP): Delete macro. |
| (do_vec_ADDP): Copy source registers before starting to update |
| destination register. |
| (do_vec_FADDP): Likewise. |
| (do_vec_load_store): Fix computation of sizeof_operation. |
| (rbit64): Fix type of constant. |
| (aarch64_step): When displaying insn value, display all 32 bits. |
| |
| 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
| |
| * config.in, configure: Regenerate. |
| |
| 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
| |
| * configure: Regenerate. |
| |
| 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
| |
| * configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call. |
| * configure: Regenerate. |
| |
| 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
| |
| * configure: Regenerate. |
| |
| 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
| |
| * configure: Regenerate. |
| |
| 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
| |
| * configure.ac (SIM_AC_OPTION_INLINE): Delete call. |
| * configure: Regenerate. |
| |
| 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
| |
| * configure: Regenerate. |
| |
| 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
| |
| * configure: Regenerate. |
| |
| 2016-01-09 Mike Frysinger <vapier@gentoo.org> |
| |
| * config.in, configure: Regenerate. |
| |
| 2016-01-06 Mike Frysinger <vapier@gentoo.org> |
| |
| * interp.c (sim_create_inferior): Mark argv and env const. |
| (sim_open): Mark argv const. |
| |
| 2016-01-05 Mike Frysinger <vapier@gentoo.org> |
| |
| * interp.c: Delete dis-asm.h include. |
| (info, opbuf, op_printf, aarch64_print_insn, sim_dis_read): Delete. |
| (sim_create_inferior): Delete disassemble init logic. |
| (OPTION_DISAS, aarch64_option_handler, aarch64_options): Delete. |
| (sim_open): Delete sim_add_option_table call. |
| * memory.c (mem_error): Delete disas check. |
| * simulator.c: Delete dis-asm.h include. |
| (disas): Delete. |
| (HALT_UNALLOC): Replace disassembly logic with TRACE_DISASM. |
| (HALT_NYI): Likewise. |
| (handle_halt): Delete disas call. |
| (aarch64_step): Replace disas logic with TRACE_DISASM. |
| * simulator.h: Delete dis-asm.h include. |
| (aarch64_print_insn): Delete. |
| |
| 2016-01-04 Mike Frysinger <vapier@gentoo.org> |
| |
| * simulator.c (MAX, MIN): Delete. |
| (do_vec_maxv): Change MAX to max and MIN to min. |
| (do_vec_fminmaxV): Likewise. |
| |
| 2016-01-04 Tristan Gingold <gingold@adacore.com> |
| |
| * simulator.c: Remove syscall.h include. |
| |
| 2016-01-04 Mike Frysinger <vapier@gentoo.org> |
| |
| * configure: Regenerate. |
| |
| 2016-01-03 Mike Frysinger <vapier@gentoo.org> |
| |
| * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete. |
| * configure: Regenerate. |
| |
| 2016-01-02 Mike Frysinger <vapier@gentoo.org> |
| |
| * configure: Regenerate. |
| |
| 2015-12-27 Mike Frysinger <vapier@gentoo.org> |
| |
| * interp.c (sim_dis_read): Change private_data to application_data. |
| (sim_create_inferior): Likewise. |
| |
| 2015-12-27 Mike Frysinger <vapier@gentoo.org> |
| |
| * Makefile.in (SIM_OBJS): Delete sim-hload.o. |
| |
| 2015-12-26 Mike Frysinger <vapier@gentoo.org> |
| |
| * config.in, configure: Regenerate. |
| |
| 2015-12-26 Mike Frysinger <vapier@gentoo.org> |
| |
| * interp.c (sim_create_inferior): Update comment and argv check. |
| |
| 2015-12-14 Nick Clifton <nickc@redhat.com> |
| |
| * simulator.c (system_get): New function. Provides read |
| access to the dczid system register. |
| (do_mrs): New function - implements the MRS instruction. |
| (dexSystem): Call do_mrs for the MRS instruction. Halt on |
| unimplemented system instructions. |
| |
| 2015-11-24 Nick Clifton <nickc@redhat.com> |
| |
| * configure.ac: New configure template. |
| * aclocal.m4: Generate. |
| * config.in: Generate. |
| * configure: Generate. |
| * cpustate.c: New file - functions for accessing AArch64 registers. |
| * cpustate.h: New header. |
| * decode.h: New header. |
| * interp.c: New file - interface between GDB and simulator. |
| * Makefile.in: New makefile template. |
| * memory.c: New file - functions for simulating aarch64 memory |
| accesses. |
| * memory.h: New header. |
| * sim-main.h: New header. |
| * simulator.c: New file - aarch64 simulator functions. |
| * simulator.h: New header. |
