lr r5, [status] | |
lr r5, [semaphore] | |
lr r5, [lp_start] | |
lr r5, [lp_end] | |
lr r5, [identity] | |
lr r5, [debug] | |
lr r5, [pc] | |
lr r5, [adcr] | |
lr r5, [apcr] | |
lr r5, [acr] | |
lr r5, [status32] | |
lr r5, [status32_l1] | |
lr r5, [status32_l2] | |
lr r5, [bpu_flush] | |
lr r5, [ivic] | |
lr r5, [ic_ivic] | |
lr r5, [che_mode] | |
lr r5, [ic_ctrl] | |
lr r5, [mulhi] | |
lr r5, [lockline] | |
lr r5, [ic_lil] | |
lr r5, [dmc_code_ram] | |
lr r5, [tag_addr_mask] | |
lr r5, [tag_data_mask] | |
lr r5, [line_length_mask] | |
lr r5, [aux_ldst_ram] | |
lr r5, [aux_dccm] | |
lr r5, [unlockline] | |
lr r5, [ic_ivil] | |
lr r5, [ic_ram_address] | |
lr r5, [ic_tag] | |
lr r5, [ic_wp] | |
lr r5, [ic_data] | |
lr r5, [sram_seq] | |
lr r5, [count0] | |
lr r5, [control0] | |
lr r5, [limit0] | |
lr r5, [pcport] | |
lr r5, [int_vector_base] | |
lr r5, [aux_vbfdw_mode] | |
lr r5, [jli_base] | |
lr r5, [aux_vbfdw_bm0] | |
lr r5, [aux_vbfdw_bm1] | |
lr r5, [aux_vbfdw_accu] | |
lr r5, [aux_vbfdw_ofst] | |
lr r5, [aux_vbfdw_intstat] | |
lr r5, [aux_xmac0_24] | |
lr r5, [aux_xmac1_24] | |
lr r5, [aux_xmac2_24] | |
lr r5, [aux_fbf_store_16] | |
lr r5, [ax0] | |
lr r5, [ax1] | |
lr r5, [aux_crc_poly] | |
lr r5, [aux_crc_mode] | |
lr r5, [mx0] | |
lr r5, [mx1] | |
lr r5, [my0] | |
lr r5, [my1] | |
lr r5, [xyconfig] | |
lr r5, [scratch_a] | |
lr r5, [burstsys] | |
lr r5, [tsch] | |
lr r5, [burstxym] | |
lr r5, [burstsz] | |
lr r5, [burstval] | |
lr r5, [xtp_newval] | |
lr r5, [aux_macmode] | |
lr r5, [lsp_newval] | |
lr r5, [aux_irq_lv12] | |
lr r5, [aux_xmac0] | |
lr r5, [aux_xmac1] | |
lr r5, [aux_xmac2] | |
lr r5, [dc_ivdc] | |
lr r5, [dc_ctrl] | |
lr r5, [dc_ldl] | |
lr r5, [dc_ivdl] | |
lr r5, [dc_flsh] | |
lr r5, [dc_fldl] | |
lr r5, [hexdata] | |
lr r5, [hexctrl] | |
lr r5, [led] | |
lr r5, [dilstat] | |
lr r5, [swstat] | |
lr r5, [dc_ram_addr] | |
lr r5, [dc_tag] | |
lr r5, [dc_wp] | |
lr r5, [dc_data] | |
lr r5, [dccm_base_build] | |
lr r5, [crc_build] | |
lr r5, [bta_link_build] | |
lr r5, [vbfdw_build] | |
lr r5, [ea_build] | |
lr r5, [dataspace] | |
lr r5, [memsubsys] | |
lr r5, [vecbase_ac_build] | |
lr r5, [p_base_addr] | |
lr r5, [data_uncached_build] | |
lr r5, [fp_build] | |
lr r5, [dpfp_build] | |
lr r5, [mpu_build] | |
lr r5, [rf_build] | |
lr r5, [mmu_build] | |
lr r5, [aa2_build] | |
lr r5, [vecbase_build] | |
lr r5, [d_cache_build] | |
lr r5, [madi_build] | |
lr r5, [dccm_build] | |
lr r5, [timer_build] | |
lr r5, [ap_build] | |
lr r5, [i_cache_build] | |
lr r5, [iccm_build] | |
lr r5, [dspram_build] | |
lr r5, [mac_build] | |
lr r5, [multiply_build] | |
lr r5, [swap_build] | |
lr r5, [norm_build] | |
lr r5, [minmax_build] | |
lr r5, [barrel_build] | |
lr r5, [ax0] | |
lr r5, [ax1] | |
lr r5, [ax2] | |
lr r5, [ax3] | |
lr r5, [ay0] | |
lr r5, [ay1] | |
lr r5, [ay2] | |
lr r5, [ay3] | |
lr r5, [mx00] | |
lr r5, [mx01] | |
lr r5, [mx10] | |
lr r5, [mx11] | |
lr r5, [mx20] | |
lr r5, [mx21] | |
lr r5, [mx30] | |
lr r5, [mx31] | |
lr r5, [my00] | |
lr r5, [my01] | |
lr r5, [my10] | |
lr r5, [my11] | |
lr r5, [my20] | |
lr r5, [my21] | |
lr r5, [my30] | |
lr r5, [my31] | |
lr r5, [xyconfig] | |
lr r5, [burstsys] | |
lr r5, [burstxym] | |
lr r5, [burstsz] | |
lr r5, [burstval] | |
lr r5, [xylsbasex] | |
lr r5, [xylsbasey] | |
lr r5, [aux_xmaclw_h] | |
lr r5, [aux_xmaclw_l] | |
lr r5, [se_ctrl] | |
lr r5, [se_stat] | |
lr r5, [se_err] | |
lr r5, [se_eadr] | |
lr r5, [se_spc] | |
lr r5, [sdm_base] | |
lr r5, [scm_base] | |
lr r5, [se_dbg_ctrl] | |
lr r5, [se_dbg_data0] | |
lr r5, [se_dbg_data1] | |
lr r5, [se_dbg_data2] | |
lr r5, [se_dbg_data3] | |
lr r5, [se_watch] | |
lr r5, [bpu_build] | |
lr r5, [arc600_build_config] | |
lr r5, [isa_config] | |
lr r5, [hwp_build] | |
lr r5, [pct_build] | |
lr r5, [cc_build] | |
lr r5, [pm_bcr] | |
lr r5, [scq_switch_build] | |
lr r5, [vraptor_build] | |
lr r5, [dma_config] | |
lr r5, [simd_config] | |
lr r5, [vlc_build] | |
lr r5, [simd_dma_build] | |
lr r5, [ifetch_queue_build] | |
lr r5, [smart_build] | |
lr r5, [count1] | |
lr r5, [control1] | |
lr r5, [limit1] | |
lr r5, [timer_xx] | |
lr r5, [arcangel_periph_xx] | |
lr r5, [periph_xx] | |
lr r5, [aux_irq_lev] | |
lr r5, [aux_irq_hint] | |
lr r5, [aux_inter_core_interrupt] | |
lr r5, [aes_aux_0] | |
lr r5, [aes_aux_1] | |
lr r5, [aes_aux_2] | |
lr r5, [aes_crypt_mode] | |
lr r5, [aes_auxs] | |
lr r5, [aes_auxi] | |
lr r5, [aes_aux_3] | |
lr r5, [aes_aux_4] | |
lr r5, [arith_ctl_aux] | |
lr r5, [des_aux] | |
lr r5, [ap_amv0] | |
lr r5, [ap_amm0] | |
lr r5, [ap_ac0] | |
lr r5, [ap_amv1] | |
lr r5, [ap_amm1] | |
lr r5, [ap_ac1] | |
lr r5, [ap_amv2] | |
lr r5, [ap_amm2] | |
lr r5, [ap_ac2] | |
lr r5, [ap_amv3] | |
lr r5, [ap_amm3] | |
lr r5, [ap_ac3] | |
lr r5, [ap_amv4] | |
lr r5, [ap_amm4] | |
lr r5, [ap_ac4] | |
lr r5, [ap_amv5] | |
lr r5, [ap_amm5] | |
lr r5, [ap_ac5] | |
lr r5, [ap_amv6] | |
lr r5, [ap_amm6] | |
lr r5, [ap_ac6] | |
lr r5, [ap_amv7] | |
lr r5, [ap_amm7] | |
lr r5, [ap_ac7] | |
lr r5, [pct_control] | |
lr r5, [pct_bank] | |
lr r5, [fp_status] | |
lr r5, [aux_dpfp1l] | |
lr r5, [d1l] | |
lr r5, [aux_dpfp1h] | |
lr r5, [d1h] | |
lr r5, [d1l] | |
lr r5, [aux_dpfp2l] | |
lr r5, [d2l] | |
lr r5, [d1h] | |
lr r5, [aux_dpfp2h] | |
lr r5, [d2h] | |
lr r5, [d2l] | |
lr r5, [dpfp_status] | |
lr r5, [d2h] | |
lr r5, [rtt] | |
lr r5, [eret] | |
lr r5, [erbta] | |
lr r5, [erstatus] | |
lr r5, [ecr] | |
lr r5, [efa] | |
lr r5, [tlbpd0] | |
lr r5, [tlbpd1] | |
lr r5, [tlbindex] | |
lr r5, [tlbcommand] | |
lr r5, [pid] | |
lr r5, [mpuen] | |
lr r5, [icause1] | |
lr r5, [icause2] | |
lr r5, [aux_ienable] | |
lr r5, [aux_itrigger] | |
lr r5, [xpu] | |
lr r5, [bta] | |
lr r5, [bta_l1] | |
lr r5, [bta_l2] | |
lr r5, [aux_irq_pulse_cancel] | |
lr r5, [aux_irq_pending] | |
lr r5, [scratch_data0] | |
lr r5, [mpuic] | |
lr r5, [mpufa] | |
lr r5, [mpurdb0] | |
lr r5, [mpurdp0] | |
lr r5, [mpurdb1] | |
lr r5, [mpurdp1] | |
lr r5, [mpurdb2] | |
lr r5, [mpurdp2] | |
lr r5, [mpurdb3] | |
lr r5, [mpurdp3] | |
lr r5, [mpurdb4] | |
lr r5, [mpurdp4] | |
lr r5, [mpurdb5] | |
lr r5, [mpurdp5] | |
lr r5, [mpurdb6] | |
lr r5, [mpurdp6] | |
lr r5, [mpurdb7] | |
lr r5, [mpurdp7] | |
lr r5, [mpurdb8] | |
lr r5, [mpurdp8] | |
lr r5, [mpurdb9] | |
lr r5, [mpurdp9] | |
lr r5, [mpurdb10] | |
lr r5, [mpurdp10] | |
lr r5, [mpurdb11] | |
lr r5, [mpurdp11] | |
lr r5, [mpurdb12] | |
lr r5, [mpurdp12] | |
lr r5, [mpurdb13] | |
lr r5, [mpurdp13] | |
lr r5, [mpurdb14] | |
lr r5, [mpurdp14] | |
lr r5, [mpurdb15] | |
lr r5, [mpurdp15] | |
lr r5, [eia_flags] | |
lr r5, [pm_status] | |
lr r5, [wake] | |
lr r5, [dvfs_performance] | |
lr r5, [pwr_ctrl] | |
lr r5, [aux_vlc_buf_idx] | |
lr r5, [aux_vlc_read_buf] | |
lr r5, [aux_vlc_valid_bits] | |
lr r5, [aux_vlc_buf_in] | |
lr r5, [aux_vlc_buf_free] | |
lr r5, [aux_vlc_ibuf_status] | |
lr r5, [aux_vlc_setup] | |
lr r5, [aux_vlc_bits] | |
lr r5, [aux_vlc_table] | |
lr r5, [aux_vlc_get_symbol] | |
lr r5, [aux_vlc_read_symbol] | |
lr r5, [aux_ucavlc_setup] | |
lr r5, [aux_ucavlc_state] | |
lr r5, [aux_cavlc_zero_left] | |
lr r5, [aux_uvlc_i_state] | |
lr r5, [aux_vlc_dma_ptr] | |
lr r5, [aux_vlc_dma_end] | |
lr r5, [aux_vlc_dma_esc] | |
lr r5, [aux_vlc_dma_ctrl] | |
lr r5, [aux_vlc_get_0bit] | |
lr r5, [aux_vlc_get_1bit] | |
lr r5, [aux_vlc_get_2bit] | |
lr r5, [aux_vlc_get_3bit] | |
lr r5, [aux_vlc_get_4bit] | |
lr r5, [aux_vlc_get_5bit] | |
lr r5, [aux_vlc_get_6bit] | |
lr r5, [aux_vlc_get_7bit] | |
lr r5, [aux_vlc_get_8bit] | |
lr r5, [aux_vlc_get_9bit] | |
lr r5, [aux_vlc_get_10bit] | |
lr r5, [aux_vlc_get_11bit] | |
lr r5, [aux_vlc_get_12bit] | |
lr r5, [aux_vlc_get_13bit] | |
lr r5, [aux_vlc_get_14bit] | |
lr r5, [aux_vlc_get_15bit] | |
lr r5, [aux_vlc_get_16bit] | |
lr r5, [aux_vlc_get_17bit] | |
lr r5, [aux_vlc_get_18bit] | |
lr r5, [aux_vlc_get_19bit] | |
lr r5, [aux_vlc_get_20bit] | |
lr r5, [aux_vlc_get_21bit] | |
lr r5, [aux_vlc_get_22bit] | |
lr r5, [aux_vlc_get_23bit] | |
lr r5, [aux_vlc_get_24bit] | |
lr r5, [aux_vlc_get_25bit] | |
lr r5, [aux_vlc_get_26bit] | |
lr r5, [aux_vlc_get_27bit] | |
lr r5, [aux_vlc_get_28bit] | |
lr r5, [aux_vlc_get_29bit] | |
lr r5, [aux_vlc_get_30bit] | |
lr r5, [aux_vlc_get_31bit] | |
lr r5, [aux_cabac_ctrl] | |
lr r5, [aux_cabac_ctx_state] | |
lr r5, [aux_cabac_cod_param] | |
lr r5, [aux_cabac_misc0] | |
lr r5, [aux_cabac_misc1] | |
lr r5, [aux_cabac_misc2] | |
lr r5, [arc600_build_config] | |
lr r5, [smart_control] | |
lr r5, [smart_data_0] | |
lr r5, [smart_data_1] | |
lr r5, [smart_data_2] | |
lr r5, [smart_data_3] |