| /* |
| * SiliconBackplane System Memory core |
| * |
| * Copyright 1999-2016, Broadcom Corporation |
| * All rights reserved, |
| * |
| * Redistribution and use in source and binary forms, with or without modification, |
| * are permitted provided that the following conditions are met: |
| * 1. Redistributions of source code must retain the above copyright notice, |
| * this list of conditions and the following disclaimer. |
| * 2. Redistributions in binary form must reproduce the above copyright notice, |
| * this list of conditions and the following disclaimer in the documentation |
| * and/or other materials provided with the distribution. |
| * |
| * This software is provided by the copyright holder "as is" and any express or |
| * implied warranties, including, but not limited to, the implied warranties of |
| * merchantability and fitness for a particular purpose are disclaimed. In no event |
| * shall copyright holder be liable for any direct, indirect, incidental, special, |
| * exemplary, or consequential damages (including, but not limited to, procurement |
| * of substitute goods or services; loss of use, data, or profits; or business |
| * interruption) however caused and on any theory of liability, whether in |
| * contract, strict liability, or tort (including negligence or otherwise) arising |
| * in any way out of the use of this software, even if advised of the possibility |
| * of such damage |
| * |
| * |
| * <<Broadcom-WL-IPTag/Open:>> |
| * |
| * $Id: sbsysmem.h 514727 2014-11-12 03:02:48Z $ |
| */ |
| |
| #ifndef _SBSYSMEM_H |
| #define _SBSYSMEM_H |
| |
| #ifndef _LANGUAGE_ASSEMBLY |
| |
| /* cpp contortions to concatenate w/arg prescan */ |
| #ifndef PAD |
| #define _PADLINE(line) pad ## line |
| #define _XSTR(line) _PADLINE(line) |
| #define PAD _XSTR(__LINE__) |
| #endif /* PAD */ |
| |
| /* sysmem core registers */ |
| typedef volatile struct sysmemregs { |
| uint32 coreinfo; |
| uint32 bwalloc; |
| uint32 extracoreinfo; |
| uint32 biststat; |
| uint32 bankidx; |
| uint32 standbyctrl; |
| |
| uint32 errlogstatus; |
| uint32 errlogaddr; |
| |
| uint32 cambankidx; |
| uint32 cambankstandbyctrl; |
| uint32 cambankpatchctrl; |
| uint32 cambankpatchtblbaseaddr; |
| uint32 cambankcmdreg; |
| uint32 cambankdatareg; |
| uint32 cambankmaskreg; |
| uint32 PAD[1]; |
| uint32 bankinfo; |
| uint32 PAD[15]; |
| uint32 extmemconfig; |
| uint32 extmemparitycsr; |
| uint32 extmemparityerrdata; |
| uint32 extmemparityerrcnt; |
| uint32 extmemwrctrlandsize; |
| uint32 PAD[84]; |
| uint32 workaround; |
| uint32 pwrctl; |
| uint32 PAD[133]; |
| uint32 sr_control; |
| uint32 sr_status; |
| uint32 sr_address; |
| uint32 sr_data; |
| } sysmemregs_t; |
| |
| #endif /* _LANGUAGE_ASSEMBLY */ |
| |
| /* Register offsets */ |
| #define SR_COREINFO 0x00 |
| #define SR_BWALLOC 0x04 |
| #define SR_BISTSTAT 0x0c |
| #define SR_BANKINDEX 0x10 |
| #define SR_BANKSTBYCTL 0x14 |
| #define SR_PWRCTL 0x1e8 |
| |
| /* Coreinfo register */ |
| #define SRCI_PT_MASK 0x00070000 /* port type[18:16] */ |
| #define SRCI_PT_SHIFT 16 |
| /* port types : SRCI_PT_<processorPT>_<backplanePT> */ |
| #define SRCI_PT_OCP_OCP 0 |
| #define SRCI_PT_AXI_OCP 1 |
| #define SRCI_PT_ARM7AHB_OCP 2 |
| #define SRCI_PT_CM3AHB_OCP 3 |
| #define SRCI_PT_AXI_AXI 4 |
| #define SRCI_PT_AHB_AXI 5 |
| |
| #define SRCI_LSS_MASK 0x00f00000 |
| #define SRCI_LSS_SHIFT 20 |
| #define SRCI_LRS_MASK 0x0f000000 |
| #define SRCI_LRS_SHIFT 24 |
| |
| /* In corerev 0, the memory size is 2 to the power of the |
| * base plus 16 plus to the contents of the memsize field plus 1. |
| */ |
| #define SRCI_MS0_MASK 0xf |
| #define SR_MS0_BASE 16 |
| |
| /* |
| * In corerev 1 the bank size is 2 ^ the bank size field plus 14, |
| * the memory size is number of banks times bank size. |
| * The same applies to rom size. |
| */ |
| #define SRCI_ROMNB_MASK 0xf000 |
| #define SRCI_ROMNB_SHIFT 12 |
| #define SRCI_ROMBSZ_MASK 0xf00 |
| #define SRCI_ROMBSZ_SHIFT 8 |
| #define SRCI_SRNB_MASK 0xf0 |
| #define SRCI_SRNB_SHIFT 4 |
| #define SRCI_SRBSZ_MASK 0xf |
| #define SRCI_SRBSZ_SHIFT 0 |
| |
| #define SR_BSZ_BASE 14 |
| |
| /* Standby control register */ |
| #define SRSC_SBYOVR_MASK 0x80000000 |
| #define SRSC_SBYOVR_SHIFT 31 |
| #define SRSC_SBYOVRVAL_MASK 0x60000000 |
| #define SRSC_SBYOVRVAL_SHIFT 29 |
| #define SRSC_SBYEN_MASK 0x01000000 |
| #define SRSC_SBYEN_SHIFT 24 |
| |
| /* Power control register */ |
| #define SRPC_PMU_STBYDIS_MASK 0x00000010 |
| #define SRPC_PMU_STBYDIS_SHIFT 4 |
| #define SRPC_STBYOVRVAL_MASK 0x00000008 |
| #define SRPC_STBYOVRVAL_SHIFT 3 |
| #define SRPC_STBYOVR_MASK 0x00000007 |
| #define SRPC_STBYOVR_SHIFT 0 |
| |
| /* Extra core capability register */ |
| #define SRECC_NUM_BANKS_MASK 0x000000F0 |
| #define SRECC_NUM_BANKS_SHIFT 4 |
| #define SRECC_BANKSIZE_MASK 0x0000000F |
| #define SRECC_BANKSIZE_SHIFT 0 |
| |
| #define SRECC_BANKSIZE(value) (1 << (value)) |
| |
| /* CAM bank patch control */ |
| #define SRCBPC_PATCHENABLE 0x80000000 |
| |
| #define SRP_ADDRESS 0x0001FFFC |
| #define SRP_VALID 0x8000 |
| |
| /* CAM bank command reg */ |
| #define SRCMD_WRITE 0x00020000 |
| #define SRCMD_READ 0x00010000 |
| #define SRCMD_DONE 0x80000000 |
| |
| #define SRCMD_DONE_DLY 1000 |
| |
| /* bankidx and bankinfo reg defines */ |
| #define SYSMEM_BANKINFO_SZMASK 0x7f |
| #define SYSMEM_BANKIDX_ROM_MASK 0x100 |
| |
| #define SYSMEM_BANKIDX_MEMTYPE_SHIFT 8 |
| /* sysmem bankinfo memtype */ |
| #define SYSMEM_MEMTYPE_RAM 0 |
| #define SYSMEM_MEMTYPE_R0M 1 |
| #define SYSMEM_MEMTYPE_DEVRAM 2 |
| |
| #define SYSMEM_BANKINFO_REG 0x40 |
| #define SYSMEM_BANKIDX_REG 0x10 |
| #define SYSMEM_BANKINFO_STDBY_MASK 0x400 |
| #define SYSMEM_BANKINFO_STDBY_TIMER 0x800 |
| |
| #define SYSMEM_BANKINFO_DEVRAMSEL_SHIFT 13 |
| #define SYSMEM_BANKINFO_DEVRAMSEL_MASK 0x2000 |
| #define SYSMEM_BANKINFO_DEVRAMPRO_SHIFT 14 |
| #define SYSMEM_BANKINFO_DEVRAMPRO_MASK 0x4000 |
| #define SYSMEM_BANKINFO_SLPSUPP_SHIFT 15 |
| #define SYSMEM_BANKINFO_SLPSUPP_MASK 0x8000 |
| #define SYSMEM_BANKINFO_RETNTRAM_SHIFT 16 |
| #define SYSMEM_BANKINFO_RETNTRAM_MASK 0x00010000 |
| #define SYSMEM_BANKINFO_PDASZ_SHIFT 17 |
| #define SYSMEM_BANKINFO_PDASZ_MASK 0x003E0000 |
| #define SYSMEM_BANKINFO_DEVRAMREMAP_SHIFT 24 |
| #define SYSMEM_BANKINFO_DEVRAMREMAP_MASK 0x01000000 |
| |
| /* extracoreinfo register */ |
| #define SYSMEM_DEVRAMBANK_MASK 0xF000 |
| #define SYSMEM_DEVRAMBANK_SHIFT 12 |
| |
| /* bank info to calculate bank size */ |
| #define SYSMEM_BANKINFO_SZBASE 8192 |
| #define SYSMEM_BANKSIZE_SHIFT 13 /* SYSMEM_BANKINFO_SZBASE */ |
| |
| #endif /* _SBSYSMEM_H */ |